105 lines · c
1/* SPDX-License-Identifier: GPL-2.0 */2/* Copyright (c) 2018, Intel Corporation. */3 4#ifndef _ICE_CONTROLQ_H_5#define _ICE_CONTROLQ_H_6 7#include "ice_adminq_cmd.h"8 9/* Maximum buffer lengths for all control queue types */10#define ICE_AQ_MAX_BUF_LEN 409611#define ICE_MBXQ_MAX_BUF_LEN 409612#define ICE_SBQ_MAX_BUF_LEN 51213 14#define ICE_CTL_Q_DESC(R, i) \15 (&(((struct ice_aq_desc *)((R).desc_buf.va))[i]))16 17#define ICE_CTL_Q_DESC_UNUSED(R) \18 ((u16)((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \19 (R)->next_to_clean - (R)->next_to_use - 1))20 21/* Defines that help manage the driver vs FW API checks.22 * Take a look at ice_aq_ver_check in ice_controlq.c for actual usage.23 */24#define EXP_FW_API_VER_MAJOR_E810 0x0125#define EXP_FW_API_VER_MINOR_E810 0x0526 27#define EXP_FW_API_VER_MAJOR_E830 0x0128#define EXP_FW_API_VER_MINOR_E830 0x0729 30#define EXP_FW_API_VER_MAJOR_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? \31 EXP_FW_API_VER_MAJOR_E830 : \32 EXP_FW_API_VER_MAJOR_E810)33#define EXP_FW_API_VER_MINOR_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? \34 EXP_FW_API_VER_MINOR_E830 : \35 EXP_FW_API_VER_MINOR_E810)36 37/* Different control queue types: These are mainly for SW consumption. */38enum ice_ctl_q {39 ICE_CTL_Q_UNKNOWN = 0,40 ICE_CTL_Q_ADMIN,41 ICE_CTL_Q_MAILBOX,42 ICE_CTL_Q_SB,43};44 45/* Control Queue timeout settings - max delay 1s */46#define ICE_CTL_Q_SQ_CMD_TIMEOUT USEC_PER_SEC47#define ICE_CTL_Q_ADMIN_INIT_TIMEOUT 10 /* Count 10 times */48#define ICE_CTL_Q_ADMIN_INIT_MSEC 100 /* Check every 100msec */49 50struct ice_ctl_q_ring {51 void *dma_head; /* Virtual address to DMA head */52 struct ice_dma_mem desc_buf; /* descriptor ring memory */53 54 union {55 struct ice_dma_mem *sq_bi;56 struct ice_dma_mem *rq_bi;57 } r;58 59 u16 count; /* Number of descriptors */60 61 /* used for interrupt processing */62 u16 next_to_use;63 u16 next_to_clean;64 65 /* used for queue tracking */66 u32 head;67 u32 tail;68 u32 len;69 u32 bah;70 u32 bal;71 u32 len_mask;72 u32 len_ena_mask;73 u32 len_crit_mask;74 u32 head_mask;75};76 77/* sq transaction details */78struct ice_sq_cd {79 struct ice_aq_desc *wb_desc;80};81 82/* rq event information */83struct ice_rq_event_info {84 struct ice_aq_desc desc;85 u16 msg_len;86 u16 buf_len;87 u8 *msg_buf;88};89 90/* Control Queue information */91struct ice_ctl_q_info {92 enum ice_ctl_q qtype;93 struct ice_ctl_q_ring rq; /* receive queue */94 struct ice_ctl_q_ring sq; /* send queue */95 u16 num_rq_entries; /* receive queue depth */96 u16 num_sq_entries; /* send queue depth */97 u16 rq_buf_size; /* receive queue buffer size */98 u16 sq_buf_size; /* send queue buffer size */99 enum ice_aq_err sq_last_status; /* last status on send queue */100 struct mutex sq_lock; /* Send queue lock */101 struct mutex rq_lock; /* Receive queue lock */102};103 104#endif /* _ICE_CONTROLQ_H_ */105