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1/* SPDX-License-Identifier: GPL-2.0 */2/* Copyright (C) 2022, Intel Corporation. */3 4#ifndef _ICE_DPLL_H_5#define _ICE_DPLL_H_6 7#include "ice.h"8 9#define ICE_DPLL_RCLK_NUM_MAX 410 11/** ice_dpll_pin - store info about pins12 * @pin: dpll pin structure13 * @pf: pointer to pf, which has registered the dpll_pin14 * @idx: ice pin private idx15 * @num_parents: hols number of parent pins16 * @parent_idx: hold indexes of parent pins17 * @flags: pin flags returned from HW18 * @state: state of a pin19 * @prop: pin properties20 * @freq: current frequency of a pin21 * @phase_adjust: current phase adjust value22 */23struct ice_dpll_pin {24 struct dpll_pin *pin;25 struct ice_pf *pf;26 u8 idx;27 u8 num_parents;28 u8 parent_idx[ICE_DPLL_RCLK_NUM_MAX];29 u8 flags[ICE_DPLL_RCLK_NUM_MAX];30 u8 state[ICE_DPLL_RCLK_NUM_MAX];31 struct dpll_pin_properties prop;32 u32 freq;33 s32 phase_adjust;34 u8 status;35};36 37/** ice_dpll - store info required for DPLL control38 * @dpll: pointer to dpll dev39 * @pf: pointer to pf, which has registered the dpll_device40 * @dpll_idx: index of dpll on the NIC41 * @input_idx: currently selected input index42 * @prev_input_idx: previously selected input index43 * @ref_state: state of dpll reference signals44 * @eec_mode: eec_mode dpll is configured for45 * @phase_offset: phase offset of active pin vs dpll signal46 * @prev_phase_offset: previous phase offset of active pin vs dpll signal47 * @input_prio: priorities of each input48 * @dpll_state: current dpll sync state49 * @prev_dpll_state: last dpll sync state50 * @active_input: pointer to active input pin51 * @prev_input: pointer to previous active input pin52 */53struct ice_dpll {54 struct dpll_device *dpll;55 struct ice_pf *pf;56 u8 dpll_idx;57 u8 input_idx;58 u8 prev_input_idx;59 u8 ref_state;60 u8 eec_mode;61 s64 phase_offset;62 s64 prev_phase_offset;63 u8 *input_prio;64 enum dpll_lock_status dpll_state;65 enum dpll_lock_status prev_dpll_state;66 enum dpll_mode mode;67 struct dpll_pin *active_input;68 struct dpll_pin *prev_input;69};70 71/** ice_dplls - store info required for CCU (clock controlling unit)72 * @kworker: periodic worker73 * @work: periodic work74 * @lock: locks access to configuration of a dpll75 * @eec: pointer to EEC dpll dev76 * @pps: pointer to PPS dpll dev77 * @inputs: input pins pointer78 * @outputs: output pins pointer79 * @rclk: recovered pins pointer80 * @num_inputs: number of input pins available on dpll81 * @num_outputs: number of output pins available on dpll82 * @cgu_state_acq_err_num: number of errors returned during periodic work83 * @base_rclk_idx: idx of first pin used for clock revocery pins84 * @clock_id: clock_id of dplls85 * @input_phase_adj_max: max phase adjust value for an input pins86 * @output_phase_adj_max: max phase adjust value for an output pins87 */88struct ice_dplls {89 struct kthread_worker *kworker;90 struct kthread_delayed_work work;91 struct mutex lock;92 struct ice_dpll eec;93 struct ice_dpll pps;94 struct ice_dpll_pin *inputs;95 struct ice_dpll_pin *outputs;96 struct ice_dpll_pin rclk;97 u8 num_inputs;98 u8 num_outputs;99 int cgu_state_acq_err_num;100 u8 base_rclk_idx;101 u64 clock_id;102 s32 input_phase_adj_max;103 s32 output_phase_adj_max;104};105 106#if IS_ENABLED(CONFIG_PTP_1588_CLOCK)107void ice_dpll_init(struct ice_pf *pf);108void ice_dpll_deinit(struct ice_pf *pf);109#else110static inline void ice_dpll_init(struct ice_pf *pf) { }111static inline void ice_dpll_deinit(struct ice_pf *pf) { }112#endif113 114#endif115