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1/* SPDX-License-Identifier: GPL-2.0 */2/* Copyright (C) 2021, Intel Corporation. */3 4#ifndef _ICE_PTP_HW_H_5#define _ICE_PTP_HW_H_6#include <linux/dpll.h>7 8enum ice_ptp_tmr_cmd {9 ICE_PTP_INIT_TIME,10 ICE_PTP_INIT_INCVAL,11 ICE_PTP_ADJ_TIME,12 ICE_PTP_ADJ_TIME_AT_TIME,13 ICE_PTP_READ_TIME,14 ICE_PTP_NOP,15};16 17enum ice_ptp_serdes {18 ICE_PTP_SERDES_1G,19 ICE_PTP_SERDES_10G,20 ICE_PTP_SERDES_25G,21 ICE_PTP_SERDES_40G,22 ICE_PTP_SERDES_50G,23 ICE_PTP_SERDES_100G24};25 26enum ice_ptp_link_spd {27 ICE_PTP_LNK_SPD_1G,28 ICE_PTP_LNK_SPD_10G,29 ICE_PTP_LNK_SPD_25G,30 ICE_PTP_LNK_SPD_25G_RS,31 ICE_PTP_LNK_SPD_40G,32 ICE_PTP_LNK_SPD_50G,33 ICE_PTP_LNK_SPD_50G_RS,34 ICE_PTP_LNK_SPD_100G_RS,35 NUM_ICE_PTP_LNK_SPD /* Must be last */36};37 38enum ice_ptp_fec_mode {39 ICE_PTP_FEC_MODE_NONE,40 ICE_PTP_FEC_MODE_CLAUSE74,41 ICE_PTP_FEC_MODE_RS_FEC42};43 44enum eth56g_res_type {45 ETH56G_PHY_REG_PTP,46 ETH56G_PHY_MEM_PTP,47 ETH56G_PHY_REG_XPCS,48 ETH56G_PHY_REG_MAC,49 ETH56G_PHY_REG_GPCS,50 NUM_ETH56G_PHY_RES51};52 53enum ice_eth56g_link_spd {54 ICE_ETH56G_LNK_SPD_1G,55 ICE_ETH56G_LNK_SPD_2_5G,56 ICE_ETH56G_LNK_SPD_10G,57 ICE_ETH56G_LNK_SPD_25G,58 ICE_ETH56G_LNK_SPD_40G,59 ICE_ETH56G_LNK_SPD_50G,60 ICE_ETH56G_LNK_SPD_50G2,61 ICE_ETH56G_LNK_SPD_100G,62 ICE_ETH56G_LNK_SPD_100G2,63 NUM_ICE_ETH56G_LNK_SPD /* Must be last */64};65 66/**67 * struct ice_phy_reg_info_eth56g - ETH56G PHY register parameters68 * @base: base address for each PHY block69 * @step: step between PHY lanes70 *71 * Characteristic information for the various PHY register parameters in the72 * ETH56G devices73 */74struct ice_phy_reg_info_eth56g {75 u32 base[NUM_ETH56G_PHY_RES];76 u32 step;77};78 79/**80 * struct ice_time_ref_info_e82x81 * @pll_freq: Frequency of PLL that drives timer ticks in Hz82 * @nominal_incval: increment to generate nanoseconds in GLTSYN_TIME_L83 * @pps_delay: propagation delay of the PPS output signal84 *85 * Characteristic information for the various TIME_REF sources possible in the86 * E822 devices87 */88struct ice_time_ref_info_e82x {89 u64 pll_freq;90 u64 nominal_incval;91 u8 pps_delay;92};93 94/**95 * struct ice_vernier_info_e82x96 * @tx_par_clk: Frequency used to calculate P_REG_PAR_TX_TUS97 * @rx_par_clk: Frequency used to calculate P_REG_PAR_RX_TUS98 * @tx_pcs_clk: Frequency used to calculate P_REG_PCS_TX_TUS99 * @rx_pcs_clk: Frequency used to calculate P_REG_PCS_RX_TUS100 * @tx_desk_rsgb_par: Frequency used to calculate P_REG_DESK_PAR_TX_TUS101 * @rx_desk_rsgb_par: Frequency used to calculate P_REG_DESK_PAR_RX_TUS102 * @tx_desk_rsgb_pcs: Frequency used to calculate P_REG_DESK_PCS_TX_TUS103 * @rx_desk_rsgb_pcs: Frequency used to calculate P_REG_DESK_PCS_RX_TUS104 * @tx_fixed_delay: Fixed Tx latency measured in 1/100th nanoseconds105 * @pmd_adj_divisor: Divisor used to calculate PDM alignment adjustment106 * @rx_fixed_delay: Fixed Rx latency measured in 1/100th nanoseconds107 *108 * Table of constants used during as part of the Vernier calibration of the Tx109 * and Rx timestamps. This includes frequency values used to compute TUs per110 * PAR/PCS clock cycle, and static delay values measured during hardware111 * design.112 *113 * Note that some values are not used for all link speeds, and the114 * P_REG_DESK_PAR* registers may represent different clock markers at115 * different link speeds, either the deskew marker for multi-lane link speeds116 * or the Reed Solomon gearbox marker for RS-FEC.117 */118struct ice_vernier_info_e82x {119 u32 tx_par_clk;120 u32 rx_par_clk;121 u32 tx_pcs_clk;122 u32 rx_pcs_clk;123 u32 tx_desk_rsgb_par;124 u32 rx_desk_rsgb_par;125 u32 tx_desk_rsgb_pcs;126 u32 rx_desk_rsgb_pcs;127 u32 tx_fixed_delay;128 u32 pmd_adj_divisor;129 u32 rx_fixed_delay;130};131 132#define ICE_ETH56G_MAC_CFG_RX_OFFSET_INT GENMASK(19, 9)133#define ICE_ETH56G_MAC_CFG_RX_OFFSET_FRAC GENMASK(8, 0)134#define ICE_ETH56G_MAC_CFG_FRAC_W 9135/**136 * struct ice_eth56g_mac_reg_cfg - MAC config values for specific PTP registers137 * @tx_mode: Tx timestamp compensation mode138 * @tx_mk_dly: Tx timestamp marker start strobe delay139 * @tx_cw_dly: Tx timestamp codeword start strobe delay140 * @rx_mode: Rx timestamp compensation mode141 * @rx_mk_dly: Rx timestamp marker start strobe delay142 * @rx_cw_dly: Rx timestamp codeword start strobe delay143 * @blks_per_clk: number of blocks transferred per clock cycle144 * @blktime: block time, fixed point145 * @mktime: marker time, fixed point146 * @tx_offset: total Tx offset, fixed point147 * @rx_offset: total Rx offset, contains value for bitslip/deskew, fixed point148 *149 * All fixed point registers except Rx offset are 23 bit unsigned ints with150 * a 9 bit fractional.151 * Rx offset is 11 bit unsigned int with a 9 bit fractional.152 */153struct ice_eth56g_mac_reg_cfg {154 struct {155 u8 def;156 u8 rs;157 } tx_mode;158 u8 tx_mk_dly;159 struct {160 u8 def;161 u8 onestep;162 } tx_cw_dly;163 struct {164 u8 def;165 u8 rs;166 } rx_mode;167 struct {168 u8 def;169 u8 rs;170 } rx_mk_dly;171 struct {172 u8 def;173 u8 rs;174 } rx_cw_dly;175 u8 blks_per_clk;176 u16 blktime;177 u16 mktime;178 struct {179 u32 serdes;180 u32 no_fec;181 u32 fc;182 u32 rs;183 u32 sfd;184 u32 onestep;185 } tx_offset;186 struct {187 u32 serdes;188 u32 no_fec;189 u32 fc;190 u32 rs;191 u32 sfd;192 u32 bs_ds;193 } rx_offset;194};195 196extern197const struct ice_eth56g_mac_reg_cfg eth56g_mac_cfg[NUM_ICE_ETH56G_LNK_SPD];198 199/**200 * struct ice_cgu_pll_params_e82x - E82X CGU parameters201 * @refclk_pre_div: Reference clock pre-divisor202 * @feedback_div: Feedback divisor203 * @frac_n_div: Fractional divisor204 * @post_pll_div: Post PLL divisor205 *206 * Clock Generation Unit parameters used to program the PLL based on the207 * selected TIME_REF frequency.208 */209struct ice_cgu_pll_params_e82x {210 u32 refclk_pre_div;211 u32 feedback_div;212 u32 frac_n_div;213 u32 post_pll_div;214};215 216#define E810C_QSFP_C827_0_HANDLE 2217#define E810C_QSFP_C827_1_HANDLE 3218enum ice_e810_c827_idx {219 C827_0,220 C827_1221};222 223enum ice_phy_rclk_pins {224 ICE_RCLKA_PIN = 0, /* SCL pin */225 ICE_RCLKB_PIN, /* SDA pin */226};227 228#define ICE_E810_RCLK_PINS_NUM (ICE_RCLKB_PIN + 1)229#define ICE_E82X_RCLK_PINS_NUM (ICE_RCLKA_PIN + 1)230#define E810T_CGU_INPUT_C827(_phy, _pin) ((_phy) * ICE_E810_RCLK_PINS_NUM + \231 (_pin) + ZL_REF1P)232 233enum ice_zl_cgu_in_pins {234 ZL_REF0P = 0,235 ZL_REF0N,236 ZL_REF1P,237 ZL_REF1N,238 ZL_REF2P,239 ZL_REF2N,240 ZL_REF3P,241 ZL_REF3N,242 ZL_REF4P,243 ZL_REF4N,244 NUM_ZL_CGU_INPUT_PINS245};246 247enum ice_zl_cgu_out_pins {248 ZL_OUT0 = 0,249 ZL_OUT1,250 ZL_OUT2,251 ZL_OUT3,252 ZL_OUT4,253 ZL_OUT5,254 ZL_OUT6,255 NUM_ZL_CGU_OUTPUT_PINS256};257 258enum ice_si_cgu_in_pins {259 SI_REF0P = 0,260 SI_REF0N,261 SI_REF1P,262 SI_REF1N,263 SI_REF2P,264 SI_REF2N,265 SI_REF3,266 SI_REF4,267 NUM_SI_CGU_INPUT_PINS268};269 270enum ice_si_cgu_out_pins {271 SI_OUT0 = 0,272 SI_OUT1,273 SI_OUT2,274 SI_OUT3,275 SI_OUT4,276 NUM_SI_CGU_OUTPUT_PINS277};278 279struct ice_cgu_pin_desc {280 char *name;281 u8 index;282 enum dpll_pin_type type;283 u32 freq_supp_num;284 struct dpll_pin_frequency *freq_supp;285};286 287extern const struct288ice_cgu_pll_params_e82x e822_cgu_params[NUM_ICE_TIME_REF_FREQ];289 290/**291 * struct ice_cgu_pll_params_e825c - E825C CGU parameters292 * @tspll_ck_refclkfreq: tspll_ck_refclkfreq selection293 * @tspll_ndivratio: ndiv ratio that goes directly to the pll294 * @tspll_fbdiv_intgr: TS PLL integer feedback divide295 * @tspll_fbdiv_frac: TS PLL fractional feedback divide296 * @ref1588_ck_div: clock divider for tspll ref297 *298 * Clock Generation Unit parameters used to program the PLL based on the299 * selected TIME_REF/TCXO frequency.300 */301struct ice_cgu_pll_params_e825c {302 u32 tspll_ck_refclkfreq;303 u32 tspll_ndivratio;304 u32 tspll_fbdiv_intgr;305 u32 tspll_fbdiv_frac;306 u32 ref1588_ck_div;307};308 309extern const struct310ice_cgu_pll_params_e825c e825c_cgu_params[NUM_ICE_TIME_REF_FREQ];311 312#define E810C_QSFP_C827_0_HANDLE 2313#define E810C_QSFP_C827_1_HANDLE 3314 315/* Table of constants related to possible ETH56G PHY resources */316extern const struct ice_phy_reg_info_eth56g eth56g_phy_res[NUM_ETH56G_PHY_RES];317 318/* Table of constants related to possible TIME_REF sources */319extern const struct ice_time_ref_info_e82x e822_time_ref[NUM_ICE_TIME_REF_FREQ];320 321/* Table of constants for Vernier calibration on E822 */322extern const struct ice_vernier_info_e82x e822_vernier[NUM_ICE_PTP_LNK_SPD];323 324/* Increment value to generate nanoseconds in the GLTSYN_TIME_L register for325 * the E810 devices. Based off of a PLL with an 812.5 MHz frequency.326 */327#define ICE_E810_PLL_FREQ 812500000328#define ICE_PTP_NOMINAL_INCVAL_E810 0x13b13b13bULL329#define E810_OUT_PROP_DELAY_NS 1330 331/* Device agnostic functions */332u8 ice_get_ptp_src_clock_index(struct ice_hw *hw);333bool ice_ptp_lock(struct ice_hw *hw);334void ice_ptp_unlock(struct ice_hw *hw);335void ice_ptp_src_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd);336int ice_ptp_init_time(struct ice_hw *hw, u64 time);337int ice_ptp_write_incval(struct ice_hw *hw, u64 incval);338int ice_ptp_write_incval_locked(struct ice_hw *hw, u64 incval);339int ice_ptp_adj_clock(struct ice_hw *hw, s32 adj);340int ice_ptp_clear_phy_offset_ready_e82x(struct ice_hw *hw);341int ice_read_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx, u64 *tstamp);342int ice_clear_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx);343void ice_ptp_reset_ts_memory(struct ice_hw *hw);344int ice_ptp_init_phc(struct ice_hw *hw);345void ice_ptp_init_hw(struct ice_hw *hw);346int ice_get_phy_tx_tstamp_ready(struct ice_hw *hw, u8 block, u64 *tstamp_ready);347int ice_ptp_one_port_cmd(struct ice_hw *hw, u8 configured_port,348 enum ice_ptp_tmr_cmd configured_cmd);349 350/* E822 family functions */351int ice_read_quad_reg_e82x(struct ice_hw *hw, u8 quad, u16 offset, u32 *val);352int ice_write_quad_reg_e82x(struct ice_hw *hw, u8 quad, u16 offset, u32 val);353void ice_ptp_reset_ts_memory_quad_e82x(struct ice_hw *hw, u8 quad);354 355/**356 * ice_e82x_time_ref - Get the current TIME_REF from capabilities357 * @hw: pointer to the HW structure358 *359 * Returns the current TIME_REF from the capabilities structure.360 */361static inline enum ice_time_ref_freq ice_e82x_time_ref(struct ice_hw *hw)362{363 return hw->func_caps.ts_func_info.time_ref;364}365 366/**367 * ice_set_e82x_time_ref - Set new TIME_REF368 * @hw: pointer to the HW structure369 * @time_ref: new TIME_REF to set370 *371 * Update the TIME_REF in the capabilities structure in response to some372 * change, such as an update to the CGU registers.373 */374static inline void375ice_set_e82x_time_ref(struct ice_hw *hw, enum ice_time_ref_freq time_ref)376{377 hw->func_caps.ts_func_info.time_ref = time_ref;378}379 380static inline u64 ice_e82x_pll_freq(enum ice_time_ref_freq time_ref)381{382 return e822_time_ref[time_ref].pll_freq;383}384 385static inline u64 ice_e82x_nominal_incval(enum ice_time_ref_freq time_ref)386{387 return e822_time_ref[time_ref].nominal_incval;388}389 390static inline u64 ice_e82x_pps_delay(enum ice_time_ref_freq time_ref)391{392 return e822_time_ref[time_ref].pps_delay;393}394 395/* E822 Vernier calibration functions */396int ice_stop_phy_timer_e82x(struct ice_hw *hw, u8 port, bool soft_reset);397int ice_start_phy_timer_e82x(struct ice_hw *hw, u8 port);398int ice_phy_cfg_tx_offset_e82x(struct ice_hw *hw, u8 port);399int ice_phy_cfg_rx_offset_e82x(struct ice_hw *hw, u8 port);400int ice_phy_cfg_intr_e82x(struct ice_hw *hw, u8 quad, bool ena, u8 threshold);401 402/* E810 family functions */403int ice_read_sma_ctrl_e810t(struct ice_hw *hw, u8 *data);404int ice_write_sma_ctrl_e810t(struct ice_hw *hw, u8 data);405int ice_read_pca9575_reg_e810t(struct ice_hw *hw, u8 offset, u8 *data);406bool ice_is_pca9575_present(struct ice_hw *hw);407int ice_cgu_get_num_pins(struct ice_hw *hw, bool input);408enum dpll_pin_type ice_cgu_get_pin_type(struct ice_hw *hw, u8 pin, bool input);409struct dpll_pin_frequency *410ice_cgu_get_pin_freq_supp(struct ice_hw *hw, u8 pin, bool input, u8 *num);411const char *ice_cgu_get_pin_name(struct ice_hw *hw, u8 pin, bool input);412int ice_get_cgu_state(struct ice_hw *hw, u8 dpll_idx,413 enum dpll_lock_status last_dpll_state, u8 *pin,414 u8 *ref_state, u8 *eec_mode, s64 *phase_offset,415 enum dpll_lock_status *dpll_state);416int ice_get_cgu_rclk_pin_info(struct ice_hw *hw, u8 *base_idx, u8 *pin_num);417int ice_cgu_get_output_pin_state_caps(struct ice_hw *hw, u8 pin_id,418 unsigned long *caps);419 420/* ETH56G family functions */421int ice_ptp_read_tx_hwtstamp_status_eth56g(struct ice_hw *hw, u32 *ts_status);422int ice_stop_phy_timer_eth56g(struct ice_hw *hw, u8 port, bool soft_reset);423int ice_start_phy_timer_eth56g(struct ice_hw *hw, u8 port);424int ice_phy_cfg_tx_offset_eth56g(struct ice_hw *hw, u8 port);425int ice_phy_cfg_rx_offset_eth56g(struct ice_hw *hw, u8 port);426int ice_phy_cfg_intr_eth56g(struct ice_hw *hw, u8 port, bool ena, u8 threshold);427int ice_phy_cfg_ptp_1step_eth56g(struct ice_hw *hw, u8 port);428 429#define ICE_ETH56G_NOMINAL_INCVAL 0x140000000ULL430#define ICE_ETH56G_NOMINAL_PCS_REF_TUS 0x100000000ULL431#define ICE_ETH56G_NOMINAL_PCS_REF_INC 0x300000000ULL432#define ICE_ETH56G_NOMINAL_THRESH4 0x7777433#define ICE_ETH56G_NOMINAL_TX_THRESH 0x6434 435/**436 * ice_get_base_incval - Get base clock increment value437 * @hw: pointer to the HW struct438 *439 * Return: base clock increment value for supported PHYs, 0 otherwise440 */441static inline u64 ice_get_base_incval(struct ice_hw *hw)442{443 switch (hw->ptp.phy_model) {444 case ICE_PHY_ETH56G:445 return ICE_ETH56G_NOMINAL_INCVAL;446 case ICE_PHY_E810:447 return ICE_PTP_NOMINAL_INCVAL_E810;448 case ICE_PHY_E82X:449 return ice_e82x_nominal_incval(ice_e82x_time_ref(hw));450 default:451 return 0;452 }453}454 455#define PFTSYN_SEM_BYTES 4456 457#define ICE_PTP_CLOCK_INDEX_0 0x00458#define ICE_PTP_CLOCK_INDEX_1 0x01459 460/* PHY timer commands */461#define SEL_CPK_SRC 8462#define SEL_PHY_SRC 3463 464/* Time Sync command Definitions */465#define GLTSYN_CMD_INIT_TIME BIT(0)466#define GLTSYN_CMD_INIT_INCVAL BIT(1)467#define GLTSYN_CMD_INIT_TIME_INCVAL (BIT(0) | BIT(1))468#define GLTSYN_CMD_ADJ_TIME BIT(2)469#define GLTSYN_CMD_ADJ_INIT_TIME (BIT(2) | BIT(3))470#define GLTSYN_CMD_READ_TIME BIT(7)471 472/* PHY port Time Sync command definitions */473#define PHY_CMD_INIT_TIME BIT(0)474#define PHY_CMD_INIT_INCVAL BIT(1)475#define PHY_CMD_ADJ_TIME (BIT(0) | BIT(1))476#define PHY_CMD_ADJ_TIME_AT_TIME (BIT(0) | BIT(2))477#define PHY_CMD_READ_TIME (BIT(0) | BIT(1) | BIT(2))478 479#define TS_CMD_MASK_E810 0xFF480#define TS_CMD_MASK 0xF481#define SYNC_EXEC_CMD 0x3482#define TS_CMD_RX_TYPE ICE_M(0x18, 0x4)483 484/* Macros to derive port low and high addresses on both quads */485#define P_Q0_L(a, p) ((((a) + (0x2000 * (p)))) & 0xFFFF)486#define P_Q0_H(a, p) ((((a) + (0x2000 * (p)))) >> 16)487#define P_Q1_L(a, p) ((((a) - (0x2000 * ((p) - ICE_PORTS_PER_QUAD)))) & 0xFFFF)488#define P_Q1_H(a, p) ((((a) - (0x2000 * ((p) - ICE_PORTS_PER_QUAD)))) >> 16)489 490/* PHY QUAD register base addresses */491#define Q_0_BASE 0x94000492#define Q_1_BASE 0x114000493 494/* Timestamp memory reset registers */495#define Q_REG_TS_CTRL 0x618496#define Q_REG_TS_CTRL_S 0497#define Q_REG_TS_CTRL_M BIT(0)498 499/* Timestamp availability status registers */500#define Q_REG_TX_MEMORY_STATUS_L 0xCF0501#define Q_REG_TX_MEMORY_STATUS_U 0xCF4502 503/* Tx FIFO status registers */504#define Q_REG_FIFO23_STATUS 0xCF8505#define Q_REG_FIFO01_STATUS 0xCFC506#define Q_REG_FIFO02_S 0507#define Q_REG_FIFO02_M ICE_M(0x3FF, 0)508#define Q_REG_FIFO13_S 10509#define Q_REG_FIFO13_M ICE_M(0x3FF, 10)510 511/* Interrupt control Config registers */512#define Q_REG_TX_MEM_GBL_CFG 0xC08513#define Q_REG_TX_MEM_GBL_CFG_LANE_TYPE_S 0514#define Q_REG_TX_MEM_GBL_CFG_LANE_TYPE_M BIT(0)515#define Q_REG_TX_MEM_GBL_CFG_TX_TYPE_M ICE_M(0xFF, 1)516#define Q_REG_TX_MEM_GBL_CFG_INTR_THR_M ICE_M(0x3F, 9)517#define Q_REG_TX_MEM_GBL_CFG_INTR_ENA_M BIT(15)518 519/* Tx Timestamp data registers */520#define Q_REG_TX_MEMORY_BANK_START 0xA00521 522/* PHY port register base addresses */523#define P_0_BASE 0x80000524#define P_4_BASE 0x106000525 526/* Timestamp init registers */527#define P_REG_RX_TIMER_INC_PRE_L 0x46C528#define P_REG_RX_TIMER_INC_PRE_U 0x470529#define P_REG_TX_TIMER_INC_PRE_L 0x44C530#define P_REG_TX_TIMER_INC_PRE_U 0x450531 532/* Timestamp match and adjust target registers */533#define P_REG_RX_TIMER_CNT_ADJ_L 0x474534#define P_REG_RX_TIMER_CNT_ADJ_U 0x478535#define P_REG_TX_TIMER_CNT_ADJ_L 0x454536#define P_REG_TX_TIMER_CNT_ADJ_U 0x458537 538/* Timestamp capture registers */539#define P_REG_RX_CAPTURE_L 0x4D8540#define P_REG_RX_CAPTURE_U 0x4DC541#define P_REG_TX_CAPTURE_L 0x4B4542#define P_REG_TX_CAPTURE_U 0x4B8543 544/* Timestamp PHY incval registers */545#define P_REG_TIMETUS_L 0x410546#define P_REG_TIMETUS_U 0x414547 548#define P_REG_40B_LOW_M GENMASK(7, 0)549#define P_REG_40B_HIGH_S 8550 551/* PHY window length registers */552#define P_REG_WL 0x40C553 554#define PTP_VERNIER_WL 0x111ed555 556/* PHY start registers */557#define P_REG_PS 0x408558#define P_REG_PS_START_S 0559#define P_REG_PS_START_M BIT(0)560#define P_REG_PS_BYPASS_MODE_S 1561#define P_REG_PS_BYPASS_MODE_M BIT(1)562#define P_REG_PS_ENA_CLK_S 2563#define P_REG_PS_ENA_CLK_M BIT(2)564#define P_REG_PS_LOAD_OFFSET_S 3565#define P_REG_PS_LOAD_OFFSET_M BIT(3)566#define P_REG_PS_SFT_RESET_S 11567#define P_REG_PS_SFT_RESET_M BIT(11)568 569/* PHY offset valid registers */570#define P_REG_TX_OV_STATUS 0x4D4571#define P_REG_TX_OV_STATUS_OV_S 0572#define P_REG_TX_OV_STATUS_OV_M BIT(0)573#define P_REG_RX_OV_STATUS 0x4F8574#define P_REG_RX_OV_STATUS_OV_S 0575#define P_REG_RX_OV_STATUS_OV_M BIT(0)576 577/* PHY offset ready registers */578#define P_REG_TX_OR 0x45C579#define P_REG_RX_OR 0x47C580 581/* PHY total offset registers */582#define P_REG_TOTAL_RX_OFFSET_L 0x460583#define P_REG_TOTAL_RX_OFFSET_U 0x464584#define P_REG_TOTAL_TX_OFFSET_L 0x440585#define P_REG_TOTAL_TX_OFFSET_U 0x444586 587/* Timestamp PAR/PCS registers */588#define P_REG_UIX66_10G_40G_L 0x480589#define P_REG_UIX66_10G_40G_U 0x484590#define P_REG_UIX66_25G_100G_L 0x488591#define P_REG_UIX66_25G_100G_U 0x48C592#define P_REG_DESK_PAR_RX_TUS_L 0x490593#define P_REG_DESK_PAR_RX_TUS_U 0x494594#define P_REG_DESK_PAR_TX_TUS_L 0x498595#define P_REG_DESK_PAR_TX_TUS_U 0x49C596#define P_REG_DESK_PCS_RX_TUS_L 0x4A0597#define P_REG_DESK_PCS_RX_TUS_U 0x4A4598#define P_REG_DESK_PCS_TX_TUS_L 0x4A8599#define P_REG_DESK_PCS_TX_TUS_U 0x4AC600#define P_REG_PAR_RX_TUS_L 0x420601#define P_REG_PAR_RX_TUS_U 0x424602#define P_REG_PAR_TX_TUS_L 0x428603#define P_REG_PAR_TX_TUS_U 0x42C604#define P_REG_PCS_RX_TUS_L 0x430605#define P_REG_PCS_RX_TUS_U 0x434606#define P_REG_PCS_TX_TUS_L 0x438607#define P_REG_PCS_TX_TUS_U 0x43C608#define P_REG_PAR_RX_TIME_L 0x4F0609#define P_REG_PAR_RX_TIME_U 0x4F4610#define P_REG_PAR_TX_TIME_L 0x4CC611#define P_REG_PAR_TX_TIME_U 0x4D0612#define P_REG_PAR_PCS_RX_OFFSET_L 0x4E8613#define P_REG_PAR_PCS_RX_OFFSET_U 0x4EC614#define P_REG_PAR_PCS_TX_OFFSET_L 0x4C4615#define P_REG_PAR_PCS_TX_OFFSET_U 0x4C8616#define P_REG_LINK_SPEED 0x4FC617#define P_REG_LINK_SPEED_SERDES_S 0618#define P_REG_LINK_SPEED_SERDES_M ICE_M(0x7, 0)619#define P_REG_LINK_SPEED_FEC_MODE_S 3620#define P_REG_LINK_SPEED_FEC_MODE_M ICE_M(0x3, 3)621#define P_REG_LINK_SPEED_FEC_MODE(reg) \622 (((reg) & P_REG_LINK_SPEED_FEC_MODE_M) >> \623 P_REG_LINK_SPEED_FEC_MODE_S)624 625/* PHY timestamp related registers */626#define P_REG_PMD_ALIGNMENT 0x0FC627#define P_REG_RX_80_TO_160_CNT 0x6FC628#define P_REG_RX_80_TO_160_CNT_RXCYC_S 0629#define P_REG_RX_80_TO_160_CNT_RXCYC_M BIT(0)630#define P_REG_RX_40_TO_160_CNT 0x8FC631#define P_REG_RX_40_TO_160_CNT_RXCYC_S 0632#define P_REG_RX_40_TO_160_CNT_RXCYC_M ICE_M(0x3, 0)633 634/* Rx FIFO status registers */635#define P_REG_RX_OV_FS 0x4F8636#define P_REG_RX_OV_FS_FIFO_STATUS_S 2637#define P_REG_RX_OV_FS_FIFO_STATUS_M ICE_M(0x3FF, 2)638 639/* Timestamp command registers */640#define P_REG_TX_TMR_CMD 0x448641#define P_REG_RX_TMR_CMD 0x468642 643/* E810 timesync enable register */644#define ETH_GLTSYN_ENA(_i) (0x03000348 + ((_i) * 4))645 646/* E810 shadow init time registers */647#define ETH_GLTSYN_SHTIME_0(i) (0x03000368 + ((i) * 32))648#define ETH_GLTSYN_SHTIME_L(i) (0x0300036C + ((i) * 32))649 650/* E810 shadow time adjust registers */651#define ETH_GLTSYN_SHADJ_L(_i) (0x03000378 + ((_i) * 32))652#define ETH_GLTSYN_SHADJ_H(_i) (0x0300037C + ((_i) * 32))653 654/* E810 timer command register */655#define E810_ETH_GLTSYN_CMD 0x03000344656 657/* Source timer incval macros */658#define INCVAL_HIGH_M 0xFF659 660/* Timestamp block macros */661#define TS_VALID BIT(0)662#define TS_LOW_M 0xFFFFFFFF663#define TS_HIGH_M 0xFF664#define TS_HIGH_S 32665 666#define TS_PHY_LOW_M 0xFF667#define TS_PHY_HIGH_M 0xFFFFFFFF668#define TS_PHY_HIGH_S 8669 670#define BYTES_PER_IDX_ADDR_L_U 8671#define BYTES_PER_IDX_ADDR_L 4672 673/* Tx timestamp low latency read definitions */674#define TS_LL_READ_RETRIES 200675#define TS_LL_READ_TS_HIGH GENMASK(23, 16)676#define TS_LL_READ_TS_IDX GENMASK(29, 24)677#define TS_LL_READ_TS_INTR BIT(30)678#define TS_LL_READ_TS BIT(31)679 680/* Internal PHY timestamp address */681#define TS_L(a, idx) ((a) + ((idx) * BYTES_PER_IDX_ADDR_L_U))682#define TS_H(a, idx) ((a) + ((idx) * BYTES_PER_IDX_ADDR_L_U + \683 BYTES_PER_IDX_ADDR_L))684 685/* External PHY timestamp address */686#define TS_EXT(a, port, idx) ((a) + (0x1000 * (port)) + \687 ((idx) * BYTES_PER_IDX_ADDR_L_U))688 689#define LOW_TX_MEMORY_BANK_START 0x03090000690#define HIGH_TX_MEMORY_BANK_START 0x03090004691 692/* E810T SMA controller pin control */693#define ICE_SMA1_DIR_EN_E810T BIT(4)694#define ICE_SMA1_TX_EN_E810T BIT(5)695#define ICE_SMA2_UFL2_RX_DIS_E810T BIT(3)696#define ICE_SMA2_DIR_EN_E810T BIT(6)697#define ICE_SMA2_TX_EN_E810T BIT(7)698 699#define ICE_SMA1_MASK_E810T (ICE_SMA1_DIR_EN_E810T | \700 ICE_SMA1_TX_EN_E810T)701#define ICE_SMA2_MASK_E810T (ICE_SMA2_UFL2_RX_DIS_E810T | \702 ICE_SMA2_DIR_EN_E810T | \703 ICE_SMA2_TX_EN_E810T)704#define ICE_ALL_SMA_MASK_E810T (ICE_SMA1_MASK_E810T | \705 ICE_SMA2_MASK_E810T)706 707#define ICE_SMA_MIN_BIT_E810T 3708#define ICE_SMA_MAX_BIT_E810T 7709#define ICE_PCA9575_P1_OFFSET 8710 711/* E810T PCA9575 IO controller registers */712#define ICE_PCA9575_P0_IN 0x0713 714/* E810T PCA9575 IO controller pin control */715#define ICE_E810T_P0_GNSS_PRSNT_N BIT(4)716 717/* ETH56G PHY register addresses */718/* Timestamp PHY incval registers */719#define PHY_REG_TIMETUS_L 0x8720#define PHY_REG_TIMETUS_U 0xC721 722/* Timestamp PCS registers */723#define PHY_PCS_REF_TUS_L 0x18724#define PHY_PCS_REF_TUS_U 0x1C725 726/* Timestamp PCS ref incval registers */727#define PHY_PCS_REF_INC_L 0x20728#define PHY_PCS_REF_INC_U 0x24729 730/* Timestamp init registers */731#define PHY_REG_RX_TIMER_INC_PRE_L 0x64732#define PHY_REG_RX_TIMER_INC_PRE_U 0x68733#define PHY_REG_TX_TIMER_INC_PRE_L 0x44734#define PHY_REG_TX_TIMER_INC_PRE_U 0x48735 736/* Timestamp match and adjust target registers */737#define PHY_REG_RX_TIMER_CNT_ADJ_L 0x6C738#define PHY_REG_RX_TIMER_CNT_ADJ_U 0x70739#define PHY_REG_TX_TIMER_CNT_ADJ_L 0x4C740#define PHY_REG_TX_TIMER_CNT_ADJ_U 0x50741 742/* Timestamp command registers */743#define PHY_REG_TX_TMR_CMD 0x40744#define PHY_REG_RX_TMR_CMD 0x60745 746/* Phy offset ready registers */747#define PHY_REG_TX_OFFSET_READY 0x54748#define PHY_REG_RX_OFFSET_READY 0x74749 750/* Phy total offset registers */751#define PHY_REG_TOTAL_TX_OFFSET_L 0x38752#define PHY_REG_TOTAL_TX_OFFSET_U 0x3C753#define PHY_REG_TOTAL_RX_OFFSET_L 0x58754#define PHY_REG_TOTAL_RX_OFFSET_U 0x5C755 756/* Timestamp capture registers */757#define PHY_REG_TX_CAPTURE_L 0x78758#define PHY_REG_TX_CAPTURE_U 0x7C759#define PHY_REG_RX_CAPTURE_L 0x8C760#define PHY_REG_RX_CAPTURE_U 0x90761 762/* Memory status registers */763#define PHY_REG_TX_MEMORY_STATUS_L 0x80764#define PHY_REG_TX_MEMORY_STATUS_U 0x84765 766/* Interrupt config register */767#define PHY_REG_TS_INT_CONFIG 0x88768 769/* XIF mode config register */770#define PHY_MAC_XIF_MODE 0x24771#define PHY_MAC_XIF_1STEP_ENA_M ICE_M(0x1, 5)772#define PHY_MAC_XIF_TS_BIN_MODE_M ICE_M(0x1, 11)773#define PHY_MAC_XIF_TS_SFD_ENA_M ICE_M(0x1, 20)774#define PHY_MAC_XIF_GMII_TS_SEL_M ICE_M(0x1, 21)775 776/* GPCS config register */777#define PHY_GPCS_CONFIG_REG0 0x268778#define PHY_GPCS_CONFIG_REG0_TX_THR_M ICE_M(0xF, 24)779#define PHY_GPCS_BITSLIP 0x5C780 781#define PHY_TS_INT_CONFIG_THRESHOLD_M ICE_M(0x3F, 0)782#define PHY_TS_INT_CONFIG_ENA_M BIT(6)783 784/* 1-step PTP config */785#define PHY_PTP_1STEP_CONFIG 0x270786#define PHY_PTP_1STEP_T1S_UP64_M ICE_M(0xF, 4)787#define PHY_PTP_1STEP_T1S_DELTA_M ICE_M(0xF, 8)788#define PHY_PTP_1STEP_PEER_DELAY(_port) (0x274 + 4 * (_port))789#define PHY_PTP_1STEP_PD_ADD_PD_M ICE_M(0x1, 0)790#define PHY_PTP_1STEP_PD_DELAY_M ICE_M(0x3fffffff, 1)791#define PHY_PTP_1STEP_PD_DLY_V_M ICE_M(0x1, 31)792 793/* Macros to derive offsets for TimeStampLow and TimeStampHigh */794#define PHY_TSTAMP_L(x) (((x) * 8) + 0)795#define PHY_TSTAMP_U(x) (((x) * 8) + 4)796 797#define PHY_REG_REVISION 0x85000798 799#define PHY_REG_DESKEW_0 0x94800#define PHY_REG_DESKEW_0_RLEVEL GENMASK(6, 0)801#define PHY_REG_DESKEW_0_RLEVEL_FRAC GENMASK(9, 7)802#define PHY_REG_DESKEW_0_RLEVEL_FRAC_W 3803#define PHY_REG_DESKEW_0_VALID GENMASK(10, 10)804 805#define PHY_REG_GPCS_BITSLIP 0x5C806#define PHY_REG_SD_BIT_SLIP(_port_offset) (0x29C + 4 * (_port_offset))807#define PHY_REVISION_ETH56G 0x10200808#define PHY_VENDOR_TXLANE_THRESH 0x2000C809 810#define PHY_MAC_TSU_CONFIG 0x40811#define PHY_MAC_TSU_CFG_RX_MODE_M ICE_M(0x7, 0)812#define PHY_MAC_TSU_CFG_RX_MII_CW_DLY_M ICE_M(0x7, 4)813#define PHY_MAC_TSU_CFG_RX_MII_MK_DLY_M ICE_M(0x7, 8)814#define PHY_MAC_TSU_CFG_TX_MODE_M ICE_M(0x7, 12)815#define PHY_MAC_TSU_CFG_TX_MII_CW_DLY_M ICE_M(0x1F, 16)816#define PHY_MAC_TSU_CFG_TX_MII_MK_DLY_M ICE_M(0x1F, 21)817#define PHY_MAC_TSU_CFG_BLKS_PER_CLK_M ICE_M(0x1, 28)818#define PHY_MAC_RX_MODULO 0x44819#define PHY_MAC_RX_OFFSET 0x48820#define PHY_MAC_RX_OFFSET_M ICE_M(0xFFFFFF, 0)821#define PHY_MAC_TX_MODULO 0x4C822#define PHY_MAC_BLOCKTIME 0x50823#define PHY_MAC_MARKERTIME 0x54824#define PHY_MAC_TX_OFFSET 0x58825 826#define PHY_PTP_INT_STATUS 0x7FD140827 828#endif /* _ICE_PTP_HW_H_ */829