125 lines · c
1/* SPDX-License-Identifier: GPL-2.0-only */2/* Copyright (C) 2023 Intel Corporation */3 4#ifndef _IDPF_LAN_PF_REGS_H_5#define _IDPF_LAN_PF_REGS_H_6 7/* Receive queues */8#define PF_QRX_BASE 0x000000009#define PF_QRX_TAIL(_QRX) (PF_QRX_BASE + (((_QRX) * 0x1000)))10#define PF_QRX_BUFFQ_BASE 0x0300000011#define PF_QRX_BUFFQ_TAIL(_QRX) (PF_QRX_BUFFQ_BASE + (((_QRX) * 0x1000)))12 13/* Transmit queues */14#define PF_QTX_BASE 0x0500000015#define PF_QTX_COMM_DBELL(_DBQM) (PF_QTX_BASE + ((_DBQM) * 0x1000))16 17/* Control(PF Mailbox) Queue */18#define PF_FW_BASE 0x0840000019 20#define PF_FW_ARQBAL (PF_FW_BASE)21#define PF_FW_ARQBAH (PF_FW_BASE + 0x4)22#define PF_FW_ARQLEN (PF_FW_BASE + 0x8)23#define PF_FW_ARQLEN_ARQLEN_S 024#define PF_FW_ARQLEN_ARQLEN_M GENMASK(12, 0)25#define PF_FW_ARQLEN_ARQVFE_S 2826#define PF_FW_ARQLEN_ARQVFE_M BIT(PF_FW_ARQLEN_ARQVFE_S)27#define PF_FW_ARQLEN_ARQOVFL_S 2928#define PF_FW_ARQLEN_ARQOVFL_M BIT(PF_FW_ARQLEN_ARQOVFL_S)29#define PF_FW_ARQLEN_ARQCRIT_S 3030#define PF_FW_ARQLEN_ARQCRIT_M BIT(PF_FW_ARQLEN_ARQCRIT_S)31#define PF_FW_ARQLEN_ARQENABLE_S 3132#define PF_FW_ARQLEN_ARQENABLE_M BIT(PF_FW_ARQLEN_ARQENABLE_S)33#define PF_FW_ARQH (PF_FW_BASE + 0xC)34#define PF_FW_ARQH_ARQH_S 035#define PF_FW_ARQH_ARQH_M GENMASK(12, 0)36#define PF_FW_ARQT (PF_FW_BASE + 0x10)37 38#define PF_FW_ATQBAL (PF_FW_BASE + 0x14)39#define PF_FW_ATQBAH (PF_FW_BASE + 0x18)40#define PF_FW_ATQLEN (PF_FW_BASE + 0x1C)41#define PF_FW_ATQLEN_ATQLEN_S 042#define PF_FW_ATQLEN_ATQLEN_M GENMASK(9, 0)43#define PF_FW_ATQLEN_ATQVFE_S 2844#define PF_FW_ATQLEN_ATQVFE_M BIT(PF_FW_ATQLEN_ATQVFE_S)45#define PF_FW_ATQLEN_ATQOVFL_S 2946#define PF_FW_ATQLEN_ATQOVFL_M BIT(PF_FW_ATQLEN_ATQOVFL_S)47#define PF_FW_ATQLEN_ATQCRIT_S 3048#define PF_FW_ATQLEN_ATQCRIT_M BIT(PF_FW_ATQLEN_ATQCRIT_S)49#define PF_FW_ATQLEN_ATQENABLE_S 3150#define PF_FW_ATQLEN_ATQENABLE_M BIT(PF_FW_ATQLEN_ATQENABLE_S)51#define PF_FW_ATQH (PF_FW_BASE + 0x20)52#define PF_FW_ATQH_ATQH_S 053#define PF_FW_ATQH_ATQH_M GENMASK(9, 0)54#define PF_FW_ATQT (PF_FW_BASE + 0x24)55 56/* Interrupts */57#define PF_GLINT_BASE 0x0890000058#define PF_GLINT_DYN_CTL(_INT) (PF_GLINT_BASE + ((_INT) * 0x1000))59#define PF_GLINT_DYN_CTL_INTENA_S 060#define PF_GLINT_DYN_CTL_INTENA_M BIT(PF_GLINT_DYN_CTL_INTENA_S)61#define PF_GLINT_DYN_CTL_CLEARPBA_S 162#define PF_GLINT_DYN_CTL_CLEARPBA_M BIT(PF_GLINT_DYN_CTL_CLEARPBA_S)63#define PF_GLINT_DYN_CTL_SWINT_TRIG_S 264#define PF_GLINT_DYN_CTL_SWINT_TRIG_M BIT(PF_GLINT_DYN_CTL_SWINT_TRIG_S)65#define PF_GLINT_DYN_CTL_ITR_INDX_S 366#define PF_GLINT_DYN_CTL_ITR_INDX_M GENMASK(4, 3)67#define PF_GLINT_DYN_CTL_INTERVAL_S 568#define PF_GLINT_DYN_CTL_INTERVAL_M BIT(PF_GLINT_DYN_CTL_INTERVAL_S)69#define PF_GLINT_DYN_CTL_SW_ITR_INDX_ENA_S 2470#define PF_GLINT_DYN_CTL_SW_ITR_INDX_ENA_M BIT(PF_GLINT_DYN_CTL_SW_ITR_INDX_ENA_S)71#define PF_GLINT_DYN_CTL_SW_ITR_INDX_S 2572#define PF_GLINT_DYN_CTL_SW_ITR_INDX_M BIT(PF_GLINT_DYN_CTL_SW_ITR_INDX_S)73#define PF_GLINT_DYN_CTL_WB_ON_ITR_S 3074#define PF_GLINT_DYN_CTL_WB_ON_ITR_M BIT(PF_GLINT_DYN_CTL_WB_ON_ITR_S)75#define PF_GLINT_DYN_CTL_INTENA_MSK_S 3176#define PF_GLINT_DYN_CTL_INTENA_MSK_M BIT(PF_GLINT_DYN_CTL_INTENA_MSK_S)77/* _ITR is ITR index, _INT is interrupt index, _itrn_indx_spacing is78 * spacing b/w itrn registers of the same vector.79 */80#define PF_GLINT_ITR_ADDR(_ITR, _reg_start, _itrn_indx_spacing) \81 ((_reg_start) + ((_ITR) * (_itrn_indx_spacing)))82/* For PF, itrn_indx_spacing is 4 and itrn_reg_spacing is 0x1000 */83#define PF_GLINT_ITR(_ITR, _INT) \84 (PF_GLINT_BASE + (((_ITR) + 1) * 4) + ((_INT) * 0x1000))85#define PF_GLINT_ITR_MAX_INDEX 286#define PF_GLINT_ITR_INTERVAL_S 087#define PF_GLINT_ITR_INTERVAL_M GENMASK(11, 0)88 89/* Generic registers */90#define PF_INT_DIR_OICR_ENA 0x0840600091#define PF_INT_DIR_OICR_ENA_S 092#define PF_INT_DIR_OICR_ENA_M GENMASK(31, 0)93#define PF_INT_DIR_OICR 0x0840600494#define PF_INT_DIR_OICR_TSYN_EVNT 095#define PF_INT_DIR_OICR_PHY_TS_0 BIT(1)96#define PF_INT_DIR_OICR_PHY_TS_1 BIT(2)97#define PF_INT_DIR_OICR_CAUSE 0x0840600898#define PF_INT_DIR_OICR_CAUSE_CAUSE_S 099#define PF_INT_DIR_OICR_CAUSE_CAUSE_M GENMASK(31, 0)100#define PF_INT_PBA_CLEAR 0x0840600C101 102#define PF_FUNC_RID 0x08406010103#define PF_FUNC_RID_FUNCTION_NUMBER_S 0104#define PF_FUNC_RID_FUNCTION_NUMBER_M GENMASK(2, 0)105#define PF_FUNC_RID_DEVICE_NUMBER_S 3106#define PF_FUNC_RID_DEVICE_NUMBER_M GENMASK(7, 3)107#define PF_FUNC_RID_BUS_NUMBER_S 8108#define PF_FUNC_RID_BUS_NUMBER_M GENMASK(15, 8)109 110/* Reset registers */111#define PFGEN_RTRIG 0x08407000112#define PFGEN_RTRIG_CORER_S 0113#define PFGEN_RTRIG_CORER_M BIT(0)114#define PFGEN_RTRIG_LINKR_S 1115#define PFGEN_RTRIG_LINKR_M BIT(1)116#define PFGEN_RTRIG_IMCR_S 2117#define PFGEN_RTRIG_IMCR_M BIT(2)118#define PFGEN_RSTAT 0x08407008 /* PFR Status */119#define PFGEN_RSTAT_PFR_STATE_S 0120#define PFGEN_RSTAT_PFR_STATE_M GENMASK(1, 0)121#define PFGEN_CTRL 0x0840700C122#define PFGEN_CTRL_PFSWR BIT(0)123 124#endif125