129 lines · c
1/* SPDX-License-Identifier: GPL-2.0-only */2/* Copyright (C) 2023 Intel Corporation */3 4#ifndef _IDPF_LAN_VF_REGS_H_5#define _IDPF_LAN_VF_REGS_H_6 7/* Reset */8#define VFGEN_RSTAT 0x000088009#define VFGEN_RSTAT_VFR_STATE_S 010#define VFGEN_RSTAT_VFR_STATE_M GENMASK(1, 0)11 12/* Control(VF Mailbox) Queue */13#define VF_BASE 0x0000600014 15#define VF_ATQBAL (VF_BASE + 0x1C00)16#define VF_ATQBAH (VF_BASE + 0x1800)17#define VF_ATQLEN (VF_BASE + 0x0800)18#define VF_ATQLEN_ATQLEN_S 019#define VF_ATQLEN_ATQLEN_M GENMASK(9, 0)20#define VF_ATQLEN_ATQVFE_S 2821#define VF_ATQLEN_ATQVFE_M BIT(VF_ATQLEN_ATQVFE_S)22#define VF_ATQLEN_ATQOVFL_S 2923#define VF_ATQLEN_ATQOVFL_M BIT(VF_ATQLEN_ATQOVFL_S)24#define VF_ATQLEN_ATQCRIT_S 3025#define VF_ATQLEN_ATQCRIT_M BIT(VF_ATQLEN_ATQCRIT_S)26#define VF_ATQLEN_ATQENABLE_S 3127#define VF_ATQLEN_ATQENABLE_M BIT(VF_ATQLEN_ATQENABLE_S)28#define VF_ATQH (VF_BASE + 0x0400)29#define VF_ATQH_ATQH_S 030#define VF_ATQH_ATQH_M GENMASK(9, 0)31#define VF_ATQT (VF_BASE + 0x2400)32 33#define VF_ARQBAL (VF_BASE + 0x0C00)34#define VF_ARQBAH (VF_BASE)35#define VF_ARQLEN (VF_BASE + 0x2000)36#define VF_ARQLEN_ARQLEN_S 037#define VF_ARQLEN_ARQLEN_M GENMASK(9, 0)38#define VF_ARQLEN_ARQVFE_S 2839#define VF_ARQLEN_ARQVFE_M BIT(VF_ARQLEN_ARQVFE_S)40#define VF_ARQLEN_ARQOVFL_S 2941#define VF_ARQLEN_ARQOVFL_M BIT(VF_ARQLEN_ARQOVFL_S)42#define VF_ARQLEN_ARQCRIT_S 3043#define VF_ARQLEN_ARQCRIT_M BIT(VF_ARQLEN_ARQCRIT_S)44#define VF_ARQLEN_ARQENABLE_S 3145#define VF_ARQLEN_ARQENABLE_M BIT(VF_ARQLEN_ARQENABLE_S)46#define VF_ARQH (VF_BASE + 0x1400)47#define VF_ARQH_ARQH_S 048#define VF_ARQH_ARQH_M GENMASK(12, 0)49#define VF_ARQT (VF_BASE + 0x1000)50 51/* Transmit queues */52#define VF_QTX_TAIL_BASE 0x0000000053#define VF_QTX_TAIL(_QTX) (VF_QTX_TAIL_BASE + (_QTX) * 0x4)54#define VF_QTX_TAIL_EXT_BASE 0x0004000055#define VF_QTX_TAIL_EXT(_QTX) (VF_QTX_TAIL_EXT_BASE + ((_QTX) * 4))56 57/* Receive queues */58#define VF_QRX_TAIL_BASE 0x0000200059#define VF_QRX_TAIL(_QRX) (VF_QRX_TAIL_BASE + ((_QRX) * 4))60#define VF_QRX_TAIL_EXT_BASE 0x0005000061#define VF_QRX_TAIL_EXT(_QRX) (VF_QRX_TAIL_EXT_BASE + ((_QRX) * 4))62#define VF_QRXB_TAIL_BASE 0x0006000063#define VF_QRXB_TAIL(_QRX) (VF_QRXB_TAIL_BASE + ((_QRX) * 4))64 65/* Interrupts */66#define VF_INT_DYN_CTL0 0x00005C0067#define VF_INT_DYN_CTL0_INTENA_S 068#define VF_INT_DYN_CTL0_INTENA_M BIT(VF_INT_DYN_CTL0_INTENA_S)69#define VF_INT_DYN_CTL0_ITR_INDX_S 370#define VF_INT_DYN_CTL0_ITR_INDX_M GENMASK(4, 3)71#define VF_INT_DYN_CTLN(_INT) (0x00003800 + ((_INT) * 4))72#define VF_INT_DYN_CTLN_EXT(_INT) (0x00070000 + ((_INT) * 4))73#define VF_INT_DYN_CTLN_INTENA_S 074#define VF_INT_DYN_CTLN_INTENA_M BIT(VF_INT_DYN_CTLN_INTENA_S)75#define VF_INT_DYN_CTLN_CLEARPBA_S 176#define VF_INT_DYN_CTLN_CLEARPBA_M BIT(VF_INT_DYN_CTLN_CLEARPBA_S)77#define VF_INT_DYN_CTLN_SWINT_TRIG_S 278#define VF_INT_DYN_CTLN_SWINT_TRIG_M BIT(VF_INT_DYN_CTLN_SWINT_TRIG_S)79#define VF_INT_DYN_CTLN_ITR_INDX_S 380#define VF_INT_DYN_CTLN_ITR_INDX_M GENMASK(4, 3)81#define VF_INT_DYN_CTLN_INTERVAL_S 582#define VF_INT_DYN_CTLN_INTERVAL_M BIT(VF_INT_DYN_CTLN_INTERVAL_S)83#define VF_INT_DYN_CTLN_SW_ITR_INDX_ENA_S 2484#define VF_INT_DYN_CTLN_SW_ITR_INDX_ENA_M BIT(VF_INT_DYN_CTLN_SW_ITR_INDX_ENA_S)85#define VF_INT_DYN_CTLN_SW_ITR_INDX_S 2586#define VF_INT_DYN_CTLN_SW_ITR_INDX_M BIT(VF_INT_DYN_CTLN_SW_ITR_INDX_S)87#define VF_INT_DYN_CTLN_WB_ON_ITR_S 3088#define VF_INT_DYN_CTLN_WB_ON_ITR_M BIT(VF_INT_DYN_CTLN_WB_ON_ITR_S)89#define VF_INT_DYN_CTLN_INTENA_MSK_S 3190#define VF_INT_DYN_CTLN_INTENA_MSK_M BIT(VF_INT_DYN_CTLN_INTENA_MSK_S)91/* _ITR is ITR index, _INT is interrupt index, _itrn_indx_spacing is spacing92 * b/w itrn registers of the same vector93 */94#define VF_INT_ITR0(_ITR) (0x00004C00 + ((_ITR) * 4))95#define VF_INT_ITRN_ADDR(_ITR, _reg_start, _itrn_indx_spacing) \96 ((_reg_start) + ((_ITR) * (_itrn_indx_spacing)))97/* For VF with 16 vector support, itrn_reg_spacing is 0x4, itrn_indx_spacing98 * is 0x40 and base register offset is 0x0000280099 */100#define VF_INT_ITRN(_INT, _ITR) \101 (0x00002800 + ((_INT) * 4) + ((_ITR) * 0x40))102/* For VF with 64 vector support, itrn_reg_spacing is 0x4, itrn_indx_spacing103 * is 0x100 and base register offset is 0x00002C00104 */105#define VF_INT_ITRN_64(_INT, _ITR) \106 (0x00002C00 + ((_INT) * 4) + ((_ITR) * 0x100))107/* For VF with 2k vector support, itrn_reg_spacing is 0x4, itrn_indx_spacing108 * is 0x2000 and base register offset is 0x00072000109 */110#define VF_INT_ITRN_2K(_INT, _ITR) \111 (0x00072000 + ((_INT) * 4) + ((_ITR) * 0x2000))112#define VF_INT_ITRN_MAX_INDEX 2113#define VF_INT_ITRN_INTERVAL_S 0114#define VF_INT_ITRN_INTERVAL_M GENMASK(11, 0)115#define VF_INT_PBA_CLEAR 0x00008900116 117#define VF_INT_ICR0_ENA1 0x00005000118#define VF_INT_ICR0_ENA1_ADMINQ_S 30119#define VF_INT_ICR0_ENA1_ADMINQ_M BIT(VF_INT_ICR0_ENA1_ADMINQ_S)120#define VF_INT_ICR0_ENA1_RSVD_S 31121#define VF_INT_ICR01 0x00004800122#define VF_QF_HENA(_i) (0x0000C400 + ((_i) * 4))123#define VF_QF_HENA_MAX_INDX 1124#define VF_QF_HKEY(_i) (0x0000CC00 + ((_i) * 4))125#define VF_QF_HKEY_MAX_INDX 12126#define VF_QF_HLUT(_i) (0x0000D000 + ((_i) * 4))127#define VF_QF_HLUT_MAX_INDX 15128#endif129