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1/* SPDX-License-Identifier: GPL-2.0 */2/* Copyright(c) 2007 - 2018 Intel Corporation. */3 4#ifndef _E1000_I210_H_5#define _E1000_I210_H_6 7s32 igb_acquire_swfw_sync_i210(struct e1000_hw *hw, u16 mask);8void igb_release_swfw_sync_i210(struct e1000_hw *hw, u16 mask);9s32 igb_valid_led_default_i210(struct e1000_hw *hw, u16 *data);10s32 igb_read_invm_version(struct e1000_hw *hw,11 struct e1000_fw_version *invm_ver);12s32 igb_read_xmdio_reg(struct e1000_hw *hw, u16 addr, u8 dev_addr, u16 *data);13s32 igb_write_xmdio_reg(struct e1000_hw *hw, u16 addr, u8 dev_addr, u16 data);14s32 igb_init_nvm_params_i210(struct e1000_hw *hw);15bool igb_get_flash_presence_i210(struct e1000_hw *hw);16s32 igb_pll_workaround_i210(struct e1000_hw *hw);17s32 igb_get_cfg_done_i210(struct e1000_hw *hw);18 19#define E1000_STM_OPCODE 0xDB0020#define E1000_EEPROM_FLASH_SIZE_WORD 0x1121 22#define INVM_DWORD_TO_RECORD_TYPE(invm_dword) \23 (u8)((invm_dword) & 0x7)24#define INVM_DWORD_TO_WORD_ADDRESS(invm_dword) \25 (u8)(((invm_dword) & 0x0000FE00) >> 9)26#define INVM_DWORD_TO_WORD_DATA(invm_dword) \27 (u16)(((invm_dword) & 0xFFFF0000) >> 16)28 29enum E1000_INVM_STRUCTURE_TYPE {30 E1000_INVM_UNINITIALIZED_STRUCTURE = 0x00,31 E1000_INVM_WORD_AUTOLOAD_STRUCTURE = 0x01,32 E1000_INVM_CSR_AUTOLOAD_STRUCTURE = 0x02,33 E1000_INVM_PHY_REGISTER_AUTOLOAD_STRUCTURE = 0x03,34 E1000_INVM_RSA_KEY_SHA256_STRUCTURE = 0x04,35 E1000_INVM_INVALIDATED_STRUCTURE = 0x0F,36};37 38#define E1000_INVM_RSA_KEY_SHA256_DATA_SIZE_IN_DWORDS 839#define E1000_INVM_CSR_AUTOLOAD_DATA_SIZE_IN_DWORDS 140#define E1000_INVM_ULT_BYTES_SIZE 841#define E1000_INVM_RECORD_SIZE_IN_BYTES 442#define E1000_INVM_VER_FIELD_ONE 0x1FF843#define E1000_INVM_VER_FIELD_TWO 0x7FE00044#define E1000_INVM_IMGTYPE_FIELD 0x1F80000045 46#define E1000_INVM_MAJOR_MASK 0x3F047#define E1000_INVM_MINOR_MASK 0xF48#define E1000_INVM_MAJOR_SHIFT 449 50#define ID_LED_DEFAULT_I210 ((ID_LED_OFF1_ON2 << 8) | \51 (ID_LED_DEF1_DEF2 << 4) | \52 (ID_LED_OFF1_OFF2))53#define ID_LED_DEFAULT_I210_SERDES ((ID_LED_DEF1_DEF2 << 8) | \54 (ID_LED_DEF1_DEF2 << 4) | \55 (ID_LED_OFF1_ON2))56 57/* NVM offset defaults for i211 device */58#define NVM_INIT_CTRL_2_DEFAULT_I211 0X724359#define NVM_INIT_CTRL_4_DEFAULT_I211 0x00C160#define NVM_LED_1_CFG_DEFAULT_I211 0x018461#define NVM_LED_0_2_CFG_DEFAULT_I211 0x200C62 63/* PLL Defines */64#define E1000_PCI_PMCSR 0x4465#define E1000_PCI_PMCSR_D3 0x0366#define E1000_MAX_PLL_TRIES 567#define E1000_PHY_PLL_UNCONF 0xFF68#define E1000_PHY_PLL_FREQ_PAGE 0xFC69#define E1000_PHY_PLL_FREQ_REG 0x000E70#define E1000_INVM_DEFAULT_AL 0x202F71#define E1000_INVM_AUTOLOAD 0x0A72#define E1000_INVM_PLL_WO_VAL 0x001073 74#endif75