3500 lines · c
1// SPDX-License-Identifier: GPL-2.02/* Copyright(c) 2007 - 2018 Intel Corporation. */3 4/* ethtool support for igb */5 6#include <linux/vmalloc.h>7#include <linux/netdevice.h>8#include <linux/pci.h>9#include <linux/delay.h>10#include <linux/interrupt.h>11#include <linux/if_ether.h>12#include <linux/ethtool.h>13#include <linux/sched.h>14#include <linux/slab.h>15#include <linux/pm_runtime.h>16#include <linux/highmem.h>17#include <linux/mdio.h>18 19#include "igb.h"20 21struct igb_stats {22 char stat_string[ETH_GSTRING_LEN];23 int sizeof_stat;24 int stat_offset;25};26 27#define IGB_STAT(_name, _stat) { \28 .stat_string = _name, \29 .sizeof_stat = sizeof_field(struct igb_adapter, _stat), \30 .stat_offset = offsetof(struct igb_adapter, _stat) \31}32static const struct igb_stats igb_gstrings_stats[] = {33 IGB_STAT("rx_packets", stats.gprc),34 IGB_STAT("tx_packets", stats.gptc),35 IGB_STAT("rx_bytes", stats.gorc),36 IGB_STAT("tx_bytes", stats.gotc),37 IGB_STAT("rx_broadcast", stats.bprc),38 IGB_STAT("tx_broadcast", stats.bptc),39 IGB_STAT("rx_multicast", stats.mprc),40 IGB_STAT("tx_multicast", stats.mptc),41 IGB_STAT("multicast", stats.mprc),42 IGB_STAT("collisions", stats.colc),43 IGB_STAT("rx_crc_errors", stats.crcerrs),44 IGB_STAT("rx_no_buffer_count", stats.rnbc),45 IGB_STAT("rx_missed_errors", stats.mpc),46 IGB_STAT("tx_aborted_errors", stats.ecol),47 IGB_STAT("tx_carrier_errors", stats.tncrs),48 IGB_STAT("tx_window_errors", stats.latecol),49 IGB_STAT("tx_abort_late_coll", stats.latecol),50 IGB_STAT("tx_deferred_ok", stats.dc),51 IGB_STAT("tx_single_coll_ok", stats.scc),52 IGB_STAT("tx_multi_coll_ok", stats.mcc),53 IGB_STAT("tx_timeout_count", tx_timeout_count),54 IGB_STAT("rx_long_length_errors", stats.roc),55 IGB_STAT("rx_short_length_errors", stats.ruc),56 IGB_STAT("rx_align_errors", stats.algnerrc),57 IGB_STAT("tx_tcp_seg_good", stats.tsctc),58 IGB_STAT("tx_tcp_seg_failed", stats.tsctfc),59 IGB_STAT("rx_flow_control_xon", stats.xonrxc),60 IGB_STAT("rx_flow_control_xoff", stats.xoffrxc),61 IGB_STAT("tx_flow_control_xon", stats.xontxc),62 IGB_STAT("tx_flow_control_xoff", stats.xofftxc),63 IGB_STAT("rx_long_byte_count", stats.gorc),64 IGB_STAT("tx_dma_out_of_sync", stats.doosync),65 IGB_STAT("tx_smbus", stats.mgptc),66 IGB_STAT("rx_smbus", stats.mgprc),67 IGB_STAT("dropped_smbus", stats.mgpdc),68 IGB_STAT("os2bmc_rx_by_bmc", stats.o2bgptc),69 IGB_STAT("os2bmc_tx_by_bmc", stats.b2ospc),70 IGB_STAT("os2bmc_tx_by_host", stats.o2bspc),71 IGB_STAT("os2bmc_rx_by_host", stats.b2ogprc),72 IGB_STAT("tx_hwtstamp_timeouts", tx_hwtstamp_timeouts),73 IGB_STAT("tx_hwtstamp_skipped", tx_hwtstamp_skipped),74 IGB_STAT("rx_hwtstamp_cleared", rx_hwtstamp_cleared),75};76 77#define IGB_NETDEV_STAT(_net_stat) { \78 .stat_string = __stringify(_net_stat), \79 .sizeof_stat = sizeof_field(struct rtnl_link_stats64, _net_stat), \80 .stat_offset = offsetof(struct rtnl_link_stats64, _net_stat) \81}82static const struct igb_stats igb_gstrings_net_stats[] = {83 IGB_NETDEV_STAT(rx_errors),84 IGB_NETDEV_STAT(tx_errors),85 IGB_NETDEV_STAT(tx_dropped),86 IGB_NETDEV_STAT(rx_length_errors),87 IGB_NETDEV_STAT(rx_over_errors),88 IGB_NETDEV_STAT(rx_frame_errors),89 IGB_NETDEV_STAT(rx_fifo_errors),90 IGB_NETDEV_STAT(tx_fifo_errors),91 IGB_NETDEV_STAT(tx_heartbeat_errors)92};93 94#define IGB_GLOBAL_STATS_LEN \95 (sizeof(igb_gstrings_stats) / sizeof(struct igb_stats))96#define IGB_NETDEV_STATS_LEN \97 (sizeof(igb_gstrings_net_stats) / sizeof(struct igb_stats))98#define IGB_RX_QUEUE_STATS_LEN \99 (sizeof(struct igb_rx_queue_stats) / sizeof(u64))100 101#define IGB_TX_QUEUE_STATS_LEN 3 /* packets, bytes, restart_queue */102 103#define IGB_QUEUE_STATS_LEN \104 ((((struct igb_adapter *)netdev_priv(netdev))->num_rx_queues * \105 IGB_RX_QUEUE_STATS_LEN) + \106 (((struct igb_adapter *)netdev_priv(netdev))->num_tx_queues * \107 IGB_TX_QUEUE_STATS_LEN))108#define IGB_STATS_LEN \109 (IGB_GLOBAL_STATS_LEN + IGB_NETDEV_STATS_LEN + IGB_QUEUE_STATS_LEN)110 111enum igb_diagnostics_results {112 TEST_REG = 0,113 TEST_EEP,114 TEST_IRQ,115 TEST_LOOP,116 TEST_LINK117};118 119static const char igb_gstrings_test[][ETH_GSTRING_LEN] = {120 [TEST_REG] = "Register test (offline)",121 [TEST_EEP] = "Eeprom test (offline)",122 [TEST_IRQ] = "Interrupt test (offline)",123 [TEST_LOOP] = "Loopback test (offline)",124 [TEST_LINK] = "Link test (on/offline)"125};126#define IGB_TEST_LEN (sizeof(igb_gstrings_test) / ETH_GSTRING_LEN)127 128static const char igb_priv_flags_strings[][ETH_GSTRING_LEN] = {129#define IGB_PRIV_FLAGS_LEGACY_RX BIT(0)130 "legacy-rx",131};132 133#define IGB_PRIV_FLAGS_STR_LEN ARRAY_SIZE(igb_priv_flags_strings)134 135static int igb_get_link_ksettings(struct net_device *netdev,136 struct ethtool_link_ksettings *cmd)137{138 struct igb_adapter *adapter = netdev_priv(netdev);139 struct e1000_hw *hw = &adapter->hw;140 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;141 struct e1000_sfp_flags *eth_flags = &dev_spec->eth_flags;142 u32 status;143 u32 speed;144 u32 supported, advertising;145 146 status = pm_runtime_suspended(&adapter->pdev->dev) ?147 0 : rd32(E1000_STATUS);148 if (hw->phy.media_type == e1000_media_type_copper) {149 150 supported = (SUPPORTED_10baseT_Half |151 SUPPORTED_10baseT_Full |152 SUPPORTED_100baseT_Half |153 SUPPORTED_100baseT_Full |154 SUPPORTED_1000baseT_Full|155 SUPPORTED_Autoneg |156 SUPPORTED_TP |157 SUPPORTED_Pause);158 advertising = ADVERTISED_TP;159 160 if (hw->mac.autoneg == 1) {161 advertising |= ADVERTISED_Autoneg;162 /* the e1000 autoneg seems to match ethtool nicely */163 advertising |= hw->phy.autoneg_advertised;164 }165 166 cmd->base.port = PORT_TP;167 cmd->base.phy_address = hw->phy.addr;168 } else {169 supported = (SUPPORTED_FIBRE |170 SUPPORTED_1000baseKX_Full |171 SUPPORTED_Autoneg |172 SUPPORTED_Pause);173 advertising = (ADVERTISED_FIBRE |174 ADVERTISED_1000baseKX_Full);175 if (hw->mac.type == e1000_i354) {176 if ((hw->device_id ==177 E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) &&178 !(status & E1000_STATUS_2P5_SKU_OVER)) {179 supported |= SUPPORTED_2500baseX_Full;180 supported &= ~SUPPORTED_1000baseKX_Full;181 advertising |= ADVERTISED_2500baseX_Full;182 advertising &= ~ADVERTISED_1000baseKX_Full;183 }184 }185 if (eth_flags->e100_base_fx || eth_flags->e100_base_lx) {186 supported |= SUPPORTED_100baseT_Full;187 advertising |= ADVERTISED_100baseT_Full;188 }189 if (hw->mac.autoneg == 1)190 advertising |= ADVERTISED_Autoneg;191 192 cmd->base.port = PORT_FIBRE;193 }194 if (hw->mac.autoneg != 1)195 advertising &= ~(ADVERTISED_Pause |196 ADVERTISED_Asym_Pause);197 198 switch (hw->fc.requested_mode) {199 case e1000_fc_full:200 advertising |= ADVERTISED_Pause;201 break;202 case e1000_fc_rx_pause:203 advertising |= (ADVERTISED_Pause |204 ADVERTISED_Asym_Pause);205 break;206 case e1000_fc_tx_pause:207 advertising |= ADVERTISED_Asym_Pause;208 break;209 default:210 advertising &= ~(ADVERTISED_Pause |211 ADVERTISED_Asym_Pause);212 }213 if (status & E1000_STATUS_LU) {214 if ((status & E1000_STATUS_2P5_SKU) &&215 !(status & E1000_STATUS_2P5_SKU_OVER)) {216 speed = SPEED_2500;217 } else if (status & E1000_STATUS_SPEED_1000) {218 speed = SPEED_1000;219 } else if (status & E1000_STATUS_SPEED_100) {220 speed = SPEED_100;221 } else {222 speed = SPEED_10;223 }224 if ((status & E1000_STATUS_FD) ||225 hw->phy.media_type != e1000_media_type_copper)226 cmd->base.duplex = DUPLEX_FULL;227 else228 cmd->base.duplex = DUPLEX_HALF;229 } else {230 speed = SPEED_UNKNOWN;231 cmd->base.duplex = DUPLEX_UNKNOWN;232 }233 cmd->base.speed = speed;234 if ((hw->phy.media_type == e1000_media_type_fiber) ||235 hw->mac.autoneg)236 cmd->base.autoneg = AUTONEG_ENABLE;237 else238 cmd->base.autoneg = AUTONEG_DISABLE;239 240 /* MDI-X => 2; MDI =>1; Invalid =>0 */241 if (hw->phy.media_type == e1000_media_type_copper)242 cmd->base.eth_tp_mdix = hw->phy.is_mdix ? ETH_TP_MDI_X :243 ETH_TP_MDI;244 else245 cmd->base.eth_tp_mdix = ETH_TP_MDI_INVALID;246 247 if (hw->phy.mdix == AUTO_ALL_MODES)248 cmd->base.eth_tp_mdix_ctrl = ETH_TP_MDI_AUTO;249 else250 cmd->base.eth_tp_mdix_ctrl = hw->phy.mdix;251 252 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,253 supported);254 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,255 advertising);256 257 return 0;258}259 260static int igb_set_link_ksettings(struct net_device *netdev,261 const struct ethtool_link_ksettings *cmd)262{263 struct igb_adapter *adapter = netdev_priv(netdev);264 struct e1000_hw *hw = &adapter->hw;265 u32 advertising;266 267 /* When SoL/IDER sessions are active, autoneg/speed/duplex268 * cannot be changed269 */270 if (igb_check_reset_block(hw)) {271 dev_err(&adapter->pdev->dev,272 "Cannot change link characteristics when SoL/IDER is active.\n");273 return -EINVAL;274 }275 276 /* MDI setting is only allowed when autoneg enabled because277 * some hardware doesn't allow MDI setting when speed or278 * duplex is forced.279 */280 if (cmd->base.eth_tp_mdix_ctrl) {281 if (hw->phy.media_type != e1000_media_type_copper)282 return -EOPNOTSUPP;283 284 if ((cmd->base.eth_tp_mdix_ctrl != ETH_TP_MDI_AUTO) &&285 (cmd->base.autoneg != AUTONEG_ENABLE)) {286 dev_err(&adapter->pdev->dev, "forcing MDI/MDI-X state is not supported when link speed and/or duplex are forced\n");287 return -EINVAL;288 }289 }290 291 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))292 usleep_range(1000, 2000);293 294 ethtool_convert_link_mode_to_legacy_u32(&advertising,295 cmd->link_modes.advertising);296 297 if (cmd->base.autoneg == AUTONEG_ENABLE) {298 hw->mac.autoneg = 1;299 if (hw->phy.media_type == e1000_media_type_fiber) {300 hw->phy.autoneg_advertised = advertising |301 ADVERTISED_FIBRE |302 ADVERTISED_Autoneg;303 switch (adapter->link_speed) {304 case SPEED_2500:305 hw->phy.autoneg_advertised =306 ADVERTISED_2500baseX_Full;307 break;308 case SPEED_1000:309 hw->phy.autoneg_advertised =310 ADVERTISED_1000baseT_Full;311 break;312 case SPEED_100:313 hw->phy.autoneg_advertised =314 ADVERTISED_100baseT_Full;315 break;316 default:317 break;318 }319 } else {320 hw->phy.autoneg_advertised = advertising |321 ADVERTISED_TP |322 ADVERTISED_Autoneg;323 }324 advertising = hw->phy.autoneg_advertised;325 if (adapter->fc_autoneg)326 hw->fc.requested_mode = e1000_fc_default;327 } else {328 u32 speed = cmd->base.speed;329 /* calling this overrides forced MDI setting */330 if (igb_set_spd_dplx(adapter, speed, cmd->base.duplex)) {331 clear_bit(__IGB_RESETTING, &adapter->state);332 return -EINVAL;333 }334 }335 336 /* MDI-X => 2; MDI => 1; Auto => 3 */337 if (cmd->base.eth_tp_mdix_ctrl) {338 /* fix up the value for auto (3 => 0) as zero is mapped339 * internally to auto340 */341 if (cmd->base.eth_tp_mdix_ctrl == ETH_TP_MDI_AUTO)342 hw->phy.mdix = AUTO_ALL_MODES;343 else344 hw->phy.mdix = cmd->base.eth_tp_mdix_ctrl;345 }346 347 /* reset the link */348 if (netif_running(adapter->netdev)) {349 igb_down(adapter);350 igb_up(adapter);351 } else352 igb_reset(adapter);353 354 clear_bit(__IGB_RESETTING, &adapter->state);355 return 0;356}357 358static u32 igb_get_link(struct net_device *netdev)359{360 struct igb_adapter *adapter = netdev_priv(netdev);361 struct e1000_mac_info *mac = &adapter->hw.mac;362 363 /* If the link is not reported up to netdev, interrupts are disabled,364 * and so the physical link state may have changed since we last365 * looked. Set get_link_status to make sure that the true link366 * state is interrogated, rather than pulling a cached and possibly367 * stale link state from the driver.368 */369 if (!netif_carrier_ok(netdev))370 mac->get_link_status = 1;371 372 return igb_has_link(adapter);373}374 375static void igb_get_pauseparam(struct net_device *netdev,376 struct ethtool_pauseparam *pause)377{378 struct igb_adapter *adapter = netdev_priv(netdev);379 struct e1000_hw *hw = &adapter->hw;380 381 pause->autoneg =382 (adapter->fc_autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE);383 384 if (hw->fc.current_mode == e1000_fc_rx_pause)385 pause->rx_pause = 1;386 else if (hw->fc.current_mode == e1000_fc_tx_pause)387 pause->tx_pause = 1;388 else if (hw->fc.current_mode == e1000_fc_full) {389 pause->rx_pause = 1;390 pause->tx_pause = 1;391 }392}393 394static int igb_set_pauseparam(struct net_device *netdev,395 struct ethtool_pauseparam *pause)396{397 struct igb_adapter *adapter = netdev_priv(netdev);398 struct e1000_hw *hw = &adapter->hw;399 int retval = 0;400 int i;401 402 /* 100basefx does not support setting link flow control */403 if (hw->dev_spec._82575.eth_flags.e100_base_fx)404 return -EINVAL;405 406 adapter->fc_autoneg = pause->autoneg;407 408 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))409 usleep_range(1000, 2000);410 411 if (adapter->fc_autoneg == AUTONEG_ENABLE) {412 hw->fc.requested_mode = e1000_fc_default;413 if (netif_running(adapter->netdev)) {414 igb_down(adapter);415 igb_up(adapter);416 } else {417 igb_reset(adapter);418 }419 } else {420 if (pause->rx_pause && pause->tx_pause)421 hw->fc.requested_mode = e1000_fc_full;422 else if (pause->rx_pause && !pause->tx_pause)423 hw->fc.requested_mode = e1000_fc_rx_pause;424 else if (!pause->rx_pause && pause->tx_pause)425 hw->fc.requested_mode = e1000_fc_tx_pause;426 else if (!pause->rx_pause && !pause->tx_pause)427 hw->fc.requested_mode = e1000_fc_none;428 429 hw->fc.current_mode = hw->fc.requested_mode;430 431 retval = ((hw->phy.media_type == e1000_media_type_copper) ?432 igb_force_mac_fc(hw) : igb_setup_link(hw));433 434 /* Make sure SRRCTL considers new fc settings for each ring */435 for (i = 0; i < adapter->num_rx_queues; i++) {436 struct igb_ring *ring = adapter->rx_ring[i];437 438 igb_setup_srrctl(adapter, ring);439 }440 }441 442 clear_bit(__IGB_RESETTING, &adapter->state);443 return retval;444}445 446static u32 igb_get_msglevel(struct net_device *netdev)447{448 struct igb_adapter *adapter = netdev_priv(netdev);449 return adapter->msg_enable;450}451 452static void igb_set_msglevel(struct net_device *netdev, u32 data)453{454 struct igb_adapter *adapter = netdev_priv(netdev);455 adapter->msg_enable = data;456}457 458static int igb_get_regs_len(struct net_device *netdev)459{460#define IGB_REGS_LEN 740461 return IGB_REGS_LEN * sizeof(u32);462}463 464static void igb_get_regs(struct net_device *netdev,465 struct ethtool_regs *regs, void *p)466{467 struct igb_adapter *adapter = netdev_priv(netdev);468 struct e1000_hw *hw = &adapter->hw;469 u32 *regs_buff = p;470 u8 i;471 472 memset(p, 0, IGB_REGS_LEN * sizeof(u32));473 474 regs->version = (1u << 24) | (hw->revision_id << 16) | hw->device_id;475 476 /* General Registers */477 regs_buff[0] = rd32(E1000_CTRL);478 regs_buff[1] = rd32(E1000_STATUS);479 regs_buff[2] = rd32(E1000_CTRL_EXT);480 regs_buff[3] = rd32(E1000_MDIC);481 regs_buff[4] = rd32(E1000_SCTL);482 regs_buff[5] = rd32(E1000_CONNSW);483 regs_buff[6] = rd32(E1000_VET);484 regs_buff[7] = rd32(E1000_LEDCTL);485 regs_buff[8] = rd32(E1000_PBA);486 regs_buff[9] = rd32(E1000_PBS);487 regs_buff[10] = rd32(E1000_FRTIMER);488 regs_buff[11] = rd32(E1000_TCPTIMER);489 490 /* NVM Register */491 regs_buff[12] = rd32(E1000_EECD);492 493 /* Interrupt */494 /* Reading EICS for EICR because they read the495 * same but EICS does not clear on read496 */497 regs_buff[13] = rd32(E1000_EICS);498 regs_buff[14] = rd32(E1000_EICS);499 regs_buff[15] = rd32(E1000_EIMS);500 regs_buff[16] = rd32(E1000_EIMC);501 regs_buff[17] = rd32(E1000_EIAC);502 regs_buff[18] = rd32(E1000_EIAM);503 /* Reading ICS for ICR because they read the504 * same but ICS does not clear on read505 */506 regs_buff[19] = rd32(E1000_ICS);507 regs_buff[20] = rd32(E1000_ICS);508 regs_buff[21] = rd32(E1000_IMS);509 regs_buff[22] = rd32(E1000_IMC);510 regs_buff[23] = rd32(E1000_IAC);511 regs_buff[24] = rd32(E1000_IAM);512 regs_buff[25] = rd32(E1000_IMIRVP);513 514 /* Flow Control */515 regs_buff[26] = rd32(E1000_FCAL);516 regs_buff[27] = rd32(E1000_FCAH);517 regs_buff[28] = rd32(E1000_FCTTV);518 regs_buff[29] = rd32(E1000_FCRTL);519 regs_buff[30] = rd32(E1000_FCRTH);520 regs_buff[31] = rd32(E1000_FCRTV);521 522 /* Receive */523 regs_buff[32] = rd32(E1000_RCTL);524 regs_buff[33] = rd32(E1000_RXCSUM);525 regs_buff[34] = rd32(E1000_RLPML);526 regs_buff[35] = rd32(E1000_RFCTL);527 regs_buff[36] = rd32(E1000_MRQC);528 regs_buff[37] = rd32(E1000_VT_CTL);529 530 /* Transmit */531 regs_buff[38] = rd32(E1000_TCTL);532 regs_buff[39] = rd32(E1000_TCTL_EXT);533 regs_buff[40] = rd32(E1000_TIPG);534 regs_buff[41] = rd32(E1000_DTXCTL);535 536 /* Wake Up */537 regs_buff[42] = rd32(E1000_WUC);538 regs_buff[43] = rd32(E1000_WUFC);539 regs_buff[44] = rd32(E1000_WUS);540 regs_buff[45] = rd32(E1000_IPAV);541 regs_buff[46] = rd32(E1000_WUPL);542 543 /* MAC */544 regs_buff[47] = rd32(E1000_PCS_CFG0);545 regs_buff[48] = rd32(E1000_PCS_LCTL);546 regs_buff[49] = rd32(E1000_PCS_LSTAT);547 regs_buff[50] = rd32(E1000_PCS_ANADV);548 regs_buff[51] = rd32(E1000_PCS_LPAB);549 regs_buff[52] = rd32(E1000_PCS_NPTX);550 regs_buff[53] = rd32(E1000_PCS_LPABNP);551 552 /* Statistics */553 regs_buff[54] = adapter->stats.crcerrs;554 regs_buff[55] = adapter->stats.algnerrc;555 regs_buff[56] = adapter->stats.symerrs;556 regs_buff[57] = adapter->stats.rxerrc;557 regs_buff[58] = adapter->stats.mpc;558 regs_buff[59] = adapter->stats.scc;559 regs_buff[60] = adapter->stats.ecol;560 regs_buff[61] = adapter->stats.mcc;561 regs_buff[62] = adapter->stats.latecol;562 regs_buff[63] = adapter->stats.colc;563 regs_buff[64] = adapter->stats.dc;564 regs_buff[65] = adapter->stats.tncrs;565 regs_buff[66] = adapter->stats.sec;566 regs_buff[67] = adapter->stats.htdpmc;567 regs_buff[68] = adapter->stats.rlec;568 regs_buff[69] = adapter->stats.xonrxc;569 regs_buff[70] = adapter->stats.xontxc;570 regs_buff[71] = adapter->stats.xoffrxc;571 regs_buff[72] = adapter->stats.xofftxc;572 regs_buff[73] = adapter->stats.fcruc;573 regs_buff[74] = adapter->stats.prc64;574 regs_buff[75] = adapter->stats.prc127;575 regs_buff[76] = adapter->stats.prc255;576 regs_buff[77] = adapter->stats.prc511;577 regs_buff[78] = adapter->stats.prc1023;578 regs_buff[79] = adapter->stats.prc1522;579 regs_buff[80] = adapter->stats.gprc;580 regs_buff[81] = adapter->stats.bprc;581 regs_buff[82] = adapter->stats.mprc;582 regs_buff[83] = adapter->stats.gptc;583 regs_buff[84] = adapter->stats.gorc;584 regs_buff[86] = adapter->stats.gotc;585 regs_buff[88] = adapter->stats.rnbc;586 regs_buff[89] = adapter->stats.ruc;587 regs_buff[90] = adapter->stats.rfc;588 regs_buff[91] = adapter->stats.roc;589 regs_buff[92] = adapter->stats.rjc;590 regs_buff[93] = adapter->stats.mgprc;591 regs_buff[94] = adapter->stats.mgpdc;592 regs_buff[95] = adapter->stats.mgptc;593 regs_buff[96] = adapter->stats.tor;594 regs_buff[98] = adapter->stats.tot;595 regs_buff[100] = adapter->stats.tpr;596 regs_buff[101] = adapter->stats.tpt;597 regs_buff[102] = adapter->stats.ptc64;598 regs_buff[103] = adapter->stats.ptc127;599 regs_buff[104] = adapter->stats.ptc255;600 regs_buff[105] = adapter->stats.ptc511;601 regs_buff[106] = adapter->stats.ptc1023;602 regs_buff[107] = adapter->stats.ptc1522;603 regs_buff[108] = adapter->stats.mptc;604 regs_buff[109] = adapter->stats.bptc;605 regs_buff[110] = adapter->stats.tsctc;606 regs_buff[111] = adapter->stats.iac;607 regs_buff[112] = adapter->stats.rpthc;608 regs_buff[113] = adapter->stats.hgptc;609 regs_buff[114] = adapter->stats.hgorc;610 regs_buff[116] = adapter->stats.hgotc;611 regs_buff[118] = adapter->stats.lenerrs;612 regs_buff[119] = adapter->stats.scvpc;613 regs_buff[120] = adapter->stats.hrmpc;614 615 for (i = 0; i < 4; i++)616 regs_buff[121 + i] = rd32(E1000_SRRCTL(i));617 for (i = 0; i < 4; i++)618 regs_buff[125 + i] = rd32(E1000_PSRTYPE(i));619 for (i = 0; i < 4; i++)620 regs_buff[129 + i] = rd32(E1000_RDBAL(i));621 for (i = 0; i < 4; i++)622 regs_buff[133 + i] = rd32(E1000_RDBAH(i));623 for (i = 0; i < 4; i++)624 regs_buff[137 + i] = rd32(E1000_RDLEN(i));625 for (i = 0; i < 4; i++)626 regs_buff[141 + i] = rd32(E1000_RDH(i));627 for (i = 0; i < 4; i++)628 regs_buff[145 + i] = rd32(E1000_RDT(i));629 for (i = 0; i < 4; i++)630 regs_buff[149 + i] = rd32(E1000_RXDCTL(i));631 632 for (i = 0; i < 10; i++)633 regs_buff[153 + i] = rd32(E1000_EITR(i));634 for (i = 0; i < 8; i++)635 regs_buff[163 + i] = rd32(E1000_IMIR(i));636 for (i = 0; i < 8; i++)637 regs_buff[171 + i] = rd32(E1000_IMIREXT(i));638 for (i = 0; i < 16; i++)639 regs_buff[179 + i] = rd32(E1000_RAL(i));640 for (i = 0; i < 16; i++)641 regs_buff[195 + i] = rd32(E1000_RAH(i));642 643 for (i = 0; i < 4; i++)644 regs_buff[211 + i] = rd32(E1000_TDBAL(i));645 for (i = 0; i < 4; i++)646 regs_buff[215 + i] = rd32(E1000_TDBAH(i));647 for (i = 0; i < 4; i++)648 regs_buff[219 + i] = rd32(E1000_TDLEN(i));649 for (i = 0; i < 4; i++)650 regs_buff[223 + i] = rd32(E1000_TDH(i));651 for (i = 0; i < 4; i++)652 regs_buff[227 + i] = rd32(E1000_TDT(i));653 for (i = 0; i < 4; i++)654 regs_buff[231 + i] = rd32(E1000_TXDCTL(i));655 for (i = 0; i < 4; i++)656 regs_buff[235 + i] = rd32(E1000_TDWBAL(i));657 for (i = 0; i < 4; i++)658 regs_buff[239 + i] = rd32(E1000_TDWBAH(i));659 for (i = 0; i < 4; i++)660 regs_buff[243 + i] = rd32(E1000_DCA_TXCTRL(i));661 662 for (i = 0; i < 4; i++)663 regs_buff[247 + i] = rd32(E1000_IP4AT_REG(i));664 for (i = 0; i < 4; i++)665 regs_buff[251 + i] = rd32(E1000_IP6AT_REG(i));666 for (i = 0; i < 32; i++)667 regs_buff[255 + i] = rd32(E1000_WUPM_REG(i));668 for (i = 0; i < 128; i++)669 regs_buff[287 + i] = rd32(E1000_FFMT_REG(i));670 for (i = 0; i < 128; i++)671 regs_buff[415 + i] = rd32(E1000_FFVT_REG(i));672 for (i = 0; i < 4; i++)673 regs_buff[543 + i] = rd32(E1000_FFLT_REG(i));674 675 regs_buff[547] = rd32(E1000_TDFH);676 regs_buff[548] = rd32(E1000_TDFT);677 regs_buff[549] = rd32(E1000_TDFHS);678 regs_buff[550] = rd32(E1000_TDFPC);679 680 if (hw->mac.type > e1000_82580) {681 regs_buff[551] = adapter->stats.o2bgptc;682 regs_buff[552] = adapter->stats.b2ospc;683 regs_buff[553] = adapter->stats.o2bspc;684 regs_buff[554] = adapter->stats.b2ogprc;685 }686 687 if (hw->mac.type == e1000_82576) {688 for (i = 0; i < 12; i++)689 regs_buff[555 + i] = rd32(E1000_SRRCTL(i + 4));690 for (i = 0; i < 4; i++)691 regs_buff[567 + i] = rd32(E1000_PSRTYPE(i + 4));692 for (i = 0; i < 12; i++)693 regs_buff[571 + i] = rd32(E1000_RDBAL(i + 4));694 for (i = 0; i < 12; i++)695 regs_buff[583 + i] = rd32(E1000_RDBAH(i + 4));696 for (i = 0; i < 12; i++)697 regs_buff[595 + i] = rd32(E1000_RDLEN(i + 4));698 for (i = 0; i < 12; i++)699 regs_buff[607 + i] = rd32(E1000_RDH(i + 4));700 for (i = 0; i < 12; i++)701 regs_buff[619 + i] = rd32(E1000_RDT(i + 4));702 for (i = 0; i < 12; i++)703 regs_buff[631 + i] = rd32(E1000_RXDCTL(i + 4));704 705 for (i = 0; i < 12; i++)706 regs_buff[643 + i] = rd32(E1000_TDBAL(i + 4));707 for (i = 0; i < 12; i++)708 regs_buff[655 + i] = rd32(E1000_TDBAH(i + 4));709 for (i = 0; i < 12; i++)710 regs_buff[667 + i] = rd32(E1000_TDLEN(i + 4));711 for (i = 0; i < 12; i++)712 regs_buff[679 + i] = rd32(E1000_TDH(i + 4));713 for (i = 0; i < 12; i++)714 regs_buff[691 + i] = rd32(E1000_TDT(i + 4));715 for (i = 0; i < 12; i++)716 regs_buff[703 + i] = rd32(E1000_TXDCTL(i + 4));717 for (i = 0; i < 12; i++)718 regs_buff[715 + i] = rd32(E1000_TDWBAL(i + 4));719 for (i = 0; i < 12; i++)720 regs_buff[727 + i] = rd32(E1000_TDWBAH(i + 4));721 }722 723 if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211)724 regs_buff[739] = rd32(E1000_I210_RR2DCDELAY);725}726 727static int igb_get_eeprom_len(struct net_device *netdev)728{729 struct igb_adapter *adapter = netdev_priv(netdev);730 return adapter->hw.nvm.word_size * 2;731}732 733static int igb_get_eeprom(struct net_device *netdev,734 struct ethtool_eeprom *eeprom, u8 *bytes)735{736 struct igb_adapter *adapter = netdev_priv(netdev);737 struct e1000_hw *hw = &adapter->hw;738 u16 *eeprom_buff;739 int first_word, last_word;740 int ret_val = 0;741 u16 i;742 743 if (eeprom->len == 0)744 return -EINVAL;745 746 eeprom->magic = hw->vendor_id | (hw->device_id << 16);747 748 first_word = eeprom->offset >> 1;749 last_word = (eeprom->offset + eeprom->len - 1) >> 1;750 751 eeprom_buff = kmalloc_array(last_word - first_word + 1, sizeof(u16),752 GFP_KERNEL);753 if (!eeprom_buff)754 return -ENOMEM;755 756 if (hw->nvm.type == e1000_nvm_eeprom_spi)757 ret_val = hw->nvm.ops.read(hw, first_word,758 last_word - first_word + 1,759 eeprom_buff);760 else {761 for (i = 0; i < last_word - first_word + 1; i++) {762 ret_val = hw->nvm.ops.read(hw, first_word + i, 1,763 &eeprom_buff[i]);764 if (ret_val)765 break;766 }767 }768 769 /* Device's eeprom is always little-endian, word addressable */770 for (i = 0; i < last_word - first_word + 1; i++)771 le16_to_cpus(&eeprom_buff[i]);772 773 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1),774 eeprom->len);775 kfree(eeprom_buff);776 777 return ret_val;778}779 780static int igb_set_eeprom(struct net_device *netdev,781 struct ethtool_eeprom *eeprom, u8 *bytes)782{783 struct igb_adapter *adapter = netdev_priv(netdev);784 struct e1000_hw *hw = &adapter->hw;785 u16 *eeprom_buff;786 void *ptr;787 int max_len, first_word, last_word, ret_val = 0;788 u16 i;789 790 if (eeprom->len == 0)791 return -EOPNOTSUPP;792 793 if ((hw->mac.type >= e1000_i210) &&794 !igb_get_flash_presence_i210(hw)) {795 return -EOPNOTSUPP;796 }797 798 if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16)))799 return -EFAULT;800 801 max_len = hw->nvm.word_size * 2;802 803 first_word = eeprom->offset >> 1;804 last_word = (eeprom->offset + eeprom->len - 1) >> 1;805 eeprom_buff = kmalloc(max_len, GFP_KERNEL);806 if (!eeprom_buff)807 return -ENOMEM;808 809 ptr = (void *)eeprom_buff;810 811 if (eeprom->offset & 1) {812 /* need read/modify/write of first changed EEPROM word813 * only the second byte of the word is being modified814 */815 ret_val = hw->nvm.ops.read(hw, first_word, 1,816 &eeprom_buff[0]);817 ptr++;818 }819 if (((eeprom->offset + eeprom->len) & 1) && (ret_val == 0)) {820 /* need read/modify/write of last changed EEPROM word821 * only the first byte of the word is being modified822 */823 ret_val = hw->nvm.ops.read(hw, last_word, 1,824 &eeprom_buff[last_word - first_word]);825 if (ret_val)826 goto out;827 }828 829 /* Device's eeprom is always little-endian, word addressable */830 for (i = 0; i < last_word - first_word + 1; i++)831 le16_to_cpus(&eeprom_buff[i]);832 833 memcpy(ptr, bytes, eeprom->len);834 835 for (i = 0; i < last_word - first_word + 1; i++)836 cpu_to_le16s(&eeprom_buff[i]);837 838 ret_val = hw->nvm.ops.write(hw, first_word,839 last_word - first_word + 1, eeprom_buff);840 841 /* Update the checksum if nvm write succeeded */842 if (ret_val == 0)843 hw->nvm.ops.update(hw);844 845 igb_set_fw_version(adapter);846out:847 kfree(eeprom_buff);848 return ret_val;849}850 851static void igb_get_drvinfo(struct net_device *netdev,852 struct ethtool_drvinfo *drvinfo)853{854 struct igb_adapter *adapter = netdev_priv(netdev);855 856 strscpy(drvinfo->driver, igb_driver_name, sizeof(drvinfo->driver));857 858 /* EEPROM image version # is reported as firmware version # for859 * 82575 controllers860 */861 strscpy(drvinfo->fw_version, adapter->fw_version,862 sizeof(drvinfo->fw_version));863 strscpy(drvinfo->bus_info, pci_name(adapter->pdev),864 sizeof(drvinfo->bus_info));865 866 drvinfo->n_priv_flags = IGB_PRIV_FLAGS_STR_LEN;867}868 869static void igb_get_ringparam(struct net_device *netdev,870 struct ethtool_ringparam *ring,871 struct kernel_ethtool_ringparam *kernel_ring,872 struct netlink_ext_ack *extack)873{874 struct igb_adapter *adapter = netdev_priv(netdev);875 876 ring->rx_max_pending = IGB_MAX_RXD;877 ring->tx_max_pending = IGB_MAX_TXD;878 ring->rx_pending = adapter->rx_ring_count;879 ring->tx_pending = adapter->tx_ring_count;880}881 882static int igb_set_ringparam(struct net_device *netdev,883 struct ethtool_ringparam *ring,884 struct kernel_ethtool_ringparam *kernel_ring,885 struct netlink_ext_ack *extack)886{887 struct igb_adapter *adapter = netdev_priv(netdev);888 struct igb_ring *temp_ring;889 int i, err = 0;890 u16 new_rx_count, new_tx_count;891 892 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))893 return -EINVAL;894 895 new_rx_count = min_t(u32, ring->rx_pending, IGB_MAX_RXD);896 new_rx_count = max_t(u16, new_rx_count, IGB_MIN_RXD);897 new_rx_count = ALIGN(new_rx_count, REQ_RX_DESCRIPTOR_MULTIPLE);898 899 new_tx_count = min_t(u32, ring->tx_pending, IGB_MAX_TXD);900 new_tx_count = max_t(u16, new_tx_count, IGB_MIN_TXD);901 new_tx_count = ALIGN(new_tx_count, REQ_TX_DESCRIPTOR_MULTIPLE);902 903 if ((new_tx_count == adapter->tx_ring_count) &&904 (new_rx_count == adapter->rx_ring_count)) {905 /* nothing to do */906 return 0;907 }908 909 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))910 usleep_range(1000, 2000);911 912 if (!netif_running(adapter->netdev)) {913 for (i = 0; i < adapter->num_tx_queues; i++)914 adapter->tx_ring[i]->count = new_tx_count;915 for (i = 0; i < adapter->num_rx_queues; i++)916 adapter->rx_ring[i]->count = new_rx_count;917 adapter->tx_ring_count = new_tx_count;918 adapter->rx_ring_count = new_rx_count;919 goto clear_reset;920 }921 922 if (adapter->num_tx_queues > adapter->num_rx_queues)923 temp_ring = vmalloc(array_size(sizeof(struct igb_ring),924 adapter->num_tx_queues));925 else926 temp_ring = vmalloc(array_size(sizeof(struct igb_ring),927 adapter->num_rx_queues));928 929 if (!temp_ring) {930 err = -ENOMEM;931 goto clear_reset;932 }933 934 igb_down(adapter);935 936 /* We can't just free everything and then setup again,937 * because the ISRs in MSI-X mode get passed pointers938 * to the Tx and Rx ring structs.939 */940 if (new_tx_count != adapter->tx_ring_count) {941 for (i = 0; i < adapter->num_tx_queues; i++) {942 memcpy(&temp_ring[i], adapter->tx_ring[i],943 sizeof(struct igb_ring));944 945 temp_ring[i].count = new_tx_count;946 err = igb_setup_tx_resources(&temp_ring[i]);947 if (err) {948 while (i) {949 i--;950 igb_free_tx_resources(&temp_ring[i]);951 }952 goto err_setup;953 }954 }955 956 for (i = 0; i < adapter->num_tx_queues; i++) {957 igb_free_tx_resources(adapter->tx_ring[i]);958 959 memcpy(adapter->tx_ring[i], &temp_ring[i],960 sizeof(struct igb_ring));961 }962 963 adapter->tx_ring_count = new_tx_count;964 }965 966 if (new_rx_count != adapter->rx_ring_count) {967 for (i = 0; i < adapter->num_rx_queues; i++) {968 memcpy(&temp_ring[i], adapter->rx_ring[i],969 sizeof(struct igb_ring));970 971 temp_ring[i].count = new_rx_count;972 err = igb_setup_rx_resources(&temp_ring[i]);973 if (err) {974 while (i) {975 i--;976 igb_free_rx_resources(&temp_ring[i]);977 }978 goto err_setup;979 }980 981 }982 983 for (i = 0; i < adapter->num_rx_queues; i++) {984 igb_free_rx_resources(adapter->rx_ring[i]);985 986 memcpy(adapter->rx_ring[i], &temp_ring[i],987 sizeof(struct igb_ring));988 }989 990 adapter->rx_ring_count = new_rx_count;991 }992err_setup:993 igb_up(adapter);994 vfree(temp_ring);995clear_reset:996 clear_bit(__IGB_RESETTING, &adapter->state);997 return err;998}999 1000/* ethtool register test data */1001struct igb_reg_test {1002 u16 reg;1003 u16 reg_offset;1004 u16 array_len;1005 u16 test_type;1006 u32 mask;1007 u32 write;1008};1009 1010/* In the hardware, registers are laid out either singly, in arrays1011 * spaced 0x100 bytes apart, or in contiguous tables. We assume1012 * most tests take place on arrays or single registers (handled1013 * as a single-element array) and special-case the tables.1014 * Table tests are always pattern tests.1015 *1016 * We also make provision for some required setup steps by specifying1017 * registers to be written without any read-back testing.1018 */1019 1020#define PATTERN_TEST 11021#define SET_READ_TEST 21022#define WRITE_NO_TEST 31023#define TABLE32_TEST 41024#define TABLE64_TEST_LO 51025#define TABLE64_TEST_HI 61026 1027/* i210 reg test */1028static struct igb_reg_test reg_test_i210[] = {1029 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },1030 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },1031 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },1032 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },1033 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },1034 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },1035 /* RDH is read-only for i210, only test RDT. */1036 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },1037 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },1038 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },1039 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },1040 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },1041 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },1042 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },1043 { E1000_TDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },1044 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },1045 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },1046 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },1047 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },1048 { E1000_RA, 0, 16, TABLE64_TEST_LO,1049 0xFFFFFFFF, 0xFFFFFFFF },1050 { E1000_RA, 0, 16, TABLE64_TEST_HI,1051 0x900FFFFF, 0xFFFFFFFF },1052 { E1000_MTA, 0, 128, TABLE32_TEST,1053 0xFFFFFFFF, 0xFFFFFFFF },1054 { 0, 0, 0, 0, 0 }1055};1056 1057/* i350 reg test */1058static struct igb_reg_test reg_test_i350[] = {1059 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },1060 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },1061 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },1062 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFF0000, 0xFFFF0000 },1063 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },1064 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },1065 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },1066 { E1000_RDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },1067 { E1000_RDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },1068 { E1000_RDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },1069 /* RDH is read-only for i350, only test RDT. */1070 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },1071 { E1000_RDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },1072 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },1073 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },1074 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },1075 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },1076 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },1077 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },1078 { E1000_TDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },1079 { E1000_TDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },1080 { E1000_TDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },1081 { E1000_TDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },1082 { E1000_TDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },1083 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },1084 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },1085 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },1086 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },1087 { E1000_RA, 0, 16, TABLE64_TEST_LO,1088 0xFFFFFFFF, 0xFFFFFFFF },1089 { E1000_RA, 0, 16, TABLE64_TEST_HI,1090 0xC3FFFFFF, 0xFFFFFFFF },1091 { E1000_RA2, 0, 16, TABLE64_TEST_LO,1092 0xFFFFFFFF, 0xFFFFFFFF },1093 { E1000_RA2, 0, 16, TABLE64_TEST_HI,1094 0xC3FFFFFF, 0xFFFFFFFF },1095 { E1000_MTA, 0, 128, TABLE32_TEST,1096 0xFFFFFFFF, 0xFFFFFFFF },1097 { 0, 0, 0, 0 }1098};1099 1100/* 82580 reg test */1101static struct igb_reg_test reg_test_82580[] = {1102 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },1103 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },1104 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },1105 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },1106 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },1107 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },1108 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },1109 { E1000_RDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },1110 { E1000_RDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },1111 { E1000_RDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },1112 /* RDH is read-only for 82580, only test RDT. */1113 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },1114 { E1000_RDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },1115 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },1116 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },1117 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },1118 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },1119 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },1120 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },1121 { E1000_TDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },1122 { E1000_TDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },1123 { E1000_TDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },1124 { E1000_TDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },1125 { E1000_TDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },1126 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },1127 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },1128 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },1129 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },1130 { E1000_RA, 0, 16, TABLE64_TEST_LO,1131 0xFFFFFFFF, 0xFFFFFFFF },1132 { E1000_RA, 0, 16, TABLE64_TEST_HI,1133 0x83FFFFFF, 0xFFFFFFFF },1134 { E1000_RA2, 0, 8, TABLE64_TEST_LO,1135 0xFFFFFFFF, 0xFFFFFFFF },1136 { E1000_RA2, 0, 8, TABLE64_TEST_HI,1137 0x83FFFFFF, 0xFFFFFFFF },1138 { E1000_MTA, 0, 128, TABLE32_TEST,1139 0xFFFFFFFF, 0xFFFFFFFF },1140 { 0, 0, 0, 0 }1141};1142 1143/* 82576 reg test */1144static struct igb_reg_test reg_test_82576[] = {1145 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },1146 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },1147 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },1148 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },1149 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },1150 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },1151 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },1152 { E1000_RDBAL(4), 0x40, 12, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },1153 { E1000_RDBAH(4), 0x40, 12, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },1154 { E1000_RDLEN(4), 0x40, 12, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },1155 /* Enable all RX queues before testing. */1156 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0,1157 E1000_RXDCTL_QUEUE_ENABLE },1158 { E1000_RXDCTL(4), 0x40, 12, WRITE_NO_TEST, 0,1159 E1000_RXDCTL_QUEUE_ENABLE },1160 /* RDH is read-only for 82576, only test RDT. */1161 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },1162 { E1000_RDT(4), 0x40, 12, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },1163 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 0 },1164 { E1000_RXDCTL(4), 0x40, 12, WRITE_NO_TEST, 0, 0 },1165 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },1166 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },1167 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },1168 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },1169 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },1170 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },1171 { E1000_TDBAL(4), 0x40, 12, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },1172 { E1000_TDBAH(4), 0x40, 12, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },1173 { E1000_TDLEN(4), 0x40, 12, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },1174 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },1175 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },1176 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },1177 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },1178 { E1000_RA, 0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },1179 { E1000_RA, 0, 16, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF },1180 { E1000_RA2, 0, 8, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },1181 { E1000_RA2, 0, 8, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF },1182 { E1000_MTA, 0, 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },1183 { 0, 0, 0, 0 }1184};1185 1186/* 82575 register test */1187static struct igb_reg_test reg_test_82575[] = {1188 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },1189 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },1190 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },1191 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },1192 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },1193 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },1194 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },1195 /* Enable all four RX queues before testing. */1196 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0,1197 E1000_RXDCTL_QUEUE_ENABLE },1198 /* RDH is read-only for 82575, only test RDT. */1199 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },1200 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 0 },1201 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },1202 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },1203 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },1204 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },1205 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },1206 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },1207 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },1208 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0x003FFFFB },1209 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0xFFFFFFFF },1210 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },1211 { E1000_TXCW, 0x100, 1, PATTERN_TEST, 0xC000FFFF, 0x0000FFFF },1212 { E1000_RA, 0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },1213 { E1000_RA, 0, 16, TABLE64_TEST_HI, 0x800FFFFF, 0xFFFFFFFF },1214 { E1000_MTA, 0, 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },1215 { 0, 0, 0, 0 }1216};1217 1218static bool reg_pattern_test(struct igb_adapter *adapter, u64 *data,1219 int reg, u32 mask, u32 write)1220{1221 struct e1000_hw *hw = &adapter->hw;1222 u32 pat, val;1223 static const u32 _test[] = {1224 0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF};1225 for (pat = 0; pat < ARRAY_SIZE(_test); pat++) {1226 wr32(reg, (_test[pat] & write));1227 val = rd32(reg) & mask;1228 if (val != (_test[pat] & write & mask)) {1229 dev_err(&adapter->pdev->dev,1230 "pattern test reg %04X failed: got 0x%08X expected 0x%08X\n",1231 reg, val, (_test[pat] & write & mask));1232 *data = reg;1233 return true;1234 }1235 }1236 1237 return false;1238}1239 1240static bool reg_set_and_check(struct igb_adapter *adapter, u64 *data,1241 int reg, u32 mask, u32 write)1242{1243 struct e1000_hw *hw = &adapter->hw;1244 u32 val;1245 1246 wr32(reg, write & mask);1247 val = rd32(reg);1248 if ((write & mask) != (val & mask)) {1249 dev_err(&adapter->pdev->dev,1250 "set/check reg %04X test failed: got 0x%08X expected 0x%08X\n",1251 reg, (val & mask), (write & mask));1252 *data = reg;1253 return true;1254 }1255 1256 return false;1257}1258 1259#define REG_PATTERN_TEST(reg, mask, write) \1260 do { \1261 if (reg_pattern_test(adapter, data, reg, mask, write)) \1262 return 1; \1263 } while (0)1264 1265#define REG_SET_AND_CHECK(reg, mask, write) \1266 do { \1267 if (reg_set_and_check(adapter, data, reg, mask, write)) \1268 return 1; \1269 } while (0)1270 1271static int igb_reg_test(struct igb_adapter *adapter, u64 *data)1272{1273 struct e1000_hw *hw = &adapter->hw;1274 struct igb_reg_test *test;1275 u32 value, before, after;1276 u32 i, toggle;1277 1278 switch (adapter->hw.mac.type) {1279 case e1000_i350:1280 case e1000_i354:1281 test = reg_test_i350;1282 toggle = 0x7FEFF3FF;1283 break;1284 case e1000_i210:1285 case e1000_i211:1286 test = reg_test_i210;1287 toggle = 0x7FEFF3FF;1288 break;1289 case e1000_82580:1290 test = reg_test_82580;1291 toggle = 0x7FEFF3FF;1292 break;1293 case e1000_82576:1294 test = reg_test_82576;1295 toggle = 0x7FFFF3FF;1296 break;1297 default:1298 test = reg_test_82575;1299 toggle = 0x7FFFF3FF;1300 break;1301 }1302 1303 /* Because the status register is such a special case,1304 * we handle it separately from the rest of the register1305 * tests. Some bits are read-only, some toggle, and some1306 * are writable on newer MACs.1307 */1308 before = rd32(E1000_STATUS);1309 value = (rd32(E1000_STATUS) & toggle);1310 wr32(E1000_STATUS, toggle);1311 after = rd32(E1000_STATUS) & toggle;1312 if (value != after) {1313 dev_err(&adapter->pdev->dev,1314 "failed STATUS register test got: 0x%08X expected: 0x%08X\n",1315 after, value);1316 *data = 1;1317 return 1;1318 }1319 /* restore previous status */1320 wr32(E1000_STATUS, before);1321 1322 /* Perform the remainder of the register test, looping through1323 * the test table until we either fail or reach the null entry.1324 */1325 while (test->reg) {1326 for (i = 0; i < test->array_len; i++) {1327 switch (test->test_type) {1328 case PATTERN_TEST:1329 REG_PATTERN_TEST(test->reg +1330 (i * test->reg_offset),1331 test->mask,1332 test->write);1333 break;1334 case SET_READ_TEST:1335 REG_SET_AND_CHECK(test->reg +1336 (i * test->reg_offset),1337 test->mask,1338 test->write);1339 break;1340 case WRITE_NO_TEST:1341 writel(test->write,1342 (adapter->hw.hw_addr + test->reg)1343 + (i * test->reg_offset));1344 break;1345 case TABLE32_TEST:1346 REG_PATTERN_TEST(test->reg + (i * 4),1347 test->mask,1348 test->write);1349 break;1350 case TABLE64_TEST_LO:1351 REG_PATTERN_TEST(test->reg + (i * 8),1352 test->mask,1353 test->write);1354 break;1355 case TABLE64_TEST_HI:1356 REG_PATTERN_TEST((test->reg + 4) + (i * 8),1357 test->mask,1358 test->write);1359 break;1360 }1361 }1362 test++;1363 }1364 1365 *data = 0;1366 return 0;1367}1368 1369static int igb_eeprom_test(struct igb_adapter *adapter, u64 *data)1370{1371 struct e1000_hw *hw = &adapter->hw;1372 1373 *data = 0;1374 1375 /* Validate eeprom on all parts but flashless */1376 switch (hw->mac.type) {1377 case e1000_i210:1378 case e1000_i211:1379 if (igb_get_flash_presence_i210(hw)) {1380 if (adapter->hw.nvm.ops.validate(&adapter->hw) < 0)1381 *data = 2;1382 }1383 break;1384 default:1385 if (adapter->hw.nvm.ops.validate(&adapter->hw) < 0)1386 *data = 2;1387 break;1388 }1389 1390 return *data;1391}1392 1393static irqreturn_t igb_test_intr(int irq, void *data)1394{1395 struct igb_adapter *adapter = (struct igb_adapter *) data;1396 struct e1000_hw *hw = &adapter->hw;1397 1398 adapter->test_icr |= rd32(E1000_ICR);1399 1400 return IRQ_HANDLED;1401}1402 1403static int igb_intr_test(struct igb_adapter *adapter, u64 *data)1404{1405 struct e1000_hw *hw = &adapter->hw;1406 struct net_device *netdev = adapter->netdev;1407 u32 mask, ics_mask, i = 0, shared_int = true;1408 u32 irq = adapter->pdev->irq;1409 1410 *data = 0;1411 1412 /* Hook up test interrupt handler just for this test */1413 if (adapter->flags & IGB_FLAG_HAS_MSIX) {1414 if (request_irq(adapter->msix_entries[0].vector,1415 igb_test_intr, 0, netdev->name, adapter)) {1416 *data = 1;1417 return -1;1418 }1419 wr32(E1000_IVAR_MISC, E1000_IVAR_VALID << 8);1420 wr32(E1000_EIMS, BIT(0));1421 } else if (adapter->flags & IGB_FLAG_HAS_MSI) {1422 shared_int = false;1423 if (request_irq(irq,1424 igb_test_intr, 0, netdev->name, adapter)) {1425 *data = 1;1426 return -1;1427 }1428 } else if (!request_irq(irq, igb_test_intr, IRQF_PROBE_SHARED,1429 netdev->name, adapter)) {1430 shared_int = false;1431 } else if (request_irq(irq, igb_test_intr, IRQF_SHARED,1432 netdev->name, adapter)) {1433 *data = 1;1434 return -1;1435 }1436 dev_info(&adapter->pdev->dev, "testing %s interrupt\n",1437 (shared_int ? "shared" : "unshared"));1438 1439 /* Disable all the interrupts */1440 wr32(E1000_IMC, ~0);1441 wrfl();1442 usleep_range(10000, 11000);1443 1444 /* Define all writable bits for ICS */1445 switch (hw->mac.type) {1446 case e1000_82575:1447 ics_mask = 0x37F47EDD;1448 break;1449 case e1000_82576:1450 ics_mask = 0x77D4FBFD;1451 break;1452 case e1000_82580:1453 ics_mask = 0x77DCFED5;1454 break;1455 case e1000_i350:1456 case e1000_i354:1457 case e1000_i210:1458 case e1000_i211:1459 ics_mask = 0x77DCFED5;1460 break;1461 default:1462 ics_mask = 0x7FFFFFFF;1463 break;1464 }1465 1466 /* Test each interrupt */1467 for (; i < 31; i++) {1468 /* Interrupt to test */1469 mask = BIT(i);1470 1471 if (!(mask & ics_mask))1472 continue;1473 1474 if (!shared_int) {1475 /* Disable the interrupt to be reported in1476 * the cause register and then force the same1477 * interrupt and see if one gets posted. If1478 * an interrupt was posted to the bus, the1479 * test failed.1480 */1481 adapter->test_icr = 0;1482 1483 /* Flush any pending interrupts */1484 wr32(E1000_ICR, ~0);1485 1486 wr32(E1000_IMC, mask);1487 wr32(E1000_ICS, mask);1488 wrfl();1489 usleep_range(10000, 11000);1490 1491 if (adapter->test_icr & mask) {1492 *data = 3;1493 break;1494 }1495 }1496 1497 /* Enable the interrupt to be reported in1498 * the cause register and then force the same1499 * interrupt and see if one gets posted. If1500 * an interrupt was not posted to the bus, the1501 * test failed.1502 */1503 adapter->test_icr = 0;1504 1505 /* Flush any pending interrupts */1506 wr32(E1000_ICR, ~0);1507 1508 wr32(E1000_IMS, mask);1509 wr32(E1000_ICS, mask);1510 wrfl();1511 usleep_range(10000, 11000);1512 1513 if (!(adapter->test_icr & mask)) {1514 *data = 4;1515 break;1516 }1517 1518 if (!shared_int) {1519 /* Disable the other interrupts to be reported in1520 * the cause register and then force the other1521 * interrupts and see if any get posted. If1522 * an interrupt was posted to the bus, the1523 * test failed.1524 */1525 adapter->test_icr = 0;1526 1527 /* Flush any pending interrupts */1528 wr32(E1000_ICR, ~0);1529 1530 wr32(E1000_IMC, ~mask);1531 wr32(E1000_ICS, ~mask);1532 wrfl();1533 usleep_range(10000, 11000);1534 1535 if (adapter->test_icr & mask) {1536 *data = 5;1537 break;1538 }1539 }1540 }1541 1542 /* Disable all the interrupts */1543 wr32(E1000_IMC, ~0);1544 wrfl();1545 usleep_range(10000, 11000);1546 1547 /* Unhook test interrupt handler */1548 if (adapter->flags & IGB_FLAG_HAS_MSIX)1549 free_irq(adapter->msix_entries[0].vector, adapter);1550 else1551 free_irq(irq, adapter);1552 1553 return *data;1554}1555 1556static void igb_free_desc_rings(struct igb_adapter *adapter)1557{1558 igb_free_tx_resources(&adapter->test_tx_ring);1559 igb_free_rx_resources(&adapter->test_rx_ring);1560}1561 1562static int igb_setup_desc_rings(struct igb_adapter *adapter)1563{1564 struct igb_ring *tx_ring = &adapter->test_tx_ring;1565 struct igb_ring *rx_ring = &adapter->test_rx_ring;1566 struct e1000_hw *hw = &adapter->hw;1567 int ret_val;1568 1569 /* Setup Tx descriptor ring and Tx buffers */1570 tx_ring->count = IGB_DEFAULT_TXD;1571 tx_ring->dev = &adapter->pdev->dev;1572 tx_ring->netdev = adapter->netdev;1573 tx_ring->reg_idx = adapter->vfs_allocated_count;1574 1575 if (igb_setup_tx_resources(tx_ring)) {1576 ret_val = 1;1577 goto err_nomem;1578 }1579 1580 igb_setup_tctl(adapter);1581 igb_configure_tx_ring(adapter, tx_ring);1582 1583 /* Setup Rx descriptor ring and Rx buffers */1584 rx_ring->count = IGB_DEFAULT_RXD;1585 rx_ring->dev = &adapter->pdev->dev;1586 rx_ring->netdev = adapter->netdev;1587 rx_ring->reg_idx = adapter->vfs_allocated_count;1588 1589 if (igb_setup_rx_resources(rx_ring)) {1590 ret_val = 3;1591 goto err_nomem;1592 }1593 1594 /* set the default queue to queue 0 of PF */1595 wr32(E1000_MRQC, adapter->vfs_allocated_count << 3);1596 1597 /* enable receive ring */1598 igb_setup_rctl(adapter);1599 igb_configure_rx_ring(adapter, rx_ring);1600 1601 igb_alloc_rx_buffers(rx_ring, igb_desc_unused(rx_ring));1602 1603 return 0;1604 1605err_nomem:1606 igb_free_desc_rings(adapter);1607 return ret_val;1608}1609 1610static void igb_phy_disable_receiver(struct igb_adapter *adapter)1611{1612 struct e1000_hw *hw = &adapter->hw;1613 1614 /* Write out to PHY registers 29 and 30 to disable the Receiver. */1615 igb_write_phy_reg(hw, 29, 0x001F);1616 igb_write_phy_reg(hw, 30, 0x8FFC);1617 igb_write_phy_reg(hw, 29, 0x001A);1618 igb_write_phy_reg(hw, 30, 0x8FF0);1619}1620 1621static int igb_integrated_phy_loopback(struct igb_adapter *adapter)1622{1623 struct e1000_hw *hw = &adapter->hw;1624 u32 ctrl_reg = 0;1625 1626 hw->mac.autoneg = false;1627 1628 if (hw->phy.type == e1000_phy_m88) {1629 if (hw->phy.id != I210_I_PHY_ID) {1630 /* Auto-MDI/MDIX Off */1631 igb_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 0x0808);1632 /* reset to update Auto-MDI/MDIX */1633 igb_write_phy_reg(hw, PHY_CONTROL, 0x9140);1634 /* autoneg off */1635 igb_write_phy_reg(hw, PHY_CONTROL, 0x8140);1636 } else {1637 /* force 1000, set loopback */1638 igb_write_phy_reg(hw, I347AT4_PAGE_SELECT, 0);1639 igb_write_phy_reg(hw, PHY_CONTROL, 0x4140);1640 }1641 } else if (hw->phy.type == e1000_phy_82580) {1642 /* enable MII loopback */1643 igb_write_phy_reg(hw, I82580_PHY_LBK_CTRL, 0x8041);1644 }1645 1646 /* add small delay to avoid loopback test failure */1647 msleep(50);1648 1649 /* force 1000, set loopback */1650 igb_write_phy_reg(hw, PHY_CONTROL, 0x4140);1651 1652 /* Now set up the MAC to the same speed/duplex as the PHY. */1653 ctrl_reg = rd32(E1000_CTRL);1654 ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */1655 ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */1656 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */1657 E1000_CTRL_SPD_1000 |/* Force Speed to 1000 */1658 E1000_CTRL_FD | /* Force Duplex to FULL */1659 E1000_CTRL_SLU); /* Set link up enable bit */1660 1661 if (hw->phy.type == e1000_phy_m88)1662 ctrl_reg |= E1000_CTRL_ILOS; /* Invert Loss of Signal */1663 1664 wr32(E1000_CTRL, ctrl_reg);1665 1666 /* Disable the receiver on the PHY so when a cable is plugged in, the1667 * PHY does not begin to autoneg when a cable is reconnected to the NIC.1668 */1669 if (hw->phy.type == e1000_phy_m88)1670 igb_phy_disable_receiver(adapter);1671 1672 msleep(500);1673 return 0;1674}1675 1676static int igb_set_phy_loopback(struct igb_adapter *adapter)1677{1678 return igb_integrated_phy_loopback(adapter);1679}1680 1681static int igb_setup_loopback_test(struct igb_adapter *adapter)1682{1683 struct e1000_hw *hw = &adapter->hw;1684 u32 reg;1685 1686 reg = rd32(E1000_CTRL_EXT);1687 1688 /* use CTRL_EXT to identify link type as SGMII can appear as copper */1689 if (reg & E1000_CTRL_EXT_LINK_MODE_MASK) {1690 if ((hw->device_id == E1000_DEV_ID_DH89XXCC_SGMII) ||1691 (hw->device_id == E1000_DEV_ID_DH89XXCC_SERDES) ||1692 (hw->device_id == E1000_DEV_ID_DH89XXCC_BACKPLANE) ||1693 (hw->device_id == E1000_DEV_ID_DH89XXCC_SFP) ||1694 (hw->device_id == E1000_DEV_ID_I354_SGMII) ||1695 (hw->device_id == E1000_DEV_ID_I354_BACKPLANE_2_5GBPS)) {1696 /* Enable DH89xxCC MPHY for near end loopback */1697 reg = rd32(E1000_MPHY_ADDR_CTL);1698 reg = (reg & E1000_MPHY_ADDR_CTL_OFFSET_MASK) |1699 E1000_MPHY_PCS_CLK_REG_OFFSET;1700 wr32(E1000_MPHY_ADDR_CTL, reg);1701 1702 reg = rd32(E1000_MPHY_DATA);1703 reg |= E1000_MPHY_PCS_CLK_REG_DIGINELBEN;1704 wr32(E1000_MPHY_DATA, reg);1705 }1706 1707 reg = rd32(E1000_RCTL);1708 reg |= E1000_RCTL_LBM_TCVR;1709 wr32(E1000_RCTL, reg);1710 1711 wr32(E1000_SCTL, E1000_ENABLE_SERDES_LOOPBACK);1712 1713 reg = rd32(E1000_CTRL);1714 reg &= ~(E1000_CTRL_RFCE |1715 E1000_CTRL_TFCE |1716 E1000_CTRL_LRST);1717 reg |= E1000_CTRL_SLU |1718 E1000_CTRL_FD;1719 wr32(E1000_CTRL, reg);1720 1721 /* Unset switch control to serdes energy detect */1722 reg = rd32(E1000_CONNSW);1723 reg &= ~E1000_CONNSW_ENRGSRC;1724 wr32(E1000_CONNSW, reg);1725 1726 /* Unset sigdetect for SERDES loopback on1727 * 82580 and newer devices.1728 */1729 if (hw->mac.type >= e1000_82580) {1730 reg = rd32(E1000_PCS_CFG0);1731 reg |= E1000_PCS_CFG_IGN_SD;1732 wr32(E1000_PCS_CFG0, reg);1733 }1734 1735 /* Set PCS register for forced speed */1736 reg = rd32(E1000_PCS_LCTL);1737 reg &= ~E1000_PCS_LCTL_AN_ENABLE; /* Disable Autoneg*/1738 reg |= E1000_PCS_LCTL_FLV_LINK_UP | /* Force link up */1739 E1000_PCS_LCTL_FSV_1000 | /* Force 1000 */1740 E1000_PCS_LCTL_FDV_FULL | /* SerDes Full duplex */1741 E1000_PCS_LCTL_FSD | /* Force Speed */1742 E1000_PCS_LCTL_FORCE_LINK; /* Force Link */1743 wr32(E1000_PCS_LCTL, reg);1744 1745 return 0;1746 }1747 1748 return igb_set_phy_loopback(adapter);1749}1750 1751static void igb_loopback_cleanup(struct igb_adapter *adapter)1752{1753 struct e1000_hw *hw = &adapter->hw;1754 u32 rctl;1755 u16 phy_reg;1756 1757 if ((hw->device_id == E1000_DEV_ID_DH89XXCC_SGMII) ||1758 (hw->device_id == E1000_DEV_ID_DH89XXCC_SERDES) ||1759 (hw->device_id == E1000_DEV_ID_DH89XXCC_BACKPLANE) ||1760 (hw->device_id == E1000_DEV_ID_DH89XXCC_SFP) ||1761 (hw->device_id == E1000_DEV_ID_I354_SGMII)) {1762 u32 reg;1763 1764 /* Disable near end loopback on DH89xxCC */1765 reg = rd32(E1000_MPHY_ADDR_CTL);1766 reg = (reg & E1000_MPHY_ADDR_CTL_OFFSET_MASK) |1767 E1000_MPHY_PCS_CLK_REG_OFFSET;1768 wr32(E1000_MPHY_ADDR_CTL, reg);1769 1770 reg = rd32(E1000_MPHY_DATA);1771 reg &= ~E1000_MPHY_PCS_CLK_REG_DIGINELBEN;1772 wr32(E1000_MPHY_DATA, reg);1773 }1774 1775 rctl = rd32(E1000_RCTL);1776 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);1777 wr32(E1000_RCTL, rctl);1778 1779 hw->mac.autoneg = true;1780 igb_read_phy_reg(hw, PHY_CONTROL, &phy_reg);1781 if (phy_reg & MII_CR_LOOPBACK) {1782 phy_reg &= ~MII_CR_LOOPBACK;1783 igb_write_phy_reg(hw, PHY_CONTROL, phy_reg);1784 igb_phy_sw_reset(hw);1785 }1786}1787 1788static void igb_create_lbtest_frame(struct sk_buff *skb,1789 unsigned int frame_size)1790{1791 memset(skb->data, 0xFF, frame_size);1792 frame_size /= 2;1793 memset(&skb->data[frame_size], 0xAA, frame_size - 1);1794 skb->data[frame_size + 10] = 0xBE;1795 skb->data[frame_size + 12] = 0xAF;1796}1797 1798static int igb_check_lbtest_frame(struct igb_rx_buffer *rx_buffer,1799 unsigned int frame_size)1800{1801 unsigned char *data;1802 bool match = true;1803 1804 frame_size >>= 1;1805 1806 data = kmap_local_page(rx_buffer->page);1807 1808 if (data[3] != 0xFF ||1809 data[frame_size + 10] != 0xBE ||1810 data[frame_size + 12] != 0xAF)1811 match = false;1812 1813 kunmap_local(data);1814 1815 return match;1816}1817 1818static int igb_clean_test_rings(struct igb_ring *rx_ring,1819 struct igb_ring *tx_ring,1820 unsigned int size)1821{1822 union e1000_adv_rx_desc *rx_desc;1823 struct igb_rx_buffer *rx_buffer_info;1824 struct igb_tx_buffer *tx_buffer_info;1825 u16 rx_ntc, tx_ntc, count = 0;1826 1827 /* initialize next to clean and descriptor values */1828 rx_ntc = rx_ring->next_to_clean;1829 tx_ntc = tx_ring->next_to_clean;1830 rx_desc = IGB_RX_DESC(rx_ring, rx_ntc);1831 1832 while (rx_desc->wb.upper.length) {1833 /* check Rx buffer */1834 rx_buffer_info = &rx_ring->rx_buffer_info[rx_ntc];1835 1836 /* sync Rx buffer for CPU read */1837 dma_sync_single_for_cpu(rx_ring->dev,1838 rx_buffer_info->dma,1839 size,1840 DMA_FROM_DEVICE);1841 1842 /* verify contents of skb */1843 if (igb_check_lbtest_frame(rx_buffer_info, size))1844 count++;1845 1846 /* sync Rx buffer for device write */1847 dma_sync_single_for_device(rx_ring->dev,1848 rx_buffer_info->dma,1849 size,1850 DMA_FROM_DEVICE);1851 1852 /* unmap buffer on Tx side */1853 tx_buffer_info = &tx_ring->tx_buffer_info[tx_ntc];1854 1855 /* Free all the Tx ring sk_buffs */1856 dev_kfree_skb_any(tx_buffer_info->skb);1857 1858 /* unmap skb header data */1859 dma_unmap_single(tx_ring->dev,1860 dma_unmap_addr(tx_buffer_info, dma),1861 dma_unmap_len(tx_buffer_info, len),1862 DMA_TO_DEVICE);1863 dma_unmap_len_set(tx_buffer_info, len, 0);1864 1865 /* increment Rx/Tx next to clean counters */1866 rx_ntc++;1867 if (rx_ntc == rx_ring->count)1868 rx_ntc = 0;1869 tx_ntc++;1870 if (tx_ntc == tx_ring->count)1871 tx_ntc = 0;1872 1873 /* fetch next descriptor */1874 rx_desc = IGB_RX_DESC(rx_ring, rx_ntc);1875 }1876 1877 netdev_tx_reset_queue(txring_txq(tx_ring));1878 1879 /* re-map buffers to ring, store next to clean values */1880 igb_alloc_rx_buffers(rx_ring, count);1881 rx_ring->next_to_clean = rx_ntc;1882 tx_ring->next_to_clean = tx_ntc;1883 1884 return count;1885}1886 1887static int igb_run_loopback_test(struct igb_adapter *adapter)1888{1889 struct igb_ring *tx_ring = &adapter->test_tx_ring;1890 struct igb_ring *rx_ring = &adapter->test_rx_ring;1891 u16 i, j, lc, good_cnt;1892 int ret_val = 0;1893 unsigned int size = IGB_RX_HDR_LEN;1894 netdev_tx_t tx_ret_val;1895 struct sk_buff *skb;1896 1897 /* allocate test skb */1898 skb = alloc_skb(size, GFP_KERNEL);1899 if (!skb)1900 return 11;1901 1902 /* place data into test skb */1903 igb_create_lbtest_frame(skb, size);1904 skb_put(skb, size);1905 1906 /* Calculate the loop count based on the largest descriptor ring1907 * The idea is to wrap the largest ring a number of times using 641908 * send/receive pairs during each loop1909 */1910 1911 if (rx_ring->count <= tx_ring->count)1912 lc = ((tx_ring->count / 64) * 2) + 1;1913 else1914 lc = ((rx_ring->count / 64) * 2) + 1;1915 1916 for (j = 0; j <= lc; j++) { /* loop count loop */1917 /* reset count of good packets */1918 good_cnt = 0;1919 1920 /* place 64 packets on the transmit queue*/1921 for (i = 0; i < 64; i++) {1922 skb_get(skb);1923 tx_ret_val = igb_xmit_frame_ring(skb, tx_ring);1924 if (tx_ret_val == NETDEV_TX_OK)1925 good_cnt++;1926 }1927 1928 if (good_cnt != 64) {1929 ret_val = 12;1930 break;1931 }1932 1933 /* allow 200 milliseconds for packets to go from Tx to Rx */1934 msleep(200);1935 1936 good_cnt = igb_clean_test_rings(rx_ring, tx_ring, size);1937 if (good_cnt != 64) {1938 ret_val = 13;1939 break;1940 }1941 } /* end loop count loop */1942 1943 /* free the original skb */1944 kfree_skb(skb);1945 1946 return ret_val;1947}1948 1949static int igb_loopback_test(struct igb_adapter *adapter, u64 *data)1950{1951 /* PHY loopback cannot be performed if SoL/IDER1952 * sessions are active1953 */1954 if (igb_check_reset_block(&adapter->hw)) {1955 dev_err(&adapter->pdev->dev,1956 "Cannot do PHY loopback test when SoL/IDER is active.\n");1957 *data = 0;1958 goto out;1959 }1960 1961 if (adapter->hw.mac.type == e1000_i354) {1962 dev_info(&adapter->pdev->dev,1963 "Loopback test not supported on i354.\n");1964 *data = 0;1965 goto out;1966 }1967 *data = igb_setup_desc_rings(adapter);1968 if (*data)1969 goto out;1970 *data = igb_setup_loopback_test(adapter);1971 if (*data)1972 goto err_loopback;1973 *data = igb_run_loopback_test(adapter);1974 igb_loopback_cleanup(adapter);1975 1976err_loopback:1977 igb_free_desc_rings(adapter);1978out:1979 return *data;1980}1981 1982static int igb_link_test(struct igb_adapter *adapter, u64 *data)1983{1984 struct e1000_hw *hw = &adapter->hw;1985 *data = 0;1986 if (hw->phy.media_type == e1000_media_type_internal_serdes) {1987 int i = 0;1988 1989 hw->mac.serdes_has_link = false;1990 1991 /* On some blade server designs, link establishment1992 * could take as long as 2-3 minutes1993 */1994 do {1995 hw->mac.ops.check_for_link(&adapter->hw);1996 if (hw->mac.serdes_has_link)1997 return *data;1998 msleep(20);1999 } while (i++ < 3750);2000 2001 *data = 1;2002 } else {2003 hw->mac.ops.check_for_link(&adapter->hw);2004 if (hw->mac.autoneg)2005 msleep(5000);2006 2007 if (!(rd32(E1000_STATUS) & E1000_STATUS_LU))2008 *data = 1;2009 }2010 return *data;2011}2012 2013static void igb_diag_test(struct net_device *netdev,2014 struct ethtool_test *eth_test, u64 *data)2015{2016 struct igb_adapter *adapter = netdev_priv(netdev);2017 u16 autoneg_advertised;2018 u8 forced_speed_duplex, autoneg;2019 bool if_running = netif_running(netdev);2020 2021 set_bit(__IGB_TESTING, &adapter->state);2022 2023 /* can't do offline tests on media switching devices */2024 if (adapter->hw.dev_spec._82575.mas_capable)2025 eth_test->flags &= ~ETH_TEST_FL_OFFLINE;2026 if (eth_test->flags == ETH_TEST_FL_OFFLINE) {2027 /* Offline tests */2028 2029 /* save speed, duplex, autoneg settings */2030 autoneg_advertised = adapter->hw.phy.autoneg_advertised;2031 forced_speed_duplex = adapter->hw.mac.forced_speed_duplex;2032 autoneg = adapter->hw.mac.autoneg;2033 2034 dev_info(&adapter->pdev->dev, "offline testing starting\n");2035 2036 /* power up link for link test */2037 igb_power_up_link(adapter);2038 2039 /* Link test performed before hardware reset so autoneg doesn't2040 * interfere with test result2041 */2042 if (igb_link_test(adapter, &data[TEST_LINK]))2043 eth_test->flags |= ETH_TEST_FL_FAILED;2044 2045 if (if_running)2046 /* indicate we're in test mode */2047 igb_close(netdev);2048 else2049 igb_reset(adapter);2050 2051 if (igb_reg_test(adapter, &data[TEST_REG]))2052 eth_test->flags |= ETH_TEST_FL_FAILED;2053 2054 igb_reset(adapter);2055 if (igb_eeprom_test(adapter, &data[TEST_EEP]))2056 eth_test->flags |= ETH_TEST_FL_FAILED;2057 2058 igb_reset(adapter);2059 if (igb_intr_test(adapter, &data[TEST_IRQ]))2060 eth_test->flags |= ETH_TEST_FL_FAILED;2061 2062 igb_reset(adapter);2063 /* power up link for loopback test */2064 igb_power_up_link(adapter);2065 if (igb_loopback_test(adapter, &data[TEST_LOOP]))2066 eth_test->flags |= ETH_TEST_FL_FAILED;2067 2068 /* restore speed, duplex, autoneg settings */2069 adapter->hw.phy.autoneg_advertised = autoneg_advertised;2070 adapter->hw.mac.forced_speed_duplex = forced_speed_duplex;2071 adapter->hw.mac.autoneg = autoneg;2072 2073 /* force this routine to wait until autoneg complete/timeout */2074 adapter->hw.phy.autoneg_wait_to_complete = true;2075 igb_reset(adapter);2076 adapter->hw.phy.autoneg_wait_to_complete = false;2077 2078 clear_bit(__IGB_TESTING, &adapter->state);2079 if (if_running)2080 igb_open(netdev);2081 } else {2082 dev_info(&adapter->pdev->dev, "online testing starting\n");2083 2084 /* PHY is powered down when interface is down */2085 if (if_running && igb_link_test(adapter, &data[TEST_LINK]))2086 eth_test->flags |= ETH_TEST_FL_FAILED;2087 else2088 data[TEST_LINK] = 0;2089 2090 /* Online tests aren't run; pass by default */2091 data[TEST_REG] = 0;2092 data[TEST_EEP] = 0;2093 data[TEST_IRQ] = 0;2094 data[TEST_LOOP] = 0;2095 2096 clear_bit(__IGB_TESTING, &adapter->state);2097 }2098 msleep_interruptible(4 * 1000);2099}2100 2101static void igb_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)2102{2103 struct igb_adapter *adapter = netdev_priv(netdev);2104 2105 wol->wolopts = 0;2106 2107 if (!(adapter->flags & IGB_FLAG_WOL_SUPPORTED))2108 return;2109 2110 wol->supported = WAKE_UCAST | WAKE_MCAST |2111 WAKE_BCAST | WAKE_MAGIC |2112 WAKE_PHY;2113 2114 /* apply any specific unsupported masks here */2115 switch (adapter->hw.device_id) {2116 default:2117 break;2118 }2119 2120 if (adapter->wol & E1000_WUFC_EX)2121 wol->wolopts |= WAKE_UCAST;2122 if (adapter->wol & E1000_WUFC_MC)2123 wol->wolopts |= WAKE_MCAST;2124 if (adapter->wol & E1000_WUFC_BC)2125 wol->wolopts |= WAKE_BCAST;2126 if (adapter->wol & E1000_WUFC_MAG)2127 wol->wolopts |= WAKE_MAGIC;2128 if (adapter->wol & E1000_WUFC_LNKC)2129 wol->wolopts |= WAKE_PHY;2130}2131 2132static int igb_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)2133{2134 struct igb_adapter *adapter = netdev_priv(netdev);2135 2136 if (wol->wolopts & (WAKE_ARP | WAKE_MAGICSECURE | WAKE_FILTER))2137 return -EOPNOTSUPP;2138 2139 if (!(adapter->flags & IGB_FLAG_WOL_SUPPORTED))2140 return wol->wolopts ? -EOPNOTSUPP : 0;2141 2142 /* these settings will always override what we currently have */2143 adapter->wol = 0;2144 2145 if (wol->wolopts & WAKE_UCAST)2146 adapter->wol |= E1000_WUFC_EX;2147 if (wol->wolopts & WAKE_MCAST)2148 adapter->wol |= E1000_WUFC_MC;2149 if (wol->wolopts & WAKE_BCAST)2150 adapter->wol |= E1000_WUFC_BC;2151 if (wol->wolopts & WAKE_MAGIC)2152 adapter->wol |= E1000_WUFC_MAG;2153 if (wol->wolopts & WAKE_PHY)2154 adapter->wol |= E1000_WUFC_LNKC;2155 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);2156 2157 return 0;2158}2159 2160/* bit defines for adapter->led_status */2161#define IGB_LED_ON 02162 2163static int igb_set_phys_id(struct net_device *netdev,2164 enum ethtool_phys_id_state state)2165{2166 struct igb_adapter *adapter = netdev_priv(netdev);2167 struct e1000_hw *hw = &adapter->hw;2168 2169 switch (state) {2170 case ETHTOOL_ID_ACTIVE:2171 igb_blink_led(hw);2172 return 2;2173 case ETHTOOL_ID_ON:2174 igb_blink_led(hw);2175 break;2176 case ETHTOOL_ID_OFF:2177 igb_led_off(hw);2178 break;2179 case ETHTOOL_ID_INACTIVE:2180 igb_led_off(hw);2181 clear_bit(IGB_LED_ON, &adapter->led_status);2182 igb_cleanup_led(hw);2183 break;2184 }2185 2186 return 0;2187}2188 2189static int igb_set_coalesce(struct net_device *netdev,2190 struct ethtool_coalesce *ec,2191 struct kernel_ethtool_coalesce *kernel_coal,2192 struct netlink_ext_ack *extack)2193{2194 struct igb_adapter *adapter = netdev_priv(netdev);2195 int i;2196 2197 if ((ec->rx_coalesce_usecs > IGB_MAX_ITR_USECS) ||2198 ((ec->rx_coalesce_usecs > 3) &&2199 (ec->rx_coalesce_usecs < IGB_MIN_ITR_USECS)) ||2200 (ec->rx_coalesce_usecs == 2))2201 return -EINVAL;2202 2203 if ((ec->tx_coalesce_usecs > IGB_MAX_ITR_USECS) ||2204 ((ec->tx_coalesce_usecs > 3) &&2205 (ec->tx_coalesce_usecs < IGB_MIN_ITR_USECS)) ||2206 (ec->tx_coalesce_usecs == 2))2207 return -EINVAL;2208 2209 if ((adapter->flags & IGB_FLAG_QUEUE_PAIRS) && ec->tx_coalesce_usecs)2210 return -EINVAL;2211 2212 /* If ITR is disabled, disable DMAC */2213 if (ec->rx_coalesce_usecs == 0) {2214 if (adapter->flags & IGB_FLAG_DMAC)2215 adapter->flags &= ~IGB_FLAG_DMAC;2216 }2217 2218 /* convert to rate of irq's per second */2219 if (ec->rx_coalesce_usecs && ec->rx_coalesce_usecs <= 3)2220 adapter->rx_itr_setting = ec->rx_coalesce_usecs;2221 else2222 adapter->rx_itr_setting = ec->rx_coalesce_usecs << 2;2223 2224 /* convert to rate of irq's per second */2225 if (adapter->flags & IGB_FLAG_QUEUE_PAIRS)2226 adapter->tx_itr_setting = adapter->rx_itr_setting;2227 else if (ec->tx_coalesce_usecs && ec->tx_coalesce_usecs <= 3)2228 adapter->tx_itr_setting = ec->tx_coalesce_usecs;2229 else2230 adapter->tx_itr_setting = ec->tx_coalesce_usecs << 2;2231 2232 for (i = 0; i < adapter->num_q_vectors; i++) {2233 struct igb_q_vector *q_vector = adapter->q_vector[i];2234 q_vector->tx.work_limit = adapter->tx_work_limit;2235 if (q_vector->rx.ring)2236 q_vector->itr_val = adapter->rx_itr_setting;2237 else2238 q_vector->itr_val = adapter->tx_itr_setting;2239 if (q_vector->itr_val && q_vector->itr_val <= 3)2240 q_vector->itr_val = IGB_START_ITR;2241 q_vector->set_itr = 1;2242 }2243 2244 return 0;2245}2246 2247static int igb_get_coalesce(struct net_device *netdev,2248 struct ethtool_coalesce *ec,2249 struct kernel_ethtool_coalesce *kernel_coal,2250 struct netlink_ext_ack *extack)2251{2252 struct igb_adapter *adapter = netdev_priv(netdev);2253 2254 if (adapter->rx_itr_setting <= 3)2255 ec->rx_coalesce_usecs = adapter->rx_itr_setting;2256 else2257 ec->rx_coalesce_usecs = adapter->rx_itr_setting >> 2;2258 2259 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS)) {2260 if (adapter->tx_itr_setting <= 3)2261 ec->tx_coalesce_usecs = adapter->tx_itr_setting;2262 else2263 ec->tx_coalesce_usecs = adapter->tx_itr_setting >> 2;2264 }2265 2266 return 0;2267}2268 2269static int igb_nway_reset(struct net_device *netdev)2270{2271 struct igb_adapter *adapter = netdev_priv(netdev);2272 if (netif_running(netdev))2273 igb_reinit_locked(adapter);2274 return 0;2275}2276 2277static int igb_get_sset_count(struct net_device *netdev, int sset)2278{2279 switch (sset) {2280 case ETH_SS_STATS:2281 return IGB_STATS_LEN;2282 case ETH_SS_TEST:2283 return IGB_TEST_LEN;2284 case ETH_SS_PRIV_FLAGS:2285 return IGB_PRIV_FLAGS_STR_LEN;2286 default:2287 return -ENOTSUPP;2288 }2289}2290 2291static void igb_get_ethtool_stats(struct net_device *netdev,2292 struct ethtool_stats *stats, u64 *data)2293{2294 struct igb_adapter *adapter = netdev_priv(netdev);2295 struct rtnl_link_stats64 *net_stats = &adapter->stats64;2296 unsigned int start;2297 struct igb_ring *ring;2298 int i, j;2299 char *p;2300 2301 spin_lock(&adapter->stats64_lock);2302 igb_update_stats(adapter);2303 2304 for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) {2305 p = (char *)adapter + igb_gstrings_stats[i].stat_offset;2306 data[i] = (igb_gstrings_stats[i].sizeof_stat ==2307 sizeof(u64)) ? *(u64 *)p : *(u32 *)p;2308 }2309 for (j = 0; j < IGB_NETDEV_STATS_LEN; j++, i++) {2310 p = (char *)net_stats + igb_gstrings_net_stats[j].stat_offset;2311 data[i] = (igb_gstrings_net_stats[j].sizeof_stat ==2312 sizeof(u64)) ? *(u64 *)p : *(u32 *)p;2313 }2314 for (j = 0; j < adapter->num_tx_queues; j++) {2315 u64 restart2;2316 2317 ring = adapter->tx_ring[j];2318 do {2319 start = u64_stats_fetch_begin(&ring->tx_syncp);2320 data[i] = ring->tx_stats.packets;2321 data[i+1] = ring->tx_stats.bytes;2322 data[i+2] = ring->tx_stats.restart_queue;2323 } while (u64_stats_fetch_retry(&ring->tx_syncp, start));2324 do {2325 start = u64_stats_fetch_begin(&ring->tx_syncp2);2326 restart2 = ring->tx_stats.restart_queue2;2327 } while (u64_stats_fetch_retry(&ring->tx_syncp2, start));2328 data[i+2] += restart2;2329 2330 i += IGB_TX_QUEUE_STATS_LEN;2331 }2332 for (j = 0; j < adapter->num_rx_queues; j++) {2333 ring = adapter->rx_ring[j];2334 do {2335 start = u64_stats_fetch_begin(&ring->rx_syncp);2336 data[i] = ring->rx_stats.packets;2337 data[i+1] = ring->rx_stats.bytes;2338 data[i+2] = ring->rx_stats.drops;2339 data[i+3] = ring->rx_stats.csum_err;2340 data[i+4] = ring->rx_stats.alloc_failed;2341 } while (u64_stats_fetch_retry(&ring->rx_syncp, start));2342 i += IGB_RX_QUEUE_STATS_LEN;2343 }2344 spin_unlock(&adapter->stats64_lock);2345}2346 2347static void igb_get_strings(struct net_device *netdev, u32 stringset, u8 *data)2348{2349 struct igb_adapter *adapter = netdev_priv(netdev);2350 u8 *p = data;2351 int i;2352 2353 switch (stringset) {2354 case ETH_SS_TEST:2355 memcpy(data, igb_gstrings_test, sizeof(igb_gstrings_test));2356 break;2357 case ETH_SS_STATS:2358 for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++)2359 ethtool_puts(&p, igb_gstrings_stats[i].stat_string);2360 for (i = 0; i < IGB_NETDEV_STATS_LEN; i++)2361 ethtool_puts(&p, igb_gstrings_net_stats[i].stat_string);2362 for (i = 0; i < adapter->num_tx_queues; i++) {2363 ethtool_sprintf(&p, "tx_queue_%u_packets", i);2364 ethtool_sprintf(&p, "tx_queue_%u_bytes", i);2365 ethtool_sprintf(&p, "tx_queue_%u_restart", i);2366 }2367 for (i = 0; i < adapter->num_rx_queues; i++) {2368 ethtool_sprintf(&p, "rx_queue_%u_packets", i);2369 ethtool_sprintf(&p, "rx_queue_%u_bytes", i);2370 ethtool_sprintf(&p, "rx_queue_%u_drops", i);2371 ethtool_sprintf(&p, "rx_queue_%u_csum_err", i);2372 ethtool_sprintf(&p, "rx_queue_%u_alloc_failed", i);2373 }2374 /* BUG_ON(p - data != IGB_STATS_LEN * ETH_GSTRING_LEN); */2375 break;2376 case ETH_SS_PRIV_FLAGS:2377 memcpy(data, igb_priv_flags_strings,2378 IGB_PRIV_FLAGS_STR_LEN * ETH_GSTRING_LEN);2379 break;2380 }2381}2382 2383static int igb_get_ts_info(struct net_device *dev,2384 struct kernel_ethtool_ts_info *info)2385{2386 struct igb_adapter *adapter = netdev_priv(dev);2387 2388 if (adapter->ptp_clock)2389 info->phc_index = ptp_clock_index(adapter->ptp_clock);2390 2391 switch (adapter->hw.mac.type) {2392 case e1000_82575:2393 info->so_timestamping =2394 SOF_TIMESTAMPING_TX_SOFTWARE;2395 return 0;2396 case e1000_82576:2397 case e1000_82580:2398 case e1000_i350:2399 case e1000_i354:2400 case e1000_i210:2401 case e1000_i211:2402 info->so_timestamping =2403 SOF_TIMESTAMPING_TX_SOFTWARE |2404 SOF_TIMESTAMPING_TX_HARDWARE |2405 SOF_TIMESTAMPING_RX_HARDWARE |2406 SOF_TIMESTAMPING_RAW_HARDWARE;2407 2408 info->tx_types =2409 BIT(HWTSTAMP_TX_OFF) |2410 BIT(HWTSTAMP_TX_ON);2411 2412 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE);2413 2414 /* 82576 does not support timestamping all packets. */2415 if (adapter->hw.mac.type >= e1000_82580)2416 info->rx_filters |= BIT(HWTSTAMP_FILTER_ALL);2417 else2418 info->rx_filters |=2419 BIT(HWTSTAMP_FILTER_PTP_V1_L4_SYNC) |2420 BIT(HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) |2421 BIT(HWTSTAMP_FILTER_PTP_V2_EVENT);2422 2423 return 0;2424 default:2425 return -EOPNOTSUPP;2426 }2427}2428 2429#define ETHER_TYPE_FULL_MASK cpu_to_be16(FIELD_MAX(U16_MAX))2430static int igb_get_ethtool_nfc_entry(struct igb_adapter *adapter,2431 struct ethtool_rxnfc *cmd)2432{2433 struct ethtool_rx_flow_spec *fsp = &cmd->fs;2434 struct igb_nfc_filter *rule = NULL;2435 2436 /* report total rule count */2437 cmd->data = IGB_MAX_RXNFC_FILTERS;2438 2439 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) {2440 if (fsp->location <= rule->sw_idx)2441 break;2442 }2443 2444 if (!rule || fsp->location != rule->sw_idx)2445 return -EINVAL;2446 2447 if (rule->filter.match_flags) {2448 fsp->flow_type = ETHER_FLOW;2449 fsp->ring_cookie = rule->action;2450 if (rule->filter.match_flags & IGB_FILTER_FLAG_ETHER_TYPE) {2451 fsp->h_u.ether_spec.h_proto = rule->filter.etype;2452 fsp->m_u.ether_spec.h_proto = ETHER_TYPE_FULL_MASK;2453 }2454 if (rule->filter.match_flags & IGB_FILTER_FLAG_VLAN_TCI) {2455 fsp->flow_type |= FLOW_EXT;2456 fsp->h_ext.vlan_tci = rule->filter.vlan_tci;2457 fsp->m_ext.vlan_tci = htons(VLAN_PRIO_MASK);2458 }2459 if (rule->filter.match_flags & IGB_FILTER_FLAG_DST_MAC_ADDR) {2460 ether_addr_copy(fsp->h_u.ether_spec.h_dest,2461 rule->filter.dst_addr);2462 /* As we only support matching by the full2463 * mask, return the mask to userspace2464 */2465 eth_broadcast_addr(fsp->m_u.ether_spec.h_dest);2466 }2467 if (rule->filter.match_flags & IGB_FILTER_FLAG_SRC_MAC_ADDR) {2468 ether_addr_copy(fsp->h_u.ether_spec.h_source,2469 rule->filter.src_addr);2470 /* As we only support matching by the full2471 * mask, return the mask to userspace2472 */2473 eth_broadcast_addr(fsp->m_u.ether_spec.h_source);2474 }2475 2476 return 0;2477 }2478 return -EINVAL;2479}2480 2481static int igb_get_ethtool_nfc_all(struct igb_adapter *adapter,2482 struct ethtool_rxnfc *cmd,2483 u32 *rule_locs)2484{2485 struct igb_nfc_filter *rule;2486 int cnt = 0;2487 2488 /* report total rule count */2489 cmd->data = IGB_MAX_RXNFC_FILTERS;2490 2491 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) {2492 if (cnt == cmd->rule_cnt)2493 return -EMSGSIZE;2494 rule_locs[cnt] = rule->sw_idx;2495 cnt++;2496 }2497 2498 cmd->rule_cnt = cnt;2499 2500 return 0;2501}2502 2503static int igb_get_rss_hash_opts(struct igb_adapter *adapter,2504 struct ethtool_rxnfc *cmd)2505{2506 cmd->data = 0;2507 2508 /* Report default options for RSS on igb */2509 switch (cmd->flow_type) {2510 case TCP_V4_FLOW:2511 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;2512 fallthrough;2513 case UDP_V4_FLOW:2514 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)2515 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;2516 fallthrough;2517 case SCTP_V4_FLOW:2518 case AH_ESP_V4_FLOW:2519 case AH_V4_FLOW:2520 case ESP_V4_FLOW:2521 case IPV4_FLOW:2522 cmd->data |= RXH_IP_SRC | RXH_IP_DST;2523 break;2524 case TCP_V6_FLOW:2525 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;2526 fallthrough;2527 case UDP_V6_FLOW:2528 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)2529 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;2530 fallthrough;2531 case SCTP_V6_FLOW:2532 case AH_ESP_V6_FLOW:2533 case AH_V6_FLOW:2534 case ESP_V6_FLOW:2535 case IPV6_FLOW:2536 cmd->data |= RXH_IP_SRC | RXH_IP_DST;2537 break;2538 default:2539 return -EINVAL;2540 }2541 2542 return 0;2543}2544 2545static int igb_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd,2546 u32 *rule_locs)2547{2548 struct igb_adapter *adapter = netdev_priv(dev);2549 int ret = -EOPNOTSUPP;2550 2551 switch (cmd->cmd) {2552 case ETHTOOL_GRXRINGS:2553 cmd->data = adapter->num_rx_queues;2554 ret = 0;2555 break;2556 case ETHTOOL_GRXCLSRLCNT:2557 cmd->rule_cnt = adapter->nfc_filter_count;2558 ret = 0;2559 break;2560 case ETHTOOL_GRXCLSRULE:2561 ret = igb_get_ethtool_nfc_entry(adapter, cmd);2562 break;2563 case ETHTOOL_GRXCLSRLALL:2564 ret = igb_get_ethtool_nfc_all(adapter, cmd, rule_locs);2565 break;2566 case ETHTOOL_GRXFH:2567 ret = igb_get_rss_hash_opts(adapter, cmd);2568 break;2569 default:2570 break;2571 }2572 2573 return ret;2574}2575 2576#define UDP_RSS_FLAGS (IGB_FLAG_RSS_FIELD_IPV4_UDP | \2577 IGB_FLAG_RSS_FIELD_IPV6_UDP)2578static int igb_set_rss_hash_opt(struct igb_adapter *adapter,2579 struct ethtool_rxnfc *nfc)2580{2581 u32 flags = adapter->flags;2582 2583 /* RSS does not support anything other than hashing2584 * to queues on src and dst IPs and ports2585 */2586 if (nfc->data & ~(RXH_IP_SRC | RXH_IP_DST |2587 RXH_L4_B_0_1 | RXH_L4_B_2_3))2588 return -EINVAL;2589 2590 switch (nfc->flow_type) {2591 case TCP_V4_FLOW:2592 case TCP_V6_FLOW:2593 if (!(nfc->data & RXH_IP_SRC) ||2594 !(nfc->data & RXH_IP_DST) ||2595 !(nfc->data & RXH_L4_B_0_1) ||2596 !(nfc->data & RXH_L4_B_2_3))2597 return -EINVAL;2598 break;2599 case UDP_V4_FLOW:2600 if (!(nfc->data & RXH_IP_SRC) ||2601 !(nfc->data & RXH_IP_DST))2602 return -EINVAL;2603 switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) {2604 case 0:2605 flags &= ~IGB_FLAG_RSS_FIELD_IPV4_UDP;2606 break;2607 case (RXH_L4_B_0_1 | RXH_L4_B_2_3):2608 flags |= IGB_FLAG_RSS_FIELD_IPV4_UDP;2609 break;2610 default:2611 return -EINVAL;2612 }2613 break;2614 case UDP_V6_FLOW:2615 if (!(nfc->data & RXH_IP_SRC) ||2616 !(nfc->data & RXH_IP_DST))2617 return -EINVAL;2618 switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) {2619 case 0:2620 flags &= ~IGB_FLAG_RSS_FIELD_IPV6_UDP;2621 break;2622 case (RXH_L4_B_0_1 | RXH_L4_B_2_3):2623 flags |= IGB_FLAG_RSS_FIELD_IPV6_UDP;2624 break;2625 default:2626 return -EINVAL;2627 }2628 break;2629 case AH_ESP_V4_FLOW:2630 case AH_V4_FLOW:2631 case ESP_V4_FLOW:2632 case SCTP_V4_FLOW:2633 case AH_ESP_V6_FLOW:2634 case AH_V6_FLOW:2635 case ESP_V6_FLOW:2636 case SCTP_V6_FLOW:2637 if (!(nfc->data & RXH_IP_SRC) ||2638 !(nfc->data & RXH_IP_DST) ||2639 (nfc->data & RXH_L4_B_0_1) ||2640 (nfc->data & RXH_L4_B_2_3))2641 return -EINVAL;2642 break;2643 default:2644 return -EINVAL;2645 }2646 2647 /* if we changed something we need to update flags */2648 if (flags != adapter->flags) {2649 struct e1000_hw *hw = &adapter->hw;2650 u32 mrqc = rd32(E1000_MRQC);2651 2652 if ((flags & UDP_RSS_FLAGS) &&2653 !(adapter->flags & UDP_RSS_FLAGS))2654 dev_err(&adapter->pdev->dev,2655 "enabling UDP RSS: fragmented packets may arrive out of order to the stack above\n");2656 2657 adapter->flags = flags;2658 2659 /* Perform hash on these packet types */2660 mrqc |= E1000_MRQC_RSS_FIELD_IPV4 |2661 E1000_MRQC_RSS_FIELD_IPV4_TCP |2662 E1000_MRQC_RSS_FIELD_IPV6 |2663 E1000_MRQC_RSS_FIELD_IPV6_TCP;2664 2665 mrqc &= ~(E1000_MRQC_RSS_FIELD_IPV4_UDP |2666 E1000_MRQC_RSS_FIELD_IPV6_UDP);2667 2668 if (flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)2669 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP;2670 2671 if (flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)2672 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP;2673 2674 wr32(E1000_MRQC, mrqc);2675 }2676 2677 return 0;2678}2679 2680static int igb_rxnfc_write_etype_filter(struct igb_adapter *adapter,2681 struct igb_nfc_filter *input)2682{2683 struct e1000_hw *hw = &adapter->hw;2684 u8 i;2685 u32 etqf;2686 u16 etype;2687 2688 /* find an empty etype filter register */2689 for (i = 0; i < MAX_ETYPE_FILTER; ++i) {2690 if (!adapter->etype_bitmap[i])2691 break;2692 }2693 if (i == MAX_ETYPE_FILTER) {2694 dev_err(&adapter->pdev->dev, "ethtool -N: etype filters are all used.\n");2695 return -EINVAL;2696 }2697 2698 adapter->etype_bitmap[i] = true;2699 2700 etqf = rd32(E1000_ETQF(i));2701 etype = ntohs(input->filter.etype & ETHER_TYPE_FULL_MASK);2702 2703 etqf |= E1000_ETQF_FILTER_ENABLE;2704 etqf &= ~E1000_ETQF_ETYPE_MASK;2705 etqf |= (etype & E1000_ETQF_ETYPE_MASK);2706 2707 etqf &= ~E1000_ETQF_QUEUE_MASK;2708 etqf |= FIELD_PREP(E1000_ETQF_QUEUE_MASK, input->action);2709 etqf |= E1000_ETQF_QUEUE_ENABLE;2710 2711 wr32(E1000_ETQF(i), etqf);2712 2713 input->etype_reg_index = i;2714 2715 return 0;2716}2717 2718static int igb_rxnfc_write_vlan_prio_filter(struct igb_adapter *adapter,2719 struct igb_nfc_filter *input)2720{2721 struct e1000_hw *hw = &adapter->hw;2722 u8 vlan_priority;2723 u16 queue_index;2724 u32 vlapqf;2725 2726 vlapqf = rd32(E1000_VLAPQF);2727 vlan_priority = FIELD_GET(VLAN_PRIO_MASK,2728 ntohs(input->filter.vlan_tci));2729 queue_index = (vlapqf >> (vlan_priority * 4)) & E1000_VLAPQF_QUEUE_MASK;2730 2731 /* check whether this vlan prio is already set */2732 if ((vlapqf & E1000_VLAPQF_P_VALID(vlan_priority)) &&2733 (queue_index != input->action)) {2734 dev_err(&adapter->pdev->dev, "ethtool rxnfc set vlan prio filter failed.\n");2735 return -EEXIST;2736 }2737 2738 vlapqf |= E1000_VLAPQF_P_VALID(vlan_priority);2739 vlapqf |= E1000_VLAPQF_QUEUE_SEL(vlan_priority, input->action);2740 2741 wr32(E1000_VLAPQF, vlapqf);2742 2743 return 0;2744}2745 2746int igb_add_filter(struct igb_adapter *adapter, struct igb_nfc_filter *input)2747{2748 struct e1000_hw *hw = &adapter->hw;2749 int err = -EINVAL;2750 2751 if (hw->mac.type == e1000_i210 &&2752 !(input->filter.match_flags & ~IGB_FILTER_FLAG_SRC_MAC_ADDR)) {2753 dev_err(&adapter->pdev->dev,2754 "i210 doesn't support flow classification rules specifying only source addresses.\n");2755 return -EOPNOTSUPP;2756 }2757 2758 if (input->filter.match_flags & IGB_FILTER_FLAG_ETHER_TYPE) {2759 err = igb_rxnfc_write_etype_filter(adapter, input);2760 if (err)2761 return err;2762 }2763 2764 if (input->filter.match_flags & IGB_FILTER_FLAG_DST_MAC_ADDR) {2765 err = igb_add_mac_steering_filter(adapter,2766 input->filter.dst_addr,2767 input->action, 0);2768 err = min_t(int, err, 0);2769 if (err)2770 return err;2771 }2772 2773 if (input->filter.match_flags & IGB_FILTER_FLAG_SRC_MAC_ADDR) {2774 err = igb_add_mac_steering_filter(adapter,2775 input->filter.src_addr,2776 input->action,2777 IGB_MAC_STATE_SRC_ADDR);2778 err = min_t(int, err, 0);2779 if (err)2780 return err;2781 }2782 2783 if (input->filter.match_flags & IGB_FILTER_FLAG_VLAN_TCI)2784 err = igb_rxnfc_write_vlan_prio_filter(adapter, input);2785 2786 return err;2787}2788 2789static void igb_clear_etype_filter_regs(struct igb_adapter *adapter,2790 u16 reg_index)2791{2792 struct e1000_hw *hw = &adapter->hw;2793 u32 etqf = rd32(E1000_ETQF(reg_index));2794 2795 etqf &= ~E1000_ETQF_QUEUE_ENABLE;2796 etqf &= ~E1000_ETQF_QUEUE_MASK;2797 etqf &= ~E1000_ETQF_FILTER_ENABLE;2798 2799 wr32(E1000_ETQF(reg_index), etqf);2800 2801 adapter->etype_bitmap[reg_index] = false;2802}2803 2804static void igb_clear_vlan_prio_filter(struct igb_adapter *adapter,2805 u16 vlan_tci)2806{2807 struct e1000_hw *hw = &adapter->hw;2808 u8 vlan_priority;2809 u32 vlapqf;2810 2811 vlan_priority = FIELD_GET(VLAN_PRIO_MASK, vlan_tci);2812 2813 vlapqf = rd32(E1000_VLAPQF);2814 vlapqf &= ~E1000_VLAPQF_P_VALID(vlan_priority);2815 vlapqf &= ~E1000_VLAPQF_QUEUE_SEL(vlan_priority,2816 E1000_VLAPQF_QUEUE_MASK);2817 2818 wr32(E1000_VLAPQF, vlapqf);2819}2820 2821int igb_erase_filter(struct igb_adapter *adapter, struct igb_nfc_filter *input)2822{2823 if (input->filter.match_flags & IGB_FILTER_FLAG_ETHER_TYPE)2824 igb_clear_etype_filter_regs(adapter,2825 input->etype_reg_index);2826 2827 if (input->filter.match_flags & IGB_FILTER_FLAG_VLAN_TCI)2828 igb_clear_vlan_prio_filter(adapter,2829 ntohs(input->filter.vlan_tci));2830 2831 if (input->filter.match_flags & IGB_FILTER_FLAG_SRC_MAC_ADDR)2832 igb_del_mac_steering_filter(adapter, input->filter.src_addr,2833 input->action,2834 IGB_MAC_STATE_SRC_ADDR);2835 2836 if (input->filter.match_flags & IGB_FILTER_FLAG_DST_MAC_ADDR)2837 igb_del_mac_steering_filter(adapter, input->filter.dst_addr,2838 input->action, 0);2839 2840 return 0;2841}2842 2843static int igb_update_ethtool_nfc_entry(struct igb_adapter *adapter,2844 struct igb_nfc_filter *input,2845 u16 sw_idx)2846{2847 struct igb_nfc_filter *rule, *parent;2848 int err = -EINVAL;2849 2850 parent = NULL;2851 rule = NULL;2852 2853 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) {2854 /* hash found, or no matching entry */2855 if (rule->sw_idx >= sw_idx)2856 break;2857 parent = rule;2858 }2859 2860 /* if there is an old rule occupying our place remove it */2861 if (rule && (rule->sw_idx == sw_idx)) {2862 if (!input)2863 err = igb_erase_filter(adapter, rule);2864 2865 hlist_del(&rule->nfc_node);2866 kfree(rule);2867 adapter->nfc_filter_count--;2868 }2869 2870 /* If no input this was a delete, err should be 0 if a rule was2871 * successfully found and removed from the list else -EINVAL2872 */2873 if (!input)2874 return err;2875 2876 /* initialize node */2877 INIT_HLIST_NODE(&input->nfc_node);2878 2879 /* add filter to the list */2880 if (parent)2881 hlist_add_behind(&input->nfc_node, &parent->nfc_node);2882 else2883 hlist_add_head(&input->nfc_node, &adapter->nfc_filter_list);2884 2885 /* update counts */2886 adapter->nfc_filter_count++;2887 2888 return 0;2889}2890 2891static int igb_add_ethtool_nfc_entry(struct igb_adapter *adapter,2892 struct ethtool_rxnfc *cmd)2893{2894 struct net_device *netdev = adapter->netdev;2895 struct ethtool_rx_flow_spec *fsp =2896 (struct ethtool_rx_flow_spec *)&cmd->fs;2897 struct igb_nfc_filter *input, *rule;2898 int err = 0;2899 2900 if (!(netdev->hw_features & NETIF_F_NTUPLE))2901 return -EOPNOTSUPP;2902 2903 /* Don't allow programming if the action is a queue greater than2904 * the number of online Rx queues.2905 */2906 if ((fsp->ring_cookie == RX_CLS_FLOW_DISC) ||2907 (fsp->ring_cookie >= adapter->num_rx_queues)) {2908 dev_err(&adapter->pdev->dev, "ethtool -N: The specified action is invalid\n");2909 return -EINVAL;2910 }2911 2912 /* Don't allow indexes to exist outside of available space */2913 if (fsp->location >= IGB_MAX_RXNFC_FILTERS) {2914 dev_err(&adapter->pdev->dev, "Location out of range\n");2915 return -EINVAL;2916 }2917 2918 if ((fsp->flow_type & ~FLOW_EXT) != ETHER_FLOW)2919 return -EINVAL;2920 2921 input = kzalloc(sizeof(*input), GFP_KERNEL);2922 if (!input)2923 return -ENOMEM;2924 2925 if (fsp->m_u.ether_spec.h_proto == ETHER_TYPE_FULL_MASK) {2926 input->filter.etype = fsp->h_u.ether_spec.h_proto;2927 input->filter.match_flags = IGB_FILTER_FLAG_ETHER_TYPE;2928 }2929 2930 /* Only support matching addresses by the full mask */2931 if (is_broadcast_ether_addr(fsp->m_u.ether_spec.h_source)) {2932 input->filter.match_flags |= IGB_FILTER_FLAG_SRC_MAC_ADDR;2933 ether_addr_copy(input->filter.src_addr,2934 fsp->h_u.ether_spec.h_source);2935 }2936 2937 /* Only support matching addresses by the full mask */2938 if (is_broadcast_ether_addr(fsp->m_u.ether_spec.h_dest)) {2939 input->filter.match_flags |= IGB_FILTER_FLAG_DST_MAC_ADDR;2940 ether_addr_copy(input->filter.dst_addr,2941 fsp->h_u.ether_spec.h_dest);2942 }2943 2944 if ((fsp->flow_type & FLOW_EXT) && fsp->m_ext.vlan_tci) {2945 if (fsp->m_ext.vlan_tci != htons(VLAN_PRIO_MASK)) {2946 err = -EINVAL;2947 goto err_out;2948 }2949 input->filter.vlan_tci = fsp->h_ext.vlan_tci;2950 input->filter.match_flags |= IGB_FILTER_FLAG_VLAN_TCI;2951 }2952 2953 input->action = fsp->ring_cookie;2954 input->sw_idx = fsp->location;2955 2956 spin_lock(&adapter->nfc_lock);2957 2958 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) {2959 if (!memcmp(&input->filter, &rule->filter,2960 sizeof(input->filter))) {2961 err = -EEXIST;2962 dev_err(&adapter->pdev->dev,2963 "ethtool: this filter is already set\n");2964 goto err_out_w_lock;2965 }2966 }2967 2968 err = igb_add_filter(adapter, input);2969 if (err)2970 goto err_out_w_lock;2971 2972 err = igb_update_ethtool_nfc_entry(adapter, input, input->sw_idx);2973 if (err)2974 goto err_out_input_filter;2975 2976 spin_unlock(&adapter->nfc_lock);2977 return 0;2978 2979err_out_input_filter:2980 igb_erase_filter(adapter, input);2981err_out_w_lock:2982 spin_unlock(&adapter->nfc_lock);2983err_out:2984 kfree(input);2985 return err;2986}2987 2988static int igb_del_ethtool_nfc_entry(struct igb_adapter *adapter,2989 struct ethtool_rxnfc *cmd)2990{2991 struct ethtool_rx_flow_spec *fsp =2992 (struct ethtool_rx_flow_spec *)&cmd->fs;2993 int err;2994 2995 spin_lock(&adapter->nfc_lock);2996 err = igb_update_ethtool_nfc_entry(adapter, NULL, fsp->location);2997 spin_unlock(&adapter->nfc_lock);2998 2999 return err;3000}3001 3002static int igb_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)3003{3004 struct igb_adapter *adapter = netdev_priv(dev);3005 int ret = -EOPNOTSUPP;3006 3007 switch (cmd->cmd) {3008 case ETHTOOL_SRXFH:3009 ret = igb_set_rss_hash_opt(adapter, cmd);3010 break;3011 case ETHTOOL_SRXCLSRLINS:3012 ret = igb_add_ethtool_nfc_entry(adapter, cmd);3013 break;3014 case ETHTOOL_SRXCLSRLDEL:3015 ret = igb_del_ethtool_nfc_entry(adapter, cmd);3016 break;3017 default:3018 break;3019 }3020 3021 return ret;3022}3023 3024static int igb_get_eee(struct net_device *netdev, struct ethtool_keee *edata)3025{3026 struct igb_adapter *adapter = netdev_priv(netdev);3027 struct e1000_hw *hw = &adapter->hw;3028 u32 ret_val;3029 u16 phy_data;3030 3031 if ((hw->mac.type < e1000_i350) ||3032 (hw->phy.media_type != e1000_media_type_copper))3033 return -EOPNOTSUPP;3034 3035 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,3036 edata->supported);3037 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT,3038 edata->supported);3039 if (!hw->dev_spec._82575.eee_disable)3040 mii_eee_cap1_mod_linkmode_t(edata->advertised,3041 adapter->eee_advert);3042 3043 /* The IPCNFG and EEER registers are not supported on I354. */3044 if (hw->mac.type == e1000_i354) {3045 igb_get_eee_status_i354(hw, (bool *)&edata->eee_active);3046 } else {3047 u32 eeer;3048 3049 eeer = rd32(E1000_EEER);3050 3051 /* EEE status on negotiated link */3052 if (eeer & E1000_EEER_EEE_NEG)3053 edata->eee_active = true;3054 3055 if (eeer & E1000_EEER_TX_LPI_EN)3056 edata->tx_lpi_enabled = true;3057 }3058 3059 /* EEE Link Partner Advertised */3060 switch (hw->mac.type) {3061 case e1000_i350:3062 ret_val = igb_read_emi_reg(hw, E1000_EEE_LP_ADV_ADDR_I350,3063 &phy_data);3064 if (ret_val)3065 return -ENODATA;3066 3067 mii_eee_cap1_mod_linkmode_t(edata->lp_advertised, phy_data);3068 break;3069 case e1000_i354:3070 case e1000_i210:3071 case e1000_i211:3072 ret_val = igb_read_xmdio_reg(hw, E1000_EEE_LP_ADV_ADDR_I210,3073 E1000_EEE_LP_ADV_DEV_I210,3074 &phy_data);3075 if (ret_val)3076 return -ENODATA;3077 3078 mii_eee_cap1_mod_linkmode_t(edata->lp_advertised, phy_data);3079 3080 break;3081 default:3082 break;3083 }3084 3085 edata->eee_enabled = !hw->dev_spec._82575.eee_disable;3086 3087 if ((hw->mac.type == e1000_i354) &&3088 (edata->eee_enabled))3089 edata->tx_lpi_enabled = true;3090 3091 /* Report correct negotiated EEE status for devices that3092 * wrongly report EEE at half-duplex3093 */3094 if (adapter->link_duplex == HALF_DUPLEX) {3095 edata->eee_enabled = false;3096 edata->eee_active = false;3097 edata->tx_lpi_enabled = false;3098 linkmode_zero(edata->advertised);3099 }3100 3101 return 0;3102}3103 3104static int igb_set_eee(struct net_device *netdev,3105 struct ethtool_keee *edata)3106{3107 struct igb_adapter *adapter = netdev_priv(netdev);3108 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported) = {};3109 __ETHTOOL_DECLARE_LINK_MODE_MASK(tmp) = {};3110 struct e1000_hw *hw = &adapter->hw;3111 struct ethtool_keee eee_curr;3112 bool adv1g_eee = true, adv100m_eee = true;3113 s32 ret_val;3114 3115 if ((hw->mac.type < e1000_i350) ||3116 (hw->phy.media_type != e1000_media_type_copper))3117 return -EOPNOTSUPP;3118 3119 memset(&eee_curr, 0, sizeof(struct ethtool_keee));3120 3121 ret_val = igb_get_eee(netdev, &eee_curr);3122 if (ret_val)3123 return ret_val;3124 3125 if (eee_curr.eee_enabled) {3126 if (eee_curr.tx_lpi_enabled != edata->tx_lpi_enabled) {3127 dev_err(&adapter->pdev->dev,3128 "Setting EEE tx-lpi is not supported\n");3129 return -EINVAL;3130 }3131 3132 /* Tx LPI timer is not implemented currently */3133 if (edata->tx_lpi_timer) {3134 dev_err(&adapter->pdev->dev,3135 "Setting EEE Tx LPI timer is not supported\n");3136 return -EINVAL;3137 }3138 3139 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,3140 supported);3141 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT,3142 supported);3143 if (linkmode_andnot(tmp, edata->advertised, supported)) {3144 dev_err(&adapter->pdev->dev,3145 "EEE Advertisement supports only 100Tx and/or 100T full duplex\n");3146 return -EINVAL;3147 }3148 adv100m_eee = linkmode_test_bit(3149 ETHTOOL_LINK_MODE_100baseT_Full_BIT,3150 edata->advertised);3151 adv1g_eee = linkmode_test_bit(3152 ETHTOOL_LINK_MODE_1000baseT_Full_BIT,3153 edata->advertised);3154 3155 } else if (!edata->eee_enabled) {3156 dev_err(&adapter->pdev->dev,3157 "Setting EEE options are not supported with EEE disabled\n");3158 return -EINVAL;3159 }3160 3161 adapter->eee_advert = linkmode_to_mii_eee_cap1_t(edata->advertised);3162 if (hw->dev_spec._82575.eee_disable != !edata->eee_enabled) {3163 hw->dev_spec._82575.eee_disable = !edata->eee_enabled;3164 adapter->flags |= IGB_FLAG_EEE;3165 3166 /* reset link */3167 if (netif_running(netdev))3168 igb_reinit_locked(adapter);3169 else3170 igb_reset(adapter);3171 }3172 3173 if (hw->mac.type == e1000_i354)3174 ret_val = igb_set_eee_i354(hw, adv1g_eee, adv100m_eee);3175 else3176 ret_val = igb_set_eee_i350(hw, adv1g_eee, adv100m_eee);3177 3178 if (ret_val) {3179 dev_err(&adapter->pdev->dev,3180 "Problem setting EEE advertisement options\n");3181 return -EINVAL;3182 }3183 3184 return 0;3185}3186 3187static int igb_get_module_info(struct net_device *netdev,3188 struct ethtool_modinfo *modinfo)3189{3190 struct igb_adapter *adapter = netdev_priv(netdev);3191 struct e1000_hw *hw = &adapter->hw;3192 u32 status = 0;3193 u16 sff8472_rev, addr_mode;3194 bool page_swap = false;3195 3196 if ((hw->phy.media_type == e1000_media_type_copper) ||3197 (hw->phy.media_type == e1000_media_type_unknown))3198 return -EOPNOTSUPP;3199 3200 /* Check whether we support SFF-8472 or not */3201 status = igb_read_phy_reg_i2c(hw, IGB_SFF_8472_COMP, &sff8472_rev);3202 if (status)3203 return -EIO;3204 3205 /* addressing mode is not supported */3206 status = igb_read_phy_reg_i2c(hw, IGB_SFF_8472_SWAP, &addr_mode);3207 if (status)3208 return -EIO;3209 3210 /* addressing mode is not supported */3211 if ((addr_mode & 0xFF) & IGB_SFF_ADDRESSING_MODE) {3212 hw_dbg("Address change required to access page 0xA2, but not supported. Please report the module type to the driver maintainers.\n");3213 page_swap = true;3214 }3215 3216 if ((sff8472_rev & 0xFF) == IGB_SFF_8472_UNSUP || page_swap) {3217 /* We have an SFP, but it does not support SFF-8472 */3218 modinfo->type = ETH_MODULE_SFF_8079;3219 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN;3220 } else {3221 /* We have an SFP which supports a revision of SFF-8472 */3222 modinfo->type = ETH_MODULE_SFF_8472;3223 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;3224 }3225 3226 return 0;3227}3228 3229static int igb_get_module_eeprom(struct net_device *netdev,3230 struct ethtool_eeprom *ee, u8 *data)3231{3232 struct igb_adapter *adapter = netdev_priv(netdev);3233 struct e1000_hw *hw = &adapter->hw;3234 u32 status = 0;3235 u16 *dataword;3236 u16 first_word, last_word;3237 int i = 0;3238 3239 if (ee->len == 0)3240 return -EINVAL;3241 3242 first_word = ee->offset >> 1;3243 last_word = (ee->offset + ee->len - 1) >> 1;3244 3245 dataword = kmalloc_array(last_word - first_word + 1, sizeof(u16),3246 GFP_KERNEL);3247 if (!dataword)3248 return -ENOMEM;3249 3250 /* Read EEPROM block, SFF-8079/SFF-8472, word at a time */3251 for (i = 0; i < last_word - first_word + 1; i++) {3252 status = igb_read_phy_reg_i2c(hw, (first_word + i) * 2,3253 &dataword[i]);3254 if (status) {3255 /* Error occurred while reading module */3256 kfree(dataword);3257 return -EIO;3258 }3259 3260 be16_to_cpus(&dataword[i]);3261 }3262 3263 memcpy(data, (u8 *)dataword + (ee->offset & 1), ee->len);3264 kfree(dataword);3265 3266 return 0;3267}3268 3269static u32 igb_get_rxfh_indir_size(struct net_device *netdev)3270{3271 return IGB_RETA_SIZE;3272}3273 3274static int igb_get_rxfh(struct net_device *netdev,3275 struct ethtool_rxfh_param *rxfh)3276{3277 struct igb_adapter *adapter = netdev_priv(netdev);3278 int i;3279 3280 rxfh->hfunc = ETH_RSS_HASH_TOP;3281 if (!rxfh->indir)3282 return 0;3283 for (i = 0; i < IGB_RETA_SIZE; i++)3284 rxfh->indir[i] = adapter->rss_indir_tbl[i];3285 3286 return 0;3287}3288 3289void igb_write_rss_indir_tbl(struct igb_adapter *adapter)3290{3291 struct e1000_hw *hw = &adapter->hw;3292 u32 reg = E1000_RETA(0);3293 u32 shift = 0;3294 int i = 0;3295 3296 switch (hw->mac.type) {3297 case e1000_82575:3298 shift = 6;3299 break;3300 case e1000_82576:3301 /* 82576 supports 2 RSS queues for SR-IOV */3302 if (adapter->vfs_allocated_count)3303 shift = 3;3304 break;3305 default:3306 break;3307 }3308 3309 while (i < IGB_RETA_SIZE) {3310 u32 val = 0;3311 int j;3312 3313 for (j = 3; j >= 0; j--) {3314 val <<= 8;3315 val |= adapter->rss_indir_tbl[i + j];3316 }3317 3318 wr32(reg, val << shift);3319 reg += 4;3320 i += 4;3321 }3322}3323 3324static int igb_set_rxfh(struct net_device *netdev,3325 struct ethtool_rxfh_param *rxfh,3326 struct netlink_ext_ack *extack)3327{3328 struct igb_adapter *adapter = netdev_priv(netdev);3329 struct e1000_hw *hw = &adapter->hw;3330 int i;3331 u32 num_queues;3332 3333 /* We do not allow change in unsupported parameters */3334 if (rxfh->key ||3335 (rxfh->hfunc != ETH_RSS_HASH_NO_CHANGE &&3336 rxfh->hfunc != ETH_RSS_HASH_TOP))3337 return -EOPNOTSUPP;3338 if (!rxfh->indir)3339 return 0;3340 3341 num_queues = adapter->rss_queues;3342 3343 switch (hw->mac.type) {3344 case e1000_82576:3345 /* 82576 supports 2 RSS queues for SR-IOV */3346 if (adapter->vfs_allocated_count)3347 num_queues = 2;3348 break;3349 default:3350 break;3351 }3352 3353 /* Verify user input. */3354 for (i = 0; i < IGB_RETA_SIZE; i++)3355 if (rxfh->indir[i] >= num_queues)3356 return -EINVAL;3357 3358 3359 for (i = 0; i < IGB_RETA_SIZE; i++)3360 adapter->rss_indir_tbl[i] = rxfh->indir[i];3361 3362 igb_write_rss_indir_tbl(adapter);3363 3364 return 0;3365}3366 3367static unsigned int igb_max_channels(struct igb_adapter *adapter)3368{3369 return igb_get_max_rss_queues(adapter);3370}3371 3372static void igb_get_channels(struct net_device *netdev,3373 struct ethtool_channels *ch)3374{3375 struct igb_adapter *adapter = netdev_priv(netdev);3376 3377 /* Report maximum channels */3378 ch->max_combined = igb_max_channels(adapter);3379 3380 /* Report info for other vector */3381 if (adapter->flags & IGB_FLAG_HAS_MSIX) {3382 ch->max_other = NON_Q_VECTORS;3383 ch->other_count = NON_Q_VECTORS;3384 }3385 3386 ch->combined_count = adapter->rss_queues;3387}3388 3389static int igb_set_channels(struct net_device *netdev,3390 struct ethtool_channels *ch)3391{3392 struct igb_adapter *adapter = netdev_priv(netdev);3393 unsigned int count = ch->combined_count;3394 unsigned int max_combined = 0;3395 3396 /* Verify they are not requesting separate vectors */3397 if (!count || ch->rx_count || ch->tx_count)3398 return -EINVAL;3399 3400 /* Verify other_count is valid and has not been changed */3401 if (ch->other_count != NON_Q_VECTORS)3402 return -EINVAL;3403 3404 /* Verify the number of channels doesn't exceed hw limits */3405 max_combined = igb_max_channels(adapter);3406 if (count > max_combined)3407 return -EINVAL;3408 3409 if (count != adapter->rss_queues) {3410 adapter->rss_queues = count;3411 igb_set_flag_queue_pairs(adapter, max_combined);3412 3413 /* Hardware has to reinitialize queues and interrupts to3414 * match the new configuration.3415 */3416 return igb_reinit_queues(adapter);3417 }3418 3419 return 0;3420}3421 3422static u32 igb_get_priv_flags(struct net_device *netdev)3423{3424 struct igb_adapter *adapter = netdev_priv(netdev);3425 u32 priv_flags = 0;3426 3427 if (adapter->flags & IGB_FLAG_RX_LEGACY)3428 priv_flags |= IGB_PRIV_FLAGS_LEGACY_RX;3429 3430 return priv_flags;3431}3432 3433static int igb_set_priv_flags(struct net_device *netdev, u32 priv_flags)3434{3435 struct igb_adapter *adapter = netdev_priv(netdev);3436 unsigned int flags = adapter->flags;3437 3438 flags &= ~IGB_FLAG_RX_LEGACY;3439 if (priv_flags & IGB_PRIV_FLAGS_LEGACY_RX)3440 flags |= IGB_FLAG_RX_LEGACY;3441 3442 if (flags != adapter->flags) {3443 adapter->flags = flags;3444 3445 /* reset interface to repopulate queues */3446 if (netif_running(netdev))3447 igb_reinit_locked(adapter);3448 }3449 3450 return 0;3451}3452 3453static const struct ethtool_ops igb_ethtool_ops = {3454 .supported_coalesce_params = ETHTOOL_COALESCE_USECS,3455 .get_drvinfo = igb_get_drvinfo,3456 .get_regs_len = igb_get_regs_len,3457 .get_regs = igb_get_regs,3458 .get_wol = igb_get_wol,3459 .set_wol = igb_set_wol,3460 .get_msglevel = igb_get_msglevel,3461 .set_msglevel = igb_set_msglevel,3462 .nway_reset = igb_nway_reset,3463 .get_link = igb_get_link,3464 .get_eeprom_len = igb_get_eeprom_len,3465 .get_eeprom = igb_get_eeprom,3466 .set_eeprom = igb_set_eeprom,3467 .get_ringparam = igb_get_ringparam,3468 .set_ringparam = igb_set_ringparam,3469 .get_pauseparam = igb_get_pauseparam,3470 .set_pauseparam = igb_set_pauseparam,3471 .self_test = igb_diag_test,3472 .get_strings = igb_get_strings,3473 .set_phys_id = igb_set_phys_id,3474 .get_sset_count = igb_get_sset_count,3475 .get_ethtool_stats = igb_get_ethtool_stats,3476 .get_coalesce = igb_get_coalesce,3477 .set_coalesce = igb_set_coalesce,3478 .get_ts_info = igb_get_ts_info,3479 .get_rxnfc = igb_get_rxnfc,3480 .set_rxnfc = igb_set_rxnfc,3481 .get_eee = igb_get_eee,3482 .set_eee = igb_set_eee,3483 .get_module_info = igb_get_module_info,3484 .get_module_eeprom = igb_get_module_eeprom,3485 .get_rxfh_indir_size = igb_get_rxfh_indir_size,3486 .get_rxfh = igb_get_rxfh,3487 .set_rxfh = igb_set_rxfh,3488 .get_channels = igb_get_channels,3489 .set_channels = igb_set_channels,3490 .get_priv_flags = igb_get_priv_flags,3491 .set_priv_flags = igb_set_priv_flags,3492 .get_link_ksettings = igb_get_link_ksettings,3493 .set_link_ksettings = igb_set_link_ksettings,3494};3495 3496void igb_set_ethtool_ops(struct net_device *netdev)3497{3498 netdev->ethtool_ops = &igb_ethtool_ops;3499}3500