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1/* SPDX-License-Identifier: GPL-2.0 */2/* Copyright (c) 2018 Intel Corporation */3 4#ifndef _IGC_H_5#define _IGC_H_6 7#include <linux/kobject.h>8#include <linux/pci.h>9#include <linux/netdevice.h>10#include <linux/vmalloc.h>11#include <linux/ethtool.h>12#include <linux/sctp.h>13#include <linux/ptp_clock_kernel.h>14#include <linux/timecounter.h>15#include <linux/net_tstamp.h>16#include <linux/bitfield.h>17#include <linux/hrtimer.h>18#include <net/xdp.h>19 20#include "igc_hw.h"21 22void igc_ethtool_set_ops(struct net_device *);23 24/* Transmit and receive queues */25#define IGC_MAX_RX_QUEUES 426#define IGC_MAX_TX_QUEUES 427 28#define MAX_Q_VECTORS 829#define MAX_STD_JUMBO_FRAME_SIZE 921630 31#define MAX_ETYPE_FILTER 832#define IGC_RETA_SIZE 12833 34/* SDP support */35#define IGC_N_EXTTS 236#define IGC_N_PEROUT 237#define IGC_N_SDP 438 39#define MAX_FLEX_FILTER 3240 41#define IGC_MAX_TX_TSTAMP_REGS 442 43enum igc_mac_filter_type {44 IGC_MAC_FILTER_TYPE_DST = 0,45 IGC_MAC_FILTER_TYPE_SRC46};47 48struct igc_tx_queue_stats {49 u64 packets;50 u64 bytes;51 u64 restart_queue;52 u64 restart_queue2;53};54 55struct igc_rx_queue_stats {56 u64 packets;57 u64 bytes;58 u64 drops;59 u64 csum_err;60 u64 alloc_failed;61};62 63struct igc_rx_packet_stats {64 u64 ipv4_packets; /* IPv4 headers processed */65 u64 ipv4e_packets; /* IPv4E headers with extensions processed */66 u64 ipv6_packets; /* IPv6 headers processed */67 u64 ipv6e_packets; /* IPv6E headers with extensions processed */68 u64 tcp_packets; /* TCP headers processed */69 u64 udp_packets; /* UDP headers processed */70 u64 sctp_packets; /* SCTP headers processed */71 u64 nfs_packets; /* NFS headers processe */72 u64 other_packets;73};74 75enum igc_tx_buffer_type {76 IGC_TX_BUFFER_TYPE_SKB,77 IGC_TX_BUFFER_TYPE_XDP,78 IGC_TX_BUFFER_TYPE_XSK,79};80 81/* wrapper around a pointer to a socket buffer,82 * so a DMA handle can be stored along with the buffer83 */84struct igc_tx_buffer {85 union igc_adv_tx_desc *next_to_watch;86 unsigned long time_stamp;87 enum igc_tx_buffer_type type;88 union {89 struct sk_buff *skb;90 struct xdp_frame *xdpf;91 };92 unsigned int bytecount;93 u16 gso_segs;94 __be16 protocol;95 96 DEFINE_DMA_UNMAP_ADDR(dma);97 DEFINE_DMA_UNMAP_LEN(len);98 u32 tx_flags;99 bool xsk_pending_ts;100};101 102struct igc_tx_timestamp_request {103 union { /* reference to the packet being timestamped */104 struct sk_buff *skb;105 struct igc_tx_buffer *xsk_tx_buffer;106 };107 enum igc_tx_buffer_type buffer_type;108 unsigned long start; /* when the tstamp request started (jiffies) */109 u32 mask; /* _TSYNCTXCTL_TXTT_{X} bit for this request */110 u32 regl; /* which TXSTMPL_{X} register should be used */111 u32 regh; /* which TXSTMPH_{X} register should be used */112 u32 flags; /* flags that should be added to the tx_buffer */113 u8 xsk_queue_index; /* Tx queue which requesting timestamp */114 struct xsk_tx_metadata_compl xsk_meta; /* ref to xsk Tx metadata */115};116 117struct igc_inline_rx_tstamps {118 /* Timestamps are saved in little endian at the beginning of the packet119 * buffer following the layout:120 *121 * DWORD: | 0 | 1 | 2 | 3 |122 * Field: | Timer1 SYSTIML | Timer1 SYSTIMH | Timer0 SYSTIML | Timer0 SYSTIMH |123 *124 * SYSTIML holds the nanoseconds part while SYSTIMH holds the seconds125 * part of the timestamp.126 *127 */128 __le32 timer1[2];129 __le32 timer0[2];130};131 132struct igc_ring_container {133 struct igc_ring *ring; /* pointer to linked list of rings */134 unsigned int total_bytes; /* total bytes processed this int */135 unsigned int total_packets; /* total packets processed this int */136 u16 work_limit; /* total work allowed per interrupt */137 u8 count; /* total number of rings in vector */138 u8 itr; /* current ITR setting for ring */139};140 141struct igc_ring {142 struct igc_q_vector *q_vector; /* backlink to q_vector */143 struct net_device *netdev; /* back pointer to net_device */144 struct device *dev; /* device for dma mapping */145 union { /* array of buffer info structs */146 struct igc_tx_buffer *tx_buffer_info;147 struct igc_rx_buffer *rx_buffer_info;148 };149 void *desc; /* descriptor ring memory */150 unsigned long flags; /* ring specific flags */151 void __iomem *tail; /* pointer to ring tail register */152 dma_addr_t dma; /* phys address of the ring */153 unsigned int size; /* length of desc. ring in bytes */154 155 u16 count; /* number of desc. in the ring */156 u8 queue_index; /* logical index of the ring*/157 u8 reg_idx; /* physical index of the ring */158 bool launchtime_enable; /* true if LaunchTime is enabled */159 ktime_t last_tx_cycle; /* end of the cycle with a launchtime transmission */160 ktime_t last_ff_cycle; /* Last cycle with an active first flag */161 162 u32 start_time;163 u32 end_time;164 u32 max_sdu;165 bool oper_gate_closed; /* Operating gate. True if the TX Queue is closed */166 bool admin_gate_closed; /* Future gate. True if the TX Queue will be closed */167 168 /* CBS parameters */169 bool cbs_enable; /* indicates if CBS is enabled */170 s32 idleslope; /* idleSlope in kbps */171 s32 sendslope; /* sendSlope in kbps */172 s32 hicredit; /* hiCredit in bytes */173 s32 locredit; /* loCredit in bytes */174 175 /* everything past this point are written often */176 u16 next_to_clean;177 u16 next_to_use;178 u16 next_to_alloc;179 180 union {181 /* TX */182 struct {183 struct igc_tx_queue_stats tx_stats;184 struct u64_stats_sync tx_syncp;185 struct u64_stats_sync tx_syncp2;186 };187 /* RX */188 struct {189 struct igc_rx_queue_stats rx_stats;190 struct igc_rx_packet_stats pkt_stats;191 struct u64_stats_sync rx_syncp;192 struct sk_buff *skb;193 };194 };195 196 struct xdp_rxq_info xdp_rxq;197 struct xsk_buff_pool *xsk_pool;198} ____cacheline_internodealigned_in_smp;199 200/* Board specific private data structure */201struct igc_adapter {202 struct net_device *netdev;203 204 struct ethtool_keee eee;205 206 unsigned long state;207 unsigned int flags;208 unsigned int num_q_vectors;209 210 struct msix_entry *msix_entries;211 212 /* TX */213 u16 tx_work_limit;214 u32 tx_timeout_count;215 int num_tx_queues;216 struct igc_ring *tx_ring[IGC_MAX_TX_QUEUES];217 218 /* RX */219 int num_rx_queues;220 struct igc_ring *rx_ring[IGC_MAX_RX_QUEUES];221 222 struct timer_list watchdog_timer;223 struct timer_list dma_err_timer;224 struct timer_list phy_info_timer;225 struct hrtimer hrtimer;226 227 u32 wol;228 u32 en_mng_pt;229 u16 link_speed;230 u16 link_duplex;231 232 u8 port_num;233 234 u8 __iomem *io_addr;235 /* Interrupt Throttle Rate */236 u32 rx_itr_setting;237 u32 tx_itr_setting;238 239 struct work_struct reset_task;240 struct work_struct watchdog_task;241 struct work_struct dma_err_task;242 bool fc_autoneg;243 244 u8 tx_timeout_factor;245 246 int msg_enable;247 u32 max_frame_size;248 u32 min_frame_size;249 250 int tc_setup_type;251 ktime_t base_time;252 ktime_t cycle_time;253 bool taprio_offload_enable;254 u32 qbv_config_change_errors;255 bool qbv_transition;256 unsigned int qbv_count;257 /* Access to oper_gate_closed, admin_gate_closed and qbv_transition258 * are protected by the qbv_tx_lock.259 */260 spinlock_t qbv_tx_lock;261 262 bool strict_priority_enable;263 u8 num_tc;264 u16 queue_per_tc[IGC_MAX_TX_QUEUES];265 266 /* OS defined structs */267 struct pci_dev *pdev;268 /* lock for statistics */269 spinlock_t stats64_lock;270 struct rtnl_link_stats64 stats64;271 272 /* structs defined in igc_hw.h */273 struct igc_hw hw;274 struct igc_hw_stats stats;275 276 struct igc_q_vector *q_vector[MAX_Q_VECTORS];277 u32 eims_enable_mask;278 u32 eims_other;279 280 u16 tx_ring_count;281 u16 rx_ring_count;282 283 u32 tx_hwtstamp_timeouts;284 u32 tx_hwtstamp_skipped;285 u32 rx_hwtstamp_cleared;286 287 u32 rss_queues;288 u32 rss_indir_tbl_init;289 290 /* Any access to elements in nfc_rule_list is protected by the291 * nfc_rule_lock.292 */293 struct mutex nfc_rule_lock;294 struct list_head nfc_rule_list;295 unsigned int nfc_rule_count;296 297 u8 rss_indir_tbl[IGC_RETA_SIZE];298 299 unsigned long link_check_timeout;300 struct igc_info ei;301 302 u32 test_icr;303 304 struct ptp_clock *ptp_clock;305 struct ptp_clock_info ptp_caps;306 /* Access to ptp_tx_skb and ptp_tx_start are protected by the307 * ptp_tx_lock.308 */309 spinlock_t ptp_tx_lock;310 struct igc_tx_timestamp_request tx_tstamp[IGC_MAX_TX_TSTAMP_REGS];311 struct hwtstamp_config tstamp_config;312 unsigned int ptp_flags;313 /* System time value lock */314 spinlock_t tmreg_lock;315 /* Free-running timer lock */316 spinlock_t free_timer_lock;317 struct cyclecounter cc;318 struct timecounter tc;319 struct timespec64 prev_ptp_time; /* Pre-reset PTP clock */320 ktime_t ptp_reset_start; /* Reset time in clock mono */321 struct system_time_snapshot snapshot;322 323 char fw_version[32];324 325 struct bpf_prog *xdp_prog;326 327 bool pps_sys_wrap_on;328 329 struct ptp_pin_desc sdp_config[IGC_N_SDP];330 struct {331 struct timespec64 start;332 struct timespec64 period;333 } perout[IGC_N_PEROUT];334 335 /* LEDs */336 struct mutex led_mutex;337 struct igc_led_classdev *leds;338};339 340void igc_up(struct igc_adapter *adapter);341void igc_down(struct igc_adapter *adapter);342int igc_open(struct net_device *netdev);343int igc_close(struct net_device *netdev);344int igc_setup_tx_resources(struct igc_ring *ring);345int igc_setup_rx_resources(struct igc_ring *ring);346void igc_free_tx_resources(struct igc_ring *ring);347void igc_free_rx_resources(struct igc_ring *ring);348unsigned int igc_get_max_rss_queues(struct igc_adapter *adapter);349void igc_set_flag_queue_pairs(struct igc_adapter *adapter,350 const u32 max_rss_queues);351int igc_reinit_queues(struct igc_adapter *adapter);352void igc_write_rss_indir_tbl(struct igc_adapter *adapter);353bool igc_has_link(struct igc_adapter *adapter);354void igc_reset(struct igc_adapter *adapter);355void igc_update_stats(struct igc_adapter *adapter);356void igc_disable_rx_ring(struct igc_ring *ring);357void igc_enable_rx_ring(struct igc_ring *ring);358void igc_disable_tx_ring(struct igc_ring *ring);359void igc_enable_tx_ring(struct igc_ring *ring);360int igc_xsk_wakeup(struct net_device *dev, u32 queue_id, u32 flags);361 362/* AF_XDP TX metadata operations */363extern const struct xsk_tx_metadata_ops igc_xsk_tx_metadata_ops;364 365/* igc_dump declarations */366void igc_rings_dump(struct igc_adapter *adapter);367void igc_regs_dump(struct igc_adapter *adapter);368 369extern char igc_driver_name[];370 371#define IGC_REGS_LEN 740372 373/* flags controlling PTP/1588 function */374#define IGC_PTP_ENABLED BIT(0)375 376/* Flags definitions */377#define IGC_FLAG_HAS_MSI BIT(0)378#define IGC_FLAG_QUEUE_PAIRS BIT(3)379#define IGC_FLAG_DMAC BIT(4)380#define IGC_FLAG_PTP BIT(8)381#define IGC_FLAG_WOL_SUPPORTED BIT(8)382#define IGC_FLAG_NEED_LINK_UPDATE BIT(9)383#define IGC_FLAG_HAS_MSIX BIT(13)384#define IGC_FLAG_EEE BIT(14)385#define IGC_FLAG_VLAN_PROMISC BIT(15)386#define IGC_FLAG_RX_LEGACY BIT(16)387#define IGC_FLAG_TSN_QBV_ENABLED BIT(17)388#define IGC_FLAG_TSN_QAV_ENABLED BIT(18)389#define IGC_FLAG_TSN_LEGACY_ENABLED BIT(19)390 391#define IGC_FLAG_TSN_ANY_ENABLED \392 (IGC_FLAG_TSN_QBV_ENABLED | IGC_FLAG_TSN_QAV_ENABLED | \393 IGC_FLAG_TSN_LEGACY_ENABLED)394 395#define IGC_FLAG_RSS_FIELD_IPV4_UDP BIT(6)396#define IGC_FLAG_RSS_FIELD_IPV6_UDP BIT(7)397 398#define IGC_MRQC_ENABLE_RSS_MQ 0x00000002399#define IGC_MRQC_RSS_FIELD_IPV4_UDP 0x00400000400#define IGC_MRQC_RSS_FIELD_IPV6_UDP 0x00800000401 402/* RX-desc Write-Back format RSS Type's */403enum igc_rss_type_num {404 IGC_RSS_TYPE_NO_HASH = 0,405 IGC_RSS_TYPE_HASH_TCP_IPV4 = 1,406 IGC_RSS_TYPE_HASH_IPV4 = 2,407 IGC_RSS_TYPE_HASH_TCP_IPV6 = 3,408 IGC_RSS_TYPE_HASH_IPV6_EX = 4,409 IGC_RSS_TYPE_HASH_IPV6 = 5,410 IGC_RSS_TYPE_HASH_TCP_IPV6_EX = 6,411 IGC_RSS_TYPE_HASH_UDP_IPV4 = 7,412 IGC_RSS_TYPE_HASH_UDP_IPV6 = 8,413 IGC_RSS_TYPE_HASH_UDP_IPV6_EX = 9,414 IGC_RSS_TYPE_MAX = 10,415};416#define IGC_RSS_TYPE_MAX_TABLE 16417#define IGC_RSS_TYPE_MASK GENMASK(3,0) /* 4-bits (3:0) = mask 0x0F */418 419/* igc_rss_type - Rx descriptor RSS type field */420static inline u32 igc_rss_type(const union igc_adv_rx_desc *rx_desc)421{422 /* RSS Type 4-bits (3:0) number: 0-9 (above 9 is reserved)423 * Accessing the same bits via u16 (wb.lower.lo_dword.hs_rss.pkt_info)424 * is slightly slower than via u32 (wb.lower.lo_dword.data)425 */426 return le32_get_bits(rx_desc->wb.lower.lo_dword.data, IGC_RSS_TYPE_MASK);427}428 429/* Interrupt defines */430#define IGC_START_ITR 648 /* ~6000 ints/sec */431#define IGC_4K_ITR 980432#define IGC_20K_ITR 196433#define IGC_70K_ITR 56434 435#define IGC_DEFAULT_ITR 3 /* dynamic */436#define IGC_MAX_ITR_USECS 10000437#define IGC_MIN_ITR_USECS 10438#define NON_Q_VECTORS 1439#define MAX_MSIX_ENTRIES 10440 441/* TX/RX descriptor defines */442#define IGC_DEFAULT_TXD 256443#define IGC_DEFAULT_TX_WORK 128444#define IGC_MIN_TXD 64445#define IGC_MAX_TXD 4096446 447#define IGC_DEFAULT_RXD 256448#define IGC_MIN_RXD 64449#define IGC_MAX_RXD 4096450 451/* Supported Rx Buffer Sizes */452#define IGC_RXBUFFER_256 256453#define IGC_RXBUFFER_2048 2048454#define IGC_RXBUFFER_3072 3072455 456#define AUTO_ALL_MODES 0457#define IGC_RX_HDR_LEN IGC_RXBUFFER_256458 459/* Transmit and receive latency (for PTP timestamps) */460#define IGC_I225_TX_LATENCY_10 240461#define IGC_I225_TX_LATENCY_100 58462#define IGC_I225_TX_LATENCY_1000 80463#define IGC_I225_TX_LATENCY_2500 1325464#define IGC_I225_RX_LATENCY_10 6450465#define IGC_I225_RX_LATENCY_100 185466#define IGC_I225_RX_LATENCY_1000 300467#define IGC_I225_RX_LATENCY_2500 1485468 469/* RX and TX descriptor control thresholds.470 * PTHRESH - MAC will consider prefetch if it has fewer than this number of471 * descriptors available in its onboard memory.472 * Setting this to 0 disables RX descriptor prefetch.473 * HTHRESH - MAC will only prefetch if there are at least this many descriptors474 * available in host memory.475 * If PTHRESH is 0, this should also be 0.476 * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back477 * descriptors until either it has this many to write back, or the478 * ITR timer expires.479 */480#define IGC_RX_PTHRESH 8481#define IGC_RX_HTHRESH 8482#define IGC_TX_PTHRESH 8483#define IGC_TX_HTHRESH 1484#define IGC_RX_WTHRESH 4485#define IGC_TX_WTHRESH 16486 487#define IGC_RX_DMA_ATTR \488 (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING)489 490#define IGC_TS_HDR_LEN 16491 492#define IGC_SKB_PAD (NET_SKB_PAD + NET_IP_ALIGN)493 494#if (PAGE_SIZE < 8192)495#define IGC_MAX_FRAME_BUILD_SKB \496 (SKB_WITH_OVERHEAD(IGC_RXBUFFER_2048) - IGC_SKB_PAD - IGC_TS_HDR_LEN)497#else498#define IGC_MAX_FRAME_BUILD_SKB (IGC_RXBUFFER_2048 - IGC_TS_HDR_LEN)499#endif500 501/* How many Rx Buffers do we bundle into one write to the hardware ? */502#define IGC_RX_BUFFER_WRITE 16 /* Must be power of 2 */503 504/* VLAN info */505#define IGC_TX_FLAGS_VLAN_MASK 0xffff0000506#define IGC_TX_FLAGS_VLAN_SHIFT 16507 508/* igc_test_staterr - tests bits within Rx descriptor status and error fields */509static inline __le32 igc_test_staterr(union igc_adv_rx_desc *rx_desc,510 const u32 stat_err_bits)511{512 return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits);513}514 515enum igc_state_t {516 __IGC_TESTING,517 __IGC_RESETTING,518 __IGC_DOWN,519};520 521enum igc_tx_flags {522 /* cmd_type flags */523 IGC_TX_FLAGS_VLAN = 0x01,524 IGC_TX_FLAGS_TSO = 0x02,525 IGC_TX_FLAGS_TSTAMP = 0x04,526 527 /* olinfo flags */528 IGC_TX_FLAGS_IPV4 = 0x10,529 IGC_TX_FLAGS_CSUM = 0x20,530 531 IGC_TX_FLAGS_TSTAMP_1 = 0x100,532 IGC_TX_FLAGS_TSTAMP_2 = 0x200,533 IGC_TX_FLAGS_TSTAMP_3 = 0x400,534 535 IGC_TX_FLAGS_TSTAMP_TIMER_1 = 0x800,536};537 538enum igc_boards {539 board_base,540};541 542/* The largest size we can write to the descriptor is 65535. In order to543 * maintain a power of two alignment we have to limit ourselves to 32K.544 */545#define IGC_MAX_TXD_PWR 15546#define IGC_MAX_DATA_PER_TXD BIT(IGC_MAX_TXD_PWR)547 548/* Tx Descriptors needed, worst case */549#define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IGC_MAX_DATA_PER_TXD)550#define DESC_NEEDED (MAX_SKB_FRAGS + 4)551 552struct igc_rx_buffer {553 union {554 struct {555 dma_addr_t dma;556 struct page *page;557#if (BITS_PER_LONG > 32) || (PAGE_SIZE >= 65536)558 __u32 page_offset;559#else560 __u16 page_offset;561#endif562 __u16 pagecnt_bias;563 };564 struct xdp_buff *xdp;565 };566};567 568/* context wrapper around xdp_buff to provide access to descriptor metadata */569struct igc_xdp_buff {570 struct xdp_buff xdp;571 union igc_adv_rx_desc *rx_desc;572 struct igc_inline_rx_tstamps *rx_ts; /* data indication bit IGC_RXDADV_STAT_TSIP */573};574 575struct igc_metadata_request {576 struct igc_tx_buffer *tx_buffer;577 struct xsk_tx_metadata *meta;578 struct igc_ring *tx_ring;579 u32 cmd_type;580};581 582struct igc_q_vector {583 struct igc_adapter *adapter; /* backlink */584 void __iomem *itr_register;585 u32 eims_value; /* EIMS mask value */586 587 u16 itr_val;588 u8 set_itr;589 590 struct igc_ring_container rx, tx;591 592 struct napi_struct napi;593 594 struct rcu_head rcu; /* to avoid race with update stats on free */595 char name[IFNAMSIZ + 9];596 597 /* for dynamic allocation of rings associated with this q_vector */598 struct igc_ring ring[] ____cacheline_internodealigned_in_smp;599};600 601enum igc_filter_match_flags {602 IGC_FILTER_FLAG_ETHER_TYPE = BIT(0),603 IGC_FILTER_FLAG_VLAN_TCI = BIT(1),604 IGC_FILTER_FLAG_SRC_MAC_ADDR = BIT(2),605 IGC_FILTER_FLAG_DST_MAC_ADDR = BIT(3),606 IGC_FILTER_FLAG_USER_DATA = BIT(4),607 IGC_FILTER_FLAG_VLAN_ETYPE = BIT(5),608};609 610struct igc_nfc_filter {611 u8 match_flags;612 u16 etype;613 u16 vlan_etype;614 u16 vlan_tci;615 u16 vlan_tci_mask;616 u8 src_addr[ETH_ALEN];617 u8 dst_addr[ETH_ALEN];618 u8 user_data[8];619 u8 user_mask[8];620 u8 flex_index;621 u8 rx_queue;622 u8 prio;623 u8 immediate_irq;624 u8 drop;625};626 627struct igc_nfc_rule {628 struct list_head list;629 struct igc_nfc_filter filter;630 u32 location;631 u16 action;632 bool flex;633};634 635/* IGC supports a total of 32 NFC rules: 16 MAC address based, 8 VLAN priority636 * based, 8 ethertype based and 32 Flex filter based rules.637 */638#define IGC_MAX_RXNFC_RULES 64639 640struct igc_flex_filter {641 u8 index;642 u8 data[128];643 u8 mask[16];644 u8 length;645 u8 rx_queue;646 u8 prio;647 u8 immediate_irq;648 u8 drop;649};650 651/* igc_desc_unused - calculate if we have unused descriptors */652static inline u16 igc_desc_unused(const struct igc_ring *ring)653{654 u16 ntc = ring->next_to_clean;655 u16 ntu = ring->next_to_use;656 657 return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1;658}659 660static inline s32 igc_get_phy_info(struct igc_hw *hw)661{662 if (hw->phy.ops.get_phy_info)663 return hw->phy.ops.get_phy_info(hw);664 665 return 0;666}667 668static inline s32 igc_reset_phy(struct igc_hw *hw)669{670 if (hw->phy.ops.reset)671 return hw->phy.ops.reset(hw);672 673 return 0;674}675 676static inline struct netdev_queue *txring_txq(const struct igc_ring *tx_ring)677{678 return netdev_get_tx_queue(tx_ring->netdev, tx_ring->queue_index);679}680 681enum igc_ring_flags_t {682 IGC_RING_FLAG_RX_3K_BUFFER,683 IGC_RING_FLAG_RX_BUILD_SKB_ENABLED,684 IGC_RING_FLAG_RX_SCTP_CSUM,685 IGC_RING_FLAG_RX_LB_VLAN_BSWAP,686 IGC_RING_FLAG_TX_CTX_IDX,687 IGC_RING_FLAG_TX_DETECT_HANG,688 IGC_RING_FLAG_AF_XDP_ZC,689 IGC_RING_FLAG_TX_HWTSTAMP,690 IGC_RING_FLAG_RX_ALLOC_FAILED,691};692 693#define ring_uses_large_buffer(ring) \694 test_bit(IGC_RING_FLAG_RX_3K_BUFFER, &(ring)->flags)695#define set_ring_uses_large_buffer(ring) \696 set_bit(IGC_RING_FLAG_RX_3K_BUFFER, &(ring)->flags)697#define clear_ring_uses_large_buffer(ring) \698 clear_bit(IGC_RING_FLAG_RX_3K_BUFFER, &(ring)->flags)699 700#define ring_uses_build_skb(ring) \701 test_bit(IGC_RING_FLAG_RX_BUILD_SKB_ENABLED, &(ring)->flags)702 703static inline unsigned int igc_rx_bufsz(struct igc_ring *ring)704{705#if (PAGE_SIZE < 8192)706 if (ring_uses_large_buffer(ring))707 return IGC_RXBUFFER_3072;708 709 if (ring_uses_build_skb(ring))710 return IGC_MAX_FRAME_BUILD_SKB + IGC_TS_HDR_LEN;711#endif712 return IGC_RXBUFFER_2048;713}714 715static inline unsigned int igc_rx_pg_order(struct igc_ring *ring)716{717#if (PAGE_SIZE < 8192)718 if (ring_uses_large_buffer(ring))719 return 1;720#endif721 return 0;722}723 724static inline s32 igc_read_phy_reg(struct igc_hw *hw, u32 offset, u16 *data)725{726 if (hw->phy.ops.read_reg)727 return hw->phy.ops.read_reg(hw, offset, data);728 729 return -EOPNOTSUPP;730}731 732void igc_reinit_locked(struct igc_adapter *);733struct igc_nfc_rule *igc_get_nfc_rule(struct igc_adapter *adapter,734 u32 location);735int igc_add_nfc_rule(struct igc_adapter *adapter, struct igc_nfc_rule *rule);736void igc_del_nfc_rule(struct igc_adapter *adapter, struct igc_nfc_rule *rule);737 738void igc_ptp_init(struct igc_adapter *adapter);739void igc_ptp_reset(struct igc_adapter *adapter);740void igc_ptp_suspend(struct igc_adapter *adapter);741void igc_ptp_stop(struct igc_adapter *adapter);742ktime_t igc_ptp_rx_pktstamp(struct igc_adapter *adapter, __le32 *buf);743int igc_ptp_set_ts_config(struct net_device *netdev, struct ifreq *ifr);744int igc_ptp_get_ts_config(struct net_device *netdev, struct ifreq *ifr);745void igc_ptp_tx_hang(struct igc_adapter *adapter);746void igc_ptp_read(struct igc_adapter *adapter, struct timespec64 *ts);747void igc_ptp_tx_tstamp_event(struct igc_adapter *adapter);748 749int igc_led_setup(struct igc_adapter *adapter);750void igc_led_free(struct igc_adapter *adapter);751 752#define igc_rx_pg_size(_ring) (PAGE_SIZE << igc_rx_pg_order(_ring))753 754#define IGC_TXD_DCMD (IGC_ADVTXD_DCMD_EOP | IGC_ADVTXD_DCMD_RS)755 756#define IGC_RX_DESC(R, i) \757 (&(((union igc_adv_rx_desc *)((R)->desc))[i]))758#define IGC_TX_DESC(R, i) \759 (&(((union igc_adv_tx_desc *)((R)->desc))[i]))760#define IGC_TX_CTXTDESC(R, i) \761 (&(((struct igc_adv_tx_context_desc *)((R)->desc))[i]))762 763#endif /* _IGC_H_ */764