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1// SPDX-License-Identifier: GPL-2.02/* Copyright (c) 2018 Intel Corporation */3 4#include <linux/bitfield.h>5#include <linux/delay.h>6 7#include "igc_hw.h"8 9/**10 * igc_acquire_nvm_i225 - Acquire exclusive access to EEPROM11 * @hw: pointer to the HW structure12 *13 * Acquire the necessary semaphores for exclusive access to the EEPROM.14 * Set the EEPROM access request bit and wait for EEPROM access grant bit.15 * Return successful if access grant bit set, else clear the request for16 * EEPROM access and return -IGC_ERR_NVM (-1).17 */18static s32 igc_acquire_nvm_i225(struct igc_hw *hw)19{20 return igc_acquire_swfw_sync_i225(hw, IGC_SWFW_EEP_SM);21}22 23/**24 * igc_release_nvm_i225 - Release exclusive access to EEPROM25 * @hw: pointer to the HW structure26 *27 * Stop any current commands to the EEPROM and clear the EEPROM request bit,28 * then release the semaphores acquired.29 */30static void igc_release_nvm_i225(struct igc_hw *hw)31{32 igc_release_swfw_sync_i225(hw, IGC_SWFW_EEP_SM);33}34 35/**36 * igc_get_hw_semaphore_i225 - Acquire hardware semaphore37 * @hw: pointer to the HW structure38 *39 * Acquire the HW semaphore to access the PHY or NVM40 */41static s32 igc_get_hw_semaphore_i225(struct igc_hw *hw)42{43 s32 timeout = hw->nvm.word_size + 1;44 s32 i = 0;45 u32 swsm;46 47 /* Get the SW semaphore */48 while (i < timeout) {49 swsm = rd32(IGC_SWSM);50 if (!(swsm & IGC_SWSM_SMBI))51 break;52 53 usleep_range(500, 600);54 i++;55 }56 57 if (i == timeout) {58 /* In rare circumstances, the SW semaphore may already be held59 * unintentionally. Clear the semaphore once before giving up.60 */61 if (hw->dev_spec._base.clear_semaphore_once) {62 hw->dev_spec._base.clear_semaphore_once = false;63 igc_put_hw_semaphore(hw);64 for (i = 0; i < timeout; i++) {65 swsm = rd32(IGC_SWSM);66 if (!(swsm & IGC_SWSM_SMBI))67 break;68 69 usleep_range(500, 600);70 }71 }72 73 /* If we do not have the semaphore here, we have to give up. */74 if (i == timeout) {75 hw_dbg("Driver can't access device - SMBI bit is set.\n");76 return -IGC_ERR_NVM;77 }78 }79 80 /* Get the FW semaphore. */81 for (i = 0; i < timeout; i++) {82 swsm = rd32(IGC_SWSM);83 wr32(IGC_SWSM, swsm | IGC_SWSM_SWESMBI);84 85 /* Semaphore acquired if bit latched */86 if (rd32(IGC_SWSM) & IGC_SWSM_SWESMBI)87 break;88 89 usleep_range(500, 600);90 }91 92 if (i == timeout) {93 /* Release semaphores */94 igc_put_hw_semaphore(hw);95 hw_dbg("Driver can't access the NVM\n");96 return -IGC_ERR_NVM;97 }98 99 return 0;100}101 102/**103 * igc_acquire_swfw_sync_i225 - Acquire SW/FW semaphore104 * @hw: pointer to the HW structure105 * @mask: specifies which semaphore to acquire106 *107 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask108 * will also specify which port we're acquiring the lock for.109 */110s32 igc_acquire_swfw_sync_i225(struct igc_hw *hw, u16 mask)111{112 s32 i = 0, timeout = 200;113 u32 fwmask = mask << 16;114 u32 swmask = mask;115 s32 ret_val = 0;116 u32 swfw_sync;117 118 while (i < timeout) {119 if (igc_get_hw_semaphore_i225(hw)) {120 ret_val = -IGC_ERR_SWFW_SYNC;121 goto out;122 }123 124 swfw_sync = rd32(IGC_SW_FW_SYNC);125 if (!(swfw_sync & (fwmask | swmask)))126 break;127 128 /* Firmware currently using resource (fwmask) */129 igc_put_hw_semaphore(hw);130 mdelay(5);131 i++;132 }133 134 if (i == timeout) {135 hw_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n");136 ret_val = -IGC_ERR_SWFW_SYNC;137 goto out;138 }139 140 swfw_sync |= swmask;141 wr32(IGC_SW_FW_SYNC, swfw_sync);142 143 igc_put_hw_semaphore(hw);144out:145 return ret_val;146}147 148/**149 * igc_release_swfw_sync_i225 - Release SW/FW semaphore150 * @hw: pointer to the HW structure151 * @mask: specifies which semaphore to acquire152 *153 * Release the SW/FW semaphore used to access the PHY or NVM. The mask154 * will also specify which port we're releasing the lock for.155 */156void igc_release_swfw_sync_i225(struct igc_hw *hw, u16 mask)157{158 u32 swfw_sync;159 160 /* Releasing the resource requires first getting the HW semaphore.161 * If we fail to get the semaphore, there is nothing we can do,162 * except log an error and quit. We are not allowed to hang here163 * indefinitely, as it may cause denial of service or system crash.164 */165 if (igc_get_hw_semaphore_i225(hw)) {166 hw_dbg("Failed to release SW_FW_SYNC.\n");167 return;168 }169 170 swfw_sync = rd32(IGC_SW_FW_SYNC);171 swfw_sync &= ~mask;172 wr32(IGC_SW_FW_SYNC, swfw_sync);173 174 igc_put_hw_semaphore(hw);175}176 177/**178 * igc_read_nvm_srrd_i225 - Reads Shadow Ram using EERD register179 * @hw: pointer to the HW structure180 * @offset: offset of word in the Shadow Ram to read181 * @words: number of words to read182 * @data: word read from the Shadow Ram183 *184 * Reads a 16 bit word from the Shadow Ram using the EERD register.185 * Uses necessary synchronization semaphores.186 */187static s32 igc_read_nvm_srrd_i225(struct igc_hw *hw, u16 offset, u16 words,188 u16 *data)189{190 s32 status = 0;191 u16 i, count;192 193 /* We cannot hold synchronization semaphores for too long,194 * because of forceful takeover procedure. However it is more efficient195 * to read in bursts than synchronizing access for each word.196 */197 for (i = 0; i < words; i += IGC_EERD_EEWR_MAX_COUNT) {198 count = (words - i) / IGC_EERD_EEWR_MAX_COUNT > 0 ?199 IGC_EERD_EEWR_MAX_COUNT : (words - i);200 201 status = hw->nvm.ops.acquire(hw);202 if (status)203 break;204 205 status = igc_read_nvm_eerd(hw, offset, count, data + i);206 hw->nvm.ops.release(hw);207 if (status)208 break;209 }210 211 return status;212}213 214/**215 * igc_write_nvm_srwr - Write to Shadow Ram using EEWR216 * @hw: pointer to the HW structure217 * @offset: offset within the Shadow Ram to be written to218 * @words: number of words to write219 * @data: 16 bit word(s) to be written to the Shadow Ram220 *221 * Writes data to Shadow Ram at offset using EEWR register.222 *223 * If igc_update_nvm_checksum is not called after this function , the224 * Shadow Ram will most likely contain an invalid checksum.225 */226static s32 igc_write_nvm_srwr(struct igc_hw *hw, u16 offset, u16 words,227 u16 *data)228{229 struct igc_nvm_info *nvm = &hw->nvm;230 s32 ret_val = -IGC_ERR_NVM;231 u32 attempts = 100000;232 u32 i, k, eewr = 0;233 234 /* A check for invalid values: offset too large, too many words,235 * too many words for the offset, and not enough words.236 */237 if (offset >= nvm->word_size || (words > (nvm->word_size - offset)) ||238 words == 0) {239 hw_dbg("nvm parameter(s) out of bounds\n");240 return ret_val;241 }242 243 for (i = 0; i < words; i++) {244 ret_val = -IGC_ERR_NVM;245 eewr = ((offset + i) << IGC_NVM_RW_ADDR_SHIFT) |246 (data[i] << IGC_NVM_RW_REG_DATA) |247 IGC_NVM_RW_REG_START;248 249 wr32(IGC_SRWR, eewr);250 251 for (k = 0; k < attempts; k++) {252 if (IGC_NVM_RW_REG_DONE &253 rd32(IGC_SRWR)) {254 ret_val = 0;255 break;256 }257 udelay(5);258 }259 260 if (ret_val) {261 hw_dbg("Shadow RAM write EEWR timed out\n");262 break;263 }264 }265 266 return ret_val;267}268 269/**270 * igc_write_nvm_srwr_i225 - Write to Shadow RAM using EEWR271 * @hw: pointer to the HW structure272 * @offset: offset within the Shadow RAM to be written to273 * @words: number of words to write274 * @data: 16 bit word(s) to be written to the Shadow RAM275 *276 * Writes data to Shadow RAM at offset using EEWR register.277 *278 * If igc_update_nvm_checksum is not called after this function , the279 * data will not be committed to FLASH and also Shadow RAM will most likely280 * contain an invalid checksum.281 *282 * If error code is returned, data and Shadow RAM may be inconsistent - buffer283 * partially written.284 */285static s32 igc_write_nvm_srwr_i225(struct igc_hw *hw, u16 offset, u16 words,286 u16 *data)287{288 s32 status = 0;289 u16 i, count;290 291 /* We cannot hold synchronization semaphores for too long,292 * because of forceful takeover procedure. However it is more efficient293 * to write in bursts than synchronizing access for each word.294 */295 for (i = 0; i < words; i += IGC_EERD_EEWR_MAX_COUNT) {296 count = (words - i) / IGC_EERD_EEWR_MAX_COUNT > 0 ?297 IGC_EERD_EEWR_MAX_COUNT : (words - i);298 299 status = hw->nvm.ops.acquire(hw);300 if (status)301 break;302 303 status = igc_write_nvm_srwr(hw, offset, count, data + i);304 hw->nvm.ops.release(hw);305 if (status)306 break;307 }308 309 return status;310}311 312/**313 * igc_validate_nvm_checksum_i225 - Validate EEPROM checksum314 * @hw: pointer to the HW structure315 *316 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM317 * and then verifies that the sum of the EEPROM is equal to 0xBABA.318 */319static s32 igc_validate_nvm_checksum_i225(struct igc_hw *hw)320{321 s32 (*read_op_ptr)(struct igc_hw *hw, u16 offset, u16 count,322 u16 *data);323 s32 status = 0;324 325 status = hw->nvm.ops.acquire(hw);326 if (status)327 goto out;328 329 /* Replace the read function with semaphore grabbing with330 * the one that skips this for a while.331 * We have semaphore taken already here.332 */333 read_op_ptr = hw->nvm.ops.read;334 hw->nvm.ops.read = igc_read_nvm_eerd;335 336 status = igc_validate_nvm_checksum(hw);337 338 /* Revert original read operation. */339 hw->nvm.ops.read = read_op_ptr;340 341 hw->nvm.ops.release(hw);342 343out:344 return status;345}346 347/**348 * igc_pool_flash_update_done_i225 - Pool FLUDONE status349 * @hw: pointer to the HW structure350 */351static s32 igc_pool_flash_update_done_i225(struct igc_hw *hw)352{353 s32 ret_val = -IGC_ERR_NVM;354 u32 i, reg;355 356 for (i = 0; i < IGC_FLUDONE_ATTEMPTS; i++) {357 reg = rd32(IGC_EECD);358 if (reg & IGC_EECD_FLUDONE_I225) {359 ret_val = 0;360 break;361 }362 udelay(5);363 }364 365 return ret_val;366}367 368/**369 * igc_update_flash_i225 - Commit EEPROM to the flash370 * @hw: pointer to the HW structure371 */372static s32 igc_update_flash_i225(struct igc_hw *hw)373{374 s32 ret_val = 0;375 u32 flup;376 377 ret_val = igc_pool_flash_update_done_i225(hw);378 if (ret_val == -IGC_ERR_NVM) {379 hw_dbg("Flash update time out\n");380 goto out;381 }382 383 flup = rd32(IGC_EECD) | IGC_EECD_FLUPD_I225;384 wr32(IGC_EECD, flup);385 386 ret_val = igc_pool_flash_update_done_i225(hw);387 if (ret_val)388 hw_dbg("Flash update time out\n");389 else390 hw_dbg("Flash update complete\n");391 392out:393 return ret_val;394}395 396/**397 * igc_update_nvm_checksum_i225 - Update EEPROM checksum398 * @hw: pointer to the HW structure399 *400 * Updates the EEPROM checksum by reading/adding each word of the EEPROM401 * up to the checksum. Then calculates the EEPROM checksum and writes the402 * value to the EEPROM. Next commit EEPROM data onto the Flash.403 */404static s32 igc_update_nvm_checksum_i225(struct igc_hw *hw)405{406 u16 checksum = 0;407 s32 ret_val = 0;408 u16 i, nvm_data;409 410 /* Read the first word from the EEPROM. If this times out or fails, do411 * not continue or we could be in for a very long wait while every412 * EEPROM read fails413 */414 ret_val = igc_read_nvm_eerd(hw, 0, 1, &nvm_data);415 if (ret_val) {416 hw_dbg("EEPROM read failed\n");417 goto out;418 }419 420 ret_val = hw->nvm.ops.acquire(hw);421 if (ret_val)422 goto out;423 424 /* Do not use hw->nvm.ops.write, hw->nvm.ops.read425 * because we do not want to take the synchronization426 * semaphores twice here.427 */428 429 for (i = 0; i < NVM_CHECKSUM_REG; i++) {430 ret_val = igc_read_nvm_eerd(hw, i, 1, &nvm_data);431 if (ret_val) {432 hw->nvm.ops.release(hw);433 hw_dbg("NVM Read Error while updating checksum.\n");434 goto out;435 }436 checksum += nvm_data;437 }438 checksum = (u16)NVM_SUM - checksum;439 ret_val = igc_write_nvm_srwr(hw, NVM_CHECKSUM_REG, 1,440 &checksum);441 if (ret_val) {442 hw->nvm.ops.release(hw);443 hw_dbg("NVM Write Error while updating checksum.\n");444 goto out;445 }446 447 hw->nvm.ops.release(hw);448 449 ret_val = igc_update_flash_i225(hw);450 451out:452 return ret_val;453}454 455/**456 * igc_get_flash_presence_i225 - Check if flash device is detected457 * @hw: pointer to the HW structure458 */459bool igc_get_flash_presence_i225(struct igc_hw *hw)460{461 bool ret_val = false;462 u32 eec = 0;463 464 eec = rd32(IGC_EECD);465 if (eec & IGC_EECD_FLASH_DETECTED_I225)466 ret_val = true;467 468 return ret_val;469}470 471/**472 * igc_init_nvm_params_i225 - Init NVM func ptrs.473 * @hw: pointer to the HW structure474 */475s32 igc_init_nvm_params_i225(struct igc_hw *hw)476{477 struct igc_nvm_info *nvm = &hw->nvm;478 479 nvm->ops.acquire = igc_acquire_nvm_i225;480 nvm->ops.release = igc_release_nvm_i225;481 482 /* NVM Function Pointers */483 if (igc_get_flash_presence_i225(hw)) {484 nvm->ops.read = igc_read_nvm_srrd_i225;485 nvm->ops.write = igc_write_nvm_srwr_i225;486 nvm->ops.validate = igc_validate_nvm_checksum_i225;487 nvm->ops.update = igc_update_nvm_checksum_i225;488 } else {489 nvm->ops.read = igc_read_nvm_eerd;490 nvm->ops.write = NULL;491 nvm->ops.validate = NULL;492 nvm->ops.update = NULL;493 }494 return 0;495}496 497/**498 * igc_set_eee_i225 - Enable/disable EEE support499 * @hw: pointer to the HW structure500 * @adv2p5G: boolean flag enabling 2.5G EEE advertisement501 * @adv1G: boolean flag enabling 1G EEE advertisement502 * @adv100M: boolean flag enabling 100M EEE advertisement503 *504 * Enable/disable EEE based on setting in dev_spec structure.505 **/506s32 igc_set_eee_i225(struct igc_hw *hw, bool adv2p5G, bool adv1G,507 bool adv100M)508{509 u32 ipcnfg, eeer;510 511 ipcnfg = rd32(IGC_IPCNFG);512 eeer = rd32(IGC_EEER);513 514 /* enable or disable per user setting */515 if (hw->dev_spec._base.eee_enable) {516 u32 eee_su = rd32(IGC_EEE_SU);517 518 if (adv100M)519 ipcnfg |= IGC_IPCNFG_EEE_100M_AN;520 else521 ipcnfg &= ~IGC_IPCNFG_EEE_100M_AN;522 523 if (adv1G)524 ipcnfg |= IGC_IPCNFG_EEE_1G_AN;525 else526 ipcnfg &= ~IGC_IPCNFG_EEE_1G_AN;527 528 if (adv2p5G)529 ipcnfg |= IGC_IPCNFG_EEE_2_5G_AN;530 else531 ipcnfg &= ~IGC_IPCNFG_EEE_2_5G_AN;532 533 eeer |= (IGC_EEER_TX_LPI_EN | IGC_EEER_RX_LPI_EN |534 IGC_EEER_LPI_FC);535 536 /* This bit should not be set in normal operation. */537 if (eee_su & IGC_EEE_SU_LPI_CLK_STP)538 hw_dbg("LPI Clock Stop Bit should not be set!\n");539 } else {540 ipcnfg &= ~(IGC_IPCNFG_EEE_2_5G_AN | IGC_IPCNFG_EEE_1G_AN |541 IGC_IPCNFG_EEE_100M_AN);542 eeer &= ~(IGC_EEER_TX_LPI_EN | IGC_EEER_RX_LPI_EN |543 IGC_EEER_LPI_FC);544 }545 wr32(IGC_IPCNFG, ipcnfg);546 wr32(IGC_EEER, eeer);547 rd32(IGC_IPCNFG);548 rd32(IGC_EEER);549 550 return IGC_SUCCESS;551}552 553/* igc_set_ltr_i225 - Set Latency Tolerance Reporting thresholds554 * @hw: pointer to the HW structure555 * @link: bool indicating link status556 *557 * Set the LTR thresholds based on the link speed (Mbps), EEE, and DMAC558 * settings, otherwise specify that there is no LTR requirement.559 */560s32 igc_set_ltr_i225(struct igc_hw *hw, bool link)561{562 u32 tw_system, ltrc, ltrv, ltr_min, ltr_max, scale_min, scale_max;563 u16 speed, duplex;564 s32 size;565 566 /* If we do not have link, LTR thresholds are zero. */567 if (link) {568 hw->mac.ops.get_speed_and_duplex(hw, &speed, &duplex);569 570 /* Check if using copper interface with EEE enabled or if the571 * link speed is 10 Mbps.572 */573 if (hw->dev_spec._base.eee_enable &&574 speed != SPEED_10) {575 /* EEE enabled, so send LTRMAX threshold. */576 ltrc = rd32(IGC_LTRC) |577 IGC_LTRC_EEEMS_EN;578 wr32(IGC_LTRC, ltrc);579 580 /* Calculate tw_system (nsec). */581 if (speed == SPEED_100) {582 tw_system = FIELD_GET(IGC_TW_SYSTEM_100_MASK,583 rd32(IGC_EEE_SU)) * 500;584 } else {585 tw_system = (rd32(IGC_EEE_SU) &586 IGC_TW_SYSTEM_1000_MASK) * 500;587 }588 } else {589 tw_system = 0;590 }591 592 /* Get the Rx packet buffer size. */593 size = rd32(IGC_RXPBS) &594 IGC_RXPBS_SIZE_I225_MASK;595 596 /* Convert size to bytes, subtract the MTU, and then597 * convert the size to bits.598 */599 size *= 1024;600 size *= 8;601 602 if (size < 0) {603 hw_dbg("Invalid effective Rx buffer size %d\n",604 size);605 return -IGC_ERR_CONFIG;606 }607 608 /* Calculate the thresholds. Since speed is in Mbps, simplify609 * the calculation by multiplying size/speed by 1000 for result610 * to be in nsec before dividing by the scale in nsec. Set the611 * scale such that the LTR threshold fits in the register.612 */613 ltr_min = (1000 * size) / speed;614 ltr_max = ltr_min + tw_system;615 scale_min = (ltr_min / 1024) < 1024 ? IGC_LTRMINV_SCALE_1024 :616 IGC_LTRMINV_SCALE_32768;617 scale_max = (ltr_max / 1024) < 1024 ? IGC_LTRMAXV_SCALE_1024 :618 IGC_LTRMAXV_SCALE_32768;619 ltr_min /= scale_min == IGC_LTRMINV_SCALE_1024 ? 1024 : 32768;620 ltr_min -= 1;621 ltr_max /= scale_max == IGC_LTRMAXV_SCALE_1024 ? 1024 : 32768;622 ltr_max -= 1;623 624 /* Only write the LTR thresholds if they differ from before. */625 ltrv = rd32(IGC_LTRMINV);626 if (ltr_min != (ltrv & IGC_LTRMINV_LTRV_MASK)) {627 ltrv = IGC_LTRMINV_LSNP_REQ | ltr_min |628 (scale_min << IGC_LTRMINV_SCALE_SHIFT);629 wr32(IGC_LTRMINV, ltrv);630 }631 632 ltrv = rd32(IGC_LTRMAXV);633 if (ltr_max != (ltrv & IGC_LTRMAXV_LTRV_MASK)) {634 ltrv = IGC_LTRMAXV_LSNP_REQ | ltr_max |635 (scale_max << IGC_LTRMAXV_SCALE_SHIFT);636 wr32(IGC_LTRMAXV, ltrv);637 }638 }639 640 return IGC_SUCCESS;641}642