brintos / linux-shallow public Read only

1// SPDX-License-Identifier: GPL-2.02/* Copyright (c)  2018 Intel Corporation */3 4#include <linux/module.h>5#include <linux/types.h>6#include <linux/if_vlan.h>7#include <linux/tcp.h>8#include <linux/udp.h>9#include <linux/ip.h>10#include <linux/pm_runtime.h>11#include <net/pkt_sched.h>12#include <linux/bpf_trace.h>13#include <net/xdp_sock_drv.h>14#include <linux/pci.h>15#include <linux/mdio.h>16 17#include <net/ipv6.h>18 19#include "igc.h"20#include "igc_hw.h"21#include "igc_tsn.h"22#include "igc_xdp.h"23 24#define DRV_SUMMARY	"Intel(R) 2.5G Ethernet Linux Driver"25 26#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)27 28#define IGC_XDP_PASS		029#define IGC_XDP_CONSUMED	BIT(0)30#define IGC_XDP_TX		BIT(1)31#define IGC_XDP_REDIRECT	BIT(2)32 33static int debug = -1;34 35MODULE_DESCRIPTION(DRV_SUMMARY);36MODULE_LICENSE("GPL v2");37module_param(debug, int, 0);38MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");39 40char igc_driver_name[] = "igc";41static const char igc_driver_string[] = DRV_SUMMARY;42static const char igc_copyright[] =43	"Copyright(c) 2018 Intel Corporation.";44 45static const struct igc_info *igc_info_tbl[] = {46	[board_base] = &igc_base_info,47};48 49static const struct pci_device_id igc_pci_tbl[] = {50	{ PCI_VDEVICE(INTEL, IGC_DEV_ID_I225_LM), board_base },51	{ PCI_VDEVICE(INTEL, IGC_DEV_ID_I225_V), board_base },52	{ PCI_VDEVICE(INTEL, IGC_DEV_ID_I225_I), board_base },53	{ PCI_VDEVICE(INTEL, IGC_DEV_ID_I220_V), board_base },54	{ PCI_VDEVICE(INTEL, IGC_DEV_ID_I225_K), board_base },55	{ PCI_VDEVICE(INTEL, IGC_DEV_ID_I225_K2), board_base },56	{ PCI_VDEVICE(INTEL, IGC_DEV_ID_I226_K), board_base },57	{ PCI_VDEVICE(INTEL, IGC_DEV_ID_I225_LMVP), board_base },58	{ PCI_VDEVICE(INTEL, IGC_DEV_ID_I226_LMVP), board_base },59	{ PCI_VDEVICE(INTEL, IGC_DEV_ID_I225_IT), board_base },60	{ PCI_VDEVICE(INTEL, IGC_DEV_ID_I226_LM), board_base },61	{ PCI_VDEVICE(INTEL, IGC_DEV_ID_I226_V), board_base },62	{ PCI_VDEVICE(INTEL, IGC_DEV_ID_I226_IT), board_base },63	{ PCI_VDEVICE(INTEL, IGC_DEV_ID_I221_V), board_base },64	{ PCI_VDEVICE(INTEL, IGC_DEV_ID_I226_BLANK_NVM), board_base },65	{ PCI_VDEVICE(INTEL, IGC_DEV_ID_I225_BLANK_NVM), board_base },66	/* required last entry */67	{0, }68};69 70MODULE_DEVICE_TABLE(pci, igc_pci_tbl);71 72enum latency_range {73	lowest_latency = 0,74	low_latency = 1,75	bulk_latency = 2,76	latency_invalid = 25577};78 79void igc_reset(struct igc_adapter *adapter)80{81	struct net_device *dev = adapter->netdev;82	struct igc_hw *hw = &adapter->hw;83	struct igc_fc_info *fc = &hw->fc;84	u32 pba, hwm;85 86	/* Repartition PBA for greater than 9k MTU if required */87	pba = IGC_PBA_34K;88 89	/* flow control settings90	 * The high water mark must be low enough to fit one full frame91	 * after transmitting the pause frame.  As such we must have enough92	 * space to allow for us to complete our current transmit and then93	 * receive the frame that is in progress from the link partner.94	 * Set it to:95	 * - the full Rx FIFO size minus one full Tx plus one full Rx frame96	 */97	hwm = (pba << 10) - (adapter->max_frame_size + MAX_JUMBO_FRAME_SIZE);98 99	fc->high_water = hwm & 0xFFFFFFF0;	/* 16-byte granularity */100	fc->low_water = fc->high_water - 16;101	fc->pause_time = 0xFFFF;102	fc->send_xon = 1;103	fc->current_mode = fc->requested_mode;104 105	hw->mac.ops.reset_hw(hw);106 107	if (hw->mac.ops.init_hw(hw))108		netdev_err(dev, "Error on hardware initialization\n");109 110	/* Re-establish EEE setting */111	igc_set_eee_i225(hw, true, true, true);112 113	if (!netif_running(adapter->netdev))114		igc_power_down_phy_copper_base(&adapter->hw);115 116	/* Enable HW to recognize an 802.1Q VLAN Ethernet packet */117	wr32(IGC_VET, ETH_P_8021Q);118 119	/* Re-enable PTP, where applicable. */120	igc_ptp_reset(adapter);121 122	/* Re-enable TSN offloading, where applicable. */123	igc_tsn_reset(adapter);124 125	igc_get_phy_info(hw);126}127 128/**129 * igc_power_up_link - Power up the phy link130 * @adapter: address of board private structure131 */132static void igc_power_up_link(struct igc_adapter *adapter)133{134	igc_reset_phy(&adapter->hw);135 136	igc_power_up_phy_copper(&adapter->hw);137 138	igc_setup_link(&adapter->hw);139}140 141/**142 * igc_release_hw_control - release control of the h/w to f/w143 * @adapter: address of board private structure144 *145 * igc_release_hw_control resets CTRL_EXT:DRV_LOAD bit.146 * For ASF and Pass Through versions of f/w this means that the147 * driver is no longer loaded.148 */149static void igc_release_hw_control(struct igc_adapter *adapter)150{151	struct igc_hw *hw = &adapter->hw;152	u32 ctrl_ext;153 154	if (!pci_device_is_present(adapter->pdev))155		return;156 157	/* Let firmware take over control of h/w */158	ctrl_ext = rd32(IGC_CTRL_EXT);159	wr32(IGC_CTRL_EXT,160	     ctrl_ext & ~IGC_CTRL_EXT_DRV_LOAD);161}162 163/**164 * igc_get_hw_control - get control of the h/w from f/w165 * @adapter: address of board private structure166 *167 * igc_get_hw_control sets CTRL_EXT:DRV_LOAD bit.168 * For ASF and Pass Through versions of f/w this means that169 * the driver is loaded.170 */171static void igc_get_hw_control(struct igc_adapter *adapter)172{173	struct igc_hw *hw = &adapter->hw;174	u32 ctrl_ext;175 176	/* Let firmware know the driver has taken over */177	ctrl_ext = rd32(IGC_CTRL_EXT);178	wr32(IGC_CTRL_EXT,179	     ctrl_ext | IGC_CTRL_EXT_DRV_LOAD);180}181 182static void igc_unmap_tx_buffer(struct device *dev, struct igc_tx_buffer *buf)183{184	dma_unmap_single(dev, dma_unmap_addr(buf, dma),185			 dma_unmap_len(buf, len), DMA_TO_DEVICE);186 187	dma_unmap_len_set(buf, len, 0);188}189 190/**191 * igc_clean_tx_ring - Free Tx Buffers192 * @tx_ring: ring to be cleaned193 */194static void igc_clean_tx_ring(struct igc_ring *tx_ring)195{196	u16 i = tx_ring->next_to_clean;197	struct igc_tx_buffer *tx_buffer = &tx_ring->tx_buffer_info[i];198	u32 xsk_frames = 0;199 200	while (i != tx_ring->next_to_use) {201		union igc_adv_tx_desc *eop_desc, *tx_desc;202 203		switch (tx_buffer->type) {204		case IGC_TX_BUFFER_TYPE_XSK:205			xsk_frames++;206			break;207		case IGC_TX_BUFFER_TYPE_XDP:208			xdp_return_frame(tx_buffer->xdpf);209			igc_unmap_tx_buffer(tx_ring->dev, tx_buffer);210			break;211		case IGC_TX_BUFFER_TYPE_SKB:212			dev_kfree_skb_any(tx_buffer->skb);213			igc_unmap_tx_buffer(tx_ring->dev, tx_buffer);214			break;215		default:216			netdev_warn_once(tx_ring->netdev, "Unknown Tx buffer type\n");217			break;218		}219 220		/* check for eop_desc to determine the end of the packet */221		eop_desc = tx_buffer->next_to_watch;222		tx_desc = IGC_TX_DESC(tx_ring, i);223 224		/* unmap remaining buffers */225		while (tx_desc != eop_desc) {226			tx_buffer++;227			tx_desc++;228			i++;229			if (unlikely(i == tx_ring->count)) {230				i = 0;231				tx_buffer = tx_ring->tx_buffer_info;232				tx_desc = IGC_TX_DESC(tx_ring, 0);233			}234 235			/* unmap any remaining paged data */236			if (dma_unmap_len(tx_buffer, len))237				igc_unmap_tx_buffer(tx_ring->dev, tx_buffer);238		}239 240		tx_buffer->next_to_watch = NULL;241 242		/* move us one more past the eop_desc for start of next pkt */243		tx_buffer++;244		i++;245		if (unlikely(i == tx_ring->count)) {246			i = 0;247			tx_buffer = tx_ring->tx_buffer_info;248		}249	}250 251	if (tx_ring->xsk_pool && xsk_frames)252		xsk_tx_completed(tx_ring->xsk_pool, xsk_frames);253 254	/* reset BQL for queue */255	netdev_tx_reset_queue(txring_txq(tx_ring));256 257	/* Zero out the buffer ring */258	memset(tx_ring->tx_buffer_info, 0,259	       sizeof(*tx_ring->tx_buffer_info) * tx_ring->count);260 261	/* Zero out the descriptor ring */262	memset(tx_ring->desc, 0, tx_ring->size);263 264	/* reset next_to_use and next_to_clean */265	tx_ring->next_to_use = 0;266	tx_ring->next_to_clean = 0;267}268 269/**270 * igc_free_tx_resources - Free Tx Resources per Queue271 * @tx_ring: Tx descriptor ring for a specific queue272 *273 * Free all transmit software resources274 */275void igc_free_tx_resources(struct igc_ring *tx_ring)276{277	igc_disable_tx_ring(tx_ring);278 279	vfree(tx_ring->tx_buffer_info);280	tx_ring->tx_buffer_info = NULL;281 282	/* if not set, then don't free */283	if (!tx_ring->desc)284		return;285 286	dma_free_coherent(tx_ring->dev, tx_ring->size,287			  tx_ring->desc, tx_ring->dma);288 289	tx_ring->desc = NULL;290}291 292/**293 * igc_free_all_tx_resources - Free Tx Resources for All Queues294 * @adapter: board private structure295 *296 * Free all transmit software resources297 */298static void igc_free_all_tx_resources(struct igc_adapter *adapter)299{300	int i;301 302	for (i = 0; i < adapter->num_tx_queues; i++)303		igc_free_tx_resources(adapter->tx_ring[i]);304}305 306/**307 * igc_clean_all_tx_rings - Free Tx Buffers for all queues308 * @adapter: board private structure309 */310static void igc_clean_all_tx_rings(struct igc_adapter *adapter)311{312	int i;313 314	for (i = 0; i < adapter->num_tx_queues; i++)315		if (adapter->tx_ring[i])316			igc_clean_tx_ring(adapter->tx_ring[i]);317}318 319static void igc_disable_tx_ring_hw(struct igc_ring *ring)320{321	struct igc_hw *hw = &ring->q_vector->adapter->hw;322	u8 idx = ring->reg_idx;323	u32 txdctl;324 325	txdctl = rd32(IGC_TXDCTL(idx));326	txdctl &= ~IGC_TXDCTL_QUEUE_ENABLE;327	txdctl |= IGC_TXDCTL_SWFLUSH;328	wr32(IGC_TXDCTL(idx), txdctl);329}330 331/**332 * igc_disable_all_tx_rings_hw - Disable all transmit queue operation333 * @adapter: board private structure334 */335static void igc_disable_all_tx_rings_hw(struct igc_adapter *adapter)336{337	int i;338 339	for (i = 0; i < adapter->num_tx_queues; i++) {340		struct igc_ring *tx_ring = adapter->tx_ring[i];341 342		igc_disable_tx_ring_hw(tx_ring);343	}344}345 346/**347 * igc_setup_tx_resources - allocate Tx resources (Descriptors)348 * @tx_ring: tx descriptor ring (for a specific queue) to setup349 *350 * Return 0 on success, negative on failure351 */352int igc_setup_tx_resources(struct igc_ring *tx_ring)353{354	struct net_device *ndev = tx_ring->netdev;355	struct device *dev = tx_ring->dev;356	int size = 0;357 358	size = sizeof(struct igc_tx_buffer) * tx_ring->count;359	tx_ring->tx_buffer_info = vzalloc(size);360	if (!tx_ring->tx_buffer_info)361		goto err;362 363	/* round up to nearest 4K */364	tx_ring->size = tx_ring->count * sizeof(union igc_adv_tx_desc);365	tx_ring->size = ALIGN(tx_ring->size, 4096);366 367	tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,368					   &tx_ring->dma, GFP_KERNEL);369 370	if (!tx_ring->desc)371		goto err;372 373	tx_ring->next_to_use = 0;374	tx_ring->next_to_clean = 0;375 376	return 0;377 378err:379	vfree(tx_ring->tx_buffer_info);380	netdev_err(ndev, "Unable to allocate memory for Tx descriptor ring\n");381	return -ENOMEM;382}383 384/**385 * igc_setup_all_tx_resources - wrapper to allocate Tx resources for all queues386 * @adapter: board private structure387 *388 * Return 0 on success, negative on failure389 */390static int igc_setup_all_tx_resources(struct igc_adapter *adapter)391{392	struct net_device *dev = adapter->netdev;393	int i, err = 0;394 395	for (i = 0; i < adapter->num_tx_queues; i++) {396		err = igc_setup_tx_resources(adapter->tx_ring[i]);397		if (err) {398			netdev_err(dev, "Error on Tx queue %u setup\n", i);399			for (i--; i >= 0; i--)400				igc_free_tx_resources(adapter->tx_ring[i]);401			break;402		}403	}404 405	return err;406}407 408static void igc_clean_rx_ring_page_shared(struct igc_ring *rx_ring)409{410	u16 i = rx_ring->next_to_clean;411 412	dev_kfree_skb(rx_ring->skb);413	rx_ring->skb = NULL;414 415	/* Free all the Rx ring sk_buffs */416	while (i != rx_ring->next_to_alloc) {417		struct igc_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i];418 419		/* Invalidate cache lines that may have been written to by420		 * device so that we avoid corrupting memory.421		 */422		dma_sync_single_range_for_cpu(rx_ring->dev,423					      buffer_info->dma,424					      buffer_info->page_offset,425					      igc_rx_bufsz(rx_ring),426					      DMA_FROM_DEVICE);427 428		/* free resources associated with mapping */429		dma_unmap_page_attrs(rx_ring->dev,430				     buffer_info->dma,431				     igc_rx_pg_size(rx_ring),432				     DMA_FROM_DEVICE,433				     IGC_RX_DMA_ATTR);434		__page_frag_cache_drain(buffer_info->page,435					buffer_info->pagecnt_bias);436 437		i++;438		if (i == rx_ring->count)439			i = 0;440	}441}442 443static void igc_clean_rx_ring_xsk_pool(struct igc_ring *ring)444{445	struct igc_rx_buffer *bi;446	u16 i;447 448	for (i = 0; i < ring->count; i++) {449		bi = &ring->rx_buffer_info[i];450		if (!bi->xdp)451			continue;452 453		xsk_buff_free(bi->xdp);454		bi->xdp = NULL;455	}456}457 458/**459 * igc_clean_rx_ring - Free Rx Buffers per Queue460 * @ring: ring to free buffers from461 */462static void igc_clean_rx_ring(struct igc_ring *ring)463{464	if (ring->xsk_pool)465		igc_clean_rx_ring_xsk_pool(ring);466	else467		igc_clean_rx_ring_page_shared(ring);468 469	clear_ring_uses_large_buffer(ring);470 471	ring->next_to_alloc = 0;472	ring->next_to_clean = 0;473	ring->next_to_use = 0;474}475 476/**477 * igc_clean_all_rx_rings - Free Rx Buffers for all queues478 * @adapter: board private structure479 */480static void igc_clean_all_rx_rings(struct igc_adapter *adapter)481{482	int i;483 484	for (i = 0; i < adapter->num_rx_queues; i++)485		if (adapter->rx_ring[i])486			igc_clean_rx_ring(adapter->rx_ring[i]);487}488 489/**490 * igc_free_rx_resources - Free Rx Resources491 * @rx_ring: ring to clean the resources from492 *493 * Free all receive software resources494 */495void igc_free_rx_resources(struct igc_ring *rx_ring)496{497	igc_clean_rx_ring(rx_ring);498 499	xdp_rxq_info_unreg(&rx_ring->xdp_rxq);500 501	vfree(rx_ring->rx_buffer_info);502	rx_ring->rx_buffer_info = NULL;503 504	/* if not set, then don't free */505	if (!rx_ring->desc)506		return;507 508	dma_free_coherent(rx_ring->dev, rx_ring->size,509			  rx_ring->desc, rx_ring->dma);510 511	rx_ring->desc = NULL;512}513 514/**515 * igc_free_all_rx_resources - Free Rx Resources for All Queues516 * @adapter: board private structure517 *518 * Free all receive software resources519 */520static void igc_free_all_rx_resources(struct igc_adapter *adapter)521{522	int i;523 524	for (i = 0; i < adapter->num_rx_queues; i++)525		igc_free_rx_resources(adapter->rx_ring[i]);526}527 528/**529 * igc_setup_rx_resources - allocate Rx resources (Descriptors)530 * @rx_ring:    rx descriptor ring (for a specific queue) to setup531 *532 * Returns 0 on success, negative on failure533 */534int igc_setup_rx_resources(struct igc_ring *rx_ring)535{536	struct net_device *ndev = rx_ring->netdev;537	struct device *dev = rx_ring->dev;538	u8 index = rx_ring->queue_index;539	int size, desc_len, res;540 541	/* XDP RX-queue info */542	if (xdp_rxq_info_is_reg(&rx_ring->xdp_rxq))543		xdp_rxq_info_unreg(&rx_ring->xdp_rxq);544	res = xdp_rxq_info_reg(&rx_ring->xdp_rxq, ndev, index,545			       rx_ring->q_vector->napi.napi_id);546	if (res < 0) {547		netdev_err(ndev, "Failed to register xdp_rxq index %u\n",548			   index);549		return res;550	}551 552	size = sizeof(struct igc_rx_buffer) * rx_ring->count;553	rx_ring->rx_buffer_info = vzalloc(size);554	if (!rx_ring->rx_buffer_info)555		goto err;556 557	desc_len = sizeof(union igc_adv_rx_desc);558 559	/* Round up to nearest 4K */560	rx_ring->size = rx_ring->count * desc_len;561	rx_ring->size = ALIGN(rx_ring->size, 4096);562 563	rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,564					   &rx_ring->dma, GFP_KERNEL);565 566	if (!rx_ring->desc)567		goto err;568 569	rx_ring->next_to_alloc = 0;570	rx_ring->next_to_clean = 0;571	rx_ring->next_to_use = 0;572 573	return 0;574 575err:576	xdp_rxq_info_unreg(&rx_ring->xdp_rxq);577	vfree(rx_ring->rx_buffer_info);578	rx_ring->rx_buffer_info = NULL;579	netdev_err(ndev, "Unable to allocate memory for Rx descriptor ring\n");580	return -ENOMEM;581}582 583/**584 * igc_setup_all_rx_resources - wrapper to allocate Rx resources585 *                                (Descriptors) for all queues586 * @adapter: board private structure587 *588 * Return 0 on success, negative on failure589 */590static int igc_setup_all_rx_resources(struct igc_adapter *adapter)591{592	struct net_device *dev = adapter->netdev;593	int i, err = 0;594 595	for (i = 0; i < adapter->num_rx_queues; i++) {596		err = igc_setup_rx_resources(adapter->rx_ring[i]);597		if (err) {598			netdev_err(dev, "Error on Rx queue %u setup\n", i);599			for (i--; i >= 0; i--)600				igc_free_rx_resources(adapter->rx_ring[i]);601			break;602		}603	}604 605	return err;606}607 608static struct xsk_buff_pool *igc_get_xsk_pool(struct igc_adapter *adapter,609					      struct igc_ring *ring)610{611	if (!igc_xdp_is_enabled(adapter) ||612	    !test_bit(IGC_RING_FLAG_AF_XDP_ZC, &ring->flags))613		return NULL;614 615	return xsk_get_pool_from_qid(ring->netdev, ring->queue_index);616}617 618/**619 * igc_configure_rx_ring - Configure a receive ring after Reset620 * @adapter: board private structure621 * @ring: receive ring to be configured622 *623 * Configure the Rx unit of the MAC after a reset.624 */625static void igc_configure_rx_ring(struct igc_adapter *adapter,626				  struct igc_ring *ring)627{628	struct igc_hw *hw = &adapter->hw;629	union igc_adv_rx_desc *rx_desc;630	int reg_idx = ring->reg_idx;631	u32 srrctl = 0, rxdctl = 0;632	u64 rdba = ring->dma;633	u32 buf_size;634 635	xdp_rxq_info_unreg_mem_model(&ring->xdp_rxq);636	ring->xsk_pool = igc_get_xsk_pool(adapter, ring);637	if (ring->xsk_pool) {638		WARN_ON(xdp_rxq_info_reg_mem_model(&ring->xdp_rxq,639						   MEM_TYPE_XSK_BUFF_POOL,640						   NULL));641		xsk_pool_set_rxq_info(ring->xsk_pool, &ring->xdp_rxq);642	} else {643		WARN_ON(xdp_rxq_info_reg_mem_model(&ring->xdp_rxq,644						   MEM_TYPE_PAGE_SHARED,645						   NULL));646	}647 648	if (igc_xdp_is_enabled(adapter))649		set_ring_uses_large_buffer(ring);650 651	/* disable the queue */652	wr32(IGC_RXDCTL(reg_idx), 0);653 654	/* Set DMA base address registers */655	wr32(IGC_RDBAL(reg_idx),656	     rdba & 0x00000000ffffffffULL);657	wr32(IGC_RDBAH(reg_idx), rdba >> 32);658	wr32(IGC_RDLEN(reg_idx),659	     ring->count * sizeof(union igc_adv_rx_desc));660 661	/* initialize head and tail */662	ring->tail = adapter->io_addr + IGC_RDT(reg_idx);663	wr32(IGC_RDH(reg_idx), 0);664	writel(0, ring->tail);665 666	/* reset next-to- use/clean to place SW in sync with hardware */667	ring->next_to_clean = 0;668	ring->next_to_use = 0;669 670	if (ring->xsk_pool)671		buf_size = xsk_pool_get_rx_frame_size(ring->xsk_pool);672	else if (ring_uses_large_buffer(ring))673		buf_size = IGC_RXBUFFER_3072;674	else675		buf_size = IGC_RXBUFFER_2048;676 677	srrctl = rd32(IGC_SRRCTL(reg_idx));678	srrctl &= ~(IGC_SRRCTL_BSIZEPKT_MASK | IGC_SRRCTL_BSIZEHDR_MASK |679		    IGC_SRRCTL_DESCTYPE_MASK);680	srrctl |= IGC_SRRCTL_BSIZEHDR(IGC_RX_HDR_LEN);681	srrctl |= IGC_SRRCTL_BSIZEPKT(buf_size);682	srrctl |= IGC_SRRCTL_DESCTYPE_ADV_ONEBUF;683 684	wr32(IGC_SRRCTL(reg_idx), srrctl);685 686	rxdctl |= IGC_RX_PTHRESH;687	rxdctl |= IGC_RX_HTHRESH << 8;688	rxdctl |= IGC_RX_WTHRESH << 16;689 690	/* initialize rx_buffer_info */691	memset(ring->rx_buffer_info, 0,692	       sizeof(struct igc_rx_buffer) * ring->count);693 694	/* initialize Rx descriptor 0 */695	rx_desc = IGC_RX_DESC(ring, 0);696	rx_desc->wb.upper.length = 0;697 698	/* enable receive descriptor fetching */699	rxdctl |= IGC_RXDCTL_QUEUE_ENABLE;700 701	wr32(IGC_RXDCTL(reg_idx), rxdctl);702}703 704/**705 * igc_configure_rx - Configure receive Unit after Reset706 * @adapter: board private structure707 *708 * Configure the Rx unit of the MAC after a reset.709 */710static void igc_configure_rx(struct igc_adapter *adapter)711{712	int i;713 714	/* Setup the HW Rx Head and Tail Descriptor Pointers and715	 * the Base and Length of the Rx Descriptor Ring716	 */717	for (i = 0; i < adapter->num_rx_queues; i++)718		igc_configure_rx_ring(adapter, adapter->rx_ring[i]);719}720 721/**722 * igc_configure_tx_ring - Configure transmit ring after Reset723 * @adapter: board private structure724 * @ring: tx ring to configure725 *726 * Configure a transmit ring after a reset.727 */728static void igc_configure_tx_ring(struct igc_adapter *adapter,729				  struct igc_ring *ring)730{731	struct igc_hw *hw = &adapter->hw;732	int reg_idx = ring->reg_idx;733	u64 tdba = ring->dma;734	u32 txdctl = 0;735 736	ring->xsk_pool = igc_get_xsk_pool(adapter, ring);737 738	/* disable the queue */739	wr32(IGC_TXDCTL(reg_idx), 0);740	wrfl();741 742	wr32(IGC_TDLEN(reg_idx),743	     ring->count * sizeof(union igc_adv_tx_desc));744	wr32(IGC_TDBAL(reg_idx),745	     tdba & 0x00000000ffffffffULL);746	wr32(IGC_TDBAH(reg_idx), tdba >> 32);747 748	ring->tail = adapter->io_addr + IGC_TDT(reg_idx);749	wr32(IGC_TDH(reg_idx), 0);750	writel(0, ring->tail);751 752	txdctl |= IGC_TX_PTHRESH;753	txdctl |= IGC_TX_HTHRESH << 8;754	txdctl |= IGC_TX_WTHRESH << 16;755 756	txdctl |= IGC_TXDCTL_QUEUE_ENABLE;757	wr32(IGC_TXDCTL(reg_idx), txdctl);758}759 760/**761 * igc_configure_tx - Configure transmit Unit after Reset762 * @adapter: board private structure763 *764 * Configure the Tx unit of the MAC after a reset.765 */766static void igc_configure_tx(struct igc_adapter *adapter)767{768	int i;769 770	for (i = 0; i < adapter->num_tx_queues; i++)771		igc_configure_tx_ring(adapter, adapter->tx_ring[i]);772}773 774/**775 * igc_setup_mrqc - configure the multiple receive queue control registers776 * @adapter: Board private structure777 */778static void igc_setup_mrqc(struct igc_adapter *adapter)779{780	struct igc_hw *hw = &adapter->hw;781	u32 j, num_rx_queues;782	u32 mrqc, rxcsum;783	u32 rss_key[10];784 785	netdev_rss_key_fill(rss_key, sizeof(rss_key));786	for (j = 0; j < 10; j++)787		wr32(IGC_RSSRK(j), rss_key[j]);788 789	num_rx_queues = adapter->rss_queues;790 791	if (adapter->rss_indir_tbl_init != num_rx_queues) {792		for (j = 0; j < IGC_RETA_SIZE; j++)793			adapter->rss_indir_tbl[j] =794			(j * num_rx_queues) / IGC_RETA_SIZE;795		adapter->rss_indir_tbl_init = num_rx_queues;796	}797	igc_write_rss_indir_tbl(adapter);798 799	/* Disable raw packet checksumming so that RSS hash is placed in800	 * descriptor on writeback.  No need to enable TCP/UDP/IP checksum801	 * offloads as they are enabled by default802	 */803	rxcsum = rd32(IGC_RXCSUM);804	rxcsum |= IGC_RXCSUM_PCSD;805 806	/* Enable Receive Checksum Offload for SCTP */807	rxcsum |= IGC_RXCSUM_CRCOFL;808 809	/* Don't need to set TUOFL or IPOFL, they default to 1 */810	wr32(IGC_RXCSUM, rxcsum);811 812	/* Generate RSS hash based on packet types, TCP/UDP813	 * port numbers and/or IPv4/v6 src and dst addresses814	 */815	mrqc = IGC_MRQC_RSS_FIELD_IPV4 |816	       IGC_MRQC_RSS_FIELD_IPV4_TCP |817	       IGC_MRQC_RSS_FIELD_IPV6 |818	       IGC_MRQC_RSS_FIELD_IPV6_TCP |819	       IGC_MRQC_RSS_FIELD_IPV6_TCP_EX;820 821	if (adapter->flags & IGC_FLAG_RSS_FIELD_IPV4_UDP)822		mrqc |= IGC_MRQC_RSS_FIELD_IPV4_UDP;823	if (adapter->flags & IGC_FLAG_RSS_FIELD_IPV6_UDP)824		mrqc |= IGC_MRQC_RSS_FIELD_IPV6_UDP;825 826	mrqc |= IGC_MRQC_ENABLE_RSS_MQ;827 828	wr32(IGC_MRQC, mrqc);829}830 831/**832 * igc_setup_rctl - configure the receive control registers833 * @adapter: Board private structure834 */835static void igc_setup_rctl(struct igc_adapter *adapter)836{837	struct igc_hw *hw = &adapter->hw;838	u32 rctl;839 840	rctl = rd32(IGC_RCTL);841 842	rctl &= ~(3 << IGC_RCTL_MO_SHIFT);843	rctl &= ~(IGC_RCTL_LBM_TCVR | IGC_RCTL_LBM_MAC);844 845	rctl |= IGC_RCTL_EN | IGC_RCTL_BAM | IGC_RCTL_RDMTS_HALF |846		(hw->mac.mc_filter_type << IGC_RCTL_MO_SHIFT);847 848	/* enable stripping of CRC. Newer features require849	 * that the HW strips the CRC.850	 */851	rctl |= IGC_RCTL_SECRC;852 853	/* disable store bad packets and clear size bits. */854	rctl &= ~(IGC_RCTL_SBP | IGC_RCTL_SZ_256);855 856	/* enable LPE to allow for reception of jumbo frames */857	rctl |= IGC_RCTL_LPE;858 859	/* disable queue 0 to prevent tail write w/o re-config */860	wr32(IGC_RXDCTL(0), 0);861 862	/* This is useful for sniffing bad packets. */863	if (adapter->netdev->features & NETIF_F_RXALL) {864		/* UPE and MPE will be handled by normal PROMISC logic865		 * in set_rx_mode866		 */867		rctl |= (IGC_RCTL_SBP | /* Receive bad packets */868			 IGC_RCTL_BAM | /* RX All Bcast Pkts */869			 IGC_RCTL_PMCF); /* RX All MAC Ctrl Pkts */870 871		rctl &= ~(IGC_RCTL_DPF | /* Allow filtered pause */872			  IGC_RCTL_CFIEN); /* Disable VLAN CFIEN Filter */873	}874 875	wr32(IGC_RCTL, rctl);876}877 878/**879 * igc_setup_tctl - configure the transmit control registers880 * @adapter: Board private structure881 */882static void igc_setup_tctl(struct igc_adapter *adapter)883{884	struct igc_hw *hw = &adapter->hw;885	u32 tctl;886 887	/* disable queue 0 which icould be enabled by default */888	wr32(IGC_TXDCTL(0), 0);889 890	/* Program the Transmit Control Register */891	tctl = rd32(IGC_TCTL);892	tctl &= ~IGC_TCTL_CT;893	tctl |= IGC_TCTL_PSP | IGC_TCTL_RTLC |894		(IGC_COLLISION_THRESHOLD << IGC_CT_SHIFT);895 896	/* Enable transmits */897	tctl |= IGC_TCTL_EN;898 899	wr32(IGC_TCTL, tctl);900}901 902/**903 * igc_set_mac_filter_hw() - Set MAC address filter in hardware904 * @adapter: Pointer to adapter where the filter should be set905 * @index: Filter index906 * @type: MAC address filter type (source or destination)907 * @addr: MAC address908 * @queue: If non-negative, queue assignment feature is enabled and frames909 *         matching the filter are enqueued onto 'queue'. Otherwise, queue910 *         assignment is disabled.911 */912static void igc_set_mac_filter_hw(struct igc_adapter *adapter, int index,913				  enum igc_mac_filter_type type,914				  const u8 *addr, int queue)915{916	struct net_device *dev = adapter->netdev;917	struct igc_hw *hw = &adapter->hw;918	u32 ral, rah;919 920	if (WARN_ON(index >= hw->mac.rar_entry_count))921		return;922 923	ral = le32_to_cpup((__le32 *)(addr));924	rah = le16_to_cpup((__le16 *)(addr + 4));925 926	if (type == IGC_MAC_FILTER_TYPE_SRC) {927		rah &= ~IGC_RAH_ASEL_MASK;928		rah |= IGC_RAH_ASEL_SRC_ADDR;929	}930 931	if (queue >= 0) {932		rah &= ~IGC_RAH_QSEL_MASK;933		rah |= (queue << IGC_RAH_QSEL_SHIFT);934		rah |= IGC_RAH_QSEL_ENABLE;935	}936 937	rah |= IGC_RAH_AV;938 939	wr32(IGC_RAL(index), ral);940	wr32(IGC_RAH(index), rah);941 942	netdev_dbg(dev, "MAC address filter set in HW: index %d", index);943}944 945/**946 * igc_clear_mac_filter_hw() - Clear MAC address filter in hardware947 * @adapter: Pointer to adapter where the filter should be cleared948 * @index: Filter index949 */950static void igc_clear_mac_filter_hw(struct igc_adapter *adapter, int index)951{952	struct net_device *dev = adapter->netdev;953	struct igc_hw *hw = &adapter->hw;954 955	if (WARN_ON(index >= hw->mac.rar_entry_count))956		return;957 958	wr32(IGC_RAL(index), 0);959	wr32(IGC_RAH(index), 0);960 961	netdev_dbg(dev, "MAC address filter cleared in HW: index %d", index);962}963 964/* Set default MAC address for the PF in the first RAR entry */965static void igc_set_default_mac_filter(struct igc_adapter *adapter)966{967	struct net_device *dev = adapter->netdev;968	u8 *addr = adapter->hw.mac.addr;969 970	netdev_dbg(dev, "Set default MAC address filter: address %pM", addr);971 972	igc_set_mac_filter_hw(adapter, 0, IGC_MAC_FILTER_TYPE_DST, addr, -1);973}974 975/**976 * igc_set_mac - Change the Ethernet Address of the NIC977 * @netdev: network interface device structure978 * @p: pointer to an address structure979 *980 * Returns 0 on success, negative on failure981 */982static int igc_set_mac(struct net_device *netdev, void *p)983{984	struct igc_adapter *adapter = netdev_priv(netdev);985	struct igc_hw *hw = &adapter->hw;986	struct sockaddr *addr = p;987 988	if (!is_valid_ether_addr(addr->sa_data))989		return -EADDRNOTAVAIL;990 991	eth_hw_addr_set(netdev, addr->sa_data);992	memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);993 994	/* set the correct pool for the new PF MAC address in entry 0 */995	igc_set_default_mac_filter(adapter);996 997	return 0;998}999 1000/**1001 *  igc_write_mc_addr_list - write multicast addresses to MTA1002 *  @netdev: network interface device structure1003 *1004 *  Writes multicast address list to the MTA hash table.1005 *  Returns: -ENOMEM on failure1006 *           0 on no addresses written1007 *           X on writing X addresses to MTA1008 **/1009static int igc_write_mc_addr_list(struct net_device *netdev)1010{1011	struct igc_adapter *adapter = netdev_priv(netdev);1012	struct igc_hw *hw = &adapter->hw;1013	struct netdev_hw_addr *ha;1014	u8  *mta_list;1015	int i;1016 1017	if (netdev_mc_empty(netdev)) {1018		/* nothing to program, so clear mc list */1019		igc_update_mc_addr_list(hw, NULL, 0);1020		return 0;1021	}1022 1023	mta_list = kcalloc(netdev_mc_count(netdev), 6, GFP_ATOMIC);1024	if (!mta_list)1025		return -ENOMEM;1026 1027	/* The shared function expects a packed array of only addresses. */1028	i = 0;1029	netdev_for_each_mc_addr(ha, netdev)1030		memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);1031 1032	igc_update_mc_addr_list(hw, mta_list, i);1033	kfree(mta_list);1034 1035	return netdev_mc_count(netdev);1036}1037 1038static __le32 igc_tx_launchtime(struct igc_ring *ring, ktime_t txtime,1039				bool *first_flag, bool *insert_empty)1040{1041	struct igc_adapter *adapter = netdev_priv(ring->netdev);1042	ktime_t cycle_time = adapter->cycle_time;1043	ktime_t base_time = adapter->base_time;1044	ktime_t now = ktime_get_clocktai();1045	ktime_t baset_est, end_of_cycle;1046	s32 launchtime;1047	s64 n;1048 1049	n = div64_s64(ktime_sub_ns(now, base_time), cycle_time);1050 1051	baset_est = ktime_add_ns(base_time, cycle_time * (n));1052	end_of_cycle = ktime_add_ns(baset_est, cycle_time);1053 1054	if (ktime_compare(txtime, end_of_cycle) >= 0) {1055		if (baset_est != ring->last_ff_cycle) {1056			*first_flag = true;1057			ring->last_ff_cycle = baset_est;1058 1059			if (ktime_compare(end_of_cycle, ring->last_tx_cycle) > 0)1060				*insert_empty = true;1061		}1062	}1063 1064	/* Introducing a window at end of cycle on which packets1065	 * potentially not honor launchtime. Window of 5us chosen1066	 * considering software update the tail pointer and packets1067	 * are dma'ed to packet buffer.1068	 */1069	if ((ktime_sub_ns(end_of_cycle, now) < 5 * NSEC_PER_USEC))1070		netdev_warn(ring->netdev, "Packet with txtime=%llu may not be honoured\n",1071			    txtime);1072 1073	ring->last_tx_cycle = end_of_cycle;1074 1075	launchtime = ktime_sub_ns(txtime, baset_est);1076	if (launchtime > 0)1077		div_s64_rem(launchtime, cycle_time, &launchtime);1078	else1079		launchtime = 0;1080 1081	return cpu_to_le32(launchtime);1082}1083 1084static int igc_init_empty_frame(struct igc_ring *ring,1085				struct igc_tx_buffer *buffer,1086				struct sk_buff *skb)1087{1088	unsigned int size;1089	dma_addr_t dma;1090 1091	size = skb_headlen(skb);1092 1093	dma = dma_map_single(ring->dev, skb->data, size, DMA_TO_DEVICE);1094	if (dma_mapping_error(ring->dev, dma)) {1095		netdev_err_once(ring->netdev, "Failed to map DMA for TX\n");1096		return -ENOMEM;1097	}1098 1099	buffer->skb = skb;1100	buffer->protocol = 0;1101	buffer->bytecount = skb->len;1102	buffer->gso_segs = 1;1103	buffer->time_stamp = jiffies;1104	dma_unmap_len_set(buffer, len, skb->len);1105	dma_unmap_addr_set(buffer, dma, dma);1106 1107	return 0;1108}1109 1110static int igc_init_tx_empty_descriptor(struct igc_ring *ring,1111					struct sk_buff *skb,1112					struct igc_tx_buffer *first)1113{1114	union igc_adv_tx_desc *desc;1115	u32 cmd_type, olinfo_status;1116	int err;1117 1118	if (!igc_desc_unused(ring))1119		return -EBUSY;1120 1121	err = igc_init_empty_frame(ring, first, skb);1122	if (err)1123		return err;1124 1125	cmd_type = IGC_ADVTXD_DTYP_DATA | IGC_ADVTXD_DCMD_DEXT |1126		   IGC_ADVTXD_DCMD_IFCS | IGC_TXD_DCMD |1127		   first->bytecount;1128	olinfo_status = first->bytecount << IGC_ADVTXD_PAYLEN_SHIFT;1129 1130	desc = IGC_TX_DESC(ring, ring->next_to_use);1131	desc->read.cmd_type_len = cpu_to_le32(cmd_type);1132	desc->read.olinfo_status = cpu_to_le32(olinfo_status);1133	desc->read.buffer_addr = cpu_to_le64(dma_unmap_addr(first, dma));1134 1135	netdev_tx_sent_queue(txring_txq(ring), skb->len);1136 1137	first->next_to_watch = desc;1138 1139	ring->next_to_use++;1140	if (ring->next_to_use == ring->count)1141		ring->next_to_use = 0;1142 1143	return 0;1144}1145 1146#define IGC_EMPTY_FRAME_SIZE 601147 1148static void igc_tx_ctxtdesc(struct igc_ring *tx_ring,1149			    __le32 launch_time, bool first_flag,1150			    u32 vlan_macip_lens, u32 type_tucmd,1151			    u32 mss_l4len_idx)1152{1153	struct igc_adv_tx_context_desc *context_desc;1154	u16 i = tx_ring->next_to_use;1155 1156	context_desc = IGC_TX_CTXTDESC(tx_ring, i);1157 1158	i++;1159	tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;1160 1161	/* set bits to identify this as an advanced context descriptor */1162	type_tucmd |= IGC_TXD_CMD_DEXT | IGC_ADVTXD_DTYP_CTXT;1163 1164	/* For i225, context index must be unique per ring. */1165	if (test_bit(IGC_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))1166		mss_l4len_idx |= tx_ring->reg_idx << 4;1167 1168	if (first_flag)1169		mss_l4len_idx |= IGC_ADVTXD_TSN_CNTX_FIRST;1170 1171	context_desc->vlan_macip_lens	= cpu_to_le32(vlan_macip_lens);1172	context_desc->type_tucmd_mlhl	= cpu_to_le32(type_tucmd);1173	context_desc->mss_l4len_idx	= cpu_to_le32(mss_l4len_idx);1174	context_desc->launch_time	= launch_time;1175}1176 1177static void igc_tx_csum(struct igc_ring *tx_ring, struct igc_tx_buffer *first,1178			__le32 launch_time, bool first_flag)1179{1180	struct sk_buff *skb = first->skb;1181	u32 vlan_macip_lens = 0;1182	u32 type_tucmd = 0;1183 1184	if (skb->ip_summed != CHECKSUM_PARTIAL) {1185csum_failed:1186		if (!(first->tx_flags & IGC_TX_FLAGS_VLAN) &&1187		    !tx_ring->launchtime_enable)1188			return;1189		goto no_csum;1190	}1191 1192	switch (skb->csum_offset) {1193	case offsetof(struct tcphdr, check):1194		type_tucmd = IGC_ADVTXD_TUCMD_L4T_TCP;1195		fallthrough;1196	case offsetof(struct udphdr, check):1197		break;1198	case offsetof(struct sctphdr, checksum):1199		/* validate that this is actually an SCTP request */1200		if (skb_csum_is_sctp(skb)) {1201			type_tucmd = IGC_ADVTXD_TUCMD_L4T_SCTP;1202			break;1203		}1204		fallthrough;1205	default:1206		skb_checksum_help(skb);1207		goto csum_failed;1208	}1209 1210	/* update TX checksum flag */1211	first->tx_flags |= IGC_TX_FLAGS_CSUM;1212	vlan_macip_lens = skb_checksum_start_offset(skb) -1213			  skb_network_offset(skb);1214no_csum:1215	vlan_macip_lens |= skb_network_offset(skb) << IGC_ADVTXD_MACLEN_SHIFT;1216	vlan_macip_lens |= first->tx_flags & IGC_TX_FLAGS_VLAN_MASK;1217 1218	igc_tx_ctxtdesc(tx_ring, launch_time, first_flag,1219			vlan_macip_lens, type_tucmd, 0);1220}1221 1222static int __igc_maybe_stop_tx(struct igc_ring *tx_ring, const u16 size)1223{1224	struct net_device *netdev = tx_ring->netdev;1225 1226	netif_stop_subqueue(netdev, tx_ring->queue_index);1227 1228	/* memory barriier comment */1229	smp_mb();1230 1231	/* We need to check again in a case another CPU has just1232	 * made room available.1233	 */1234	if (igc_desc_unused(tx_ring) < size)1235		return -EBUSY;1236 1237	/* A reprieve! */1238	netif_wake_subqueue(netdev, tx_ring->queue_index);1239 1240	u64_stats_update_begin(&tx_ring->tx_syncp2);1241	tx_ring->tx_stats.restart_queue2++;1242	u64_stats_update_end(&tx_ring->tx_syncp2);1243 1244	return 0;1245}1246 1247static inline int igc_maybe_stop_tx(struct igc_ring *tx_ring, const u16 size)1248{1249	if (igc_desc_unused(tx_ring) >= size)1250		return 0;1251	return __igc_maybe_stop_tx(tx_ring, size);1252}1253 1254#define IGC_SET_FLAG(_input, _flag, _result) \1255	(((_flag) <= (_result)) ?				\1256	 ((u32)((_input) & (_flag)) * ((_result) / (_flag))) :	\1257	 ((u32)((_input) & (_flag)) / ((_flag) / (_result))))1258 1259static u32 igc_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)1260{1261	/* set type for advanced descriptor with frame checksum insertion */1262	u32 cmd_type = IGC_ADVTXD_DTYP_DATA |1263		       IGC_ADVTXD_DCMD_DEXT |1264		       IGC_ADVTXD_DCMD_IFCS;1265 1266	/* set HW vlan bit if vlan is present */1267	cmd_type |= IGC_SET_FLAG(tx_flags, IGC_TX_FLAGS_VLAN,1268				 IGC_ADVTXD_DCMD_VLE);1269 1270	/* set segmentation bits for TSO */1271	cmd_type |= IGC_SET_FLAG(tx_flags, IGC_TX_FLAGS_TSO,1272				 (IGC_ADVTXD_DCMD_TSE));1273 1274	/* set timestamp bit if present, will select the register set1275	 * based on the _TSTAMP(_X) bit.1276	 */1277	cmd_type |= IGC_SET_FLAG(tx_flags, IGC_TX_FLAGS_TSTAMP,1278				 (IGC_ADVTXD_MAC_TSTAMP));1279 1280	cmd_type |= IGC_SET_FLAG(tx_flags, IGC_TX_FLAGS_TSTAMP_1,1281				 (IGC_ADVTXD_TSTAMP_REG_1));1282 1283	cmd_type |= IGC_SET_FLAG(tx_flags, IGC_TX_FLAGS_TSTAMP_2,1284				 (IGC_ADVTXD_TSTAMP_REG_2));1285 1286	cmd_type |= IGC_SET_FLAG(tx_flags, IGC_TX_FLAGS_TSTAMP_3,1287				 (IGC_ADVTXD_TSTAMP_REG_3));1288 1289	/* insert frame checksum */1290	cmd_type ^= IGC_SET_FLAG(skb->no_fcs, 1, IGC_ADVTXD_DCMD_IFCS);1291 1292	return cmd_type;1293}1294 1295static void igc_tx_olinfo_status(struct igc_ring *tx_ring,1296				 union igc_adv_tx_desc *tx_desc,1297				 u32 tx_flags, unsigned int paylen)1298{1299	u32 olinfo_status = paylen << IGC_ADVTXD_PAYLEN_SHIFT;1300 1301	/* insert L4 checksum */1302	olinfo_status |= IGC_SET_FLAG(tx_flags, IGC_TX_FLAGS_CSUM,1303				      (IGC_TXD_POPTS_TXSM << 8));1304 1305	/* insert IPv4 checksum */1306	olinfo_status |= IGC_SET_FLAG(tx_flags, IGC_TX_FLAGS_IPV4,1307				      (IGC_TXD_POPTS_IXSM << 8));1308 1309	/* Use the second timer (free running, in general) for the timestamp */1310	olinfo_status |= IGC_SET_FLAG(tx_flags, IGC_TX_FLAGS_TSTAMP_TIMER_1,1311				      IGC_TXD_PTP2_TIMER_1);1312 1313	tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);1314}1315 1316static int igc_tx_map(struct igc_ring *tx_ring,1317		      struct igc_tx_buffer *first,1318		      const u8 hdr_len)1319{1320	struct sk_buff *skb = first->skb;1321	struct igc_tx_buffer *tx_buffer;1322	union igc_adv_tx_desc *tx_desc;1323	u32 tx_flags = first->tx_flags;1324	skb_frag_t *frag;1325	u16 i = tx_ring->next_to_use;1326	unsigned int data_len, size;1327	dma_addr_t dma;1328	u32 cmd_type;1329 1330	cmd_type = igc_tx_cmd_type(skb, tx_flags);1331	tx_desc = IGC_TX_DESC(tx_ring, i);1332 1333	igc_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len);1334 1335	size = skb_headlen(skb);1336	data_len = skb->data_len;1337 1338	dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);1339 1340	tx_buffer = first;1341 1342	for (frag = &skb_shinfo(skb)->frags[0];; frag++) {1343		if (dma_mapping_error(tx_ring->dev, dma))1344			goto dma_error;1345 1346		/* record length, and DMA address */1347		dma_unmap_len_set(tx_buffer, len, size);1348		dma_unmap_addr_set(tx_buffer, dma, dma);1349 1350		tx_desc->read.buffer_addr = cpu_to_le64(dma);1351 1352		while (unlikely(size > IGC_MAX_DATA_PER_TXD)) {1353			tx_desc->read.cmd_type_len =1354				cpu_to_le32(cmd_type ^ IGC_MAX_DATA_PER_TXD);1355 1356			i++;1357			tx_desc++;1358			if (i == tx_ring->count) {1359				tx_desc = IGC_TX_DESC(tx_ring, 0);1360				i = 0;1361			}1362			tx_desc->read.olinfo_status = 0;1363 1364			dma += IGC_MAX_DATA_PER_TXD;1365			size -= IGC_MAX_DATA_PER_TXD;1366 1367			tx_desc->read.buffer_addr = cpu_to_le64(dma);1368		}1369 1370		if (likely(!data_len))1371			break;1372 1373		tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);1374 1375		i++;1376		tx_desc++;1377		if (i == tx_ring->count) {1378			tx_desc = IGC_TX_DESC(tx_ring, 0);1379			i = 0;1380		}1381		tx_desc->read.olinfo_status = 0;1382 1383		size = skb_frag_size(frag);1384		data_len -= size;1385 1386		dma = skb_frag_dma_map(tx_ring->dev, frag, 0,1387				       size, DMA_TO_DEVICE);1388 1389		tx_buffer = &tx_ring->tx_buffer_info[i];1390	}1391 1392	/* write last descriptor with RS and EOP bits */1393	cmd_type |= size | IGC_TXD_DCMD;1394	tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);1395 1396	netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);1397 1398	/* set the timestamp */1399	first->time_stamp = jiffies;1400 1401	skb_tx_timestamp(skb);1402 1403	/* Force memory writes to complete before letting h/w know there1404	 * are new descriptors to fetch.  (Only applicable for weak-ordered1405	 * memory model archs, such as IA-64).1406	 *1407	 * We also need this memory barrier to make certain all of the1408	 * status bits have been updated before next_to_watch is written.1409	 */1410	wmb();1411 1412	/* set next_to_watch value indicating a packet is present */1413	first->next_to_watch = tx_desc;1414 1415	i++;1416	if (i == tx_ring->count)1417		i = 0;1418 1419	tx_ring->next_to_use = i;1420 1421	/* Make sure there is space in the ring for the next send. */1422	igc_maybe_stop_tx(tx_ring, DESC_NEEDED);1423 1424	if (netif_xmit_stopped(txring_txq(tx_ring)) || !netdev_xmit_more()) {1425		writel(i, tx_ring->tail);1426	}1427 1428	return 0;1429dma_error:1430	netdev_err(tx_ring->netdev, "TX DMA map failed\n");1431	tx_buffer = &tx_ring->tx_buffer_info[i];1432 1433	/* clear dma mappings for failed tx_buffer_info map */1434	while (tx_buffer != first) {1435		if (dma_unmap_len(tx_buffer, len))1436			igc_unmap_tx_buffer(tx_ring->dev, tx_buffer);1437 1438		if (i-- == 0)1439			i += tx_ring->count;1440		tx_buffer = &tx_ring->tx_buffer_info[i];1441	}1442 1443	if (dma_unmap_len(tx_buffer, len))1444		igc_unmap_tx_buffer(tx_ring->dev, tx_buffer);1445 1446	dev_kfree_skb_any(tx_buffer->skb);1447	tx_buffer->skb = NULL;1448 1449	tx_ring->next_to_use = i;1450 1451	return -1;1452}1453 1454static int igc_tso(struct igc_ring *tx_ring,1455		   struct igc_tx_buffer *first,1456		   __le32 launch_time, bool first_flag,1457		   u8 *hdr_len)1458{1459	u32 vlan_macip_lens, type_tucmd, mss_l4len_idx;1460	struct sk_buff *skb = first->skb;1461	union {1462		struct iphdr *v4;1463		struct ipv6hdr *v6;1464		unsigned char *hdr;1465	} ip;1466	union {1467		struct tcphdr *tcp;1468		struct udphdr *udp;1469		unsigned char *hdr;1470	} l4;1471	u32 paylen, l4_offset;1472	int err;1473 1474	if (skb->ip_summed != CHECKSUM_PARTIAL)1475		return 0;1476 1477	if (!skb_is_gso(skb))1478		return 0;1479 1480	err = skb_cow_head(skb, 0);1481	if (err < 0)1482		return err;1483 1484	ip.hdr = skb_network_header(skb);1485	l4.hdr = skb_checksum_start(skb);1486 1487	/* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */1488	type_tucmd = IGC_ADVTXD_TUCMD_L4T_TCP;1489 1490	/* initialize outer IP header fields */1491	if (ip.v4->version == 4) {1492		unsigned char *csum_start = skb_checksum_start(skb);1493		unsigned char *trans_start = ip.hdr + (ip.v4->ihl * 4);1494 1495		/* IP header will have to cancel out any data that1496		 * is not a part of the outer IP header1497		 */1498		ip.v4->check = csum_fold(csum_partial(trans_start,1499						      csum_start - trans_start,1500						      0));1501		type_tucmd |= IGC_ADVTXD_TUCMD_IPV4;1502 1503		ip.v4->tot_len = 0;1504		first->tx_flags |= IGC_TX_FLAGS_TSO |1505				   IGC_TX_FLAGS_CSUM |1506				   IGC_TX_FLAGS_IPV4;1507	} else {1508		ip.v6->payload_len = 0;1509		first->tx_flags |= IGC_TX_FLAGS_TSO |1510				   IGC_TX_FLAGS_CSUM;1511	}1512 1513	/* determine offset of inner transport header */1514	l4_offset = l4.hdr - skb->data;1515 1516	/* remove payload length from inner checksum */1517	paylen = skb->len - l4_offset;1518	if (type_tucmd & IGC_ADVTXD_TUCMD_L4T_TCP) {1519		/* compute length of segmentation header */1520		*hdr_len = (l4.tcp->doff * 4) + l4_offset;1521		csum_replace_by_diff(&l4.tcp->check,1522				     (__force __wsum)htonl(paylen));1523	} else {1524		/* compute length of segmentation header */1525		*hdr_len = sizeof(*l4.udp) + l4_offset;1526		csum_replace_by_diff(&l4.udp->check,1527				     (__force __wsum)htonl(paylen));1528	}1529 1530	/* update gso size and bytecount with header size */1531	first->gso_segs = skb_shinfo(skb)->gso_segs;1532	first->bytecount += (first->gso_segs - 1) * *hdr_len;1533 1534	/* MSS L4LEN IDX */1535	mss_l4len_idx = (*hdr_len - l4_offset) << IGC_ADVTXD_L4LEN_SHIFT;1536	mss_l4len_idx |= skb_shinfo(skb)->gso_size << IGC_ADVTXD_MSS_SHIFT;1537 1538	/* VLAN MACLEN IPLEN */1539	vlan_macip_lens = l4.hdr - ip.hdr;1540	vlan_macip_lens |= (ip.hdr - skb->data) << IGC_ADVTXD_MACLEN_SHIFT;1541	vlan_macip_lens |= first->tx_flags & IGC_TX_FLAGS_VLAN_MASK;1542 1543	igc_tx_ctxtdesc(tx_ring, launch_time, first_flag,1544			vlan_macip_lens, type_tucmd, mss_l4len_idx);1545 1546	return 1;1547}1548 1549static bool igc_request_tx_tstamp(struct igc_adapter *adapter, struct sk_buff *skb, u32 *flags)1550{1551	int i;1552 1553	for (i = 0; i < IGC_MAX_TX_TSTAMP_REGS; i++) {1554		struct igc_tx_timestamp_request *tstamp = &adapter->tx_tstamp[i];1555 1556		if (tstamp->skb)1557			continue;1558 1559		tstamp->skb = skb_get(skb);1560		tstamp->start = jiffies;1561		*flags = tstamp->flags;1562 1563		return true;1564	}1565 1566	return false;1567}1568 1569static netdev_tx_t igc_xmit_frame_ring(struct sk_buff *skb,1570				       struct igc_ring *tx_ring)1571{1572	struct igc_adapter *adapter = netdev_priv(tx_ring->netdev);1573	bool first_flag = false, insert_empty = false;1574	u16 count = TXD_USE_COUNT(skb_headlen(skb));1575	__be16 protocol = vlan_get_protocol(skb);1576	struct igc_tx_buffer *first;1577	__le32 launch_time = 0;1578	u32 tx_flags = 0;1579	unsigned short f;1580	ktime_t txtime;1581	u8 hdr_len = 0;1582	int tso = 0;1583 1584	/* need: 1 descriptor per page * PAGE_SIZE/IGC_MAX_DATA_PER_TXD,1585	 *	+ 1 desc for skb_headlen/IGC_MAX_DATA_PER_TXD,1586	 *	+ 2 desc gap to keep tail from touching head,1587	 *	+ 1 desc for context descriptor,1588	 * otherwise try next time1589	 */1590	for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)1591		count += TXD_USE_COUNT(skb_frag_size(1592						&skb_shinfo(skb)->frags[f]));1593 1594	if (igc_maybe_stop_tx(tx_ring, count + 5)) {1595		/* this is a hard error */1596		return NETDEV_TX_BUSY;1597	}1598 1599	if (!tx_ring->launchtime_enable)1600		goto done;1601 1602	txtime = skb->tstamp;1603	skb->tstamp = ktime_set(0, 0);1604	launch_time = igc_tx_launchtime(tx_ring, txtime, &first_flag, &insert_empty);1605 1606	if (insert_empty) {1607		struct igc_tx_buffer *empty_info;1608		struct sk_buff *empty;1609		void *data;1610 1611		empty_info = &tx_ring->tx_buffer_info[tx_ring->next_to_use];1612		empty = alloc_skb(IGC_EMPTY_FRAME_SIZE, GFP_ATOMIC);1613		if (!empty)1614			goto done;1615 1616		data = skb_put(empty, IGC_EMPTY_FRAME_SIZE);1617		memset(data, 0, IGC_EMPTY_FRAME_SIZE);1618 1619		igc_tx_ctxtdesc(tx_ring, 0, false, 0, 0, 0);1620 1621		if (igc_init_tx_empty_descriptor(tx_ring,1622						 empty,1623						 empty_info) < 0)1624			dev_kfree_skb_any(empty);1625	}1626 1627done:1628	/* record the location of the first descriptor for this packet */1629	first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];1630	first->type = IGC_TX_BUFFER_TYPE_SKB;1631	first->skb = skb;1632	first->bytecount = skb->len;1633	first->gso_segs = 1;1634 1635	if (adapter->qbv_transition || tx_ring->oper_gate_closed)1636		goto out_drop;1637 1638	if (tx_ring->max_sdu > 0 && first->bytecount > tx_ring->max_sdu) {1639		adapter->stats.txdrop++;1640		goto out_drop;1641	}1642 1643	if (unlikely(test_bit(IGC_RING_FLAG_TX_HWTSTAMP, &tx_ring->flags) &&1644		     skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {1645		unsigned long flags;1646		u32 tstamp_flags;1647 1648		spin_lock_irqsave(&adapter->ptp_tx_lock, flags);1649		if (igc_request_tx_tstamp(adapter, skb, &tstamp_flags)) {1650			skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;1651			tx_flags |= IGC_TX_FLAGS_TSTAMP | tstamp_flags;1652			if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP_USE_CYCLES)1653				tx_flags |= IGC_TX_FLAGS_TSTAMP_TIMER_1;1654		} else {1655			adapter->tx_hwtstamp_skipped++;1656		}1657 1658		spin_unlock_irqrestore(&adapter->ptp_tx_lock, flags);1659	}1660 1661	if (skb_vlan_tag_present(skb)) {1662		tx_flags |= IGC_TX_FLAGS_VLAN;1663		tx_flags |= (skb_vlan_tag_get(skb) << IGC_TX_FLAGS_VLAN_SHIFT);1664	}1665 1666	/* record initial flags and protocol */1667	first->tx_flags = tx_flags;1668	first->protocol = protocol;1669 1670	tso = igc_tso(tx_ring, first, launch_time, first_flag, &hdr_len);1671	if (tso < 0)1672		goto out_drop;1673	else if (!tso)1674		igc_tx_csum(tx_ring, first, launch_time, first_flag);1675 1676	igc_tx_map(tx_ring, first, hdr_len);1677 1678	return NETDEV_TX_OK;1679 1680out_drop:1681	dev_kfree_skb_any(first->skb);1682	first->skb = NULL;1683 1684	return NETDEV_TX_OK;1685}1686 1687static inline struct igc_ring *igc_tx_queue_mapping(struct igc_adapter *adapter,1688						    struct sk_buff *skb)1689{1690	unsigned int r_idx = skb->queue_mapping;1691 1692	if (r_idx >= adapter->num_tx_queues)1693		r_idx = r_idx % adapter->num_tx_queues;1694 1695	return adapter->tx_ring[r_idx];1696}1697 1698static netdev_tx_t igc_xmit_frame(struct sk_buff *skb,1699				  struct net_device *netdev)1700{1701	struct igc_adapter *adapter = netdev_priv(netdev);1702 1703	/* The minimum packet size with TCTL.PSP set is 17 so pad the skb1704	 * in order to meet this minimum size requirement.1705	 */1706	if (skb->len < 17) {1707		if (skb_padto(skb, 17))1708			return NETDEV_TX_OK;1709		skb->len = 17;1710	}1711 1712	return igc_xmit_frame_ring(skb, igc_tx_queue_mapping(adapter, skb));1713}1714 1715static void igc_rx_checksum(struct igc_ring *ring,1716			    union igc_adv_rx_desc *rx_desc,1717			    struct sk_buff *skb)1718{1719	skb_checksum_none_assert(skb);1720 1721	/* Ignore Checksum bit is set */1722	if (igc_test_staterr(rx_desc, IGC_RXD_STAT_IXSM))1723		return;1724 1725	/* Rx checksum disabled via ethtool */1726	if (!(ring->netdev->features & NETIF_F_RXCSUM))1727		return;1728 1729	/* TCP/UDP checksum error bit is set */1730	if (igc_test_staterr(rx_desc,1731			     IGC_RXDEXT_STATERR_L4E |1732			     IGC_RXDEXT_STATERR_IPE)) {1733		/* work around errata with sctp packets where the TCPE aka1734		 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)1735		 * packets (aka let the stack check the crc32c)1736		 */1737		if (!(skb->len == 60 &&1738		      test_bit(IGC_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) {1739			u64_stats_update_begin(&ring->rx_syncp);1740			ring->rx_stats.csum_err++;1741			u64_stats_update_end(&ring->rx_syncp);1742		}1743		/* let the stack verify checksum errors */1744		return;1745	}1746	/* It must be a TCP or UDP packet with a valid checksum */1747	if (igc_test_staterr(rx_desc, IGC_RXD_STAT_TCPCS |1748				      IGC_RXD_STAT_UDPCS))1749		skb->ip_summed = CHECKSUM_UNNECESSARY;1750 1751	netdev_dbg(ring->netdev, "cksum success: bits %08X\n",1752		   le32_to_cpu(rx_desc->wb.upper.status_error));1753}1754 1755/* Mapping HW RSS Type to enum pkt_hash_types */1756static const enum pkt_hash_types igc_rss_type_table[IGC_RSS_TYPE_MAX_TABLE] = {1757	[IGC_RSS_TYPE_NO_HASH]		= PKT_HASH_TYPE_L2,1758	[IGC_RSS_TYPE_HASH_TCP_IPV4]	= PKT_HASH_TYPE_L4,1759	[IGC_RSS_TYPE_HASH_IPV4]	= PKT_HASH_TYPE_L3,1760	[IGC_RSS_TYPE_HASH_TCP_IPV6]	= PKT_HASH_TYPE_L4,1761	[IGC_RSS_TYPE_HASH_IPV6_EX]	= PKT_HASH_TYPE_L3,1762	[IGC_RSS_TYPE_HASH_IPV6]	= PKT_HASH_TYPE_L3,1763	[IGC_RSS_TYPE_HASH_TCP_IPV6_EX] = PKT_HASH_TYPE_L4,1764	[IGC_RSS_TYPE_HASH_UDP_IPV4]	= PKT_HASH_TYPE_L4,1765	[IGC_RSS_TYPE_HASH_UDP_IPV6]	= PKT_HASH_TYPE_L4,1766	[IGC_RSS_TYPE_HASH_UDP_IPV6_EX] = PKT_HASH_TYPE_L4,1767	[10] = PKT_HASH_TYPE_NONE, /* RSS Type above 9 "Reserved" by HW  */1768	[11] = PKT_HASH_TYPE_NONE, /* keep array sized for SW bit-mask   */1769	[12] = PKT_HASH_TYPE_NONE, /* to handle future HW revisons       */1770	[13] = PKT_HASH_TYPE_NONE,1771	[14] = PKT_HASH_TYPE_NONE,1772	[15] = PKT_HASH_TYPE_NONE,1773};1774 1775static inline void igc_rx_hash(struct igc_ring *ring,1776			       union igc_adv_rx_desc *rx_desc,1777			       struct sk_buff *skb)1778{1779	if (ring->netdev->features & NETIF_F_RXHASH) {1780		u32 rss_hash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);1781		u32 rss_type = igc_rss_type(rx_desc);1782 1783		skb_set_hash(skb, rss_hash, igc_rss_type_table[rss_type]);1784	}1785}1786 1787static void igc_rx_vlan(struct igc_ring *rx_ring,1788			union igc_adv_rx_desc *rx_desc,1789			struct sk_buff *skb)1790{1791	struct net_device *dev = rx_ring->netdev;1792	u16 vid;1793 1794	if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&1795	    igc_test_staterr(rx_desc, IGC_RXD_STAT_VP)) {1796		if (igc_test_staterr(rx_desc, IGC_RXDEXT_STATERR_LB) &&1797		    test_bit(IGC_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags))1798			vid = be16_to_cpu((__force __be16)rx_desc->wb.upper.vlan);1799		else1800			vid = le16_to_cpu(rx_desc->wb.upper.vlan);1801 1802		__vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);1803	}1804}1805 1806/**1807 * igc_process_skb_fields - Populate skb header fields from Rx descriptor1808 * @rx_ring: rx descriptor ring packet is being transacted on1809 * @rx_desc: pointer to the EOP Rx descriptor1810 * @skb: pointer to current skb being populated1811 *1812 * This function checks the ring, descriptor, and packet information in order1813 * to populate the hash, checksum, VLAN, protocol, and other fields within the1814 * skb.1815 */1816static void igc_process_skb_fields(struct igc_ring *rx_ring,1817				   union igc_adv_rx_desc *rx_desc,1818				   struct sk_buff *skb)1819{1820	igc_rx_hash(rx_ring, rx_desc, skb);1821 1822	igc_rx_checksum(rx_ring, rx_desc, skb);1823 1824	igc_rx_vlan(rx_ring, rx_desc, skb);1825 1826	skb_record_rx_queue(skb, rx_ring->queue_index);1827 1828	skb->protocol = eth_type_trans(skb, rx_ring->netdev);1829}1830 1831static void igc_vlan_mode(struct net_device *netdev, netdev_features_t features)1832{1833	bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX);1834	struct igc_adapter *adapter = netdev_priv(netdev);1835	struct igc_hw *hw = &adapter->hw;1836	u32 ctrl;1837 1838	ctrl = rd32(IGC_CTRL);1839 1840	if (enable) {1841		/* enable VLAN tag insert/strip */1842		ctrl |= IGC_CTRL_VME;1843	} else {1844		/* disable VLAN tag insert/strip */1845		ctrl &= ~IGC_CTRL_VME;1846	}1847	wr32(IGC_CTRL, ctrl);1848}1849 1850static void igc_restore_vlan(struct igc_adapter *adapter)1851{1852	igc_vlan_mode(adapter->netdev, adapter->netdev->features);1853}1854 1855static struct igc_rx_buffer *igc_get_rx_buffer(struct igc_ring *rx_ring,1856					       const unsigned int size,1857					       int *rx_buffer_pgcnt)1858{1859	struct igc_rx_buffer *rx_buffer;1860 1861	rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];1862	*rx_buffer_pgcnt =1863#if (PAGE_SIZE < 8192)1864		page_count(rx_buffer->page);1865#else1866		0;1867#endif1868	prefetchw(rx_buffer->page);1869 1870	/* we are reusing so sync this buffer for CPU use */1871	dma_sync_single_range_for_cpu(rx_ring->dev,1872				      rx_buffer->dma,1873				      rx_buffer->page_offset,1874				      size,1875				      DMA_FROM_DEVICE);1876 1877	rx_buffer->pagecnt_bias--;1878 1879	return rx_buffer;1880}1881 1882static void igc_rx_buffer_flip(struct igc_rx_buffer *buffer,1883			       unsigned int truesize)1884{1885#if (PAGE_SIZE < 8192)1886	buffer->page_offset ^= truesize;1887#else1888	buffer->page_offset += truesize;1889#endif1890}1891 1892static unsigned int igc_get_rx_frame_truesize(struct igc_ring *ring,1893					      unsigned int size)1894{1895	unsigned int truesize;1896 1897#if (PAGE_SIZE < 8192)1898	truesize = igc_rx_pg_size(ring) / 2;1899#else1900	truesize = ring_uses_build_skb(ring) ?1901		   SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) +1902		   SKB_DATA_ALIGN(IGC_SKB_PAD + size) :1903		   SKB_DATA_ALIGN(size);1904#endif1905	return truesize;1906}1907 1908/**1909 * igc_add_rx_frag - Add contents of Rx buffer to sk_buff1910 * @rx_ring: rx descriptor ring to transact packets on1911 * @rx_buffer: buffer containing page to add1912 * @skb: sk_buff to place the data into1913 * @size: size of buffer to be added1914 *1915 * This function will add the data contained in rx_buffer->page to the skb.1916 */1917static void igc_add_rx_frag(struct igc_ring *rx_ring,1918			    struct igc_rx_buffer *rx_buffer,1919			    struct sk_buff *skb,1920			    unsigned int size)1921{1922	unsigned int truesize;1923 1924#if (PAGE_SIZE < 8192)1925	truesize = igc_rx_pg_size(rx_ring) / 2;1926#else1927	truesize = ring_uses_build_skb(rx_ring) ?1928		   SKB_DATA_ALIGN(IGC_SKB_PAD + size) :1929		   SKB_DATA_ALIGN(size);1930#endif1931	skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page,1932			rx_buffer->page_offset, size, truesize);1933 1934	igc_rx_buffer_flip(rx_buffer, truesize);1935}1936 1937static struct sk_buff *igc_build_skb(struct igc_ring *rx_ring,1938				     struct igc_rx_buffer *rx_buffer,1939				     struct xdp_buff *xdp)1940{1941	unsigned int size = xdp->data_end - xdp->data;1942	unsigned int truesize = igc_get_rx_frame_truesize(rx_ring, size);1943	unsigned int metasize = xdp->data - xdp->data_meta;1944	struct sk_buff *skb;1945 1946	/* prefetch first cache line of first page */1947	net_prefetch(xdp->data_meta);1948 1949	/* build an skb around the page buffer */1950	skb = napi_build_skb(xdp->data_hard_start, truesize);1951	if (unlikely(!skb))1952		return NULL;1953 1954	/* update pointers within the skb to store the data */1955	skb_reserve(skb, xdp->data - xdp->data_hard_start);1956	__skb_put(skb, size);1957	if (metasize)1958		skb_metadata_set(skb, metasize);1959 1960	igc_rx_buffer_flip(rx_buffer, truesize);1961	return skb;1962}1963 1964static struct sk_buff *igc_construct_skb(struct igc_ring *rx_ring,1965					 struct igc_rx_buffer *rx_buffer,1966					 struct igc_xdp_buff *ctx)1967{1968	struct xdp_buff *xdp = &ctx->xdp;1969	unsigned int metasize = xdp->data - xdp->data_meta;1970	unsigned int size = xdp->data_end - xdp->data;1971	unsigned int truesize = igc_get_rx_frame_truesize(rx_ring, size);1972	void *va = xdp->data;1973	unsigned int headlen;1974	struct sk_buff *skb;1975 1976	/* prefetch first cache line of first page */1977	net_prefetch(xdp->data_meta);1978 1979	/* allocate a skb to store the frags */1980	skb = napi_alloc_skb(&rx_ring->q_vector->napi,1981			     IGC_RX_HDR_LEN + metasize);1982	if (unlikely(!skb))1983		return NULL;1984 1985	if (ctx->rx_ts) {1986		skb_shinfo(skb)->tx_flags |= SKBTX_HW_TSTAMP_NETDEV;1987		skb_hwtstamps(skb)->netdev_data = ctx->rx_ts;1988	}1989 1990	/* Determine available headroom for copy */1991	headlen = size;1992	if (headlen > IGC_RX_HDR_LEN)1993		headlen = eth_get_headlen(skb->dev, va, IGC_RX_HDR_LEN);1994 1995	/* align pull length to size of long to optimize memcpy performance */1996	memcpy(__skb_put(skb, headlen + metasize), xdp->data_meta,1997	       ALIGN(headlen + metasize, sizeof(long)));1998 1999	if (metasize) {2000		skb_metadata_set(skb, metasize);2001		__skb_pull(skb, metasize);2002	}2003 2004	/* update all of the pointers */2005	size -= headlen;2006	if (size) {2007		skb_add_rx_frag(skb, 0, rx_buffer->page,2008				(va + headlen) - page_address(rx_buffer->page),2009				size, truesize);2010		igc_rx_buffer_flip(rx_buffer, truesize);2011	} else {2012		rx_buffer->pagecnt_bias++;2013	}2014 2015	return skb;2016}2017 2018/**2019 * igc_reuse_rx_page - page flip buffer and store it back on the ring2020 * @rx_ring: rx descriptor ring to store buffers on2021 * @old_buff: donor buffer to have page reused2022 *2023 * Synchronizes page for reuse by the adapter2024 */2025static void igc_reuse_rx_page(struct igc_ring *rx_ring,2026			      struct igc_rx_buffer *old_buff)2027{2028	u16 nta = rx_ring->next_to_alloc;2029	struct igc_rx_buffer *new_buff;2030 2031	new_buff = &rx_ring->rx_buffer_info[nta];2032 2033	/* update, and store next to alloc */2034	nta++;2035	rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;2036 2037	/* Transfer page from old buffer to new buffer.2038	 * Move each member individually to avoid possible store2039	 * forwarding stalls.2040	 */2041	new_buff->dma		= old_buff->dma;2042	new_buff->page		= old_buff->page;2043	new_buff->page_offset	= old_buff->page_offset;2044	new_buff->pagecnt_bias	= old_buff->pagecnt_bias;2045}2046 2047static bool igc_can_reuse_rx_page(struct igc_rx_buffer *rx_buffer,2048				  int rx_buffer_pgcnt)2049{2050	unsigned int pagecnt_bias = rx_buffer->pagecnt_bias;2051	struct page *page = rx_buffer->page;2052 2053	/* avoid re-using remote and pfmemalloc pages */2054	if (!dev_page_is_reusable(page))2055		return false;2056 2057#if (PAGE_SIZE < 8192)2058	/* if we are only owner of page we can reuse it */2059	if (unlikely((rx_buffer_pgcnt - pagecnt_bias) > 1))2060		return false;2061#else2062#define IGC_LAST_OFFSET \2063	(SKB_WITH_OVERHEAD(PAGE_SIZE) - IGC_RXBUFFER_2048)2064 2065	if (rx_buffer->page_offset > IGC_LAST_OFFSET)2066		return false;2067#endif2068 2069	/* If we have drained the page fragment pool we need to update2070	 * the pagecnt_bias and page count so that we fully restock the2071	 * number of references the driver holds.2072	 */2073	if (unlikely(pagecnt_bias == 1)) {2074		page_ref_add(page, USHRT_MAX - 1);2075		rx_buffer->pagecnt_bias = USHRT_MAX;2076	}2077 2078	return true;2079}2080 2081/**2082 * igc_is_non_eop - process handling of non-EOP buffers2083 * @rx_ring: Rx ring being processed2084 * @rx_desc: Rx descriptor for current buffer2085 *2086 * This function updates next to clean.  If the buffer is an EOP buffer2087 * this function exits returning false, otherwise it will place the2088 * sk_buff in the next buffer to be chained and return true indicating2089 * that this is in fact a non-EOP buffer.2090 */2091static bool igc_is_non_eop(struct igc_ring *rx_ring,2092			   union igc_adv_rx_desc *rx_desc)2093{2094	u32 ntc = rx_ring->next_to_clean + 1;2095 2096	/* fetch, update, and store next to clean */2097	ntc = (ntc < rx_ring->count) ? ntc : 0;2098	rx_ring->next_to_clean = ntc;2099 2100	prefetch(IGC_RX_DESC(rx_ring, ntc));2101 2102	if (likely(igc_test_staterr(rx_desc, IGC_RXD_STAT_EOP)))2103		return false;2104 2105	return true;2106}2107 2108/**2109 * igc_cleanup_headers - Correct corrupted or empty headers2110 * @rx_ring: rx descriptor ring packet is being transacted on2111 * @rx_desc: pointer to the EOP Rx descriptor2112 * @skb: pointer to current skb being fixed2113 *2114 * Address the case where we are pulling data in on pages only2115 * and as such no data is present in the skb header.2116 *2117 * In addition if skb is not at least 60 bytes we need to pad it so that2118 * it is large enough to qualify as a valid Ethernet frame.2119 *2120 * Returns true if an error was encountered and skb was freed.2121 */2122static bool igc_cleanup_headers(struct igc_ring *rx_ring,2123				union igc_adv_rx_desc *rx_desc,2124				struct sk_buff *skb)2125{2126	/* XDP packets use error pointer so abort at this point */2127	if (IS_ERR(skb))2128		return true;2129 2130	if (unlikely(igc_test_staterr(rx_desc, IGC_RXDEXT_STATERR_RXE))) {2131		struct net_device *netdev = rx_ring->netdev;2132 2133		if (!(netdev->features & NETIF_F_RXALL)) {2134			dev_kfree_skb_any(skb);2135			return true;2136		}2137	}2138 2139	/* if eth_skb_pad returns an error the skb was freed */2140	if (eth_skb_pad(skb))2141		return true;2142 2143	return false;2144}2145 2146static void igc_put_rx_buffer(struct igc_ring *rx_ring,2147			      struct igc_rx_buffer *rx_buffer,2148			      int rx_buffer_pgcnt)2149{2150	if (igc_can_reuse_rx_page(rx_buffer, rx_buffer_pgcnt)) {2151		/* hand second half of page back to the ring */2152		igc_reuse_rx_page(rx_ring, rx_buffer);2153	} else {2154		/* We are not reusing the buffer so unmap it and free2155		 * any references we are holding to it2156		 */2157		dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma,2158				     igc_rx_pg_size(rx_ring), DMA_FROM_DEVICE,2159				     IGC_RX_DMA_ATTR);2160		__page_frag_cache_drain(rx_buffer->page,2161					rx_buffer->pagecnt_bias);2162	}2163 2164	/* clear contents of rx_buffer */2165	rx_buffer->page = NULL;2166}2167 2168static inline unsigned int igc_rx_offset(struct igc_ring *rx_ring)2169{2170	struct igc_adapter *adapter = rx_ring->q_vector->adapter;2171 2172	if (ring_uses_build_skb(rx_ring))2173		return IGC_SKB_PAD;2174	if (igc_xdp_is_enabled(adapter))2175		return XDP_PACKET_HEADROOM;2176 2177	return 0;2178}2179 2180static bool igc_alloc_mapped_page(struct igc_ring *rx_ring,2181				  struct igc_rx_buffer *bi)2182{2183	struct page *page = bi->page;2184	dma_addr_t dma;2185 2186	/* since we are recycling buffers we should seldom need to alloc */2187	if (likely(page))2188		return true;2189 2190	/* alloc new page for storage */2191	page = dev_alloc_pages(igc_rx_pg_order(rx_ring));2192	if (unlikely(!page)) {2193		rx_ring->rx_stats.alloc_failed++;2194		set_bit(IGC_RING_FLAG_RX_ALLOC_FAILED, &rx_ring->flags);2195		return false;2196	}2197 2198	/* map page for use */2199	dma = dma_map_page_attrs(rx_ring->dev, page, 0,2200				 igc_rx_pg_size(rx_ring),2201				 DMA_FROM_DEVICE,2202				 IGC_RX_DMA_ATTR);2203 2204	/* if mapping failed free memory back to system since2205	 * there isn't much point in holding memory we can't use2206	 */2207	if (dma_mapping_error(rx_ring->dev, dma)) {2208		__free_page(page);2209 2210		rx_ring->rx_stats.alloc_failed++;2211		set_bit(IGC_RING_FLAG_RX_ALLOC_FAILED, &rx_ring->flags);2212		return false;2213	}2214 2215	bi->dma = dma;2216	bi->page = page;2217	bi->page_offset = igc_rx_offset(rx_ring);2218	page_ref_add(page, USHRT_MAX - 1);2219	bi->pagecnt_bias = USHRT_MAX;2220 2221	return true;2222}2223 2224/**2225 * igc_alloc_rx_buffers - Replace used receive buffers; packet split2226 * @rx_ring: rx descriptor ring2227 * @cleaned_count: number of buffers to clean2228 */2229static void igc_alloc_rx_buffers(struct igc_ring *rx_ring, u16 cleaned_count)2230{2231	union igc_adv_rx_desc *rx_desc;2232	u16 i = rx_ring->next_to_use;2233	struct igc_rx_buffer *bi;2234	u16 bufsz;2235 2236	/* nothing to do */2237	if (!cleaned_count)2238		return;2239 2240	rx_desc = IGC_RX_DESC(rx_ring, i);2241	bi = &rx_ring->rx_buffer_info[i];2242	i -= rx_ring->count;2243 2244	bufsz = igc_rx_bufsz(rx_ring);2245 2246	do {2247		if (!igc_alloc_mapped_page(rx_ring, bi))2248			break;2249 2250		/* sync the buffer for use by the device */2251		dma_sync_single_range_for_device(rx_ring->dev, bi->dma,2252						 bi->page_offset, bufsz,2253						 DMA_FROM_DEVICE);2254 2255		/* Refresh the desc even if buffer_addrs didn't change2256		 * because each write-back erases this info.2257		 */2258		rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);2259 2260		rx_desc++;2261		bi++;2262		i++;2263		if (unlikely(!i)) {2264			rx_desc = IGC_RX_DESC(rx_ring, 0);2265			bi = rx_ring->rx_buffer_info;2266			i -= rx_ring->count;2267		}2268 2269		/* clear the length for the next_to_use descriptor */2270		rx_desc->wb.upper.length = 0;2271 2272		cleaned_count--;2273	} while (cleaned_count);2274 2275	i += rx_ring->count;2276 2277	if (rx_ring->next_to_use != i) {2278		/* record the next descriptor to use */2279		rx_ring->next_to_use = i;2280 2281		/* update next to alloc since we have filled the ring */2282		rx_ring->next_to_alloc = i;2283 2284		/* Force memory writes to complete before letting h/w2285		 * know there are new descriptors to fetch.  (Only2286		 * applicable for weak-ordered memory model archs,2287		 * such as IA-64).2288		 */2289		wmb();2290		writel(i, rx_ring->tail);2291	}2292}2293 2294static bool igc_alloc_rx_buffers_zc(struct igc_ring *ring, u16 count)2295{2296	union igc_adv_rx_desc *desc;2297	u16 i = ring->next_to_use;2298	struct igc_rx_buffer *bi;2299	dma_addr_t dma;2300	bool ok = true;2301 2302	if (!count)2303		return ok;2304 2305	XSK_CHECK_PRIV_TYPE(struct igc_xdp_buff);2306 2307	desc = IGC_RX_DESC(ring, i);2308	bi = &ring->rx_buffer_info[i];2309	i -= ring->count;2310 2311	do {2312		bi->xdp = xsk_buff_alloc(ring->xsk_pool);2313		if (!bi->xdp) {2314			ok = false;2315			break;2316		}2317 2318		dma = xsk_buff_xdp_get_dma(bi->xdp);2319		desc->read.pkt_addr = cpu_to_le64(dma);2320 2321		desc++;2322		bi++;2323		i++;2324		if (unlikely(!i)) {2325			desc = IGC_RX_DESC(ring, 0);2326			bi = ring->rx_buffer_info;2327			i -= ring->count;2328		}2329 2330		/* Clear the length for the next_to_use descriptor. */2331		desc->wb.upper.length = 0;2332 2333		count--;2334	} while (count);2335 2336	i += ring->count;2337 2338	if (ring->next_to_use != i) {2339		ring->next_to_use = i;2340 2341		/* Force memory writes to complete before letting h/w2342		 * know there are new descriptors to fetch.  (Only2343		 * applicable for weak-ordered memory model archs,2344		 * such as IA-64).2345		 */2346		wmb();2347		writel(i, ring->tail);2348	}2349 2350	return ok;2351}2352 2353/* This function requires __netif_tx_lock is held by the caller. */2354static int igc_xdp_init_tx_descriptor(struct igc_ring *ring,2355				      struct xdp_frame *xdpf)2356{2357	struct skb_shared_info *sinfo = xdp_get_shared_info_from_frame(xdpf);2358	u8 nr_frags = unlikely(xdp_frame_has_frags(xdpf)) ? sinfo->nr_frags : 0;2359	u16 count, index = ring->next_to_use;2360	struct igc_tx_buffer *head = &ring->tx_buffer_info[index];2361	struct igc_tx_buffer *buffer = head;2362	union igc_adv_tx_desc *desc = IGC_TX_DESC(ring, index);2363	u32 olinfo_status, len = xdpf->len, cmd_type;2364	void *data = xdpf->data;2365	u16 i;2366 2367	count = TXD_USE_COUNT(len);2368	for (i = 0; i < nr_frags; i++)2369		count += TXD_USE_COUNT(skb_frag_size(&sinfo->frags[i]));2370 2371	if (igc_maybe_stop_tx(ring, count + 3)) {2372		/* this is a hard error */2373		return -EBUSY;2374	}2375 2376	i = 0;2377	head->bytecount = xdp_get_frame_len(xdpf);2378	head->type = IGC_TX_BUFFER_TYPE_XDP;2379	head->gso_segs = 1;2380	head->xdpf = xdpf;2381 2382	olinfo_status = head->bytecount << IGC_ADVTXD_PAYLEN_SHIFT;2383	desc->read.olinfo_status = cpu_to_le32(olinfo_status);2384 2385	for (;;) {2386		dma_addr_t dma;2387 2388		dma = dma_map_single(ring->dev, data, len, DMA_TO_DEVICE);2389		if (dma_mapping_error(ring->dev, dma)) {2390			netdev_err_once(ring->netdev,2391					"Failed to map DMA for TX\n");2392			goto unmap;2393		}2394 2395		dma_unmap_len_set(buffer, len, len);2396		dma_unmap_addr_set(buffer, dma, dma);2397 2398		cmd_type = IGC_ADVTXD_DTYP_DATA | IGC_ADVTXD_DCMD_DEXT |2399			   IGC_ADVTXD_DCMD_IFCS | len;2400 2401		desc->read.cmd_type_len = cpu_to_le32(cmd_type);2402		desc->read.buffer_addr = cpu_to_le64(dma);2403 2404		buffer->protocol = 0;2405 2406		if (++index == ring->count)2407			index = 0;2408 2409		if (i == nr_frags)2410			break;2411 2412		buffer = &ring->tx_buffer_info[index];2413		desc = IGC_TX_DESC(ring, index);2414		desc->read.olinfo_status = 0;2415 2416		data = skb_frag_address(&sinfo->frags[i]);2417		len = skb_frag_size(&sinfo->frags[i]);2418		i++;2419	}2420	desc->read.cmd_type_len |= cpu_to_le32(IGC_TXD_DCMD);2421 2422	netdev_tx_sent_queue(txring_txq(ring), head->bytecount);2423	/* set the timestamp */2424	head->time_stamp = jiffies;2425	/* set next_to_watch value indicating a packet is present */2426	head->next_to_watch = desc;2427	ring->next_to_use = index;2428 2429	return 0;2430 2431unmap:2432	for (;;) {2433		buffer = &ring->tx_buffer_info[index];2434		if (dma_unmap_len(buffer, len))2435			dma_unmap_page(ring->dev,2436				       dma_unmap_addr(buffer, dma),2437				       dma_unmap_len(buffer, len),2438				       DMA_TO_DEVICE);2439		dma_unmap_len_set(buffer, len, 0);2440		if (buffer == head)2441			break;2442 2443		if (!index)2444			index += ring->count;2445		index--;2446	}2447 2448	return -ENOMEM;2449}2450 2451static struct igc_ring *igc_xdp_get_tx_ring(struct igc_adapter *adapter,2452					    int cpu)2453{2454	int index = cpu;2455 2456	if (unlikely(index < 0))2457		index = 0;2458 2459	while (index >= adapter->num_tx_queues)2460		index -= adapter->num_tx_queues;2461 2462	return adapter->tx_ring[index];2463}2464 2465static int igc_xdp_xmit_back(struct igc_adapter *adapter, struct xdp_buff *xdp)2466{2467	struct xdp_frame *xdpf = xdp_convert_buff_to_frame(xdp);2468	int cpu = smp_processor_id();2469	struct netdev_queue *nq;2470	struct igc_ring *ring;2471	int res;2472 2473	if (unlikely(!xdpf))2474		return -EFAULT;2475 2476	ring = igc_xdp_get_tx_ring(adapter, cpu);2477	nq = txring_txq(ring);2478 2479	__netif_tx_lock(nq, cpu);2480	/* Avoid transmit queue timeout since we share it with the slow path */2481	txq_trans_cond_update(nq);2482	res = igc_xdp_init_tx_descriptor(ring, xdpf);2483	__netif_tx_unlock(nq);2484	return res;2485}2486 2487/* This function assumes rcu_read_lock() is held by the caller. */2488static int __igc_xdp_run_prog(struct igc_adapter *adapter,2489			      struct bpf_prog *prog,2490			      struct xdp_buff *xdp)2491{2492	u32 act = bpf_prog_run_xdp(prog, xdp);2493 2494	switch (act) {2495	case XDP_PASS:2496		return IGC_XDP_PASS;2497	case XDP_TX:2498		if (igc_xdp_xmit_back(adapter, xdp) < 0)2499			goto out_failure;2500		return IGC_XDP_TX;2501	case XDP_REDIRECT:2502		if (xdp_do_redirect(adapter->netdev, xdp, prog) < 0)2503			goto out_failure;2504		return IGC_XDP_REDIRECT;2505		break;2506	default:2507		bpf_warn_invalid_xdp_action(adapter->netdev, prog, act);2508		fallthrough;2509	case XDP_ABORTED:2510out_failure:2511		trace_xdp_exception(adapter->netdev, prog, act);2512		fallthrough;2513	case XDP_DROP:2514		return IGC_XDP_CONSUMED;2515	}2516}2517 2518static struct sk_buff *igc_xdp_run_prog(struct igc_adapter *adapter,2519					struct xdp_buff *xdp)2520{2521	struct bpf_prog *prog;2522	int res;2523 2524	prog = READ_ONCE(adapter->xdp_prog);2525	if (!prog) {2526		res = IGC_XDP_PASS;2527		goto out;2528	}2529 2530	res = __igc_xdp_run_prog(adapter, prog, xdp);2531 2532out:2533	return ERR_PTR(-res);2534}2535 2536/* This function assumes __netif_tx_lock is held by the caller. */2537static void igc_flush_tx_descriptors(struct igc_ring *ring)2538{2539	/* Once tail pointer is updated, hardware can fetch the descriptors2540	 * any time so we issue a write membar here to ensure all memory2541	 * writes are complete before the tail pointer is updated.2542	 */2543	wmb();2544	writel(ring->next_to_use, ring->tail);2545}2546 2547static void igc_finalize_xdp(struct igc_adapter *adapter, int status)2548{2549	int cpu = smp_processor_id();2550	struct netdev_queue *nq;2551	struct igc_ring *ring;2552 2553	if (status & IGC_XDP_TX) {2554		ring = igc_xdp_get_tx_ring(adapter, cpu);2555		nq = txring_txq(ring);2556 2557		__netif_tx_lock(nq, cpu);2558		igc_flush_tx_descriptors(ring);2559		__netif_tx_unlock(nq);2560	}2561 2562	if (status & IGC_XDP_REDIRECT)2563		xdp_do_flush();2564}2565 2566static void igc_update_rx_stats(struct igc_q_vector *q_vector,2567				unsigned int packets, unsigned int bytes)2568{2569	struct igc_ring *ring = q_vector->rx.ring;2570 2571	u64_stats_update_begin(&ring->rx_syncp);2572	ring->rx_stats.packets += packets;2573	ring->rx_stats.bytes += bytes;2574	u64_stats_update_end(&ring->rx_syncp);2575 2576	q_vector->rx.total_packets += packets;2577	q_vector->rx.total_bytes += bytes;2578}2579 2580static int igc_clean_rx_irq(struct igc_q_vector *q_vector, const int budget)2581{2582	unsigned int total_bytes = 0, total_packets = 0;2583	struct igc_adapter *adapter = q_vector->adapter;2584	struct igc_ring *rx_ring = q_vector->rx.ring;2585	struct sk_buff *skb = rx_ring->skb;2586	u16 cleaned_count = igc_desc_unused(rx_ring);2587	int xdp_status = 0, rx_buffer_pgcnt;2588 2589	while (likely(total_packets < budget)) {2590		struct igc_xdp_buff ctx = { .rx_ts = NULL };2591		struct igc_rx_buffer *rx_buffer;2592		union igc_adv_rx_desc *rx_desc;2593		unsigned int size, truesize;2594		int pkt_offset = 0;2595		void *pktbuf;2596 2597		/* return some buffers to hardware, one at a time is too slow */2598		if (cleaned_count >= IGC_RX_BUFFER_WRITE) {2599			igc_alloc_rx_buffers(rx_ring, cleaned_count);2600			cleaned_count = 0;2601		}2602 2603		rx_desc = IGC_RX_DESC(rx_ring, rx_ring->next_to_clean);2604		size = le16_to_cpu(rx_desc->wb.upper.length);2605		if (!size)2606			break;2607 2608		/* This memory barrier is needed to keep us from reading2609		 * any other fields out of the rx_desc until we know the2610		 * descriptor has been written back2611		 */2612		dma_rmb();2613 2614		rx_buffer = igc_get_rx_buffer(rx_ring, size, &rx_buffer_pgcnt);2615		truesize = igc_get_rx_frame_truesize(rx_ring, size);2616 2617		pktbuf = page_address(rx_buffer->page) + rx_buffer->page_offset;2618 2619		if (igc_test_staterr(rx_desc, IGC_RXDADV_STAT_TSIP)) {2620			ctx.rx_ts = pktbuf;2621			pkt_offset = IGC_TS_HDR_LEN;2622			size -= IGC_TS_HDR_LEN;2623		}2624 2625		if (!skb) {2626			xdp_init_buff(&ctx.xdp, truesize, &rx_ring->xdp_rxq);2627			xdp_prepare_buff(&ctx.xdp, pktbuf - igc_rx_offset(rx_ring),2628					 igc_rx_offset(rx_ring) + pkt_offset,2629					 size, true);2630			xdp_buff_clear_frags_flag(&ctx.xdp);2631			ctx.rx_desc = rx_desc;2632 2633			skb = igc_xdp_run_prog(adapter, &ctx.xdp);2634		}2635 2636		if (IS_ERR(skb)) {2637			unsigned int xdp_res = -PTR_ERR(skb);2638 2639			switch (xdp_res) {2640			case IGC_XDP_CONSUMED:2641				rx_buffer->pagecnt_bias++;2642				break;2643			case IGC_XDP_TX:2644			case IGC_XDP_REDIRECT:2645				igc_rx_buffer_flip(rx_buffer, truesize);2646				xdp_status |= xdp_res;2647				break;2648			}2649 2650			total_packets++;2651			total_bytes += size;2652		} else if (skb)2653			igc_add_rx_frag(rx_ring, rx_buffer, skb, size);2654		else if (ring_uses_build_skb(rx_ring))2655			skb = igc_build_skb(rx_ring, rx_buffer, &ctx.xdp);2656		else2657			skb = igc_construct_skb(rx_ring, rx_buffer, &ctx);2658 2659		/* exit if we failed to retrieve a buffer */2660		if (!skb) {2661			rx_ring->rx_stats.alloc_failed++;2662			rx_buffer->pagecnt_bias++;2663			set_bit(IGC_RING_FLAG_RX_ALLOC_FAILED, &rx_ring->flags);2664			break;2665		}2666 2667		igc_put_rx_buffer(rx_ring, rx_buffer, rx_buffer_pgcnt);2668		cleaned_count++;2669 2670		/* fetch next buffer in frame if non-eop */2671		if (igc_is_non_eop(rx_ring, rx_desc))2672			continue;2673 2674		/* verify the packet layout is correct */2675		if (igc_cleanup_headers(rx_ring, rx_desc, skb)) {2676			skb = NULL;2677			continue;2678		}2679 2680		/* probably a little skewed due to removing CRC */2681		total_bytes += skb->len;2682 2683		/* populate checksum, VLAN, and protocol */2684		igc_process_skb_fields(rx_ring, rx_desc, skb);2685 2686		napi_gro_receive(&q_vector->napi, skb);2687 2688		/* reset skb pointer */2689		skb = NULL;2690 2691		/* update budget accounting */2692		total_packets++;2693	}2694 2695	if (xdp_status)2696		igc_finalize_xdp(adapter, xdp_status);2697 2698	/* place incomplete frames back on ring for completion */2699	rx_ring->skb = skb;2700 2701	igc_update_rx_stats(q_vector, total_packets, total_bytes);2702 2703	if (cleaned_count)2704		igc_alloc_rx_buffers(rx_ring, cleaned_count);2705 2706	return total_packets;2707}2708 2709static struct sk_buff *igc_construct_skb_zc(struct igc_ring *ring,2710					    struct xdp_buff *xdp)2711{2712	unsigned int totalsize = xdp->data_end - xdp->data_meta;2713	unsigned int metasize = xdp->data - xdp->data_meta;2714	struct sk_buff *skb;2715 2716	net_prefetch(xdp->data_meta);2717 2718	skb = napi_alloc_skb(&ring->q_vector->napi, totalsize);2719	if (unlikely(!skb))2720		return NULL;2721 2722	memcpy(__skb_put(skb, totalsize), xdp->data_meta,2723	       ALIGN(totalsize, sizeof(long)));2724 2725	if (metasize) {2726		skb_metadata_set(skb, metasize);2727		__skb_pull(skb, metasize);2728	}2729 2730	return skb;2731}2732 2733static void igc_dispatch_skb_zc(struct igc_q_vector *q_vector,2734				union igc_adv_rx_desc *desc,2735				struct xdp_buff *xdp,2736				ktime_t timestamp)2737{2738	struct igc_ring *ring = q_vector->rx.ring;2739	struct sk_buff *skb;2740 2741	skb = igc_construct_skb_zc(ring, xdp);2742	if (!skb) {2743		ring->rx_stats.alloc_failed++;2744		set_bit(IGC_RING_FLAG_RX_ALLOC_FAILED, &ring->flags);2745		return;2746	}2747 2748	if (timestamp)2749		skb_hwtstamps(skb)->hwtstamp = timestamp;2750 2751	if (igc_cleanup_headers(ring, desc, skb))2752		return;2753 2754	igc_process_skb_fields(ring, desc, skb);2755	napi_gro_receive(&q_vector->napi, skb);2756}2757 2758static struct igc_xdp_buff *xsk_buff_to_igc_ctx(struct xdp_buff *xdp)2759{2760	/* xdp_buff pointer used by ZC code path is alloc as xdp_buff_xsk. The2761	 * igc_xdp_buff shares its layout with xdp_buff_xsk and private2762	 * igc_xdp_buff fields fall into xdp_buff_xsk->cb2763	 */2764       return (struct igc_xdp_buff *)xdp;2765}2766 2767static int igc_clean_rx_irq_zc(struct igc_q_vector *q_vector, const int budget)2768{2769	struct igc_adapter *adapter = q_vector->adapter;2770	struct igc_ring *ring = q_vector->rx.ring;2771	u16 cleaned_count = igc_desc_unused(ring);2772	int total_bytes = 0, total_packets = 0;2773	u16 ntc = ring->next_to_clean;2774	struct bpf_prog *prog;2775	bool failure = false;2776	int xdp_status = 0;2777 2778	rcu_read_lock();2779 2780	prog = READ_ONCE(adapter->xdp_prog);2781 2782	while (likely(total_packets < budget)) {2783		union igc_adv_rx_desc *desc;2784		struct igc_rx_buffer *bi;2785		struct igc_xdp_buff *ctx;2786		ktime_t timestamp = 0;2787		unsigned int size;2788		int res;2789 2790		desc = IGC_RX_DESC(ring, ntc);2791		size = le16_to_cpu(desc->wb.upper.length);2792		if (!size)2793			break;2794 2795		/* This memory barrier is needed to keep us from reading2796		 * any other fields out of the rx_desc until we know the2797		 * descriptor has been written back2798		 */2799		dma_rmb();2800 2801		bi = &ring->rx_buffer_info[ntc];2802 2803		ctx = xsk_buff_to_igc_ctx(bi->xdp);2804		ctx->rx_desc = desc;2805 2806		if (igc_test_staterr(desc, IGC_RXDADV_STAT_TSIP)) {2807			ctx->rx_ts = bi->xdp->data;2808 2809			bi->xdp->data += IGC_TS_HDR_LEN;2810 2811			/* HW timestamp has been copied into local variable. Metadata2812			 * length when XDP program is called should be 0.2813			 */2814			bi->xdp->data_meta += IGC_TS_HDR_LEN;2815			size -= IGC_TS_HDR_LEN;2816		}2817 2818		bi->xdp->data_end = bi->xdp->data + size;2819		xsk_buff_dma_sync_for_cpu(bi->xdp);2820 2821		res = __igc_xdp_run_prog(adapter, prog, bi->xdp);2822		switch (res) {2823		case IGC_XDP_PASS:2824			igc_dispatch_skb_zc(q_vector, desc, bi->xdp, timestamp);2825			fallthrough;2826		case IGC_XDP_CONSUMED:2827			xsk_buff_free(bi->xdp);2828			break;2829		case IGC_XDP_TX:2830		case IGC_XDP_REDIRECT:2831			xdp_status |= res;2832			break;2833		}2834 2835		bi->xdp = NULL;2836		total_bytes += size;2837		total_packets++;2838		cleaned_count++;2839		ntc++;2840		if (ntc == ring->count)2841			ntc = 0;2842	}2843 2844	ring->next_to_clean = ntc;2845	rcu_read_unlock();2846 2847	if (cleaned_count >= IGC_RX_BUFFER_WRITE)2848		failure = !igc_alloc_rx_buffers_zc(ring, cleaned_count);2849 2850	if (xdp_status)2851		igc_finalize_xdp(adapter, xdp_status);2852 2853	igc_update_rx_stats(q_vector, total_packets, total_bytes);2854 2855	if (xsk_uses_need_wakeup(ring->xsk_pool)) {2856		if (failure || ring->next_to_clean == ring->next_to_use)2857			xsk_set_rx_need_wakeup(ring->xsk_pool);2858		else2859			xsk_clear_rx_need_wakeup(ring->xsk_pool);2860		return total_packets;2861	}2862 2863	return failure ? budget : total_packets;2864}2865 2866static void igc_update_tx_stats(struct igc_q_vector *q_vector,2867				unsigned int packets, unsigned int bytes)2868{2869	struct igc_ring *ring = q_vector->tx.ring;2870 2871	u64_stats_update_begin(&ring->tx_syncp);2872	ring->tx_stats.bytes += bytes;2873	ring->tx_stats.packets += packets;2874	u64_stats_update_end(&ring->tx_syncp);2875 2876	q_vector->tx.total_bytes += bytes;2877	q_vector->tx.total_packets += packets;2878}2879 2880static void igc_xsk_request_timestamp(void *_priv)2881{2882	struct igc_metadata_request *meta_req = _priv;2883	struct igc_ring *tx_ring = meta_req->tx_ring;2884	struct igc_tx_timestamp_request *tstamp;2885	u32 tx_flags = IGC_TX_FLAGS_TSTAMP;2886	struct igc_adapter *adapter;2887	unsigned long lock_flags;2888	bool found = false;2889	int i;2890 2891	if (test_bit(IGC_RING_FLAG_TX_HWTSTAMP, &tx_ring->flags)) {2892		adapter = netdev_priv(tx_ring->netdev);2893 2894		spin_lock_irqsave(&adapter->ptp_tx_lock, lock_flags);2895 2896		/* Search for available tstamp regs */2897		for (i = 0; i < IGC_MAX_TX_TSTAMP_REGS; i++) {2898			tstamp = &adapter->tx_tstamp[i];2899 2900			/* tstamp->skb and tstamp->xsk_tx_buffer are in union.2901			 * When tstamp->skb is equal to NULL,2902			 * tstamp->xsk_tx_buffer is equal to NULL as well.2903			 * This condition means that the particular tstamp reg2904			 * is not occupied by other packet.2905			 */2906			if (!tstamp->skb) {2907				found = true;2908				break;2909			}2910		}2911 2912		/* Return if no available tstamp regs */2913		if (!found) {2914			adapter->tx_hwtstamp_skipped++;2915			spin_unlock_irqrestore(&adapter->ptp_tx_lock,2916					       lock_flags);2917			return;2918		}2919 2920		tstamp->start = jiffies;2921		tstamp->xsk_queue_index = tx_ring->queue_index;2922		tstamp->xsk_tx_buffer = meta_req->tx_buffer;2923		tstamp->buffer_type = IGC_TX_BUFFER_TYPE_XSK;2924 2925		/* Hold the transmit completion until timestamp is ready */2926		meta_req->tx_buffer->xsk_pending_ts = true;2927 2928		/* Keep the pointer to tx_timestamp, which is located in XDP2929		 * metadata area. It is the location to store the value of2930		 * tx hardware timestamp.2931		 */2932		xsk_tx_metadata_to_compl(meta_req->meta, &tstamp->xsk_meta);2933 2934		/* Set timestamp bit based on the _TSTAMP(_X) bit. */2935		tx_flags |= tstamp->flags;2936		meta_req->cmd_type |= IGC_SET_FLAG(tx_flags,2937						   IGC_TX_FLAGS_TSTAMP,2938						   (IGC_ADVTXD_MAC_TSTAMP));2939		meta_req->cmd_type |= IGC_SET_FLAG(tx_flags,2940						   IGC_TX_FLAGS_TSTAMP_1,2941						   (IGC_ADVTXD_TSTAMP_REG_1));2942		meta_req->cmd_type |= IGC_SET_FLAG(tx_flags,2943						   IGC_TX_FLAGS_TSTAMP_2,2944						   (IGC_ADVTXD_TSTAMP_REG_2));2945		meta_req->cmd_type |= IGC_SET_FLAG(tx_flags,2946						   IGC_TX_FLAGS_TSTAMP_3,2947						   (IGC_ADVTXD_TSTAMP_REG_3));2948 2949		spin_unlock_irqrestore(&adapter->ptp_tx_lock, lock_flags);2950	}2951}2952 2953static u64 igc_xsk_fill_timestamp(void *_priv)2954{2955	return *(u64 *)_priv;2956}2957 2958const struct xsk_tx_metadata_ops igc_xsk_tx_metadata_ops = {2959	.tmo_request_timestamp		= igc_xsk_request_timestamp,2960	.tmo_fill_timestamp		= igc_xsk_fill_timestamp,2961};2962 2963static void igc_xdp_xmit_zc(struct igc_ring *ring)2964{2965	struct xsk_buff_pool *pool = ring->xsk_pool;2966	struct netdev_queue *nq = txring_txq(ring);2967	union igc_adv_tx_desc *tx_desc = NULL;2968	int cpu = smp_processor_id();2969	struct xdp_desc xdp_desc;2970	u16 budget, ntu;2971 2972	if (!netif_carrier_ok(ring->netdev))2973		return;2974 2975	__netif_tx_lock(nq, cpu);2976 2977	/* Avoid transmit queue timeout since we share it with the slow path */2978	txq_trans_cond_update(nq);2979 2980	ntu = ring->next_to_use;2981	budget = igc_desc_unused(ring);2982 2983	while (xsk_tx_peek_desc(pool, &xdp_desc) && budget--) {2984		struct igc_metadata_request meta_req;2985		struct xsk_tx_metadata *meta = NULL;2986		struct igc_tx_buffer *bi;2987		u32 olinfo_status;2988		dma_addr_t dma;2989 2990		meta_req.cmd_type = IGC_ADVTXD_DTYP_DATA |2991				    IGC_ADVTXD_DCMD_DEXT |2992				    IGC_ADVTXD_DCMD_IFCS |2993				    IGC_TXD_DCMD | xdp_desc.len;2994		olinfo_status = xdp_desc.len << IGC_ADVTXD_PAYLEN_SHIFT;2995 2996		dma = xsk_buff_raw_get_dma(pool, xdp_desc.addr);2997		meta = xsk_buff_get_metadata(pool, xdp_desc.addr);2998		xsk_buff_raw_dma_sync_for_device(pool, dma, xdp_desc.len);2999		bi = &ring->tx_buffer_info[ntu];3000 3001		meta_req.tx_ring = ring;3002		meta_req.tx_buffer = bi;3003		meta_req.meta = meta;3004		xsk_tx_metadata_request(meta, &igc_xsk_tx_metadata_ops,3005					&meta_req);3006 3007		tx_desc = IGC_TX_DESC(ring, ntu);3008		tx_desc->read.cmd_type_len = cpu_to_le32(meta_req.cmd_type);3009		tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);3010		tx_desc->read.buffer_addr = cpu_to_le64(dma);3011 3012		bi->type = IGC_TX_BUFFER_TYPE_XSK;3013		bi->protocol = 0;3014		bi->bytecount = xdp_desc.len;3015		bi->gso_segs = 1;3016		bi->time_stamp = jiffies;3017		bi->next_to_watch = tx_desc;3018 3019		netdev_tx_sent_queue(txring_txq(ring), xdp_desc.len);3020 3021		ntu++;3022		if (ntu == ring->count)3023			ntu = 0;3024	}3025 3026	ring->next_to_use = ntu;3027	if (tx_desc) {3028		igc_flush_tx_descriptors(ring);3029		xsk_tx_release(pool);3030	}3031 3032	__netif_tx_unlock(nq);3033}3034 3035/**3036 * igc_clean_tx_irq - Reclaim resources after transmit completes3037 * @q_vector: pointer to q_vector containing needed info3038 * @napi_budget: Used to determine if we are in netpoll3039 *3040 * returns true if ring is completely cleaned3041 */3042static bool igc_clean_tx_irq(struct igc_q_vector *q_vector, int napi_budget)3043{3044	struct igc_adapter *adapter = q_vector->adapter;3045	unsigned int total_bytes = 0, total_packets = 0;3046	unsigned int budget = q_vector->tx.work_limit;3047	struct igc_ring *tx_ring = q_vector->tx.ring;3048	unsigned int i = tx_ring->next_to_clean;3049	struct igc_tx_buffer *tx_buffer;3050	union igc_adv_tx_desc *tx_desc;3051	u32 xsk_frames = 0;3052 3053	if (test_bit(__IGC_DOWN, &adapter->state))3054		return true;3055 3056	tx_buffer = &tx_ring->tx_buffer_info[i];3057	tx_desc = IGC_TX_DESC(tx_ring, i);3058	i -= tx_ring->count;3059 3060	do {3061		union igc_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;3062 3063		/* if next_to_watch is not set then there is no work pending */3064		if (!eop_desc)3065			break;3066 3067		/* prevent any other reads prior to eop_desc */3068		smp_rmb();3069 3070		/* if DD is not set pending work has not been completed */3071		if (!(eop_desc->wb.status & cpu_to_le32(IGC_TXD_STAT_DD)))3072			break;3073 3074		/* Hold the completions while there's a pending tx hardware3075		 * timestamp request from XDP Tx metadata.3076		 */3077		if (tx_buffer->type == IGC_TX_BUFFER_TYPE_XSK &&3078		    tx_buffer->xsk_pending_ts)3079			break;3080 3081		/* clear next_to_watch to prevent false hangs */3082		tx_buffer->next_to_watch = NULL;3083 3084		/* update the statistics for this packet */3085		total_bytes += tx_buffer->bytecount;3086		total_packets += tx_buffer->gso_segs;3087 3088		switch (tx_buffer->type) {3089		case IGC_TX_BUFFER_TYPE_XSK:3090			xsk_frames++;3091			break;3092		case IGC_TX_BUFFER_TYPE_XDP:3093			xdp_return_frame(tx_buffer->xdpf);3094			igc_unmap_tx_buffer(tx_ring->dev, tx_buffer);3095			break;3096		case IGC_TX_BUFFER_TYPE_SKB:3097			napi_consume_skb(tx_buffer->skb, napi_budget);3098			igc_unmap_tx_buffer(tx_ring->dev, tx_buffer);3099			break;3100		default:3101			netdev_warn_once(tx_ring->netdev, "Unknown Tx buffer type\n");3102			break;3103		}3104 3105		/* clear last DMA location and unmap remaining buffers */3106		while (tx_desc != eop_desc) {3107			tx_buffer++;3108			tx_desc++;3109			i++;3110			if (unlikely(!i)) {3111				i -= tx_ring->count;3112				tx_buffer = tx_ring->tx_buffer_info;3113				tx_desc = IGC_TX_DESC(tx_ring, 0);3114			}3115 3116			/* unmap any remaining paged data */3117			if (dma_unmap_len(tx_buffer, len))3118				igc_unmap_tx_buffer(tx_ring->dev, tx_buffer);3119		}3120 3121		/* move us one more past the eop_desc for start of next pkt */3122		tx_buffer++;3123		tx_desc++;3124		i++;3125		if (unlikely(!i)) {3126			i -= tx_ring->count;3127			tx_buffer = tx_ring->tx_buffer_info;3128			tx_desc = IGC_TX_DESC(tx_ring, 0);3129		}3130 3131		/* issue prefetch for next Tx descriptor */3132		prefetch(tx_desc);3133 3134		/* update budget accounting */3135		budget--;3136	} while (likely(budget));3137 3138	netdev_tx_completed_queue(txring_txq(tx_ring),3139				  total_packets, total_bytes);3140 3141	i += tx_ring->count;3142	tx_ring->next_to_clean = i;3143 3144	igc_update_tx_stats(q_vector, total_packets, total_bytes);3145 3146	if (tx_ring->xsk_pool) {3147		if (xsk_frames)3148			xsk_tx_completed(tx_ring->xsk_pool, xsk_frames);3149		if (xsk_uses_need_wakeup(tx_ring->xsk_pool))3150			xsk_set_tx_need_wakeup(tx_ring->xsk_pool);3151		igc_xdp_xmit_zc(tx_ring);3152	}3153 3154	if (test_bit(IGC_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) {3155		struct igc_hw *hw = &adapter->hw;3156 3157		/* Detect a transmit hang in hardware, this serializes the3158		 * check with the clearing of time_stamp and movement of i3159		 */3160		clear_bit(IGC_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);3161		if (tx_buffer->next_to_watch &&3162		    time_after(jiffies, tx_buffer->time_stamp +3163		    (adapter->tx_timeout_factor * HZ)) &&3164		    !(rd32(IGC_STATUS) & IGC_STATUS_TXOFF) &&3165		    (rd32(IGC_TDH(tx_ring->reg_idx)) != readl(tx_ring->tail)) &&3166		    !tx_ring->oper_gate_closed) {3167			/* detected Tx unit hang */3168			netdev_err(tx_ring->netdev,3169				   "Detected Tx Unit Hang\n"3170				   "  Tx Queue             <%d>\n"3171				   "  TDH                  <%x>\n"3172				   "  TDT                  <%x>\n"3173				   "  next_to_use          <%x>\n"3174				   "  next_to_clean        <%x>\n"3175				   "buffer_info[next_to_clean]\n"3176				   "  time_stamp           <%lx>\n"3177				   "  next_to_watch        <%p>\n"3178				   "  jiffies              <%lx>\n"3179				   "  desc.status          <%x>\n",3180				   tx_ring->queue_index,3181				   rd32(IGC_TDH(tx_ring->reg_idx)),3182				   readl(tx_ring->tail),3183				   tx_ring->next_to_use,3184				   tx_ring->next_to_clean,3185				   tx_buffer->time_stamp,3186				   tx_buffer->next_to_watch,3187				   jiffies,3188				   tx_buffer->next_to_watch->wb.status);3189			netif_stop_subqueue(tx_ring->netdev,3190					    tx_ring->queue_index);3191 3192			/* we are about to reset, no point in enabling stuff */3193			return true;3194		}3195	}3196 3197#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)3198	if (unlikely(total_packets &&3199		     netif_carrier_ok(tx_ring->netdev) &&3200		     igc_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) {3201		/* Make sure that anybody stopping the queue after this3202		 * sees the new next_to_clean.3203		 */3204		smp_mb();3205		if (__netif_subqueue_stopped(tx_ring->netdev,3206					     tx_ring->queue_index) &&3207		    !(test_bit(__IGC_DOWN, &adapter->state))) {3208			netif_wake_subqueue(tx_ring->netdev,3209					    tx_ring->queue_index);3210 3211			u64_stats_update_begin(&tx_ring->tx_syncp);3212			tx_ring->tx_stats.restart_queue++;3213			u64_stats_update_end(&tx_ring->tx_syncp);3214		}3215	}3216 3217	return !!budget;3218}3219 3220static int igc_find_mac_filter(struct igc_adapter *adapter,3221			       enum igc_mac_filter_type type, const u8 *addr)3222{3223	struct igc_hw *hw = &adapter->hw;3224	int max_entries = hw->mac.rar_entry_count;3225	u32 ral, rah;3226	int i;3227 3228	for (i = 0; i < max_entries; i++) {3229		ral = rd32(IGC_RAL(i));3230		rah = rd32(IGC_RAH(i));3231 3232		if (!(rah & IGC_RAH_AV))3233			continue;3234		if (!!(rah & IGC_RAH_ASEL_SRC_ADDR) != type)3235			continue;3236		if ((rah & IGC_RAH_RAH_MASK) !=3237		    le16_to_cpup((__le16 *)(addr + 4)))3238			continue;3239		if (ral != le32_to_cpup((__le32 *)(addr)))3240			continue;3241 3242		return i;3243	}3244 3245	return -1;3246}3247 3248static int igc_get_avail_mac_filter_slot(struct igc_adapter *adapter)3249{3250	struct igc_hw *hw = &adapter->hw;3251	int max_entries = hw->mac.rar_entry_count;3252	u32 rah;3253	int i;3254 3255	for (i = 0; i < max_entries; i++) {3256		rah = rd32(IGC_RAH(i));3257 3258		if (!(rah & IGC_RAH_AV))3259			return i;3260	}3261 3262	return -1;3263}3264 3265/**3266 * igc_add_mac_filter() - Add MAC address filter3267 * @adapter: Pointer to adapter where the filter should be added3268 * @type: MAC address filter type (source or destination)3269 * @addr: MAC address3270 * @queue: If non-negative, queue assignment feature is enabled and frames3271 *         matching the filter are enqueued onto 'queue'. Otherwise, queue3272 *         assignment is disabled.3273 *3274 * Return: 0 in case of success, negative errno code otherwise.3275 */3276static int igc_add_mac_filter(struct igc_adapter *adapter,3277			      enum igc_mac_filter_type type, const u8 *addr,3278			      int queue)3279{3280	struct net_device *dev = adapter->netdev;3281	int index;3282 3283	index = igc_find_mac_filter(adapter, type, addr);3284	if (index >= 0)3285		goto update_filter;3286 3287	index = igc_get_avail_mac_filter_slot(adapter);3288	if (index < 0)3289		return -ENOSPC;3290 3291	netdev_dbg(dev, "Add MAC address filter: index %d type %s address %pM queue %d\n",3292		   index, type == IGC_MAC_FILTER_TYPE_DST ? "dst" : "src",3293		   addr, queue);3294 3295update_filter:3296	igc_set_mac_filter_hw(adapter, index, type, addr, queue);3297	return 0;3298}3299 3300/**3301 * igc_del_mac_filter() - Delete MAC address filter3302 * @adapter: Pointer to adapter where the filter should be deleted from3303 * @type: MAC address filter type (source or destination)3304 * @addr: MAC address3305 */3306static void igc_del_mac_filter(struct igc_adapter *adapter,3307			       enum igc_mac_filter_type type, const u8 *addr)3308{3309	struct net_device *dev = adapter->netdev;3310	int index;3311 3312	index = igc_find_mac_filter(adapter, type, addr);3313	if (index < 0)3314		return;3315 3316	if (index == 0) {3317		/* If this is the default filter, we don't actually delete it.3318		 * We just reset to its default value i.e. disable queue3319		 * assignment.3320		 */3321		netdev_dbg(dev, "Disable default MAC filter queue assignment");3322 3323		igc_set_mac_filter_hw(adapter, 0, type, addr, -1);3324	} else {3325		netdev_dbg(dev, "Delete MAC address filter: index %d type %s address %pM\n",3326			   index,3327			   type == IGC_MAC_FILTER_TYPE_DST ? "dst" : "src",3328			   addr);3329 3330		igc_clear_mac_filter_hw(adapter, index);3331	}3332}3333 3334/**3335 * igc_add_vlan_prio_filter() - Add VLAN priority filter3336 * @adapter: Pointer to adapter where the filter should be added3337 * @prio: VLAN priority value3338 * @queue: Queue number which matching frames are assigned to3339 *3340 * Return: 0 in case of success, negative errno code otherwise.3341 */3342static int igc_add_vlan_prio_filter(struct igc_adapter *adapter, int prio,3343				    int queue)3344{3345	struct net_device *dev = adapter->netdev;3346	struct igc_hw *hw = &adapter->hw;3347	u32 vlanpqf;3348 3349	vlanpqf = rd32(IGC_VLANPQF);3350 3351	if (vlanpqf & IGC_VLANPQF_VALID(prio)) {3352		netdev_dbg(dev, "VLAN priority filter already in use\n");3353		return -EEXIST;3354	}3355 3356	vlanpqf |= IGC_VLANPQF_QSEL(prio, queue);3357	vlanpqf |= IGC_VLANPQF_VALID(prio);3358 3359	wr32(IGC_VLANPQF, vlanpqf);3360 3361	netdev_dbg(dev, "Add VLAN priority filter: prio %d queue %d\n",3362		   prio, queue);3363	return 0;3364}3365 3366/**3367 * igc_del_vlan_prio_filter() - Delete VLAN priority filter3368 * @adapter: Pointer to adapter where the filter should be deleted from3369 * @prio: VLAN priority value3370 */3371static void igc_del_vlan_prio_filter(struct igc_adapter *adapter, int prio)3372{3373	struct igc_hw *hw = &adapter->hw;3374	u32 vlanpqf;3375 3376	vlanpqf = rd32(IGC_VLANPQF);3377 3378	vlanpqf &= ~IGC_VLANPQF_VALID(prio);3379	vlanpqf &= ~IGC_VLANPQF_QSEL(prio, IGC_VLANPQF_QUEUE_MASK);3380 3381	wr32(IGC_VLANPQF, vlanpqf);3382 3383	netdev_dbg(adapter->netdev, "Delete VLAN priority filter: prio %d\n",3384		   prio);3385}3386 3387static int igc_get_avail_etype_filter_slot(struct igc_adapter *adapter)3388{3389	struct igc_hw *hw = &adapter->hw;3390	int i;3391 3392	for (i = 0; i < MAX_ETYPE_FILTER; i++) {3393		u32 etqf = rd32(IGC_ETQF(i));3394 3395		if (!(etqf & IGC_ETQF_FILTER_ENABLE))3396			return i;3397	}3398 3399	return -1;3400}3401 3402/**3403 * igc_add_etype_filter() - Add ethertype filter3404 * @adapter: Pointer to adapter where the filter should be added3405 * @etype: Ethertype value3406 * @queue: If non-negative, queue assignment feature is enabled and frames3407 *         matching the filter are enqueued onto 'queue'. Otherwise, queue3408 *         assignment is disabled.3409 *3410 * Return: 0 in case of success, negative errno code otherwise.3411 */3412static int igc_add_etype_filter(struct igc_adapter *adapter, u16 etype,3413				int queue)3414{3415	struct igc_hw *hw = &adapter->hw;3416	int index;3417	u32 etqf;3418 3419	index = igc_get_avail_etype_filter_slot(adapter);3420	if (index < 0)3421		return -ENOSPC;3422 3423	etqf = rd32(IGC_ETQF(index));3424 3425	etqf &= ~IGC_ETQF_ETYPE_MASK;3426	etqf |= etype;3427 3428	if (queue >= 0) {3429		etqf &= ~IGC_ETQF_QUEUE_MASK;3430		etqf |= (queue << IGC_ETQF_QUEUE_SHIFT);3431		etqf |= IGC_ETQF_QUEUE_ENABLE;3432	}3433 3434	etqf |= IGC_ETQF_FILTER_ENABLE;3435 3436	wr32(IGC_ETQF(index), etqf);3437 3438	netdev_dbg(adapter->netdev, "Add ethertype filter: etype %04x queue %d\n",3439		   etype, queue);3440	return 0;3441}3442 3443static int igc_find_etype_filter(struct igc_adapter *adapter, u16 etype)3444{3445	struct igc_hw *hw = &adapter->hw;3446	int i;3447 3448	for (i = 0; i < MAX_ETYPE_FILTER; i++) {3449		u32 etqf = rd32(IGC_ETQF(i));3450 3451		if ((etqf & IGC_ETQF_ETYPE_MASK) == etype)3452			return i;3453	}3454 3455	return -1;3456}3457 3458/**3459 * igc_del_etype_filter() - Delete ethertype filter3460 * @adapter: Pointer to adapter where the filter should be deleted from3461 * @etype: Ethertype value3462 */3463static void igc_del_etype_filter(struct igc_adapter *adapter, u16 etype)3464{3465	struct igc_hw *hw = &adapter->hw;3466	int index;3467 3468	index = igc_find_etype_filter(adapter, etype);3469	if (index < 0)3470		return;3471 3472	wr32(IGC_ETQF(index), 0);3473 3474	netdev_dbg(adapter->netdev, "Delete ethertype filter: etype %04x\n",3475		   etype);3476}3477 3478static int igc_flex_filter_select(struct igc_adapter *adapter,3479				  struct igc_flex_filter *input,3480				  u32 *fhft)3481{3482	struct igc_hw *hw = &adapter->hw;3483	u8 fhft_index;3484	u32 fhftsl;3485 3486	if (input->index >= MAX_FLEX_FILTER) {3487		netdev_err(adapter->netdev, "Wrong Flex Filter index selected!\n");3488		return -EINVAL;3489	}3490 3491	/* Indirect table select register */3492	fhftsl = rd32(IGC_FHFTSL);3493	fhftsl &= ~IGC_FHFTSL_FTSL_MASK;3494	switch (input->index) {3495	case 0 ... 7:3496		fhftsl |= 0x00;3497		break;3498	case 8 ... 15:3499		fhftsl |= 0x01;3500		break;3501	case 16 ... 23:3502		fhftsl |= 0x02;3503		break;3504	case 24 ... 31:3505		fhftsl |= 0x03;3506		break;3507	}3508	wr32(IGC_FHFTSL, fhftsl);3509 3510	/* Normalize index down to host table register */3511	fhft_index = input->index % 8;3512 3513	*fhft = (fhft_index < 4) ? IGC_FHFT(fhft_index) :3514		IGC_FHFT_EXT(fhft_index - 4);3515 3516	return 0;3517}3518 3519static int igc_write_flex_filter_ll(struct igc_adapter *adapter,3520				    struct igc_flex_filter *input)3521{3522	struct igc_hw *hw = &adapter->hw;3523	u8 *data = input->data;3524	u8 *mask = input->mask;3525	u32 queuing;3526	u32 fhft;3527	u32 wufc;3528	int ret;3529	int i;3530 3531	/* Length has to be aligned to 8. Otherwise the filter will fail. Bail3532	 * out early to avoid surprises later.3533	 */3534	if (input->length % 8 != 0) {3535		netdev_err(adapter->netdev, "The length of a flex filter has to be 8 byte aligned!\n");3536		return -EINVAL;3537	}3538 3539	/* Select corresponding flex filter register and get base for host table. */3540	ret = igc_flex_filter_select(adapter, input, &fhft);3541	if (ret)3542		return ret;3543 3544	/* When adding a filter globally disable flex filter feature. That is3545	 * recommended within the datasheet.3546	 */3547	wufc = rd32(IGC_WUFC);3548	wufc &= ~IGC_WUFC_FLEX_HQ;3549	wr32(IGC_WUFC, wufc);3550 3551	/* Configure filter */3552	queuing = input->length & IGC_FHFT_LENGTH_MASK;3553	queuing |= FIELD_PREP(IGC_FHFT_QUEUE_MASK, input->rx_queue);3554	queuing |= FIELD_PREP(IGC_FHFT_PRIO_MASK, input->prio);3555 3556	if (input->immediate_irq)3557		queuing |= IGC_FHFT_IMM_INT;3558 3559	if (input->drop)3560		queuing |= IGC_FHFT_DROP;3561 3562	wr32(fhft + 0xFC, queuing);3563 3564	/* Write data (128 byte) and mask (128 bit) */3565	for (i = 0; i < 16; ++i) {3566		const size_t data_idx = i * 8;3567		const size_t row_idx = i * 16;3568		u32 dw0 =3569			(data[data_idx + 0] << 0) |3570			(data[data_idx + 1] << 8) |3571			(data[data_idx + 2] << 16) |3572			(data[data_idx + 3] << 24);3573		u32 dw1 =3574			(data[data_idx + 4] << 0) |3575			(data[data_idx + 5] << 8) |3576			(data[data_idx + 6] << 16) |3577			(data[data_idx + 7] << 24);3578		u32 tmp;3579 3580		/* Write row: dw0, dw1 and mask */3581		wr32(fhft + row_idx, dw0);3582		wr32(fhft + row_idx + 4, dw1);3583 3584		/* mask is only valid for MASK(7, 0) */3585		tmp = rd32(fhft + row_idx + 8);3586		tmp &= ~GENMASK(7, 0);3587		tmp |= mask[i];3588		wr32(fhft + row_idx + 8, tmp);3589	}3590 3591	/* Enable filter. */3592	wufc |= IGC_WUFC_FLEX_HQ;3593	if (input->index > 8) {3594		/* Filter 0-7 are enabled via WUFC. The other 24 filters are not. */3595		u32 wufc_ext = rd32(IGC_WUFC_EXT);3596 3597		wufc_ext |= (IGC_WUFC_EXT_FLX8 << (input->index - 8));3598 3599		wr32(IGC_WUFC_EXT, wufc_ext);3600	} else {3601		wufc |= (IGC_WUFC_FLX0 << input->index);3602	}3603	wr32(IGC_WUFC, wufc);3604 3605	netdev_dbg(adapter->netdev, "Added flex filter %u to HW.\n",3606		   input->index);3607 3608	return 0;3609}3610 3611static void igc_flex_filter_add_field(struct igc_flex_filter *flex,3612				      const void *src, unsigned int offset,3613				      size_t len, const void *mask)3614{3615	int i;3616 3617	/* data */3618	memcpy(&flex->data[offset], src, len);3619 3620	/* mask */3621	for (i = 0; i < len; ++i) {3622		const unsigned int idx = i + offset;3623		const u8 *ptr = mask;3624 3625		if (mask) {3626			if (ptr[i] & 0xff)3627				flex->mask[idx / 8] |= BIT(idx % 8);3628 3629			continue;3630		}3631 3632		flex->mask[idx / 8] |= BIT(idx % 8);3633	}3634}3635 3636static int igc_find_avail_flex_filter_slot(struct igc_adapter *adapter)3637{3638	struct igc_hw *hw = &adapter->hw;3639	u32 wufc, wufc_ext;3640	int i;3641 3642	wufc = rd32(IGC_WUFC);3643	wufc_ext = rd32(IGC_WUFC_EXT);3644 3645	for (i = 0; i < MAX_FLEX_FILTER; i++) {3646		if (i < 8) {3647			if (!(wufc & (IGC_WUFC_FLX0 << i)))3648				return i;3649		} else {3650			if (!(wufc_ext & (IGC_WUFC_EXT_FLX8 << (i - 8))))3651				return i;3652		}3653	}3654 3655	return -ENOSPC;3656}3657 3658static bool igc_flex_filter_in_use(struct igc_adapter *adapter)3659{3660	struct igc_hw *hw = &adapter->hw;3661	u32 wufc, wufc_ext;3662 3663	wufc = rd32(IGC_WUFC);3664	wufc_ext = rd32(IGC_WUFC_EXT);3665 3666	if (wufc & IGC_WUFC_FILTER_MASK)3667		return true;3668 3669	if (wufc_ext & IGC_WUFC_EXT_FILTER_MASK)3670		return true;3671 3672	return false;3673}3674 3675static int igc_add_flex_filter(struct igc_adapter *adapter,3676			       struct igc_nfc_rule *rule)3677{3678	struct igc_nfc_filter *filter = &rule->filter;3679	unsigned int eth_offset, user_offset;3680	struct igc_flex_filter flex = { };3681	int ret, index;3682	bool vlan;3683 3684	index = igc_find_avail_flex_filter_slot(adapter);3685	if (index < 0)3686		return -ENOSPC;3687 3688	/* Construct the flex filter:3689	 *  -> dest_mac [6]3690	 *  -> src_mac [6]3691	 *  -> tpid [2]3692	 *  -> vlan tci [2]3693	 *  -> ether type [2]3694	 *  -> user data [8]3695	 *  -> = 26 bytes => 32 length3696	 */3697	flex.index    = index;3698	flex.length   = 32;3699	flex.rx_queue = rule->action;3700 3701	vlan = rule->filter.vlan_tci || rule->filter.vlan_etype;3702	eth_offset = vlan ? 16 : 12;3703	user_offset = vlan ? 18 : 14;3704 3705	/* Add destination MAC  */3706	if (rule->filter.match_flags & IGC_FILTER_FLAG_DST_MAC_ADDR)3707		igc_flex_filter_add_field(&flex, &filter->dst_addr, 0,3708					  ETH_ALEN, NULL);3709 3710	/* Add source MAC */3711	if (rule->filter.match_flags & IGC_FILTER_FLAG_SRC_MAC_ADDR)3712		igc_flex_filter_add_field(&flex, &filter->src_addr, 6,3713					  ETH_ALEN, NULL);3714 3715	/* Add VLAN etype */3716	if (rule->filter.match_flags & IGC_FILTER_FLAG_VLAN_ETYPE) {3717		__be16 vlan_etype = cpu_to_be16(filter->vlan_etype);3718 3719		igc_flex_filter_add_field(&flex, &vlan_etype, 12,3720					  sizeof(vlan_etype), NULL);3721	}3722 3723	/* Add VLAN TCI */3724	if (rule->filter.match_flags & IGC_FILTER_FLAG_VLAN_TCI)3725		igc_flex_filter_add_field(&flex, &filter->vlan_tci, 14,3726					  sizeof(filter->vlan_tci), NULL);3727 3728	/* Add Ether type */3729	if (rule->filter.match_flags & IGC_FILTER_FLAG_ETHER_TYPE) {3730		__be16 etype = cpu_to_be16(filter->etype);3731 3732		igc_flex_filter_add_field(&flex, &etype, eth_offset,3733					  sizeof(etype), NULL);3734	}3735 3736	/* Add user data */3737	if (rule->filter.match_flags & IGC_FILTER_FLAG_USER_DATA)3738		igc_flex_filter_add_field(&flex, &filter->user_data,3739					  user_offset,3740					  sizeof(filter->user_data),3741					  filter->user_mask);3742 3743	/* Add it down to the hardware and enable it. */3744	ret = igc_write_flex_filter_ll(adapter, &flex);3745	if (ret)3746		return ret;3747 3748	filter->flex_index = index;3749 3750	return 0;3751}3752 3753static void igc_del_flex_filter(struct igc_adapter *adapter,3754				u16 reg_index)3755{3756	struct igc_hw *hw = &adapter->hw;3757	u32 wufc;3758 3759	/* Just disable the filter. The filter table itself is kept3760	 * intact. Another flex_filter_add() should override the "old" data3761	 * then.3762	 */3763	if (reg_index > 8) {3764		u32 wufc_ext = rd32(IGC_WUFC_EXT);3765 3766		wufc_ext &= ~(IGC_WUFC_EXT_FLX8 << (reg_index - 8));3767		wr32(IGC_WUFC_EXT, wufc_ext);3768	} else {3769		wufc = rd32(IGC_WUFC);3770 3771		wufc &= ~(IGC_WUFC_FLX0 << reg_index);3772		wr32(IGC_WUFC, wufc);3773	}3774 3775	if (igc_flex_filter_in_use(adapter))3776		return;3777 3778	/* No filters are in use, we may disable flex filters */3779	wufc = rd32(IGC_WUFC);3780	wufc &= ~IGC_WUFC_FLEX_HQ;3781	wr32(IGC_WUFC, wufc);3782}3783 3784static int igc_enable_nfc_rule(struct igc_adapter *adapter,3785			       struct igc_nfc_rule *rule)3786{3787	int err;3788 3789	if (rule->flex) {3790		return igc_add_flex_filter(adapter, rule);3791	}3792 3793	if (rule->filter.match_flags & IGC_FILTER_FLAG_ETHER_TYPE) {3794		err = igc_add_etype_filter(adapter, rule->filter.etype,3795					   rule->action);3796		if (err)3797			return err;3798	}3799 3800	if (rule->filter.match_flags & IGC_FILTER_FLAG_SRC_MAC_ADDR) {3801		err = igc_add_mac_filter(adapter, IGC_MAC_FILTER_TYPE_SRC,3802					 rule->filter.src_addr, rule->action);3803		if (err)3804			return err;3805	}3806 3807	if (rule->filter.match_flags & IGC_FILTER_FLAG_DST_MAC_ADDR) {3808		err = igc_add_mac_filter(adapter, IGC_MAC_FILTER_TYPE_DST,3809					 rule->filter.dst_addr, rule->action);3810		if (err)3811			return err;3812	}3813 3814	if (rule->filter.match_flags & IGC_FILTER_FLAG_VLAN_TCI) {3815		int prio = FIELD_GET(VLAN_PRIO_MASK, rule->filter.vlan_tci);3816 3817		err = igc_add_vlan_prio_filter(adapter, prio, rule->action);3818		if (err)3819			return err;3820	}3821 3822	return 0;3823}3824 3825static void igc_disable_nfc_rule(struct igc_adapter *adapter,3826				 const struct igc_nfc_rule *rule)3827{3828	if (rule->flex) {3829		igc_del_flex_filter(adapter, rule->filter.flex_index);3830		return;3831	}3832 3833	if (rule->filter.match_flags & IGC_FILTER_FLAG_ETHER_TYPE)3834		igc_del_etype_filter(adapter, rule->filter.etype);3835 3836	if (rule->filter.match_flags & IGC_FILTER_FLAG_VLAN_TCI) {3837		int prio = FIELD_GET(VLAN_PRIO_MASK, rule->filter.vlan_tci);3838 3839		igc_del_vlan_prio_filter(adapter, prio);3840	}3841 3842	if (rule->filter.match_flags & IGC_FILTER_FLAG_SRC_MAC_ADDR)3843		igc_del_mac_filter(adapter, IGC_MAC_FILTER_TYPE_SRC,3844				   rule->filter.src_addr);3845 3846	if (rule->filter.match_flags & IGC_FILTER_FLAG_DST_MAC_ADDR)3847		igc_del_mac_filter(adapter, IGC_MAC_FILTER_TYPE_DST,3848				   rule->filter.dst_addr);3849}3850 3851/**3852 * igc_get_nfc_rule() - Get NFC rule3853 * @adapter: Pointer to adapter3854 * @location: Rule location3855 *3856 * Context: Expects adapter->nfc_rule_lock to be held by caller.3857 *3858 * Return: Pointer to NFC rule at @location. If not found, NULL.3859 */3860struct igc_nfc_rule *igc_get_nfc_rule(struct igc_adapter *adapter,3861				      u32 location)3862{3863	struct igc_nfc_rule *rule;3864 3865	list_for_each_entry(rule, &adapter->nfc_rule_list, list) {3866		if (rule->location == location)3867			return rule;3868		if (rule->location > location)3869			break;3870	}3871 3872	return NULL;3873}3874 3875/**3876 * igc_del_nfc_rule() - Delete NFC rule3877 * @adapter: Pointer to adapter3878 * @rule: Pointer to rule to be deleted3879 *3880 * Disable NFC rule in hardware and delete it from adapter.3881 *3882 * Context: Expects adapter->nfc_rule_lock to be held by caller.3883 */3884void igc_del_nfc_rule(struct igc_adapter *adapter, struct igc_nfc_rule *rule)3885{3886	igc_disable_nfc_rule(adapter, rule);3887 3888	list_del(&rule->list);3889	adapter->nfc_rule_count--;3890 3891	kfree(rule);3892}3893 3894static void igc_flush_nfc_rules(struct igc_adapter *adapter)3895{3896	struct igc_nfc_rule *rule, *tmp;3897 3898	mutex_lock(&adapter->nfc_rule_lock);3899 3900	list_for_each_entry_safe(rule, tmp, &adapter->nfc_rule_list, list)3901		igc_del_nfc_rule(adapter, rule);3902 3903	mutex_unlock(&adapter->nfc_rule_lock);3904}3905 3906/**3907 * igc_add_nfc_rule() - Add NFC rule3908 * @adapter: Pointer to adapter3909 * @rule: Pointer to rule to be added3910 *3911 * Enable NFC rule in hardware and add it to adapter.3912 *3913 * Context: Expects adapter->nfc_rule_lock to be held by caller.3914 *3915 * Return: 0 on success, negative errno on failure.3916 */3917int igc_add_nfc_rule(struct igc_adapter *adapter, struct igc_nfc_rule *rule)3918{3919	struct igc_nfc_rule *pred, *cur;3920	int err;3921 3922	err = igc_enable_nfc_rule(adapter, rule);3923	if (err)3924		return err;3925 3926	pred = NULL;3927	list_for_each_entry(cur, &adapter->nfc_rule_list, list) {3928		if (cur->location >= rule->location)3929			break;3930		pred = cur;3931	}3932 3933	list_add(&rule->list, pred ? &pred->list : &adapter->nfc_rule_list);3934	adapter->nfc_rule_count++;3935	return 0;3936}3937 3938static void igc_restore_nfc_rules(struct igc_adapter *adapter)3939{3940	struct igc_nfc_rule *rule;3941 3942	mutex_lock(&adapter->nfc_rule_lock);3943 3944	list_for_each_entry_reverse(rule, &adapter->nfc_rule_list, list)3945		igc_enable_nfc_rule(adapter, rule);3946 3947	mutex_unlock(&adapter->nfc_rule_lock);3948}3949 3950static int igc_uc_sync(struct net_device *netdev, const unsigned char *addr)3951{3952	struct igc_adapter *adapter = netdev_priv(netdev);3953 3954	return igc_add_mac_filter(adapter, IGC_MAC_FILTER_TYPE_DST, addr, -1);3955}3956 3957static int igc_uc_unsync(struct net_device *netdev, const unsigned char *addr)3958{3959	struct igc_adapter *adapter = netdev_priv(netdev);3960 3961	igc_del_mac_filter(adapter, IGC_MAC_FILTER_TYPE_DST, addr);3962	return 0;3963}3964 3965/**3966 * igc_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set3967 * @netdev: network interface device structure3968 *3969 * The set_rx_mode entry point is called whenever the unicast or multicast3970 * address lists or the network interface flags are updated.  This routine is3971 * responsible for configuring the hardware for proper unicast, multicast,3972 * promiscuous mode, and all-multi behavior.3973 */3974static void igc_set_rx_mode(struct net_device *netdev)3975{3976	struct igc_adapter *adapter = netdev_priv(netdev);3977	struct igc_hw *hw = &adapter->hw;3978	u32 rctl = 0, rlpml = MAX_JUMBO_FRAME_SIZE;3979	int count;3980 3981	/* Check for Promiscuous and All Multicast modes */3982	if (netdev->flags & IFF_PROMISC) {3983		rctl |= IGC_RCTL_UPE | IGC_RCTL_MPE;3984	} else {3985		if (netdev->flags & IFF_ALLMULTI) {3986			rctl |= IGC_RCTL_MPE;3987		} else {3988			/* Write addresses to the MTA, if the attempt fails3989			 * then we should just turn on promiscuous mode so3990			 * that we can at least receive multicast traffic3991			 */3992			count = igc_write_mc_addr_list(netdev);3993			if (count < 0)3994				rctl |= IGC_RCTL_MPE;3995		}3996	}3997 3998	/* Write addresses to available RAR registers, if there is not3999	 * sufficient space to store all the addresses then enable4000	 * unicast promiscuous mode4001	 */4002	if (__dev_uc_sync(netdev, igc_uc_sync, igc_uc_unsync))4003		rctl |= IGC_RCTL_UPE;4004 4005	/* update state of unicast and multicast */4006	rctl |= rd32(IGC_RCTL) & ~(IGC_RCTL_UPE | IGC_RCTL_MPE);4007	wr32(IGC_RCTL, rctl);4008 4009#if (PAGE_SIZE < 8192)4010	if (adapter->max_frame_size <= IGC_MAX_FRAME_BUILD_SKB)4011		rlpml = IGC_MAX_FRAME_BUILD_SKB;4012#endif4013	wr32(IGC_RLPML, rlpml);4014}4015 4016/**4017 * igc_configure - configure the hardware for RX and TX4018 * @adapter: private board structure4019 */4020static void igc_configure(struct igc_adapter *adapter)4021{4022	struct net_device *netdev = adapter->netdev;4023	int i = 0;4024 4025	igc_get_hw_control(adapter);4026	igc_set_rx_mode(netdev);4027 4028	igc_restore_vlan(adapter);4029 4030	igc_setup_tctl(adapter);4031	igc_setup_mrqc(adapter);4032	igc_setup_rctl(adapter);4033 4034	igc_set_default_mac_filter(adapter);4035	igc_restore_nfc_rules(adapter);4036 4037	igc_configure_tx(adapter);4038	igc_configure_rx(adapter);4039 4040	igc_rx_fifo_flush_base(&adapter->hw);4041 4042	/* call igc_desc_unused which always leaves4043	 * at least 1 descriptor unused to make sure4044	 * next_to_use != next_to_clean4045	 */4046	for (i = 0; i < adapter->num_rx_queues; i++) {4047		struct igc_ring *ring = adapter->rx_ring[i];4048 4049		if (ring->xsk_pool)4050			igc_alloc_rx_buffers_zc(ring, igc_desc_unused(ring));4051		else4052			igc_alloc_rx_buffers(ring, igc_desc_unused(ring));4053	}4054}4055 4056/**4057 * igc_write_ivar - configure ivar for given MSI-X vector4058 * @hw: pointer to the HW structure4059 * @msix_vector: vector number we are allocating to a given ring4060 * @index: row index of IVAR register to write within IVAR table4061 * @offset: column offset of in IVAR, should be multiple of 84062 *4063 * The IVAR table consists of 2 columns,4064 * each containing an cause allocation for an Rx and Tx ring, and a4065 * variable number of rows depending on the number of queues supported.4066 */4067static void igc_write_ivar(struct igc_hw *hw, int msix_vector,4068			   int index, int offset)4069{4070	u32 ivar = array_rd32(IGC_IVAR0, index);4071 4072	/* clear any bits that are currently set */4073	ivar &= ~((u32)0xFF << offset);4074 4075	/* write vector and valid bit */4076	ivar |= (msix_vector | IGC_IVAR_VALID) << offset;4077 4078	array_wr32(IGC_IVAR0, index, ivar);4079}4080 4081static void igc_assign_vector(struct igc_q_vector *q_vector, int msix_vector)4082{4083	struct igc_adapter *adapter = q_vector->adapter;4084	struct igc_hw *hw = &adapter->hw;4085	int rx_queue = IGC_N0_QUEUE;4086	int tx_queue = IGC_N0_QUEUE;4087 4088	if (q_vector->rx.ring)4089		rx_queue = q_vector->rx.ring->reg_idx;4090	if (q_vector->tx.ring)4091		tx_queue = q_vector->tx.ring->reg_idx;4092 4093	switch (hw->mac.type) {4094	case igc_i225:4095		if (rx_queue > IGC_N0_QUEUE)4096			igc_write_ivar(hw, msix_vector,4097				       rx_queue >> 1,4098				       (rx_queue & 0x1) << 4);4099		if (tx_queue > IGC_N0_QUEUE)4100			igc_write_ivar(hw, msix_vector,4101				       tx_queue >> 1,4102				       ((tx_queue & 0x1) << 4) + 8);4103		q_vector->eims_value = BIT(msix_vector);4104		break;4105	default:4106		WARN_ONCE(hw->mac.type != igc_i225, "Wrong MAC type\n");4107		break;4108	}4109 4110	/* add q_vector eims value to global eims_enable_mask */4111	adapter->eims_enable_mask |= q_vector->eims_value;4112 4113	/* configure q_vector to set itr on first interrupt */4114	q_vector->set_itr = 1;4115}4116 4117/**4118 * igc_configure_msix - Configure MSI-X hardware4119 * @adapter: Pointer to adapter structure4120 *4121 * igc_configure_msix sets up the hardware to properly4122 * generate MSI-X interrupts.4123 */4124static void igc_configure_msix(struct igc_adapter *adapter)4125{4126	struct igc_hw *hw = &adapter->hw;4127	int i, vector = 0;4128	u32 tmp;4129 4130	adapter->eims_enable_mask = 0;4131 4132	/* set vector for other causes, i.e. link changes */4133	switch (hw->mac.type) {4134	case igc_i225:4135		/* Turn on MSI-X capability first, or our settings4136		 * won't stick.  And it will take days to debug.4137		 */4138		wr32(IGC_GPIE, IGC_GPIE_MSIX_MODE |4139		     IGC_GPIE_PBA | IGC_GPIE_EIAME |4140		     IGC_GPIE_NSICR);4141 4142		/* enable msix_other interrupt */4143		adapter->eims_other = BIT(vector);4144		tmp = (vector++ | IGC_IVAR_VALID) << 8;4145 4146		wr32(IGC_IVAR_MISC, tmp);4147		break;4148	default:4149		/* do nothing, since nothing else supports MSI-X */4150		break;4151	} /* switch (hw->mac.type) */4152 4153	adapter->eims_enable_mask |= adapter->eims_other;4154 4155	for (i = 0; i < adapter->num_q_vectors; i++)4156		igc_assign_vector(adapter->q_vector[i], vector++);4157 4158	wrfl();4159}4160 4161/**4162 * igc_irq_enable - Enable default interrupt generation settings4163 * @adapter: board private structure4164 */4165static void igc_irq_enable(struct igc_adapter *adapter)4166{4167	struct igc_hw *hw = &adapter->hw;4168 4169	if (adapter->msix_entries) {4170		u32 ims = IGC_IMS_LSC | IGC_IMS_DOUTSYNC | IGC_IMS_DRSTA;4171		u32 regval = rd32(IGC_EIAC);4172 4173		wr32(IGC_EIAC, regval | adapter->eims_enable_mask);4174		regval = rd32(IGC_EIAM);4175		wr32(IGC_EIAM, regval | adapter->eims_enable_mask);4176		wr32(IGC_EIMS, adapter->eims_enable_mask);4177		wr32(IGC_IMS, ims);4178	} else {4179		wr32(IGC_IMS, IMS_ENABLE_MASK | IGC_IMS_DRSTA);4180		wr32(IGC_IAM, IMS_ENABLE_MASK | IGC_IMS_DRSTA);4181	}4182}4183 4184/**4185 * igc_irq_disable - Mask off interrupt generation on the NIC4186 * @adapter: board private structure4187 */4188static void igc_irq_disable(struct igc_adapter *adapter)4189{4190	struct igc_hw *hw = &adapter->hw;4191 4192	if (adapter->msix_entries) {4193		u32 regval = rd32(IGC_EIAM);4194 4195		wr32(IGC_EIAM, regval & ~adapter->eims_enable_mask);4196		wr32(IGC_EIMC, adapter->eims_enable_mask);4197		regval = rd32(IGC_EIAC);4198		wr32(IGC_EIAC, regval & ~adapter->eims_enable_mask);4199	}4200 4201	wr32(IGC_IAM, 0);4202	wr32(IGC_IMC, ~0);4203	wrfl();4204 4205	if (adapter->msix_entries) {4206		int vector = 0, i;4207 4208		synchronize_irq(adapter->msix_entries[vector++].vector);4209 4210		for (i = 0; i < adapter->num_q_vectors; i++)4211			synchronize_irq(adapter->msix_entries[vector++].vector);4212	} else {4213		synchronize_irq(adapter->pdev->irq);4214	}4215}4216 4217void igc_set_flag_queue_pairs(struct igc_adapter *adapter,4218			      const u32 max_rss_queues)4219{4220	/* Determine if we need to pair queues. */4221	/* If rss_queues > half of max_rss_queues, pair the queues in4222	 * order to conserve interrupts due to limited supply.4223	 */4224	if (adapter->rss_queues > (max_rss_queues / 2))4225		adapter->flags |= IGC_FLAG_QUEUE_PAIRS;4226	else4227		adapter->flags &= ~IGC_FLAG_QUEUE_PAIRS;4228}4229 4230unsigned int igc_get_max_rss_queues(struct igc_adapter *adapter)4231{4232	return IGC_MAX_RX_QUEUES;4233}4234 4235static void igc_init_queue_configuration(struct igc_adapter *adapter)4236{4237	u32 max_rss_queues;4238 4239	max_rss_queues = igc_get_max_rss_queues(adapter);4240	adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus());4241 4242	igc_set_flag_queue_pairs(adapter, max_rss_queues);4243}4244 4245/**4246 * igc_reset_q_vector - Reset config for interrupt vector4247 * @adapter: board private structure to initialize4248 * @v_idx: Index of vector to be reset4249 *4250 * If NAPI is enabled it will delete any references to the4251 * NAPI struct. This is preparation for igc_free_q_vector.4252 */4253static void igc_reset_q_vector(struct igc_adapter *adapter, int v_idx)4254{4255	struct igc_q_vector *q_vector = adapter->q_vector[v_idx];4256 4257	/* if we're coming from igc_set_interrupt_capability, the vectors are4258	 * not yet allocated4259	 */4260	if (!q_vector)4261		return;4262 4263	if (q_vector->tx.ring)4264		adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL;4265 4266	if (q_vector->rx.ring)4267		adapter->rx_ring[q_vector->rx.ring->queue_index] = NULL;4268 4269	netif_napi_del(&q_vector->napi);4270}4271 4272/**4273 * igc_free_q_vector - Free memory allocated for specific interrupt vector4274 * @adapter: board private structure to initialize4275 * @v_idx: Index of vector to be freed4276 *4277 * This function frees the memory allocated to the q_vector.4278 */4279static void igc_free_q_vector(struct igc_adapter *adapter, int v_idx)4280{4281	struct igc_q_vector *q_vector = adapter->q_vector[v_idx];4282 4283	adapter->q_vector[v_idx] = NULL;4284 4285	/* igc_get_stats64() might access the rings on this vector,4286	 * we must wait a grace period before freeing it.4287	 */4288	if (q_vector)4289		kfree_rcu(q_vector, rcu);4290}4291 4292/**4293 * igc_free_q_vectors - Free memory allocated for interrupt vectors4294 * @adapter: board private structure to initialize4295 *4296 * This function frees the memory allocated to the q_vectors.  In addition if4297 * NAPI is enabled it will delete any references to the NAPI struct prior4298 * to freeing the q_vector.4299 */4300static void igc_free_q_vectors(struct igc_adapter *adapter)4301{4302	int v_idx = adapter->num_q_vectors;4303 4304	adapter->num_tx_queues = 0;4305	adapter->num_rx_queues = 0;4306	adapter->num_q_vectors = 0;4307 4308	while (v_idx--) {4309		igc_reset_q_vector(adapter, v_idx);4310		igc_free_q_vector(adapter, v_idx);4311	}4312}4313 4314/**4315 * igc_update_itr - update the dynamic ITR value based on statistics4316 * @q_vector: pointer to q_vector4317 * @ring_container: ring info to update the itr for4318 *4319 * Stores a new ITR value based on packets and byte4320 * counts during the last interrupt.  The advantage of per interrupt4321 * computation is faster updates and more accurate ITR for the current4322 * traffic pattern.  Constants in this function were computed4323 * based on theoretical maximum wire speed and thresholds were set based4324 * on testing data as well as attempting to minimize response time4325 * while increasing bulk throughput.4326 * NOTE: These calculations are only valid when operating in a single-4327 * queue environment.4328 */4329static void igc_update_itr(struct igc_q_vector *q_vector,4330			   struct igc_ring_container *ring_container)4331{4332	unsigned int packets = ring_container->total_packets;4333	unsigned int bytes = ring_container->total_bytes;4334	u8 itrval = ring_container->itr;4335 4336	/* no packets, exit with status unchanged */4337	if (packets == 0)4338		return;4339 4340	switch (itrval) {4341	case lowest_latency:4342		/* handle TSO and jumbo frames */4343		if (bytes / packets > 8000)4344			itrval = bulk_latency;4345		else if ((packets < 5) && (bytes > 512))4346			itrval = low_latency;4347		break;4348	case low_latency:  /* 50 usec aka 20000 ints/s */4349		if (bytes > 10000) {4350			/* this if handles the TSO accounting */4351			if (bytes / packets > 8000)4352				itrval = bulk_latency;4353			else if ((packets < 10) || ((bytes / packets) > 1200))4354				itrval = bulk_latency;4355			else if ((packets > 35))4356				itrval = lowest_latency;4357		} else if (bytes / packets > 2000) {4358			itrval = bulk_latency;4359		} else if (packets <= 2 && bytes < 512) {4360			itrval = lowest_latency;4361		}4362		break;4363	case bulk_latency: /* 250 usec aka 4000 ints/s */4364		if (bytes > 25000) {4365			if (packets > 35)4366				itrval = low_latency;4367		} else if (bytes < 1500) {4368			itrval = low_latency;4369		}4370		break;4371	}4372 4373	/* clear work counters since we have the values we need */4374	ring_container->total_bytes = 0;4375	ring_container->total_packets = 0;4376 4377	/* write updated itr to ring container */4378	ring_container->itr = itrval;4379}4380 4381static void igc_set_itr(struct igc_q_vector *q_vector)4382{4383	struct igc_adapter *adapter = q_vector->adapter;4384	u32 new_itr = q_vector->itr_val;4385	u8 current_itr = 0;4386 4387	/* for non-gigabit speeds, just fix the interrupt rate at 4000 */4388	switch (adapter->link_speed) {4389	case SPEED_10:4390	case SPEED_100:4391		current_itr = 0;4392		new_itr = IGC_4K_ITR;4393		goto set_itr_now;4394	default:4395		break;4396	}4397 4398	igc_update_itr(q_vector, &q_vector->tx);4399	igc_update_itr(q_vector, &q_vector->rx);4400 4401	current_itr = max(q_vector->rx.itr, q_vector->tx.itr);4402 4403	/* conservative mode (itr 3) eliminates the lowest_latency setting */4404	if (current_itr == lowest_latency &&4405	    ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||4406	    (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))4407		current_itr = low_latency;4408 4409	switch (current_itr) {4410	/* counts and packets in update_itr are dependent on these numbers */4411	case lowest_latency:4412		new_itr = IGC_70K_ITR; /* 70,000 ints/sec */4413		break;4414	case low_latency:4415		new_itr = IGC_20K_ITR; /* 20,000 ints/sec */4416		break;4417	case bulk_latency:4418		new_itr = IGC_4K_ITR;  /* 4,000 ints/sec */4419		break;4420	default:4421		break;4422	}4423 4424set_itr_now:4425	if (new_itr != q_vector->itr_val) {4426		/* this attempts to bias the interrupt rate towards Bulk4427		 * by adding intermediate steps when interrupt rate is4428		 * increasing4429		 */4430		new_itr = new_itr > q_vector->itr_val ?4431			  max((new_itr * q_vector->itr_val) /4432			  (new_itr + (q_vector->itr_val >> 2)),4433			  new_itr) : new_itr;4434		/* Don't write the value here; it resets the adapter's4435		 * internal timer, and causes us to delay far longer than4436		 * we should between interrupts.  Instead, we write the ITR4437		 * value at the beginning of the next interrupt so the timing4438		 * ends up being correct.4439		 */4440		q_vector->itr_val = new_itr;4441		q_vector->set_itr = 1;4442	}4443}4444 4445static void igc_reset_interrupt_capability(struct igc_adapter *adapter)4446{4447	int v_idx = adapter->num_q_vectors;4448 4449	if (adapter->msix_entries) {4450		pci_disable_msix(adapter->pdev);4451		kfree(adapter->msix_entries);4452		adapter->msix_entries = NULL;4453	} else if (adapter->flags & IGC_FLAG_HAS_MSI) {4454		pci_disable_msi(adapter->pdev);4455	}4456 4457	while (v_idx--)4458		igc_reset_q_vector(adapter, v_idx);4459}4460 4461/**4462 * igc_set_interrupt_capability - set MSI or MSI-X if supported4463 * @adapter: Pointer to adapter structure4464 * @msix: boolean value for MSI-X capability4465 *4466 * Attempt to configure interrupts using the best available4467 * capabilities of the hardware and kernel.4468 */4469static void igc_set_interrupt_capability(struct igc_adapter *adapter,4470					 bool msix)4471{4472	int numvecs, i;4473	int err;4474 4475	if (!msix)4476		goto msi_only;4477	adapter->flags |= IGC_FLAG_HAS_MSIX;4478 4479	/* Number of supported queues. */4480	adapter->num_rx_queues = adapter->rss_queues;4481 4482	adapter->num_tx_queues = adapter->rss_queues;4483 4484	/* start with one vector for every Rx queue */4485	numvecs = adapter->num_rx_queues;4486 4487	/* if Tx handler is separate add 1 for every Tx queue */4488	if (!(adapter->flags & IGC_FLAG_QUEUE_PAIRS))4489		numvecs += adapter->num_tx_queues;4490 4491	/* store the number of vectors reserved for queues */4492	adapter->num_q_vectors = numvecs;4493 4494	/* add 1 vector for link status interrupts */4495	numvecs++;4496 4497	adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),4498					GFP_KERNEL);4499 4500	if (!adapter->msix_entries)4501		return;4502 4503	/* populate entry values */4504	for (i = 0; i < numvecs; i++)4505		adapter->msix_entries[i].entry = i;4506 4507	err = pci_enable_msix_range(adapter->pdev,4508				    adapter->msix_entries,4509				    numvecs,4510				    numvecs);4511	if (err > 0)4512		return;4513 4514	kfree(adapter->msix_entries);4515	adapter->msix_entries = NULL;4516 4517	igc_reset_interrupt_capability(adapter);4518 4519msi_only:4520	adapter->flags &= ~IGC_FLAG_HAS_MSIX;4521 4522	adapter->rss_queues = 1;4523	adapter->flags |= IGC_FLAG_QUEUE_PAIRS;4524	adapter->num_rx_queues = 1;4525	adapter->num_tx_queues = 1;4526	adapter->num_q_vectors = 1;4527	if (!pci_enable_msi(adapter->pdev))4528		adapter->flags |= IGC_FLAG_HAS_MSI;4529}4530 4531/**4532 * igc_update_ring_itr - update the dynamic ITR value based on packet size4533 * @q_vector: pointer to q_vector4534 *4535 * Stores a new ITR value based on strictly on packet size.  This4536 * algorithm is less sophisticated than that used in igc_update_itr,4537 * due to the difficulty of synchronizing statistics across multiple4538 * receive rings.  The divisors and thresholds used by this function4539 * were determined based on theoretical maximum wire speed and testing4540 * data, in order to minimize response time while increasing bulk4541 * throughput.4542 * NOTE: This function is called only when operating in a multiqueue4543 * receive environment.4544 */4545static void igc_update_ring_itr(struct igc_q_vector *q_vector)4546{4547	struct igc_adapter *adapter = q_vector->adapter;4548	int new_val = q_vector->itr_val;4549	int avg_wire_size = 0;4550	unsigned int packets;4551 4552	/* For non-gigabit speeds, just fix the interrupt rate at 40004553	 * ints/sec - ITR timer value of 120 ticks.4554	 */4555	switch (adapter->link_speed) {4556	case SPEED_10:4557	case SPEED_100:4558		new_val = IGC_4K_ITR;4559		goto set_itr_val;4560	default:4561		break;4562	}4563 4564	packets = q_vector->rx.total_packets;4565	if (packets)4566		avg_wire_size = q_vector->rx.total_bytes / packets;4567 4568	packets = q_vector->tx.total_packets;4569	if (packets)4570		avg_wire_size = max_t(u32, avg_wire_size,4571				      q_vector->tx.total_bytes / packets);4572 4573	/* if avg_wire_size isn't set no work was done */4574	if (!avg_wire_size)4575		goto clear_counts;4576 4577	/* Add 24 bytes to size to account for CRC, preamble, and gap */4578	avg_wire_size += 24;4579 4580	/* Don't starve jumbo frames */4581	avg_wire_size = min(avg_wire_size, 3000);4582 4583	/* Give a little boost to mid-size frames */4584	if (avg_wire_size > 300 && avg_wire_size < 1200)4585		new_val = avg_wire_size / 3;4586	else4587		new_val = avg_wire_size / 2;4588 4589	/* conservative mode (itr 3) eliminates the lowest_latency setting */4590	if (new_val < IGC_20K_ITR &&4591	    ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||4592	    (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))4593		new_val = IGC_20K_ITR;4594 4595set_itr_val:4596	if (new_val != q_vector->itr_val) {4597		q_vector->itr_val = new_val;4598		q_vector->set_itr = 1;4599	}4600clear_counts:4601	q_vector->rx.total_bytes = 0;4602	q_vector->rx.total_packets = 0;4603	q_vector->tx.total_bytes = 0;4604	q_vector->tx.total_packets = 0;4605}4606 4607static void igc_ring_irq_enable(struct igc_q_vector *q_vector)4608{4609	struct igc_adapter *adapter = q_vector->adapter;4610	struct igc_hw *hw = &adapter->hw;4611 4612	if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) ||4613	    (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) {4614		if (adapter->num_q_vectors == 1)4615			igc_set_itr(q_vector);4616		else4617			igc_update_ring_itr(q_vector);4618	}4619 4620	if (!test_bit(__IGC_DOWN, &adapter->state)) {4621		if (adapter->msix_entries)4622			wr32(IGC_EIMS, q_vector->eims_value);4623		else4624			igc_irq_enable(adapter);4625	}4626}4627 4628static void igc_add_ring(struct igc_ring *ring,4629			 struct igc_ring_container *head)4630{4631	head->ring = ring;4632	head->count++;4633}4634 4635/**4636 * igc_cache_ring_register - Descriptor ring to register mapping4637 * @adapter: board private structure to initialize4638 *4639 * Once we know the feature-set enabled for the device, we'll cache4640 * the register offset the descriptor ring is assigned to.4641 */4642static void igc_cache_ring_register(struct igc_adapter *adapter)4643{4644	int i = 0, j = 0;4645 4646	switch (adapter->hw.mac.type) {4647	case igc_i225:4648	default:4649		for (; i < adapter->num_rx_queues; i++)4650			adapter->rx_ring[i]->reg_idx = i;4651		for (; j < adapter->num_tx_queues; j++)4652			adapter->tx_ring[j]->reg_idx = j;4653		break;4654	}4655}4656 4657/**4658 * igc_poll - NAPI Rx polling callback4659 * @napi: napi polling structure4660 * @budget: count of how many packets we should handle4661 */4662static int igc_poll(struct napi_struct *napi, int budget)4663{4664	struct igc_q_vector *q_vector = container_of(napi,4665						     struct igc_q_vector,4666						     napi);4667	struct igc_ring *rx_ring = q_vector->rx.ring;4668	bool clean_complete = true;4669	int work_done = 0;4670 4671	if (q_vector->tx.ring)4672		clean_complete = igc_clean_tx_irq(q_vector, budget);4673 4674	if (rx_ring) {4675		int cleaned = rx_ring->xsk_pool ?4676			      igc_clean_rx_irq_zc(q_vector, budget) :4677			      igc_clean_rx_irq(q_vector, budget);4678 4679		work_done += cleaned;4680		if (cleaned >= budget)4681			clean_complete = false;4682	}4683 4684	/* If all work not completed, return budget and keep polling */4685	if (!clean_complete)4686		return budget;4687 4688	/* Exit the polling mode, but don't re-enable interrupts if stack might4689	 * poll us due to busy-polling4690	 */4691	if (likely(napi_complete_done(napi, work_done)))4692		igc_ring_irq_enable(q_vector);4693 4694	return min(work_done, budget - 1);4695}4696 4697/**4698 * igc_alloc_q_vector - Allocate memory for a single interrupt vector4699 * @adapter: board private structure to initialize4700 * @v_count: q_vectors allocated on adapter, used for ring interleaving4701 * @v_idx: index of vector in adapter struct4702 * @txr_count: total number of Tx rings to allocate4703 * @txr_idx: index of first Tx ring to allocate4704 * @rxr_count: total number of Rx rings to allocate4705 * @rxr_idx: index of first Rx ring to allocate4706 *4707 * We allocate one q_vector.  If allocation fails we return -ENOMEM.4708 */4709static int igc_alloc_q_vector(struct igc_adapter *adapter,4710			      unsigned int v_count, unsigned int v_idx,4711			      unsigned int txr_count, unsigned int txr_idx,4712			      unsigned int rxr_count, unsigned int rxr_idx)4713{4714	struct igc_q_vector *q_vector;4715	struct igc_ring *ring;4716	int ring_count;4717 4718	/* igc only supports 1 Tx and/or 1 Rx queue per vector */4719	if (txr_count > 1 || rxr_count > 1)4720		return -ENOMEM;4721 4722	ring_count = txr_count + rxr_count;4723 4724	/* allocate q_vector and rings */4725	q_vector = adapter->q_vector[v_idx];4726	if (!q_vector)4727		q_vector = kzalloc(struct_size(q_vector, ring, ring_count),4728				   GFP_KERNEL);4729	else4730		memset(q_vector, 0, struct_size(q_vector, ring, ring_count));4731	if (!q_vector)4732		return -ENOMEM;4733 4734	/* initialize NAPI */4735	netif_napi_add(adapter->netdev, &q_vector->napi, igc_poll);4736 4737	/* tie q_vector and adapter together */4738	adapter->q_vector[v_idx] = q_vector;4739	q_vector->adapter = adapter;4740 4741	/* initialize work limits */4742	q_vector->tx.work_limit = adapter->tx_work_limit;4743 4744	/* initialize ITR configuration */4745	q_vector->itr_register = adapter->io_addr + IGC_EITR(0);4746	q_vector->itr_val = IGC_START_ITR;4747 4748	/* initialize pointer to rings */4749	ring = q_vector->ring;4750 4751	/* initialize ITR */4752	if (rxr_count) {4753		/* rx or rx/tx vector */4754		if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3)4755			q_vector->itr_val = adapter->rx_itr_setting;4756	} else {4757		/* tx only vector */4758		if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3)4759			q_vector->itr_val = adapter->tx_itr_setting;4760	}4761 4762	if (txr_count) {4763		/* assign generic ring traits */4764		ring->dev = &adapter->pdev->dev;4765		ring->netdev = adapter->netdev;4766 4767		/* configure backlink on ring */4768		ring->q_vector = q_vector;4769 4770		/* update q_vector Tx values */4771		igc_add_ring(ring, &q_vector->tx);4772 4773		/* apply Tx specific ring traits */4774		ring->count = adapter->tx_ring_count;4775		ring->queue_index = txr_idx;4776 4777		/* assign ring to adapter */4778		adapter->tx_ring[txr_idx] = ring;4779 4780		/* push pointer to next ring */4781		ring++;4782	}4783 4784	if (rxr_count) {4785		/* assign generic ring traits */4786		ring->dev = &adapter->pdev->dev;4787		ring->netdev = adapter->netdev;4788 4789		/* configure backlink on ring */4790		ring->q_vector = q_vector;4791 4792		/* update q_vector Rx values */4793		igc_add_ring(ring, &q_vector->rx);4794 4795		/* apply Rx specific ring traits */4796		ring->count = adapter->rx_ring_count;4797		ring->queue_index = rxr_idx;4798 4799		/* assign ring to adapter */4800		adapter->rx_ring[rxr_idx] = ring;4801	}4802 4803	return 0;4804}4805 4806/**4807 * igc_alloc_q_vectors - Allocate memory for interrupt vectors4808 * @adapter: board private structure to initialize4809 *4810 * We allocate one q_vector per queue interrupt.  If allocation fails we4811 * return -ENOMEM.4812 */4813static int igc_alloc_q_vectors(struct igc_adapter *adapter)4814{4815	int rxr_remaining = adapter->num_rx_queues;4816	int txr_remaining = adapter->num_tx_queues;4817	int rxr_idx = 0, txr_idx = 0, v_idx = 0;4818	int q_vectors = adapter->num_q_vectors;4819	int err;4820 4821	if (q_vectors >= (rxr_remaining + txr_remaining)) {4822		for (; rxr_remaining; v_idx++) {4823			err = igc_alloc_q_vector(adapter, q_vectors, v_idx,4824						 0, 0, 1, rxr_idx);4825 4826			if (err)4827				goto err_out;4828 4829			/* update counts and index */4830			rxr_remaining--;4831			rxr_idx++;4832		}4833	}4834 4835	for (; v_idx < q_vectors; v_idx++) {4836		int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx);4837		int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx);4838 4839		err = igc_alloc_q_vector(adapter, q_vectors, v_idx,4840					 tqpv, txr_idx, rqpv, rxr_idx);4841 4842		if (err)4843			goto err_out;4844 4845		/* update counts and index */4846		rxr_remaining -= rqpv;4847		txr_remaining -= tqpv;4848		rxr_idx++;4849		txr_idx++;4850	}4851 4852	return 0;4853 4854err_out:4855	adapter->num_tx_queues = 0;4856	adapter->num_rx_queues = 0;4857	adapter->num_q_vectors = 0;4858 4859	while (v_idx--)4860		igc_free_q_vector(adapter, v_idx);4861 4862	return -ENOMEM;4863}4864 4865/**4866 * igc_init_interrupt_scheme - initialize interrupts, allocate queues/vectors4867 * @adapter: Pointer to adapter structure4868 * @msix: boolean for MSI-X capability4869 *4870 * This function initializes the interrupts and allocates all of the queues.4871 */4872static int igc_init_interrupt_scheme(struct igc_adapter *adapter, bool msix)4873{4874	struct net_device *dev = adapter->netdev;4875	int err = 0;4876 4877	igc_set_interrupt_capability(adapter, msix);4878 4879	err = igc_alloc_q_vectors(adapter);4880	if (err) {4881		netdev_err(dev, "Unable to allocate memory for vectors\n");4882		goto err_alloc_q_vectors;4883	}4884 4885	igc_cache_ring_register(adapter);4886 4887	return 0;4888 4889err_alloc_q_vectors:4890	igc_reset_interrupt_capability(adapter);4891	return err;4892}4893 4894/**4895 * igc_sw_init - Initialize general software structures (struct igc_adapter)4896 * @adapter: board private structure to initialize4897 *4898 * igc_sw_init initializes the Adapter private data structure.4899 * Fields are initialized based on PCI device information and4900 * OS network device settings (MTU size).4901 */4902static int igc_sw_init(struct igc_adapter *adapter)4903{4904	struct net_device *netdev = adapter->netdev;4905	struct pci_dev *pdev = adapter->pdev;4906	struct igc_hw *hw = &adapter->hw;4907 4908	pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);4909 4910	/* set default ring sizes */4911	adapter->tx_ring_count = IGC_DEFAULT_TXD;4912	adapter->rx_ring_count = IGC_DEFAULT_RXD;4913 4914	/* set default ITR values */4915	adapter->rx_itr_setting = IGC_DEFAULT_ITR;4916	adapter->tx_itr_setting = IGC_DEFAULT_ITR;4917 4918	/* set default work limits */4919	adapter->tx_work_limit = IGC_DEFAULT_TX_WORK;4920 4921	/* adjust max frame to be at least the size of a standard frame */4922	adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN +4923				VLAN_HLEN;4924	adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;4925 4926	mutex_init(&adapter->nfc_rule_lock);4927	INIT_LIST_HEAD(&adapter->nfc_rule_list);4928	adapter->nfc_rule_count = 0;4929 4930	spin_lock_init(&adapter->stats64_lock);4931	spin_lock_init(&adapter->qbv_tx_lock);4932	/* Assume MSI-X interrupts, will be checked during IRQ allocation */4933	adapter->flags |= IGC_FLAG_HAS_MSIX;4934 4935	igc_init_queue_configuration(adapter);4936 4937	/* This call may decrease the number of queues */4938	if (igc_init_interrupt_scheme(adapter, true)) {4939		netdev_err(netdev, "Unable to allocate memory for queues\n");4940		return -ENOMEM;4941	}4942 4943	/* Explicitly disable IRQ since the NIC can be in any state. */4944	igc_irq_disable(adapter);4945 4946	set_bit(__IGC_DOWN, &adapter->state);4947 4948	return 0;4949}4950 4951/**4952 * igc_up - Open the interface and prepare it to handle traffic4953 * @adapter: board private structure4954 */4955void igc_up(struct igc_adapter *adapter)4956{4957	struct igc_hw *hw = &adapter->hw;4958	int i = 0;4959 4960	/* hardware has been reset, we need to reload some things */4961	igc_configure(adapter);4962 4963	clear_bit(__IGC_DOWN, &adapter->state);4964 4965	for (i = 0; i < adapter->num_q_vectors; i++)4966		napi_enable(&adapter->q_vector[i]->napi);4967 4968	if (adapter->msix_entries)4969		igc_configure_msix(adapter);4970	else4971		igc_assign_vector(adapter->q_vector[0], 0);4972 4973	/* Clear any pending interrupts. */4974	rd32(IGC_ICR);4975	igc_irq_enable(adapter);4976 4977	netif_tx_start_all_queues(adapter->netdev);4978 4979	/* start the watchdog. */4980	hw->mac.get_link_status = true;4981	schedule_work(&adapter->watchdog_task);4982}4983 4984/**4985 * igc_update_stats - Update the board statistics counters4986 * @adapter: board private structure4987 */4988void igc_update_stats(struct igc_adapter *adapter)4989{4990	struct rtnl_link_stats64 *net_stats = &adapter->stats64;4991	struct pci_dev *pdev = adapter->pdev;4992	struct igc_hw *hw = &adapter->hw;4993	u64 _bytes, _packets;4994	u64 bytes, packets;4995	unsigned int start;4996	u32 mpc;4997	int i;4998 4999	/* Prevent stats update while adapter is being reset, or if the pci5000	 * connection is down.5001	 */5002	if (adapter->link_speed == 0)5003		return;5004	if (pci_channel_offline(pdev))5005		return;5006 5007	packets = 0;5008	bytes = 0;5009 5010	rcu_read_lock();5011	for (i = 0; i < adapter->num_rx_queues; i++) {5012		struct igc_ring *ring = adapter->rx_ring[i];5013		u32 rqdpc = rd32(IGC_RQDPC(i));5014 5015		if (hw->mac.type >= igc_i225)5016			wr32(IGC_RQDPC(i), 0);5017 5018		if (rqdpc) {5019			ring->rx_stats.drops += rqdpc;5020			net_stats->rx_fifo_errors += rqdpc;5021		}5022 5023		do {5024			start = u64_stats_fetch_begin(&ring->rx_syncp);5025			_bytes = ring->rx_stats.bytes;5026			_packets = ring->rx_stats.packets;5027		} while (u64_stats_fetch_retry(&ring->rx_syncp, start));5028		bytes += _bytes;5029		packets += _packets;5030	}5031 5032	net_stats->rx_bytes = bytes;5033	net_stats->rx_packets = packets;5034 5035	packets = 0;5036	bytes = 0;5037	for (i = 0; i < adapter->num_tx_queues; i++) {5038		struct igc_ring *ring = adapter->tx_ring[i];5039 5040		do {5041			start = u64_stats_fetch_begin(&ring->tx_syncp);5042			_bytes = ring->tx_stats.bytes;5043			_packets = ring->tx_stats.packets;5044		} while (u64_stats_fetch_retry(&ring->tx_syncp, start));5045		bytes += _bytes;5046		packets += _packets;5047	}5048	net_stats->tx_bytes = bytes;5049	net_stats->tx_packets = packets;5050	rcu_read_unlock();5051 5052	/* read stats registers */5053	adapter->stats.crcerrs += rd32(IGC_CRCERRS);5054	adapter->stats.gprc += rd32(IGC_GPRC);5055	adapter->stats.gorc += rd32(IGC_GORCL);5056	rd32(IGC_GORCH); /* clear GORCL */5057	adapter->stats.bprc += rd32(IGC_BPRC);5058	adapter->stats.mprc += rd32(IGC_MPRC);5059	adapter->stats.roc += rd32(IGC_ROC);5060 5061	adapter->stats.prc64 += rd32(IGC_PRC64);5062	adapter->stats.prc127 += rd32(IGC_PRC127);5063	adapter->stats.prc255 += rd32(IGC_PRC255);5064	adapter->stats.prc511 += rd32(IGC_PRC511);5065	adapter->stats.prc1023 += rd32(IGC_PRC1023);5066	adapter->stats.prc1522 += rd32(IGC_PRC1522);5067	adapter->stats.tlpic += rd32(IGC_TLPIC);5068	adapter->stats.rlpic += rd32(IGC_RLPIC);5069	adapter->stats.hgptc += rd32(IGC_HGPTC);5070 5071	mpc = rd32(IGC_MPC);5072	adapter->stats.mpc += mpc;5073	net_stats->rx_fifo_errors += mpc;5074	adapter->stats.scc += rd32(IGC_SCC);5075	adapter->stats.ecol += rd32(IGC_ECOL);5076	adapter->stats.mcc += rd32(IGC_MCC);5077	adapter->stats.latecol += rd32(IGC_LATECOL);5078	adapter->stats.dc += rd32(IGC_DC);5079	adapter->stats.rlec += rd32(IGC_RLEC);5080	adapter->stats.xonrxc += rd32(IGC_XONRXC);5081	adapter->stats.xontxc += rd32(IGC_XONTXC);5082	adapter->stats.xoffrxc += rd32(IGC_XOFFRXC);5083	adapter->stats.xofftxc += rd32(IGC_XOFFTXC);5084	adapter->stats.fcruc += rd32(IGC_FCRUC);5085	adapter->stats.gptc += rd32(IGC_GPTC);5086	adapter->stats.gotc += rd32(IGC_GOTCL);5087	rd32(IGC_GOTCH); /* clear GOTCL */5088	adapter->stats.rnbc += rd32(IGC_RNBC);5089	adapter->stats.ruc += rd32(IGC_RUC);5090	adapter->stats.rfc += rd32(IGC_RFC);5091	adapter->stats.rjc += rd32(IGC_RJC);5092	adapter->stats.tor += rd32(IGC_TORH);5093	adapter->stats.tot += rd32(IGC_TOTH);5094	adapter->stats.tpr += rd32(IGC_TPR);5095 5096	adapter->stats.ptc64 += rd32(IGC_PTC64);5097	adapter->stats.ptc127 += rd32(IGC_PTC127);5098	adapter->stats.ptc255 += rd32(IGC_PTC255);5099	adapter->stats.ptc511 += rd32(IGC_PTC511);5100	adapter->stats.ptc1023 += rd32(IGC_PTC1023);5101	adapter->stats.ptc1522 += rd32(IGC_PTC1522);5102 5103	adapter->stats.mptc += rd32(IGC_MPTC);5104	adapter->stats.bptc += rd32(IGC_BPTC);5105 5106	adapter->stats.tpt += rd32(IGC_TPT);5107	adapter->stats.colc += rd32(IGC_COLC);5108	adapter->stats.colc += rd32(IGC_RERC);5109 5110	adapter->stats.algnerrc += rd32(IGC_ALGNERRC);5111 5112	adapter->stats.tsctc += rd32(IGC_TSCTC);5113 5114	adapter->stats.iac += rd32(IGC_IAC);5115 5116	/* Fill out the OS statistics structure */5117	net_stats->multicast = adapter->stats.mprc;5118	net_stats->collisions = adapter->stats.colc;5119 5120	/* Rx Errors */5121 5122	/* RLEC on some newer hardware can be incorrect so build5123	 * our own version based on RUC and ROC5124	 */5125	net_stats->rx_errors = adapter->stats.rxerrc +5126		adapter->stats.crcerrs + adapter->stats.algnerrc +5127		adapter->stats.ruc + adapter->stats.roc +5128		adapter->stats.cexterr;5129	net_stats->rx_length_errors = adapter->stats.ruc +5130				      adapter->stats.roc;5131	net_stats->rx_crc_errors = adapter->stats.crcerrs;5132	net_stats->rx_frame_errors = adapter->stats.algnerrc;5133	net_stats->rx_missed_errors = adapter->stats.mpc;5134 5135	/* Tx Errors */5136	net_stats->tx_errors = adapter->stats.ecol +5137			       adapter->stats.latecol;5138	net_stats->tx_aborted_errors = adapter->stats.ecol;5139	net_stats->tx_window_errors = adapter->stats.latecol;5140	net_stats->tx_carrier_errors = adapter->stats.tncrs;5141 5142	/* Tx Dropped */5143	net_stats->tx_dropped = adapter->stats.txdrop;5144 5145	/* Management Stats */5146	adapter->stats.mgptc += rd32(IGC_MGTPTC);5147	adapter->stats.mgprc += rd32(IGC_MGTPRC);5148	adapter->stats.mgpdc += rd32(IGC_MGTPDC);5149}5150 5151/**5152 * igc_down - Close the interface5153 * @adapter: board private structure5154 */5155void igc_down(struct igc_adapter *adapter)5156{5157	struct net_device *netdev = adapter->netdev;5158	struct igc_hw *hw = &adapter->hw;5159	u32 tctl, rctl;5160	int i = 0;5161 5162	set_bit(__IGC_DOWN, &adapter->state);5163 5164	igc_ptp_suspend(adapter);5165 5166	if (pci_device_is_present(adapter->pdev)) {5167		/* disable receives in the hardware */5168		rctl = rd32(IGC_RCTL);5169		wr32(IGC_RCTL, rctl & ~IGC_RCTL_EN);5170		/* flush and sleep below */5171	}5172	/* set trans_start so we don't get spurious watchdogs during reset */5173	netif_trans_update(netdev);5174 5175	netif_carrier_off(netdev);5176	netif_tx_stop_all_queues(netdev);5177 5178	if (pci_device_is_present(adapter->pdev)) {5179		/* disable transmits in the hardware */5180		tctl = rd32(IGC_TCTL);5181		tctl &= ~IGC_TCTL_EN;5182		wr32(IGC_TCTL, tctl);5183		/* flush both disables and wait for them to finish */5184		wrfl();5185		usleep_range(10000, 20000);5186 5187		igc_irq_disable(adapter);5188	}5189 5190	adapter->flags &= ~IGC_FLAG_NEED_LINK_UPDATE;5191 5192	for (i = 0; i < adapter->num_q_vectors; i++) {5193		if (adapter->q_vector[i]) {5194			napi_synchronize(&adapter->q_vector[i]->napi);5195			napi_disable(&adapter->q_vector[i]->napi);5196		}5197	}5198 5199	del_timer_sync(&adapter->watchdog_timer);5200	del_timer_sync(&adapter->phy_info_timer);5201 5202	/* record the stats before reset*/5203	spin_lock(&adapter->stats64_lock);5204	igc_update_stats(adapter);5205	spin_unlock(&adapter->stats64_lock);5206 5207	adapter->link_speed = 0;5208	adapter->link_duplex = 0;5209 5210	if (!pci_channel_offline(adapter->pdev))5211		igc_reset(adapter);5212 5213	/* clear VLAN promisc flag so VFTA will be updated if necessary */5214	adapter->flags &= ~IGC_FLAG_VLAN_PROMISC;5215 5216	igc_disable_all_tx_rings_hw(adapter);5217	igc_clean_all_tx_rings(adapter);5218	igc_clean_all_rx_rings(adapter);5219}5220 5221void igc_reinit_locked(struct igc_adapter *adapter)5222{5223	while (test_and_set_bit(__IGC_RESETTING, &adapter->state))5224		usleep_range(1000, 2000);5225	igc_down(adapter);5226	igc_up(adapter);5227	clear_bit(__IGC_RESETTING, &adapter->state);5228}5229 5230static void igc_reset_task(struct work_struct *work)5231{5232	struct igc_adapter *adapter;5233 5234	adapter = container_of(work, struct igc_adapter, reset_task);5235 5236	rtnl_lock();5237	/* If we're already down or resetting, just bail */5238	if (test_bit(__IGC_DOWN, &adapter->state) ||5239	    test_bit(__IGC_RESETTING, &adapter->state)) {5240		rtnl_unlock();5241		return;5242	}5243 5244	igc_rings_dump(adapter);5245	igc_regs_dump(adapter);5246	netdev_err(adapter->netdev, "Reset adapter\n");5247	igc_reinit_locked(adapter);5248	rtnl_unlock();5249}5250 5251/**5252 * igc_change_mtu - Change the Maximum Transfer Unit5253 * @netdev: network interface device structure5254 * @new_mtu: new value for maximum frame size5255 *5256 * Returns 0 on success, negative on failure5257 */5258static int igc_change_mtu(struct net_device *netdev, int new_mtu)5259{5260	int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;5261	struct igc_adapter *adapter = netdev_priv(netdev);5262 5263	if (igc_xdp_is_enabled(adapter) && new_mtu > ETH_DATA_LEN) {5264		netdev_dbg(netdev, "Jumbo frames not supported with XDP");5265		return -EINVAL;5266	}5267 5268	/* adjust max frame to be at least the size of a standard frame */5269	if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))5270		max_frame = ETH_FRAME_LEN + ETH_FCS_LEN;5271 5272	while (test_and_set_bit(__IGC_RESETTING, &adapter->state))5273		usleep_range(1000, 2000);5274 5275	/* igc_down has a dependency on max_frame_size */5276	adapter->max_frame_size = max_frame;5277 5278	if (netif_running(netdev))5279		igc_down(adapter);5280 5281	netdev_dbg(netdev, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);5282	WRITE_ONCE(netdev->mtu, new_mtu);5283 5284	if (netif_running(netdev))5285		igc_up(adapter);5286	else5287		igc_reset(adapter);5288 5289	clear_bit(__IGC_RESETTING, &adapter->state);5290 5291	return 0;5292}5293 5294/**5295 * igc_tx_timeout - Respond to a Tx Hang5296 * @netdev: network interface device structure5297 * @txqueue: queue number that timed out5298 **/5299static void igc_tx_timeout(struct net_device *netdev,5300			   unsigned int __always_unused txqueue)5301{5302	struct igc_adapter *adapter = netdev_priv(netdev);5303	struct igc_hw *hw = &adapter->hw;5304 5305	/* Do the reset outside of interrupt context */5306	adapter->tx_timeout_count++;5307	schedule_work(&adapter->reset_task);5308	wr32(IGC_EICS,5309	     (adapter->eims_enable_mask & ~adapter->eims_other));5310}5311 5312/**5313 * igc_get_stats64 - Get System Network Statistics5314 * @netdev: network interface device structure5315 * @stats: rtnl_link_stats64 pointer5316 *5317 * Returns the address of the device statistics structure.5318 * The statistics are updated here and also from the timer callback.5319 */5320static void igc_get_stats64(struct net_device *netdev,5321			    struct rtnl_link_stats64 *stats)5322{5323	struct igc_adapter *adapter = netdev_priv(netdev);5324 5325	spin_lock(&adapter->stats64_lock);5326	if (!test_bit(__IGC_RESETTING, &adapter->state))5327		igc_update_stats(adapter);5328	memcpy(stats, &adapter->stats64, sizeof(*stats));5329	spin_unlock(&adapter->stats64_lock);5330}5331 5332static netdev_features_t igc_fix_features(struct net_device *netdev,5333					  netdev_features_t features)5334{5335	/* Since there is no support for separate Rx/Tx vlan accel5336	 * enable/disable make sure Tx flag is always in same state as Rx.5337	 */5338	if (features & NETIF_F_HW_VLAN_CTAG_RX)5339		features |= NETIF_F_HW_VLAN_CTAG_TX;5340	else5341		features &= ~NETIF_F_HW_VLAN_CTAG_TX;5342 5343	return features;5344}5345 5346static int igc_set_features(struct net_device *netdev,5347			    netdev_features_t features)5348{5349	netdev_features_t changed = netdev->features ^ features;5350	struct igc_adapter *adapter = netdev_priv(netdev);5351 5352	if (changed & NETIF_F_HW_VLAN_CTAG_RX)5353		igc_vlan_mode(netdev, features);5354 5355	/* Add VLAN support */5356	if (!(changed & (NETIF_F_RXALL | NETIF_F_NTUPLE)))5357		return 0;5358 5359	if (!(features & NETIF_F_NTUPLE))5360		igc_flush_nfc_rules(adapter);5361 5362	netdev->features = features;5363 5364	if (netif_running(netdev))5365		igc_reinit_locked(adapter);5366	else5367		igc_reset(adapter);5368 5369	return 1;5370}5371 5372static netdev_features_t5373igc_features_check(struct sk_buff *skb, struct net_device *dev,5374		   netdev_features_t features)5375{5376	unsigned int network_hdr_len, mac_hdr_len;5377 5378	/* Make certain the headers can be described by a context descriptor */5379	mac_hdr_len = skb_network_offset(skb);5380	if (unlikely(mac_hdr_len > IGC_MAX_MAC_HDR_LEN))5381		return features & ~(NETIF_F_HW_CSUM |5382				    NETIF_F_SCTP_CRC |5383				    NETIF_F_HW_VLAN_CTAG_TX |5384				    NETIF_F_TSO |5385				    NETIF_F_TSO6);5386 5387	network_hdr_len = skb_checksum_start(skb) - skb_network_header(skb);5388	if (unlikely(network_hdr_len >  IGC_MAX_NETWORK_HDR_LEN))5389		return features & ~(NETIF_F_HW_CSUM |5390				    NETIF_F_SCTP_CRC |5391				    NETIF_F_TSO |5392				    NETIF_F_TSO6);5393 5394	/* We can only support IPv4 TSO in tunnels if we can mangle the5395	 * inner IP ID field, so strip TSO if MANGLEID is not supported.5396	 */5397	if (skb->encapsulation && !(features & NETIF_F_TSO_MANGLEID))5398		features &= ~NETIF_F_TSO;5399 5400	return features;5401}5402 5403static void igc_tsync_interrupt(struct igc_adapter *adapter)5404{5405	struct igc_hw *hw = &adapter->hw;5406	u32 tsauxc, sec, nsec, tsicr;5407	struct ptp_clock_event event;5408	struct timespec64 ts;5409 5410	tsicr = rd32(IGC_TSICR);5411 5412	if (tsicr & IGC_TSICR_SYS_WRAP) {5413		event.type = PTP_CLOCK_PPS;5414		if (adapter->ptp_caps.pps)5415			ptp_clock_event(adapter->ptp_clock, &event);5416	}5417 5418	if (tsicr & IGC_TSICR_TXTS) {5419		/* retrieve hardware timestamp */5420		igc_ptp_tx_tstamp_event(adapter);5421	}5422 5423	if (tsicr & IGC_TSICR_TT0) {5424		spin_lock(&adapter->tmreg_lock);5425		ts = timespec64_add(adapter->perout[0].start,5426				    adapter->perout[0].period);5427		wr32(IGC_TRGTTIML0, ts.tv_nsec | IGC_TT_IO_TIMER_SEL_SYSTIM0);5428		wr32(IGC_TRGTTIMH0, (u32)ts.tv_sec);5429		tsauxc = rd32(IGC_TSAUXC);5430		tsauxc |= IGC_TSAUXC_EN_TT0;5431		wr32(IGC_TSAUXC, tsauxc);5432		adapter->perout[0].start = ts;5433		spin_unlock(&adapter->tmreg_lock);5434	}5435 5436	if (tsicr & IGC_TSICR_TT1) {5437		spin_lock(&adapter->tmreg_lock);5438		ts = timespec64_add(adapter->perout[1].start,5439				    adapter->perout[1].period);5440		wr32(IGC_TRGTTIML1, ts.tv_nsec | IGC_TT_IO_TIMER_SEL_SYSTIM0);5441		wr32(IGC_TRGTTIMH1, (u32)ts.tv_sec);5442		tsauxc = rd32(IGC_TSAUXC);5443		tsauxc |= IGC_TSAUXC_EN_TT1;5444		wr32(IGC_TSAUXC, tsauxc);5445		adapter->perout[1].start = ts;5446		spin_unlock(&adapter->tmreg_lock);5447	}5448 5449	if (tsicr & IGC_TSICR_AUTT0) {5450		nsec = rd32(IGC_AUXSTMPL0);5451		sec  = rd32(IGC_AUXSTMPH0);5452		event.type = PTP_CLOCK_EXTTS;5453		event.index = 0;5454		event.timestamp = sec * NSEC_PER_SEC + nsec;5455		ptp_clock_event(adapter->ptp_clock, &event);5456	}5457 5458	if (tsicr & IGC_TSICR_AUTT1) {5459		nsec = rd32(IGC_AUXSTMPL1);5460		sec  = rd32(IGC_AUXSTMPH1);5461		event.type = PTP_CLOCK_EXTTS;5462		event.index = 1;5463		event.timestamp = sec * NSEC_PER_SEC + nsec;5464		ptp_clock_event(adapter->ptp_clock, &event);5465	}5466}5467 5468/**5469 * igc_msix_other - msix other interrupt handler5470 * @irq: interrupt number5471 * @data: pointer to a q_vector5472 */5473static irqreturn_t igc_msix_other(int irq, void *data)5474{5475	struct igc_adapter *adapter = data;5476	struct igc_hw *hw = &adapter->hw;5477	u32 icr = rd32(IGC_ICR);5478 5479	/* reading ICR causes bit 31 of EICR to be cleared */5480	if (icr & IGC_ICR_DRSTA)5481		schedule_work(&adapter->reset_task);5482 5483	if (icr & IGC_ICR_DOUTSYNC) {5484		/* HW is reporting DMA is out of sync */5485		adapter->stats.doosync++;5486	}5487 5488	if (icr & IGC_ICR_LSC) {5489		hw->mac.get_link_status = true;5490		/* guard against interrupt when we're going down */5491		if (!test_bit(__IGC_DOWN, &adapter->state))5492			mod_timer(&adapter->watchdog_timer, jiffies + 1);5493	}5494 5495	if (icr & IGC_ICR_TS)5496		igc_tsync_interrupt(adapter);5497 5498	wr32(IGC_EIMS, adapter->eims_other);5499 5500	return IRQ_HANDLED;5501}5502 5503static void igc_write_itr(struct igc_q_vector *q_vector)5504{5505	u32 itr_val = q_vector->itr_val & IGC_QVECTOR_MASK;5506 5507	if (!q_vector->set_itr)5508		return;5509 5510	if (!itr_val)5511		itr_val = IGC_ITR_VAL_MASK;5512 5513	itr_val |= IGC_EITR_CNT_IGNR;5514 5515	writel(itr_val, q_vector->itr_register);5516	q_vector->set_itr = 0;5517}5518 5519static irqreturn_t igc_msix_ring(int irq, void *data)5520{5521	struct igc_q_vector *q_vector = data;5522 5523	/* Write the ITR value calculated from the previous interrupt. */5524	igc_write_itr(q_vector);5525 5526	napi_schedule(&q_vector->napi);5527 5528	return IRQ_HANDLED;5529}5530 5531/**5532 * igc_request_msix - Initialize MSI-X interrupts5533 * @adapter: Pointer to adapter structure5534 *5535 * igc_request_msix allocates MSI-X vectors and requests interrupts from the5536 * kernel.5537 */5538static int igc_request_msix(struct igc_adapter *adapter)5539{5540	unsigned int num_q_vectors = adapter->num_q_vectors;5541	int i = 0, err = 0, vector = 0, free_vector = 0;5542	struct net_device *netdev = adapter->netdev;5543 5544	err = request_irq(adapter->msix_entries[vector].vector,5545			  &igc_msix_other, 0, netdev->name, adapter);5546	if (err)5547		goto err_out;5548 5549	if (num_q_vectors > MAX_Q_VECTORS) {5550		num_q_vectors = MAX_Q_VECTORS;5551		dev_warn(&adapter->pdev->dev,5552			 "The number of queue vectors (%d) is higher than max allowed (%d)\n",5553			 adapter->num_q_vectors, MAX_Q_VECTORS);5554	}5555	for (i = 0; i < num_q_vectors; i++) {5556		struct igc_q_vector *q_vector = adapter->q_vector[i];5557 5558		vector++;5559 5560		q_vector->itr_register = adapter->io_addr + IGC_EITR(vector);5561 5562		if (q_vector->rx.ring && q_vector->tx.ring)5563			sprintf(q_vector->name, "%s-TxRx-%u", netdev->name,5564				q_vector->rx.ring->queue_index);5565		else if (q_vector->tx.ring)5566			sprintf(q_vector->name, "%s-tx-%u", netdev->name,5567				q_vector->tx.ring->queue_index);5568		else if (q_vector->rx.ring)5569			sprintf(q_vector->name, "%s-rx-%u", netdev->name,5570				q_vector->rx.ring->queue_index);5571		else5572			sprintf(q_vector->name, "%s-unused", netdev->name);5573 5574		err = request_irq(adapter->msix_entries[vector].vector,5575				  igc_msix_ring, 0, q_vector->name,5576				  q_vector);5577		if (err)5578			goto err_free;5579	}5580 5581	igc_configure_msix(adapter);5582	return 0;5583 5584err_free:5585	/* free already assigned IRQs */5586	free_irq(adapter->msix_entries[free_vector++].vector, adapter);5587 5588	vector--;5589	for (i = 0; i < vector; i++) {5590		free_irq(adapter->msix_entries[free_vector++].vector,5591			 adapter->q_vector[i]);5592	}5593err_out:5594	return err;5595}5596 5597/**5598 * igc_clear_interrupt_scheme - reset the device to a state of no interrupts5599 * @adapter: Pointer to adapter structure5600 *5601 * This function resets the device so that it has 0 rx queues, tx queues, and5602 * MSI-X interrupts allocated.5603 */5604static void igc_clear_interrupt_scheme(struct igc_adapter *adapter)5605{5606	igc_free_q_vectors(adapter);5607	igc_reset_interrupt_capability(adapter);5608}5609 5610/* Need to wait a few seconds after link up to get diagnostic information from5611 * the phy5612 */5613static void igc_update_phy_info(struct timer_list *t)5614{5615	struct igc_adapter *adapter = from_timer(adapter, t, phy_info_timer);5616 5617	igc_get_phy_info(&adapter->hw);5618}5619 5620/**5621 * igc_has_link - check shared code for link and determine up/down5622 * @adapter: pointer to driver private info5623 */5624bool igc_has_link(struct igc_adapter *adapter)5625{5626	struct igc_hw *hw = &adapter->hw;5627	bool link_active = false;5628 5629	/* get_link_status is set on LSC (link status) interrupt or5630	 * rx sequence error interrupt.  get_link_status will stay5631	 * false until the igc_check_for_link establishes link5632	 * for copper adapters ONLY5633	 */5634	if (!hw->mac.get_link_status)5635		return true;5636	hw->mac.ops.check_for_link(hw);5637	link_active = !hw->mac.get_link_status;5638 5639	if (hw->mac.type == igc_i225) {5640		if (!netif_carrier_ok(adapter->netdev)) {5641			adapter->flags &= ~IGC_FLAG_NEED_LINK_UPDATE;5642		} else if (!(adapter->flags & IGC_FLAG_NEED_LINK_UPDATE)) {5643			adapter->flags |= IGC_FLAG_NEED_LINK_UPDATE;5644			adapter->link_check_timeout = jiffies;5645		}5646	}5647 5648	return link_active;5649}5650 5651/**5652 * igc_watchdog - Timer Call-back5653 * @t: timer for the watchdog5654 */5655static void igc_watchdog(struct timer_list *t)5656{5657	struct igc_adapter *adapter = from_timer(adapter, t, watchdog_timer);5658	/* Do the rest outside of interrupt context */5659	schedule_work(&adapter->watchdog_task);5660}5661 5662static void igc_watchdog_task(struct work_struct *work)5663{5664	struct igc_adapter *adapter = container_of(work,5665						   struct igc_adapter,5666						   watchdog_task);5667	struct net_device *netdev = adapter->netdev;5668	struct igc_hw *hw = &adapter->hw;5669	struct igc_phy_info *phy = &hw->phy;5670	u16 phy_data, retry_count = 20;5671	u32 link;5672	int i;5673 5674	link = igc_has_link(adapter);5675 5676	if (adapter->flags & IGC_FLAG_NEED_LINK_UPDATE) {5677		if (time_after(jiffies, (adapter->link_check_timeout + HZ)))5678			adapter->flags &= ~IGC_FLAG_NEED_LINK_UPDATE;5679		else5680			link = false;5681	}5682 5683	if (link) {5684		/* Cancel scheduled suspend requests. */5685		pm_runtime_resume(netdev->dev.parent);5686 5687		if (!netif_carrier_ok(netdev)) {5688			u32 ctrl;5689 5690			hw->mac.ops.get_speed_and_duplex(hw,5691							 &adapter->link_speed,5692							 &adapter->link_duplex);5693 5694			ctrl = rd32(IGC_CTRL);5695			/* Link status message must follow this format */5696			netdev_info(netdev,5697				    "NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n",5698				    adapter->link_speed,5699				    adapter->link_duplex == FULL_DUPLEX ?5700				    "Full" : "Half",5701				    (ctrl & IGC_CTRL_TFCE) &&5702				    (ctrl & IGC_CTRL_RFCE) ? "RX/TX" :5703				    (ctrl & IGC_CTRL_RFCE) ?  "RX" :5704				    (ctrl & IGC_CTRL_TFCE) ?  "TX" : "None");5705 5706			/* disable EEE if enabled */5707			if ((adapter->flags & IGC_FLAG_EEE) &&5708			    adapter->link_duplex == HALF_DUPLEX) {5709				netdev_info(netdev,5710					    "EEE Disabled: unsupported at half duplex. Re-enable using ethtool when at full duplex\n");5711				adapter->hw.dev_spec._base.eee_enable = false;5712				adapter->flags &= ~IGC_FLAG_EEE;5713			}5714 5715			/* check if SmartSpeed worked */5716			igc_check_downshift(hw);5717			if (phy->speed_downgraded)5718				netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n");5719 5720			/* adjust timeout factor according to speed/duplex */5721			adapter->tx_timeout_factor = 1;5722			switch (adapter->link_speed) {5723			case SPEED_10:5724				adapter->tx_timeout_factor = 14;5725				break;5726			case SPEED_100:5727			case SPEED_1000:5728			case SPEED_2500:5729				adapter->tx_timeout_factor = 1;5730				break;5731			}5732 5733			/* Once the launch time has been set on the wire, there5734			 * is a delay before the link speed can be determined5735			 * based on link-up activity. Write into the register5736			 * as soon as we know the correct link speed.5737			 */5738			igc_tsn_adjust_txtime_offset(adapter);5739 5740			if (adapter->link_speed != SPEED_1000)5741				goto no_wait;5742 5743			/* wait for Remote receiver status OK */5744retry_read_status:5745			if (!igc_read_phy_reg(hw, PHY_1000T_STATUS,5746					      &phy_data)) {5747				if (!(phy_data & SR_1000T_REMOTE_RX_STATUS) &&5748				    retry_count) {5749					msleep(100);5750					retry_count--;5751					goto retry_read_status;5752				} else if (!retry_count) {5753					netdev_err(netdev, "exceed max 2 second\n");5754				}5755			} else {5756				netdev_err(netdev, "read 1000Base-T Status Reg\n");5757			}5758no_wait:5759			netif_carrier_on(netdev);5760 5761			/* link state has changed, schedule phy info update */5762			if (!test_bit(__IGC_DOWN, &adapter->state))5763				mod_timer(&adapter->phy_info_timer,5764					  round_jiffies(jiffies + 2 * HZ));5765		}5766	} else {5767		if (netif_carrier_ok(netdev)) {5768			adapter->link_speed = 0;5769			adapter->link_duplex = 0;5770 5771			/* Links status message must follow this format */5772			netdev_info(netdev, "NIC Link is Down\n");5773			netif_carrier_off(netdev);5774 5775			/* link state has changed, schedule phy info update */5776			if (!test_bit(__IGC_DOWN, &adapter->state))5777				mod_timer(&adapter->phy_info_timer,5778					  round_jiffies(jiffies + 2 * HZ));5779 5780			pm_schedule_suspend(netdev->dev.parent,5781					    MSEC_PER_SEC * 5);5782		}5783	}5784 5785	spin_lock(&adapter->stats64_lock);5786	igc_update_stats(adapter);5787	spin_unlock(&adapter->stats64_lock);5788 5789	for (i = 0; i < adapter->num_tx_queues; i++) {5790		struct igc_ring *tx_ring = adapter->tx_ring[i];5791 5792		if (!netif_carrier_ok(netdev)) {5793			/* We've lost link, so the controller stops DMA,5794			 * but we've got queued Tx work that's never going5795			 * to get done, so reset controller to flush Tx.5796			 * (Do the reset outside of interrupt context).5797			 */5798			if (igc_desc_unused(tx_ring) + 1 < tx_ring->count) {5799				adapter->tx_timeout_count++;5800				schedule_work(&adapter->reset_task);5801				/* return immediately since reset is imminent */5802				return;5803			}5804		}5805 5806		/* Force detection of hung controller every watchdog period */5807		set_bit(IGC_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);5808	}5809 5810	/* Cause software interrupt to ensure Rx ring is cleaned */5811	if (adapter->flags & IGC_FLAG_HAS_MSIX) {5812		u32 eics = 0;5813 5814		for (i = 0; i < adapter->num_q_vectors; i++) {5815			struct igc_q_vector *q_vector = adapter->q_vector[i];5816			struct igc_ring *rx_ring;5817 5818			if (!q_vector->rx.ring)5819				continue;5820 5821			rx_ring = adapter->rx_ring[q_vector->rx.ring->queue_index];5822 5823			if (test_bit(IGC_RING_FLAG_RX_ALLOC_FAILED, &rx_ring->flags)) {5824				eics |= q_vector->eims_value;5825				clear_bit(IGC_RING_FLAG_RX_ALLOC_FAILED, &rx_ring->flags);5826			}5827		}5828		if (eics)5829			wr32(IGC_EICS, eics);5830	} else {5831		struct igc_ring *rx_ring = adapter->rx_ring[0];5832 5833		if (test_bit(IGC_RING_FLAG_RX_ALLOC_FAILED, &rx_ring->flags)) {5834			clear_bit(IGC_RING_FLAG_RX_ALLOC_FAILED, &rx_ring->flags);5835			wr32(IGC_ICS, IGC_ICS_RXDMT0);5836		}5837	}5838 5839	igc_ptp_tx_hang(adapter);5840 5841	/* Reset the timer */5842	if (!test_bit(__IGC_DOWN, &adapter->state)) {5843		if (adapter->flags & IGC_FLAG_NEED_LINK_UPDATE)5844			mod_timer(&adapter->watchdog_timer,5845				  round_jiffies(jiffies +  HZ));5846		else5847			mod_timer(&adapter->watchdog_timer,5848				  round_jiffies(jiffies + 2 * HZ));5849	}5850}5851 5852/**5853 * igc_intr_msi - Interrupt Handler5854 * @irq: interrupt number5855 * @data: pointer to a network interface device structure5856 */5857static irqreturn_t igc_intr_msi(int irq, void *data)5858{5859	struct igc_adapter *adapter = data;5860	struct igc_q_vector *q_vector = adapter->q_vector[0];5861	struct igc_hw *hw = &adapter->hw;5862	/* read ICR disables interrupts using IAM */5863	u32 icr = rd32(IGC_ICR);5864 5865	igc_write_itr(q_vector);5866 5867	if (icr & IGC_ICR_DRSTA)5868		schedule_work(&adapter->reset_task);5869 5870	if (icr & IGC_ICR_DOUTSYNC) {5871		/* HW is reporting DMA is out of sync */5872		adapter->stats.doosync++;5873	}5874 5875	if (icr & (IGC_ICR_RXSEQ | IGC_ICR_LSC)) {5876		hw->mac.get_link_status = true;5877		if (!test_bit(__IGC_DOWN, &adapter->state))5878			mod_timer(&adapter->watchdog_timer, jiffies + 1);5879	}5880 5881	if (icr & IGC_ICR_TS)5882		igc_tsync_interrupt(adapter);5883 5884	napi_schedule(&q_vector->napi);5885 5886	return IRQ_HANDLED;5887}5888 5889/**5890 * igc_intr - Legacy Interrupt Handler5891 * @irq: interrupt number5892 * @data: pointer to a network interface device structure5893 */5894static irqreturn_t igc_intr(int irq, void *data)5895{5896	struct igc_adapter *adapter = data;5897	struct igc_q_vector *q_vector = adapter->q_vector[0];5898	struct igc_hw *hw = &adapter->hw;5899	/* Interrupt Auto-Mask...upon reading ICR, interrupts are masked.  No5900	 * need for the IMC write5901	 */5902	u32 icr = rd32(IGC_ICR);5903 5904	/* IMS will not auto-mask if INT_ASSERTED is not set, and if it is5905	 * not set, then the adapter didn't send an interrupt5906	 */5907	if (!(icr & IGC_ICR_INT_ASSERTED))5908		return IRQ_NONE;5909 5910	igc_write_itr(q_vector);5911 5912	if (icr & IGC_ICR_DRSTA)5913		schedule_work(&adapter->reset_task);5914 5915	if (icr & IGC_ICR_DOUTSYNC) {5916		/* HW is reporting DMA is out of sync */5917		adapter->stats.doosync++;5918	}5919 5920	if (icr & (IGC_ICR_RXSEQ | IGC_ICR_LSC)) {5921		hw->mac.get_link_status = true;5922		/* guard against interrupt when we're going down */5923		if (!test_bit(__IGC_DOWN, &adapter->state))5924			mod_timer(&adapter->watchdog_timer, jiffies + 1);5925	}5926 5927	if (icr & IGC_ICR_TS)5928		igc_tsync_interrupt(adapter);5929 5930	napi_schedule(&q_vector->napi);5931 5932	return IRQ_HANDLED;5933}5934 5935static void igc_free_irq(struct igc_adapter *adapter)5936{5937	if (adapter->msix_entries) {5938		int vector = 0, i;5939 5940		free_irq(adapter->msix_entries[vector++].vector, adapter);5941 5942		for (i = 0; i < adapter->num_q_vectors; i++)5943			free_irq(adapter->msix_entries[vector++].vector,5944				 adapter->q_vector[i]);5945	} else {5946		free_irq(adapter->pdev->irq, adapter);5947	}5948}5949 5950/**5951 * igc_request_irq - initialize interrupts5952 * @adapter: Pointer to adapter structure5953 *5954 * Attempts to configure interrupts using the best available5955 * capabilities of the hardware and kernel.5956 */5957static int igc_request_irq(struct igc_adapter *adapter)5958{5959	struct net_device *netdev = adapter->netdev;5960	struct pci_dev *pdev = adapter->pdev;5961	int err = 0;5962 5963	if (adapter->flags & IGC_FLAG_HAS_MSIX) {5964		err = igc_request_msix(adapter);5965		if (!err)5966			goto request_done;5967		/* fall back to MSI */5968		igc_free_all_tx_resources(adapter);5969		igc_free_all_rx_resources(adapter);5970 5971		igc_clear_interrupt_scheme(adapter);5972		err = igc_init_interrupt_scheme(adapter, false);5973		if (err)5974			goto request_done;5975		igc_setup_all_tx_resources(adapter);5976		igc_setup_all_rx_resources(adapter);5977		igc_configure(adapter);5978	}5979 5980	igc_assign_vector(adapter->q_vector[0], 0);5981 5982	if (adapter->flags & IGC_FLAG_HAS_MSI) {5983		err = request_irq(pdev->irq, &igc_intr_msi, 0,5984				  netdev->name, adapter);5985		if (!err)5986			goto request_done;5987 5988		/* fall back to legacy interrupts */5989		igc_reset_interrupt_capability(adapter);5990		adapter->flags &= ~IGC_FLAG_HAS_MSI;5991	}5992 5993	err = request_irq(pdev->irq, &igc_intr, IRQF_SHARED,5994			  netdev->name, adapter);5995 5996	if (err)5997		netdev_err(netdev, "Error %d getting interrupt\n", err);5998 5999request_done:6000	return err;6001}6002 6003/**6004 * __igc_open - Called when a network interface is made active6005 * @netdev: network interface device structure6006 * @resuming: boolean indicating if the device is resuming6007 *6008 * Returns 0 on success, negative value on failure6009 *6010 * The open entry point is called when a network interface is made6011 * active by the system (IFF_UP).  At this point all resources needed6012 * for transmit and receive operations are allocated, the interrupt6013 * handler is registered with the OS, the watchdog timer is started,6014 * and the stack is notified that the interface is ready.6015 */6016static int __igc_open(struct net_device *netdev, bool resuming)6017{6018	struct igc_adapter *adapter = netdev_priv(netdev);6019	struct pci_dev *pdev = adapter->pdev;6020	struct igc_hw *hw = &adapter->hw;6021	int err = 0;6022	int i = 0;6023 6024	/* disallow open during test */6025 6026	if (test_bit(__IGC_TESTING, &adapter->state)) {6027		WARN_ON(resuming);6028		return -EBUSY;6029	}6030 6031	if (!resuming)6032		pm_runtime_get_sync(&pdev->dev);6033 6034	netif_carrier_off(netdev);6035 6036	/* allocate transmit descriptors */6037	err = igc_setup_all_tx_resources(adapter);6038	if (err)6039		goto err_setup_tx;6040 6041	/* allocate receive descriptors */6042	err = igc_setup_all_rx_resources(adapter);6043	if (err)6044		goto err_setup_rx;6045 6046	igc_power_up_link(adapter);6047 6048	igc_configure(adapter);6049 6050	err = igc_request_irq(adapter);6051	if (err)6052		goto err_req_irq;6053 6054	clear_bit(__IGC_DOWN, &adapter->state);6055 6056	for (i = 0; i < adapter->num_q_vectors; i++)6057		napi_enable(&adapter->q_vector[i]->napi);6058 6059	/* Clear any pending interrupts. */6060	rd32(IGC_ICR);6061	igc_irq_enable(adapter);6062 6063	if (!resuming)6064		pm_runtime_put(&pdev->dev);6065 6066	netif_tx_start_all_queues(netdev);6067 6068	/* start the watchdog. */6069	hw->mac.get_link_status = true;6070	schedule_work(&adapter->watchdog_task);6071 6072	return IGC_SUCCESS;6073 6074err_req_irq:6075	igc_release_hw_control(adapter);6076	igc_power_down_phy_copper_base(&adapter->hw);6077	igc_free_all_rx_resources(adapter);6078err_setup_rx:6079	igc_free_all_tx_resources(adapter);6080err_setup_tx:6081	igc_reset(adapter);6082	if (!resuming)6083		pm_runtime_put(&pdev->dev);6084 6085	return err;6086}6087 6088int igc_open(struct net_device *netdev)6089{6090	struct igc_adapter *adapter = netdev_priv(netdev);6091	int err;6092 6093	/* Notify the stack of the actual queue counts. */6094	err = netif_set_real_num_queues(netdev, adapter->num_tx_queues,6095					adapter->num_rx_queues);6096	if (err) {6097		netdev_err(netdev, "error setting real queue count\n");6098		return err;6099	}6100 6101	return __igc_open(netdev, false);6102}6103 6104/**6105 * __igc_close - Disables a network interface6106 * @netdev: network interface device structure6107 * @suspending: boolean indicating the device is suspending6108 *6109 * Returns 0, this is not allowed to fail6110 *6111 * The close entry point is called when an interface is de-activated6112 * by the OS.  The hardware is still under the driver's control, but6113 * needs to be disabled.  A global MAC reset is issued to stop the6114 * hardware, and all transmit and receive resources are freed.6115 */6116static int __igc_close(struct net_device *netdev, bool suspending)6117{6118	struct igc_adapter *adapter = netdev_priv(netdev);6119	struct pci_dev *pdev = adapter->pdev;6120 6121	WARN_ON(test_bit(__IGC_RESETTING, &adapter->state));6122 6123	if (!suspending)6124		pm_runtime_get_sync(&pdev->dev);6125 6126	igc_down(adapter);6127 6128	igc_release_hw_control(adapter);6129 6130	igc_free_irq(adapter);6131 6132	igc_free_all_tx_resources(adapter);6133	igc_free_all_rx_resources(adapter);6134 6135	if (!suspending)6136		pm_runtime_put_sync(&pdev->dev);6137 6138	return 0;6139}6140 6141int igc_close(struct net_device *netdev)6142{6143	if (netif_device_present(netdev) || netdev->dismantle)6144		return __igc_close(netdev, false);6145	return 0;6146}6147 6148/**6149 * igc_ioctl - Access the hwtstamp interface6150 * @netdev: network interface device structure6151 * @ifr: interface request data6152 * @cmd: ioctl command6153 **/6154static int igc_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)6155{6156	switch (cmd) {6157	case SIOCGHWTSTAMP:6158		return igc_ptp_get_ts_config(netdev, ifr);6159	case SIOCSHWTSTAMP:6160		return igc_ptp_set_ts_config(netdev, ifr);6161	default:6162		return -EOPNOTSUPP;6163	}6164}6165 6166static int igc_save_launchtime_params(struct igc_adapter *adapter, int queue,6167				      bool enable)6168{6169	struct igc_ring *ring;6170 6171	if (queue < 0 || queue >= adapter->num_tx_queues)6172		return -EINVAL;6173 6174	ring = adapter->tx_ring[queue];6175	ring->launchtime_enable = enable;6176 6177	return 0;6178}6179 6180static bool is_base_time_past(ktime_t base_time, const struct timespec64 *now)6181{6182	struct timespec64 b;6183 6184	b = ktime_to_timespec64(base_time);6185 6186	return timespec64_compare(now, &b) > 0;6187}6188 6189static bool validate_schedule(struct igc_adapter *adapter,6190			      const struct tc_taprio_qopt_offload *qopt)6191{6192	int queue_uses[IGC_MAX_TX_QUEUES] = { };6193	struct igc_hw *hw = &adapter->hw;6194	struct timespec64 now;6195	size_t n;6196 6197	if (qopt->cycle_time_extension)6198		return false;6199 6200	igc_ptp_read(adapter, &now);6201 6202	/* If we program the controller's BASET registers with a time6203	 * in the future, it will hold all the packets until that6204	 * time, causing a lot of TX Hangs, so to avoid that, we6205	 * reject schedules that would start in the future.6206	 * Note: Limitation above is no longer in i226.6207	 */6208	if (!is_base_time_past(qopt->base_time, &now) &&6209	    igc_is_device_id_i225(hw))6210		return false;6211 6212	for (n = 0; n < qopt->num_entries; n++) {6213		const struct tc_taprio_sched_entry *e, *prev;6214		int i;6215 6216		prev = n ? &qopt->entries[n - 1] : NULL;6217		e = &qopt->entries[n];6218 6219		/* i225 only supports "global" frame preemption6220		 * settings.6221		 */6222		if (e->command != TC_TAPRIO_CMD_SET_GATES)6223			return false;6224 6225		for (i = 0; i < adapter->num_tx_queues; i++)6226			if (e->gate_mask & BIT(i)) {6227				queue_uses[i]++;6228 6229				/* There are limitations: A single queue cannot6230				 * be opened and closed multiple times per cycle6231				 * unless the gate stays open. Check for it.6232				 */6233				if (queue_uses[i] > 1 &&6234				    !(prev->gate_mask & BIT(i)))6235					return false;6236			}6237	}6238 6239	return true;6240}6241 6242static int igc_tsn_enable_launchtime(struct igc_adapter *adapter,6243				     struct tc_etf_qopt_offload *qopt)6244{6245	struct igc_hw *hw = &adapter->hw;6246	int err;6247 6248	if (hw->mac.type != igc_i225)6249		return -EOPNOTSUPP;6250 6251	err = igc_save_launchtime_params(adapter, qopt->queue, qopt->enable);6252	if (err)6253		return err;6254 6255	return igc_tsn_offload_apply(adapter);6256}6257 6258static int igc_qbv_clear_schedule(struct igc_adapter *adapter)6259{6260	unsigned long flags;6261	int i;6262 6263	adapter->base_time = 0;6264	adapter->cycle_time = NSEC_PER_SEC;6265	adapter->taprio_offload_enable = false;6266	adapter->qbv_config_change_errors = 0;6267	adapter->qbv_count = 0;6268 6269	for (i = 0; i < adapter->num_tx_queues; i++) {6270		struct igc_ring *ring = adapter->tx_ring[i];6271 6272		ring->start_time = 0;6273		ring->end_time = NSEC_PER_SEC;6274		ring->max_sdu = 0;6275	}6276 6277	spin_lock_irqsave(&adapter->qbv_tx_lock, flags);6278 6279	adapter->qbv_transition = false;6280 6281	for (i = 0; i < adapter->num_tx_queues; i++) {6282		struct igc_ring *ring = adapter->tx_ring[i];6283 6284		ring->oper_gate_closed = false;6285		ring->admin_gate_closed = false;6286	}6287 6288	spin_unlock_irqrestore(&adapter->qbv_tx_lock, flags);6289 6290	return 0;6291}6292 6293static int igc_tsn_clear_schedule(struct igc_adapter *adapter)6294{6295	igc_qbv_clear_schedule(adapter);6296 6297	return 0;6298}6299 6300static void igc_taprio_stats(struct net_device *dev,6301			     struct tc_taprio_qopt_stats *stats)6302{6303	/* When Strict_End is enabled, the tx_overruns counter6304	 * will always be zero.6305	 */6306	stats->tx_overruns = 0;6307}6308 6309static void igc_taprio_queue_stats(struct net_device *dev,6310				   struct tc_taprio_qopt_queue_stats *queue_stats)6311{6312	struct tc_taprio_qopt_stats *stats = &queue_stats->stats;6313 6314	/* When Strict_End is enabled, the tx_overruns counter6315	 * will always be zero.6316	 */6317	stats->tx_overruns = 0;6318}6319 6320static int igc_save_qbv_schedule(struct igc_adapter *adapter,6321				 struct tc_taprio_qopt_offload *qopt)6322{6323	bool queue_configured[IGC_MAX_TX_QUEUES] = { };6324	struct igc_hw *hw = &adapter->hw;6325	u32 start_time = 0, end_time = 0;6326	struct timespec64 now;6327	unsigned long flags;6328	size_t n;6329	int i;6330 6331	if (qopt->base_time < 0)6332		return -ERANGE;6333 6334	if (igc_is_device_id_i225(hw) && adapter->taprio_offload_enable)6335		return -EALREADY;6336 6337	if (!validate_schedule(adapter, qopt))6338		return -EINVAL;6339 6340	igc_ptp_read(adapter, &now);6341 6342	if (igc_tsn_is_taprio_activated_by_user(adapter) &&6343	    is_base_time_past(qopt->base_time, &now))6344		adapter->qbv_config_change_errors++;6345 6346	adapter->cycle_time = qopt->cycle_time;6347	adapter->base_time = qopt->base_time;6348	adapter->taprio_offload_enable = true;6349 6350	for (n = 0; n < qopt->num_entries; n++) {6351		struct tc_taprio_sched_entry *e = &qopt->entries[n];6352 6353		end_time += e->interval;6354 6355		/* If any of the conditions below are true, we need to manually6356		 * control the end time of the cycle.6357		 * 1. Qbv users can specify a cycle time that is not equal6358		 * to the total GCL intervals. Hence, recalculation is6359		 * necessary here to exclude the time interval that6360		 * exceeds the cycle time.6361		 * 2. According to IEEE Std. 802.1Q-2018 section 8.6.9.2,6362		 * once the end of the list is reached, it will switch6363		 * to the END_OF_CYCLE state and leave the gates in the6364		 * same state until the next cycle is started.6365		 */6366		if (end_time > adapter->cycle_time ||6367		    n + 1 == qopt->num_entries)6368			end_time = adapter->cycle_time;6369 6370		for (i = 0; i < adapter->num_tx_queues; i++) {6371			struct igc_ring *ring = adapter->tx_ring[i];6372 6373			if (!(e->gate_mask & BIT(i)))6374				continue;6375 6376			/* Check whether a queue stays open for more than one6377			 * entry. If so, keep the start and advance the end6378			 * time.6379			 */6380			if (!queue_configured[i])6381				ring->start_time = start_time;6382			ring->end_time = end_time;6383 6384			if (ring->start_time >= adapter->cycle_time)6385				queue_configured[i] = false;6386			else6387				queue_configured[i] = true;6388		}6389 6390		start_time += e->interval;6391	}6392 6393	spin_lock_irqsave(&adapter->qbv_tx_lock, flags);6394 6395	/* Check whether a queue gets configured.6396	 * If not, set the start and end time to be end time.6397	 */6398	for (i = 0; i < adapter->num_tx_queues; i++) {6399		struct igc_ring *ring = adapter->tx_ring[i];6400 6401		if (!is_base_time_past(qopt->base_time, &now)) {6402			ring->admin_gate_closed = false;6403		} else {6404			ring->oper_gate_closed = false;6405			ring->admin_gate_closed = false;6406		}6407 6408		if (!queue_configured[i]) {6409			if (!is_base_time_past(qopt->base_time, &now))6410				ring->admin_gate_closed = true;6411			else6412				ring->oper_gate_closed = true;6413 6414			ring->start_time = end_time;6415			ring->end_time = end_time;6416		}6417	}6418 6419	spin_unlock_irqrestore(&adapter->qbv_tx_lock, flags);6420 6421	for (i = 0; i < adapter->num_tx_queues; i++) {6422		struct igc_ring *ring = adapter->tx_ring[i];6423		struct net_device *dev = adapter->netdev;6424 6425		if (qopt->max_sdu[i])6426			ring->max_sdu = qopt->max_sdu[i] + dev->hard_header_len - ETH_TLEN;6427		else6428			ring->max_sdu = 0;6429	}6430 6431	return 0;6432}6433 6434static int igc_tsn_enable_qbv_scheduling(struct igc_adapter *adapter,6435					 struct tc_taprio_qopt_offload *qopt)6436{6437	struct igc_hw *hw = &adapter->hw;6438	int err;6439 6440	if (hw->mac.type != igc_i225)6441		return -EOPNOTSUPP;6442 6443	switch (qopt->cmd) {6444	case TAPRIO_CMD_REPLACE:6445		err = igc_save_qbv_schedule(adapter, qopt);6446		break;6447	case TAPRIO_CMD_DESTROY:6448		err = igc_tsn_clear_schedule(adapter);6449		break;6450	case TAPRIO_CMD_STATS:6451		igc_taprio_stats(adapter->netdev, &qopt->stats);6452		return 0;6453	case TAPRIO_CMD_QUEUE_STATS:6454		igc_taprio_queue_stats(adapter->netdev, &qopt->queue_stats);6455		return 0;6456	default:6457		return -EOPNOTSUPP;6458	}6459 6460	if (err)6461		return err;6462 6463	return igc_tsn_offload_apply(adapter);6464}6465 6466static int igc_save_cbs_params(struct igc_adapter *adapter, int queue,6467			       bool enable, int idleslope, int sendslope,6468			       int hicredit, int locredit)6469{6470	bool cbs_status[IGC_MAX_SR_QUEUES] = { false };6471	struct net_device *netdev = adapter->netdev;6472	struct igc_ring *ring;6473	int i;6474 6475	/* i225 has two sets of credit-based shaper logic.6476	 * Supporting it only on the top two priority queues6477	 */6478	if (queue < 0 || queue > 1)6479		return -EINVAL;6480 6481	ring = adapter->tx_ring[queue];6482 6483	for (i = 0; i < IGC_MAX_SR_QUEUES; i++)6484		if (adapter->tx_ring[i])6485			cbs_status[i] = adapter->tx_ring[i]->cbs_enable;6486 6487	/* CBS should be enabled on the highest priority queue first in order6488	 * for the CBS algorithm to operate as intended.6489	 */6490	if (enable) {6491		if (queue == 1 && !cbs_status[0]) {6492			netdev_err(netdev,6493				   "Enabling CBS on queue1 before queue0\n");6494			return -EINVAL;6495		}6496	} else {6497		if (queue == 0 && cbs_status[1]) {6498			netdev_err(netdev,6499				   "Disabling CBS on queue0 before queue1\n");6500			return -EINVAL;6501		}6502	}6503 6504	ring->cbs_enable = enable;6505	ring->idleslope = idleslope;6506	ring->sendslope = sendslope;6507	ring->hicredit = hicredit;6508	ring->locredit = locredit;6509 6510	return 0;6511}6512 6513static int igc_tsn_enable_cbs(struct igc_adapter *adapter,6514			      struct tc_cbs_qopt_offload *qopt)6515{6516	struct igc_hw *hw = &adapter->hw;6517	int err;6518 6519	if (hw->mac.type != igc_i225)6520		return -EOPNOTSUPP;6521 6522	if (qopt->queue < 0 || qopt->queue > 1)6523		return -EINVAL;6524 6525	err = igc_save_cbs_params(adapter, qopt->queue, qopt->enable,6526				  qopt->idleslope, qopt->sendslope,6527				  qopt->hicredit, qopt->locredit);6528	if (err)6529		return err;6530 6531	return igc_tsn_offload_apply(adapter);6532}6533 6534static int igc_tc_query_caps(struct igc_adapter *adapter,6535			     struct tc_query_caps_base *base)6536{6537	struct igc_hw *hw = &adapter->hw;6538 6539	switch (base->type) {6540	case TC_SETUP_QDISC_MQPRIO: {6541		struct tc_mqprio_caps *caps = base->caps;6542 6543		caps->validate_queue_counts = true;6544 6545		return 0;6546	}6547	case TC_SETUP_QDISC_TAPRIO: {6548		struct tc_taprio_caps *caps = base->caps;6549 6550		caps->broken_mqprio = true;6551 6552		if (hw->mac.type == igc_i225) {6553			caps->supports_queue_max_sdu = true;6554			caps->gate_mask_per_txq = true;6555		}6556 6557		return 0;6558	}6559	default:6560		return -EOPNOTSUPP;6561	}6562}6563 6564static void igc_save_mqprio_params(struct igc_adapter *adapter, u8 num_tc,6565				   u16 *offset)6566{6567	int i;6568 6569	adapter->strict_priority_enable = true;6570	adapter->num_tc = num_tc;6571 6572	for (i = 0; i < num_tc; i++)6573		adapter->queue_per_tc[i] = offset[i];6574}6575 6576static int igc_tsn_enable_mqprio(struct igc_adapter *adapter,6577				 struct tc_mqprio_qopt_offload *mqprio)6578{6579	struct igc_hw *hw = &adapter->hw;6580	int i;6581 6582	if (hw->mac.type != igc_i225)6583		return -EOPNOTSUPP;6584 6585	if (!mqprio->qopt.num_tc) {6586		adapter->strict_priority_enable = false;6587		goto apply;6588	}6589 6590	/* There are as many TCs as Tx queues. */6591	if (mqprio->qopt.num_tc != adapter->num_tx_queues) {6592		NL_SET_ERR_MSG_FMT_MOD(mqprio->extack,6593				       "Only %d traffic classes supported",6594				       adapter->num_tx_queues);6595		return -EOPNOTSUPP;6596	}6597 6598	/* Only one queue per TC is supported. */6599	for (i = 0; i < mqprio->qopt.num_tc; i++) {6600		if (mqprio->qopt.count[i] != 1) {6601			NL_SET_ERR_MSG_MOD(mqprio->extack,6602					   "Only one queue per TC supported");6603			return -EOPNOTSUPP;6604		}6605	}6606 6607	/* Preemption is not supported yet. */6608	if (mqprio->preemptible_tcs) {6609		NL_SET_ERR_MSG_MOD(mqprio->extack,6610				   "Preemption is not supported yet");6611		return -EOPNOTSUPP;6612	}6613 6614	igc_save_mqprio_params(adapter, mqprio->qopt.num_tc,6615			       mqprio->qopt.offset);6616 6617	mqprio->qopt.hw = TC_MQPRIO_HW_OFFLOAD_TCS;6618 6619apply:6620	return igc_tsn_offload_apply(adapter);6621}6622 6623static int igc_setup_tc(struct net_device *dev, enum tc_setup_type type,6624			void *type_data)6625{6626	struct igc_adapter *adapter = netdev_priv(dev);6627 6628	adapter->tc_setup_type = type;6629 6630	switch (type) {6631	case TC_QUERY_CAPS:6632		return igc_tc_query_caps(adapter, type_data);6633	case TC_SETUP_QDISC_TAPRIO:6634		return igc_tsn_enable_qbv_scheduling(adapter, type_data);6635 6636	case TC_SETUP_QDISC_ETF:6637		return igc_tsn_enable_launchtime(adapter, type_data);6638 6639	case TC_SETUP_QDISC_CBS:6640		return igc_tsn_enable_cbs(adapter, type_data);6641 6642	case TC_SETUP_QDISC_MQPRIO:6643		return igc_tsn_enable_mqprio(adapter, type_data);6644 6645	default:6646		return -EOPNOTSUPP;6647	}6648}6649 6650static int igc_bpf(struct net_device *dev, struct netdev_bpf *bpf)6651{6652	struct igc_adapter *adapter = netdev_priv(dev);6653 6654	switch (bpf->command) {6655	case XDP_SETUP_PROG:6656		return igc_xdp_set_prog(adapter, bpf->prog, bpf->extack);6657	case XDP_SETUP_XSK_POOL:6658		return igc_xdp_setup_pool(adapter, bpf->xsk.pool,6659					  bpf->xsk.queue_id);6660	default:6661		return -EOPNOTSUPP;6662	}6663}6664 6665static int igc_xdp_xmit(struct net_device *dev, int num_frames,6666			struct xdp_frame **frames, u32 flags)6667{6668	struct igc_adapter *adapter = netdev_priv(dev);6669	int cpu = smp_processor_id();6670	struct netdev_queue *nq;6671	struct igc_ring *ring;6672	int i, nxmit;6673 6674	if (unlikely(!netif_carrier_ok(dev)))6675		return -ENETDOWN;6676 6677	if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK))6678		return -EINVAL;6679 6680	ring = igc_xdp_get_tx_ring(adapter, cpu);6681	nq = txring_txq(ring);6682 6683	__netif_tx_lock(nq, cpu);6684 6685	/* Avoid transmit queue timeout since we share it with the slow path */6686	txq_trans_cond_update(nq);6687 6688	nxmit = 0;6689	for (i = 0; i < num_frames; i++) {6690		int err;6691		struct xdp_frame *xdpf = frames[i];6692 6693		err = igc_xdp_init_tx_descriptor(ring, xdpf);6694		if (err)6695			break;6696		nxmit++;6697	}6698 6699	if (flags & XDP_XMIT_FLUSH)6700		igc_flush_tx_descriptors(ring);6701 6702	__netif_tx_unlock(nq);6703 6704	return nxmit;6705}6706 6707static void igc_trigger_rxtxq_interrupt(struct igc_adapter *adapter,6708					struct igc_q_vector *q_vector)6709{6710	struct igc_hw *hw = &adapter->hw;6711	u32 eics = 0;6712 6713	eics |= q_vector->eims_value;6714	wr32(IGC_EICS, eics);6715}6716 6717int igc_xsk_wakeup(struct net_device *dev, u32 queue_id, u32 flags)6718{6719	struct igc_adapter *adapter = netdev_priv(dev);6720	struct igc_q_vector *q_vector;6721	struct igc_ring *ring;6722 6723	if (test_bit(__IGC_DOWN, &adapter->state))6724		return -ENETDOWN;6725 6726	if (!igc_xdp_is_enabled(adapter))6727		return -ENXIO;6728 6729	if (queue_id >= adapter->num_rx_queues)6730		return -EINVAL;6731 6732	ring = adapter->rx_ring[queue_id];6733 6734	if (!ring->xsk_pool)6735		return -ENXIO;6736 6737	q_vector = adapter->q_vector[queue_id];6738	if (!napi_if_scheduled_mark_missed(&q_vector->napi))6739		igc_trigger_rxtxq_interrupt(adapter, q_vector);6740 6741	return 0;6742}6743 6744static ktime_t igc_get_tstamp(struct net_device *dev,6745			      const struct skb_shared_hwtstamps *hwtstamps,6746			      bool cycles)6747{6748	struct igc_adapter *adapter = netdev_priv(dev);6749	struct igc_inline_rx_tstamps *tstamp;6750	ktime_t timestamp;6751 6752	tstamp = hwtstamps->netdev_data;6753 6754	if (cycles)6755		timestamp = igc_ptp_rx_pktstamp(adapter, tstamp->timer1);6756	else6757		timestamp = igc_ptp_rx_pktstamp(adapter, tstamp->timer0);6758 6759	return timestamp;6760}6761 6762static const struct net_device_ops igc_netdev_ops = {6763	.ndo_open		= igc_open,6764	.ndo_stop		= igc_close,6765	.ndo_start_xmit		= igc_xmit_frame,6766	.ndo_set_rx_mode	= igc_set_rx_mode,6767	.ndo_set_mac_address	= igc_set_mac,6768	.ndo_change_mtu		= igc_change_mtu,6769	.ndo_tx_timeout		= igc_tx_timeout,6770	.ndo_get_stats64	= igc_get_stats64,6771	.ndo_fix_features	= igc_fix_features,6772	.ndo_set_features	= igc_set_features,6773	.ndo_features_check	= igc_features_check,6774	.ndo_eth_ioctl		= igc_ioctl,6775	.ndo_setup_tc		= igc_setup_tc,6776	.ndo_bpf		= igc_bpf,6777	.ndo_xdp_xmit		= igc_xdp_xmit,6778	.ndo_xsk_wakeup		= igc_xsk_wakeup,6779	.ndo_get_tstamp		= igc_get_tstamp,6780};6781 6782/* PCIe configuration access */6783void igc_read_pci_cfg(struct igc_hw *hw, u32 reg, u16 *value)6784{6785	struct igc_adapter *adapter = hw->back;6786 6787	pci_read_config_word(adapter->pdev, reg, value);6788}6789 6790void igc_write_pci_cfg(struct igc_hw *hw, u32 reg, u16 *value)6791{6792	struct igc_adapter *adapter = hw->back;6793 6794	pci_write_config_word(adapter->pdev, reg, *value);6795}6796 6797s32 igc_read_pcie_cap_reg(struct igc_hw *hw, u32 reg, u16 *value)6798{6799	struct igc_adapter *adapter = hw->back;6800 6801	if (!pci_is_pcie(adapter->pdev))6802		return -IGC_ERR_CONFIG;6803 6804	pcie_capability_read_word(adapter->pdev, reg, value);6805 6806	return IGC_SUCCESS;6807}6808 6809s32 igc_write_pcie_cap_reg(struct igc_hw *hw, u32 reg, u16 *value)6810{6811	struct igc_adapter *adapter = hw->back;6812 6813	if (!pci_is_pcie(adapter->pdev))6814		return -IGC_ERR_CONFIG;6815 6816	pcie_capability_write_word(adapter->pdev, reg, *value);6817 6818	return IGC_SUCCESS;6819}6820 6821u32 igc_rd32(struct igc_hw *hw, u32 reg)6822{6823	struct igc_adapter *igc = container_of(hw, struct igc_adapter, hw);6824	u8 __iomem *hw_addr = READ_ONCE(hw->hw_addr);6825	u32 value = 0;6826 6827	if (IGC_REMOVED(hw_addr))6828		return ~value;6829 6830	value = readl(&hw_addr[reg]);6831 6832	/* reads should not return all F's */6833	if (!(~value) && (!reg || !(~readl(hw_addr)))) {6834		struct net_device *netdev = igc->netdev;6835 6836		hw->hw_addr = NULL;6837		netif_device_detach(netdev);6838		netdev_err(netdev, "PCIe link lost, device now detached\n");6839		WARN(pci_device_is_present(igc->pdev),6840		     "igc: Failed to read reg 0x%x!\n", reg);6841	}6842 6843	return value;6844}6845 6846/* Mapping HW RSS Type to enum xdp_rss_hash_type */6847static enum xdp_rss_hash_type igc_xdp_rss_type[IGC_RSS_TYPE_MAX_TABLE] = {6848	[IGC_RSS_TYPE_NO_HASH]		= XDP_RSS_TYPE_L2,6849	[IGC_RSS_TYPE_HASH_TCP_IPV4]	= XDP_RSS_TYPE_L4_IPV4_TCP,6850	[IGC_RSS_TYPE_HASH_IPV4]	= XDP_RSS_TYPE_L3_IPV4,6851	[IGC_RSS_TYPE_HASH_TCP_IPV6]	= XDP_RSS_TYPE_L4_IPV6_TCP,6852	[IGC_RSS_TYPE_HASH_IPV6_EX]	= XDP_RSS_TYPE_L3_IPV6_EX,6853	[IGC_RSS_TYPE_HASH_IPV6]	= XDP_RSS_TYPE_L3_IPV6,6854	[IGC_RSS_TYPE_HASH_TCP_IPV6_EX] = XDP_RSS_TYPE_L4_IPV6_TCP_EX,6855	[IGC_RSS_TYPE_HASH_UDP_IPV4]	= XDP_RSS_TYPE_L4_IPV4_UDP,6856	[IGC_RSS_TYPE_HASH_UDP_IPV6]	= XDP_RSS_TYPE_L4_IPV6_UDP,6857	[IGC_RSS_TYPE_HASH_UDP_IPV6_EX] = XDP_RSS_TYPE_L4_IPV6_UDP_EX,6858	[10] = XDP_RSS_TYPE_NONE, /* RSS Type above 9 "Reserved" by HW  */6859	[11] = XDP_RSS_TYPE_NONE, /* keep array sized for SW bit-mask   */6860	[12] = XDP_RSS_TYPE_NONE, /* to handle future HW revisons       */6861	[13] = XDP_RSS_TYPE_NONE,6862	[14] = XDP_RSS_TYPE_NONE,6863	[15] = XDP_RSS_TYPE_NONE,6864};6865 6866static int igc_xdp_rx_hash(const struct xdp_md *_ctx, u32 *hash,6867			   enum xdp_rss_hash_type *rss_type)6868{6869	const struct igc_xdp_buff *ctx = (void *)_ctx;6870 6871	if (!(ctx->xdp.rxq->dev->features & NETIF_F_RXHASH))6872		return -ENODATA;6873 6874	*hash = le32_to_cpu(ctx->rx_desc->wb.lower.hi_dword.rss);6875	*rss_type = igc_xdp_rss_type[igc_rss_type(ctx->rx_desc)];6876 6877	return 0;6878}6879 6880static int igc_xdp_rx_timestamp(const struct xdp_md *_ctx, u64 *timestamp)6881{6882	const struct igc_xdp_buff *ctx = (void *)_ctx;6883	struct igc_adapter *adapter = netdev_priv(ctx->xdp.rxq->dev);6884	struct igc_inline_rx_tstamps *tstamp = ctx->rx_ts;6885 6886	if (igc_test_staterr(ctx->rx_desc, IGC_RXDADV_STAT_TSIP)) {6887		*timestamp = igc_ptp_rx_pktstamp(adapter, tstamp->timer0);6888 6889		return 0;6890	}6891 6892	return -ENODATA;6893}6894 6895static const struct xdp_metadata_ops igc_xdp_metadata_ops = {6896	.xmo_rx_hash			= igc_xdp_rx_hash,6897	.xmo_rx_timestamp		= igc_xdp_rx_timestamp,6898};6899 6900static enum hrtimer_restart igc_qbv_scheduling_timer(struct hrtimer *timer)6901{6902	struct igc_adapter *adapter = container_of(timer, struct igc_adapter,6903						   hrtimer);6904	unsigned long flags;6905	unsigned int i;6906 6907	spin_lock_irqsave(&adapter->qbv_tx_lock, flags);6908 6909	adapter->qbv_transition = true;6910	for (i = 0; i < adapter->num_tx_queues; i++) {6911		struct igc_ring *tx_ring = adapter->tx_ring[i];6912 6913		if (tx_ring->admin_gate_closed) {6914			tx_ring->admin_gate_closed = false;6915			tx_ring->oper_gate_closed = true;6916		} else {6917			tx_ring->oper_gate_closed = false;6918		}6919	}6920	adapter->qbv_transition = false;6921 6922	spin_unlock_irqrestore(&adapter->qbv_tx_lock, flags);6923 6924	return HRTIMER_NORESTART;6925}6926 6927/**6928 * igc_probe - Device Initialization Routine6929 * @pdev: PCI device information struct6930 * @ent: entry in igc_pci_tbl6931 *6932 * Returns 0 on success, negative on failure6933 *6934 * igc_probe initializes an adapter identified by a pci_dev structure.6935 * The OS initialization, configuring the adapter private structure,6936 * and a hardware reset occur.6937 */6938static int igc_probe(struct pci_dev *pdev,6939		     const struct pci_device_id *ent)6940{6941	struct igc_adapter *adapter;6942	struct net_device *netdev;6943	struct igc_hw *hw;6944	const struct igc_info *ei = igc_info_tbl[ent->driver_data];6945	int err;6946 6947	err = pci_enable_device_mem(pdev);6948	if (err)6949		return err;6950 6951	err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));6952	if (err) {6953		dev_err(&pdev->dev,6954			"No usable DMA configuration, aborting\n");6955		goto err_dma;6956	}6957 6958	err = pci_request_mem_regions(pdev, igc_driver_name);6959	if (err)6960		goto err_pci_reg;6961 6962	err = pci_enable_ptm(pdev, NULL);6963	if (err < 0)6964		dev_info(&pdev->dev, "PCIe PTM not supported by PCIe bus/controller\n");6965 6966	pci_set_master(pdev);6967 6968	err = -ENOMEM;6969	netdev = alloc_etherdev_mq(sizeof(struct igc_adapter),6970				   IGC_MAX_TX_QUEUES);6971 6972	if (!netdev)6973		goto err_alloc_etherdev;6974 6975	SET_NETDEV_DEV(netdev, &pdev->dev);6976 6977	pci_set_drvdata(pdev, netdev);6978	adapter = netdev_priv(netdev);6979	adapter->netdev = netdev;6980	adapter->pdev = pdev;6981	hw = &adapter->hw;6982	hw->back = adapter;6983	adapter->port_num = hw->bus.func;6984	adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);6985 6986	err = pci_save_state(pdev);6987	if (err)6988		goto err_ioremap;6989 6990	err = -EIO;6991	adapter->io_addr = ioremap(pci_resource_start(pdev, 0),6992				   pci_resource_len(pdev, 0));6993	if (!adapter->io_addr)6994		goto err_ioremap;6995 6996	/* hw->hw_addr can be zeroed, so use adapter->io_addr for unmap */6997	hw->hw_addr = adapter->io_addr;6998 6999	netdev->netdev_ops = &igc_netdev_ops;7000	netdev->xdp_metadata_ops = &igc_xdp_metadata_ops;7001	netdev->xsk_tx_metadata_ops = &igc_xsk_tx_metadata_ops;7002	igc_ethtool_set_ops(netdev);7003	netdev->watchdog_timeo = 5 * HZ;7004 7005	netdev->mem_start = pci_resource_start(pdev, 0);7006	netdev->mem_end = pci_resource_end(pdev, 0);7007 7008	/* PCI config space info */7009	hw->vendor_id = pdev->vendor;7010	hw->device_id = pdev->device;7011	hw->revision_id = pdev->revision;7012	hw->subsystem_vendor_id = pdev->subsystem_vendor;7013	hw->subsystem_device_id = pdev->subsystem_device;7014 7015	/* Copy the default MAC and PHY function pointers */7016	memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));7017	memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));7018 7019	/* Initialize skew-specific constants */7020	err = ei->get_invariants(hw);7021	if (err)7022		goto err_sw_init;7023 7024	/* Add supported features to the features list*/7025	netdev->features |= NETIF_F_SG;7026	netdev->features |= NETIF_F_TSO;7027	netdev->features |= NETIF_F_TSO6;7028	netdev->features |= NETIF_F_TSO_ECN;7029	netdev->features |= NETIF_F_RXHASH;7030	netdev->features |= NETIF_F_RXCSUM;7031	netdev->features |= NETIF_F_HW_CSUM;7032	netdev->features |= NETIF_F_SCTP_CRC;7033	netdev->features |= NETIF_F_HW_TC;7034 7035#define IGC_GSO_PARTIAL_FEATURES (NETIF_F_GSO_GRE | \7036				  NETIF_F_GSO_GRE_CSUM | \7037				  NETIF_F_GSO_IPXIP4 | \7038				  NETIF_F_GSO_IPXIP6 | \7039				  NETIF_F_GSO_UDP_TUNNEL | \7040				  NETIF_F_GSO_UDP_TUNNEL_CSUM)7041 7042	netdev->gso_partial_features = IGC_GSO_PARTIAL_FEATURES;7043	netdev->features |= NETIF_F_GSO_PARTIAL | IGC_GSO_PARTIAL_FEATURES;7044 7045	/* setup the private structure */7046	err = igc_sw_init(adapter);7047	if (err)7048		goto err_sw_init;7049 7050	/* copy netdev features into list of user selectable features */7051	netdev->hw_features |= NETIF_F_NTUPLE;7052	netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX;7053	netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;7054	netdev->hw_features |= netdev->features;7055 7056	netdev->features |= NETIF_F_HIGHDMA;7057 7058	netdev->vlan_features |= netdev->features | NETIF_F_TSO_MANGLEID;7059	netdev->mpls_features |= NETIF_F_HW_CSUM;7060	netdev->hw_enc_features |= netdev->vlan_features;7061 7062	netdev->xdp_features = NETDEV_XDP_ACT_BASIC | NETDEV_XDP_ACT_REDIRECT |7063			       NETDEV_XDP_ACT_XSK_ZEROCOPY;7064 7065	/* MTU range: 68 - 9216 */7066	netdev->min_mtu = ETH_MIN_MTU;7067	netdev->max_mtu = MAX_STD_JUMBO_FRAME_SIZE;7068 7069	/* before reading the NVM, reset the controller to put the device in a7070	 * known good starting state7071	 */7072	hw->mac.ops.reset_hw(hw);7073 7074	if (igc_get_flash_presence_i225(hw)) {7075		if (hw->nvm.ops.validate(hw) < 0) {7076			dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");7077			err = -EIO;7078			goto err_eeprom;7079		}7080	}7081 7082	if (eth_platform_get_mac_address(&pdev->dev, hw->mac.addr)) {7083		/* copy the MAC address out of the NVM */7084		if (hw->mac.ops.read_mac_addr(hw))7085			dev_err(&pdev->dev, "NVM Read Error\n");7086	}7087 7088	eth_hw_addr_set(netdev, hw->mac.addr);7089 7090	if (!is_valid_ether_addr(netdev->dev_addr)) {7091		dev_err(&pdev->dev, "Invalid MAC Address\n");7092		err = -EIO;7093		goto err_eeprom;7094	}7095 7096	/* configure RXPBSIZE and TXPBSIZE */7097	wr32(IGC_RXPBS, I225_RXPBSIZE_DEFAULT);7098	wr32(IGC_TXPBS, I225_TXPBSIZE_DEFAULT);7099 7100	timer_setup(&adapter->watchdog_timer, igc_watchdog, 0);7101	timer_setup(&adapter->phy_info_timer, igc_update_phy_info, 0);7102 7103	INIT_WORK(&adapter->reset_task, igc_reset_task);7104	INIT_WORK(&adapter->watchdog_task, igc_watchdog_task);7105 7106	hrtimer_init(&adapter->hrtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);7107	adapter->hrtimer.function = &igc_qbv_scheduling_timer;7108 7109	/* Initialize link properties that are user-changeable */7110	adapter->fc_autoneg = true;7111	hw->mac.autoneg = true;7112	hw->phy.autoneg_advertised = 0xaf;7113 7114	hw->fc.requested_mode = igc_fc_default;7115	hw->fc.current_mode = igc_fc_default;7116 7117	/* By default, support wake on port A */7118	adapter->flags |= IGC_FLAG_WOL_SUPPORTED;7119 7120	/* initialize the wol settings based on the eeprom settings */7121	if (adapter->flags & IGC_FLAG_WOL_SUPPORTED)7122		adapter->wol |= IGC_WUFC_MAG;7123 7124	device_set_wakeup_enable(&adapter->pdev->dev,7125				 adapter->flags & IGC_FLAG_WOL_SUPPORTED);7126 7127	igc_ptp_init(adapter);7128 7129	igc_tsn_clear_schedule(adapter);7130 7131	/* reset the hardware with the new settings */7132	igc_reset(adapter);7133 7134	/* let the f/w know that the h/w is now under the control of the7135	 * driver.7136	 */7137	igc_get_hw_control(adapter);7138 7139	strscpy(netdev->name, "eth%d", sizeof(netdev->name));7140	err = register_netdev(netdev);7141	if (err)7142		goto err_register;7143 7144	 /* carrier off reporting is important to ethtool even BEFORE open */7145	netif_carrier_off(netdev);7146 7147	/* Check if Media Autosense is enabled */7148	adapter->ei = *ei;7149 7150	/* print pcie link status and MAC address */7151	pcie_print_link_status(pdev);7152	netdev_info(netdev, "MAC: %pM\n", netdev->dev_addr);7153 7154	dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NO_DIRECT_COMPLETE);7155	/* Disable EEE for internal PHY devices */7156	hw->dev_spec._base.eee_enable = false;7157	adapter->flags &= ~IGC_FLAG_EEE;7158	igc_set_eee_i225(hw, false, false, false);7159 7160	pm_runtime_put_noidle(&pdev->dev);7161 7162	if (IS_ENABLED(CONFIG_IGC_LEDS)) {7163		err = igc_led_setup(adapter);7164		if (err)7165			goto err_register;7166	}7167 7168	return 0;7169 7170err_register:7171	igc_release_hw_control(adapter);7172err_eeprom:7173	if (!igc_check_reset_block(hw))7174		igc_reset_phy(hw);7175err_sw_init:7176	igc_clear_interrupt_scheme(adapter);7177	iounmap(adapter->io_addr);7178err_ioremap:7179	free_netdev(netdev);7180err_alloc_etherdev:7181	pci_release_mem_regions(pdev);7182err_pci_reg:7183err_dma:7184	pci_disable_device(pdev);7185	return err;7186}7187 7188/**7189 * igc_remove - Device Removal Routine7190 * @pdev: PCI device information struct7191 *7192 * igc_remove is called by the PCI subsystem to alert the driver7193 * that it should release a PCI device.  This could be caused by a7194 * Hot-Plug event, or because the driver is going to be removed from7195 * memory.7196 */7197static void igc_remove(struct pci_dev *pdev)7198{7199	struct net_device *netdev = pci_get_drvdata(pdev);7200	struct igc_adapter *adapter = netdev_priv(netdev);7201 7202	pm_runtime_get_noresume(&pdev->dev);7203 7204	igc_flush_nfc_rules(adapter);7205 7206	igc_ptp_stop(adapter);7207 7208	pci_disable_ptm(pdev);7209	pci_clear_master(pdev);7210 7211	set_bit(__IGC_DOWN, &adapter->state);7212 7213	del_timer_sync(&adapter->watchdog_timer);7214	del_timer_sync(&adapter->phy_info_timer);7215 7216	cancel_work_sync(&adapter->reset_task);7217	cancel_work_sync(&adapter->watchdog_task);7218	hrtimer_cancel(&adapter->hrtimer);7219 7220	if (IS_ENABLED(CONFIG_IGC_LEDS))7221		igc_led_free(adapter);7222 7223	/* Release control of h/w to f/w.  If f/w is AMT enabled, this7224	 * would have already happened in close and is redundant.7225	 */7226	igc_release_hw_control(adapter);7227	unregister_netdev(netdev);7228 7229	igc_clear_interrupt_scheme(adapter);7230	pci_iounmap(pdev, adapter->io_addr);7231	pci_release_mem_regions(pdev);7232 7233	free_netdev(netdev);7234 7235	pci_disable_device(pdev);7236}7237 7238static int __igc_shutdown(struct pci_dev *pdev, bool *enable_wake,7239			  bool runtime)7240{7241	struct net_device *netdev = pci_get_drvdata(pdev);7242	struct igc_adapter *adapter = netdev_priv(netdev);7243	u32 wufc = runtime ? IGC_WUFC_LNKC : adapter->wol;7244	struct igc_hw *hw = &adapter->hw;7245	u32 ctrl, rctl, status;7246	bool wake;7247 7248	rtnl_lock();7249	netif_device_detach(netdev);7250 7251	if (netif_running(netdev))7252		__igc_close(netdev, true);7253 7254	igc_ptp_suspend(adapter);7255 7256	igc_clear_interrupt_scheme(adapter);7257	rtnl_unlock();7258 7259	status = rd32(IGC_STATUS);7260	if (status & IGC_STATUS_LU)7261		wufc &= ~IGC_WUFC_LNKC;7262 7263	if (wufc) {7264		igc_setup_rctl(adapter);7265		igc_set_rx_mode(netdev);7266 7267		/* turn on all-multi mode if wake on multicast is enabled */7268		if (wufc & IGC_WUFC_MC) {7269			rctl = rd32(IGC_RCTL);7270			rctl |= IGC_RCTL_MPE;7271			wr32(IGC_RCTL, rctl);7272		}7273 7274		ctrl = rd32(IGC_CTRL);7275		ctrl |= IGC_CTRL_ADVD3WUC;7276		wr32(IGC_CTRL, ctrl);7277 7278		/* Allow time for pending master requests to run */7279		igc_disable_pcie_master(hw);7280 7281		wr32(IGC_WUC, IGC_WUC_PME_EN);7282		wr32(IGC_WUFC, wufc);7283	} else {7284		wr32(IGC_WUC, 0);7285		wr32(IGC_WUFC, 0);7286	}7287 7288	wake = wufc || adapter->en_mng_pt;7289	if (!wake)7290		igc_power_down_phy_copper_base(&adapter->hw);7291	else7292		igc_power_up_link(adapter);7293 7294	if (enable_wake)7295		*enable_wake = wake;7296 7297	/* Release control of h/w to f/w.  If f/w is AMT enabled, this7298	 * would have already happened in close and is redundant.7299	 */7300	igc_release_hw_control(adapter);7301 7302	pci_disable_device(pdev);7303 7304	return 0;7305}7306 7307static int igc_runtime_suspend(struct device *dev)7308{7309	return __igc_shutdown(to_pci_dev(dev), NULL, 1);7310}7311 7312static void igc_deliver_wake_packet(struct net_device *netdev)7313{7314	struct igc_adapter *adapter = netdev_priv(netdev);7315	struct igc_hw *hw = &adapter->hw;7316	struct sk_buff *skb;7317	u32 wupl;7318 7319	wupl = rd32(IGC_WUPL) & IGC_WUPL_MASK;7320 7321	/* WUPM stores only the first 128 bytes of the wake packet.7322	 * Read the packet only if we have the whole thing.7323	 */7324	if (wupl == 0 || wupl > IGC_WUPM_BYTES)7325		return;7326 7327	skb = netdev_alloc_skb_ip_align(netdev, IGC_WUPM_BYTES);7328	if (!skb)7329		return;7330 7331	skb_put(skb, wupl);7332 7333	/* Ensure reads are 32-bit aligned */7334	wupl = roundup(wupl, 4);7335 7336	memcpy_fromio(skb->data, hw->hw_addr + IGC_WUPM_REG(0), wupl);7337 7338	skb->protocol = eth_type_trans(skb, netdev);7339	netif_rx(skb);7340}7341 7342static int igc_resume(struct device *dev)7343{7344	struct pci_dev *pdev = to_pci_dev(dev);7345	struct net_device *netdev = pci_get_drvdata(pdev);7346	struct igc_adapter *adapter = netdev_priv(netdev);7347	struct igc_hw *hw = &adapter->hw;7348	u32 err, val;7349 7350	pci_set_power_state(pdev, PCI_D0);7351	pci_restore_state(pdev);7352	pci_save_state(pdev);7353 7354	if (!pci_device_is_present(pdev))7355		return -ENODEV;7356	err = pci_enable_device_mem(pdev);7357	if (err) {7358		netdev_err(netdev, "Cannot enable PCI device from suspend\n");7359		return err;7360	}7361	pci_set_master(pdev);7362 7363	pci_enable_wake(pdev, PCI_D3hot, 0);7364	pci_enable_wake(pdev, PCI_D3cold, 0);7365 7366	if (igc_init_interrupt_scheme(adapter, true)) {7367		netdev_err(netdev, "Unable to allocate memory for queues\n");7368		return -ENOMEM;7369	}7370 7371	igc_reset(adapter);7372 7373	/* let the f/w know that the h/w is now under the control of the7374	 * driver.7375	 */7376	igc_get_hw_control(adapter);7377 7378	val = rd32(IGC_WUS);7379	if (val & WAKE_PKT_WUS)7380		igc_deliver_wake_packet(netdev);7381 7382	wr32(IGC_WUS, ~0);7383 7384	if (netif_running(netdev)) {7385		err = __igc_open(netdev, true);7386		if (!err)7387			netif_device_attach(netdev);7388	}7389 7390	return err;7391}7392 7393static int igc_runtime_resume(struct device *dev)7394{7395	return igc_resume(dev);7396}7397 7398static int igc_suspend(struct device *dev)7399{7400	return __igc_shutdown(to_pci_dev(dev), NULL, 0);7401}7402 7403static int __maybe_unused igc_runtime_idle(struct device *dev)7404{7405	struct net_device *netdev = dev_get_drvdata(dev);7406	struct igc_adapter *adapter = netdev_priv(netdev);7407 7408	if (!igc_has_link(adapter))7409		pm_schedule_suspend(dev, MSEC_PER_SEC * 5);7410 7411	return -EBUSY;7412}7413 7414static void igc_shutdown(struct pci_dev *pdev)7415{7416	bool wake;7417 7418	__igc_shutdown(pdev, &wake, 0);7419 7420	if (system_state == SYSTEM_POWER_OFF) {7421		pci_wake_from_d3(pdev, wake);7422		pci_set_power_state(pdev, PCI_D3hot);7423	}7424}7425 7426/**7427 *  igc_io_error_detected - called when PCI error is detected7428 *  @pdev: Pointer to PCI device7429 *  @state: The current PCI connection state7430 *7431 *  This function is called after a PCI bus error affecting7432 *  this device has been detected.7433 **/7434static pci_ers_result_t igc_io_error_detected(struct pci_dev *pdev,7435					      pci_channel_state_t state)7436{7437	struct net_device *netdev = pci_get_drvdata(pdev);7438	struct igc_adapter *adapter = netdev_priv(netdev);7439 7440	netif_device_detach(netdev);7441 7442	if (state == pci_channel_io_perm_failure)7443		return PCI_ERS_RESULT_DISCONNECT;7444 7445	if (netif_running(netdev))7446		igc_down(adapter);7447	pci_disable_device(pdev);7448 7449	/* Request a slot reset. */7450	return PCI_ERS_RESULT_NEED_RESET;7451}7452 7453/**7454 *  igc_io_slot_reset - called after the PCI bus has been reset.7455 *  @pdev: Pointer to PCI device7456 *7457 *  Restart the card from scratch, as if from a cold-boot. Implementation7458 *  resembles the first-half of the igc_resume routine.7459 **/7460static pci_ers_result_t igc_io_slot_reset(struct pci_dev *pdev)7461{7462	struct net_device *netdev = pci_get_drvdata(pdev);7463	struct igc_adapter *adapter = netdev_priv(netdev);7464	struct igc_hw *hw = &adapter->hw;7465	pci_ers_result_t result;7466 7467	if (pci_enable_device_mem(pdev)) {7468		netdev_err(netdev, "Could not re-enable PCI device after reset\n");7469		result = PCI_ERS_RESULT_DISCONNECT;7470	} else {7471		pci_set_master(pdev);7472		pci_restore_state(pdev);7473		pci_save_state(pdev);7474 7475		pci_enable_wake(pdev, PCI_D3hot, 0);7476		pci_enable_wake(pdev, PCI_D3cold, 0);7477 7478		/* In case of PCI error, adapter loses its HW address7479		 * so we should re-assign it here.7480		 */7481		hw->hw_addr = adapter->io_addr;7482 7483		igc_reset(adapter);7484		wr32(IGC_WUS, ~0);7485		result = PCI_ERS_RESULT_RECOVERED;7486	}7487 7488	return result;7489}7490 7491/**7492 *  igc_io_resume - called when traffic can start to flow again.7493 *  @pdev: Pointer to PCI device7494 *7495 *  This callback is called when the error recovery driver tells us that7496 *  its OK to resume normal operation. Implementation resembles the7497 *  second-half of the igc_resume routine.7498 */7499static void igc_io_resume(struct pci_dev *pdev)7500{7501	struct net_device *netdev = pci_get_drvdata(pdev);7502	struct igc_adapter *adapter = netdev_priv(netdev);7503 7504	rtnl_lock();7505	if (netif_running(netdev)) {7506		if (igc_open(netdev)) {7507			rtnl_unlock();7508			netdev_err(netdev, "igc_open failed after reset\n");7509			return;7510		}7511	}7512 7513	netif_device_attach(netdev);7514 7515	/* let the f/w know that the h/w is now under the control of the7516	 * driver.7517	 */7518	igc_get_hw_control(adapter);7519	rtnl_unlock();7520}7521 7522static const struct pci_error_handlers igc_err_handler = {7523	.error_detected = igc_io_error_detected,7524	.slot_reset = igc_io_slot_reset,7525	.resume = igc_io_resume,7526};7527 7528static _DEFINE_DEV_PM_OPS(igc_pm_ops, igc_suspend, igc_resume,7529			  igc_runtime_suspend, igc_runtime_resume,7530			  igc_runtime_idle);7531 7532static struct pci_driver igc_driver = {7533	.name     = igc_driver_name,7534	.id_table = igc_pci_tbl,7535	.probe    = igc_probe,7536	.remove   = igc_remove,7537	.driver.pm = pm_ptr(&igc_pm_ops),7538	.shutdown = igc_shutdown,7539	.err_handler = &igc_err_handler,7540};7541 7542/**7543 * igc_reinit_queues - return error7544 * @adapter: pointer to adapter structure7545 */7546int igc_reinit_queues(struct igc_adapter *adapter)7547{7548	struct net_device *netdev = adapter->netdev;7549	int err = 0;7550 7551	if (netif_running(netdev))7552		igc_close(netdev);7553 7554	igc_reset_interrupt_capability(adapter);7555 7556	if (igc_init_interrupt_scheme(adapter, true)) {7557		netdev_err(netdev, "Unable to allocate memory for queues\n");7558		return -ENOMEM;7559	}7560 7561	if (netif_running(netdev))7562		err = igc_open(netdev);7563 7564	return err;7565}7566 7567/**7568 * igc_get_hw_dev - return device7569 * @hw: pointer to hardware structure7570 *7571 * used by hardware layer to print debugging information7572 */7573struct net_device *igc_get_hw_dev(struct igc_hw *hw)7574{7575	struct igc_adapter *adapter = hw->back;7576 7577	return adapter->netdev;7578}7579 7580static void igc_disable_rx_ring_hw(struct igc_ring *ring)7581{7582	struct igc_hw *hw = &ring->q_vector->adapter->hw;7583	u8 idx = ring->reg_idx;7584	u32 rxdctl;7585 7586	rxdctl = rd32(IGC_RXDCTL(idx));7587	rxdctl &= ~IGC_RXDCTL_QUEUE_ENABLE;7588	rxdctl |= IGC_RXDCTL_SWFLUSH;7589	wr32(IGC_RXDCTL(idx), rxdctl);7590}7591 7592void igc_disable_rx_ring(struct igc_ring *ring)7593{7594	igc_disable_rx_ring_hw(ring);7595	igc_clean_rx_ring(ring);7596}7597 7598void igc_enable_rx_ring(struct igc_ring *ring)7599{7600	struct igc_adapter *adapter = ring->q_vector->adapter;7601 7602	igc_configure_rx_ring(adapter, ring);7603 7604	if (ring->xsk_pool)7605		igc_alloc_rx_buffers_zc(ring, igc_desc_unused(ring));7606	else7607		igc_alloc_rx_buffers(ring, igc_desc_unused(ring));7608}7609 7610void igc_disable_tx_ring(struct igc_ring *ring)7611{7612	igc_disable_tx_ring_hw(ring);7613	igc_clean_tx_ring(ring);7614}7615 7616void igc_enable_tx_ring(struct igc_ring *ring)7617{7618	struct igc_adapter *adapter = ring->q_vector->adapter;7619 7620	igc_configure_tx_ring(adapter, ring);7621}7622 7623/**7624 * igc_init_module - Driver Registration Routine7625 *7626 * igc_init_module is the first routine called when the driver is7627 * loaded. All it does is register with the PCI subsystem.7628 */7629static int __init igc_init_module(void)7630{7631	int ret;7632 7633	pr_info("%s\n", igc_driver_string);7634	pr_info("%s\n", igc_copyright);7635 7636	ret = pci_register_driver(&igc_driver);7637	return ret;7638}7639 7640module_init(igc_init_module);7641 7642/**7643 * igc_exit_module - Driver Exit Cleanup Routine7644 *7645 * igc_exit_module is called just before the driver is removed7646 * from memory.7647 */7648static void __exit igc_exit_module(void)7649{7650	pci_unregister_driver(&igc_driver);7651}7652 7653module_exit(igc_exit_module);7654/* igc_main.c */7655