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1// SPDX-License-Identifier: GPL-2.02/* Copyright (c) 2018 Intel Corporation */3 4#include <linux/bitfield.h>5#include "igc_phy.h"6 7/**8 * igc_check_reset_block - Check if PHY reset is blocked9 * @hw: pointer to the HW structure10 *11 * Read the PHY management control register and check whether a PHY reset12 * is blocked. If a reset is not blocked return 0, otherwise13 * return IGC_ERR_BLK_PHY_RESET (12).14 */15s32 igc_check_reset_block(struct igc_hw *hw)16{17 u32 manc;18 19 manc = rd32(IGC_MANC);20 21 return (manc & IGC_MANC_BLK_PHY_RST_ON_IDE) ?22 IGC_ERR_BLK_PHY_RESET : 0;23}24 25/**26 * igc_get_phy_id - Retrieve the PHY ID and revision27 * @hw: pointer to the HW structure28 *29 * Reads the PHY registers and stores the PHY ID and possibly the PHY30 * revision in the hardware structure.31 */32s32 igc_get_phy_id(struct igc_hw *hw)33{34 struct igc_phy_info *phy = &hw->phy;35 s32 ret_val = 0;36 u16 phy_id;37 38 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);39 if (ret_val)40 goto out;41 42 phy->id = (u32)(phy_id << 16);43 usleep_range(200, 500);44 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);45 if (ret_val)46 goto out;47 48 phy->id |= (u32)(phy_id & PHY_REVISION_MASK);49 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);50 51out:52 return ret_val;53}54 55/**56 * igc_phy_has_link - Polls PHY for link57 * @hw: pointer to the HW structure58 * @iterations: number of times to poll for link59 * @usec_interval: delay between polling attempts60 * @success: pointer to whether polling was successful or not61 *62 * Polls the PHY status register for link, 'iterations' number of times.63 */64s32 igc_phy_has_link(struct igc_hw *hw, u32 iterations,65 u32 usec_interval, bool *success)66{67 u16 i, phy_status;68 s32 ret_val = 0;69 70 for (i = 0; i < iterations; i++) {71 /* Some PHYs require the PHY_STATUS register to be read72 * twice due to the link bit being sticky. No harm doing73 * it across the board.74 */75 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);76 if (ret_val && usec_interval > 0) {77 /* If the first read fails, another entity may have78 * ownership of the resources, wait and try again to79 * see if they have relinquished the resources yet.80 */81 if (usec_interval >= 1000)82 mdelay(usec_interval / 1000);83 else84 udelay(usec_interval);85 }86 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);87 if (ret_val)88 break;89 if (phy_status & MII_SR_LINK_STATUS)90 break;91 if (usec_interval >= 1000)92 mdelay(usec_interval / 1000);93 else94 udelay(usec_interval);95 }96 97 *success = (i < iterations) ? true : false;98 99 return ret_val;100}101 102/**103 * igc_power_up_phy_copper - Restore copper link in case of PHY power down104 * @hw: pointer to the HW structure105 *106 * In the case of a PHY power down to save power, or to turn off link during a107 * driver unload, restore the link to previous settings.108 */109void igc_power_up_phy_copper(struct igc_hw *hw)110{111 u16 mii_reg = 0;112 113 /* The PHY will retain its settings across a power down/up cycle */114 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);115 mii_reg &= ~MII_CR_POWER_DOWN;116 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);117}118 119/**120 * igc_power_down_phy_copper - Power down copper PHY121 * @hw: pointer to the HW structure122 *123 * Power down PHY to save power when interface is down and wake on lan124 * is not enabled.125 */126void igc_power_down_phy_copper(struct igc_hw *hw)127{128 u16 mii_reg = 0;129 130 /* The PHY will retain its settings across a power down/up cycle */131 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);132 mii_reg |= MII_CR_POWER_DOWN;133 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);134 usleep_range(1000, 2000);135}136 137/**138 * igc_check_downshift - Checks whether a downshift in speed occurred139 * @hw: pointer to the HW structure140 *141 * A downshift is detected by querying the PHY link health.142 */143void igc_check_downshift(struct igc_hw *hw)144{145 struct igc_phy_info *phy = &hw->phy;146 147 /* speed downshift not supported */148 phy->speed_downgraded = false;149}150 151/**152 * igc_phy_hw_reset - PHY hardware reset153 * @hw: pointer to the HW structure154 *155 * Verify the reset block is not blocking us from resetting. Acquire156 * semaphore (if necessary) and read/set/write the device control reset157 * bit in the PHY. Wait the appropriate delay time for the device to158 * reset and release the semaphore (if necessary).159 */160s32 igc_phy_hw_reset(struct igc_hw *hw)161{162 struct igc_phy_info *phy = &hw->phy;163 u32 phpm = 0, timeout = 10000;164 s32 ret_val;165 u32 ctrl;166 167 ret_val = igc_check_reset_block(hw);168 if (ret_val) {169 ret_val = 0;170 goto out;171 }172 173 ret_val = phy->ops.acquire(hw);174 if (ret_val)175 goto out;176 177 phpm = rd32(IGC_I225_PHPM);178 179 ctrl = rd32(IGC_CTRL);180 wr32(IGC_CTRL, ctrl | IGC_CTRL_PHY_RST);181 wrfl();182 183 udelay(phy->reset_delay_us);184 185 wr32(IGC_CTRL, ctrl);186 wrfl();187 188 /* SW should guarantee 100us for the completion of the PHY reset */189 usleep_range(100, 150);190 do {191 phpm = rd32(IGC_I225_PHPM);192 timeout--;193 udelay(1);194 } while (!(phpm & IGC_PHY_RST_COMP) && timeout);195 196 if (!timeout)197 hw_dbg("Timeout is expired after a phy reset\n");198 199 usleep_range(100, 150);200 201 phy->ops.release(hw);202 203out:204 return ret_val;205}206 207/**208 * igc_phy_setup_autoneg - Configure PHY for auto-negotiation209 * @hw: pointer to the HW structure210 *211 * Reads the MII auto-neg advertisement register and/or the 1000T control212 * register and if the PHY is already setup for auto-negotiation, then213 * return successful. Otherwise, setup advertisement and flow control to214 * the appropriate values for the wanted auto-negotiation.215 */216static s32 igc_phy_setup_autoneg(struct igc_hw *hw)217{218 struct igc_phy_info *phy = &hw->phy;219 u16 aneg_multigbt_an_ctrl = 0;220 u16 mii_1000t_ctrl_reg = 0;221 u16 mii_autoneg_adv_reg;222 s32 ret_val;223 224 phy->autoneg_advertised &= phy->autoneg_mask;225 226 /* Read the MII Auto-Neg Advertisement Register (Address 4). */227 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);228 if (ret_val)229 return ret_val;230 231 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {232 /* Read the MII 1000Base-T Control Register (Address 9). */233 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL,234 &mii_1000t_ctrl_reg);235 if (ret_val)236 return ret_val;237 }238 239 if (phy->autoneg_mask & ADVERTISE_2500_FULL) {240 /* Read the MULTI GBT AN Control Register - reg 7.32 */241 ret_val = phy->ops.read_reg(hw, (STANDARD_AN_REG_MASK <<242 MMD_DEVADDR_SHIFT) |243 IGC_ANEG_MULTIGBT_AN_CTRL,244 &aneg_multigbt_an_ctrl);245 246 if (ret_val)247 return ret_val;248 }249 250 /* Need to parse both autoneg_advertised and fc and set up251 * the appropriate PHY registers. First we will parse for252 * autoneg_advertised software override. Since we can advertise253 * a plethora of combinations, we need to check each bit254 * individually.255 */256 257 /* First we clear all the 10/100 mb speed bits in the Auto-Neg258 * Advertisement Register (Address 4) and the 1000 mb speed bits in259 * the 1000Base-T Control Register (Address 9).260 */261 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS |262 NWAY_AR_100TX_HD_CAPS |263 NWAY_AR_10T_FD_CAPS |264 NWAY_AR_10T_HD_CAPS);265 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS);266 267 hw_dbg("autoneg_advertised %x\n", phy->autoneg_advertised);268 269 /* Do we want to advertise 10 Mb Half Duplex? */270 if (phy->autoneg_advertised & ADVERTISE_10_HALF) {271 hw_dbg("Advertise 10mb Half duplex\n");272 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;273 }274 275 /* Do we want to advertise 10 Mb Full Duplex? */276 if (phy->autoneg_advertised & ADVERTISE_10_FULL) {277 hw_dbg("Advertise 10mb Full duplex\n");278 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;279 }280 281 /* Do we want to advertise 100 Mb Half Duplex? */282 if (phy->autoneg_advertised & ADVERTISE_100_HALF) {283 hw_dbg("Advertise 100mb Half duplex\n");284 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;285 }286 287 /* Do we want to advertise 100 Mb Full Duplex? */288 if (phy->autoneg_advertised & ADVERTISE_100_FULL) {289 hw_dbg("Advertise 100mb Full duplex\n");290 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;291 }292 293 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */294 if (phy->autoneg_advertised & ADVERTISE_1000_HALF)295 hw_dbg("Advertise 1000mb Half duplex request denied!\n");296 297 /* Do we want to advertise 1000 Mb Full Duplex? */298 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {299 hw_dbg("Advertise 1000mb Full duplex\n");300 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;301 }302 303 /* We do not allow the Phy to advertise 2500 Mb Half Duplex */304 if (phy->autoneg_advertised & ADVERTISE_2500_HALF)305 hw_dbg("Advertise 2500mb Half duplex request denied!\n");306 307 /* Do we want to advertise 2500 Mb Full Duplex? */308 if (phy->autoneg_advertised & ADVERTISE_2500_FULL) {309 hw_dbg("Advertise 2500mb Full duplex\n");310 aneg_multigbt_an_ctrl |= CR_2500T_FD_CAPS;311 } else {312 aneg_multigbt_an_ctrl &= ~CR_2500T_FD_CAPS;313 }314 315 /* Check for a software override of the flow control settings, and316 * setup the PHY advertisement registers accordingly. If317 * auto-negotiation is enabled, then software will have to set the318 * "PAUSE" bits to the correct value in the Auto-Negotiation319 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-320 * negotiation.321 *322 * The possible values of the "fc" parameter are:323 * 0: Flow control is completely disabled324 * 1: Rx flow control is enabled (we can receive pause frames325 * but not send pause frames).326 * 2: Tx flow control is enabled (we can send pause frames327 * but we do not support receiving pause frames).328 * 3: Both Rx and Tx flow control (symmetric) are enabled.329 * other: No software override. The flow control configuration330 * in the EEPROM is used.331 */332 switch (hw->fc.current_mode) {333 case igc_fc_none:334 /* Flow control (Rx & Tx) is completely disabled by a335 * software over-ride.336 */337 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);338 break;339 case igc_fc_rx_pause:340 /* Rx Flow control is enabled, and Tx Flow control is341 * disabled, by a software over-ride.342 *343 * Since there really isn't a way to advertise that we are344 * capable of Rx Pause ONLY, we will advertise that we345 * support both symmetric and asymmetric Rx PAUSE. Later346 * (in igc_config_fc_after_link_up) we will disable the347 * hw's ability to send PAUSE frames.348 */349 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);350 break;351 case igc_fc_tx_pause:352 /* Tx Flow control is enabled, and Rx Flow control is353 * disabled, by a software over-ride.354 */355 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;356 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;357 break;358 case igc_fc_full:359 /* Flow control (both Rx and Tx) is enabled by a software360 * over-ride.361 */362 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);363 break;364 default:365 hw_dbg("Flow control param set incorrectly\n");366 return -IGC_ERR_CONFIG;367 }368 369 ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);370 if (ret_val)371 return ret_val;372 373 hw_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);374 375 if (phy->autoneg_mask & ADVERTISE_1000_FULL)376 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL,377 mii_1000t_ctrl_reg);378 379 if (phy->autoneg_mask & ADVERTISE_2500_FULL)380 ret_val = phy->ops.write_reg(hw,381 (STANDARD_AN_REG_MASK <<382 MMD_DEVADDR_SHIFT) |383 IGC_ANEG_MULTIGBT_AN_CTRL,384 aneg_multigbt_an_ctrl);385 386 return ret_val;387}388 389/**390 * igc_wait_autoneg - Wait for auto-neg completion391 * @hw: pointer to the HW structure392 *393 * Waits for auto-negotiation to complete or for the auto-negotiation time394 * limit to expire, which ever happens first.395 */396static s32 igc_wait_autoneg(struct igc_hw *hw)397{398 u16 i, phy_status;399 s32 ret_val = 0;400 401 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */402 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) {403 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);404 if (ret_val)405 break;406 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);407 if (ret_val)408 break;409 if (phy_status & MII_SR_AUTONEG_COMPLETE)410 break;411 msleep(100);412 }413 414 /* PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation415 * has completed.416 */417 return ret_val;418}419 420/**421 * igc_copper_link_autoneg - Setup/Enable autoneg for copper link422 * @hw: pointer to the HW structure423 *424 * Performs initial bounds checking on autoneg advertisement parameter, then425 * configure to advertise the full capability. Setup the PHY to autoneg426 * and restart the negotiation process between the link partner. If427 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting.428 */429static s32 igc_copper_link_autoneg(struct igc_hw *hw)430{431 struct igc_phy_info *phy = &hw->phy;432 u16 phy_ctrl;433 s32 ret_val;434 435 /* Perform some bounds checking on the autoneg advertisement436 * parameter.437 */438 phy->autoneg_advertised &= phy->autoneg_mask;439 440 /* If autoneg_advertised is zero, we assume it was not defaulted441 * by the calling code so we set to advertise full capability.442 */443 if (phy->autoneg_advertised == 0)444 phy->autoneg_advertised = phy->autoneg_mask;445 446 hw_dbg("Reconfiguring auto-neg advertisement params\n");447 ret_val = igc_phy_setup_autoneg(hw);448 if (ret_val) {449 hw_dbg("Error Setting up Auto-Negotiation\n");450 goto out;451 }452 hw_dbg("Restarting Auto-Neg\n");453 454 /* Restart auto-negotiation by setting the Auto Neg Enable bit and455 * the Auto Neg Restart bit in the PHY control register.456 */457 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);458 if (ret_val)459 goto out;460 461 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);462 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl);463 if (ret_val)464 goto out;465 466 /* Does the user want to wait for Auto-Neg to complete here, or467 * check at a later time (for example, callback routine).468 */469 if (phy->autoneg_wait_to_complete) {470 ret_val = igc_wait_autoneg(hw);471 if (ret_val) {472 hw_dbg("Error while waiting for autoneg to complete\n");473 goto out;474 }475 }476 477 hw->mac.get_link_status = true;478 479out:480 return ret_val;481}482 483/**484 * igc_setup_copper_link - Configure copper link settings485 * @hw: pointer to the HW structure486 *487 * Calls the appropriate function to configure the link for auto-neg or forced488 * speed and duplex. Then we check for link, once link is established calls489 * to configure collision distance and flow control are called. If link is490 * not established, we return -IGC_ERR_PHY (-2).491 */492s32 igc_setup_copper_link(struct igc_hw *hw)493{494 s32 ret_val = 0;495 bool link;496 497 if (hw->mac.autoneg) {498 /* Setup autoneg and flow control advertisement and perform499 * autonegotiation.500 */501 ret_val = igc_copper_link_autoneg(hw);502 if (ret_val)503 goto out;504 } else {505 /* PHY will be set to 10H, 10F, 100H or 100F506 * depending on user settings.507 */508 hw_dbg("Forcing Speed and Duplex\n");509 ret_val = hw->phy.ops.force_speed_duplex(hw);510 if (ret_val) {511 hw_dbg("Error Forcing Speed and Duplex\n");512 goto out;513 }514 }515 516 /* Check link status. Wait up to 100 microseconds for link to become517 * valid.518 */519 ret_val = igc_phy_has_link(hw, COPPER_LINK_UP_LIMIT, 10, &link);520 if (ret_val)521 goto out;522 523 if (link) {524 hw_dbg("Valid link established!!!\n");525 igc_config_collision_dist(hw);526 ret_val = igc_config_fc_after_link_up(hw);527 } else {528 hw_dbg("Unable to establish link!!!\n");529 }530 531out:532 return ret_val;533}534 535/**536 * igc_read_phy_reg_mdic - Read MDI control register537 * @hw: pointer to the HW structure538 * @offset: register offset to be read539 * @data: pointer to the read data540 *541 * Reads the MDI control register in the PHY at offset and stores the542 * information read to data.543 */544static s32 igc_read_phy_reg_mdic(struct igc_hw *hw, u32 offset, u16 *data)545{546 struct igc_phy_info *phy = &hw->phy;547 u32 i, mdic = 0;548 s32 ret_val = 0;549 550 if (offset > MAX_PHY_REG_ADDRESS) {551 hw_dbg("PHY Address %d is out of range\n", offset);552 ret_val = -IGC_ERR_PARAM;553 goto out;554 }555 556 /* Set up Op-code, Phy Address, and register offset in the MDI557 * Control register. The MAC will take care of interfacing with the558 * PHY to retrieve the desired data.559 */560 mdic = ((offset << IGC_MDIC_REG_SHIFT) |561 (phy->addr << IGC_MDIC_PHY_SHIFT) |562 (IGC_MDIC_OP_READ));563 564 wr32(IGC_MDIC, mdic);565 566 /* Poll the ready bit to see if the MDI read completed567 * Increasing the time out as testing showed failures with568 * the lower time out569 */570 for (i = 0; i < IGC_GEN_POLL_TIMEOUT; i++) {571 udelay(50);572 mdic = rd32(IGC_MDIC);573 if (mdic & IGC_MDIC_READY)574 break;575 }576 if (!(mdic & IGC_MDIC_READY)) {577 hw_dbg("MDI Read did not complete\n");578 ret_val = -IGC_ERR_PHY;579 goto out;580 }581 if (mdic & IGC_MDIC_ERROR) {582 hw_dbg("MDI Error\n");583 ret_val = -IGC_ERR_PHY;584 goto out;585 }586 *data = (u16)mdic;587 588out:589 return ret_val;590}591 592/**593 * igc_write_phy_reg_mdic - Write MDI control register594 * @hw: pointer to the HW structure595 * @offset: register offset to write to596 * @data: data to write to register at offset597 *598 * Writes data to MDI control register in the PHY at offset.599 */600static s32 igc_write_phy_reg_mdic(struct igc_hw *hw, u32 offset, u16 data)601{602 struct igc_phy_info *phy = &hw->phy;603 u32 i, mdic = 0;604 s32 ret_val = 0;605 606 if (offset > MAX_PHY_REG_ADDRESS) {607 hw_dbg("PHY Address %d is out of range\n", offset);608 ret_val = -IGC_ERR_PARAM;609 goto out;610 }611 612 /* Set up Op-code, Phy Address, and register offset in the MDI613 * Control register. The MAC will take care of interfacing with the614 * PHY to write the desired data.615 */616 mdic = (((u32)data) |617 (offset << IGC_MDIC_REG_SHIFT) |618 (phy->addr << IGC_MDIC_PHY_SHIFT) |619 (IGC_MDIC_OP_WRITE));620 621 wr32(IGC_MDIC, mdic);622 623 /* Poll the ready bit to see if the MDI read completed624 * Increasing the time out as testing showed failures with625 * the lower time out626 */627 for (i = 0; i < IGC_GEN_POLL_TIMEOUT; i++) {628 udelay(50);629 mdic = rd32(IGC_MDIC);630 if (mdic & IGC_MDIC_READY)631 break;632 }633 if (!(mdic & IGC_MDIC_READY)) {634 hw_dbg("MDI Write did not complete\n");635 ret_val = -IGC_ERR_PHY;636 goto out;637 }638 if (mdic & IGC_MDIC_ERROR) {639 hw_dbg("MDI Error\n");640 ret_val = -IGC_ERR_PHY;641 goto out;642 }643 644out:645 return ret_val;646}647 648/**649 * __igc_access_xmdio_reg - Read/write XMDIO register650 * @hw: pointer to the HW structure651 * @address: XMDIO address to program652 * @dev_addr: device address to program653 * @data: pointer to value to read/write from/to the XMDIO address654 * @read: boolean flag to indicate read or write655 */656static s32 __igc_access_xmdio_reg(struct igc_hw *hw, u16 address,657 u8 dev_addr, u16 *data, bool read)658{659 s32 ret_val;660 661 ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAC, dev_addr);662 if (ret_val)663 return ret_val;664 665 ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAAD, address);666 if (ret_val)667 return ret_val;668 669 ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAC, IGC_MMDAC_FUNC_DATA |670 dev_addr);671 if (ret_val)672 return ret_val;673 674 if (read)675 ret_val = hw->phy.ops.read_reg(hw, IGC_MMDAAD, data);676 else677 ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAAD, *data);678 if (ret_val)679 return ret_val;680 681 /* Recalibrate the device back to 0 */682 ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAC, 0);683 if (ret_val)684 return ret_val;685 686 return ret_val;687}688 689/**690 * igc_read_xmdio_reg - Read XMDIO register691 * @hw: pointer to the HW structure692 * @addr: XMDIO address to program693 * @dev_addr: device address to program694 * @data: value to be read from the EMI address695 */696static s32 igc_read_xmdio_reg(struct igc_hw *hw, u16 addr,697 u8 dev_addr, u16 *data)698{699 return __igc_access_xmdio_reg(hw, addr, dev_addr, data, true);700}701 702/**703 * igc_write_xmdio_reg - Write XMDIO register704 * @hw: pointer to the HW structure705 * @addr: XMDIO address to program706 * @dev_addr: device address to program707 * @data: value to be written to the XMDIO address708 */709static s32 igc_write_xmdio_reg(struct igc_hw *hw, u16 addr,710 u8 dev_addr, u16 data)711{712 return __igc_access_xmdio_reg(hw, addr, dev_addr, &data, false);713}714 715/**716 * igc_write_phy_reg_gpy - Write GPY PHY register717 * @hw: pointer to the HW structure718 * @offset: register offset to write to719 * @data: data to write at register offset720 *721 * Acquires semaphore, if necessary, then writes the data to PHY register722 * at the offset. Release any acquired semaphores before exiting.723 */724s32 igc_write_phy_reg_gpy(struct igc_hw *hw, u32 offset, u16 data)725{726 u8 dev_addr = FIELD_GET(GPY_MMD_MASK, offset);727 s32 ret_val;728 729 offset = offset & GPY_REG_MASK;730 731 if (!dev_addr) {732 ret_val = hw->phy.ops.acquire(hw);733 if (ret_val)734 return ret_val;735 ret_val = igc_write_phy_reg_mdic(hw, offset, data);736 hw->phy.ops.release(hw);737 } else {738 ret_val = igc_write_xmdio_reg(hw, (u16)offset, dev_addr,739 data);740 }741 742 return ret_val;743}744 745/**746 * igc_read_phy_reg_gpy - Read GPY PHY register747 * @hw: pointer to the HW structure748 * @offset: lower half is register offset to read to749 * upper half is MMD to use.750 * @data: data to read at register offset751 *752 * Acquires semaphore, if necessary, then reads the data in the PHY register753 * at the offset. Release any acquired semaphores before exiting.754 */755s32 igc_read_phy_reg_gpy(struct igc_hw *hw, u32 offset, u16 *data)756{757 u8 dev_addr = FIELD_GET(GPY_MMD_MASK, offset);758 s32 ret_val;759 760 offset = offset & GPY_REG_MASK;761 762 if (!dev_addr) {763 ret_val = hw->phy.ops.acquire(hw);764 if (ret_val)765 return ret_val;766 ret_val = igc_read_phy_reg_mdic(hw, offset, data);767 hw->phy.ops.release(hw);768 } else {769 ret_val = igc_read_xmdio_reg(hw, (u16)offset, dev_addr,770 data);771 }772 773 return ret_val;774}775 776/**777 * igc_read_phy_fw_version - Read gPHY firmware version778 * @hw: pointer to the HW structure779 */780u16 igc_read_phy_fw_version(struct igc_hw *hw)781{782 struct igc_phy_info *phy = &hw->phy;783 u16 gphy_version = 0;784 u16 ret_val;785 786 /* NVM image version is reported as firmware version for i225 device */787 ret_val = phy->ops.read_reg(hw, IGC_GPHY_VERSION, &gphy_version);788 if (ret_val)789 hw_dbg("igc_phy: read wrong gphy version\n");790 791 return gphy_version;792}793