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1/* SPDX-License-Identifier: GPL-2.0 */2/* Copyright(c) 1999 - 2018 Intel Corporation. */3 4#ifndef _DCB_82599_CONFIG_H_5#define _DCB_82599_CONFIG_H_6 7/* DCB register definitions */8#define IXGBE_RTTDCS_TDPAC 0x00000001 /* 0 Round Robin,9 * 1 WSP - Weighted Strict Priority10 */11#define IXGBE_RTTDCS_VMPAC 0x00000002 /* 0 Round Robin,12 * 1 WRR - Weighted Round Robin13 */14#define IXGBE_RTTDCS_TDRM 0x00000010 /* Transmit Recycle Mode */15#define IXGBE_RTTDCS_ARBDIS 0x00000040 /* DCB arbiter disable */16#define IXGBE_RTTDCS_BDPM 0x00400000 /* Bypass Data Pipe - must clear! */17#define IXGBE_RTTDCS_BPBFSM 0x00800000 /* Bypass PB Free Space - must18 * clear!19 */20#define IXGBE_RTTDCS_SPEED_CHG 0x80000000 /* Link speed change */21 22/* Receive UP2TC mapping */23#define IXGBE_RTRUP2TC_UP_SHIFT 324#define IXGBE_RTRUP2TC_UP_MASK 725/* Transmit UP2TC mapping */26#define IXGBE_RTTUP2TC_UP_SHIFT 327 28#define IXGBE_RTRPT4C_MCL_SHIFT 12 /* Offset to Max Credit Limit setting */29#define IXGBE_RTRPT4C_BWG_SHIFT 9 /* Offset to BWG index */30#define IXGBE_RTRPT4C_GSP 0x40000000 /* GSP enable bit */31#define IXGBE_RTRPT4C_LSP 0x80000000 /* LSP enable bit */32 33#define IXGBE_RDRXCTL_MPBEN 0x00000010 /* DMA config for multiple packet34 * buffers enable35 */36#define IXGBE_RDRXCTL_MCEN 0x00000040 /* DMA config for multiple cores37 * (RSS) enable38 */39 40/* RTRPCS Bit Masks */41#define IXGBE_RTRPCS_RRM 0x00000002 /* Receive Recycle Mode enable */42/* Receive Arbitration Control: 0 Round Robin, 1 DFP */43#define IXGBE_RTRPCS_RAC 0x0000000444#define IXGBE_RTRPCS_ARBDIS 0x00000040 /* Arbitration disable bit */45 46/* RTTDT2C Bit Masks */47#define IXGBE_RTTDT2C_MCL_SHIFT 1248#define IXGBE_RTTDT2C_BWG_SHIFT 949#define IXGBE_RTTDT2C_GSP 0x4000000050#define IXGBE_RTTDT2C_LSP 0x8000000051 52#define IXGBE_RTTPT2C_MCL_SHIFT 1253#define IXGBE_RTTPT2C_BWG_SHIFT 954#define IXGBE_RTTPT2C_GSP 0x4000000055#define IXGBE_RTTPT2C_LSP 0x8000000056 57/* RTTPCS Bit Masks */58#define IXGBE_RTTPCS_TPPAC 0x00000020 /* 0 Round Robin,59 * 1 SP - Strict Priority60 */61#define IXGBE_RTTPCS_ARBDIS 0x00000040 /* Arbiter disable */62#define IXGBE_RTTPCS_TPRM 0x00000100 /* Transmit Recycle Mode enable */63#define IXGBE_RTTPCS_ARBD_SHIFT 2264#define IXGBE_RTTPCS_ARBD_DCB 0x4 /* Arbitration delay in DCB mode */65 66/* SECTXMINIFG DCB */67#define IXGBE_SECTX_DCB 0x00001F00 /* DCB TX Buffer IFG */68 69 70/* DCB hardware-specific driver APIs */71 72/* DCB PFC functions */73int ixgbe_dcb_config_pfc_82599(struct ixgbe_hw *hw, u8 pfc_en, u8 *prio_tc);74 75/* DCB hw initialization */76int ixgbe_dcb_config_rx_arbiter_82599(struct ixgbe_hw *hw, u16 *refill,77 u16 *max, u8 *bwg_id, u8 *prio_type,78 u8 *prio_tc);79 80int ixgbe_dcb_config_tx_desc_arbiter_82599(struct ixgbe_hw *hw, u16 *refill,81 u16 *max, u8 *bwg_id, u8 *prio_type);82 83int ixgbe_dcb_config_tx_data_arbiter_82599(struct ixgbe_hw *hw, u16 *refill,84 u16 *max, u8 *bwg_id, u8 *prio_type,85 u8 *prio_tc);86 87int ixgbe_dcb_hw_config_82599(struct ixgbe_hw *hw, u8 pfc_en, u16 *refill,88 u16 *max, u8 *bwg_id, u8 *prio_type,89 u8 *prio_tc);90 91#endif /* _DCB_82599_CONFIG_H */92