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1/* SPDX-License-Identifier: GPL-2.0 */2/* Copyright(c) 1999 - 2018 Intel Corporation. */3 4#ifndef _IXGBE_PHY_H_5#define _IXGBE_PHY_H_6 7#include "ixgbe_type.h"8#define IXGBE_I2C_EEPROM_DEV_ADDR 0xA09#define IXGBE_I2C_EEPROM_DEV_ADDR2 0xA210 11/* EEPROM byte offsets */12#define IXGBE_SFF_IDENTIFIER 0x013#define IXGBE_SFF_IDENTIFIER_SFP 0x314#define IXGBE_SFF_VENDOR_OUI_BYTE0 0x2515#define IXGBE_SFF_VENDOR_OUI_BYTE1 0x2616#define IXGBE_SFF_VENDOR_OUI_BYTE2 0x2717#define IXGBE_SFF_1GBE_COMP_CODES 0x618#define IXGBE_SFF_10GBE_COMP_CODES 0x319#define IXGBE_SFF_CABLE_TECHNOLOGY 0x820#define IXGBE_SFF_BITRATE_NOMINAL 0xC21#define IXGBE_SFF_CABLE_SPEC_COMP 0x3C22#define IXGBE_SFF_SFF_8472_SWAP 0x5C23#define IXGBE_SFF_SFF_8472_COMP 0x5E24#define IXGBE_SFF_SFF_8472_OSCB 0x6E25#define IXGBE_SFF_SFF_8472_ESCB 0x7626#define IXGBE_SFF_IDENTIFIER_QSFP_PLUS 0xD27#define IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0 0xA528#define IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1 0xA629#define IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2 0xA730#define IXGBE_SFF_QSFP_CONNECTOR 0x8231#define IXGBE_SFF_QSFP_10GBE_COMP 0x8332#define IXGBE_SFF_QSFP_1GBE_COMP 0x8633#define IXGBE_SFF_QSFP_CABLE_LENGTH 0x9234#define IXGBE_SFF_QSFP_DEVICE_TECH 0x9335 36/* Bitmasks */37#define IXGBE_SFF_DA_PASSIVE_CABLE 0x438#define IXGBE_SFF_DA_ACTIVE_CABLE 0x839#define IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING 0x440#define IXGBE_SFF_1GBASESX_CAPABLE 0x141#define IXGBE_SFF_1GBASELX_CAPABLE 0x242#define IXGBE_SFF_1GBASET_CAPABLE 0x843#define IXGBE_SFF_BASEBX10_CAPABLE 0x6444#define IXGBE_SFF_10GBASESR_CAPABLE 0x1045#define IXGBE_SFF_10GBASELR_CAPABLE 0x2046#define IXGBE_SFF_SOFT_RS_SELECT_MASK 0x847#define IXGBE_SFF_SOFT_RS_SELECT_10G 0x848#define IXGBE_SFF_SOFT_RS_SELECT_1G 0x049#define IXGBE_SFF_ADDRESSING_MODE 0x450#define IXGBE_SFF_DDM_IMPLEMENTED 0x4051#define IXGBE_SFF_QSFP_DA_ACTIVE_CABLE 0x152#define IXGBE_SFF_QSFP_DA_PASSIVE_CABLE 0x853#define IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE 0x2354#define IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL 0x055#define IXGBE_I2C_EEPROM_READ_MASK 0x10056#define IXGBE_I2C_EEPROM_STATUS_MASK 0x357#define IXGBE_I2C_EEPROM_STATUS_NO_OPERATION 0x058#define IXGBE_I2C_EEPROM_STATUS_PASS 0x159#define IXGBE_I2C_EEPROM_STATUS_FAIL 0x260#define IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS 0x361#define IXGBE_CS4227 0xBE /* CS4227 address */62#define IXGBE_CS4227_GLOBAL_ID_LSB 063#define IXGBE_CS4227_GLOBAL_ID_MSB 164#define IXGBE_CS4227_SCRATCH 265#define IXGBE_CS4227_EFUSE_PDF_SKU 0x19F66#define IXGBE_CS4223_SKU_ID 0x0010 /* Quad port */67#define IXGBE_CS4227_SKU_ID 0x0014 /* Dual port */68#define IXGBE_CS4227_RESET_PENDING 0x135769#define IXGBE_CS4227_RESET_COMPLETE 0x5AA570#define IXGBE_CS4227_RETRIES 1571#define IXGBE_CS4227_EFUSE_STATUS 0x018172#define IXGBE_CS4227_LINE_SPARE22_MSB 0x12AD /* Reg to set speed */73#define IXGBE_CS4227_LINE_SPARE24_LSB 0x12B0 /* Reg to set EDC */74#define IXGBE_CS4227_HOST_SPARE22_MSB 0x1AAD /* Reg to set speed */75#define IXGBE_CS4227_HOST_SPARE24_LSB 0x1AB0 /* Reg to program EDC */76#define IXGBE_CS4227_EEPROM_STATUS 0x500177#define IXGBE_CS4227_EEPROM_LOAD_OK 0x000178#define IXGBE_CS4227_SPEED_1G 0x800079#define IXGBE_CS4227_SPEED_10G 080#define IXGBE_CS4227_EDC_MODE_CX1 0x000281#define IXGBE_CS4227_EDC_MODE_SR 0x000482#define IXGBE_CS4227_EDC_MODE_DIAG 0x000883#define IXGBE_CS4227_RESET_HOLD 500 /* microseconds */84#define IXGBE_CS4227_RESET_DELAY 500 /* milliseconds */85#define IXGBE_CS4227_CHECK_DELAY 30 /* milliseconds */86#define IXGBE_PE 0xE0 /* Port expander addr */87#define IXGBE_PE_OUTPUT 1 /* Output reg offset */88#define IXGBE_PE_CONFIG 3 /* Config reg offset */89#define IXGBE_PE_BIT1 BIT(1)90 91/* Flow control defines */92#define IXGBE_TAF_SYM_PAUSE 0x40093#define IXGBE_TAF_ASM_PAUSE 0x80094 95/* Bit-shift macros */96#define IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT 2497#define IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT 1698#define IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT 899 100/* Vendor OUIs: format of OUI is 0x[byte0][byte1][byte2][00] */101#define IXGBE_SFF_VENDOR_OUI_TYCO 0x00407600102#define IXGBE_SFF_VENDOR_OUI_FTL 0x00906500103#define IXGBE_SFF_VENDOR_OUI_AVAGO 0x00176A00104#define IXGBE_SFF_VENDOR_OUI_INTEL 0x001B2100105 106/* I2C SDA and SCL timing parameters for standard mode */107#define IXGBE_I2C_T_HD_STA 4108#define IXGBE_I2C_T_LOW 5109#define IXGBE_I2C_T_HIGH 4110#define IXGBE_I2C_T_SU_STA 5111#define IXGBE_I2C_T_HD_DATA 5112#define IXGBE_I2C_T_SU_DATA 1113#define IXGBE_I2C_T_RISE 1114#define IXGBE_I2C_T_FALL 1115#define IXGBE_I2C_T_SU_STO 4116#define IXGBE_I2C_T_BUF 5117 118#define IXGBE_SFP_DETECT_RETRIES 2119 120#define IXGBE_TN_LASI_STATUS_REG 0x9005121#define IXGBE_TN_LASI_STATUS_TEMP_ALARM 0x0008122 123/* SFP+ SFF-8472 Compliance code */124#define IXGBE_SFF_SFF_8472_UNSUP 0x00125 126int ixgbe_mii_bus_init(struct ixgbe_hw *hw);127 128int ixgbe_identify_phy_generic(struct ixgbe_hw *hw);129int ixgbe_reset_phy_generic(struct ixgbe_hw *hw);130int ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,131 u32 device_type, u16 *phy_data);132int ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,133 u32 device_type, u16 phy_data);134int ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,135 u32 device_type, u16 *phy_data);136int ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,137 u32 device_type, u16 phy_data);138int ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw);139int ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,140 ixgbe_link_speed speed,141 bool autoneg_wait_to_complete);142int ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,143 ixgbe_link_speed *speed,144 bool *autoneg);145bool ixgbe_check_reset_blocked(struct ixgbe_hw *hw);146 147/* PHY specific */148int ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw,149 ixgbe_link_speed *speed,150 bool *link_up);151int ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw);152 153int ixgbe_reset_phy_nl(struct ixgbe_hw *hw);154int ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on);155int ixgbe_identify_module_generic(struct ixgbe_hw *hw);156int ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw);157int ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,158 u16 *list_offset,159 u16 *data_offset);160bool ixgbe_tn_check_overtemp(struct ixgbe_hw *hw);161int ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,162 u8 dev_addr, u8 *data);163int ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,164 u8 dev_addr, u8 *data);165int ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,166 u8 dev_addr, u8 data);167int ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,168 u8 dev_addr, u8 data);169int ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,170 u8 *eeprom_data);171int ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,172 u8 *sff8472_data);173int ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,174 u8 eeprom_data);175int ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *, u8 addr, u16 reg,176 u16 *val, bool lock);177int ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *, u8 addr, u16 reg,178 u16 val, bool lock);179#endif /* _IXGBE_PHY_H_ */180