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1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * Definitions for Marvell PPv2 network controller for Armada 375 SoC.4 *5 * Copyright (C) 2014 Marvell6 *7 * Marcin Wojtas <mw@semihalf.com>8 */9#ifndef _MVPP2_H_10#define _MVPP2_H_11 12#include <linux/interrupt.h>13#include <linux/kernel.h>14#include <linux/netdevice.h>15#include <linux/net_tstamp.h>16#include <linux/phy.h>17#include <linux/phylink.h>18#include <net/flow_offload.h>19#include <net/page_pool/types.h>20#include <linux/bpf.h>21#include <net/xdp.h>22 23/* The PacketOffset field is measured in units of 32 bytes and is 3 bits wide,24 * so the maximum offset is 7 * 32 = 22425 */26#define MVPP2_SKB_HEADROOM min(max(XDP_PACKET_HEADROOM, NET_SKB_PAD), 224)27 28#define MVPP2_XDP_PASS 029#define MVPP2_XDP_DROPPED BIT(0)30#define MVPP2_XDP_TX BIT(1)31#define MVPP2_XDP_REDIR BIT(2)32 33/* Fifo Registers */34#define MVPP2_RX_DATA_FIFO_SIZE_REG(port) (0x00 + 4 * (port))35#define MVPP2_RX_ATTR_FIFO_SIZE_REG(port) (0x20 + 4 * (port))36#define MVPP2_RX_MIN_PKT_SIZE_REG 0x6037#define MVPP2_RX_FIFO_INIT_REG 0x6438#define MVPP22_TX_FIFO_THRESH_REG(port) (0x8840 + 4 * (port))39#define MVPP22_TX_FIFO_SIZE_REG(port) (0x8860 + 4 * (port))40 41/* RX DMA Top Registers */42#define MVPP2_RX_CTRL_REG(port) (0x140 + 4 * (port))43#define MVPP2_RX_LOW_LATENCY_PKT_SIZE(s) (((s) & 0xfff) << 16)44#define MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK BIT(31)45#define MVPP2_POOL_BUF_SIZE_REG(pool) (0x180 + 4 * (pool))46#define MVPP2_POOL_BUF_SIZE_OFFSET 547#define MVPP2_RXQ_CONFIG_REG(rxq) (0x800 + 4 * (rxq))48#define MVPP2_SNOOP_PKT_SIZE_MASK 0x1ff49#define MVPP2_SNOOP_BUF_HDR_MASK BIT(9)50#define MVPP2_RXQ_POOL_SHORT_OFFS 2051#define MVPP21_RXQ_POOL_SHORT_MASK 0x70000052#define MVPP22_RXQ_POOL_SHORT_MASK 0xf0000053#define MVPP2_RXQ_POOL_LONG_OFFS 2454#define MVPP21_RXQ_POOL_LONG_MASK 0x700000055#define MVPP22_RXQ_POOL_LONG_MASK 0xf00000056#define MVPP2_RXQ_PACKET_OFFSET_OFFS 2857#define MVPP2_RXQ_PACKET_OFFSET_MASK 0x7000000058#define MVPP2_RXQ_DISABLE_MASK BIT(31)59 60/* Top Registers */61#define MVPP2_MH_REG(port) (0x5040 + 4 * (port))62#define MVPP2_DSA_EXTENDED BIT(5)63#define MVPP2_VER_ID_REG 0x50b064#define MVPP2_VER_PP22 0x1065#define MVPP2_VER_PP23 0x1166 67/* Parser Registers */68#define MVPP2_PRS_INIT_LOOKUP_REG 0x100069#define MVPP2_PRS_PORT_LU_MAX 0xf70#define MVPP2_PRS_PORT_LU_MASK(port) (0xff << ((port) * 4))71#define MVPP2_PRS_PORT_LU_VAL(port, val) ((val) << ((port) * 4))72#define MVPP2_PRS_INIT_OFFS_REG(port) (0x1004 + ((port) & 4))73#define MVPP2_PRS_INIT_OFF_MASK(port) (0x3f << (((port) % 4) * 8))74#define MVPP2_PRS_INIT_OFF_VAL(port, val) ((val) << (((port) % 4) * 8))75#define MVPP2_PRS_MAX_LOOP_REG(port) (0x100c + ((port) & 4))76#define MVPP2_PRS_MAX_LOOP_MASK(port) (0xff << (((port) % 4) * 8))77#define MVPP2_PRS_MAX_LOOP_VAL(port, val) ((val) << (((port) % 4) * 8))78#define MVPP2_PRS_TCAM_IDX_REG 0x110079#define MVPP2_PRS_TCAM_DATA_REG(idx) (0x1104 + (idx) * 4)80#define MVPP2_PRS_TCAM_INV_MASK BIT(31)81#define MVPP2_PRS_SRAM_IDX_REG 0x120082#define MVPP2_PRS_SRAM_DATA_REG(idx) (0x1204 + (idx) * 4)83#define MVPP2_PRS_TCAM_CTRL_REG 0x123084#define MVPP2_PRS_TCAM_EN_MASK BIT(0)85#define MVPP2_PRS_TCAM_HIT_IDX_REG 0x124086#define MVPP2_PRS_TCAM_HIT_CNT_REG 0x124487#define MVPP2_PRS_TCAM_HIT_CNT_MASK GENMASK(15, 0)88 89/* RSS Registers */90#define MVPP22_RSS_INDEX 0x150091#define MVPP22_RSS_INDEX_TABLE_ENTRY(idx) (idx)92#define MVPP22_RSS_INDEX_TABLE(idx) ((idx) << 8)93#define MVPP22_RSS_INDEX_QUEUE(idx) ((idx) << 16)94#define MVPP22_RXQ2RSS_TABLE 0x150495#define MVPP22_RSS_TABLE_POINTER(p) (p)96#define MVPP22_RSS_TABLE_ENTRY 0x150897#define MVPP22_RSS_WIDTH 0x150c98 99/* Classifier Registers */100#define MVPP2_CLS_MODE_REG 0x1800101#define MVPP2_CLS_MODE_ACTIVE_MASK BIT(0)102#define MVPP2_CLS_PORT_WAY_REG 0x1810103#define MVPP2_CLS_PORT_WAY_MASK(port) (1 << (port))104#define MVPP2_CLS_LKP_INDEX_REG 0x1814105#define MVPP2_CLS_LKP_INDEX_WAY_OFFS 6106#define MVPP2_CLS_LKP_TBL_REG 0x1818107#define MVPP2_CLS_LKP_TBL_RXQ_MASK 0xff108#define MVPP2_CLS_LKP_FLOW_PTR(flow) ((flow) << 16)109#define MVPP2_CLS_LKP_TBL_LOOKUP_EN_MASK BIT(25)110#define MVPP2_CLS_FLOW_INDEX_REG 0x1820111#define MVPP2_CLS_FLOW_TBL0_REG 0x1824112#define MVPP2_CLS_FLOW_TBL0_LAST BIT(0)113#define MVPP2_CLS_FLOW_TBL0_ENG_MASK 0x7114#define MVPP2_CLS_FLOW_TBL0_OFFS 1115#define MVPP2_CLS_FLOW_TBL0_ENG(x) ((x) << 1)116#define MVPP2_CLS_FLOW_TBL0_PORT_ID_MASK 0xff117#define MVPP2_CLS_FLOW_TBL0_PORT_ID(port) ((port) << 4)118#define MVPP2_CLS_FLOW_TBL0_PORT_ID_SEL BIT(23)119#define MVPP2_CLS_FLOW_TBL1_REG 0x1828120#define MVPP2_CLS_FLOW_TBL1_N_FIELDS_MASK 0x7121#define MVPP2_CLS_FLOW_TBL1_N_FIELDS(x) (x)122#define MVPP2_CLS_FLOW_TBL1_LU_TYPE(lu) (((lu) & 0x3f) << 3)123#define MVPP2_CLS_FLOW_TBL1_PRIO_MASK 0x3f124#define MVPP2_CLS_FLOW_TBL1_PRIO(x) ((x) << 9)125#define MVPP2_CLS_FLOW_TBL1_SEQ_MASK 0x7126#define MVPP2_CLS_FLOW_TBL1_SEQ(x) ((x) << 15)127#define MVPP2_CLS_FLOW_TBL2_REG 0x182c128#define MVPP2_CLS_FLOW_TBL2_FLD_MASK 0x3f129#define MVPP2_CLS_FLOW_TBL2_FLD_OFFS(n) ((n) * 6)130#define MVPP2_CLS_FLOW_TBL2_FLD(n, x) ((x) << ((n) * 6))131#define MVPP2_CLS_OVERSIZE_RXQ_LOW_REG(port) (0x1980 + ((port) * 4))132#define MVPP2_CLS_OVERSIZE_RXQ_LOW_BITS 3133#define MVPP2_CLS_OVERSIZE_RXQ_LOW_MASK 0x7134#define MVPP2_CLS_SWFWD_P2HQ_REG(port) (0x19b0 + ((port) * 4))135#define MVPP2_CLS_SWFWD_PCTRL_REG 0x19d0136#define MVPP2_CLS_SWFWD_PCTRL_MASK(port) (1 << (port))137 138/* Classifier C2 engine Registers */139#define MVPP22_CLS_C2_TCAM_IDX 0x1b00140#define MVPP22_CLS_C2_TCAM_DATA0 0x1b10141#define MVPP22_CLS_C2_TCAM_DATA1 0x1b14142#define MVPP22_CLS_C2_TCAM_DATA2 0x1b18143#define MVPP22_CLS_C2_TCAM_DATA3 0x1b1c144#define MVPP22_CLS_C2_TCAM_DATA4 0x1b20145#define MVPP22_CLS_C2_LU_TYPE(lu) ((lu) & 0x3f)146#define MVPP22_CLS_C2_PORT_ID(port) ((port) << 8)147#define MVPP22_CLS_C2_PORT_MASK (0xff << 8)148#define MVPP22_CLS_C2_TCAM_INV 0x1b24149#define MVPP22_CLS_C2_TCAM_INV_BIT BIT(31)150#define MVPP22_CLS_C2_HIT_CTR 0x1b50151#define MVPP22_CLS_C2_ACT 0x1b60152#define MVPP22_CLS_C2_ACT_RSS_EN(act) (((act) & 0x3) << 19)153#define MVPP22_CLS_C2_ACT_FWD(act) (((act) & 0x7) << 13)154#define MVPP22_CLS_C2_ACT_QHIGH(act) (((act) & 0x3) << 11)155#define MVPP22_CLS_C2_ACT_QLOW(act) (((act) & 0x3) << 9)156#define MVPP22_CLS_C2_ACT_COLOR(act) ((act) & 0x7)157#define MVPP22_CLS_C2_ATTR0 0x1b64158#define MVPP22_CLS_C2_ATTR0_QHIGH(qh) (((qh) & 0x1f) << 24)159#define MVPP22_CLS_C2_ATTR0_QHIGH_MASK 0x1f160#define MVPP22_CLS_C2_ATTR0_QHIGH_OFFS 24161#define MVPP22_CLS_C2_ATTR0_QLOW(ql) (((ql) & 0x7) << 21)162#define MVPP22_CLS_C2_ATTR0_QLOW_MASK 0x7163#define MVPP22_CLS_C2_ATTR0_QLOW_OFFS 21164#define MVPP22_CLS_C2_ATTR1 0x1b68165#define MVPP22_CLS_C2_ATTR2 0x1b6c166#define MVPP22_CLS_C2_ATTR2_RSS_EN BIT(30)167#define MVPP22_CLS_C2_ATTR3 0x1b70168#define MVPP22_CLS_C2_TCAM_CTRL 0x1b90169#define MVPP22_CLS_C2_TCAM_BYPASS_FIFO BIT(0)170 171/* Descriptor Manager Top Registers */172#define MVPP2_RXQ_NUM_REG 0x2040173#define MVPP2_RXQ_DESC_ADDR_REG 0x2044174#define MVPP22_DESC_ADDR_OFFS 8175#define MVPP2_RXQ_DESC_SIZE_REG 0x2048176#define MVPP2_RXQ_DESC_SIZE_MASK 0x3ff0177#define MVPP2_RXQ_STATUS_UPDATE_REG(rxq) (0x3000 + 4 * (rxq))178#define MVPP2_RXQ_NUM_PROCESSED_OFFSET 0179#define MVPP2_RXQ_NUM_NEW_OFFSET 16180#define MVPP2_RXQ_STATUS_REG(rxq) (0x3400 + 4 * (rxq))181#define MVPP2_RXQ_OCCUPIED_MASK 0x3fff182#define MVPP2_RXQ_NON_OCCUPIED_OFFSET 16183#define MVPP2_RXQ_NON_OCCUPIED_MASK 0x3fff0000184#define MVPP2_RXQ_THRESH_REG 0x204c185#define MVPP2_OCCUPIED_THRESH_OFFSET 0186#define MVPP2_OCCUPIED_THRESH_MASK 0x3fff187#define MVPP2_RXQ_INDEX_REG 0x2050188#define MVPP2_TXQ_NUM_REG 0x2080189#define MVPP2_TXQ_DESC_ADDR_REG 0x2084190#define MVPP2_TXQ_DESC_SIZE_REG 0x2088191#define MVPP2_TXQ_DESC_SIZE_MASK 0x3ff0192#define MVPP2_TXQ_THRESH_REG 0x2094193#define MVPP2_TXQ_THRESH_OFFSET 16194#define MVPP2_TXQ_THRESH_MASK 0x3fff195#define MVPP2_AGGR_TXQ_UPDATE_REG 0x2090196#define MVPP2_TXQ_INDEX_REG 0x2098197#define MVPP2_TXQ_PREF_BUF_REG 0x209c198#define MVPP2_PREF_BUF_PTR(desc) ((desc) & 0xfff)199#define MVPP2_PREF_BUF_SIZE_4 (BIT(12) | BIT(13))200#define MVPP2_PREF_BUF_SIZE_16 (BIT(12) | BIT(14))201#define MVPP2_PREF_BUF_THRESH(val) ((val) << 17)202#define MVPP2_TXQ_DRAIN_EN_MASK BIT(31)203#define MVPP2_TXQ_PENDING_REG 0x20a0204#define MVPP2_TXQ_PENDING_MASK 0x3fff205#define MVPP2_TXQ_INT_STATUS_REG 0x20a4206#define MVPP2_TXQ_SENT_REG(txq) (0x3c00 + 4 * (txq))207#define MVPP2_TRANSMITTED_COUNT_OFFSET 16208#define MVPP2_TRANSMITTED_COUNT_MASK 0x3fff0000209#define MVPP2_TXQ_RSVD_REQ_REG 0x20b0210#define MVPP2_TXQ_RSVD_REQ_Q_OFFSET 16211#define MVPP2_TXQ_RSVD_RSLT_REG 0x20b4212#define MVPP2_TXQ_RSVD_RSLT_MASK 0x3fff213#define MVPP2_TXQ_RSVD_CLR_REG 0x20b8214#define MVPP2_TXQ_RSVD_CLR_OFFSET 16215#define MVPP2_AGGR_TXQ_DESC_ADDR_REG(cpu) (0x2100 + 4 * (cpu))216#define MVPP22_AGGR_TXQ_DESC_ADDR_OFFS 8217#define MVPP2_AGGR_TXQ_DESC_SIZE_REG(cpu) (0x2140 + 4 * (cpu))218#define MVPP2_AGGR_TXQ_DESC_SIZE_MASK 0x3ff0219#define MVPP2_AGGR_TXQ_STATUS_REG(cpu) (0x2180 + 4 * (cpu))220#define MVPP2_AGGR_TXQ_PENDING_MASK 0x3fff221#define MVPP2_AGGR_TXQ_INDEX_REG(cpu) (0x21c0 + 4 * (cpu))222 223/* MBUS bridge registers */224#define MVPP2_WIN_BASE(w) (0x4000 + ((w) << 2))225#define MVPP2_WIN_SIZE(w) (0x4020 + ((w) << 2))226#define MVPP2_WIN_REMAP(w) (0x4040 + ((w) << 2))227#define MVPP2_BASE_ADDR_ENABLE 0x4060228 229/* AXI Bridge Registers */230#define MVPP22_AXI_BM_WR_ATTR_REG 0x4100231#define MVPP22_AXI_BM_RD_ATTR_REG 0x4104232#define MVPP22_AXI_AGGRQ_DESCR_RD_ATTR_REG 0x4110233#define MVPP22_AXI_TXQ_DESCR_WR_ATTR_REG 0x4114234#define MVPP22_AXI_TXQ_DESCR_RD_ATTR_REG 0x4118235#define MVPP22_AXI_RXQ_DESCR_WR_ATTR_REG 0x411c236#define MVPP22_AXI_RX_DATA_WR_ATTR_REG 0x4120237#define MVPP22_AXI_TX_DATA_RD_ATTR_REG 0x4130238#define MVPP22_AXI_RD_NORMAL_CODE_REG 0x4150239#define MVPP22_AXI_RD_SNOOP_CODE_REG 0x4154240#define MVPP22_AXI_WR_NORMAL_CODE_REG 0x4160241#define MVPP22_AXI_WR_SNOOP_CODE_REG 0x4164242 243/* Values for AXI Bridge registers */244#define MVPP22_AXI_ATTR_CACHE_OFFS 0245#define MVPP22_AXI_ATTR_DOMAIN_OFFS 12246 247#define MVPP22_AXI_CODE_CACHE_OFFS 0248#define MVPP22_AXI_CODE_DOMAIN_OFFS 4249 250#define MVPP22_AXI_CODE_CACHE_NON_CACHE 0x3251#define MVPP22_AXI_CODE_CACHE_WR_CACHE 0x7252#define MVPP22_AXI_CODE_CACHE_RD_CACHE 0xb253 254#define MVPP22_AXI_CODE_DOMAIN_OUTER_DOM 2255#define MVPP22_AXI_CODE_DOMAIN_SYSTEM 3256 257/* Interrupt Cause and Mask registers */258#define MVPP2_ISR_TX_THRESHOLD_REG(port) (0x5140 + 4 * (port))259#define MVPP2_MAX_ISR_TX_THRESHOLD 0xfffff0260 261#define MVPP2_ISR_RX_THRESHOLD_REG(rxq) (0x5200 + 4 * (rxq))262#define MVPP2_MAX_ISR_RX_THRESHOLD 0xfffff0263#define MVPP21_ISR_RXQ_GROUP_REG(port) (0x5400 + 4 * (port))264 265#define MVPP22_ISR_RXQ_GROUP_INDEX_REG 0x5400266#define MVPP22_ISR_RXQ_GROUP_INDEX_SUBGROUP_MASK 0xf267#define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_MASK 0x380268#define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET 7269 270#define MVPP22_ISR_RXQ_GROUP_INDEX_SUBGROUP_MASK 0xf271#define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_MASK 0x380272 273#define MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG 0x5404274#define MVPP22_ISR_RXQ_SUB_GROUP_STARTQ_MASK 0x1f275#define MVPP22_ISR_RXQ_SUB_GROUP_SIZE_MASK 0xf00276#define MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET 8277 278#define MVPP2_ISR_ENABLE_REG(port) (0x5420 + 4 * (port))279#define MVPP2_ISR_ENABLE_INTERRUPT(mask) ((mask) & 0xffff)280#define MVPP2_ISR_DISABLE_INTERRUPT(mask) (((mask) << 16) & 0xffff0000)281#define MVPP2_ISR_RX_TX_CAUSE_REG(port) (0x5480 + 4 * (port))282#define MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK(version) \283 ((version) == MVPP21 ? 0xffff : 0xff)284#define MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK 0xff0000285#define MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_OFFSET 16286#define MVPP2_CAUSE_RX_FIFO_OVERRUN_MASK BIT(24)287#define MVPP2_CAUSE_FCS_ERR_MASK BIT(25)288#define MVPP2_CAUSE_TX_FIFO_UNDERRUN_MASK BIT(26)289#define MVPP2_CAUSE_TX_EXCEPTION_SUM_MASK BIT(29)290#define MVPP2_CAUSE_RX_EXCEPTION_SUM_MASK BIT(30)291#define MVPP2_CAUSE_MISC_SUM_MASK BIT(31)292#define MVPP2_ISR_RX_TX_MASK_REG(port) (0x54a0 + 4 * (port))293#define MVPP2_ISR_PON_RX_TX_MASK_REG 0x54bc294#define MVPP2_PON_CAUSE_RXQ_OCCUP_DESC_ALL_MASK 0xffff295#define MVPP2_PON_CAUSE_TXP_OCCUP_DESC_ALL_MASK 0x3fc00000296#define MVPP2_PON_CAUSE_MISC_SUM_MASK BIT(31)297#define MVPP2_ISR_MISC_CAUSE_REG 0x55b0298#define MVPP2_ISR_RX_ERR_CAUSE_REG(port) (0x5520 + 4 * (port))299#define MVPP2_ISR_RX_ERR_CAUSE_NONOCC_MASK 0x00ff300 301/* Buffer Manager registers */302#define MVPP2_BM_POOL_BASE_REG(pool) (0x6000 + ((pool) * 4))303#define MVPP2_BM_POOL_BASE_ADDR_MASK 0xfffff80304#define MVPP2_BM_POOL_SIZE_REG(pool) (0x6040 + ((pool) * 4))305#define MVPP2_BM_POOL_SIZE_MASK 0xfff0306#define MVPP2_BM_POOL_READ_PTR_REG(pool) (0x6080 + ((pool) * 4))307#define MVPP2_BM_POOL_GET_READ_PTR_MASK 0xfff0308#define MVPP2_BM_POOL_PTRS_NUM_REG(pool) (0x60c0 + ((pool) * 4))309#define MVPP2_BM_POOL_PTRS_NUM_MASK 0xfff0310#define MVPP2_BM_BPPI_READ_PTR_REG(pool) (0x6100 + ((pool) * 4))311#define MVPP2_BM_BPPI_PTRS_NUM_REG(pool) (0x6140 + ((pool) * 4))312#define MVPP2_BM_BPPI_PTR_NUM_MASK 0x7ff313#define MVPP22_BM_POOL_PTRS_NUM_MASK 0xfff8314#define MVPP2_BM_BPPI_PREFETCH_FULL_MASK BIT(16)315#define MVPP2_BM_POOL_CTRL_REG(pool) (0x6200 + ((pool) * 4))316#define MVPP2_BM_START_MASK BIT(0)317#define MVPP2_BM_STOP_MASK BIT(1)318#define MVPP2_BM_STATE_MASK BIT(4)319#define MVPP2_BM_LOW_THRESH_OFFS 8320#define MVPP2_BM_LOW_THRESH_MASK 0x7f00321#define MVPP2_BM_LOW_THRESH_VALUE(val) ((val) << \322 MVPP2_BM_LOW_THRESH_OFFS)323#define MVPP2_BM_HIGH_THRESH_OFFS 16324#define MVPP2_BM_HIGH_THRESH_MASK 0x7f0000325#define MVPP2_BM_HIGH_THRESH_VALUE(val) ((val) << \326 MVPP2_BM_HIGH_THRESH_OFFS)327#define MVPP2_BM_BPPI_HIGH_THRESH 0x1E328#define MVPP2_BM_BPPI_LOW_THRESH 0x1C329#define MVPP23_BM_BPPI_HIGH_THRESH 0x34330#define MVPP23_BM_BPPI_LOW_THRESH 0x28331#define MVPP2_BM_INTR_CAUSE_REG(pool) (0x6240 + ((pool) * 4))332#define MVPP2_BM_RELEASED_DELAY_MASK BIT(0)333#define MVPP2_BM_ALLOC_FAILED_MASK BIT(1)334#define MVPP2_BM_BPPE_EMPTY_MASK BIT(2)335#define MVPP2_BM_BPPE_FULL_MASK BIT(3)336#define MVPP2_BM_AVAILABLE_BP_LOW_MASK BIT(4)337#define MVPP2_BM_INTR_MASK_REG(pool) (0x6280 + ((pool) * 4))338#define MVPP2_BM_PHY_ALLOC_REG(pool) (0x6400 + ((pool) * 4))339#define MVPP2_BM_PHY_ALLOC_GRNTD_MASK BIT(0)340#define MVPP2_BM_VIRT_ALLOC_REG 0x6440341#define MVPP22_BM_ADDR_HIGH_ALLOC 0x6444342#define MVPP22_BM_ADDR_HIGH_PHYS_MASK 0xff343#define MVPP22_BM_ADDR_HIGH_VIRT_MASK 0xff00344#define MVPP22_BM_ADDR_HIGH_VIRT_SHIFT 8345#define MVPP2_BM_PHY_RLS_REG(pool) (0x6480 + ((pool) * 4))346#define MVPP2_BM_PHY_RLS_MC_BUFF_MASK BIT(0)347#define MVPP2_BM_PHY_RLS_PRIO_EN_MASK BIT(1)348#define MVPP2_BM_PHY_RLS_GRNTD_MASK BIT(2)349#define MVPP2_BM_VIRT_RLS_REG 0x64c0350#define MVPP22_BM_ADDR_HIGH_RLS_REG 0x64c4351#define MVPP22_BM_ADDR_HIGH_PHYS_RLS_MASK 0xff352#define MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK 0xff00353#define MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT 8354 355/* Packet Processor per-port counters */356#define MVPP2_OVERRUN_ETH_DROP 0x7000357#define MVPP2_CLS_ETH_DROP 0x7020358 359#define MVPP22_BM_POOL_BASE_ADDR_HIGH_REG 0x6310360#define MVPP22_BM_POOL_BASE_ADDR_HIGH_MASK 0xff361#define MVPP23_BM_8POOL_MODE BIT(8)362 363/* Hit counters registers */364#define MVPP2_CTRS_IDX 0x7040365#define MVPP22_CTRS_TX_CTR(port, txq) ((txq) | ((port) << 3) | BIT(7))366#define MVPP2_TX_DESC_ENQ_CTR 0x7100367#define MVPP2_TX_DESC_ENQ_TO_DDR_CTR 0x7104368#define MVPP2_TX_BUFF_ENQ_TO_DDR_CTR 0x7108369#define MVPP2_TX_DESC_ENQ_HW_FWD_CTR 0x710c370#define MVPP2_RX_DESC_ENQ_CTR 0x7120371#define MVPP2_TX_PKTS_DEQ_CTR 0x7130372#define MVPP2_TX_PKTS_FULL_QUEUE_DROP_CTR 0x7200373#define MVPP2_TX_PKTS_EARLY_DROP_CTR 0x7204374#define MVPP2_TX_PKTS_BM_DROP_CTR 0x7208375#define MVPP2_TX_PKTS_BM_MC_DROP_CTR 0x720c376#define MVPP2_RX_PKTS_FULL_QUEUE_DROP_CTR 0x7220377#define MVPP2_RX_PKTS_EARLY_DROP_CTR 0x7224378#define MVPP2_RX_PKTS_BM_DROP_CTR 0x7228379#define MVPP2_CLS_DEC_TBL_HIT_CTR 0x7700380#define MVPP2_CLS_FLOW_TBL_HIT_CTR 0x7704381 382/* TX Scheduler registers */383#define MVPP2_TXP_SCHED_PORT_INDEX_REG 0x8000384#define MVPP2_TXP_SCHED_Q_CMD_REG 0x8004385#define MVPP2_TXP_SCHED_ENQ_MASK 0xff386#define MVPP2_TXP_SCHED_DISQ_OFFSET 8387#define MVPP2_TXP_SCHED_CMD_1_REG 0x8010388#define MVPP2_TXP_SCHED_FIXED_PRIO_REG 0x8014389#define MVPP2_TXP_SCHED_PERIOD_REG 0x8018390#define MVPP2_TXP_SCHED_MTU_REG 0x801c391#define MVPP2_TXP_MTU_MAX 0x7FFFF392#define MVPP2_TXP_SCHED_REFILL_REG 0x8020393#define MVPP2_TXP_REFILL_TOKENS_ALL_MASK 0x7ffff394#define MVPP2_TXP_REFILL_PERIOD_ALL_MASK 0x3ff00000395#define MVPP2_TXP_REFILL_PERIOD_MASK(v) ((v) << 20)396#define MVPP2_TXP_SCHED_TOKEN_SIZE_REG 0x8024397#define MVPP2_TXP_TOKEN_SIZE_MAX 0xffffffff398#define MVPP2_TXQ_SCHED_REFILL_REG(q) (0x8040 + ((q) << 2))399#define MVPP2_TXQ_REFILL_TOKENS_ALL_MASK 0x7ffff400#define MVPP2_TXQ_REFILL_PERIOD_ALL_MASK 0x3ff00000401#define MVPP2_TXQ_REFILL_PERIOD_MASK(v) ((v) << 20)402#define MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(q) (0x8060 + ((q) << 2))403#define MVPP2_TXQ_TOKEN_SIZE_MAX 0x7fffffff404#define MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(q) (0x8080 + ((q) << 2))405#define MVPP2_TXQ_TOKEN_CNTR_MAX 0xffffffff406 407/* TX general registers */408#define MVPP2_TX_SNOOP_REG 0x8800409#define MVPP2_TX_PORT_FLUSH_REG 0x8810410#define MVPP2_TX_PORT_FLUSH_MASK(port) (1 << (port))411 412/* LMS registers */413#define MVPP2_SRC_ADDR_MIDDLE 0x24414#define MVPP2_SRC_ADDR_HIGH 0x28415#define MVPP2_PHY_AN_CFG0_REG 0x34416#define MVPP2_PHY_AN_STOP_SMI0_MASK BIT(7)417#define MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG 0x305c418#define MVPP2_EXT_GLOBAL_CTRL_DEFAULT 0x27419 420/* Per-port registers */421#define MVPP2_GMAC_CTRL_0_REG 0x0422#define MVPP2_GMAC_PORT_EN_MASK BIT(0)423#define MVPP2_GMAC_PORT_TYPE_MASK BIT(1)424#define MVPP2_GMAC_MAX_RX_SIZE_OFFS 2425#define MVPP2_GMAC_MAX_RX_SIZE_MASK 0x7ffc426#define MVPP2_GMAC_MIB_CNTR_EN_MASK BIT(15)427#define MVPP2_GMAC_CTRL_1_REG 0x4428#define MVPP2_GMAC_PERIODIC_XON_EN_MASK BIT(1)429#define MVPP2_GMAC_GMII_LB_EN_MASK BIT(5)430#define MVPP2_GMAC_PCS_LB_EN_BIT 6431#define MVPP2_GMAC_PCS_LB_EN_MASK BIT(6)432#define MVPP2_GMAC_SA_LOW_OFFS 7433#define MVPP2_GMAC_CTRL_2_REG 0x8434#define MVPP2_GMAC_INBAND_AN_MASK BIT(0)435#define MVPP2_GMAC_FLOW_CTRL_MASK GENMASK(2, 1)436#define MVPP2_GMAC_PCS_ENABLE_MASK BIT(3)437#define MVPP2_GMAC_INTERNAL_CLK_MASK BIT(4)438#define MVPP2_GMAC_DISABLE_PADDING BIT(5)439#define MVPP2_GMAC_PORT_RESET_MASK BIT(6)440#define MVPP2_GMAC_AUTONEG_CONFIG 0xc441#define MVPP2_GMAC_FORCE_LINK_DOWN BIT(0)442#define MVPP2_GMAC_FORCE_LINK_PASS BIT(1)443#define MVPP2_GMAC_IN_BAND_AUTONEG BIT(2)444#define MVPP2_GMAC_IN_BAND_AUTONEG_BYPASS BIT(3)445#define MVPP2_GMAC_IN_BAND_RESTART_AN BIT(4)446#define MVPP2_GMAC_CONFIG_MII_SPEED BIT(5)447#define MVPP2_GMAC_CONFIG_GMII_SPEED BIT(6)448#define MVPP2_GMAC_AN_SPEED_EN BIT(7)449#define MVPP2_GMAC_FC_ADV_EN BIT(9)450#define MVPP2_GMAC_FC_ADV_ASM_EN BIT(10)451#define MVPP2_GMAC_FLOW_CTRL_AUTONEG BIT(11)452#define MVPP2_GMAC_CONFIG_FULL_DUPLEX BIT(12)453#define MVPP2_GMAC_AN_DUPLEX_EN BIT(13)454#define MVPP2_GMAC_STATUS0 0x10455#define MVPP2_GMAC_STATUS0_LINK_UP BIT(0)456#define MVPP2_GMAC_STATUS0_GMII_SPEED BIT(1)457#define MVPP2_GMAC_STATUS0_MII_SPEED BIT(2)458#define MVPP2_GMAC_STATUS0_FULL_DUPLEX BIT(3)459#define MVPP2_GMAC_STATUS0_RX_PAUSE BIT(4)460#define MVPP2_GMAC_STATUS0_TX_PAUSE BIT(5)461#define MVPP2_GMAC_STATUS0_AN_COMPLETE BIT(11)462#define MVPP2_GMAC_PORT_FIFO_CFG_1_REG 0x1c463#define MVPP2_GMAC_TX_FIFO_MIN_TH_OFFS 6464#define MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK 0x1fc0465#define MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(v) (((v) << 6) & \466 MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK)467#define MVPP22_GMAC_INT_STAT 0x20468#define MVPP22_GMAC_INT_STAT_LINK BIT(1)469#define MVPP22_GMAC_INT_MASK 0x24470#define MVPP22_GMAC_INT_MASK_LINK_STAT BIT(1)471#define MVPP22_GMAC_CTRL_4_REG 0x90472#define MVPP22_CTRL4_EXT_PIN_GMII_SEL BIT(0)473#define MVPP22_CTRL4_RX_FC_EN BIT(3)474#define MVPP22_CTRL4_TX_FC_EN BIT(4)475#define MVPP22_CTRL4_DP_CLK_SEL BIT(5)476#define MVPP22_CTRL4_SYNC_BYPASS_DIS BIT(6)477#define MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE BIT(7)478#define MVPP22_GMAC_INT_SUM_STAT 0xa0479#define MVPP22_GMAC_INT_SUM_STAT_INTERNAL BIT(1)480#define MVPP22_GMAC_INT_SUM_STAT_PTP BIT(2)481#define MVPP22_GMAC_INT_SUM_MASK 0xa4482#define MVPP22_GMAC_INT_SUM_MASK_LINK_STAT BIT(1)483#define MVPP22_GMAC_INT_SUM_MASK_PTP BIT(2)484 485/* Per-port XGMAC registers. PPv2.2 and PPv2.3, only for GOP port 0,486 * relative to port->base.487 */488#define MVPP22_XLG_CTRL0_REG 0x100489#define MVPP22_XLG_CTRL0_PORT_EN BIT(0)490#define MVPP22_XLG_CTRL0_MAC_RESET_DIS BIT(1)491#define MVPP22_XLG_CTRL0_FORCE_LINK_DOWN BIT(2)492#define MVPP22_XLG_CTRL0_FORCE_LINK_PASS BIT(3)493#define MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN BIT(7)494#define MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN BIT(8)495#define MVPP22_XLG_CTRL0_MIB_CNT_DIS BIT(14)496#define MVPP22_XLG_CTRL1_REG 0x104497#define MVPP22_XLG_CTRL1_FRAMESIZELIMIT_OFFS 0498#define MVPP22_XLG_CTRL1_FRAMESIZELIMIT_MASK 0x1fff499#define MVPP22_XLG_STATUS 0x10c500#define MVPP22_XLG_STATUS_LINK_UP BIT(0)501#define MVPP22_XLG_INT_STAT 0x114502#define MVPP22_XLG_INT_STAT_LINK BIT(1)503#define MVPP22_XLG_INT_MASK 0x118504#define MVPP22_XLG_INT_MASK_LINK BIT(1)505#define MVPP22_XLG_CTRL3_REG 0x11c506#define MVPP22_XLG_CTRL3_MACMODESELECT_MASK (7 << 13)507#define MVPP22_XLG_CTRL3_MACMODESELECT_GMAC (0 << 13)508#define MVPP22_XLG_CTRL3_MACMODESELECT_10G (1 << 13)509#define MVPP22_XLG_EXT_INT_STAT 0x158510#define MVPP22_XLG_EXT_INT_STAT_XLG BIT(1)511#define MVPP22_XLG_EXT_INT_STAT_PTP BIT(7)512#define MVPP22_XLG_EXT_INT_MASK 0x15c513#define MVPP22_XLG_EXT_INT_MASK_XLG BIT(1)514#define MVPP22_XLG_EXT_INT_MASK_GIG BIT(2)515#define MVPP22_XLG_EXT_INT_MASK_PTP BIT(7)516#define MVPP22_XLG_CTRL4_REG 0x184517#define MVPP22_XLG_CTRL4_FWD_FC BIT(5)518#define MVPP22_XLG_CTRL4_FWD_PFC BIT(6)519#define MVPP22_XLG_CTRL4_MACMODSELECT_GMAC BIT(12)520#define MVPP22_XLG_CTRL4_EN_IDLE_CHECK BIT(14)521 522/* SMI registers. PPv2.2 and PPv2.3, relative to priv->iface_base. */523#define MVPP22_SMI_MISC_CFG_REG 0x1204524#define MVPP22_SMI_POLLING_EN BIT(10)525 526/* TAI registers, PPv2.2 only, relative to priv->iface_base */527#define MVPP22_TAI_INT_CAUSE 0x1400528#define MVPP22_TAI_INT_MASK 0x1404529#define MVPP22_TAI_CR0 0x1408530#define MVPP22_TAI_CR1 0x140c531#define MVPP22_TAI_TCFCR0 0x1410532#define MVPP22_TAI_TCFCR1 0x1414533#define MVPP22_TAI_TCFCR2 0x1418534#define MVPP22_TAI_FATWR 0x141c535#define MVPP22_TAI_TOD_STEP_NANO_CR 0x1420536#define MVPP22_TAI_TOD_STEP_FRAC_HIGH 0x1424537#define MVPP22_TAI_TOD_STEP_FRAC_LOW 0x1428538#define MVPP22_TAI_TAPDC_HIGH 0x142c539#define MVPP22_TAI_TAPDC_LOW 0x1430540#define MVPP22_TAI_TGTOD_SEC_HIGH 0x1434541#define MVPP22_TAI_TGTOD_SEC_MED 0x1438542#define MVPP22_TAI_TGTOD_SEC_LOW 0x143c543#define MVPP22_TAI_TGTOD_NANO_HIGH 0x1440544#define MVPP22_TAI_TGTOD_NANO_LOW 0x1444545#define MVPP22_TAI_TGTOD_FRAC_HIGH 0x1448546#define MVPP22_TAI_TGTOD_FRAC_LOW 0x144c547#define MVPP22_TAI_TLV_SEC_HIGH 0x1450548#define MVPP22_TAI_TLV_SEC_MED 0x1454549#define MVPP22_TAI_TLV_SEC_LOW 0x1458550#define MVPP22_TAI_TLV_NANO_HIGH 0x145c551#define MVPP22_TAI_TLV_NANO_LOW 0x1460552#define MVPP22_TAI_TLV_FRAC_HIGH 0x1464553#define MVPP22_TAI_TLV_FRAC_LOW 0x1468554#define MVPP22_TAI_TCV0_SEC_HIGH 0x146c555#define MVPP22_TAI_TCV0_SEC_MED 0x1470556#define MVPP22_TAI_TCV0_SEC_LOW 0x1474557#define MVPP22_TAI_TCV0_NANO_HIGH 0x1478558#define MVPP22_TAI_TCV0_NANO_LOW 0x147c559#define MVPP22_TAI_TCV0_FRAC_HIGH 0x1480560#define MVPP22_TAI_TCV0_FRAC_LOW 0x1484561#define MVPP22_TAI_TCV1_SEC_HIGH 0x1488562#define MVPP22_TAI_TCV1_SEC_MED 0x148c563#define MVPP22_TAI_TCV1_SEC_LOW 0x1490564#define MVPP22_TAI_TCV1_NANO_HIGH 0x1494565#define MVPP22_TAI_TCV1_NANO_LOW 0x1498566#define MVPP22_TAI_TCV1_FRAC_HIGH 0x149c567#define MVPP22_TAI_TCV1_FRAC_LOW 0x14a0568#define MVPP22_TAI_TCSR 0x14a4569#define MVPP22_TAI_TUC_LSB 0x14a8570#define MVPP22_TAI_GFM_SEC_HIGH 0x14ac571#define MVPP22_TAI_GFM_SEC_MED 0x14b0572#define MVPP22_TAI_GFM_SEC_LOW 0x14b4573#define MVPP22_TAI_GFM_NANO_HIGH 0x14b8574#define MVPP22_TAI_GFM_NANO_LOW 0x14bc575#define MVPP22_TAI_GFM_FRAC_HIGH 0x14c0576#define MVPP22_TAI_GFM_FRAC_LOW 0x14c4577#define MVPP22_TAI_PCLK_DA_HIGH 0x14c8578#define MVPP22_TAI_PCLK_DA_LOW 0x14cc579#define MVPP22_TAI_CTCR 0x14d0580#define MVPP22_TAI_PCLK_CCC_HIGH 0x14d4581#define MVPP22_TAI_PCLK_CCC_LOW 0x14d8582#define MVPP22_TAI_DTC_HIGH 0x14dc583#define MVPP22_TAI_DTC_LOW 0x14e0584#define MVPP22_TAI_CCC_HIGH 0x14e4585#define MVPP22_TAI_CCC_LOW 0x14e8586#define MVPP22_TAI_ICICE 0x14f4587#define MVPP22_TAI_ICICC_LOW 0x14f8588#define MVPP22_TAI_TUC_MSB 0x14fc589 590#define MVPP22_GMAC_BASE(port) (0x7000 + (port) * 0x1000 + 0xe00)591 592#define MVPP2_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff593 594/* Descriptor ring Macros */595#define MVPP2_QUEUE_NEXT_DESC(q, index) \596 (((index) < (q)->last_desc) ? ((index) + 1) : 0)597 598/* XPCS registers.PPv2.2 and PPv2.3 */599#define MVPP22_MPCS_BASE(port) (0x7000 + (port) * 0x1000)600#define MVPP22_MPCS_CTRL 0x14601#define MVPP22_MPCS_CTRL_FWD_ERR_CONN BIT(10)602#define MVPP22_MPCS_CLK_RESET 0x14c603#define MAC_CLK_RESET_SD_TX BIT(0)604#define MAC_CLK_RESET_SD_RX BIT(1)605#define MAC_CLK_RESET_MAC BIT(2)606#define MVPP22_MPCS_CLK_RESET_DIV_RATIO(n) ((n) << 4)607#define MVPP22_MPCS_CLK_RESET_DIV_SET BIT(11)608 609/* FCA registers. PPv2.2 and PPv2.3 */610#define MVPP22_FCA_BASE(port) (0x7600 + (port) * 0x1000)611#define MVPP22_FCA_REG_SIZE 16612#define MVPP22_FCA_REG_MASK 0xFFFF613#define MVPP22_FCA_CONTROL_REG 0x0614#define MVPP22_FCA_ENABLE_PERIODIC BIT(11)615#define MVPP22_PERIODIC_COUNTER_LSB_REG (0x110)616#define MVPP22_PERIODIC_COUNTER_MSB_REG (0x114)617 618/* XPCS registers. PPv2.2 and PPv2.3 */619#define MVPP22_XPCS_BASE(port) (0x7400 + (port) * 0x1000)620#define MVPP22_XPCS_CFG0 0x0621#define MVPP22_XPCS_CFG0_RESET_DIS BIT(0)622#define MVPP22_XPCS_CFG0_PCS_MODE(n) ((n) << 3)623#define MVPP22_XPCS_CFG0_ACTIVE_LANE(n) ((n) << 5)624 625/* PTP registers. PPv2.2 only */626#define MVPP22_PTP_BASE(port) (0x7800 + (port * 0x1000))627#define MVPP22_PTP_INT_CAUSE 0x00628#define MVPP22_PTP_INT_CAUSE_QUEUE1 BIT(6)629#define MVPP22_PTP_INT_CAUSE_QUEUE0 BIT(5)630#define MVPP22_PTP_INT_MASK 0x04631#define MVPP22_PTP_INT_MASK_QUEUE1 BIT(6)632#define MVPP22_PTP_INT_MASK_QUEUE0 BIT(5)633#define MVPP22_PTP_GCR 0x08634#define MVPP22_PTP_GCR_RX_RESET BIT(13)635#define MVPP22_PTP_GCR_TX_RESET BIT(1)636#define MVPP22_PTP_GCR_TSU_ENABLE BIT(0)637#define MVPP22_PTP_TX_Q0_R0 0x0c638#define MVPP22_PTP_TX_Q0_R1 0x10639#define MVPP22_PTP_TX_Q0_R2 0x14640#define MVPP22_PTP_TX_Q1_R0 0x18641#define MVPP22_PTP_TX_Q1_R1 0x1c642#define MVPP22_PTP_TX_Q1_R2 0x20643#define MVPP22_PTP_TPCR 0x24644#define MVPP22_PTP_V1PCR 0x28645#define MVPP22_PTP_V2PCR 0x2c646#define MVPP22_PTP_Y1731PCR 0x30647#define MVPP22_PTP_NTPTSPCR 0x34648#define MVPP22_PTP_NTPRXPCR 0x38649#define MVPP22_PTP_NTPTXPCR 0x3c650#define MVPP22_PTP_WAMPPCR 0x40651#define MVPP22_PTP_NAPCR 0x44652#define MVPP22_PTP_FAPCR 0x48653#define MVPP22_PTP_CAPCR 0x50654#define MVPP22_PTP_ATAPCR 0x54655#define MVPP22_PTP_ACTAPCR 0x58656#define MVPP22_PTP_CATAPCR 0x5c657#define MVPP22_PTP_CACTAPCR 0x60658#define MVPP22_PTP_AITAPCR 0x64659#define MVPP22_PTP_CAITAPCR 0x68660#define MVPP22_PTP_CITAPCR 0x6c661#define MVPP22_PTP_NTP_OFF_HIGH 0x70662#define MVPP22_PTP_NTP_OFF_LOW 0x74663#define MVPP22_PTP_TX_PIPE_STATUS_DELAY 0x78664 665/* System controller registers. Accessed through a regmap. */666#define GENCONF_SOFT_RESET1 0x1108667#define GENCONF_SOFT_RESET1_GOP BIT(6)668#define GENCONF_PORT_CTRL0 0x1110669#define GENCONF_PORT_CTRL0_BUS_WIDTH_SELECT BIT(1)670#define GENCONF_PORT_CTRL0_RX_DATA_SAMPLE BIT(29)671#define GENCONF_PORT_CTRL0_CLK_DIV_PHASE_CLR BIT(31)672#define GENCONF_PORT_CTRL1 0x1114673#define GENCONF_PORT_CTRL1_EN(p) BIT(p)674#define GENCONF_PORT_CTRL1_RESET(p) (BIT(p) << 28)675#define GENCONF_CTRL0 0x1120676#define GENCONF_CTRL0_PORT2_RGMII BIT(0)677#define GENCONF_CTRL0_PORT3_RGMII_MII BIT(1)678#define GENCONF_CTRL0_PORT3_RGMII BIT(2)679 680/* Various constants */681 682/* Coalescing */683#define MVPP2_TXDONE_COAL_PKTS_THRESH 64684#define MVPP2_TXDONE_HRTIMER_PERIOD_NS 1000000UL685#define MVPP2_TXDONE_COAL_USEC 1000686#define MVPP2_RX_COAL_PKTS 32687#define MVPP2_RX_COAL_USEC 64688 689/* The two bytes Marvell header. Either contains a special value used690 * by Marvell switches when a specific hardware mode is enabled (not691 * supported by this driver) or is filled automatically by zeroes on692 * the RX side. Those two bytes being at the front of the Ethernet693 * header, they allow to have the IP header aligned on a 4 bytes694 * boundary automatically: the hardware skips those two bytes on its695 * own.696 */697#define MVPP2_MH_SIZE 2698#define MVPP2_ETH_TYPE_LEN 2699#define MVPP2_PPPOE_HDR_SIZE 8700#define MVPP2_VLAN_TAG_LEN 4701#define MVPP2_VLAN_TAG_EDSA_LEN 8702 703/* Lbtd 802.3 type */704#define MVPP2_IP_LBDT_TYPE 0xfffa705 706#define MVPP2_TX_CSUM_MAX_SIZE 9800707 708/* Timeout constants */709#define MVPP2_TX_DISABLE_TIMEOUT_MSEC 1000710#define MVPP2_TX_PENDING_TIMEOUT_MSEC 1000711 712#define MVPP2_TX_MTU_MAX 0x7ffff713 714/* Maximum number of T-CONTs of PON port */715#define MVPP2_MAX_TCONT 16716 717/* Maximum number of supported ports */718#define MVPP2_MAX_PORTS 4719 720/* Loopback port index */721#define MVPP2_LOOPBACK_PORT_INDEX 3722 723/* Maximum number of TXQs used by single port */724#define MVPP2_MAX_TXQ 8725 726/* MVPP2_MAX_TSO_SEGS is the maximum number of fragments to allow in the GSO727 * skb. As we need a maxium of two descriptors per fragments (1 header, 1 data),728 * multiply this value by two to count the maximum number of skb descs needed.729 */730#define MVPP2_MAX_TSO_SEGS 300731#define MVPP2_MAX_SKB_DESCS (MVPP2_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS)732 733/* Max number of RXQs per port */734#define MVPP2_PORT_MAX_RXQ 32735 736/* Max number of Rx descriptors */737#define MVPP2_MAX_RXD_MAX 2048738#define MVPP2_MAX_RXD_DFLT 1024739 740/* Max number of Tx descriptors */741#define MVPP2_MAX_TXD_MAX 2048742#define MVPP2_MAX_TXD_DFLT 1024743 744/* Amount of Tx descriptors that can be reserved at once by CPU */745#define MVPP2_CPU_DESC_CHUNK 64746 747/* Max number of Tx descriptors in each aggregated queue */748#define MVPP2_AGGR_TXQ_SIZE 256749 750/* Descriptor aligned size */751#define MVPP2_DESC_ALIGNED_SIZE 32752 753/* Descriptor alignment mask */754#define MVPP2_TX_DESC_ALIGN (MVPP2_DESC_ALIGNED_SIZE - 1)755 756/* RX FIFO constants */757#define MVPP2_RX_FIFO_PORT_DATA_SIZE_44KB 0xb000758#define MVPP2_RX_FIFO_PORT_DATA_SIZE_32KB 0x8000759#define MVPP2_RX_FIFO_PORT_DATA_SIZE_8KB 0x2000760#define MVPP2_RX_FIFO_PORT_DATA_SIZE_4KB 0x1000761#define MVPP2_RX_FIFO_PORT_ATTR_SIZE(data_size) ((data_size) >> 6)762#define MVPP2_RX_FIFO_PORT_ATTR_SIZE_4KB 0x40763#define MVPP2_RX_FIFO_PORT_MIN_PKT 0x80764 765/* TX FIFO constants */766#define MVPP22_TX_FIFO_DATA_SIZE_18KB 18767#define MVPP22_TX_FIFO_DATA_SIZE_10KB 10768#define MVPP22_TX_FIFO_DATA_SIZE_1KB 1769#define MVPP2_TX_FIFO_THRESHOLD_MIN 256 /* Bytes */770#define MVPP2_TX_FIFO_THRESHOLD(kb) \771 ((kb) * 1024 - MVPP2_TX_FIFO_THRESHOLD_MIN)772 773/* RX FIFO threshold in 1KB granularity */774#define MVPP23_PORT0_FIFO_TRSH (9 * 1024)775#define MVPP23_PORT1_FIFO_TRSH (4 * 1024)776#define MVPP23_PORT2_FIFO_TRSH (2 * 1024)777 778/* RX Flow Control Registers */779#define MVPP2_RX_FC_REG(port) (0x150 + 4 * (port))780#define MVPP2_RX_FC_EN BIT(24)781#define MVPP2_RX_FC_TRSH_OFFS 16782#define MVPP2_RX_FC_TRSH_MASK (0xFF << MVPP2_RX_FC_TRSH_OFFS)783#define MVPP2_RX_FC_TRSH_UNIT 256784 785/* MSS Flow control */786#define MSS_FC_COM_REG 0787#define FLOW_CONTROL_ENABLE_BIT BIT(0)788#define FLOW_CONTROL_UPDATE_COMMAND_BIT BIT(31)789#define FC_QUANTA 0xFFFF790#define FC_CLK_DIVIDER 100791 792#define MSS_RXQ_TRESH_BASE 0x200793#define MSS_RXQ_TRESH_OFFS 4794#define MSS_RXQ_TRESH_REG(q, fq) (MSS_RXQ_TRESH_BASE + (((q) + (fq)) \795 * MSS_RXQ_TRESH_OFFS))796 797#define MSS_BUF_POOL_BASE 0x40798#define MSS_BUF_POOL_OFFS 4799#define MSS_BUF_POOL_REG(id) (MSS_BUF_POOL_BASE \800 + (id) * MSS_BUF_POOL_OFFS)801 802#define MSS_BUF_POOL_STOP_MASK 0xFFF803#define MSS_BUF_POOL_START_MASK (0xFFF << MSS_BUF_POOL_START_OFFS)804#define MSS_BUF_POOL_START_OFFS 12805#define MSS_BUF_POOL_PORTS_MASK (0xF << MSS_BUF_POOL_PORTS_OFFS)806#define MSS_BUF_POOL_PORTS_OFFS 24807#define MSS_BUF_POOL_PORT_OFFS(id) (0x1 << \808 ((id) + MSS_BUF_POOL_PORTS_OFFS))809 810#define MSS_RXQ_TRESH_START_MASK 0xFFFF811#define MSS_RXQ_TRESH_STOP_MASK (0xFFFF << MSS_RXQ_TRESH_STOP_OFFS)812#define MSS_RXQ_TRESH_STOP_OFFS 16813 814#define MSS_RXQ_ASS_BASE 0x80815#define MSS_RXQ_ASS_OFFS 4816#define MSS_RXQ_ASS_PER_REG 4817#define MSS_RXQ_ASS_PER_OFFS 8818#define MSS_RXQ_ASS_PORTID_OFFS 0819#define MSS_RXQ_ASS_PORTID_MASK 0x3820#define MSS_RXQ_ASS_HOSTID_OFFS 2821#define MSS_RXQ_ASS_HOSTID_MASK 0x3F822 823#define MSS_RXQ_ASS_Q_BASE(q, fq) ((((q) + (fq)) % MSS_RXQ_ASS_PER_REG) \824 * MSS_RXQ_ASS_PER_OFFS)825#define MSS_RXQ_ASS_PQ_BASE(q, fq) ((((q) + (fq)) / MSS_RXQ_ASS_PER_REG) \826 * MSS_RXQ_ASS_OFFS)827#define MSS_RXQ_ASS_REG(q, fq) (MSS_RXQ_ASS_BASE + MSS_RXQ_ASS_PQ_BASE(q, fq))828 829#define MSS_THRESHOLD_STOP 768830#define MSS_THRESHOLD_START 1024831#define MSS_FC_MAX_TIMEOUT 5000832 833/* RX buffer constants */834#define MVPP2_SKB_SHINFO_SIZE \835 SKB_DATA_ALIGN(sizeof(struct skb_shared_info))836 837#define MVPP2_RX_PKT_SIZE(mtu) \838 ALIGN((mtu) + MVPP2_MH_SIZE + MVPP2_VLAN_TAG_LEN + \839 ETH_HLEN + ETH_FCS_LEN, cache_line_size())840 841#define MVPP2_RX_BUF_SIZE(pkt_size) ((pkt_size) + MVPP2_SKB_HEADROOM)842#define MVPP2_RX_TOTAL_SIZE(buf_size) ((buf_size) + MVPP2_SKB_SHINFO_SIZE)843#define MVPP2_RX_MAX_PKT_SIZE(total_size) \844 ((total_size) - MVPP2_SKB_HEADROOM - MVPP2_SKB_SHINFO_SIZE)845 846#define MVPP2_MAX_RX_BUF_SIZE (PAGE_SIZE - MVPP2_SKB_SHINFO_SIZE - MVPP2_SKB_HEADROOM)847 848#define MVPP2_BIT_TO_BYTE(bit) ((bit) / 8)849#define MVPP2_BIT_TO_WORD(bit) ((bit) / 32)850#define MVPP2_BIT_IN_WORD(bit) ((bit) % 32)851 852#define MVPP2_N_PRS_FLOWS 52853#define MVPP2_N_RFS_ENTRIES_PER_FLOW 4854 855/* There are 7 supported high-level flows */856#define MVPP2_N_RFS_RULES (MVPP2_N_RFS_ENTRIES_PER_FLOW * 7)857 858/* RSS constants */859#define MVPP22_N_RSS_TABLES 8860#define MVPP22_RSS_TABLE_ENTRIES 32861 862/* IPv6 max L3 address size */863#define MVPP2_MAX_L3_ADDR_SIZE 16864 865/* Port flags */866#define MVPP2_F_LOOPBACK BIT(0)867#define MVPP2_F_DT_COMPAT BIT(1)868 869/* Marvell tag types */870enum mvpp2_tag_type {871 MVPP2_TAG_TYPE_NONE = 0,872 MVPP2_TAG_TYPE_MH = 1,873 MVPP2_TAG_TYPE_DSA = 2,874 MVPP2_TAG_TYPE_EDSA = 3,875 MVPP2_TAG_TYPE_VLAN = 4,876 MVPP2_TAG_TYPE_LAST = 5877};878 879/* L2 cast enum */880enum mvpp2_prs_l2_cast {881 MVPP2_PRS_L2_UNI_CAST,882 MVPP2_PRS_L2_MULTI_CAST,883};884 885/* L3 cast enum */886enum mvpp2_prs_l3_cast {887 MVPP2_PRS_L3_UNI_CAST,888 MVPP2_PRS_L3_MULTI_CAST,889 MVPP2_PRS_L3_BROAD_CAST890};891 892/* PTP descriptor constants. The low bits of the descriptor are stored893 * separately from the high bits.894 */895#define MVPP22_PTP_DESC_MASK_LOW 0xfff896 897/* PTPAction */898enum mvpp22_ptp_action {899 MVPP22_PTP_ACTION_NONE = 0,900 MVPP22_PTP_ACTION_FORWARD = 1,901 MVPP22_PTP_ACTION_CAPTURE = 3,902 /* The following have not been verified */903 MVPP22_PTP_ACTION_ADDTIME = 4,904 MVPP22_PTP_ACTION_ADDCORRECTEDTIME = 5,905 MVPP22_PTP_ACTION_CAPTUREADDTIME = 6,906 MVPP22_PTP_ACTION_CAPTUREADDCORRECTEDTIME = 7,907 MVPP22_PTP_ACTION_ADDINGRESSTIME = 8,908 MVPP22_PTP_ACTION_CAPTUREADDINGRESSTIME = 9,909 MVPP22_PTP_ACTION_CAPTUREINGRESSTIME = 10,910};911 912/* PTPPacketFormat */913enum mvpp22_ptp_packet_format {914 MVPP22_PTP_PKT_FMT_PTPV2 = 0,915 MVPP22_PTP_PKT_FMT_PTPV1 = 1,916 MVPP22_PTP_PKT_FMT_Y1731 = 2,917 MVPP22_PTP_PKT_FMT_NTPTS = 3,918 MVPP22_PTP_PKT_FMT_NTPRX = 4,919 MVPP22_PTP_PKT_FMT_NTPTX = 5,920 MVPP22_PTP_PKT_FMT_TWAMP = 6,921};922 923#define MVPP22_PTP_ACTION(x) (((x) & 15) << 0)924#define MVPP22_PTP_PACKETFORMAT(x) (((x) & 7) << 4)925#define MVPP22_PTP_MACTIMESTAMPINGEN BIT(11)926#define MVPP22_PTP_TIMESTAMPENTRYID(x) (((x) & 31) << 12)927#define MVPP22_PTP_TIMESTAMPQUEUESELECT BIT(18)928 929/* BM constants */930#define MVPP2_BM_JUMBO_BUF_NUM 2048931#define MVPP2_BM_LONG_BUF_NUM 2048932#define MVPP2_BM_SHORT_BUF_NUM 2048933#define MVPP2_BM_POOL_SIZE_MAX (16*1024 - MVPP2_BM_POOL_PTR_ALIGN/4)934#define MVPP2_BM_POOL_PTR_ALIGN 128935#define MVPP2_BM_MAX_POOLS 8936 937/* BM cookie (32 bits) definition */938#define MVPP2_BM_COOKIE_POOL_OFFS 8939#define MVPP2_BM_COOKIE_CPU_OFFS 24940 941#define MVPP2_BM_SHORT_FRAME_SIZE 736 /* frame size 128 */942#define MVPP2_BM_LONG_FRAME_SIZE 2240 /* frame size 1664 */943#define MVPP2_BM_JUMBO_FRAME_SIZE 10432 /* frame size 9856 */944/* BM short pool packet size945 * These value assure that for SWF the total number946 * of bytes allocated for each buffer will be 512947 */948#define MVPP2_BM_SHORT_PKT_SIZE MVPP2_RX_MAX_PKT_SIZE(MVPP2_BM_SHORT_FRAME_SIZE)949#define MVPP2_BM_LONG_PKT_SIZE MVPP2_RX_MAX_PKT_SIZE(MVPP2_BM_LONG_FRAME_SIZE)950#define MVPP2_BM_JUMBO_PKT_SIZE MVPP2_RX_MAX_PKT_SIZE(MVPP2_BM_JUMBO_FRAME_SIZE)951 952#define MVPP21_ADDR_SPACE_SZ 0953#define MVPP22_ADDR_SPACE_SZ SZ_64K954 955#define MVPP2_MAX_THREADS 9956#define MVPP2_MAX_QVECS MVPP2_MAX_THREADS957 958/* GMAC MIB Counters register definitions */959#define MVPP21_MIB_COUNTERS_OFFSET 0x1000960#define MVPP21_MIB_COUNTERS_PORT_SZ 0x400961#define MVPP22_MIB_COUNTERS_OFFSET 0x0962#define MVPP22_MIB_COUNTERS_PORT_SZ 0x100963 964#define MVPP2_MIB_GOOD_OCTETS_RCVD 0x0965#define MVPP2_MIB_BAD_OCTETS_RCVD 0x8966#define MVPP2_MIB_CRC_ERRORS_SENT 0xc967#define MVPP2_MIB_UNICAST_FRAMES_RCVD 0x10968#define MVPP2_MIB_BROADCAST_FRAMES_RCVD 0x18969#define MVPP2_MIB_MULTICAST_FRAMES_RCVD 0x1c970#define MVPP2_MIB_FRAMES_64_OCTETS 0x20971#define MVPP2_MIB_FRAMES_65_TO_127_OCTETS 0x24972#define MVPP2_MIB_FRAMES_128_TO_255_OCTETS 0x28973#define MVPP2_MIB_FRAMES_256_TO_511_OCTETS 0x2c974#define MVPP2_MIB_FRAMES_512_TO_1023_OCTETS 0x30975#define MVPP2_MIB_FRAMES_1024_TO_MAX_OCTETS 0x34976#define MVPP2_MIB_GOOD_OCTETS_SENT 0x38977#define MVPP2_MIB_UNICAST_FRAMES_SENT 0x40978#define MVPP2_MIB_MULTICAST_FRAMES_SENT 0x48979#define MVPP2_MIB_BROADCAST_FRAMES_SENT 0x4c980#define MVPP2_MIB_FC_SENT 0x54981#define MVPP2_MIB_FC_RCVD 0x58982#define MVPP2_MIB_RX_FIFO_OVERRUN 0x5c983#define MVPP2_MIB_UNDERSIZE_RCVD 0x60984#define MVPP2_MIB_FRAGMENTS_RCVD 0x64985#define MVPP2_MIB_OVERSIZE_RCVD 0x68986#define MVPP2_MIB_JABBER_RCVD 0x6c987#define MVPP2_MIB_MAC_RCV_ERROR 0x70988#define MVPP2_MIB_BAD_CRC_EVENT 0x74989#define MVPP2_MIB_COLLISION 0x78990#define MVPP2_MIB_LATE_COLLISION 0x7c991 992#define MVPP2_MIB_COUNTERS_STATS_DELAY (1 * HZ)993 994#define MVPP2_DESC_DMA_MASK DMA_BIT_MASK(40)995 996/* Buffer header info bits */997#define MVPP2_B_HDR_INFO_MC_ID_MASK 0xfff998#define MVPP2_B_HDR_INFO_MC_ID(info) ((info) & MVPP2_B_HDR_INFO_MC_ID_MASK)999#define MVPP2_B_HDR_INFO_LAST_OFFS 121000#define MVPP2_B_HDR_INFO_LAST_MASK BIT(12)1001#define MVPP2_B_HDR_INFO_IS_LAST(info) \1002 (((info) & MVPP2_B_HDR_INFO_LAST_MASK) >> MVPP2_B_HDR_INFO_LAST_OFFS)1003 1004struct mvpp2_tai;1005 1006/* Definitions */1007struct mvpp2_dbgfs_entries;1008 1009struct mvpp2_rss_table {1010 u32 indir[MVPP22_RSS_TABLE_ENTRIES];1011};1012 1013struct mvpp2_buff_hdr {1014 __le32 next_phys_addr;1015 __le32 next_dma_addr;1016 __le16 byte_count;1017 __le16 info;1018 __le16 reserved1; /* bm_qset (for future use, BM) */1019 u8 next_phys_addr_high;1020 u8 next_dma_addr_high;1021 __le16 reserved2;1022 __le16 reserved3;1023 __le16 reserved4;1024 __le16 reserved5;1025};1026 1027/* Shared Packet Processor resources */1028struct mvpp2 {1029 /* Shared registers' base addresses */1030 void __iomem *lms_base;1031 void __iomem *iface_base;1032 void __iomem *cm3_base;1033 1034 /* On PPv2.2 and PPv2.3, each "software thread" can access the base1035 * register through a separate address space, each 64 KB apart1036 * from each other. Typically, such address spaces will be1037 * used per CPU.1038 */1039 void __iomem *swth_base[MVPP2_MAX_THREADS];1040 1041 /* On PPv2.2 and PPv2.3, some port control registers are located into1042 * the system controller space. These registers are accessible1043 * through a regmap.1044 */1045 struct regmap *sysctrl_base;1046 1047 /* Common clocks */1048 struct clk *pp_clk;1049 struct clk *gop_clk;1050 struct clk *mg_clk;1051 struct clk *mg_core_clk;1052 struct clk *axi_clk;1053 1054 /* List of pointers to port structures */1055 int port_count;1056 struct mvpp2_port *port_list[MVPP2_MAX_PORTS];1057 /* Map of enabled ports */1058 unsigned long port_map;1059 1060 struct mvpp2_tai *tai;1061 1062 /* Number of Tx threads used */1063 unsigned int nthreads;1064 /* Map of threads needing locking */1065 unsigned long lock_map;1066 1067 /* Aggregated TXQs */1068 struct mvpp2_tx_queue *aggr_txqs;1069 1070 /* Are we using page_pool with per-cpu pools? */1071 int percpu_pools;1072 1073 /* BM pools */1074 struct mvpp2_bm_pool *bm_pools;1075 1076 /* PRS shadow table */1077 struct mvpp2_prs_shadow *prs_shadow;1078 /* PRS auxiliary table for double vlan entries control */1079 bool *prs_double_vlans;1080 1081 /* Tclk value */1082 u32 tclk;1083 1084 /* HW version */1085 enum { MVPP21, MVPP22, MVPP23 } hw_version;1086 1087 /* Maximum number of RXQs per port */1088 unsigned int max_port_rxqs;1089 1090 /* Workqueue to gather hardware statistics */1091 char queue_name[31];1092 struct workqueue_struct *stats_queue;1093 1094 /* Debugfs root entry */1095 struct dentry *dbgfs_dir;1096 1097 /* Debugfs entries private data */1098 struct mvpp2_dbgfs_entries *dbgfs_entries;1099 1100 /* RSS Indirection tables */1101 struct mvpp2_rss_table *rss_tables[MVPP22_N_RSS_TABLES];1102 1103 /* page_pool allocator */1104 struct page_pool *page_pool[MVPP2_PORT_MAX_RXQ];1105 1106 /* Global TX Flow Control config */1107 bool global_tx_fc;1108 1109 /* Spinlocks for CM3 shared memory configuration */1110 spinlock_t mss_spinlock;1111};1112 1113struct mvpp2_pcpu_stats {1114 struct u64_stats_sync syncp;1115 u64 rx_packets;1116 u64 rx_bytes;1117 u64 tx_packets;1118 u64 tx_bytes;1119 /* XDP */1120 u64 xdp_redirect;1121 u64 xdp_pass;1122 u64 xdp_drop;1123 u64 xdp_xmit;1124 u64 xdp_xmit_err;1125 u64 xdp_tx;1126 u64 xdp_tx_err;1127};1128 1129/* Per-CPU port control */1130struct mvpp2_port_pcpu {1131 struct hrtimer tx_done_timer;1132 struct net_device *dev;1133 bool timer_scheduled;1134};1135 1136struct mvpp2_queue_vector {1137 int irq;1138 struct napi_struct napi;1139 enum { MVPP2_QUEUE_VECTOR_SHARED, MVPP2_QUEUE_VECTOR_PRIVATE } type;1140 int sw_thread_id;1141 u16 sw_thread_mask;1142 int first_rxq;1143 int nrxqs;1144 u32 pending_cause_rx;1145 struct mvpp2_port *port;1146 struct cpumask *mask;1147};1148 1149/* Internal represention of a Flow Steering rule */1150struct mvpp2_rfs_rule {1151 /* Rule location inside the flow*/1152 int loc;1153 1154 /* Flow type, such as TCP_V4_FLOW, IP6_FLOW, etc. */1155 int flow_type;1156 1157 /* Index of the C2 TCAM entry handling this rule */1158 int c2_index;1159 1160 /* Header fields that needs to be extracted to match this flow */1161 u16 hek_fields;1162 1163 /* CLS engine : only c2 is supported for now. */1164 u8 engine;1165 1166 /* TCAM key and mask for C2-based steering. These fields should be1167 * encapsulated in a union should we add more engines.1168 */1169 u64 c2_tcam;1170 u64 c2_tcam_mask;1171 1172 struct flow_rule *flow;1173};1174 1175struct mvpp2_ethtool_fs {1176 struct mvpp2_rfs_rule rule;1177 struct ethtool_rxnfc rxnfc;1178};1179 1180struct mvpp2_hwtstamp_queue {1181 struct sk_buff *skb[32];1182 u8 next;1183};1184 1185struct mvpp2_port {1186 u8 id;1187 1188 /* Index of the port from the "group of ports" complex point1189 * of view. This is specific to PPv2.2.1190 */1191 int gop_id;1192 1193 int port_irq;1194 1195 struct mvpp2 *priv;1196 1197 /* Firmware node associated to the port */1198 struct fwnode_handle *fwnode;1199 1200 /* Per-port registers' base address */1201 void __iomem *base;1202 void __iomem *stats_base;1203 1204 struct mvpp2_rx_queue **rxqs;1205 unsigned int nrxqs;1206 struct mvpp2_tx_queue **txqs;1207 unsigned int ntxqs;1208 struct net_device *dev;1209 1210 struct bpf_prog *xdp_prog;1211 1212 int pkt_size;1213 1214 /* Per-CPU port control */1215 struct mvpp2_port_pcpu __percpu *pcpu;1216 1217 /* Protect the BM refills and the Tx paths when a thread is used on more1218 * than a single CPU.1219 */1220 spinlock_t bm_lock[MVPP2_MAX_THREADS];1221 spinlock_t tx_lock[MVPP2_MAX_THREADS];1222 1223 /* Flags */1224 unsigned long flags;1225 1226 u16 tx_ring_size;1227 u16 rx_ring_size;1228 struct mvpp2_pcpu_stats __percpu *stats;1229 u64 *ethtool_stats;1230 1231 unsigned long state;1232 1233 /* Per-port work and its lock to gather hardware statistics */1234 struct mutex gather_stats_lock;1235 struct delayed_work stats_work;1236 1237 struct device_node *of_node;1238 1239 phy_interface_t phy_interface;1240 struct phylink *phylink;1241 struct phylink_config phylink_config;1242 struct phylink_pcs pcs_gmac;1243 struct phylink_pcs pcs_xlg;1244 struct phy *comphy;1245 1246 struct mvpp2_bm_pool *pool_long;1247 struct mvpp2_bm_pool *pool_short;1248 1249 /* Index of first port's physical RXQ */1250 u8 first_rxq;1251 1252 struct mvpp2_queue_vector qvecs[MVPP2_MAX_QVECS];1253 unsigned int nqvecs;1254 bool has_tx_irqs;1255 1256 u32 tx_time_coal;1257 1258 /* List of steering rules active on that port */1259 struct mvpp2_ethtool_fs *rfs_rules[MVPP2_N_RFS_ENTRIES_PER_FLOW];1260 int n_rfs_rules;1261 1262 /* Each port has its own view of the rss contexts, so that it can number1263 * them from 01264 */1265 int rss_ctx[MVPP22_N_RSS_TABLES];1266 1267 bool hwtstamp;1268 bool rx_hwtstamp;1269 enum hwtstamp_tx_types tx_hwtstamp_type;1270 struct mvpp2_hwtstamp_queue tx_hwtstamp_queue[2];1271 1272 /* Firmware TX flow control */1273 bool tx_fc;1274};1275 1276/* The mvpp2_tx_desc and mvpp2_rx_desc structures describe the1277 * layout of the transmit and reception DMA descriptors, and their1278 * layout is therefore defined by the hardware design1279 */1280 1281#define MVPP2_TXD_L3_OFF_SHIFT 01282#define MVPP2_TXD_IP_HLEN_SHIFT 81283#define MVPP2_TXD_L4_CSUM_FRAG BIT(13)1284#define MVPP2_TXD_L4_CSUM_NOT BIT(14)1285#define MVPP2_TXD_IP_CSUM_DISABLE BIT(15)1286#define MVPP2_TXD_PADDING_DISABLE BIT(23)1287#define MVPP2_TXD_L4_UDP BIT(24)1288#define MVPP2_TXD_L3_IP6 BIT(26)1289#define MVPP2_TXD_L_DESC BIT(28)1290#define MVPP2_TXD_F_DESC BIT(29)1291 1292#define MVPP2_RXD_ERR_SUMMARY BIT(15)1293#define MVPP2_RXD_ERR_CODE_MASK (BIT(13) | BIT(14))1294#define MVPP2_RXD_ERR_CRC 0x01295#define MVPP2_RXD_ERR_OVERRUN BIT(13)1296#define MVPP2_RXD_ERR_RESOURCE (BIT(13) | BIT(14))1297#define MVPP2_RXD_BM_POOL_ID_OFFS 161298#define MVPP2_RXD_BM_POOL_ID_MASK (BIT(16) | BIT(17) | BIT(18))1299#define MVPP2_RXD_HWF_SYNC BIT(21)1300#define MVPP2_RXD_L4_CSUM_OK BIT(22)1301#define MVPP2_RXD_IP4_HEADER_ERR BIT(24)1302#define MVPP2_RXD_L4_TCP BIT(25)1303#define MVPP2_RXD_L4_UDP BIT(26)1304#define MVPP2_RXD_L3_IP4 BIT(28)1305#define MVPP2_RXD_L3_IP6 BIT(30)1306#define MVPP2_RXD_BUF_HDR BIT(31)1307 1308/* HW TX descriptor for PPv2.1 */1309struct mvpp21_tx_desc {1310 __le32 command; /* Options used by HW for packet transmitting.*/1311 u8 packet_offset; /* the offset from the buffer beginning */1312 u8 phys_txq; /* destination queue ID */1313 __le16 data_size; /* data size of transmitted packet in bytes */1314 __le32 buf_dma_addr; /* physical addr of transmitted buffer */1315 __le32 buf_cookie; /* cookie for access to TX buffer in tx path */1316 __le32 reserved1[3]; /* hw_cmd (for future use, BM, PON, PNC) */1317 __le32 reserved2; /* reserved (for future use) */1318};1319 1320/* HW RX descriptor for PPv2.1 */1321struct mvpp21_rx_desc {1322 __le32 status; /* info about received packet */1323 __le16 reserved1; /* parser_info (for future use, PnC) */1324 __le16 data_size; /* size of received packet in bytes */1325 __le32 buf_dma_addr; /* physical address of the buffer */1326 __le32 buf_cookie; /* cookie for access to RX buffer in rx path */1327 __le16 reserved2; /* gem_port_id (for future use, PON) */1328 __le16 reserved3; /* csum_l4 (for future use, PnC) */1329 u8 reserved4; /* bm_qset (for future use, BM) */1330 u8 reserved5;1331 __le16 reserved6; /* classify_info (for future use, PnC) */1332 __le32 reserved7; /* flow_id (for future use, PnC) */1333 __le32 reserved8;1334};1335 1336/* HW TX descriptor for PPv2.2 and PPv2.3 */1337struct mvpp22_tx_desc {1338 __le32 command;1339 u8 packet_offset;1340 u8 phys_txq;1341 __le16 data_size;1342 __le32 ptp_descriptor;1343 __le32 reserved2;1344 __le64 buf_dma_addr_ptp;1345 __le64 buf_cookie_misc;1346};1347 1348/* HW RX descriptor for PPv2.2 and PPv2.3 */1349struct mvpp22_rx_desc {1350 __le32 status;1351 __le16 reserved1;1352 __le16 data_size;1353 __le32 reserved2;1354 __le32 timestamp;1355 __le64 buf_dma_addr_key_hash;1356 __le64 buf_cookie_misc;1357};1358 1359/* Opaque type used by the driver to manipulate the HW TX and RX1360 * descriptors1361 */1362struct mvpp2_tx_desc {1363 union {1364 struct mvpp21_tx_desc pp21;1365 struct mvpp22_tx_desc pp22;1366 };1367};1368 1369struct mvpp2_rx_desc {1370 union {1371 struct mvpp21_rx_desc pp21;1372 struct mvpp22_rx_desc pp22;1373 };1374};1375 1376enum mvpp2_tx_buf_type {1377 MVPP2_TYPE_SKB,1378 MVPP2_TYPE_XDP_TX,1379 MVPP2_TYPE_XDP_NDO,1380};1381 1382struct mvpp2_txq_pcpu_buf {1383 enum mvpp2_tx_buf_type type;1384 1385 /* Transmitted SKB */1386 union {1387 struct xdp_frame *xdpf;1388 struct sk_buff *skb;1389 };1390 1391 /* Physical address of transmitted buffer */1392 dma_addr_t dma;1393 1394 /* Size transmitted */1395 size_t size;1396};1397 1398/* Per-CPU Tx queue control */1399struct mvpp2_txq_pcpu {1400 unsigned int thread;1401 1402 /* Number of Tx DMA descriptors in the descriptor ring */1403 int size;1404 1405 /* Number of currently used Tx DMA descriptor in the1406 * descriptor ring1407 */1408 int count;1409 1410 int wake_threshold;1411 int stop_threshold;1412 1413 /* Number of Tx DMA descriptors reserved for each CPU */1414 int reserved_num;1415 1416 /* Infos about transmitted buffers */1417 struct mvpp2_txq_pcpu_buf *buffs;1418 1419 /* Index of last TX DMA descriptor that was inserted */1420 int txq_put_index;1421 1422 /* Index of the TX DMA descriptor to be cleaned up */1423 int txq_get_index;1424 1425 /* DMA buffer for TSO headers */1426 char *tso_headers;1427 dma_addr_t tso_headers_dma;1428};1429 1430struct mvpp2_tx_queue {1431 /* Physical number of this Tx queue */1432 u8 id;1433 1434 /* Logical number of this Tx queue */1435 u8 log_id;1436 1437 /* Number of Tx DMA descriptors in the descriptor ring */1438 int size;1439 1440 /* Number of currently used Tx DMA descriptor in the descriptor ring */1441 int count;1442 1443 /* Per-CPU control of physical Tx queues */1444 struct mvpp2_txq_pcpu __percpu *pcpu;1445 1446 u32 done_pkts_coal;1447 1448 /* Virtual address of thex Tx DMA descriptors array */1449 struct mvpp2_tx_desc *descs;1450 1451 /* DMA address of the Tx DMA descriptors array */1452 dma_addr_t descs_dma;1453 1454 /* Index of the last Tx DMA descriptor */1455 int last_desc;1456 1457 /* Index of the next Tx DMA descriptor to process */1458 int next_desc_to_proc;1459};1460 1461struct mvpp2_rx_queue {1462 /* RX queue number, in the range 0-31 for physical RXQs */1463 u8 id;1464 1465 /* Num of rx descriptors in the rx descriptor ring */1466 int size;1467 1468 u32 pkts_coal;1469 u32 time_coal;1470 1471 /* Virtual address of the RX DMA descriptors array */1472 struct mvpp2_rx_desc *descs;1473 1474 /* DMA address of the RX DMA descriptors array */1475 dma_addr_t descs_dma;1476 1477 /* Index of the last RX DMA descriptor */1478 int last_desc;1479 1480 /* Index of the next RX DMA descriptor to process */1481 int next_desc_to_proc;1482 1483 /* ID of port to which physical RXQ is mapped */1484 int port;1485 1486 /* Port's logic RXQ number to which physical RXQ is mapped */1487 int logic_rxq;1488 1489 /* XDP memory accounting */1490 struct xdp_rxq_info xdp_rxq_short;1491 struct xdp_rxq_info xdp_rxq_long;1492};1493 1494struct mvpp2_bm_pool {1495 /* Pool number in the range 0-7 */1496 int id;1497 1498 /* Buffer Pointers Pool External (BPPE) size */1499 int size;1500 /* BPPE size in bytes */1501 int size_bytes;1502 /* Number of buffers for this pool */1503 int buf_num;1504 /* Pool buffer size */1505 int buf_size;1506 /* Packet size */1507 int pkt_size;1508 int frag_size;1509 1510 /* BPPE virtual base address */1511 u32 *virt_addr;1512 /* BPPE DMA base address */1513 dma_addr_t dma_addr;1514 1515 /* Ports using BM pool */1516 u32 port_map;1517};1518 1519#define IS_TSO_HEADER(txq_pcpu, addr) \1520 ((addr) >= (txq_pcpu)->tso_headers_dma && \1521 (addr) < (txq_pcpu)->tso_headers_dma + \1522 (txq_pcpu)->size * TSO_HEADER_SIZE)1523 1524#define MVPP2_DRIVER_NAME "mvpp2"1525#define MVPP2_DRIVER_VERSION "1.0"1526 1527void mvpp2_write(struct mvpp2 *priv, u32 offset, u32 data);1528u32 mvpp2_read(struct mvpp2 *priv, u32 offset);1529 1530void mvpp2_dbgfs_init(struct mvpp2 *priv, const char *name);1531 1532void mvpp2_dbgfs_cleanup(struct mvpp2 *priv);1533void mvpp2_dbgfs_exit(void);1534 1535void mvpp23_rx_fifo_fc_en(struct mvpp2 *priv, int port, bool en);1536 1537#ifdef CONFIG_MVPP2_PTP1538int mvpp22_tai_probe(struct device *dev, struct mvpp2 *priv);1539void mvpp22_tai_tstamp(struct mvpp2_tai *tai, u32 tstamp,1540 struct skb_shared_hwtstamps *hwtstamp);1541void mvpp22_tai_start(struct mvpp2_tai *tai);1542void mvpp22_tai_stop(struct mvpp2_tai *tai);1543int mvpp22_tai_ptp_clock_index(struct mvpp2_tai *tai);1544#else1545static inline int mvpp22_tai_probe(struct device *dev, struct mvpp2 *priv)1546{1547 return 0;1548}1549static inline void mvpp22_tai_tstamp(struct mvpp2_tai *tai, u32 tstamp,1550 struct skb_shared_hwtstamps *hwtstamp)1551{1552}1553static inline void mvpp22_tai_start(struct mvpp2_tai *tai)1554{1555}1556static inline void mvpp22_tai_stop(struct mvpp2_tai *tai)1557{1558}1559static inline int mvpp22_tai_ptp_clock_index(struct mvpp2_tai *tai)1560{1561 return -1;1562}1563#endif1564 1565static inline bool mvpp22_rx_hwtstamping(struct mvpp2_port *port)1566{1567 return IS_ENABLED(CONFIG_MVPP2_PTP) && port->rx_hwtstamp;1568}1569 1570#endif1571