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1/* SPDX-License-Identifier: GPL-2.0 */2/* Marvell Octeon EP (EndPoint) VF Ethernet Driver3 *4 * Copyright (C) 2020 Marvell.5 *6 */7 8#ifndef _OCTEP_VF_RX_H_9#define _OCTEP_VF_RX_H_10 11/* struct octep_vf_oq_desc_hw - Octeon Hardware OQ descriptor format.12 *13 * The descriptor ring is made of descriptors which have 2 64-bit values:14 *15 * @buffer_ptr: DMA address of the skb->data16 * @info_ptr: DMA address of host memory, used to update pkt count by hw.17 * This is currently unused to save pci writes.18 */19struct octep_vf_oq_desc_hw {20 dma_addr_t buffer_ptr;21 u64 info_ptr;22};23 24static_assert(sizeof(struct octep_vf_oq_desc_hw) == 16);25 26#define OCTEP_VF_OQ_DESC_SIZE (sizeof(struct octep_vf_oq_desc_hw))27 28/* Rx offload flags */29#define OCTEP_VF_RX_OFFLOAD_VLAN_STRIP BIT(0)30#define OCTEP_VF_RX_OFFLOAD_IPV4_CKSUM BIT(1)31#define OCTEP_VF_RX_OFFLOAD_UDP_CKSUM BIT(2)32#define OCTEP_VF_RX_OFFLOAD_TCP_CKSUM BIT(3)33 34#define OCTEP_VF_RX_OFFLOAD_CKSUM (OCTEP_VF_RX_OFFLOAD_IPV4_CKSUM | \35 OCTEP_VF_RX_OFFLOAD_UDP_CKSUM | \36 OCTEP_VF_RX_OFFLOAD_TCP_CKSUM)37 38#define OCTEP_VF_RX_IP_CSUM(flags) ((flags) & \39 (OCTEP_VF_RX_OFFLOAD_IPV4_CKSUM | \40 OCTEP_VF_RX_OFFLOAD_TCP_CKSUM | \41 OCTEP_VF_RX_OFFLOAD_UDP_CKSUM))42 43/* bit 0 is vlan strip */44#define OCTEP_VF_RX_CSUM_IP_VERIFIED BIT(1)45#define OCTEP_VF_RX_CSUM_L4_VERIFIED BIT(2)46 47#define OCTEP_VF_RX_CSUM_VERIFIED(flags) ((flags) & \48 (OCTEP_VF_RX_CSUM_L4_VERIFIED | \49 OCTEP_VF_RX_CSUM_IP_VERIFIED))50 51/* Extended Response Header in packet data received from Hardware.52 * Includes metadata like checksum status.53 * this is valid only if hardware/firmware published support for this.54 * This is at offset 0 of packet data (skb->data).55 */56struct octep_vf_oq_resp_hw_ext {57 /* Reserved. */58 u64 rsvd:48;59 60 /* rx offload flags */61 u16 rx_ol_flags;62};63 64static_assert(sizeof(struct octep_vf_oq_resp_hw_ext) == 8);65 66#define OCTEP_VF_OQ_RESP_HW_EXT_SIZE (sizeof(struct octep_vf_oq_resp_hw_ext))67 68/* Length of Rx packet DMA'ed by Octeon to Host.69 * this is in bigendian; so need to be converted to cpu endian.70 * Octeon writes this at the beginning of Rx buffer (skb->data).71 */72struct octep_vf_oq_resp_hw {73 /* The Length of the packet. */74 __be64 length;75};76 77static_assert(sizeof(struct octep_vf_oq_resp_hw) == 8);78 79#define OCTEP_VF_OQ_RESP_HW_SIZE (sizeof(struct octep_vf_oq_resp_hw))80 81/* Pointer to data buffer.82 * Driver keeps a pointer to the data buffer that it made available to83 * the Octeon device. Since the descriptor ring keeps physical (bus)84 * addresses, this field is required for the driver to keep track of85 * the virtual address pointers. The fields are operated by86 * OS-dependent routines.87 */88struct octep_vf_rx_buffer {89 struct page *page;90 91 /* length from rx hardware descriptor after converting to cpu endian */92 u64 len;93};94 95#define OCTEP_VF_OQ_RECVBUF_SIZE (sizeof(struct octep_vf_rx_buffer))96 97/* Output Queue statistics. Each output queue has four stats fields. */98struct octep_vf_oq_stats {99 /* Number of packets received from the Device. */100 u64 packets;101 102 /* Number of bytes received from the Device. */103 u64 bytes;104 105 /* Number of times failed to allocate buffers. */106 u64 alloc_failures;107};108 109#define OCTEP_VF_OQ_STATS_SIZE (sizeof(struct octep_vf_oq_stats))110 111/* Hardware interface Rx statistics */112struct octep_vf_iface_rx_stats {113 /* Received packets */114 u64 pkts;115 116 /* Octets of received packets */117 u64 octets;118 119 /* Received PAUSE and Control packets */120 u64 pause_pkts;121 122 /* Received PAUSE and Control octets */123 u64 pause_octets;124 125 /* Filtered DMAC0 packets */126 u64 dmac0_pkts;127 128 /* Filtered DMAC0 octets */129 u64 dmac0_octets;130 131 /* Packets dropped due to RX FIFO full */132 u64 dropped_pkts_fifo_full;133 134 /* Octets dropped due to RX FIFO full */135 u64 dropped_octets_fifo_full;136 137 /* Error packets */138 u64 err_pkts;139 140 /* Filtered DMAC1 packets */141 u64 dmac1_pkts;142 143 /* Filtered DMAC1 octets */144 u64 dmac1_octets;145 146 /* NCSI-bound packets dropped */147 u64 ncsi_dropped_pkts;148 149 /* NCSI-bound octets dropped */150 u64 ncsi_dropped_octets;151 152 /* Multicast packets received. */153 u64 mcast_pkts;154 155 /* Broadcast packets received. */156 u64 bcast_pkts;157 158};159 160/* The Descriptor Ring Output Queue structure.161 * This structure has all the information required to implement a162 * Octeon OQ.163 */164struct octep_vf_oq {165 u32 q_no;166 167 struct octep_vf_device *octep_vf_dev;168 struct net_device *netdev;169 struct device *dev;170 171 struct napi_struct *napi;172 173 /* The receive buffer list. This list has the virtual addresses174 * of the buffers.175 */176 struct octep_vf_rx_buffer *buff_info;177 178 /* Pointer to the mapped packet credit register.179 * Host writes number of info/buffer ptrs available to this register180 */181 u8 __iomem *pkts_credit_reg;182 183 /* Pointer to the mapped packet sent register.184 * Octeon writes the number of packets DMA'ed to host memory185 * in this register.186 */187 u8 __iomem *pkts_sent_reg;188 189 /* Statistics for this OQ. */190 struct octep_vf_oq_stats stats;191 192 /* Packets pending to be processed */193 u32 pkts_pending;194 u32 last_pkt_count;195 196 /* Index in the ring where the driver should read the next packet */197 u32 host_read_idx;198 199 /* Number of descriptors in this ring. */200 u32 max_count;201 u32 ring_size_mask;202 203 /* The number of descriptors pending refill. */204 u32 refill_count;205 206 /* Index in the ring where the driver will refill the207 * descriptor's buffer208 */209 u32 host_refill_idx;210 u32 refill_threshold;211 212 /* The size of each buffer pointed by the buffer pointer. */213 u32 buffer_size;214 u32 max_single_buffer_size;215 216 /* The 8B aligned descriptor ring starts at this address. */217 struct octep_vf_oq_desc_hw *desc_ring;218 219 /* DMA mapped address of the OQ descriptor ring. */220 dma_addr_t desc_ring_dma;221};222 223#define OCTEP_VF_OQ_SIZE (sizeof(struct octep_vf_oq))224#endif /* _OCTEP_VF_RX_H_ */225