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1/* SPDX-License-Identifier: GPL-2.0 */2/* Marvell OcteonTx2 CGX driver3 *4 * Copyright (C) 2018 Marvell.5 *6 */7 8#ifndef CGX_H9#define CGX_H10 11#include "mbox.h"12#include "cgx_fw_if.h"13#include "rpm.h"14 15 /* PCI device IDs */16#define PCI_DEVID_OCTEONTX2_CGX 0xA05917 18/* PCI BAR nos */19#define PCI_CFG_REG_BAR_NUM 020 21#define CGX_ID_MASK 0xF22 23/* Registers */24#define CGXX_CMRX_CFG 0x0025#define CMR_P2X_SEL_MASK GENMASK_ULL(61, 59)26#define CMR_P2X_SEL_SHIFT 59ULL27#define CMR_P2X_SEL_NIX0 1ULL28#define CMR_P2X_SEL_NIX1 2ULL29#define DATA_PKT_TX_EN BIT_ULL(53)30#define DATA_PKT_RX_EN BIT_ULL(54)31#define CGX_LMAC_TYPE_SHIFT 4032#define CGX_LMAC_TYPE_MASK 0xF33#define CGXX_CMRX_INT 0x04034#define FW_CGX_INT BIT_ULL(1)35#define CGXX_CMRX_INT_ENA_W1S 0x05836#define CGXX_CMRX_RX_ID_MAP 0x06037#define CGXX_CMRX_RX_STAT0 0x07038#define CGXX_CMRX_RX_LOGL_XON 0x10039#define CGXX_CMRX_RX_LMACS 0x12840#define CGXX_CMRX_RX_DMAC_CTL0 (0x1F8 + mac_ops->csr_offset)41#define CGX_DMAC_CTL0_CAM_ENABLE BIT_ULL(3)42#define CGX_DMAC_CAM_ACCEPT BIT_ULL(3)43#define CGX_DMAC_MCAST_MODE_CAM BIT_ULL(2)44#define CGX_DMAC_MCAST_MODE BIT_ULL(1)45#define CGX_DMAC_BCAST_MODE BIT_ULL(0)46#define CGXX_CMRX_RX_DMAC_CAM0 (0x200 + mac_ops->csr_offset)47#define CGX_DMAC_CAM_ADDR_ENABLE BIT_ULL(48)48#define CGX_DMAC_CAM_ENTRY_LMACID GENMASK_ULL(50, 49)49#define CGXX_CMRX_RX_DMAC_CAM1 0x40050#define CGX_RX_DMAC_ADR_MASK GENMASK_ULL(47, 0)51#define CGXX_CMRX_TX_STAT0 0x70052#define CGXX_SCRATCH0_REG 0x105053#define CGXX_SCRATCH1_REG 0x105854#define CGX_CONST 0x200055#define CGX_CONST_RXFIFO_SIZE GENMASK_ULL(55, 32)56#define CGX_CONST_MAX_LMACS GENMASK_ULL(31, 24)57#define CGXX_SPUX_CONTROL1 0x1000058#define CGXX_SPUX_LNX_FEC_CORR_BLOCKS 0x1070059#define CGXX_SPUX_LNX_FEC_UNCORR_BLOCKS 0x1080060#define CGXX_SPUX_RSFEC_CORR 0x1008861#define CGXX_SPUX_RSFEC_UNCORR 0x1009062 63#define CGXX_SPUX_CONTROL1_LBK BIT_ULL(14)64#define CGXX_GMP_PCS_MRX_CTL 0x3000065#define CGXX_GMP_PCS_MRX_CTL_LBK BIT_ULL(14)66 67#define CGXX_SMUX_RX_FRM_CTL 0x2002068#define CGX_SMUX_RX_FRM_CTL_CTL_BCK BIT_ULL(3)69#define CGX_SMUX_RX_FRM_CTL_PTP_MODE BIT_ULL(12)70#define CGXX_GMP_GMI_RXX_FRM_CTL 0x3802871#define CGX_GMP_GMI_RXX_FRM_CTL_CTL_BCK BIT_ULL(3)72#define CGX_GMP_GMI_RXX_FRM_CTL_PTP_MODE BIT_ULL(12)73#define CGXX_SMUX_TX_CTL 0x2017874#define CGXX_SMUX_TX_PAUSE_PKT_TIME 0x2011075#define CGXX_SMUX_TX_PAUSE_PKT_INTERVAL 0x2012076#define CGXX_SMUX_SMAC 0x2010877#define CGXX_SMUX_CBFC_CTL 0x2021878#define CGXX_SMUX_CBFC_CTL_RX_EN BIT_ULL(0)79#define CGXX_SMUX_CBFC_CTL_TX_EN BIT_ULL(1)80#define CGXX_SMUX_CBFC_CTL_DRP_EN BIT_ULL(2)81#define CGXX_SMUX_CBFC_CTL_BCK_EN BIT_ULL(3)82#define CGX_PFC_CLASS_MASK GENMASK_ULL(47, 32)83#define CGXX_GMP_GMI_TX_PAUSE_PKT_TIME 0x3823084#define CGXX_GMP_GMI_TX_PAUSE_PKT_INTERVAL 0x3824885#define CGX_SMUX_TX_CTL_L2P_BP_CONV BIT_ULL(7)86#define CGXX_CMR_RX_OVR_BP 0x13087#define CGX_CMR_RX_OVR_BP_EN(X) BIT_ULL(((X) + 8))88#define CGX_CMR_RX_OVR_BP_BP(X) BIT_ULL(((X) + 4))89 90#define CGX_COMMAND_REG CGXX_SCRATCH1_REG91#define CGX_EVENT_REG CGXX_SCRATCH0_REG92#define CGX_CMD_TIMEOUT 5000 /* msecs */93#define DEFAULT_PAUSE_TIME 0x7FF94 95#define CGX_LMAC_FWI 096 97enum cgx_nix_stat_type {98 NIX_STATS_RX,99 NIX_STATS_TX,100};101 102enum LMAC_TYPE {103 LMAC_MODE_SGMII = 0,104 LMAC_MODE_XAUI = 1,105 LMAC_MODE_RXAUI = 2,106 LMAC_MODE_10G_R = 3,107 LMAC_MODE_40G_R = 4,108 LMAC_MODE_QSGMII = 6,109 LMAC_MODE_25G_R = 7,110 LMAC_MODE_50G_R = 8,111 LMAC_MODE_100G_R = 9,112 LMAC_MODE_USXGMII = 10,113 LMAC_MODE_USGMII = 11,114 LMAC_MODE_MAX,115};116 117struct cgx_link_event {118 struct cgx_link_user_info link_uinfo;119 u8 cgx_id;120 u8 lmac_id;121};122 123/**124 * struct cgx_event_cb125 * @notify_link_chg: callback for link change notification126 * @data: data passed to callback function127 */128struct cgx_event_cb {129 int (*notify_link_chg)(struct cgx_link_event *event, void *data);130 void *data;131};132 133extern struct pci_driver cgx_driver;134 135int cgx_get_cgxcnt_max(void);136int cgx_get_cgxid(void *cgxd);137int cgx_get_lmac_cnt(void *cgxd);138void *cgx_get_pdata(int cgx_id);139int cgx_set_pkind(void *cgxd, u8 lmac_id, int pkind);140int cgx_lmac_evh_register(struct cgx_event_cb *cb, void *cgxd, int lmac_id);141int cgx_lmac_evh_unregister(void *cgxd, int lmac_id);142int cgx_get_tx_stats(void *cgxd, int lmac_id, int idx, u64 *tx_stat);143int cgx_get_rx_stats(void *cgxd, int lmac_id, int idx, u64 *rx_stat);144int cgx_stats_reset(void *cgxd, int lmac_id);145int cgx_lmac_rx_tx_enable(void *cgxd, int lmac_id, bool enable);146int cgx_lmac_tx_enable(void *cgxd, int lmac_id, bool enable);147int cgx_lmac_addr_set(u8 cgx_id, u8 lmac_id, u8 *mac_addr);148int cgx_lmac_addr_reset(u8 cgx_id, u8 lmac_id);149u64 cgx_lmac_addr_get(u8 cgx_id, u8 lmac_id);150int cgx_lmac_addr_add(u8 cgx_id, u8 lmac_id, u8 *mac_addr);151int cgx_lmac_addr_del(u8 cgx_id, u8 lmac_id, u8 index);152int cgx_lmac_addr_max_entries_get(u8 cgx_id, u8 lmac_id);153void cgx_lmac_promisc_config(int cgx_id, int lmac_id, bool enable);154void cgx_lmac_enadis_rx_pause_fwding(void *cgxd, int lmac_id, bool enable);155int cgx_lmac_internal_loopback(void *cgxd, int lmac_id, bool enable);156int cgx_get_link_info(void *cgxd, int lmac_id,157 struct cgx_link_user_info *linfo);158int cgx_lmac_linkup_start(void *cgxd);159int cgx_get_fwdata_base(u64 *base);160int cgx_lmac_get_pause_frm(void *cgxd, int lmac_id,161 u8 *tx_pause, u8 *rx_pause);162int cgx_lmac_set_pause_frm(void *cgxd, int lmac_id,163 u8 tx_pause, u8 rx_pause);164void cgx_lmac_ptp_config(void *cgxd, int lmac_id, bool enable);165u8 cgx_lmac_get_p2x(int cgx_id, int lmac_id);166int cgx_set_fec(u64 fec, int cgx_id, int lmac_id);167int cgx_get_fec_stats(void *cgxd, int lmac_id, struct cgx_fec_stats_rsp *rsp);168int cgx_get_phy_fec_stats(void *cgxd, int lmac_id);169int cgx_set_link_mode(void *cgxd, struct cgx_set_link_mode_args args,170 int cgx_id, int lmac_id);171u64 cgx_features_get(void *cgxd);172struct mac_ops *get_mac_ops(void *cgxd);173int cgx_get_nr_lmacs(void *cgxd);174u8 cgx_get_lmacid(void *cgxd, u8 lmac_index);175unsigned long cgx_get_lmac_bmap(void *cgxd);176void cgx_lmac_write(int cgx_id, int lmac_id, u64 offset, u64 val);177u64 cgx_lmac_read(int cgx_id, int lmac_id, u64 offset);178int cgx_lmac_addr_update(u8 cgx_id, u8 lmac_id, u8 *mac_addr, u8 index);179u64 cgx_read_dmac_ctrl(void *cgxd, int lmac_id);180u64 cgx_read_dmac_entry(void *cgxd, int index);181int cgx_lmac_pfc_config(void *cgxd, int lmac_id, u8 tx_pause, u8 rx_pause,182 u16 pfc_en);183int cgx_lmac_get_pfc_frm_cfg(void *cgxd, int lmac_id, u8 *tx_pause,184 u8 *rx_pause);185int verify_lmac_fc_cfg(void *cgxd, int lmac_id, u8 tx_pause, u8 rx_pause,186 int pfvf_idx);187int cgx_lmac_reset(void *cgxd, int lmac_id, u8 pf_req_flr);188#endif /* CGX_H */189