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1/* SPDX-License-Identifier: GPL-2.0 */2/* Marvell CN10K RPM driver3 *4 * Copyright (C) 2020 Marvell.5 *6 */7 8#ifndef RPM_H9#define RPM_H10 11#include <linux/bits.h>12 13/* PCI device IDs */14#define PCI_DEVID_CN10K_RPM 0xA06015#define PCI_SUBSYS_DEVID_CNF10KB_RPM 0xBC0016#define PCI_DEVID_CN10KB_RPM 0xA09F17 18/* Registers */19#define RPMX_CMRX_CFG 0x0020#define RPMX_RX_TS_PREPEND BIT_ULL(22)21#define RPMX_TX_PTP_1S_SUPPORT BIT_ULL(17)22#define RPMX_CMRX_RX_ID_MAP 0x8023#define RPMX_CMRX_SW_INT 0x18024#define RPMX_CMRX_SW_INT_W1S 0x18825#define RPMX_CMRX_SW_INT_ENA_W1S 0x19826#define RPMX_CMRX_LINK_CFG 0x107027#define RPMX_MTI_PCS100X_CONTROL1 0x2000028#define RPMX_MTI_PCS_LBK BIT_ULL(14)29#define RPMX_MTI_LPCSX_CONTROL(id) (0x30000 | ((id) * 0x100))30 31#define RPMX_CMRX_LINK_RANGE_MASK GENMASK_ULL(19, 16)32#define RPMX_CMRX_LINK_BASE_MASK GENMASK_ULL(11, 0)33#define RPMX_MTI_MAC100X_COMMAND_CONFIG 0x801034#define RPMX_MTI_MAC100X_COMMAND_CONFIG_RX_P_DISABLE BIT_ULL(29)35#define RPMX_MTI_MAC100X_COMMAND_CONFIG_TX_P_DISABLE BIT_ULL(28)36#define RPMX_MTI_MAC100X_COMMAND_CONFIG_PAUSE_IGNORE BIT_ULL(8)37#define RPMX_MTI_MAC100X_COMMAND_CONFIG_PFC_MODE BIT_ULL(19)38#define RPMX_MTI_MAC100X_CL01_PAUSE_QUANTA 0x80A839#define RPMX_MTI_MAC100X_CL23_PAUSE_QUANTA 0x80B040#define RPMX_MTI_MAC100X_CL45_PAUSE_QUANTA 0x80B841#define RPMX_MTI_MAC100X_CL67_PAUSE_QUANTA 0x80C042#define RPMX_MTI_MAC100X_CL01_QUANTA_THRESH 0x80C843#define RPMX_MTI_MAC100X_CL23_QUANTA_THRESH 0x80D044#define RPMX_MTI_MAC100X_CL45_QUANTA_THRESH 0x80D845#define RPMX_MTI_MAC100X_CL67_QUANTA_THRESH 0x80E046#define RPMX_MTI_MAC100X_CL89_PAUSE_QUANTA 0x810847#define RPMX_MTI_MAC100X_CL1011_PAUSE_QUANTA 0x811048#define RPMX_MTI_MAC100X_CL1213_PAUSE_QUANTA 0x811849#define RPMX_MTI_MAC100X_CL1415_PAUSE_QUANTA 0x812050#define RPMX_MTI_MAC100X_CL89_QUANTA_THRESH 0x812851#define RPMX_MTI_MAC100X_CL1011_QUANTA_THRESH 0x813052#define RPMX_MTI_MAC100X_CL1213_QUANTA_THRESH 0x813853#define RPMX_MTI_MAC100X_CL1415_QUANTA_THRESH 0x814054#define RPMX_CMR_RX_OVR_BP 0x412055#define RPMX_CMR_RX_OVR_BP_EN(x) BIT_ULL((x) + 8)56#define RPMX_CMR_RX_OVR_BP_BP(x) BIT_ULL((x) + 4)57#define RPMX_CMR_CHAN_MSK_OR 0x411858#define RPMX_MTI_STAT_RX_STAT_PAGES_COUNTERX 0x1200059#define RPMX_MTI_STAT_TX_STAT_PAGES_COUNTERX 0x1300060#define RPMX_MTI_STAT_DATA_HI_CDC 0x1003861 62#define RPM_LMAC_FWI 0xa63#define RPM_TX_EN BIT_ULL(0)64#define RPM_RX_EN BIT_ULL(1)65#define RPMX_CMRX_PRT_CBFC_CTL 0x5B0866#define RPMX_CMRX_PRT_CBFC_CTL_LOGL_EN_RX_SHIFT 3367#define RPMX_CMRX_PRT_CBFC_CTL_PHYS_BP_SHIFT 1668#define RPMX_CMRX_PRT_CBFC_CTL_LOGL_EN_TX_SHIFT 069#define RPM_PFC_CLASS_MASK GENMASK_ULL(48, 33)70#define RPMX_MTI_MAC100X_CL89_QUANTA_THRESH 0x812871#define RPMX_MTI_MAC100X_COMMAND_CONFIG_TX_PAD_EN BIT_ULL(11)72#define RPMX_MTI_MAC100X_COMMAND_CONFIG_PAUSE_IGNORE BIT_ULL(8)73#define RPMX_MTI_MAC100X_COMMAND_CONFIG_PAUSE_FWD BIT_ULL(7)74#define RPMX_MTI_MAC100X_CL01_PAUSE_QUANTA 0x80A875#define RPMX_MTI_MAC100X_CL89_PAUSE_QUANTA 0x810876#define RPM_DEFAULT_PAUSE_TIME 0x7FF77#define RPMX_CMRX_RX_LOGL_XON 0x410078 79#define RPMX_MTI_MAC100X_XIF_MODE 0x810080#define RPMX_ONESTEP_ENABLE BIT_ULL(5)81#define RPMX_TS_BINARY_MODE BIT_ULL(11)82#define RPMX_CONST1 0x200883 84/* FEC stats */85#define RPMX_MTI_STAT_STATN_CONTROL 0x1001886#define RPMX_MTI_STAT_DATA_HI_CDC 0x1003887#define RPMX_RSFEC_RX_CAPTURE BIT_ULL(27)88#define RPMX_CMD_CLEAR_RX BIT_ULL(30)89#define RPMX_CMD_CLEAR_TX BIT_ULL(31)90#define RPMX_MTI_RSFEC_STAT_COUNTER_CAPTURE_2 0x4005091#define RPMX_MTI_RSFEC_STAT_COUNTER_CAPTURE_3 0x4005892#define RPMX_MTI_FCFECX_VL0_CCW_LO 0x3861893#define RPMX_MTI_FCFECX_VL0_NCCW_LO 0x3862094#define RPMX_MTI_FCFECX_VL1_CCW_LO 0x3862895#define RPMX_MTI_FCFECX_VL1_NCCW_LO 0x3863096#define RPMX_MTI_FCFECX_CW_HI 0x3863897 98/* CN10KB CSR Declaration */99#define RPM2_CMRX_SW_INT 0x1b0100#define RPM2_CMRX_SW_INT_ENA_W1S 0x1c8101#define RPM2_LMAC_FWI 0x12102#define RPM2_CMR_CHAN_MSK_OR 0x3120103#define RPM2_CMR_RX_OVR_BP_EN BIT_ULL(2)104#define RPM2_CMR_RX_OVR_BP_BP BIT_ULL(1)105#define RPM2_CMR_RX_OVR_BP 0x3130106#define RPM2_CSR_OFFSET 0x3e00107#define RPM2_CMRX_PRT_CBFC_CTL 0x6510108#define RPM2_CMRX_RX_LMACS 0x100109#define RPM2_CMRX_RX_LOGL_XON 0x3100110#define RPM2_CMRX_RX_STAT2 0x3010111#define RPM2_USX_PCSX_CONTROL1 0x80000112#define RPM2_USX_PCS_LBK BIT_ULL(14)113 114/* Function Declarations */115int rpm_get_nr_lmacs(void *rpmd);116u8 rpm_get_lmac_type(void *rpmd, int lmac_id);117u32 rpm_get_lmac_fifo_len(void *rpmd, int lmac_id);118u32 rpm2_get_lmac_fifo_len(void *rpmd, int lmac_id);119int rpm_lmac_internal_loopback(void *rpmd, int lmac_id, bool enable);120void rpm_lmac_enadis_rx_pause_fwding(void *rpmd, int lmac_id, bool enable);121int rpm_lmac_get_pause_frm_status(void *cgxd, int lmac_id, u8 *tx_pause,122 u8 *rx_pause);123void rpm_lmac_pause_frm_config(void *rpmd, int lmac_id, bool enable);124int rpm_lmac_enadis_pause_frm(void *rpmd, int lmac_id, u8 tx_pause,125 u8 rx_pause);126int rpm_get_tx_stats(void *rpmd, int lmac_id, int idx, u64 *tx_stat);127int rpm_get_rx_stats(void *rpmd, int lmac_id, int idx, u64 *rx_stat);128void rpm_lmac_ptp_config(void *rpmd, int lmac_id, bool enable);129int rpm_lmac_rx_tx_enable(void *rpmd, int lmac_id, bool enable);130int rpm_lmac_tx_enable(void *rpmd, int lmac_id, bool enable);131int rpm_lmac_pfc_config(void *rpmd, int lmac_id, u8 tx_pause, u8 rx_pause,132 u16 pfc_en);133int rpm_lmac_get_pfc_frm_cfg(void *rpmd, int lmac_id, u8 *tx_pause,134 u8 *rx_pause);135int rpm2_get_nr_lmacs(void *rpmd);136bool is_dev_rpm2(void *rpmd);137int rpm_get_fec_stats(void *cgxd, int lmac_id, struct cgx_fec_stats_rsp *rsp);138int rpm_lmac_reset(void *rpmd, int lmac_id, u8 pf_req_flr);139int rpm_stats_reset(void *rpmd, int lmac_id);140#endif /* RPM_H */141