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1// SPDX-License-Identifier: GPL-2.02/* Marvell RVU Admin Function driver3 *4 * Copyright (C) 2018 Marvell.5 *6 */7 8#include <linux/types.h>9#include <linux/module.h>10#include <linux/pci.h>11 12#include "rvu.h"13#include "cgx.h"14#include "lmac_common.h"15#include "rvu_reg.h"16#include "rvu_trace.h"17#include "rvu_npc_hash.h"18 19struct cgx_evq_entry {20 struct list_head evq_node;21 struct cgx_link_event link_event;22};23 24#define M(_name, _id, _fn_name, _req_type, _rsp_type) \25static struct _req_type __maybe_unused \26*otx2_mbox_alloc_msg_ ## _fn_name(struct rvu *rvu, int devid) \27{ \28 struct _req_type *req; \29 \30 req = (struct _req_type *)otx2_mbox_alloc_msg_rsp( \31 &rvu->afpf_wq_info.mbox_up, devid, sizeof(struct _req_type), \32 sizeof(struct _rsp_type)); \33 if (!req) \34 return NULL; \35 req->hdr.sig = OTX2_MBOX_REQ_SIG; \36 req->hdr.id = _id; \37 trace_otx2_msg_alloc(rvu->pdev, _id, sizeof(*req)); \38 return req; \39}40 41MBOX_UP_CGX_MESSAGES42#undef M43 44bool is_mac_feature_supported(struct rvu *rvu, int pf, int feature)45{46 u8 cgx_id, lmac_id;47 void *cgxd;48 49 if (!is_pf_cgxmapped(rvu, pf))50 return 0;51 52 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);53 cgxd = rvu_cgx_pdata(cgx_id, rvu);54 55 return (cgx_features_get(cgxd) & feature);56}57 58#define CGX_OFFSET(x) ((x) * rvu->hw->lmac_per_cgx)59/* Returns bitmap of mapped PFs */60static u64 cgxlmac_to_pfmap(struct rvu *rvu, u8 cgx_id, u8 lmac_id)61{62 return rvu->cgxlmac2pf_map[CGX_OFFSET(cgx_id) + lmac_id];63}64 65int cgxlmac_to_pf(struct rvu *rvu, int cgx_id, int lmac_id)66{67 unsigned long pfmap;68 69 pfmap = cgxlmac_to_pfmap(rvu, cgx_id, lmac_id);70 71 /* Assumes only one pf mapped to a cgx lmac port */72 if (!pfmap)73 return -ENODEV;74 else75 return find_first_bit(&pfmap,76 rvu->cgx_cnt_max * rvu->hw->lmac_per_cgx);77}78 79static u8 cgxlmac_id_to_bmap(u8 cgx_id, u8 lmac_id)80{81 return ((cgx_id & 0xF) << 4) | (lmac_id & 0xF);82}83 84void *rvu_cgx_pdata(u8 cgx_id, struct rvu *rvu)85{86 if (cgx_id >= rvu->cgx_cnt_max)87 return NULL;88 89 return rvu->cgx_idmap[cgx_id];90}91 92/* Return first enabled CGX instance if none are enabled then return NULL */93void *rvu_first_cgx_pdata(struct rvu *rvu)94{95 int first_enabled_cgx = 0;96 void *cgxd = NULL;97 98 for (; first_enabled_cgx < rvu->cgx_cnt_max; first_enabled_cgx++) {99 cgxd = rvu_cgx_pdata(first_enabled_cgx, rvu);100 if (cgxd)101 break;102 }103 104 return cgxd;105}106 107/* Based on P2X connectivity find mapped NIX block for a PF */108static void rvu_map_cgx_nix_block(struct rvu *rvu, int pf,109 int cgx_id, int lmac_id)110{111 struct rvu_pfvf *pfvf = &rvu->pf[pf];112 u8 p2x;113 114 p2x = cgx_lmac_get_p2x(cgx_id, lmac_id);115 /* Firmware sets P2X_SELECT as either NIX0 or NIX1 */116 pfvf->nix_blkaddr = BLKADDR_NIX0;117 if (is_rvu_supports_nix1(rvu) && p2x == CMR_P2X_SEL_NIX1)118 pfvf->nix_blkaddr = BLKADDR_NIX1;119}120 121static int rvu_map_cgx_lmac_pf(struct rvu *rvu)122{123 struct npc_pkind *pkind = &rvu->hw->pkind;124 int cgx_cnt_max = rvu->cgx_cnt_max;125 int pf = PF_CGXMAP_BASE;126 unsigned long lmac_bmap;127 int size, free_pkind;128 int cgx, lmac, iter;129 int numvfs, hwvfs;130 131 if (!cgx_cnt_max)132 return 0;133 134 if (cgx_cnt_max > 0xF || rvu->hw->lmac_per_cgx > 0xF)135 return -EINVAL;136 137 /* Alloc map table138 * An additional entry is required since PF id starts from 1 and139 * hence entry at offset 0 is invalid.140 */141 size = (cgx_cnt_max * rvu->hw->lmac_per_cgx + 1) * sizeof(u8);142 rvu->pf2cgxlmac_map = devm_kmalloc(rvu->dev, size, GFP_KERNEL);143 if (!rvu->pf2cgxlmac_map)144 return -ENOMEM;145 146 /* Initialize all entries with an invalid cgx and lmac id */147 memset(rvu->pf2cgxlmac_map, 0xFF, size);148 149 /* Reverse map table */150 rvu->cgxlmac2pf_map =151 devm_kzalloc(rvu->dev,152 cgx_cnt_max * rvu->hw->lmac_per_cgx * sizeof(u64),153 GFP_KERNEL);154 if (!rvu->cgxlmac2pf_map)155 return -ENOMEM;156 157 rvu->cgx_mapped_pfs = 0;158 for (cgx = 0; cgx < cgx_cnt_max; cgx++) {159 if (!rvu_cgx_pdata(cgx, rvu))160 continue;161 lmac_bmap = cgx_get_lmac_bmap(rvu_cgx_pdata(cgx, rvu));162 for_each_set_bit(iter, &lmac_bmap, rvu->hw->lmac_per_cgx) {163 if (iter >= MAX_LMAC_COUNT)164 continue;165 lmac = cgx_get_lmacid(rvu_cgx_pdata(cgx, rvu),166 iter);167 rvu->pf2cgxlmac_map[pf] = cgxlmac_id_to_bmap(cgx, lmac);168 rvu->cgxlmac2pf_map[CGX_OFFSET(cgx) + lmac] = 1 << pf;169 free_pkind = rvu_alloc_rsrc(&pkind->rsrc);170 pkind->pfchan_map[free_pkind] = ((pf) & 0x3F) << 16;171 rvu_map_cgx_nix_block(rvu, pf, cgx, lmac);172 rvu->cgx_mapped_pfs++;173 rvu_get_pf_numvfs(rvu, pf, &numvfs, &hwvfs);174 rvu->cgx_mapped_vfs += numvfs;175 pf++;176 }177 }178 return 0;179}180 181static int rvu_cgx_send_link_info(int cgx_id, int lmac_id, struct rvu *rvu)182{183 struct cgx_evq_entry *qentry;184 unsigned long flags;185 int err;186 187 qentry = kmalloc(sizeof(*qentry), GFP_KERNEL);188 if (!qentry)189 return -ENOMEM;190 191 /* Lock the event queue before we read the local link status */192 spin_lock_irqsave(&rvu->cgx_evq_lock, flags);193 err = cgx_get_link_info(rvu_cgx_pdata(cgx_id, rvu), lmac_id,194 &qentry->link_event.link_uinfo);195 qentry->link_event.cgx_id = cgx_id;196 qentry->link_event.lmac_id = lmac_id;197 if (err) {198 kfree(qentry);199 goto skip_add;200 }201 list_add_tail(&qentry->evq_node, &rvu->cgx_evq_head);202skip_add:203 spin_unlock_irqrestore(&rvu->cgx_evq_lock, flags);204 205 /* start worker to process the events */206 queue_work(rvu->cgx_evh_wq, &rvu->cgx_evh_work);207 208 return 0;209}210 211/* This is called from interrupt context and is expected to be atomic */212static int cgx_lmac_postevent(struct cgx_link_event *event, void *data)213{214 struct cgx_evq_entry *qentry;215 struct rvu *rvu = data;216 217 /* post event to the event queue */218 qentry = kmalloc(sizeof(*qentry), GFP_ATOMIC);219 if (!qentry)220 return -ENOMEM;221 qentry->link_event = *event;222 spin_lock(&rvu->cgx_evq_lock);223 list_add_tail(&qentry->evq_node, &rvu->cgx_evq_head);224 spin_unlock(&rvu->cgx_evq_lock);225 226 /* start worker to process the events */227 queue_work(rvu->cgx_evh_wq, &rvu->cgx_evh_work);228 229 return 0;230}231 232static void cgx_notify_pfs(struct cgx_link_event *event, struct rvu *rvu)233{234 struct cgx_link_user_info *linfo;235 struct cgx_link_info_msg *msg;236 unsigned long pfmap;237 int pfid;238 239 linfo = &event->link_uinfo;240 pfmap = cgxlmac_to_pfmap(rvu, event->cgx_id, event->lmac_id);241 if (!pfmap) {242 dev_err(rvu->dev, "CGX port%d:%d not mapped with PF\n",243 event->cgx_id, event->lmac_id);244 return;245 }246 247 do {248 pfid = find_first_bit(&pfmap,249 rvu->cgx_cnt_max * rvu->hw->lmac_per_cgx);250 clear_bit(pfid, &pfmap);251 252 /* check if notification is enabled */253 if (!test_bit(pfid, &rvu->pf_notify_bmap)) {254 dev_info(rvu->dev, "cgx %d: lmac %d Link status %s\n",255 event->cgx_id, event->lmac_id,256 linfo->link_up ? "UP" : "DOWN");257 continue;258 }259 260 mutex_lock(&rvu->mbox_lock);261 262 /* Send mbox message to PF */263 msg = otx2_mbox_alloc_msg_cgx_link_event(rvu, pfid);264 if (!msg) {265 mutex_unlock(&rvu->mbox_lock);266 continue;267 }268 269 msg->link_info = *linfo;270 271 otx2_mbox_wait_for_zero(&rvu->afpf_wq_info.mbox_up, pfid);272 273 otx2_mbox_msg_send_up(&rvu->afpf_wq_info.mbox_up, pfid);274 275 mutex_unlock(&rvu->mbox_lock);276 } while (pfmap);277}278 279static void cgx_evhandler_task(struct work_struct *work)280{281 struct rvu *rvu = container_of(work, struct rvu, cgx_evh_work);282 struct cgx_evq_entry *qentry;283 struct cgx_link_event *event;284 unsigned long flags;285 286 do {287 /* Dequeue an event */288 spin_lock_irqsave(&rvu->cgx_evq_lock, flags);289 qentry = list_first_entry_or_null(&rvu->cgx_evq_head,290 struct cgx_evq_entry,291 evq_node);292 if (qentry)293 list_del(&qentry->evq_node);294 spin_unlock_irqrestore(&rvu->cgx_evq_lock, flags);295 if (!qentry)296 break; /* nothing more to process */297 298 event = &qentry->link_event;299 300 /* process event */301 cgx_notify_pfs(event, rvu);302 kfree(qentry);303 } while (1);304}305 306static int cgx_lmac_event_handler_init(struct rvu *rvu)307{308 unsigned long lmac_bmap;309 struct cgx_event_cb cb;310 int cgx, lmac, err;311 void *cgxd;312 313 spin_lock_init(&rvu->cgx_evq_lock);314 INIT_LIST_HEAD(&rvu->cgx_evq_head);315 INIT_WORK(&rvu->cgx_evh_work, cgx_evhandler_task);316 rvu->cgx_evh_wq = alloc_workqueue("rvu_evh_wq", 0, 0);317 if (!rvu->cgx_evh_wq) {318 dev_err(rvu->dev, "alloc workqueue failed");319 return -ENOMEM;320 }321 322 cb.notify_link_chg = cgx_lmac_postevent; /* link change call back */323 cb.data = rvu;324 325 for (cgx = 0; cgx <= rvu->cgx_cnt_max; cgx++) {326 cgxd = rvu_cgx_pdata(cgx, rvu);327 if (!cgxd)328 continue;329 lmac_bmap = cgx_get_lmac_bmap(cgxd);330 for_each_set_bit(lmac, &lmac_bmap, rvu->hw->lmac_per_cgx) {331 err = cgx_lmac_evh_register(&cb, cgxd, lmac);332 if (err)333 dev_err(rvu->dev,334 "%d:%d handler register failed\n",335 cgx, lmac);336 }337 }338 339 return 0;340}341 342static void rvu_cgx_wq_destroy(struct rvu *rvu)343{344 if (rvu->cgx_evh_wq) {345 destroy_workqueue(rvu->cgx_evh_wq);346 rvu->cgx_evh_wq = NULL;347 }348}349 350int rvu_cgx_init(struct rvu *rvu)351{352 int cgx, err;353 void *cgxd;354 355 /* CGX port id starts from 0 and are not necessarily contiguous356 * Hence we allocate resources based on the maximum port id value.357 */358 rvu->cgx_cnt_max = cgx_get_cgxcnt_max();359 if (!rvu->cgx_cnt_max) {360 dev_info(rvu->dev, "No CGX devices found!\n");361 return 0;362 }363 364 rvu->cgx_idmap = devm_kzalloc(rvu->dev, rvu->cgx_cnt_max *365 sizeof(void *), GFP_KERNEL);366 if (!rvu->cgx_idmap)367 return -ENOMEM;368 369 /* Initialize the cgxdata table */370 for (cgx = 0; cgx < rvu->cgx_cnt_max; cgx++)371 rvu->cgx_idmap[cgx] = cgx_get_pdata(cgx);372 373 /* Map CGX LMAC interfaces to RVU PFs */374 err = rvu_map_cgx_lmac_pf(rvu);375 if (err)376 return err;377 378 /* Register for CGX events */379 err = cgx_lmac_event_handler_init(rvu);380 if (err)381 return err;382 383 mutex_init(&rvu->cgx_cfg_lock);384 385 /* Ensure event handler registration is completed, before386 * we turn on the links387 */388 mb();389 390 /* Do link up for all CGX ports */391 for (cgx = 0; cgx <= rvu->cgx_cnt_max; cgx++) {392 cgxd = rvu_cgx_pdata(cgx, rvu);393 if (!cgxd)394 continue;395 err = cgx_lmac_linkup_start(cgxd);396 if (err)397 dev_err(rvu->dev,398 "Link up process failed to start on cgx %d\n",399 cgx);400 }401 402 return 0;403}404 405int rvu_cgx_exit(struct rvu *rvu)406{407 unsigned long lmac_bmap;408 int cgx, lmac;409 void *cgxd;410 411 for (cgx = 0; cgx <= rvu->cgx_cnt_max; cgx++) {412 cgxd = rvu_cgx_pdata(cgx, rvu);413 if (!cgxd)414 continue;415 lmac_bmap = cgx_get_lmac_bmap(cgxd);416 for_each_set_bit(lmac, &lmac_bmap, rvu->hw->lmac_per_cgx)417 cgx_lmac_evh_unregister(cgxd, lmac);418 }419 420 /* Ensure event handler unregister is completed */421 mb();422 423 rvu_cgx_wq_destroy(rvu);424 return 0;425}426 427/* Most of the CGX configuration is restricted to the mapped PF only,428 * VF's of mapped PF and other PFs are not allowed. This fn() checks429 * whether a PFFUNC is permitted to do the config or not.430 */431inline bool is_cgx_config_permitted(struct rvu *rvu, u16 pcifunc)432{433 if ((pcifunc & RVU_PFVF_FUNC_MASK) ||434 !is_pf_cgxmapped(rvu, rvu_get_pf(pcifunc)))435 return false;436 return true;437}438 439void rvu_cgx_enadis_rx_bp(struct rvu *rvu, int pf, bool enable)440{441 struct mac_ops *mac_ops;442 u8 cgx_id, lmac_id;443 void *cgxd;444 445 if (!is_pf_cgxmapped(rvu, pf))446 return;447 448 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);449 cgxd = rvu_cgx_pdata(cgx_id, rvu);450 451 mac_ops = get_mac_ops(cgxd);452 /* Set / clear CTL_BCK to control pause frame forwarding to NIX */453 if (enable)454 mac_ops->mac_enadis_rx_pause_fwding(cgxd, lmac_id, true);455 else456 mac_ops->mac_enadis_rx_pause_fwding(cgxd, lmac_id, false);457}458 459int rvu_cgx_config_rxtx(struct rvu *rvu, u16 pcifunc, bool start)460{461 int pf = rvu_get_pf(pcifunc);462 struct mac_ops *mac_ops;463 u8 cgx_id, lmac_id;464 void *cgxd;465 466 if (!is_cgx_config_permitted(rvu, pcifunc))467 return LMAC_AF_ERR_PERM_DENIED;468 469 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);470 cgxd = rvu_cgx_pdata(cgx_id, rvu);471 mac_ops = get_mac_ops(cgxd);472 473 return mac_ops->mac_rx_tx_enable(cgxd, lmac_id, start);474}475 476int rvu_cgx_tx_enable(struct rvu *rvu, u16 pcifunc, bool enable)477{478 int pf = rvu_get_pf(pcifunc);479 struct mac_ops *mac_ops;480 u8 cgx_id, lmac_id;481 void *cgxd;482 483 if (!is_cgx_config_permitted(rvu, pcifunc))484 return LMAC_AF_ERR_PERM_DENIED;485 486 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);487 cgxd = rvu_cgx_pdata(cgx_id, rvu);488 mac_ops = get_mac_ops(cgxd);489 490 return mac_ops->mac_tx_enable(cgxd, lmac_id, enable);491}492 493int rvu_cgx_config_tx(void *cgxd, int lmac_id, bool enable)494{495 struct mac_ops *mac_ops;496 497 mac_ops = get_mac_ops(cgxd);498 return mac_ops->mac_tx_enable(cgxd, lmac_id, enable);499}500 501void rvu_cgx_disable_dmac_entries(struct rvu *rvu, u16 pcifunc)502{503 int pf = rvu_get_pf(pcifunc);504 int i = 0, lmac_count = 0;505 struct mac_ops *mac_ops;506 u8 max_dmac_filters;507 u8 cgx_id, lmac_id;508 void *cgx_dev;509 510 if (!is_cgx_config_permitted(rvu, pcifunc))511 return;512 513 if (rvu_npc_exact_has_match_table(rvu)) {514 rvu_npc_exact_reset(rvu, pcifunc);515 return;516 }517 518 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);519 cgx_dev = cgx_get_pdata(cgx_id);520 lmac_count = cgx_get_lmac_cnt(cgx_dev);521 522 mac_ops = get_mac_ops(cgx_dev);523 if (!mac_ops)524 return;525 526 max_dmac_filters = mac_ops->dmac_filter_count / lmac_count;527 528 for (i = 0; i < max_dmac_filters; i++)529 cgx_lmac_addr_del(cgx_id, lmac_id, i);530 531 /* As cgx_lmac_addr_del does not clear entry for index 0532 * so it needs to be done explicitly533 */534 cgx_lmac_addr_reset(cgx_id, lmac_id);535}536 537int rvu_mbox_handler_cgx_start_rxtx(struct rvu *rvu, struct msg_req *req,538 struct msg_rsp *rsp)539{540 rvu_cgx_config_rxtx(rvu, req->hdr.pcifunc, true);541 return 0;542}543 544int rvu_mbox_handler_cgx_stop_rxtx(struct rvu *rvu, struct msg_req *req,545 struct msg_rsp *rsp)546{547 rvu_cgx_config_rxtx(rvu, req->hdr.pcifunc, false);548 return 0;549}550 551static int rvu_lmac_get_stats(struct rvu *rvu, struct msg_req *req,552 void *rsp)553{554 int pf = rvu_get_pf(req->hdr.pcifunc);555 struct mac_ops *mac_ops;556 int stat = 0, err = 0;557 u64 tx_stat, rx_stat;558 u8 cgx_idx, lmac;559 void *cgxd;560 561 if (!is_cgx_config_permitted(rvu, req->hdr.pcifunc))562 return LMAC_AF_ERR_PERM_DENIED;563 564 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_idx, &lmac);565 cgxd = rvu_cgx_pdata(cgx_idx, rvu);566 mac_ops = get_mac_ops(cgxd);567 568 /* Rx stats */569 while (stat < mac_ops->rx_stats_cnt) {570 err = mac_ops->mac_get_rx_stats(cgxd, lmac, stat, &rx_stat);571 if (err)572 return err;573 if (mac_ops->rx_stats_cnt == RPM_RX_STATS_COUNT)574 ((struct rpm_stats_rsp *)rsp)->rx_stats[stat] = rx_stat;575 else576 ((struct cgx_stats_rsp *)rsp)->rx_stats[stat] = rx_stat;577 stat++;578 }579 580 /* Tx stats */581 stat = 0;582 while (stat < mac_ops->tx_stats_cnt) {583 err = mac_ops->mac_get_tx_stats(cgxd, lmac, stat, &tx_stat);584 if (err)585 return err;586 if (mac_ops->tx_stats_cnt == RPM_TX_STATS_COUNT)587 ((struct rpm_stats_rsp *)rsp)->tx_stats[stat] = tx_stat;588 else589 ((struct cgx_stats_rsp *)rsp)->tx_stats[stat] = tx_stat;590 stat++;591 }592 return 0;593}594 595int rvu_mbox_handler_cgx_stats(struct rvu *rvu, struct msg_req *req,596 struct cgx_stats_rsp *rsp)597{598 return rvu_lmac_get_stats(rvu, req, (void *)rsp);599}600 601int rvu_mbox_handler_rpm_stats(struct rvu *rvu, struct msg_req *req,602 struct rpm_stats_rsp *rsp)603{604 return rvu_lmac_get_stats(rvu, req, (void *)rsp);605}606 607int rvu_mbox_handler_cgx_stats_rst(struct rvu *rvu, struct msg_req *req,608 struct msg_rsp *rsp)609{610 int pf = rvu_get_pf(req->hdr.pcifunc);611 struct rvu_pfvf *parent_pf;612 struct mac_ops *mac_ops;613 u8 cgx_idx, lmac;614 void *cgxd;615 616 if (!is_cgx_config_permitted(rvu, req->hdr.pcifunc))617 return LMAC_AF_ERR_PERM_DENIED;618 619 parent_pf = &rvu->pf[pf];620 /* To ensure reset cgx stats won't affect VF stats,621 * check if it used by only PF interface.622 * If not, return623 */624 if (parent_pf->cgx_users > 1) {625 dev_info(rvu->dev, "CGX busy, could not reset statistics\n");626 return 0;627 }628 629 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_idx, &lmac);630 cgxd = rvu_cgx_pdata(cgx_idx, rvu);631 mac_ops = get_mac_ops(cgxd);632 633 return mac_ops->mac_stats_reset(cgxd, lmac);634}635 636int rvu_mbox_handler_cgx_fec_stats(struct rvu *rvu,637 struct msg_req *req,638 struct cgx_fec_stats_rsp *rsp)639{640 int pf = rvu_get_pf(req->hdr.pcifunc);641 struct mac_ops *mac_ops;642 u8 cgx_idx, lmac;643 void *cgxd;644 645 if (!is_cgx_config_permitted(rvu, req->hdr.pcifunc))646 return LMAC_AF_ERR_PERM_DENIED;647 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_idx, &lmac);648 649 cgxd = rvu_cgx_pdata(cgx_idx, rvu);650 mac_ops = get_mac_ops(cgxd);651 return mac_ops->get_fec_stats(cgxd, lmac, rsp);652}653 654int rvu_mbox_handler_cgx_mac_addr_set(struct rvu *rvu,655 struct cgx_mac_addr_set_or_get *req,656 struct cgx_mac_addr_set_or_get *rsp)657{658 int pf = rvu_get_pf(req->hdr.pcifunc);659 u8 cgx_id, lmac_id;660 661 if (!is_cgx_config_permitted(rvu, req->hdr.pcifunc))662 return -EPERM;663 664 if (rvu_npc_exact_has_match_table(rvu))665 return rvu_npc_exact_mac_addr_set(rvu, req, rsp);666 667 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);668 669 cgx_lmac_addr_set(cgx_id, lmac_id, req->mac_addr);670 671 return 0;672}673 674int rvu_mbox_handler_cgx_mac_addr_add(struct rvu *rvu,675 struct cgx_mac_addr_add_req *req,676 struct cgx_mac_addr_add_rsp *rsp)677{678 int pf = rvu_get_pf(req->hdr.pcifunc);679 u8 cgx_id, lmac_id;680 int rc = 0;681 682 if (!is_cgx_config_permitted(rvu, req->hdr.pcifunc))683 return -EPERM;684 685 if (rvu_npc_exact_has_match_table(rvu))686 return rvu_npc_exact_mac_addr_add(rvu, req, rsp);687 688 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);689 rc = cgx_lmac_addr_add(cgx_id, lmac_id, req->mac_addr);690 if (rc >= 0) {691 rsp->index = rc;692 return 0;693 }694 695 return rc;696}697 698int rvu_mbox_handler_cgx_mac_addr_del(struct rvu *rvu,699 struct cgx_mac_addr_del_req *req,700 struct msg_rsp *rsp)701{702 int pf = rvu_get_pf(req->hdr.pcifunc);703 u8 cgx_id, lmac_id;704 705 if (!is_cgx_config_permitted(rvu, req->hdr.pcifunc))706 return -EPERM;707 708 if (rvu_npc_exact_has_match_table(rvu))709 return rvu_npc_exact_mac_addr_del(rvu, req, rsp);710 711 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);712 return cgx_lmac_addr_del(cgx_id, lmac_id, req->index);713}714 715int rvu_mbox_handler_cgx_mac_max_entries_get(struct rvu *rvu,716 struct msg_req *req,717 struct cgx_max_dmac_entries_get_rsp718 *rsp)719{720 int pf = rvu_get_pf(req->hdr.pcifunc);721 u8 cgx_id, lmac_id;722 723 /* If msg is received from PFs(which are not mapped to CGX LMACs)724 * or VF then no entries are allocated for DMAC filters at CGX level.725 * So returning zero.726 */727 if (!is_cgx_config_permitted(rvu, req->hdr.pcifunc)) {728 rsp->max_dmac_filters = 0;729 return 0;730 }731 732 if (rvu_npc_exact_has_match_table(rvu)) {733 rsp->max_dmac_filters = rvu_npc_exact_get_max_entries(rvu);734 return 0;735 }736 737 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);738 rsp->max_dmac_filters = cgx_lmac_addr_max_entries_get(cgx_id, lmac_id);739 return 0;740}741 742int rvu_mbox_handler_cgx_mac_addr_get(struct rvu *rvu,743 struct cgx_mac_addr_set_or_get *req,744 struct cgx_mac_addr_set_or_get *rsp)745{746 int pf = rvu_get_pf(req->hdr.pcifunc);747 u8 cgx_id, lmac_id;748 int rc = 0;749 u64 cfg;750 751 if (!is_cgx_config_permitted(rvu, req->hdr.pcifunc))752 return -EPERM;753 754 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);755 756 rsp->hdr.rc = rc;757 cfg = cgx_lmac_addr_get(cgx_id, lmac_id);758 /* copy 48 bit mac address to req->mac_addr */759 u64_to_ether_addr(cfg, rsp->mac_addr);760 return 0;761}762 763int rvu_mbox_handler_cgx_promisc_enable(struct rvu *rvu, struct msg_req *req,764 struct msg_rsp *rsp)765{766 u16 pcifunc = req->hdr.pcifunc;767 int pf = rvu_get_pf(pcifunc);768 u8 cgx_id, lmac_id;769 770 if (!is_cgx_config_permitted(rvu, req->hdr.pcifunc))771 return -EPERM;772 773 /* Disable drop on non hit rule */774 if (rvu_npc_exact_has_match_table(rvu))775 return rvu_npc_exact_promisc_enable(rvu, req->hdr.pcifunc);776 777 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);778 779 cgx_lmac_promisc_config(cgx_id, lmac_id, true);780 return 0;781}782 783int rvu_mbox_handler_cgx_promisc_disable(struct rvu *rvu, struct msg_req *req,784 struct msg_rsp *rsp)785{786 int pf = rvu_get_pf(req->hdr.pcifunc);787 u8 cgx_id, lmac_id;788 789 if (!is_cgx_config_permitted(rvu, req->hdr.pcifunc))790 return -EPERM;791 792 /* Disable drop on non hit rule */793 if (rvu_npc_exact_has_match_table(rvu))794 return rvu_npc_exact_promisc_disable(rvu, req->hdr.pcifunc);795 796 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);797 798 cgx_lmac_promisc_config(cgx_id, lmac_id, false);799 return 0;800}801 802static int rvu_cgx_ptp_rx_cfg(struct rvu *rvu, u16 pcifunc, bool enable)803{804 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc);805 int pf = rvu_get_pf(pcifunc);806 struct mac_ops *mac_ops;807 u8 cgx_id, lmac_id;808 void *cgxd;809 810 if (!is_mac_feature_supported(rvu, pf, RVU_LMAC_FEAT_PTP))811 return 0;812 813 /* This msg is expected only from PF/VFs that are mapped to CGX/RPM LMACs,814 * if received from other PF/VF simply ACK, nothing to do.815 */816 if (!is_pf_cgxmapped(rvu, pf))817 return -EPERM;818 819 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);820 cgxd = rvu_cgx_pdata(cgx_id, rvu);821 822 mac_ops = get_mac_ops(cgxd);823 mac_ops->mac_enadis_ptp_config(cgxd, lmac_id, enable);824 /* If PTP is enabled then inform NPC that packets to be825 * parsed by this PF will have their data shifted by 8 bytes826 * and if PTP is disabled then no shift is required827 */828 if (npc_config_ts_kpuaction(rvu, pf, pcifunc, enable))829 return -EINVAL;830 /* This flag is required to clean up CGX conf if app gets killed */831 pfvf->hw_rx_tstamp_en = enable;832 833 /* Inform MCS about 8B RX header */834 rvu_mcs_ptp_cfg(rvu, cgx_id, lmac_id, enable);835 return 0;836}837 838int rvu_mbox_handler_cgx_ptp_rx_enable(struct rvu *rvu, struct msg_req *req,839 struct msg_rsp *rsp)840{841 if (!is_pf_cgxmapped(rvu, rvu_get_pf(req->hdr.pcifunc)))842 return -EPERM;843 844 return rvu_cgx_ptp_rx_cfg(rvu, req->hdr.pcifunc, true);845}846 847int rvu_mbox_handler_cgx_ptp_rx_disable(struct rvu *rvu, struct msg_req *req,848 struct msg_rsp *rsp)849{850 return rvu_cgx_ptp_rx_cfg(rvu, req->hdr.pcifunc, false);851}852 853static int rvu_cgx_config_linkevents(struct rvu *rvu, u16 pcifunc, bool en)854{855 int pf = rvu_get_pf(pcifunc);856 u8 cgx_id, lmac_id;857 858 if (!is_cgx_config_permitted(rvu, pcifunc))859 return -EPERM;860 861 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);862 863 if (en) {864 set_bit(pf, &rvu->pf_notify_bmap);865 /* Send the current link status to PF */866 rvu_cgx_send_link_info(cgx_id, lmac_id, rvu);867 } else {868 clear_bit(pf, &rvu->pf_notify_bmap);869 }870 871 return 0;872}873 874int rvu_mbox_handler_cgx_start_linkevents(struct rvu *rvu, struct msg_req *req,875 struct msg_rsp *rsp)876{877 rvu_cgx_config_linkevents(rvu, req->hdr.pcifunc, true);878 return 0;879}880 881int rvu_mbox_handler_cgx_stop_linkevents(struct rvu *rvu, struct msg_req *req,882 struct msg_rsp *rsp)883{884 rvu_cgx_config_linkevents(rvu, req->hdr.pcifunc, false);885 return 0;886}887 888int rvu_mbox_handler_cgx_get_linkinfo(struct rvu *rvu, struct msg_req *req,889 struct cgx_link_info_msg *rsp)890{891 u8 cgx_id, lmac_id;892 int pf, err;893 894 pf = rvu_get_pf(req->hdr.pcifunc);895 896 if (!is_pf_cgxmapped(rvu, pf))897 return -ENODEV;898 899 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);900 901 err = cgx_get_link_info(rvu_cgx_pdata(cgx_id, rvu), lmac_id,902 &rsp->link_info);903 return err;904}905 906int rvu_mbox_handler_cgx_features_get(struct rvu *rvu,907 struct msg_req *req,908 struct cgx_features_info_msg *rsp)909{910 int pf = rvu_get_pf(req->hdr.pcifunc);911 u8 cgx_idx, lmac;912 void *cgxd;913 914 if (!is_pf_cgxmapped(rvu, pf))915 return 0;916 917 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_idx, &lmac);918 cgxd = rvu_cgx_pdata(cgx_idx, rvu);919 rsp->lmac_features = cgx_features_get(cgxd);920 921 return 0;922}923 924u32 rvu_cgx_get_fifolen(struct rvu *rvu)925{926 struct mac_ops *mac_ops;927 u32 fifo_len;928 929 mac_ops = get_mac_ops(rvu_first_cgx_pdata(rvu));930 fifo_len = mac_ops ? mac_ops->fifo_len : 0;931 932 return fifo_len;933}934 935u32 rvu_cgx_get_lmac_fifolen(struct rvu *rvu, int cgx, int lmac)936{937 struct mac_ops *mac_ops;938 void *cgxd;939 940 cgxd = rvu_cgx_pdata(cgx, rvu);941 if (!cgxd)942 return 0;943 944 mac_ops = get_mac_ops(cgxd);945 if (!mac_ops->lmac_fifo_len)946 return 0;947 948 return mac_ops->lmac_fifo_len(cgxd, lmac);949}950 951static int rvu_cgx_config_intlbk(struct rvu *rvu, u16 pcifunc, bool en)952{953 int pf = rvu_get_pf(pcifunc);954 struct mac_ops *mac_ops;955 u8 cgx_id, lmac_id;956 957 if (!is_cgx_config_permitted(rvu, pcifunc))958 return -EPERM;959 960 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);961 mac_ops = get_mac_ops(rvu_cgx_pdata(cgx_id, rvu));962 963 return mac_ops->mac_lmac_intl_lbk(rvu_cgx_pdata(cgx_id, rvu),964 lmac_id, en);965}966 967int rvu_mbox_handler_cgx_intlbk_enable(struct rvu *rvu, struct msg_req *req,968 struct msg_rsp *rsp)969{970 rvu_cgx_config_intlbk(rvu, req->hdr.pcifunc, true);971 return 0;972}973 974int rvu_mbox_handler_cgx_intlbk_disable(struct rvu *rvu, struct msg_req *req,975 struct msg_rsp *rsp)976{977 rvu_cgx_config_intlbk(rvu, req->hdr.pcifunc, false);978 return 0;979}980 981int rvu_cgx_cfg_pause_frm(struct rvu *rvu, u16 pcifunc, u8 tx_pause, u8 rx_pause)982{983 int pf = rvu_get_pf(pcifunc);984 u8 rx_pfc = 0, tx_pfc = 0;985 struct mac_ops *mac_ops;986 u8 cgx_id, lmac_id;987 void *cgxd;988 989 if (!is_mac_feature_supported(rvu, pf, RVU_LMAC_FEAT_FC))990 return 0;991 992 /* This msg is expected only from PF/VFs that are mapped to CGX LMACs,993 * if received from other PF/VF simply ACK, nothing to do.994 */995 if (!is_pf_cgxmapped(rvu, pf))996 return LMAC_AF_ERR_PF_NOT_MAPPED;997 998 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);999 cgxd = rvu_cgx_pdata(cgx_id, rvu);1000 mac_ops = get_mac_ops(cgxd);1001 1002 mac_ops->mac_get_pfc_frm_cfg(cgxd, lmac_id, &tx_pfc, &rx_pfc);1003 if (tx_pfc || rx_pfc) {1004 dev_warn(rvu->dev,1005 "Can not configure 802.3X flow control as PFC frames are enabled");1006 return LMAC_AF_ERR_8023PAUSE_ENADIS_PERM_DENIED;1007 }1008 1009 mutex_lock(&rvu->rsrc_lock);1010 if (verify_lmac_fc_cfg(cgxd, lmac_id, tx_pause, rx_pause,1011 pcifunc & RVU_PFVF_FUNC_MASK)) {1012 mutex_unlock(&rvu->rsrc_lock);1013 return LMAC_AF_ERR_PERM_DENIED;1014 }1015 mutex_unlock(&rvu->rsrc_lock);1016 1017 return mac_ops->mac_enadis_pause_frm(cgxd, lmac_id, tx_pause, rx_pause);1018}1019 1020int rvu_mbox_handler_cgx_cfg_pause_frm(struct rvu *rvu,1021 struct cgx_pause_frm_cfg *req,1022 struct cgx_pause_frm_cfg *rsp)1023{1024 int pf = rvu_get_pf(req->hdr.pcifunc);1025 struct mac_ops *mac_ops;1026 u8 cgx_id, lmac_id;1027 int err = 0;1028 void *cgxd;1029 1030 /* This msg is expected only from PF/VFs that are mapped to CGX LMACs,1031 * if received from other PF/VF simply ACK, nothing to do.1032 */1033 if (!is_pf_cgxmapped(rvu, pf))1034 return -ENODEV;1035 1036 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);1037 cgxd = rvu_cgx_pdata(cgx_id, rvu);1038 mac_ops = get_mac_ops(cgxd);1039 1040 if (req->set)1041 err = rvu_cgx_cfg_pause_frm(rvu, req->hdr.pcifunc, req->tx_pause, req->rx_pause);1042 else1043 mac_ops->mac_get_pause_frm_status(cgxd, lmac_id, &rsp->tx_pause, &rsp->rx_pause);1044 1045 return err;1046}1047 1048int rvu_mbox_handler_cgx_get_phy_fec_stats(struct rvu *rvu, struct msg_req *req,1049 struct msg_rsp *rsp)1050{1051 int pf = rvu_get_pf(req->hdr.pcifunc);1052 u8 cgx_id, lmac_id;1053 1054 if (!is_pf_cgxmapped(rvu, pf))1055 return LMAC_AF_ERR_PF_NOT_MAPPED;1056 1057 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);1058 return cgx_get_phy_fec_stats(rvu_cgx_pdata(cgx_id, rvu), lmac_id);1059}1060 1061/* Finds cumulative status of NIX rx/tx counters from LF of a PF and those1062 * from its VFs as well. ie. NIX rx/tx counters at the CGX port level1063 */1064int rvu_cgx_nix_cuml_stats(struct rvu *rvu, void *cgxd, int lmac_id,1065 int index, int rxtxflag, u64 *stat)1066{1067 struct rvu_block *block;1068 int blkaddr;1069 u16 pcifunc;1070 int pf, lf;1071 1072 *stat = 0;1073 1074 if (!cgxd || !rvu)1075 return -EINVAL;1076 1077 pf = cgxlmac_to_pf(rvu, cgx_get_cgxid(cgxd), lmac_id);1078 if (pf < 0)1079 return pf;1080 1081 /* Assumes LF of a PF and all of its VF belongs to the same1082 * NIX block1083 */1084 pcifunc = pf << RVU_PFVF_PF_SHIFT;1085 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc);1086 if (blkaddr < 0)1087 return 0;1088 block = &rvu->hw->block[blkaddr];1089 1090 for (lf = 0; lf < block->lf.max; lf++) {1091 /* Check if a lf is attached to this PF or one of its VFs */1092 if (!((block->fn_map[lf] & ~RVU_PFVF_FUNC_MASK) == (pcifunc &1093 ~RVU_PFVF_FUNC_MASK)))1094 continue;1095 if (rxtxflag == NIX_STATS_RX)1096 *stat += rvu_read64(rvu, blkaddr,1097 NIX_AF_LFX_RX_STATX(lf, index));1098 else1099 *stat += rvu_read64(rvu, blkaddr,1100 NIX_AF_LFX_TX_STATX(lf, index));1101 }1102 1103 return 0;1104}1105 1106int rvu_cgx_start_stop_io(struct rvu *rvu, u16 pcifunc, bool start)1107{1108 struct rvu_pfvf *parent_pf, *pfvf;1109 int cgx_users, err = 0;1110 1111 if (!is_pf_cgxmapped(rvu, rvu_get_pf(pcifunc)))1112 return 0;1113 1114 parent_pf = &rvu->pf[rvu_get_pf(pcifunc)];1115 pfvf = rvu_get_pfvf(rvu, pcifunc);1116 1117 mutex_lock(&rvu->cgx_cfg_lock);1118 1119 if (start && pfvf->cgx_in_use)1120 goto exit; /* CGX is already started hence nothing to do */1121 if (!start && !pfvf->cgx_in_use)1122 goto exit; /* CGX is already stopped hence nothing to do */1123 1124 if (start) {1125 cgx_users = parent_pf->cgx_users;1126 parent_pf->cgx_users++;1127 } else {1128 parent_pf->cgx_users--;1129 cgx_users = parent_pf->cgx_users;1130 }1131 1132 /* Start CGX when first of all NIXLFs is started.1133 * Stop CGX when last of all NIXLFs is stopped.1134 */1135 if (!cgx_users) {1136 err = rvu_cgx_config_rxtx(rvu, pcifunc & ~RVU_PFVF_FUNC_MASK,1137 start);1138 if (err) {1139 dev_err(rvu->dev, "Unable to %s CGX\n",1140 start ? "start" : "stop");1141 /* Revert the usage count in case of error */1142 parent_pf->cgx_users = start ? parent_pf->cgx_users - 11143 : parent_pf->cgx_users + 1;1144 goto exit;1145 }1146 }1147 pfvf->cgx_in_use = start;1148exit:1149 mutex_unlock(&rvu->cgx_cfg_lock);1150 return err;1151}1152 1153int rvu_mbox_handler_cgx_set_fec_param(struct rvu *rvu,1154 struct fec_mode *req,1155 struct fec_mode *rsp)1156{1157 int pf = rvu_get_pf(req->hdr.pcifunc);1158 u8 cgx_id, lmac_id;1159 1160 if (!is_pf_cgxmapped(rvu, pf))1161 return -EPERM;1162 1163 if (req->fec == OTX2_FEC_OFF)1164 req->fec = OTX2_FEC_NONE;1165 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);1166 rsp->fec = cgx_set_fec(req->fec, cgx_id, lmac_id);1167 return 0;1168}1169 1170int rvu_mbox_handler_cgx_get_aux_link_info(struct rvu *rvu, struct msg_req *req,1171 struct cgx_fw_data *rsp)1172{1173 int pf = rvu_get_pf(req->hdr.pcifunc);1174 u8 cgx_id, lmac_id;1175 1176 if (!rvu->fwdata)1177 return LMAC_AF_ERR_FIRMWARE_DATA_NOT_MAPPED;1178 1179 if (!is_pf_cgxmapped(rvu, pf))1180 return -EPERM;1181 1182 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);1183 1184 if (rvu->hw->lmac_per_cgx == CGX_LMACS_USX)1185 memcpy(&rsp->fwdata,1186 &rvu->fwdata->cgx_fw_data_usx[cgx_id][lmac_id],1187 sizeof(struct cgx_lmac_fwdata_s));1188 else1189 memcpy(&rsp->fwdata,1190 &rvu->fwdata->cgx_fw_data[cgx_id][lmac_id],1191 sizeof(struct cgx_lmac_fwdata_s));1192 1193 return 0;1194}1195 1196int rvu_mbox_handler_cgx_set_link_mode(struct rvu *rvu,1197 struct cgx_set_link_mode_req *req,1198 struct cgx_set_link_mode_rsp *rsp)1199{1200 int pf = rvu_get_pf(req->hdr.pcifunc);1201 u8 cgx_idx, lmac;1202 void *cgxd;1203 1204 if (!is_cgx_config_permitted(rvu, req->hdr.pcifunc))1205 return -EPERM;1206 1207 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_idx, &lmac);1208 cgxd = rvu_cgx_pdata(cgx_idx, rvu);1209 rsp->status = cgx_set_link_mode(cgxd, req->args, cgx_idx, lmac);1210 return 0;1211}1212 1213int rvu_mbox_handler_cgx_mac_addr_reset(struct rvu *rvu, struct cgx_mac_addr_reset_req *req,1214 struct msg_rsp *rsp)1215{1216 int pf = rvu_get_pf(req->hdr.pcifunc);1217 u8 cgx_id, lmac_id;1218 1219 if (!is_cgx_config_permitted(rvu, req->hdr.pcifunc))1220 return LMAC_AF_ERR_PERM_DENIED;1221 1222 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);1223 1224 if (rvu_npc_exact_has_match_table(rvu))1225 return rvu_npc_exact_mac_addr_reset(rvu, req, rsp);1226 1227 return cgx_lmac_addr_reset(cgx_id, lmac_id);1228}1229 1230int rvu_mbox_handler_cgx_mac_addr_update(struct rvu *rvu,1231 struct cgx_mac_addr_update_req *req,1232 struct cgx_mac_addr_update_rsp *rsp)1233{1234 int pf = rvu_get_pf(req->hdr.pcifunc);1235 u8 cgx_id, lmac_id;1236 1237 if (!is_cgx_config_permitted(rvu, req->hdr.pcifunc))1238 return LMAC_AF_ERR_PERM_DENIED;1239 1240 if (rvu_npc_exact_has_match_table(rvu))1241 return rvu_npc_exact_mac_addr_update(rvu, req, rsp);1242 1243 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);1244 return cgx_lmac_addr_update(cgx_id, lmac_id, req->mac_addr, req->index);1245}1246 1247int rvu_cgx_prio_flow_ctrl_cfg(struct rvu *rvu, u16 pcifunc, u8 tx_pause,1248 u8 rx_pause, u16 pfc_en)1249{1250 int pf = rvu_get_pf(pcifunc);1251 u8 rx_8023 = 0, tx_8023 = 0;1252 struct mac_ops *mac_ops;1253 u8 cgx_id, lmac_id;1254 void *cgxd;1255 1256 /* This msg is expected only from PF/VFs that are mapped to CGX LMACs,1257 * if received from other PF/VF simply ACK, nothing to do.1258 */1259 if (!is_pf_cgxmapped(rvu, pf))1260 return -ENODEV;1261 1262 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);1263 cgxd = rvu_cgx_pdata(cgx_id, rvu);1264 mac_ops = get_mac_ops(cgxd);1265 1266 mac_ops->mac_get_pause_frm_status(cgxd, lmac_id, &tx_8023, &rx_8023);1267 if (tx_8023 || rx_8023) {1268 dev_warn(rvu->dev,1269 "Can not configure PFC as 802.3X pause frames are enabled");1270 return LMAC_AF_ERR_PFC_ENADIS_PERM_DENIED;1271 }1272 1273 mutex_lock(&rvu->rsrc_lock);1274 if (verify_lmac_fc_cfg(cgxd, lmac_id, tx_pause, rx_pause,1275 pcifunc & RVU_PFVF_FUNC_MASK)) {1276 mutex_unlock(&rvu->rsrc_lock);1277 return LMAC_AF_ERR_PERM_DENIED;1278 }1279 mutex_unlock(&rvu->rsrc_lock);1280 1281 return mac_ops->pfc_config(cgxd, lmac_id, tx_pause, rx_pause, pfc_en);1282}1283 1284int rvu_mbox_handler_cgx_prio_flow_ctrl_cfg(struct rvu *rvu,1285 struct cgx_pfc_cfg *req,1286 struct cgx_pfc_rsp *rsp)1287{1288 int pf = rvu_get_pf(req->hdr.pcifunc);1289 struct mac_ops *mac_ops;1290 u8 cgx_id, lmac_id;1291 void *cgxd;1292 int err;1293 1294 /* This msg is expected only from PF/VFs that are mapped to CGX LMACs,1295 * if received from other PF/VF simply ACK, nothing to do.1296 */1297 if (!is_pf_cgxmapped(rvu, pf))1298 return -ENODEV;1299 1300 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);1301 cgxd = rvu_cgx_pdata(cgx_id, rvu);1302 mac_ops = get_mac_ops(cgxd);1303 1304 err = rvu_cgx_prio_flow_ctrl_cfg(rvu, req->hdr.pcifunc, req->tx_pause,1305 req->rx_pause, req->pfc_en);1306 1307 mac_ops->mac_get_pfc_frm_cfg(cgxd, lmac_id, &rsp->tx_pause, &rsp->rx_pause);1308 return err;1309}1310 1311void rvu_mac_reset(struct rvu *rvu, u16 pcifunc)1312{1313 int pf = rvu_get_pf(pcifunc);1314 struct mac_ops *mac_ops;1315 struct cgx *cgxd;1316 u8 cgx, lmac;1317 1318 if (!is_pf_cgxmapped(rvu, pf))1319 return;1320 1321 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx, &lmac);1322 cgxd = rvu_cgx_pdata(cgx, rvu);1323 mac_ops = get_mac_ops(cgxd);1324 1325 if (mac_ops->mac_reset(cgxd, lmac, !is_vf(pcifunc)))1326 dev_err(rvu->dev, "Failed to reset MAC\n");1327}1328