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1// SPDX-License-Identifier: GPL-2.0-only2/* Copyright (C) 2020 Felix Fietkau <nbd@nbd.name> */3 4#ifndef __MTK_WED_REGS_H5#define __MTK_WED_REGS_H6 7#define MTK_WFDMA_DESC_CTRL_TO_HOST BIT(8)8#define MTK_WDMA_DESC_CTRL_LEN1 GENMASK(14, 0)9#define MTK_WDMA_DESC_CTRL_LEN1_V2 GENMASK(13, 0)10#define MTK_WDMA_DESC_CTRL_LAST_SEG1 BIT(15)11#define MTK_WDMA_DESC_CTRL_BURST BIT(16)12#define MTK_WDMA_DESC_CTRL_LEN0 GENMASK(29, 16)13#define MTK_WDMA_DESC_CTRL_LAST_SEG0 BIT(30)14#define MTK_WDMA_DESC_CTRL_DMA_DONE BIT(31)15 16#define MTK_WDMA_TXD0_DESC_INFO_DMA_DONE BIT(29)17#define MTK_WDMA_TXD1_DESC_INFO_DMA_DONE BIT(31)18 19struct mtk_wdma_desc {20 __le32 buf0;21 __le32 ctrl;22 __le32 buf1;23 __le32 info;24} __packed __aligned(4);25 26#define MTK_WED_REV_ID 0x00427 28#define MTK_WED_RESET 0x00829#define MTK_WED_RESET_TX_BM BIT(0)30#define MTK_WED_RESET_RX_BM BIT(1)31#define MTK_WED_RESET_RX_PG_BM BIT(2)32#define MTK_WED_RESET_RRO_RX_TO_PG BIT(3)33#define MTK_WED_RESET_TX_FREE_AGENT BIT(4)34#define MTK_WED_RESET_WPDMA_TX_DRV BIT(8)35#define MTK_WED_RESET_WPDMA_RX_DRV BIT(9)36#define MTK_WED_RESET_WPDMA_RX_D_DRV BIT(10)37#define MTK_WED_RESET_WPDMA_INT_AGENT BIT(11)38#define MTK_WED_RESET_WED_TX_DMA BIT(12)39#define MTK_WED_RESET_WED_RX_DMA BIT(13)40#define MTK_WED_RESET_WDMA_TX_DRV BIT(16)41#define MTK_WED_RESET_WDMA_RX_DRV BIT(17)42#define MTK_WED_RESET_WDMA_INT_AGENT BIT(19)43#define MTK_WED_RESET_RX_RRO_QM BIT(20)44#define MTK_WED_RESET_RX_ROUTE_QM BIT(21)45#define MTK_WED_RESET_TX_AMSDU BIT(22)46#define MTK_WED_RESET_WED BIT(31)47 48#define MTK_WED_CTRL 0x00c49#define MTK_WED_CTRL_WPDMA_INT_AGENT_EN BIT(0)50#define MTK_WED_CTRL_WPDMA_INT_AGENT_BUSY BIT(1)51#define MTK_WED_CTRL_WDMA_INT_AGENT_EN BIT(2)52#define MTK_WED_CTRL_WDMA_INT_AGENT_BUSY BIT(3)53#define MTK_WED_CTRL_WED_RX_IND_CMD_EN BIT(5)54#define MTK_WED_CTRL_WED_RX_PG_BM_EN BIT(6)55#define MTK_WED_CTRL_WED_RX_PG_BM_BUSY BIT(7)56#define MTK_WED_CTRL_WED_TX_BM_EN BIT(8)57#define MTK_WED_CTRL_WED_TX_BM_BUSY BIT(9)58#define MTK_WED_CTRL_WED_TX_FREE_AGENT_EN BIT(10)59#define MTK_WED_CTRL_WED_TX_FREE_AGENT_BUSY BIT(11)60#define MTK_WED_CTRL_WED_RX_BM_EN BIT(12)61#define MTK_WED_CTRL_WED_RX_BM_BUSY BIT(13)62#define MTK_WED_CTRL_RX_RRO_QM_EN BIT(14)63#define MTK_WED_CTRL_RX_RRO_QM_BUSY BIT(15)64#define MTK_WED_CTRL_RX_ROUTE_QM_EN BIT(16)65#define MTK_WED_CTRL_RX_ROUTE_QM_BUSY BIT(17)66#define MTK_WED_CTRL_TX_TKID_ALI_EN BIT(20)67#define MTK_WED_CTRL_TX_TKID_ALI_BUSY BIT(21)68#define MTK_WED_CTRL_TX_AMSDU_EN BIT(22)69#define MTK_WED_CTRL_TX_AMSDU_BUSY BIT(23)70#define MTK_WED_CTRL_FINAL_DIDX_READ BIT(24)71#define MTK_WED_CTRL_ETH_DMAD_FMT BIT(25)72#define MTK_WED_CTRL_MIB_READ_CLEAR BIT(28)73#define MTK_WED_CTRL_FLD_MIB_RD_CLR BIT(28)74 75#define MTK_WED_EXT_INT_STATUS 0x02076#define MTK_WED_EXT_INT_STATUS_TF_LEN_ERR BIT(0)77#define MTK_WED_EXT_INT_STATUS_TKID_WO_PYLD BIT(1)78#define MTK_WED_EXT_INT_STATUS_TKID_TITO_INVALID BIT(4)79#define MTK_WED_EXT_INT_STATUS_TX_FBUF_LO_TH BIT(8)80#define MTK_WED_EXT_INT_STATUS_TX_FBUF_HI_TH BIT(9)81#define MTK_WED_EXT_INT_STATUS_RX_FBUF_LO_TH BIT(10) /* wed v2 */82#define MTK_WED_EXT_INT_STATUS_RX_FBUF_HI_TH BIT(11) /* wed v2 */83#define MTK_WED_EXT_INT_STATUS_RX_DRV_R_RESP_ERR BIT(16)84#define MTK_WED_EXT_INT_STATUS_RX_DRV_W_RESP_ERR BIT(17)85#define MTK_WED_EXT_INT_STATUS_RX_DRV_COHERENT BIT(18)86#define MTK_WED_EXT_INT_STATUS_RX_DRV_INIT_WDMA_EN BIT(19)87#define MTK_WED_EXT_INT_STATUS_RX_DRV_BM_DMAD_COHERENT BIT(20)88#define MTK_WED_EXT_INT_STATUS_TX_DRV_R_RESP_ERR BIT(21)89#define MTK_WED_EXT_INT_STATUS_TX_DMA_R_RESP_ERR BIT(22)90#define MTK_WED_EXT_INT_STATUS_TX_DMA_W_RESP_ERR BIT(23)91#define MTK_WED_EXT_INT_STATUS_RX_DRV_DMA_RECYCLE BIT(24)92#define MTK_WED_EXT_INT_STATUS_RX_DRV_GET_BM_DMAD_SKIP BIT(25)93#define MTK_WED_EXT_INT_STATUS_WPDMA_RX_D_DRV_ERR BIT(26)94#define MTK_WED_EXT_INT_STATUS_WPDMA_MID_RDY BIT(27)95#define MTK_WED_EXT_INT_STATUS_ERROR_MASK (MTK_WED_EXT_INT_STATUS_TF_LEN_ERR | \96 MTK_WED_EXT_INT_STATUS_TKID_WO_PYLD | \97 MTK_WED_EXT_INT_STATUS_TKID_TITO_INVALID | \98 MTK_WED_EXT_INT_STATUS_RX_DRV_R_RESP_ERR | \99 MTK_WED_EXT_INT_STATUS_RX_DRV_W_RESP_ERR | \100 MTK_WED_EXT_INT_STATUS_RX_DRV_INIT_WDMA_EN | \101 MTK_WED_EXT_INT_STATUS_TX_DMA_R_RESP_ERR)102 103#define MTK_WED_EXT_INT_MASK 0x028104#define MTK_WED_EXT_INT_MASK1 0x02c105#define MTK_WED_EXT_INT_MASK2 0x030106#define MTK_WED_EXT_INT_MASK3 0x034107 108#define MTK_WED_STATUS 0x060109#define MTK_WED_STATUS_TX GENMASK(15, 8)110 111#define MTK_WED_WPDMA_STATUS 0x068112#define MTK_WED_WPDMA_STATUS_TX_DRV GENMASK(15, 8)113 114#define MTK_WED_TX_BM_CTRL 0x080115#define MTK_WED_TX_BM_CTRL_VLD_GRP_NUM GENMASK(6, 0)116#define MTK_WED_TX_BM_CTRL_RSV_GRP_NUM GENMASK(22, 16)117#define MTK_WED_TX_BM_CTRL_LEGACY_EN BIT(26)118#define MTK_WED_TX_TKID_CTRL_FREE_FORMAT BIT(27)119#define MTK_WED_TX_BM_CTRL_PAUSE BIT(28)120 121#define MTK_WED_TX_BM_BASE 0x084122#define MTK_WED_TX_BM_INIT_PTR 0x088123#define MTK_WED_TX_BM_SW_TAIL_IDX GENMASK(16, 0)124#define MTK_WED_TX_BM_INIT_SW_TAIL_IDX BIT(16)125 126#define MTK_WED_TX_BM_TKID_START GENMASK(15, 0)127#define MTK_WED_TX_BM_TKID_END GENMASK(31, 16)128 129#define MTK_WED_TX_BM_BUF_LEN 0x08c130 131#define MTK_WED_TX_BM_INTF 0x09c132#define MTK_WED_TX_BM_INTF_TKID GENMASK(15, 0)133#define MTK_WED_TX_BM_INTF_TKFIFO_FDEP GENMASK(23, 16)134#define MTK_WED_TX_BM_INTF_TKID_VALID BIT(28)135#define MTK_WED_TX_BM_INTF_TKID_READ BIT(29)136 137#define MTK_WED_TX_BM_DYN_THR 0x0a0138#define MTK_WED_TX_BM_DYN_THR_LO GENMASK(6, 0)139#define MTK_WED_TX_BM_DYN_THR_LO_V2 GENMASK(8, 0)140#define MTK_WED_TX_BM_DYN_THR_HI GENMASK(22, 16)141#define MTK_WED_TX_BM_DYN_THR_HI_V2 GENMASK(24, 16)142 143#define MTK_WED_TX_TKID_CTRL 0x0c0144#define MTK_WED_TX_TKID_CTRL_VLD_GRP_NUM GENMASK(6, 0)145#define MTK_WED_TX_TKID_CTRL_RSV_GRP_NUM GENMASK(22, 16)146#define MTK_WED_TX_TKID_CTRL_PAUSE BIT(28)147 148#define MTK_WED_TX_TKID_INTF 0x0dc149#define MTK_WED_TX_TKID_INTF_TKFIFO_FDEP GENMASK(25, 16)150 151#define MTK_WED_TX_TKID_CTRL_VLD_GRP_NUM_V3 GENMASK(7, 0)152#define MTK_WED_TX_TKID_CTRL_RSV_GRP_NUM_V3 GENMASK(23, 16)153 154#define MTK_WED_TX_TKID_DYN_THR 0x0e0155#define MTK_WED_TX_TKID_DYN_THR_LO GENMASK(6, 0)156#define MTK_WED_TX_TKID_DYN_THR_HI GENMASK(22, 16)157 158#define MTK_WED_TXP_DW0 0x120159#define MTK_WED_TXP_DW1 0x124160#define MTK_WED_WPDMA_WRITE_TXP GENMASK(31, 16)161#define MTK_WED_TXDP_CTRL 0x130162#define MTK_WED_TXDP_DW9_OVERWR BIT(9)163#define MTK_WED_RX_BM_TKID_MIB 0x1cc164 165#define MTK_WED_INT_STATUS 0x200166#define MTK_WED_INT_MASK 0x204167 168#define MTK_WED_GLO_CFG 0x208169#define MTK_WED_GLO_CFG_TX_DMA_EN BIT(0)170#define MTK_WED_GLO_CFG_TX_DMA_BUSY BIT(1)171#define MTK_WED_GLO_CFG_RX_DMA_EN BIT(2)172#define MTK_WED_GLO_CFG_RX_DMA_BUSY BIT(3)173#define MTK_WED_GLO_CFG_RX_BT_SIZE GENMASK(5, 4)174#define MTK_WED_GLO_CFG_TX_WB_DDONE BIT(6)175#define MTK_WED_GLO_CFG_BIG_ENDIAN BIT(7)176#define MTK_WED_GLO_CFG_DIS_BT_SIZE_ALIGN BIT(8)177#define MTK_WED_GLO_CFG_TX_BT_SIZE_LO BIT(9)178#define MTK_WED_GLO_CFG_MULTI_DMA_EN GENMASK(11, 10)179#define MTK_WED_GLO_CFG_FIFO_LITTLE_ENDIAN BIT(12)180#define MTK_WED_GLO_CFG_MI_DEPTH_RD GENMASK(21, 13)181#define MTK_WED_GLO_CFG_TX_BT_SIZE_HI GENMASK(23, 22)182#define MTK_WED_GLO_CFG_SW_RESET BIT(24)183#define MTK_WED_GLO_CFG_FIRST_TOKEN_ONLY BIT(26)184#define MTK_WED_GLO_CFG_OMIT_RX_INFO BIT(27)185#define MTK_WED_GLO_CFG_OMIT_TX_INFO BIT(28)186#define MTK_WED_GLO_CFG_BYTE_SWAP BIT(29)187#define MTK_WED_GLO_CFG_RX_2B_OFFSET BIT(31)188 189#define MTK_WED_RESET_IDX 0x20c190#define MTK_WED_RESET_WPDMA_IDX_RX GENMASK(31, 30)191 192#define MTK_WED_TX_MIB(_n) (0x2a0 + (_n) * 4)193#define MTK_WED_RX_MIB(_n) (0x2e0 + (_n) * 4)194 195#define MTK_WED_RING_TX(_n) (0x300 + (_n) * 0x10)196 197#define MTK_WED_RING_RX(_n) (0x400 + (_n) * 0x10)198#define MTK_WED_RING_RX_DATA(_n) (0x420 + (_n) * 0x10)199 200#define MTK_WED_SCR0 0x3c0201#define MTK_WED_RX1_CTRL2 0x418202#define MTK_WED_WPDMA_INT_TRIGGER 0x504203#define MTK_WED_WPDMA_INT_TRIGGER_RX_DONE BIT(1)204#define MTK_WED_WPDMA_INT_TRIGGER_TX_DONE GENMASK(5, 4)205 206#define MTK_WED_WPDMA_GLO_CFG 0x508207#define MTK_WED_WPDMA_GLO_CFG_TX_DRV_EN BIT(0)208#define MTK_WED_WPDMA_GLO_CFG_TX_DRV_BUSY BIT(1)209#define MTK_WED_WPDMA_GLO_CFG_RX_DRV_EN BIT(2)210#define MTK_WED_WPDMA_GLO_CFG_RX_DRV_BUSY BIT(3)211#define MTK_WED_WPDMA_GLO_CFG_RX_BT_SIZE GENMASK(5, 4)212#define MTK_WED_WPDMA_GLO_CFG_TX_WB_DDONE BIT(6)213#define MTK_WED_WPDMA_GLO_CFG_BIG_ENDIAN BIT(7)214#define MTK_WED_WPDMA_GLO_CFG_DIS_BT_SIZE_ALIGN BIT(8)215#define MTK_WED_WPDMA_GLO_CFG_TX_BT_SIZE_LO BIT(9)216#define MTK_WED_WPDMA_GLO_CFG_MULTI_DMA_EN GENMASK(11, 10)217#define MTK_WED_WPDMA_GLO_CFG_FIFO_LITTLE_ENDIAN BIT(12)218#define MTK_WED_WPDMA_GLO_CFG_MI_DEPTH_RD GENMASK(21, 13)219#define MTK_WED_WPDMA_GLO_CFG_TX_BT_SIZE_HI GENMASK(23, 22)220#define MTK_WED_WPDMA_GLO_CFG_SW_RESET BIT(24)221#define MTK_WED_WPDMA_GLO_CFG_FIRST_TOKEN_ONLY BIT(26)222#define MTK_WED_WPDMA_GLO_CFG_OMIT_RX_INFO BIT(27)223#define MTK_WED_WPDMA_GLO_CFG_OMIT_TX_INFO BIT(28)224#define MTK_WED_WPDMA_GLO_CFG_BYTE_SWAP BIT(29)225#define MTK_WED_WPDMA_GLO_CFG_RX_2B_OFFSET BIT(31)226 227/* CONFIG_MEDIATEK_NETSYS_V2 */228#define MTK_WED_WPDMA_GLO_CFG_RX_DRV_R0_PKT_PROC BIT(4)229#define MTK_WED_WPDMA_GLO_CFG_RX_DRV_R1_PKT_PROC BIT(5)230#define MTK_WED_WPDMA_GLO_CFG_RX_DRV_R0_CRX_SYNC BIT(6)231#define MTK_WED_WPDMA_GLO_CFG_RX_DRV_R1_CRX_SYNC BIT(7)232#define MTK_WED_WPDMA_GLO_CFG_RX_DRV_EVENT_PKT_FMT_VER GENMASK(15, 12)233#define MTK_WED_WPDMA_GLO_CFG_RX_DRV_UNS_VER_FORCE_4 BIT(18)234#define MTK_WED_WPDMA_GLO_CFG_RX_DRV_UNSUPPORT_FMT BIT(19)235#define MTK_WED_WPDMA_GLO_CFG_RX_DRV_EVENT_PKT_FMT_CHK BIT(20)236#define MTK_WED_WPDMA_GLO_CFG_RX_DDONE2_WR BIT(21)237#define MTK_WED_WPDMA_GLO_CFG_TX_TKID_KEEP BIT(24)238#define MTK_WED_WPDMA_GLO_CFG_TX_DDONE_CHK_LAST BIT(25)239#define MTK_WED_WPDMA_GLO_CFG_TX_DMAD_DW3_PREV BIT(28)240#define MTK_WED_WPDMA_GLO_CFG_TX_DDONE_CHK BIT(30)241 242#define MTK_WED_WPDMA_RESET_IDX 0x50c243#define MTK_WED_WPDMA_RESET_IDX_TX GENMASK(3, 0)244#define MTK_WED_WPDMA_RESET_IDX_RX GENMASK(17, 16)245 246#define MTK_WED_WPDMA_CTRL 0x518247#define MTK_WED_WPDMA_CTRL_SDL1_FIXED BIT(31)248 249#define MTK_WED_WPDMA_INT_CTRL 0x520250#define MTK_WED_WPDMA_INT_CTRL_SUBRT_ADV BIT(21)251#define MTK_WED_WPDMA_INT_CTRL_SIG_SRC BIT(22)252#define MTK_WED_WPDMA_INT_CTRL_SRC_SEL GENMASK(17, 16)253 254#define MTK_WED_WPDMA_INT_MASK 0x524255 256#define MTK_WED_WPDMA_INT_CTRL_TX 0x530257#define MTK_WED_WPDMA_INT_CTRL_TX0_DONE_EN BIT(0)258#define MTK_WED_WPDMA_INT_CTRL_TX0_DONE_CLR BIT(1)259#define MTK_WED_WPDMA_INT_CTRL_TX0_DONE_TRIG GENMASK(6, 2)260#define MTK_WED_WPDMA_INT_CTRL_TX1_DONE_EN BIT(8)261#define MTK_WED_WPDMA_INT_CTRL_TX1_DONE_CLR BIT(9)262#define MTK_WED_WPDMA_INT_CTRL_TX1_DONE_TRIG GENMASK(14, 10)263 264#define MTK_WED_WPDMA_INT_CTRL_RX 0x534265#define MTK_WED_WPDMA_INT_CTRL_RX0_EN BIT(0)266#define MTK_WED_WPDMA_INT_CTRL_RX0_CLR BIT(1)267#define MTK_WED_WPDMA_INT_CTRL_RX0_DONE_TRIG GENMASK(6, 2)268#define MTK_WED_WPDMA_INT_CTRL_RX1_EN BIT(8)269#define MTK_WED_WPDMA_INT_CTRL_RX1_CLR BIT(9)270#define MTK_WED_WPDMA_INT_CTRL_RX1_DONE_TRIG GENMASK(14, 10)271 272#define MTK_WED_WPDMA_INT_CTRL_TX_FREE 0x538273#define MTK_WED_WPDMA_INT_CTRL_TX_FREE_DONE_EN BIT(0)274#define MTK_WED_WPDMA_INT_CTRL_TX_FREE_DONE_CLR BIT(1)275#define MTK_WED_WPDMA_INT_CTRL_TX_FREE_DONE_TRIG GENMASK(6, 2)276 277#define MTK_WED_PCIE_CFG_BASE 0x560278 279#define MTK_WED_PCIE_CFG_BASE 0x560280#define MTK_WED_PCIE_CFG_INTM 0x564281#define MTK_WED_PCIE_CFG_MSIS 0x568282#define MTK_WED_PCIE_INT_TRIGGER 0x570283#define MTK_WED_PCIE_INT_TRIGGER_STATUS BIT(16)284 285#define MTK_WED_PCIE_INT_CTRL 0x57c286#define MTK_WED_PCIE_INT_CTRL_POLL_EN GENMASK(13, 12)287#define MTK_WED_PCIE_INT_CTRL_SRC_SEL GENMASK(17, 16)288#define MTK_WED_PCIE_INT_CTRL_MSK_EN_POLA BIT(20)289#define MTK_WED_PCIE_INT_CTRL_MSK_IRQ_FILTER BIT(21)290 291#define MTK_WED_WPDMA_CFG_BASE 0x580292#define MTK_WED_WPDMA_CFG_INT_MASK 0x584293#define MTK_WED_WPDMA_CFG_TX 0x588294#define MTK_WED_WPDMA_CFG_TX_FREE 0x58c295 296#define MTK_WED_WPDMA_TX_MIB(_n) (0x5a0 + (_n) * 4)297#define MTK_WED_WPDMA_TX_COHERENT_MIB(_n) (0x5d0 + (_n) * 4)298#define MTK_WED_WPDMA_RX_MIB(_n) (0x5e0 + (_n) * 4)299#define MTK_WED_WPDMA_RX_COHERENT_MIB(_n) (0x5f0 + (_n) * 4)300 301#define MTK_WED_WPDMA_RING_TX(_n) (0x600 + (_n) * 0x10)302#define MTK_WED_WPDMA_RING_RX(_n) (0x700 + (_n) * 0x10)303#define MTK_WED_WPDMA_RING_RX_DATA(_n) (0x730 + (_n) * 0x10)304 305#define MTK_WED_WPDMA_RX_D_GLO_CFG 0x75c306#define MTK_WED_WPDMA_RX_D_RX_DRV_EN BIT(0)307#define MTK_WED_WPDMA_RX_D_RX_DRV_BUSY BIT(1)308#define MTK_WED_WPDMA_RX_D_FSM_RETURN_IDLE BIT(3)309#define MTK_WED_WPDMA_RX_D_RST_INIT_COMPLETE BIT(4)310#define MTK_WED_WPDMA_RX_D_INIT_PHASE_RXEN_SEL GENMASK(11, 7)311#define MTK_WED_WPDMA_RX_D_RXD_READ_LEN GENMASK(31, 24)312 313#define MTK_WED_WPDMA_RX_D_RST_IDX 0x760314#define MTK_WED_WPDMA_RX_D_RST_CRX_IDX GENMASK(17, 16)315#define MTK_WED_WPDMA_RX_D_RST_DRV_IDX_ALL BIT(20)316#define MTK_WED_WPDMA_RX_D_RST_DRV_IDX GENMASK(25, 24)317 318#define MTK_WED_WPDMA_RX_GLO_CFG 0x76c319 320#define MTK_WED_WPDMA_RX_D_MIB(_n) (0x774 + (_n) * 4)321#define MTK_WED_WPDMA_RX_D_PROCESSED_MIB(_n) (0x784 + (_n) * 4)322#define MTK_WED_WPDMA_RX_D_COHERENT_MIB 0x78c323 324#define MTK_WED_WPDMA_RX_D_PREF_CFG 0x7b4325#define MTK_WED_WPDMA_RX_D_PREF_EN BIT(0)326#define MTK_WED_WPDMA_RX_D_PREF_BUSY BIT(1)327#define MTK_WED_WPDMA_RX_D_PREF_BURST_SIZE GENMASK(12, 8)328#define MTK_WED_WPDMA_RX_D_PREF_LOW_THRES GENMASK(21, 16)329 330#define MTK_WED_WPDMA_RX_D_PREF_RX0_SIDX 0x7b8331#define MTK_WED_WPDMA_RX_D_PREF_SIDX_IDX_CLR BIT(15)332 333#define MTK_WED_WPDMA_RX_D_PREF_RX1_SIDX 0x7bc334 335#define MTK_WED_WPDMA_RX_D_PREF_FIFO_CFG 0x7c0336#define MTK_WED_WPDMA_RX_D_PREF_FIFO_CFG_R0_CLR BIT(0)337#define MTK_WED_WPDMA_RX_D_PREF_FIFO_CFG_R1_CLR BIT(16)338 339#define MTK_WED_WDMA_RING_TX 0x800340 341#define MTK_WED_WDMA_TX_MIB 0x810342 343#define MTK_WED_WDMA_RING_RX(_n) (0x900 + (_n) * 0x10)344#define MTK_WED_WDMA_RX_THRES(_n) (0x940 + (_n) * 0x4)345 346#define MTK_WED_WDMA_RX_PREF_CFG 0x950347#define MTK_WED_WDMA_RX_PREF_EN BIT(0)348#define MTK_WED_WDMA_RX_PREF_BUSY BIT(1)349#define MTK_WED_WDMA_RX_PREF_BURST_SIZE GENMASK(12, 8)350#define MTK_WED_WDMA_RX_PREF_LOW_THRES GENMASK(21, 16)351#define MTK_WED_WDMA_RX_PREF_RX0_SIDX_CLR BIT(24)352#define MTK_WED_WDMA_RX_PREF_RX1_SIDX_CLR BIT(25)353#define MTK_WED_WDMA_RX_PREF_DDONE2_EN BIT(26)354#define MTK_WED_WDMA_RX_PREF_DDONE2_BUSY BIT(27)355 356#define MTK_WED_WDMA_RX_PREF_FIFO_CFG 0x95C357#define MTK_WED_WDMA_RX_PREF_FIFO_RX0_CLR BIT(0)358#define MTK_WED_WDMA_RX_PREF_FIFO_RX1_CLR BIT(16)359 360#define MTK_WED_WDMA_GLO_CFG 0xa04361#define MTK_WED_WDMA_GLO_CFG_TX_DRV_EN BIT(0)362#define MTK_WED_WDMA_GLO_CFG_TX_DDONE_CHK BIT(1)363#define MTK_WED_WDMA_GLO_CFG_RX_DRV_EN BIT(2)364#define MTK_WED_WDMA_GLO_CFG_RX_DRV_BUSY BIT(3)365#define MTK_WED_WDMA_GLO_CFG_BT_SIZE GENMASK(5, 4)366#define MTK_WED_WDMA_GLO_CFG_TX_WB_DDONE BIT(6)367#define MTK_WED_WDMA_GLO_CFG_RX_DIS_FSM_AUTO_IDLE BIT(13)368#define MTK_WED_WDMA_GLO_CFG_WCOMPLETE_SEL BIT(16)369#define MTK_WED_WDMA_GLO_CFG_INIT_PHASE_RXDMA_BYPASS BIT(17)370#define MTK_WED_WDMA_GLO_CFG_INIT_PHASE_BYPASS BIT(18)371#define MTK_WED_WDMA_GLO_CFG_FSM_RETURN_IDLE BIT(19)372#define MTK_WED_WDMA_GLO_CFG_WAIT_COHERENT BIT(20)373#define MTK_WED_WDMA_GLO_CFG_AXI_W_AFTER_AW BIT(21)374#define MTK_WED_WDMA_GLO_CFG_IDLE_DMAD_SUPPLY_SINGLE_W BIT(22)375#define MTK_WED_WDMA_GLO_CFG_IDLE_DMAD_SUPPLY BIT(23)376#define MTK_WED_WDMA_GLO_CFG_DYNAMIC_SKIP_DMAD_PREP BIT(24)377#define MTK_WED_WDMA_GLO_CFG_DYNAMIC_DMAD_RECYCLE BIT(25)378#define MTK_WED_WDMA_GLO_CFG_RST_INIT_COMPLETE BIT(26)379#define MTK_WED_WDMA_GLO_CFG_RXDRV_CLKGATE_BYPASS BIT(30)380 381#define MTK_WED_WDMA_RESET_IDX 0xa08382#define MTK_WED_WDMA_RESET_IDX_RX GENMASK(17, 16)383#define MTK_WED_WDMA_RESET_IDX_RX_ALL BIT(20)384#define MTK_WED_WDMA_RESET_IDX_DRV GENMASK(25, 24)385 386#define MTK_WED_WDMA_INT_CLR 0xa24387#define MTK_WED_WDMA_INT_CLR_RX_DONE GENMASK(17, 16)388 389#define MTK_WED_WDMA_INT_TRIGGER 0xa28390#define MTK_WED_WDMA_INT_TRIGGER_RX_DONE GENMASK(17, 16)391 392#define MTK_WED_WDMA_INT_CTRL 0xa2c393#define MTK_WED_WDMA_INT_POLL_PRD GENMASK(7, 0)394#define MTK_WED_WDMA_INT_CTRL_POLL_SRC_SEL GENMASK(17, 16)395 396#define MTK_WED_WDMA_CFG_BASE 0xaa0397#define MTK_WED_WDMA_OFFSET0 0xaa4398#define MTK_WED_WDMA_OFFSET1 0xaa8399 400#define MTK_WED_WDMA_OFST0_GLO_INTS GENMASK(15, 0)401#define MTK_WED_WDMA_OFST0_GLO_CFG GENMASK(31, 16)402#define MTK_WED_WDMA_OFST1_TX_CTRL GENMASK(15, 0)403#define MTK_WED_WDMA_OFST1_RX_CTRL GENMASK(31, 16)404 405#define MTK_WED_WDMA_RX_MIB(_n) (0xae0 + (_n) * 4)406#define MTK_WED_WDMA_RX_RECYCLE_MIB(_n) (0xae8 + (_n) * 4)407#define MTK_WED_WDMA_RX_PROCESSED_MIB(_n) (0xaf0 + (_n) * 4)408 409#define MTK_WED_RX_BM_RX_DMAD 0xd80410#define MTK_WED_RX_BM_RX_DMAD_SDL0 GENMASK(13, 0)411 412#define MTK_WED_RX_BM_BASE 0xd84413#define MTK_WED_RX_BM_INIT_PTR 0xd88414#define MTK_WED_RX_BM_SW_TAIL GENMASK(15, 0)415#define MTK_WED_RX_BM_INIT_SW_TAIL BIT(16)416 417#define MTK_WED_RX_PTR 0xd8c418 419#define MTK_WED_RX_BM_DYN_ALLOC_TH 0xdb4420#define MTK_WED_RX_BM_DYN_ALLOC_TH_H GENMASK(31, 16)421#define MTK_WED_RX_BM_DYN_ALLOC_TH_L GENMASK(15, 0)422 423#define MTK_WED_RING_OFS_BASE 0x00424#define MTK_WED_RING_OFS_COUNT 0x04425#define MTK_WED_RING_OFS_CPU_IDX 0x08426#define MTK_WED_RING_OFS_DMA_IDX 0x0c427 428#define MTK_WDMA_RING_TX(_n) (0x000 + (_n) * 0x10)429#define MTK_WDMA_RING_RX(_n) (0x100 + (_n) * 0x10)430 431#define MTK_WDMA_GLO_CFG 0x204432#define MTK_WDMA_GLO_CFG_TX_DMA_EN BIT(0)433#define MTK_WDMA_GLO_CFG_TX_DMA_BUSY BIT(1)434#define MTK_WDMA_GLO_CFG_RX_DMA_EN BIT(2)435#define MTK_WDMA_GLO_CFG_RX_DMA_BUSY BIT(3)436#define MTK_WDMA_GLO_CFG_RX_INFO3_PRERES BIT(26)437#define MTK_WDMA_GLO_CFG_RX_INFO2_PRERES BIT(27)438#define MTK_WDMA_GLO_CFG_RX_INFO1_PRERES BIT(28)439 440#define MTK_WDMA_RESET_IDX 0x208441#define MTK_WDMA_RESET_IDX_TX GENMASK(3, 0)442#define MTK_WDMA_RESET_IDX_RX GENMASK(17, 16)443 444#define MTK_WDMA_INT_STATUS 0x220445 446#define MTK_WDMA_INT_MASK 0x228447#define MTK_WDMA_INT_MASK_TX_DONE GENMASK(3, 0)448#define MTK_WDMA_INT_MASK_RX_DONE GENMASK(17, 16)449#define MTK_WDMA_INT_MASK_TX_DELAY BIT(28)450#define MTK_WDMA_INT_MASK_TX_COHERENT BIT(29)451#define MTK_WDMA_INT_MASK_RX_DELAY BIT(30)452#define MTK_WDMA_INT_MASK_RX_COHERENT BIT(31)453 454#define MTK_WDMA_XDMA_TX_FIFO_CFG 0x238455#define MTK_WDMA_XDMA_TX_FIFO_CFG_TX_PAR_FIFO_CLEAR BIT(0)456#define MTK_WDMA_XDMA_TX_FIFO_CFG_TX_CMD_FIFO_CLEAR BIT(4)457#define MTK_WDMA_XDMA_TX_FIFO_CFG_TX_DMAD_FIFO_CLEAR BIT(8)458#define MTK_WDMA_XDMA_TX_FIFO_CFG_TX_ARR_FIFO_CLEAR BIT(12)459 460#define MTK_WDMA_XDMA_RX_FIFO_CFG 0x23c461#define MTK_WDMA_XDMA_RX_FIFO_CFG_RX_PAR_FIFO_CLEAR BIT(0)462#define MTK_WDMA_XDMA_RX_FIFO_CFG_RX_CMD_FIFO_CLEAR BIT(4)463#define MTK_WDMA_XDMA_RX_FIFO_CFG_RX_DMAD_FIFO_CLEAR BIT(8)464#define MTK_WDMA_XDMA_RX_FIFO_CFG_RX_ARR_FIFO_CLEAR BIT(12)465#define MTK_WDMA_XDMA_RX_FIFO_CFG_RX_LEN_FIFO_CLEAR BIT(15)466#define MTK_WDMA_XDMA_RX_FIFO_CFG_RX_WID_FIFO_CLEAR BIT(18)467#define MTK_WDMA_XDMA_RX_FIFO_CFG_RX_BID_FIFO_CLEAR BIT(21)468 469#define MTK_WDMA_INT_GRP1 0x250470#define MTK_WDMA_INT_GRP2 0x254471 472#define MTK_WDMA_PREF_TX_CFG 0x2d0473#define MTK_WDMA_PREF_TX_CFG_PREF_EN BIT(0)474#define MTK_WDMA_PREF_TX_CFG_PREF_BUSY BIT(1)475 476#define MTK_WDMA_PREF_RX_CFG 0x2dc477#define MTK_WDMA_PREF_RX_CFG_PREF_EN BIT(0)478#define MTK_WDMA_PREF_RX_CFG_PREF_BUSY BIT(1)479 480#define MTK_WDMA_PREF_RX_FIFO_CFG 0x2e0481#define MTK_WDMA_PREF_RX_FIFO_CFG_RING0_CLEAR BIT(0)482#define MTK_WDMA_PREF_RX_FIFO_CFG_RING1_CLEAR BIT(16)483 484#define MTK_WDMA_PREF_TX_FIFO_CFG 0x2d4485#define MTK_WDMA_PREF_TX_FIFO_CFG_RING0_CLEAR BIT(0)486#define MTK_WDMA_PREF_TX_FIFO_CFG_RING1_CLEAR BIT(16)487 488#define MTK_WDMA_PREF_SIDX_CFG 0x2e4489#define MTK_WDMA_PREF_SIDX_CFG_TX_RING_CLEAR GENMASK(3, 0)490#define MTK_WDMA_PREF_SIDX_CFG_RX_RING_CLEAR GENMASK(5, 4)491 492#define MTK_WDMA_WRBK_TX_CFG 0x300493#define MTK_WDMA_WRBK_TX_CFG_WRBK_BUSY BIT(0)494#define MTK_WDMA_WRBK_TX_CFG_WRBK_EN BIT(30)495 496#define MTK_WDMA_WRBK_TX_FIFO_CFG(_n) (0x304 + (_n) * 0x4)497#define MTK_WDMA_WRBK_TX_FIFO_CFG_RING_CLEAR BIT(0)498 499#define MTK_WDMA_WRBK_RX_CFG 0x344500#define MTK_WDMA_WRBK_RX_CFG_WRBK_BUSY BIT(0)501#define MTK_WDMA_WRBK_RX_CFG_WRBK_EN BIT(30)502 503#define MTK_WDMA_WRBK_RX_FIFO_CFG(_n) (0x348 + (_n) * 0x4)504#define MTK_WDMA_WRBK_RX_FIFO_CFG_RING_CLEAR BIT(0)505 506#define MTK_WDMA_WRBK_SIDX_CFG 0x388507#define MTK_WDMA_WRBK_SIDX_CFG_TX_RING_CLEAR GENMASK(3, 0)508#define MTK_WDMA_WRBK_SIDX_CFG_RX_RING_CLEAR GENMASK(5, 4)509 510#define MTK_PCIE_MIRROR_MAP(n) ((n) ? 0x4 : 0x0)511#define MTK_PCIE_MIRROR_MAP_EN BIT(0)512#define MTK_PCIE_MIRROR_MAP_WED_ID BIT(1)513 514/* DMA channel mapping */515#define HIFSYS_DMA_AG_MAP 0x008516 517#define MTK_WED_RTQM_GLO_CFG 0xb00518#define MTK_WED_RTQM_BUSY BIT(1)519#define MTK_WED_RTQM_Q_RST BIT(2)520#define MTK_WED_RTQM_Q_DBG_BYPASS BIT(5)521#define MTK_WED_RTQM_TXDMAD_FPORT GENMASK(23, 20)522 523#define MTK_WED_RTQM_RST 0xb04524 525#define MTK_WED_RTQM_IGRS0_I2HW_DMAD_CNT 0xb1c526#define MTK_WED_RTQM_IGRS0_I2H_DMAD_CNT(_n) (0xb20 + (_n) * 0x4)527#define MTK_WED_RTQM_IGRS0_I2HW_PKT_CNT 0xb28528#define MTK_WED_RTQM_IGRS0_I2H_PKT_CNT(_n) (0xb2c + (_n) * 0x4)529#define MTK_WED_RTQM_IGRS0_FDROP_CNT 0xb34530 531#define MTK_WED_RTQM_IGRS1_I2HW_DMAD_CNT 0xb44532#define MTK_WED_RTQM_IGRS1_I2H_DMAD_CNT(_n) (0xb48 + (_n) * 0x4)533#define MTK_WED_RTQM_IGRS1_I2HW_PKT_CNT 0xb50534#define MTK_WED_RTQM_IGRS1_I2H_PKT_CNT(_n) (0xb54 + (_n) * 0x4)535#define MTK_WED_RTQM_IGRS1_FDROP_CNT 0xb5c536 537#define MTK_WED_RTQM_IGRS2_I2HW_DMAD_CNT 0xb6c538#define MTK_WED_RTQM_IGRS2_I2H_DMAD_CNT(_n) (0xb70 + (_n) * 0x4)539#define MTK_WED_RTQM_IGRS2_I2HW_PKT_CNT 0xb78540#define MTK_WED_RTQM_IGRS2_I2H_PKT_CNT(_n) (0xb7c + (_n) * 0x4)541#define MTK_WED_RTQM_IGRS2_FDROP_CNT 0xb84542 543#define MTK_WED_RTQM_IGRS3_I2HW_DMAD_CNT 0xb94544#define MTK_WED_RTQM_IGRS3_I2H_DMAD_CNT(_n) (0xb98 + (_n) * 0x4)545#define MTK_WED_RTQM_IGRS3_I2HW_PKT_CNT 0xba0546#define MTK_WED_RTQM_IGRS3_I2H_PKT_CNT(_n) (0xba4 + (_n) * 0x4)547#define MTK_WED_RTQM_IGRS3_FDROP_CNT 0xbac548 549#define MTK_WED_RTQM_R2H_MIB(_n) (0xb70 + (_n) * 0x4)550#define MTK_WED_RTQM_R2Q_MIB(_n) (0xb78 + (_n) * 0x4)551#define MTK_WED_RTQM_Q2N_MIB 0xb80552#define MTK_WED_RTQM_Q2H_MIB(_n) (0xb84 + (_n) * 0x4)553 554#define MTK_WED_RTQM_Q2B_MIB 0xb8c555#define MTK_WED_RTQM_PFDBK_MIB 0xb90556 557#define MTK_WED_RTQM_ENQ_CFG0 0xbb8558#define MTK_WED_RTQM_ENQ_CFG_TXDMAD_FPORT GENMASK(15, 12)559 560#define MTK_WED_RTQM_FDROP_MIB 0xb84561#define MTK_WED_RTQM_ENQ_I2Q_DMAD_CNT 0xbbc562#define MTK_WED_RTQM_ENQ_I2N_DMAD_CNT 0xbc0563#define MTK_WED_RTQM_ENQ_I2Q_PKT_CNT 0xbc4564#define MTK_WED_RTQM_ENQ_I2N_PKT_CNT 0xbc8565#define MTK_WED_RTQM_ENQ_USED_ENTRY_CNT 0xbcc566#define MTK_WED_RTQM_ENQ_ERR_CNT 0xbd0567 568#define MTK_WED_RTQM_DEQ_DMAD_CNT 0xbd8569#define MTK_WED_RTQM_DEQ_Q2I_DMAD_CNT 0xbdc570#define MTK_WED_RTQM_DEQ_PKT_CNT 0xbe0571#define MTK_WED_RTQM_DEQ_Q2I_PKT_CNT 0xbe4572#define MTK_WED_RTQM_DEQ_USED_PFDBK_CNT 0xbe8573#define MTK_WED_RTQM_DEQ_ERR_CNT 0xbec574 575#define MTK_WED_RROQM_GLO_CFG 0xc04576#define MTK_WED_RROQM_RST_IDX 0xc08577#define MTK_WED_RROQM_RST_IDX_MIOD BIT(0)578#define MTK_WED_RROQM_RST_IDX_FDBK BIT(4)579 580#define MTK_WED_RROQM_MIOD_CTRL0 0xc40581#define MTK_WED_RROQM_MIOD_CTRL1 0xc44582#define MTK_WED_RROQM_MIOD_CNT GENMASK(11, 0)583 584#define MTK_WED_RROQM_MIOD_CTRL2 0xc48585#define MTK_WED_RROQM_MIOD_CTRL3 0xc4c586 587#define MTK_WED_RROQM_FDBK_CTRL0 0xc50588#define MTK_WED_RROQM_FDBK_CTRL1 0xc54589#define MTK_WED_RROQM_FDBK_CNT GENMASK(11, 0)590 591#define MTK_WED_RROQM_FDBK_CTRL2 0xc58592 593#define MTK_WED_RROQ_BASE_L 0xc80594#define MTK_WED_RROQ_BASE_H 0xc84595 596#define MTK_WED_RROQM_MIOD_CFG 0xc8c597#define MTK_WED_RROQM_MIOD_MID_DW GENMASK(5, 0)598#define MTK_WED_RROQM_MIOD_MOD_DW GENMASK(13, 8)599#define MTK_WED_RROQM_MIOD_ENTRY_DW GENMASK(22, 16)600 601#define MTK_WED_RROQM_MID_MIB 0xcc0602#define MTK_WED_RROQM_MOD_MIB 0xcc4603#define MTK_WED_RROQM_MOD_COHERENT_MIB 0xcc8604#define MTK_WED_RROQM_FDBK_MIB 0xcd0605#define MTK_WED_RROQM_FDBK_COHERENT_MIB 0xcd4606#define MTK_WED_RROQM_FDBK_IND_MIB 0xce0607#define MTK_WED_RROQM_FDBK_ENQ_MIB 0xce4608#define MTK_WED_RROQM_FDBK_ANC_MIB 0xce8609#define MTK_WED_RROQM_FDBK_ANC2H_MIB 0xcec610 611#define MTK_WED_RX_BM_RX_DMAD 0xd80612#define MTK_WED_RX_BM_BASE 0xd84613#define MTK_WED_RX_BM_INIT_PTR 0xd88614#define MTK_WED_RX_BM_PTR 0xd8c615#define MTK_WED_RX_BM_PTR_HEAD GENMASK(32, 16)616#define MTK_WED_RX_BM_PTR_TAIL GENMASK(15, 0)617 618#define MTK_WED_RX_BM_BLEN 0xd90619#define MTK_WED_RX_BM_STS 0xd94620#define MTK_WED_RX_BM_INTF2 0xd98621#define MTK_WED_RX_BM_INTF 0xd9c622#define MTK_WED_RX_BM_ERR_STS 0xda8623 624#define MTK_RRO_IND_CMD_SIGNATURE 0xe00625#define MTK_RRO_IND_CMD_DMA_IDX GENMASK(11, 0)626#define MTK_RRO_IND_CMD_MAGIC_CNT GENMASK(30, 28)627 628#define MTK_WED_IND_CMD_RX_CTRL0 0xe04629#define MTK_WED_IND_CMD_PROC_IDX GENMASK(11, 0)630#define MTK_WED_IND_CMD_PREFETCH_FREE_CNT GENMASK(19, 16)631#define MTK_WED_IND_CMD_MAGIC_CNT GENMASK(30, 28)632 633#define MTK_WED_IND_CMD_RX_CTRL1 0xe08634#define MTK_WED_IND_CMD_RX_CTRL2 0xe0c635#define MTK_WED_IND_CMD_MAX_CNT GENMASK(11, 0)636#define MTK_WED_IND_CMD_BASE_M GENMASK(19, 16)637 638#define MTK_WED_RRO_CFG0 0xe10639#define MTK_WED_RRO_CFG1 0xe14640#define MTK_WED_RRO_CFG1_MAX_WIN_SZ GENMASK(31, 29)641#define MTK_WED_RRO_CFG1_ACK_SN_BASE_M GENMASK(19, 16)642#define MTK_WED_RRO_CFG1_PARTICL_SE_ID GENMASK(11, 0)643 644#define MTK_WED_ADDR_ELEM_CFG0 0xe18645#define MTK_WED_ADDR_ELEM_CFG1 0xe1c646#define MTK_WED_ADDR_ELEM_PREFETCH_FREE_CNT GENMASK(19, 16)647 648#define MTK_WED_ADDR_ELEM_TBL_CFG 0xe20649#define MTK_WED_ADDR_ELEM_TBL_OFFSET GENMASK(6, 0)650#define MTK_WED_ADDR_ELEM_TBL_RD_RDY BIT(28)651#define MTK_WED_ADDR_ELEM_TBL_WR_RDY BIT(29)652#define MTK_WED_ADDR_ELEM_TBL_RD BIT(30)653#define MTK_WED_ADDR_ELEM_TBL_WR BIT(31)654 655#define MTK_WED_RADDR_ELEM_TBL_WDATA 0xe24656#define MTK_WED_RADDR_ELEM_TBL_RDATA 0xe28657 658#define MTK_WED_PN_CHECK_CFG 0xe30659#define MTK_WED_PN_CHECK_SE_ID GENMASK(11, 0)660#define MTK_WED_PN_CHECK_RD_RDY BIT(28)661#define MTK_WED_PN_CHECK_WR_RDY BIT(29)662#define MTK_WED_PN_CHECK_RD BIT(30)663#define MTK_WED_PN_CHECK_WR BIT(31)664 665#define MTK_WED_PN_CHECK_WDATA_M 0xe38666#define MTK_WED_PN_CHECK_IS_FIRST BIT(17)667 668#define MTK_WED_RRO_MSDU_PG_RING_CFG(_n) (0xe44 + (_n) * 0x8)669 670#define MTK_WED_RRO_MSDU_PG_RING2_CFG 0xe58671#define MTK_WED_RRO_MSDU_PG_DRV_CLR BIT(26)672#define MTK_WED_RRO_MSDU_PG_DRV_EN BIT(31)673 674#define MTK_WED_RRO_MSDU_PG_CTRL0(_n) (0xe5c + (_n) * 0xc)675#define MTK_WED_RRO_MSDU_PG_CTRL1(_n) (0xe60 + (_n) * 0xc)676#define MTK_WED_RRO_MSDU_PG_CTRL2(_n) (0xe64 + (_n) * 0xc)677 678#define MTK_WED_RRO_RX_D_RX(_n) (0xe80 + (_n) * 0x10)679 680#define MTK_WED_RRO_RX_MAGIC_CNT BIT(13)681 682#define MTK_WED_RRO_RX_D_CFG(_n) (0xea0 + (_n) * 0x4)683#define MTK_WED_RRO_RX_D_DRV_CLR BIT(26)684#define MTK_WED_RRO_RX_D_DRV_EN BIT(31)685 686#define MTK_WED_RRO_PG_BM_RX_DMAM 0xeb0687#define MTK_WED_RRO_PG_BM_RX_SDL0 GENMASK(13, 0)688 689#define MTK_WED_RRO_PG_BM_BASE 0xeb4690#define MTK_WED_RRO_PG_BM_INIT_PTR 0xeb8691#define MTK_WED_RRO_PG_BM_SW_TAIL_IDX GENMASK(15, 0)692#define MTK_WED_RRO_PG_BM_INIT_SW_TAIL_IDX BIT(16)693 694#define MTK_WED_WPDMA_INT_CTRL_RRO_RX 0xeec695#define MTK_WED_WPDMA_INT_CTRL_RRO_RX0_EN BIT(0)696#define MTK_WED_WPDMA_INT_CTRL_RRO_RX0_CLR BIT(1)697#define MTK_WED_WPDMA_INT_CTRL_RRO_RX0_DONE_TRIG GENMASK(6, 2)698#define MTK_WED_WPDMA_INT_CTRL_RRO_RX1_EN BIT(8)699#define MTK_WED_WPDMA_INT_CTRL_RRO_RX1_CLR BIT(9)700#define MTK_WED_WPDMA_INT_CTRL_RRO_RX1_DONE_TRIG GENMASK(14, 10)701 702#define MTK_WED_WPDMA_INT_CTRL_RRO_MSDU_PG 0xef4703#define MTK_WED_WPDMA_INT_CTRL_RRO_PG0_EN BIT(0)704#define MTK_WED_WPDMA_INT_CTRL_RRO_PG0_CLR BIT(1)705#define MTK_WED_WPDMA_INT_CTRL_RRO_PG0_DONE_TRIG GENMASK(6, 2)706#define MTK_WED_WPDMA_INT_CTRL_RRO_PG1_EN BIT(8)707#define MTK_WED_WPDMA_INT_CTRL_RRO_PG1_CLR BIT(9)708#define MTK_WED_WPDMA_INT_CTRL_RRO_PG1_DONE_TRIG GENMASK(14, 10)709#define MTK_WED_WPDMA_INT_CTRL_RRO_PG2_EN BIT(16)710#define MTK_WED_WPDMA_INT_CTRL_RRO_PG2_CLR BIT(17)711#define MTK_WED_WPDMA_INT_CTRL_RRO_PG2_DONE_TRIG GENMASK(22, 18)712 713#define MTK_WED_RRO_RX_HW_STS 0xf00714#define MTK_WED_RX_IND_CMD_BUSY GENMASK(31, 0)715 716#define MTK_WED_RX_IND_CMD_CNT0 0xf20717#define MTK_WED_RX_IND_CMD_DBG_CNT_EN BIT(31)718 719#define MTK_WED_RX_IND_CMD_CNT(_n) (0xf20 + (_n) * 0x4)720#define MTK_WED_IND_CMD_MAGIC_CNT_FAIL_CNT GENMASK(15, 0)721 722#define MTK_WED_RX_ADDR_ELEM_CNT(_n) (0xf48 + (_n) * 0x4)723#define MTK_WED_ADDR_ELEM_SIG_FAIL_CNT GENMASK(15, 0)724#define MTK_WED_ADDR_ELEM_FIRST_SIG_FAIL_CNT GENMASK(31, 16)725#define MTK_WED_ADDR_ELEM_ACKSN_CNT GENMASK(27, 0)726 727#define MTK_WED_RX_MSDU_PG_CNT(_n) (0xf5c + (_n) * 0x4)728 729#define MTK_WED_RX_PN_CHK_CNT 0xf70730#define MTK_WED_PN_CHK_FAIL_CNT GENMASK(15, 0)731 732#define MTK_WED_WOCPU_VIEW_MIOD_BASE 0x8000733#define MTK_WED_PCIE_INT_MASK 0x0734 735#define MTK_WED_AMSDU_FIFO 0x1800736#define MTK_WED_AMSDU_IS_PRIOR0_RING BIT(10)737 738#define MTK_WED_AMSDU_STA_INFO 0x01810739#define MTK_WED_AMSDU_STA_INFO_DO_INIT BIT(0)740#define MTK_WED_AMSDU_STA_INFO_SET_INIT BIT(1)741 742#define MTK_WED_AMSDU_STA_INFO_INIT 0x01814743#define MTK_WED_AMSDU_STA_WTBL_HDRT_MODE BIT(0)744#define MTK_WED_AMSDU_STA_RMVL BIT(1)745#define MTK_WED_AMSDU_STA_MAX_AMSDU_LEN GENMASK(7, 2)746#define MTK_WED_AMSDU_STA_MAX_AMSDU_NUM GENMASK(11, 8)747 748#define MTK_WED_AMSDU_HIFTXD_BASE_L(_n) (0x1980 + (_n) * 0x4)749 750#define MTK_WED_AMSDU_PSE 0x1910751#define MTK_WED_AMSDU_PSE_RESET BIT(16)752 753#define MTK_WED_AMSDU_HIFTXD_CFG 0x1968754#define MTK_WED_AMSDU_HIFTXD_SRC GENMASK(16, 15)755 756#define MTK_WED_MON_AMSDU_FIFO_DMAD 0x1a34757 758#define MTK_WED_MON_AMSDU_ENG_DMAD(_n) (0x1a80 + (_n) * 0x50)759#define MTK_WED_MON_AMSDU_ENG_QFPL(_n) (0x1a84 + (_n) * 0x50)760#define MTK_WED_MON_AMSDU_ENG_QENI(_n) (0x1a88 + (_n) * 0x50)761#define MTK_WED_MON_AMSDU_ENG_QENO(_n) (0x1a8c + (_n) * 0x50)762#define MTK_WED_MON_AMSDU_ENG_MERG(_n) (0x1a90 + (_n) * 0x50)763 764#define MTK_WED_MON_AMSDU_ENG_CNT8(_n) (0x1a94 + (_n) * 0x50)765#define MTK_WED_AMSDU_ENG_MAX_QGPP_CNT GENMASK(10, 0)766#define MTK_WED_AMSDU_ENG_MAX_PL_CNT GENMASK(27, 16)767 768#define MTK_WED_MON_AMSDU_ENG_CNT9(_n) (0x1a98 + (_n) * 0x50)769#define MTK_WED_AMSDU_ENG_CUR_ENTRY GENMASK(10, 0)770#define MTK_WED_AMSDU_ENG_MAX_BUF_MERGED GENMASK(20, 16)771#define MTK_WED_AMSDU_ENG_MAX_MSDU_MERGED GENMASK(28, 24)772 773#define MTK_WED_MON_AMSDU_QMEM_STS1 0x1e04774 775#define MTK_WED_MON_AMSDU_QMEM_CNT(_n) (0x1e0c + (_n) * 0x4)776#define MTK_WED_AMSDU_QMEM_FQ_CNT GENMASK(27, 16)777#define MTK_WED_AMSDU_QMEM_SP_QCNT GENMASK(11, 0)778#define MTK_WED_AMSDU_QMEM_TID0_QCNT GENMASK(27, 16)779#define MTK_WED_AMSDU_QMEM_TID1_QCNT GENMASK(11, 0)780#define MTK_WED_AMSDU_QMEM_TID2_QCNT GENMASK(27, 16)781#define MTK_WED_AMSDU_QMEM_TID3_QCNT GENMASK(11, 0)782#define MTK_WED_AMSDU_QMEM_TID4_QCNT GENMASK(27, 16)783#define MTK_WED_AMSDU_QMEM_TID5_QCNT GENMASK(11, 0)784#define MTK_WED_AMSDU_QMEM_TID6_QCNT GENMASK(27, 16)785#define MTK_WED_AMSDU_QMEM_TID7_QCNT GENMASK(11, 0)786 787#define MTK_WED_MON_AMSDU_QMEM_PTR(_n) (0x1e20 + (_n) * 0x4)788#define MTK_WED_AMSDU_QMEM_FQ_HEAD GENMASK(27, 16)789#define MTK_WED_AMSDU_QMEM_SP_QHEAD GENMASK(11, 0)790#define MTK_WED_AMSDU_QMEM_TID0_QHEAD GENMASK(27, 16)791#define MTK_WED_AMSDU_QMEM_TID1_QHEAD GENMASK(11, 0)792#define MTK_WED_AMSDU_QMEM_TID2_QHEAD GENMASK(27, 16)793#define MTK_WED_AMSDU_QMEM_TID3_QHEAD GENMASK(11, 0)794#define MTK_WED_AMSDU_QMEM_TID4_QHEAD GENMASK(27, 16)795#define MTK_WED_AMSDU_QMEM_TID5_QHEAD GENMASK(11, 0)796#define MTK_WED_AMSDU_QMEM_TID6_QHEAD GENMASK(27, 16)797#define MTK_WED_AMSDU_QMEM_TID7_QHEAD GENMASK(11, 0)798#define MTK_WED_AMSDU_QMEM_FQ_TAIL GENMASK(27, 16)799#define MTK_WED_AMSDU_QMEM_SP_QTAIL GENMASK(11, 0)800#define MTK_WED_AMSDU_QMEM_TID0_QTAIL GENMASK(27, 16)801#define MTK_WED_AMSDU_QMEM_TID1_QTAIL GENMASK(11, 0)802#define MTK_WED_AMSDU_QMEM_TID2_QTAIL GENMASK(27, 16)803#define MTK_WED_AMSDU_QMEM_TID3_QTAIL GENMASK(11, 0)804#define MTK_WED_AMSDU_QMEM_TID4_QTAIL GENMASK(27, 16)805#define MTK_WED_AMSDU_QMEM_TID5_QTAIL GENMASK(11, 0)806#define MTK_WED_AMSDU_QMEM_TID6_QTAIL GENMASK(27, 16)807#define MTK_WED_AMSDU_QMEM_TID7_QTAIL GENMASK(11, 0)808 809#define MTK_WED_MON_AMSDU_HIFTXD_FETCH_MSDU(_n) (0x1ec4 + (_n) * 0x4)810 811#define MTK_WED_PCIE_BASE 0x11280000812#define MTK_WED_PCIE_BASE0 0x11300000813#define MTK_WED_PCIE_BASE1 0x11310000814#define MTK_WED_PCIE_BASE2 0x11290000815#endif816