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1/*2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved.3 *4 * This software is available to you under a choice of one of two5 * licenses. You may choose to be licensed under the terms of the GNU6 * General Public License (GPL) Version 2, available from the file7 * COPYING in the main directory of this source tree, or the8 * OpenIB.org BSD license below:9 *10 * Redistribution and use in source and binary forms, with or11 * without modification, are permitted provided that the following12 * conditions are met:13 *14 * - Redistributions of source code must retain the above15 * copyright notice, this list of conditions and the following16 * disclaimer.17 *18 * - Redistributions in binary form must reproduce the above19 * copyright notice, this list of conditions and the following20 * disclaimer in the documentation and/or other materials21 * provided with the distribution.22 *23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE30 * SOFTWARE.31 *32 */33 34#include <linux/bpf.h>35#include <linux/bpf_trace.h>36#include <linux/mlx4/cq.h>37#include <linux/slab.h>38#include <linux/mlx4/qp.h>39#include <linux/skbuff.h>40#include <linux/rculist.h>41#include <linux/if_ether.h>42#include <linux/if_vlan.h>43#include <linux/vmalloc.h>44#include <linux/irq.h>45#include <linux/skbuff_ref.h>46 47#include <net/ip.h>48#if IS_ENABLED(CONFIG_IPV6)49#include <net/ip6_checksum.h>50#endif51 52#include "mlx4_en.h"53 54static int mlx4_alloc_page(struct mlx4_en_priv *priv,55 struct mlx4_en_rx_alloc *frag,56 gfp_t gfp)57{58 struct page *page;59 dma_addr_t dma;60 61 page = alloc_page(gfp);62 if (unlikely(!page))63 return -ENOMEM;64 dma = dma_map_page(priv->ddev, page, 0, PAGE_SIZE, priv->dma_dir);65 if (unlikely(dma_mapping_error(priv->ddev, dma))) {66 __free_page(page);67 return -ENOMEM;68 }69 frag->page = page;70 frag->dma = dma;71 frag->page_offset = priv->rx_headroom;72 return 0;73}74 75static int mlx4_en_alloc_frags(struct mlx4_en_priv *priv,76 struct mlx4_en_rx_ring *ring,77 struct mlx4_en_rx_desc *rx_desc,78 struct mlx4_en_rx_alloc *frags,79 gfp_t gfp)80{81 int i;82 83 for (i = 0; i < priv->num_frags; i++, frags++) {84 if (!frags->page) {85 if (mlx4_alloc_page(priv, frags, gfp)) {86 ring->alloc_fail++;87 return -ENOMEM;88 }89 ring->rx_alloc_pages++;90 }91 rx_desc->data[i].addr = cpu_to_be64(frags->dma +92 frags->page_offset);93 }94 return 0;95}96 97static void mlx4_en_free_frag(const struct mlx4_en_priv *priv,98 struct mlx4_en_rx_alloc *frag)99{100 if (frag->page) {101 dma_unmap_page(priv->ddev, frag->dma,102 PAGE_SIZE, priv->dma_dir);103 __free_page(frag->page);104 }105 /* We need to clear all fields, otherwise a change of priv->log_rx_info106 * could lead to see garbage later in frag->page.107 */108 memset(frag, 0, sizeof(*frag));109}110 111static void mlx4_en_init_rx_desc(const struct mlx4_en_priv *priv,112 struct mlx4_en_rx_ring *ring, int index)113{114 struct mlx4_en_rx_desc *rx_desc = ring->buf + ring->stride * index;115 int possible_frags;116 int i;117 118 /* Set size and memtype fields */119 for (i = 0; i < priv->num_frags; i++) {120 rx_desc->data[i].byte_count =121 cpu_to_be32(priv->frag_info[i].frag_size);122 rx_desc->data[i].lkey = cpu_to_be32(priv->mdev->mr.key);123 }124 125 /* If the number of used fragments does not fill up the ring stride,126 * remaining (unused) fragments must be padded with null address/size127 * and a special memory key */128 possible_frags = (ring->stride - sizeof(struct mlx4_en_rx_desc)) / DS_SIZE;129 for (i = priv->num_frags; i < possible_frags; i++) {130 rx_desc->data[i].byte_count = 0;131 rx_desc->data[i].lkey = cpu_to_be32(MLX4_EN_MEMTYPE_PAD);132 rx_desc->data[i].addr = 0;133 }134}135 136static int mlx4_en_prepare_rx_desc(struct mlx4_en_priv *priv,137 struct mlx4_en_rx_ring *ring, int index,138 gfp_t gfp)139{140 struct mlx4_en_rx_desc *rx_desc = ring->buf +141 (index << ring->log_stride);142 struct mlx4_en_rx_alloc *frags = ring->rx_info +143 (index << priv->log_rx_info);144 if (likely(ring->page_cache.index > 0)) {145 /* XDP uses a single page per frame */146 if (!frags->page) {147 ring->page_cache.index--;148 frags->page = ring->page_cache.buf[ring->page_cache.index].page;149 frags->dma = ring->page_cache.buf[ring->page_cache.index].dma;150 }151 frags->page_offset = XDP_PACKET_HEADROOM;152 rx_desc->data[0].addr = cpu_to_be64(frags->dma +153 XDP_PACKET_HEADROOM);154 return 0;155 }156 157 return mlx4_en_alloc_frags(priv, ring, rx_desc, frags, gfp);158}159 160static bool mlx4_en_is_ring_empty(const struct mlx4_en_rx_ring *ring)161{162 return ring->prod == ring->cons;163}164 165static inline void mlx4_en_update_rx_prod_db(struct mlx4_en_rx_ring *ring)166{167 *ring->wqres.db.db = cpu_to_be32(ring->prod & 0xffff);168}169 170/* slow path */171static void mlx4_en_free_rx_desc(const struct mlx4_en_priv *priv,172 struct mlx4_en_rx_ring *ring,173 int index)174{175 struct mlx4_en_rx_alloc *frags;176 int nr;177 178 frags = ring->rx_info + (index << priv->log_rx_info);179 for (nr = 0; nr < priv->num_frags; nr++) {180 en_dbg(DRV, priv, "Freeing fragment:%d\n", nr);181 mlx4_en_free_frag(priv, frags + nr);182 }183}184 185/* Function not in fast-path */186static int mlx4_en_fill_rx_buffers(struct mlx4_en_priv *priv)187{188 struct mlx4_en_rx_ring *ring;189 int ring_ind;190 int buf_ind;191 int new_size;192 193 for (buf_ind = 0; buf_ind < priv->prof->rx_ring_size; buf_ind++) {194 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {195 ring = priv->rx_ring[ring_ind];196 197 if (mlx4_en_prepare_rx_desc(priv, ring,198 ring->actual_size,199 GFP_KERNEL)) {200 if (ring->actual_size < MLX4_EN_MIN_RX_SIZE) {201 en_err(priv, "Failed to allocate enough rx buffers\n");202 return -ENOMEM;203 } else {204 new_size = rounddown_pow_of_two(ring->actual_size);205 en_warn(priv, "Only %d buffers allocated reducing ring size to %d\n",206 ring->actual_size, new_size);207 goto reduce_rings;208 }209 }210 ring->actual_size++;211 ring->prod++;212 }213 }214 return 0;215 216reduce_rings:217 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {218 ring = priv->rx_ring[ring_ind];219 while (ring->actual_size > new_size) {220 ring->actual_size--;221 ring->prod--;222 mlx4_en_free_rx_desc(priv, ring, ring->actual_size);223 }224 }225 226 return 0;227}228 229static void mlx4_en_free_rx_buf(struct mlx4_en_priv *priv,230 struct mlx4_en_rx_ring *ring)231{232 int index;233 234 en_dbg(DRV, priv, "Freeing Rx buf - cons:%d prod:%d\n",235 ring->cons, ring->prod);236 237 /* Unmap and free Rx buffers */238 for (index = 0; index < ring->size; index++) {239 en_dbg(DRV, priv, "Processing descriptor:%d\n", index);240 mlx4_en_free_rx_desc(priv, ring, index);241 }242 ring->cons = 0;243 ring->prod = 0;244}245 246void mlx4_en_set_num_rx_rings(struct mlx4_en_dev *mdev)247{248 int i;249 int num_of_eqs;250 int num_rx_rings;251 struct mlx4_dev *dev = mdev->dev;252 253 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_ETH) {254 num_of_eqs = max_t(int, MIN_RX_RINGS,255 min_t(int,256 mlx4_get_eqs_per_port(mdev->dev, i),257 DEF_RX_RINGS));258 259 num_rx_rings = mlx4_low_memory_profile() ? MIN_RX_RINGS :260 min_t(int, num_of_eqs, num_online_cpus());261 mdev->profile.prof[i].rx_ring_num =262 rounddown_pow_of_two(num_rx_rings);263 }264}265 266int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv,267 struct mlx4_en_rx_ring **pring,268 u32 size, u16 stride, int node, int queue_index)269{270 struct mlx4_en_dev *mdev = priv->mdev;271 struct mlx4_en_rx_ring *ring;272 int err = -ENOMEM;273 int tmp;274 275 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, node);276 if (!ring) {277 en_err(priv, "Failed to allocate RX ring structure\n");278 return -ENOMEM;279 }280 281 ring->prod = 0;282 ring->cons = 0;283 ring->size = size;284 ring->size_mask = size - 1;285 ring->stride = stride;286 ring->log_stride = ffs(ring->stride) - 1;287 ring->buf_size = ring->size * ring->stride + TXBB_SIZE;288 289 if (xdp_rxq_info_reg(&ring->xdp_rxq, priv->dev, queue_index, 0) < 0)290 goto err_ring;291 292 tmp = size * roundup_pow_of_two(MLX4_EN_MAX_RX_FRAGS *293 sizeof(struct mlx4_en_rx_alloc));294 ring->rx_info = kvzalloc_node(tmp, GFP_KERNEL, node);295 if (!ring->rx_info) {296 err = -ENOMEM;297 goto err_xdp_info;298 }299 300 en_dbg(DRV, priv, "Allocated rx_info ring at addr:%p size:%d\n",301 ring->rx_info, tmp);302 303 /* Allocate HW buffers on provided NUMA node */304 set_dev_node(&mdev->dev->persist->pdev->dev, node);305 err = mlx4_alloc_hwq_res(mdev->dev, &ring->wqres, ring->buf_size);306 set_dev_node(&mdev->dev->persist->pdev->dev, mdev->dev->numa_node);307 if (err)308 goto err_info;309 310 ring->buf = ring->wqres.buf.direct.buf;311 312 ring->hwtstamp_rx_filter = priv->hwtstamp_config.rx_filter;313 314 *pring = ring;315 return 0;316 317err_info:318 kvfree(ring->rx_info);319 ring->rx_info = NULL;320err_xdp_info:321 xdp_rxq_info_unreg(&ring->xdp_rxq);322err_ring:323 kfree(ring);324 *pring = NULL;325 326 return err;327}328 329int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv)330{331 struct mlx4_en_rx_ring *ring;332 int i;333 int ring_ind;334 int err;335 int stride = roundup_pow_of_two(sizeof(struct mlx4_en_rx_desc) +336 DS_SIZE * priv->num_frags);337 338 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {339 ring = priv->rx_ring[ring_ind];340 341 ring->prod = 0;342 ring->cons = 0;343 ring->actual_size = 0;344 ring->cqn = priv->rx_cq[ring_ind]->mcq.cqn;345 346 ring->stride = stride;347 if (ring->stride <= TXBB_SIZE) {348 /* Stamp first unused send wqe */349 __be32 *ptr = (__be32 *)ring->buf;350 __be32 stamp = cpu_to_be32(1 << STAMP_SHIFT);351 *ptr = stamp;352 /* Move pointer to start of rx section */353 ring->buf += TXBB_SIZE;354 }355 356 ring->log_stride = ffs(ring->stride) - 1;357 ring->buf_size = ring->size * ring->stride;358 359 memset(ring->buf, 0, ring->buf_size);360 mlx4_en_update_rx_prod_db(ring);361 362 /* Initialize all descriptors */363 for (i = 0; i < ring->size; i++)364 mlx4_en_init_rx_desc(priv, ring, i);365 }366 err = mlx4_en_fill_rx_buffers(priv);367 if (err)368 goto err_buffers;369 370 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {371 ring = priv->rx_ring[ring_ind];372 373 ring->size_mask = ring->actual_size - 1;374 mlx4_en_update_rx_prod_db(ring);375 }376 377 return 0;378 379err_buffers:380 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++)381 mlx4_en_free_rx_buf(priv, priv->rx_ring[ring_ind]);382 383 ring_ind = priv->rx_ring_num - 1;384 while (ring_ind >= 0) {385 if (priv->rx_ring[ring_ind]->stride <= TXBB_SIZE)386 priv->rx_ring[ring_ind]->buf -= TXBB_SIZE;387 ring_ind--;388 }389 return err;390}391 392/* We recover from out of memory by scheduling our napi poll393 * function (mlx4_en_process_cq), which tries to allocate394 * all missing RX buffers (call to mlx4_en_refill_rx_buffers).395 */396void mlx4_en_recover_from_oom(struct mlx4_en_priv *priv)397{398 int ring;399 400 if (!priv->port_up)401 return;402 403 for (ring = 0; ring < priv->rx_ring_num; ring++) {404 if (mlx4_en_is_ring_empty(priv->rx_ring[ring])) {405 local_bh_disable();406 napi_schedule(&priv->rx_cq[ring]->napi);407 local_bh_enable();408 }409 }410}411 412/* When the rx ring is running in page-per-packet mode, a released frame can go413 * directly into a small cache, to avoid unmapping or touching the page414 * allocator. In bpf prog performance scenarios, buffers are either forwarded415 * or dropped, never converted to skbs, so every page can come directly from416 * this cache when it is sized to be a multiple of the napi budget.417 */418bool mlx4_en_rx_recycle(struct mlx4_en_rx_ring *ring,419 struct mlx4_en_rx_alloc *frame)420{421 struct mlx4_en_page_cache *cache = &ring->page_cache;422 423 if (cache->index >= MLX4_EN_CACHE_SIZE)424 return false;425 426 cache->buf[cache->index].page = frame->page;427 cache->buf[cache->index].dma = frame->dma;428 cache->index++;429 return true;430}431 432void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv,433 struct mlx4_en_rx_ring **pring,434 u32 size, u16 stride)435{436 struct mlx4_en_dev *mdev = priv->mdev;437 struct mlx4_en_rx_ring *ring = *pring;438 struct bpf_prog *old_prog;439 440 old_prog = rcu_dereference_protected(441 ring->xdp_prog,442 lockdep_is_held(&mdev->state_lock));443 if (old_prog)444 bpf_prog_put(old_prog);445 xdp_rxq_info_unreg(&ring->xdp_rxq);446 mlx4_free_hwq_res(mdev->dev, &ring->wqres, size * stride + TXBB_SIZE);447 kvfree(ring->rx_info);448 ring->rx_info = NULL;449 kfree(ring);450 *pring = NULL;451}452 453void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv,454 struct mlx4_en_rx_ring *ring)455{456 int i;457 458 for (i = 0; i < ring->page_cache.index; i++) {459 dma_unmap_page(priv->ddev, ring->page_cache.buf[i].dma,460 PAGE_SIZE, priv->dma_dir);461 put_page(ring->page_cache.buf[i].page);462 }463 ring->page_cache.index = 0;464 mlx4_en_free_rx_buf(priv, ring);465 if (ring->stride <= TXBB_SIZE)466 ring->buf -= TXBB_SIZE;467}468 469 470static int mlx4_en_complete_rx_desc(struct mlx4_en_priv *priv,471 struct mlx4_en_rx_alloc *frags,472 struct sk_buff *skb,473 int length)474{475 const struct mlx4_en_frag_info *frag_info = priv->frag_info;476 unsigned int truesize = 0;477 bool release = true;478 int nr, frag_size;479 struct page *page;480 dma_addr_t dma;481 482 /* Collect used fragments while replacing them in the HW descriptors */483 for (nr = 0;; frags++) {484 frag_size = min_t(int, length, frag_info->frag_size);485 486 page = frags->page;487 if (unlikely(!page))488 goto fail;489 490 dma = frags->dma;491 dma_sync_single_range_for_cpu(priv->ddev, dma, frags->page_offset,492 frag_size, priv->dma_dir);493 494 __skb_fill_page_desc(skb, nr, page, frags->page_offset,495 frag_size);496 497 truesize += frag_info->frag_stride;498 if (frag_info->frag_stride == PAGE_SIZE / 2) {499 frags->page_offset ^= PAGE_SIZE / 2;500 release = page_count(page) != 1 ||501 page_is_pfmemalloc(page) ||502 page_to_nid(page) != numa_mem_id();503 } else if (!priv->rx_headroom) {504 /* rx_headroom for non XDP setup is always 0.505 * When XDP is set, the above condition will506 * guarantee page is always released.507 */508 u32 sz_align = ALIGN(frag_size, SMP_CACHE_BYTES);509 510 frags->page_offset += sz_align;511 release = frags->page_offset + frag_info->frag_size > PAGE_SIZE;512 }513 if (release) {514 dma_unmap_page(priv->ddev, dma, PAGE_SIZE, priv->dma_dir);515 frags->page = NULL;516 } else {517 page_ref_inc(page);518 }519 520 nr++;521 length -= frag_size;522 if (!length)523 break;524 frag_info++;525 }526 skb->truesize += truesize;527 return nr;528 529fail:530 while (nr > 0) {531 nr--;532 __skb_frag_unref(skb_shinfo(skb)->frags + nr, false);533 }534 return 0;535}536 537static void validate_loopback(struct mlx4_en_priv *priv, void *va)538{539 const unsigned char *data = va + ETH_HLEN;540 int i;541 542 for (i = 0; i < MLX4_LOOPBACK_TEST_PAYLOAD; i++) {543 if (data[i] != (unsigned char)i)544 return;545 }546 /* Loopback found */547 priv->loopback_ok = 1;548}549 550static void mlx4_en_refill_rx_buffers(struct mlx4_en_priv *priv,551 struct mlx4_en_rx_ring *ring)552{553 u32 missing = ring->actual_size - (ring->prod - ring->cons);554 555 /* Try to batch allocations, but not too much. */556 if (missing < 8)557 return;558 do {559 if (mlx4_en_prepare_rx_desc(priv, ring,560 ring->prod & ring->size_mask,561 GFP_ATOMIC | __GFP_MEMALLOC))562 break;563 ring->prod++;564 } while (likely(--missing));565 566 mlx4_en_update_rx_prod_db(ring);567}568 569/* When hardware doesn't strip the vlan, we need to calculate the checksum570 * over it and add it to the hardware's checksum calculation571 */572static inline __wsum get_fixed_vlan_csum(__wsum hw_checksum,573 struct vlan_hdr *vlanh)574{575 return csum_add(hw_checksum, *(__wsum *)vlanh);576}577 578/* Although the stack expects checksum which doesn't include the pseudo579 * header, the HW adds it. To address that, we are subtracting the pseudo580 * header checksum from the checksum value provided by the HW.581 */582static int get_fixed_ipv4_csum(__wsum hw_checksum, struct sk_buff *skb,583 struct iphdr *iph)584{585 __u16 length_for_csum = 0;586 __wsum csum_pseudo_header = 0;587 __u8 ipproto = iph->protocol;588 589 if (unlikely(ipproto == IPPROTO_SCTP))590 return -1;591 592 length_for_csum = (be16_to_cpu(iph->tot_len) - (iph->ihl << 2));593 csum_pseudo_header = csum_tcpudp_nofold(iph->saddr, iph->daddr,594 length_for_csum, ipproto, 0);595 skb->csum = csum_sub(hw_checksum, csum_pseudo_header);596 return 0;597}598 599#if IS_ENABLED(CONFIG_IPV6)600/* In IPv6 packets, hw_checksum lacks 6 bytes from IPv6 header:601 * 4 first bytes : priority, version, flow_lbl602 * and 2 additional bytes : nexthdr, hop_limit.603 */604static int get_fixed_ipv6_csum(__wsum hw_checksum, struct sk_buff *skb,605 struct ipv6hdr *ipv6h)606{607 __u8 nexthdr = ipv6h->nexthdr;608 __wsum temp;609 610 if (unlikely(nexthdr == IPPROTO_FRAGMENT ||611 nexthdr == IPPROTO_HOPOPTS ||612 nexthdr == IPPROTO_SCTP))613 return -1;614 615 /* priority, version, flow_lbl */616 temp = csum_add(hw_checksum, *(__wsum *)ipv6h);617 /* nexthdr and hop_limit */618 skb->csum = csum_add(temp, (__force __wsum)*(__be16 *)&ipv6h->nexthdr);619 return 0;620}621#endif622 623#define short_frame(size) ((size) <= ETH_ZLEN + ETH_FCS_LEN)624 625/* We reach this function only after checking that any of626 * the (IPv4 | IPv6) bits are set in cqe->status.627 */628static int check_csum(struct mlx4_cqe *cqe, struct sk_buff *skb, void *va,629 netdev_features_t dev_features)630{631 __wsum hw_checksum = 0;632 void *hdr;633 634 /* CQE csum doesn't cover padding octets in short ethernet635 * frames. And the pad field is appended prior to calculating636 * and appending the FCS field.637 *638 * Detecting these padded frames requires to verify and parse639 * IP headers, so we simply force all those small frames to skip640 * checksum complete.641 */642 if (short_frame(skb->len))643 return -EINVAL;644 645 hdr = (u8 *)va + sizeof(struct ethhdr);646 hw_checksum = csum_unfold((__force __sum16)cqe->checksum);647 648 if (cqe->vlan_my_qpn & cpu_to_be32(MLX4_CQE_CVLAN_PRESENT_MASK) &&649 !(dev_features & NETIF_F_HW_VLAN_CTAG_RX)) {650 hw_checksum = get_fixed_vlan_csum(hw_checksum, hdr);651 hdr += sizeof(struct vlan_hdr);652 }653 654#if IS_ENABLED(CONFIG_IPV6)655 if (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPV6))656 return get_fixed_ipv6_csum(hw_checksum, skb, hdr);657#endif658 return get_fixed_ipv4_csum(hw_checksum, skb, hdr);659}660 661#if IS_ENABLED(CONFIG_IPV6)662#define MLX4_CQE_STATUS_IP_ANY (MLX4_CQE_STATUS_IPV4 | MLX4_CQE_STATUS_IPV6)663#else664#define MLX4_CQE_STATUS_IP_ANY (MLX4_CQE_STATUS_IPV4)665#endif666 667struct mlx4_en_xdp_buff {668 struct xdp_buff xdp;669 struct mlx4_cqe *cqe;670 struct mlx4_en_dev *mdev;671 struct mlx4_en_rx_ring *ring;672 struct net_device *dev;673};674 675int mlx4_en_xdp_rx_timestamp(const struct xdp_md *ctx, u64 *timestamp)676{677 struct mlx4_en_xdp_buff *_ctx = (void *)ctx;678 679 if (unlikely(_ctx->ring->hwtstamp_rx_filter != HWTSTAMP_FILTER_ALL))680 return -ENODATA;681 682 *timestamp = mlx4_en_get_hwtstamp(_ctx->mdev,683 mlx4_en_get_cqe_ts(_ctx->cqe));684 return 0;685}686 687int mlx4_en_xdp_rx_hash(const struct xdp_md *ctx, u32 *hash,688 enum xdp_rss_hash_type *rss_type)689{690 struct mlx4_en_xdp_buff *_ctx = (void *)ctx;691 struct mlx4_cqe *cqe = _ctx->cqe;692 enum xdp_rss_hash_type xht = 0;693 __be16 status;694 695 if (unlikely(!(_ctx->dev->features & NETIF_F_RXHASH)))696 return -ENODATA;697 698 *hash = be32_to_cpu(cqe->immed_rss_invalid);699 status = cqe->status;700 if (status & cpu_to_be16(MLX4_CQE_STATUS_TCP))701 xht = XDP_RSS_L4_TCP;702 if (status & cpu_to_be16(MLX4_CQE_STATUS_UDP))703 xht = XDP_RSS_L4_UDP;704 if (status & cpu_to_be16(MLX4_CQE_STATUS_IPV4 | MLX4_CQE_STATUS_IPV4F))705 xht |= XDP_RSS_L3_IPV4;706 if (status & cpu_to_be16(MLX4_CQE_STATUS_IPV6)) {707 xht |= XDP_RSS_L3_IPV6;708 if (cqe->ipv6_ext_mask)709 xht |= XDP_RSS_L3_DYNHDR;710 }711 *rss_type = xht;712 713 return 0;714}715 716int mlx4_en_process_rx_cq(struct net_device *dev, struct mlx4_en_cq *cq, int budget)717{718 struct mlx4_en_priv *priv = netdev_priv(dev);719 struct mlx4_en_xdp_buff mxbuf = {};720 int factor = priv->cqe_factor;721 struct mlx4_en_rx_ring *ring;722 struct bpf_prog *xdp_prog;723 int cq_ring = cq->ring;724 bool doorbell_pending;725 bool xdp_redir_flush;726 struct mlx4_cqe *cqe;727 int polled = 0;728 int index;729 730 if (unlikely(!priv->port_up || budget <= 0))731 return 0;732 733 ring = priv->rx_ring[cq_ring];734 735 xdp_prog = rcu_dereference_bh(ring->xdp_prog);736 xdp_init_buff(&mxbuf.xdp, priv->frag_info[0].frag_stride, &ring->xdp_rxq);737 doorbell_pending = false;738 xdp_redir_flush = false;739 740 /* We assume a 1:1 mapping between CQEs and Rx descriptors, so Rx741 * descriptor offset can be deduced from the CQE index instead of742 * reading 'cqe->index' */743 index = cq->mcq.cons_index & ring->size_mask;744 cqe = mlx4_en_get_cqe(cq->buf, index, priv->cqe_size) + factor;745 746 /* Process all completed CQEs */747 while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK,748 cq->mcq.cons_index & cq->size)) {749 struct mlx4_en_rx_alloc *frags;750 enum pkt_hash_types hash_type;751 struct sk_buff *skb;752 unsigned int length;753 int ip_summed;754 void *va;755 int nr;756 757 frags = ring->rx_info + (index << priv->log_rx_info);758 va = page_address(frags[0].page) + frags[0].page_offset;759 net_prefetchw(va);760 /*761 * make sure we read the CQE after we read the ownership bit762 */763 dma_rmb();764 765 /* Drop packet on bad receive or bad checksum */766 if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) ==767 MLX4_CQE_OPCODE_ERROR)) {768 en_err(priv, "CQE completed in error - vendor syndrome:%d syndrome:%d\n",769 ((struct mlx4_err_cqe *)cqe)->vendor_err_syndrome,770 ((struct mlx4_err_cqe *)cqe)->syndrome);771 goto next;772 }773 if (unlikely(cqe->badfcs_enc & MLX4_CQE_BAD_FCS)) {774 en_dbg(RX_ERR, priv, "Accepted frame with bad FCS\n");775 goto next;776 }777 778 /* Check if we need to drop the packet if SRIOV is not enabled779 * and not performing the selftest or flb disabled780 */781 if (priv->flags & MLX4_EN_FLAG_RX_FILTER_NEEDED) {782 const struct ethhdr *ethh = va;783 dma_addr_t dma;784 /* Get pointer to first fragment since we haven't785 * skb yet and cast it to ethhdr struct786 */787 dma = frags[0].dma + frags[0].page_offset;788 dma_sync_single_for_cpu(priv->ddev, dma, sizeof(*ethh),789 DMA_FROM_DEVICE);790 791 if (is_multicast_ether_addr(ethh->h_dest)) {792 struct mlx4_mac_entry *entry;793 struct hlist_head *bucket;794 unsigned int mac_hash;795 796 /* Drop the packet, since HW loopback-ed it */797 mac_hash = ethh->h_source[MLX4_EN_MAC_HASH_IDX];798 bucket = &priv->mac_hash[mac_hash];799 hlist_for_each_entry_rcu_bh(entry, bucket, hlist) {800 if (ether_addr_equal_64bits(entry->mac,801 ethh->h_source))802 goto next;803 }804 }805 }806 807 if (unlikely(priv->validate_loopback)) {808 validate_loopback(priv, va);809 goto next;810 }811 812 /*813 * Packet is OK - process it.814 */815 length = be32_to_cpu(cqe->byte_cnt);816 length -= ring->fcs_del;817 818 /* A bpf program gets first chance to drop the packet. It may819 * read bytes but not past the end of the frag.820 */821 if (xdp_prog) {822 dma_addr_t dma;823 void *orig_data;824 u32 act;825 826 dma = frags[0].dma + frags[0].page_offset;827 dma_sync_single_for_cpu(priv->ddev, dma,828 priv->frag_info[0].frag_size,829 DMA_FROM_DEVICE);830 831 xdp_prepare_buff(&mxbuf.xdp, va - frags[0].page_offset,832 frags[0].page_offset, length, true);833 orig_data = mxbuf.xdp.data;834 mxbuf.cqe = cqe;835 mxbuf.mdev = priv->mdev;836 mxbuf.ring = ring;837 mxbuf.dev = dev;838 839 act = bpf_prog_run_xdp(xdp_prog, &mxbuf.xdp);840 841 length = mxbuf.xdp.data_end - mxbuf.xdp.data;842 if (mxbuf.xdp.data != orig_data) {843 frags[0].page_offset = mxbuf.xdp.data -844 mxbuf.xdp.data_hard_start;845 va = mxbuf.xdp.data;846 }847 848 switch (act) {849 case XDP_PASS:850 break;851 case XDP_REDIRECT:852 if (likely(!xdp_do_redirect(dev, &mxbuf.xdp, xdp_prog))) {853 ring->xdp_redirect++;854 xdp_redir_flush = true;855 frags[0].page = NULL;856 goto next;857 }858 ring->xdp_redirect_fail++;859 trace_xdp_exception(dev, xdp_prog, act);860 goto xdp_drop_no_cnt;861 case XDP_TX:862 if (likely(!mlx4_en_xmit_frame(ring, frags, priv,863 length, cq_ring,864 &doorbell_pending))) {865 frags[0].page = NULL;866 goto next;867 }868 trace_xdp_exception(dev, xdp_prog, act);869 goto xdp_drop_no_cnt; /* Drop on xmit failure */870 default:871 bpf_warn_invalid_xdp_action(dev, xdp_prog, act);872 fallthrough;873 case XDP_ABORTED:874 trace_xdp_exception(dev, xdp_prog, act);875 fallthrough;876 case XDP_DROP:877 ring->xdp_drop++;878xdp_drop_no_cnt:879 goto next;880 }881 }882 883 ring->bytes += length;884 ring->packets++;885 886 skb = napi_get_frags(&cq->napi);887 if (unlikely(!skb))888 goto next;889 890 if (unlikely(ring->hwtstamp_rx_filter == HWTSTAMP_FILTER_ALL)) {891 u64 timestamp = mlx4_en_get_cqe_ts(cqe);892 893 mlx4_en_fill_hwtstamps(priv->mdev, skb_hwtstamps(skb),894 timestamp);895 }896 skb_record_rx_queue(skb, cq_ring);897 898 if (likely(dev->features & NETIF_F_RXCSUM)) {899 /* TODO: For IP non TCP/UDP packets when csum complete is900 * not an option (not supported or any other reason) we can901 * actually check cqe IPOK status bit and report902 * CHECKSUM_UNNECESSARY rather than CHECKSUM_NONE903 */904 if ((cqe->status & cpu_to_be16(MLX4_CQE_STATUS_TCP |905 MLX4_CQE_STATUS_UDP)) &&906 (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPOK)) &&907 cqe->checksum == cpu_to_be16(0xffff)) {908 bool l2_tunnel;909 910 l2_tunnel = (dev->hw_enc_features & NETIF_F_RXCSUM) &&911 (cqe->vlan_my_qpn & cpu_to_be32(MLX4_CQE_L2_TUNNEL));912 ip_summed = CHECKSUM_UNNECESSARY;913 hash_type = PKT_HASH_TYPE_L4;914 if (l2_tunnel)915 skb->csum_level = 1;916 ring->csum_ok++;917 } else {918 if (!(priv->flags & MLX4_EN_FLAG_RX_CSUM_NON_TCP_UDP &&919 (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IP_ANY))))920 goto csum_none;921 if (check_csum(cqe, skb, va, dev->features))922 goto csum_none;923 ip_summed = CHECKSUM_COMPLETE;924 hash_type = PKT_HASH_TYPE_L3;925 ring->csum_complete++;926 }927 } else {928csum_none:929 ip_summed = CHECKSUM_NONE;930 hash_type = PKT_HASH_TYPE_L3;931 ring->csum_none++;932 }933 skb->ip_summed = ip_summed;934 if (dev->features & NETIF_F_RXHASH)935 skb_set_hash(skb,936 be32_to_cpu(cqe->immed_rss_invalid),937 hash_type);938 939 if ((cqe->vlan_my_qpn &940 cpu_to_be32(MLX4_CQE_CVLAN_PRESENT_MASK)) &&941 (dev->features & NETIF_F_HW_VLAN_CTAG_RX))942 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),943 be16_to_cpu(cqe->sl_vid));944 else if ((cqe->vlan_my_qpn &945 cpu_to_be32(MLX4_CQE_SVLAN_PRESENT_MASK)) &&946 (dev->features & NETIF_F_HW_VLAN_STAG_RX))947 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021AD),948 be16_to_cpu(cqe->sl_vid));949 950 nr = mlx4_en_complete_rx_desc(priv, frags, skb, length);951 if (likely(nr)) {952 skb_shinfo(skb)->nr_frags = nr;953 skb->len = length;954 skb->data_len = length;955 napi_gro_frags(&cq->napi);956 } else {957 __vlan_hwaccel_clear_tag(skb);958 skb_clear_hash(skb);959 }960next:961 ++cq->mcq.cons_index;962 index = (cq->mcq.cons_index) & ring->size_mask;963 cqe = mlx4_en_get_cqe(cq->buf, index, priv->cqe_size) + factor;964 if (unlikely(++polled == budget))965 break;966 }967 968 if (xdp_redir_flush)969 xdp_do_flush();970 971 if (likely(polled)) {972 if (doorbell_pending) {973 priv->tx_cq[TX_XDP][cq_ring]->xdp_busy = true;974 mlx4_en_xmit_doorbell(priv->tx_ring[TX_XDP][cq_ring]);975 }976 977 mlx4_cq_set_ci(&cq->mcq);978 wmb(); /* ensure HW sees CQ consumer before we post new buffers */979 ring->cons = cq->mcq.cons_index;980 }981 982 mlx4_en_refill_rx_buffers(priv, ring);983 984 return polled;985}986 987 988void mlx4_en_rx_irq(struct mlx4_cq *mcq)989{990 struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq);991 struct mlx4_en_priv *priv = netdev_priv(cq->dev);992 993 if (likely(priv->port_up))994 napi_schedule_irqoff(&cq->napi);995 else996 mlx4_en_arm_cq(priv, cq);997}998 999/* Rx CQ polling - called by NAPI */1000int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget)1001{1002 struct mlx4_en_cq *cq = container_of(napi, struct mlx4_en_cq, napi);1003 struct net_device *dev = cq->dev;1004 struct mlx4_en_priv *priv = netdev_priv(dev);1005 struct mlx4_en_cq *xdp_tx_cq = NULL;1006 bool clean_complete = true;1007 int done;1008 1009 if (!budget)1010 return 0;1011 1012 if (priv->tx_ring_num[TX_XDP]) {1013 xdp_tx_cq = priv->tx_cq[TX_XDP][cq->ring];1014 if (xdp_tx_cq->xdp_busy) {1015 clean_complete = mlx4_en_process_tx_cq(dev, xdp_tx_cq,1016 budget) < budget;1017 xdp_tx_cq->xdp_busy = !clean_complete;1018 }1019 }1020 1021 done = mlx4_en_process_rx_cq(dev, cq, budget);1022 1023 /* If we used up all the quota - we're probably not done yet... */1024 if (done == budget || !clean_complete) {1025 int cpu_curr;1026 1027 /* in case we got here because of !clean_complete */1028 done = budget;1029 1030 cpu_curr = smp_processor_id();1031 1032 if (likely(cpumask_test_cpu(cpu_curr, cq->aff_mask)))1033 return budget;1034 1035 /* Current cpu is not according to smp_irq_affinity -1036 * probably affinity changed. Need to stop this NAPI1037 * poll, and restart it on the right CPU.1038 * Try to avoid returning a too small value (like 0),1039 * to not fool net_rx_action() and its netdev_budget1040 */1041 if (done)1042 done--;1043 }1044 /* Done for now */1045 if (likely(napi_complete_done(napi, done)))1046 mlx4_en_arm_cq(priv, cq);1047 return done;1048}1049 1050void mlx4_en_calc_rx_buf(struct net_device *dev)1051{1052 struct mlx4_en_priv *priv = netdev_priv(dev);1053 int eff_mtu = MLX4_EN_EFF_MTU(dev->mtu);1054 int i = 0;1055 1056 /* bpf requires buffers to be set up as 1 packet per page.1057 * This only works when num_frags == 1.1058 */1059 if (priv->tx_ring_num[TX_XDP]) {1060 priv->frag_info[0].frag_size = eff_mtu;1061 /* This will gain efficient xdp frame recycling at the1062 * expense of more costly truesize accounting1063 */1064 priv->frag_info[0].frag_stride = PAGE_SIZE;1065 priv->dma_dir = DMA_BIDIRECTIONAL;1066 priv->rx_headroom = XDP_PACKET_HEADROOM;1067 i = 1;1068 } else {1069 int frag_size_max = 2048, buf_size = 0;1070 1071 /* should not happen, right ? */1072 if (eff_mtu > PAGE_SIZE + (MLX4_EN_MAX_RX_FRAGS - 1) * 2048)1073 frag_size_max = PAGE_SIZE;1074 1075 while (buf_size < eff_mtu) {1076 int frag_stride, frag_size = eff_mtu - buf_size;1077 int pad, nb;1078 1079 if (i < MLX4_EN_MAX_RX_FRAGS - 1)1080 frag_size = min(frag_size, frag_size_max);1081 1082 priv->frag_info[i].frag_size = frag_size;1083 frag_stride = ALIGN(frag_size, SMP_CACHE_BYTES);1084 /* We can only pack 2 1536-bytes frames in on 4K page1085 * Therefore, each frame would consume more bytes (truesize)1086 */1087 nb = PAGE_SIZE / frag_stride;1088 pad = (PAGE_SIZE - nb * frag_stride) / nb;1089 pad &= ~(SMP_CACHE_BYTES - 1);1090 priv->frag_info[i].frag_stride = frag_stride + pad;1091 1092 buf_size += frag_size;1093 i++;1094 }1095 priv->dma_dir = DMA_FROM_DEVICE;1096 priv->rx_headroom = 0;1097 }1098 1099 priv->num_frags = i;1100 priv->rx_skb_size = eff_mtu;1101 priv->log_rx_info = ROUNDUP_LOG2(i * sizeof(struct mlx4_en_rx_alloc));1102 1103 en_dbg(DRV, priv, "Rx buffer scatter-list (effective-mtu:%d num_frags:%d):\n",1104 eff_mtu, priv->num_frags);1105 for (i = 0; i < priv->num_frags; i++) {1106 en_dbg(DRV,1107 priv,1108 " frag:%d - size:%d stride:%d\n",1109 i,1110 priv->frag_info[i].frag_size,1111 priv->frag_info[i].frag_stride);1112 }1113}1114 1115/* RSS related functions */1116 1117static int mlx4_en_config_rss_qp(struct mlx4_en_priv *priv, int qpn,1118 struct mlx4_en_rx_ring *ring,1119 enum mlx4_qp_state *state,1120 struct mlx4_qp *qp)1121{1122 struct mlx4_en_dev *mdev = priv->mdev;1123 struct mlx4_qp_context *context;1124 int err = 0;1125 1126 context = kzalloc(sizeof(*context), GFP_KERNEL);1127 if (!context)1128 return -ENOMEM;1129 1130 err = mlx4_qp_alloc(mdev->dev, qpn, qp);1131 if (err) {1132 en_err(priv, "Failed to allocate qp #%x\n", qpn);1133 goto out;1134 }1135 qp->event = mlx4_en_sqp_event;1136 1137 mlx4_en_fill_qp_context(priv, ring->actual_size, ring->stride, 0, 0,1138 qpn, ring->cqn, -1, context);1139 context->db_rec_addr = cpu_to_be64(ring->wqres.db.dma);1140 1141 /* Cancel FCS removal if FW allows */1142 if (mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP) {1143 context->param3 |= cpu_to_be32(1 << 29);1144 if (priv->dev->features & NETIF_F_RXFCS)1145 ring->fcs_del = 0;1146 else1147 ring->fcs_del = ETH_FCS_LEN;1148 } else1149 ring->fcs_del = 0;1150 1151 err = mlx4_qp_to_ready(mdev->dev, &ring->wqres.mtt, context, qp, state);1152 if (err) {1153 mlx4_qp_remove(mdev->dev, qp);1154 mlx4_qp_free(mdev->dev, qp);1155 }1156 mlx4_en_update_rx_prod_db(ring);1157out:1158 kfree(context);1159 return err;1160}1161 1162int mlx4_en_create_drop_qp(struct mlx4_en_priv *priv)1163{1164 int err;1165 u32 qpn;1166 1167 err = mlx4_qp_reserve_range(priv->mdev->dev, 1, 1, &qpn,1168 MLX4_RESERVE_A0_QP,1169 MLX4_RES_USAGE_DRIVER);1170 if (err) {1171 en_err(priv, "Failed reserving drop qpn\n");1172 return err;1173 }1174 err = mlx4_qp_alloc(priv->mdev->dev, qpn, &priv->drop_qp);1175 if (err) {1176 en_err(priv, "Failed allocating drop qp\n");1177 mlx4_qp_release_range(priv->mdev->dev, qpn, 1);1178 return err;1179 }1180 1181 return 0;1182}1183 1184void mlx4_en_destroy_drop_qp(struct mlx4_en_priv *priv)1185{1186 u32 qpn;1187 1188 qpn = priv->drop_qp.qpn;1189 mlx4_qp_remove(priv->mdev->dev, &priv->drop_qp);1190 mlx4_qp_free(priv->mdev->dev, &priv->drop_qp);1191 mlx4_qp_release_range(priv->mdev->dev, qpn, 1);1192}1193 1194/* Allocate rx qp's and configure them according to rss map */1195int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv)1196{1197 struct mlx4_en_dev *mdev = priv->mdev;1198 struct mlx4_en_rss_map *rss_map = &priv->rss_map;1199 struct mlx4_qp_context context;1200 struct mlx4_rss_context *rss_context;1201 int rss_rings;1202 void *ptr;1203 u8 rss_mask = (MLX4_RSS_IPV4 | MLX4_RSS_TCP_IPV4 | MLX4_RSS_IPV6 |1204 MLX4_RSS_TCP_IPV6);1205 int i, qpn;1206 int err = 0;1207 int good_qps = 0;1208 u8 flags;1209 1210 en_dbg(DRV, priv, "Configuring rss steering\n");1211 1212 flags = priv->rx_ring_num == 1 ? MLX4_RESERVE_A0_QP : 0;1213 err = mlx4_qp_reserve_range(mdev->dev, priv->rx_ring_num,1214 priv->rx_ring_num,1215 &rss_map->base_qpn, flags,1216 MLX4_RES_USAGE_DRIVER);1217 if (err) {1218 en_err(priv, "Failed reserving %d qps\n", priv->rx_ring_num);1219 return err;1220 }1221 1222 for (i = 0; i < priv->rx_ring_num; i++) {1223 qpn = rss_map->base_qpn + i;1224 err = mlx4_en_config_rss_qp(priv, qpn, priv->rx_ring[i],1225 &rss_map->state[i],1226 &rss_map->qps[i]);1227 if (err)1228 goto rss_err;1229 1230 ++good_qps;1231 }1232 1233 if (priv->rx_ring_num == 1) {1234 rss_map->indir_qp = &rss_map->qps[0];1235 priv->base_qpn = rss_map->indir_qp->qpn;1236 en_info(priv, "Optimized Non-RSS steering\n");1237 return 0;1238 }1239 1240 rss_map->indir_qp = kzalloc(sizeof(*rss_map->indir_qp), GFP_KERNEL);1241 if (!rss_map->indir_qp) {1242 err = -ENOMEM;1243 goto rss_err;1244 }1245 1246 /* Configure RSS indirection qp */1247 err = mlx4_qp_alloc(mdev->dev, priv->base_qpn, rss_map->indir_qp);1248 if (err) {1249 en_err(priv, "Failed to allocate RSS indirection QP\n");1250 goto qp_alloc_err;1251 }1252 1253 rss_map->indir_qp->event = mlx4_en_sqp_event;1254 mlx4_en_fill_qp_context(priv, 0, 0, 0, 1, priv->base_qpn,1255 priv->rx_ring[0]->cqn, -1, &context);1256 1257 if (!priv->prof->rss_rings || priv->prof->rss_rings > priv->rx_ring_num)1258 rss_rings = priv->rx_ring_num;1259 else1260 rss_rings = priv->prof->rss_rings;1261 1262 ptr = ((void *) &context) + offsetof(struct mlx4_qp_context, pri_path)1263 + MLX4_RSS_OFFSET_IN_QPC_PRI_PATH;1264 rss_context = ptr;1265 rss_context->base_qpn = cpu_to_be32(ilog2(rss_rings) << 24 |1266 (rss_map->base_qpn));1267 rss_context->default_qpn = cpu_to_be32(rss_map->base_qpn);1268 if (priv->mdev->profile.udp_rss) {1269 rss_mask |= MLX4_RSS_UDP_IPV4 | MLX4_RSS_UDP_IPV6;1270 rss_context->base_qpn_udp = rss_context->default_qpn;1271 }1272 1273 if (mdev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {1274 en_info(priv, "Setting RSS context tunnel type to RSS on inner headers\n");1275 rss_mask |= MLX4_RSS_BY_INNER_HEADERS;1276 }1277 1278 rss_context->flags = rss_mask;1279 rss_context->hash_fn = MLX4_RSS_HASH_TOP;1280 if (priv->rss_hash_fn == ETH_RSS_HASH_XOR) {1281 rss_context->hash_fn = MLX4_RSS_HASH_XOR;1282 } else if (priv->rss_hash_fn == ETH_RSS_HASH_TOP) {1283 rss_context->hash_fn = MLX4_RSS_HASH_TOP;1284 memcpy(rss_context->rss_key, priv->rss_key,1285 MLX4_EN_RSS_KEY_SIZE);1286 } else {1287 en_err(priv, "Unknown RSS hash function requested\n");1288 err = -EINVAL;1289 goto indir_err;1290 }1291 1292 err = mlx4_qp_to_ready(mdev->dev, &priv->res.mtt, &context,1293 rss_map->indir_qp, &rss_map->indir_state);1294 if (err)1295 goto indir_err;1296 1297 return 0;1298 1299indir_err:1300 mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state,1301 MLX4_QP_STATE_RST, NULL, 0, 0, rss_map->indir_qp);1302 mlx4_qp_remove(mdev->dev, rss_map->indir_qp);1303 mlx4_qp_free(mdev->dev, rss_map->indir_qp);1304qp_alloc_err:1305 kfree(rss_map->indir_qp);1306 rss_map->indir_qp = NULL;1307rss_err:1308 for (i = 0; i < good_qps; i++) {1309 mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i],1310 MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]);1311 mlx4_qp_remove(mdev->dev, &rss_map->qps[i]);1312 mlx4_qp_free(mdev->dev, &rss_map->qps[i]);1313 }1314 mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num);1315 return err;1316}1317 1318void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv)1319{1320 struct mlx4_en_dev *mdev = priv->mdev;1321 struct mlx4_en_rss_map *rss_map = &priv->rss_map;1322 int i;1323 1324 if (priv->rx_ring_num > 1) {1325 mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state,1326 MLX4_QP_STATE_RST, NULL, 0, 0,1327 rss_map->indir_qp);1328 mlx4_qp_remove(mdev->dev, rss_map->indir_qp);1329 mlx4_qp_free(mdev->dev, rss_map->indir_qp);1330 kfree(rss_map->indir_qp);1331 rss_map->indir_qp = NULL;1332 }1333 1334 for (i = 0; i < priv->rx_ring_num; i++) {1335 mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i],1336 MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]);1337 mlx4_qp_remove(mdev->dev, &rss_map->qps[i]);1338 mlx4_qp_free(mdev->dev, &rss_map->qps[i]);1339 }1340 mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num);1341}1342