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1/*2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved.3 *4 * This software is available to you under a choice of one of two5 * licenses. You may choose to be licensed under the terms of the GNU6 * General Public License (GPL) Version 2, available from the file7 * COPYING in the main directory of this source tree, or the8 * OpenIB.org BSD license below:9 *10 * Redistribution and use in source and binary forms, with or11 * without modification, are permitted provided that the following12 * conditions are met:13 *14 * - Redistributions of source code must retain the above15 * copyright notice, this list of conditions and the following16 * disclaimer.17 *18 * - Redistributions in binary form must reproduce the above19 * copyright notice, this list of conditions and the following20 * disclaimer in the documentation and/or other materials21 * provided with the distribution.22 *23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE30 * SOFTWARE.31 *32 */33 34#ifndef _MLX4_EN_H_35#define _MLX4_EN_H_36 37#include <linux/bitops.h>38#include <linux/compiler.h>39#include <linux/ethtool.h>40#include <linux/list.h>41#include <linux/mutex.h>42#include <linux/netdevice.h>43#include <linux/if_vlan.h>44#include <linux/net_tstamp.h>45#ifdef CONFIG_MLX4_EN_DCB46#include <linux/dcbnl.h>47#endif48#include <linux/cpu_rmap.h>49#include <linux/ptp_clock_kernel.h>50#include <linux/irq.h>51#include <net/xdp.h>52#include <linux/notifier.h>53 54#include <linux/mlx4/device.h>55#include <linux/mlx4/qp.h>56#include <linux/mlx4/cq.h>57#include <linux/mlx4/srq.h>58#include <linux/mlx4/doorbell.h>59#include <linux/mlx4/cmd.h>60 61#include "en_port.h"62#include "mlx4_stats.h"63 64#define DRV_NAME "mlx4_en"65#define DRV_VERSION "4.0-0"66 67#define MLX4_EN_MSG_LEVEL (NETIF_MSG_LINK | NETIF_MSG_IFDOWN)68 69/*70 * Device constants71 */72 73 74#define MLX4_EN_PAGE_SHIFT 1275#define MLX4_EN_PAGE_SIZE (1 << MLX4_EN_PAGE_SHIFT)76#define DEF_RX_RINGS 1677#define MAX_RX_RINGS 12878#define MIN_RX_RINGS 179#define LOG_TXBB_SIZE 680#define TXBB_SIZE BIT(LOG_TXBB_SIZE)81#define HEADROOM (2048 / TXBB_SIZE + 1)82#define STAMP_STRIDE 6483#define STAMP_DWORDS (STAMP_STRIDE / 4)84#define STAMP_SHIFT 3185#define STAMP_VAL 0x7fffffff86#define STATS_DELAY (HZ / 4)87#define SERVICE_TASK_DELAY (HZ / 4)88#define MAX_NUM_OF_FS_RULES 25689 90#define MLX4_EN_FILTER_HASH_SHIFT 491#define MLX4_EN_FILTER_EXPIRY_QUOTA 6092 93#define CTRL_SIZE sizeof(struct mlx4_wqe_ctrl_seg)94#define DS_SIZE sizeof(struct mlx4_wqe_data_seg)95 96/* Maximal size of the bounce buffer:97 * 256 bytes for LSO headers.98 * CTRL_SIZE for control desc.99 * DS_SIZE if skb->head contains some payload.100 * MAX_SKB_FRAGS frags.101 */102#define MLX4_TX_BOUNCE_BUFFER_SIZE \103 ALIGN(256 + CTRL_SIZE + DS_SIZE + MAX_SKB_FRAGS * DS_SIZE, TXBB_SIZE)104 105#define MLX4_MAX_DESC_TXBBS (MLX4_TX_BOUNCE_BUFFER_SIZE / TXBB_SIZE)106 107/*108 * OS related constants and tunables109 */110 111#define MLX4_EN_PRIV_FLAGS_BLUEFLAME 1112#define MLX4_EN_PRIV_FLAGS_PHV 2113 114#define MLX4_EN_WATCHDOG_TIMEOUT (15 * HZ)115 116/* Use the maximum between 16384 and a single page */117#define MLX4_EN_ALLOC_SIZE PAGE_ALIGN(16384)118 119#define MLX4_EN_MAX_RX_FRAGS 4120 121/* Maximum ring sizes */122#define MLX4_EN_MAX_TX_SIZE 8192123#define MLX4_EN_MAX_RX_SIZE 8192124 125/* Minimum ring size for our page-allocation scheme to work */126#define MLX4_EN_MIN_RX_SIZE (MLX4_EN_ALLOC_SIZE / SMP_CACHE_BYTES)127#define MLX4_EN_MIN_TX_SIZE (4096 / TXBB_SIZE)128 129#define MLX4_EN_SMALL_PKT_SIZE 64130#define MLX4_EN_MIN_TX_RING_P_UP 1131#define MLX4_EN_MAX_TX_RING_P_UP 32132#define MLX4_EN_NUM_UP_LOW 1133#define MLX4_EN_NUM_UP_HIGH 8134#define MLX4_EN_DEF_RX_RING_SIZE 1024135#define MLX4_EN_DEF_TX_RING_SIZE MLX4_EN_DEF_RX_RING_SIZE136#define MAX_TX_RINGS (MLX4_EN_MAX_TX_RING_P_UP * \137 MLX4_EN_NUM_UP_HIGH)138 139#define MLX4_EN_DEFAULT_TX_WORK 256140 141/* Target number of packets to coalesce with interrupt moderation */142#define MLX4_EN_RX_COAL_TARGET 44143#define MLX4_EN_RX_COAL_TIME 0x10144 145#define MLX4_EN_TX_COAL_PKTS 16146#define MLX4_EN_TX_COAL_TIME 0x10147 148#define MLX4_EN_MAX_COAL_PKTS U16_MAX149#define MLX4_EN_MAX_COAL_TIME U16_MAX150 151#define MLX4_EN_RX_RATE_LOW 400000152#define MLX4_EN_RX_COAL_TIME_LOW 0153#define MLX4_EN_RX_RATE_HIGH 450000154#define MLX4_EN_RX_COAL_TIME_HIGH 128155#define MLX4_EN_RX_SIZE_THRESH 1024156#define MLX4_EN_RX_RATE_THRESH (1000000 / MLX4_EN_RX_COAL_TIME_HIGH)157#define MLX4_EN_SAMPLE_INTERVAL 0158#define MLX4_EN_AVG_PKT_SMALL 256159 160#define MLX4_EN_AUTO_CONF 0xffff161 162#define MLX4_EN_DEF_RX_PAUSE 1163#define MLX4_EN_DEF_TX_PAUSE 1164 165/* Interval between successive polls in the Tx routine when polling is used166 instead of interrupts (in per-core Tx rings) - should be power of 2 */167#define MLX4_EN_TX_POLL_MODER 16168#define MLX4_EN_TX_POLL_TIMEOUT (HZ / 4)169 170#define SMALL_PACKET_SIZE (256 - NET_IP_ALIGN)171#define HEADER_COPY_SIZE (128 - NET_IP_ALIGN)172#define MLX4_LOOPBACK_TEST_PAYLOAD (HEADER_COPY_SIZE - ETH_HLEN)173#define PREAMBLE_LEN 8174#define MLX4_SELFTEST_LB_MIN_MTU (MLX4_LOOPBACK_TEST_PAYLOAD + NET_IP_ALIGN + \175 ETH_HLEN + PREAMBLE_LEN)176 177/* VLAN_HLEN is added twice,to support skb vlan tagged with multiple178 * headers. (For example: ETH_P_8021Q and ETH_P_8021AD).179 */180#define MLX4_EN_EFF_MTU(mtu) ((mtu) + ETH_HLEN + (2 * VLAN_HLEN))181#define ETH_BCAST 0xffffffffffffULL182 183#define MLX4_EN_LOOPBACK_RETRIES 5184#define MLX4_EN_LOOPBACK_TIMEOUT 100185 186/* Constants for TX flow */187enum {188 MAX_INLINE = 104, /* 128 - 16 - 4 - 4 */189 MAX_BF = 256,190 MIN_PKT_LEN = 17,191};192 193/*194 * Configurables195 */196 197enum cq_type {198 /* keep tx types first */199 TX,200 TX_XDP,201#define MLX4_EN_NUM_TX_TYPES (TX_XDP + 1)202 RX,203};204 205 206/*207 * Useful macros208 */209#define ROUNDUP_LOG2(x) ilog2(roundup_pow_of_two(x))210#define XNOR(x, y) (!(x) == !(y))211 212 213struct mlx4_en_tx_info {214 union {215 struct sk_buff *skb;216 struct page *page;217 };218 dma_addr_t map0_dma;219 u32 map0_byte_count;220 u32 nr_txbb;221 u32 nr_bytes;222 u8 linear;223 u8 data_offset;224 u8 inl;225 u8 ts_requested;226 u8 nr_maps;227} ____cacheline_aligned_in_smp;228 229 230#define MLX4_EN_BIT_DESC_OWN 0x80000000231#define MLX4_EN_MEMTYPE_PAD 0x100232 233 234struct mlx4_en_tx_desc {235 struct mlx4_wqe_ctrl_seg ctrl;236 union {237 struct mlx4_wqe_data_seg data; /* at least one data segment */238 struct mlx4_wqe_lso_seg lso;239 struct mlx4_wqe_inline_seg inl;240 };241};242 243#define MLX4_EN_USE_SRQ 0x01000000244 245#define MLX4_EN_CX3_LOW_ID 0x1000246#define MLX4_EN_CX3_HIGH_ID 0x1005247 248struct mlx4_en_rx_alloc {249 struct page *page;250 dma_addr_t dma;251 u32 page_offset;252};253 254#define MLX4_EN_CACHE_SIZE (2 * NAPI_POLL_WEIGHT)255 256struct mlx4_en_page_cache {257 u32 index;258 struct {259 struct page *page;260 dma_addr_t dma;261 } buf[MLX4_EN_CACHE_SIZE];262};263 264enum {265 MLX4_EN_TX_RING_STATE_RECOVERING,266};267 268struct mlx4_en_priv;269 270struct mlx4_en_tx_ring {271 /* cache line used and dirtied in tx completion272 * (mlx4_en_free_tx_buf())273 */274 u32 last_nr_txbb;275 u32 cons;276 unsigned long wake_queue;277 struct netdev_queue *tx_queue;278 u32 (*free_tx_desc)(struct mlx4_en_priv *priv,279 struct mlx4_en_tx_ring *ring,280 int index,281 u64 timestamp, int napi_mode);282 struct mlx4_en_rx_ring *recycle_ring;283 284 /* cache line used and dirtied in mlx4_en_xmit() */285 u32 prod ____cacheline_aligned_in_smp;286 unsigned int tx_dropped;287 unsigned long bytes;288 unsigned long packets;289 unsigned long tx_csum;290 unsigned long tso_packets;291 unsigned long xmit_more;292 struct mlx4_bf bf;293 294 /* Following part should be mostly read */295 void __iomem *doorbell_address;296 __be32 doorbell_qpn;297 __be32 mr_key;298 u32 size; /* number of TXBBs */299 u32 size_mask;300 u32 full_size;301 u32 buf_size;302 void *buf;303 struct mlx4_en_tx_info *tx_info;304 int qpn;305 u8 queue_index;306 bool bf_enabled;307 bool bf_alloced;308 u8 hwtstamp_tx_type;309 u8 *bounce_buf;310 311 /* Not used in fast path312 * Only queue_stopped might be used if BQL is not properly working.313 */314 unsigned long queue_stopped;315 unsigned long state;316 struct mlx4_hwq_resources sp_wqres;317 struct mlx4_qp sp_qp;318 struct mlx4_qp_context sp_context;319 cpumask_t sp_affinity_mask;320 enum mlx4_qp_state sp_qp_state;321 u16 sp_stride;322 u16 sp_cqn; /* index of port CQ associated with this ring */323} ____cacheline_aligned_in_smp;324 325struct mlx4_en_rx_desc {326 /* actual number of entries depends on rx ring stride */327 DECLARE_FLEX_ARRAY(struct mlx4_wqe_data_seg, data);328};329 330struct mlx4_en_rx_ring {331 struct mlx4_hwq_resources wqres;332 u32 size ; /* number of Rx descs*/333 u32 actual_size;334 u32 size_mask;335 u16 stride;336 u16 log_stride;337 u16 cqn; /* index of port CQ associated with this ring */338 u32 prod;339 u32 cons;340 u32 buf_size;341 u8 fcs_del;342 void *buf;343 void *rx_info;344 struct bpf_prog __rcu *xdp_prog;345 struct mlx4_en_page_cache page_cache;346 unsigned long bytes;347 unsigned long packets;348 unsigned long csum_ok;349 unsigned long csum_none;350 unsigned long csum_complete;351 unsigned long rx_alloc_pages;352 unsigned long xdp_drop;353 unsigned long xdp_redirect;354 unsigned long xdp_redirect_fail;355 unsigned long xdp_tx;356 unsigned long xdp_tx_full;357 unsigned long dropped;358 unsigned long alloc_fail;359 int hwtstamp_rx_filter;360 cpumask_var_t affinity_mask;361 struct xdp_rxq_info xdp_rxq;362};363 364struct mlx4_en_cq {365 struct mlx4_cq mcq;366 struct mlx4_hwq_resources wqres;367 int ring;368 struct net_device *dev;369 union {370 struct napi_struct napi;371 bool xdp_busy;372 };373 int size;374 int buf_size;375 int vector;376 enum cq_type type;377 u16 moder_time;378 u16 moder_cnt;379 struct mlx4_cqe *buf;380#define MLX4_EN_OPCODE_ERROR 0x1e381 382 const struct cpumask *aff_mask;383 int cq_idx;384};385 386struct mlx4_en_port_profile {387 u32 flags;388 u32 tx_ring_num[MLX4_EN_NUM_TX_TYPES];389 u32 rx_ring_num;390 u32 tx_ring_size;391 u32 rx_ring_size;392 u8 num_tx_rings_p_up;393 u8 rx_pause;394 u8 rx_ppp;395 u8 tx_pause;396 u8 tx_ppp;397 u8 num_up;398 int rss_rings;399 int inline_thold;400 struct hwtstamp_config hwtstamp_config;401};402 403struct mlx4_en_profile {404 int udp_rss;405 u8 rss_mask;406 u32 active_ports;407 u32 small_pkt_int;408 u8 no_reset;409 u8 max_num_tx_rings_p_up;410 struct mlx4_en_port_profile prof[MLX4_MAX_PORTS + 1];411};412 413struct mlx4_en_dev {414 struct mlx4_dev *dev;415 struct pci_dev *pdev;416 struct mutex state_lock;417 struct net_device *pndev[MLX4_MAX_PORTS + 1];418 struct net_device *upper[MLX4_MAX_PORTS + 1];419 u32 port_cnt;420 bool device_up;421 struct mlx4_en_profile profile;422 u32 LSO_support;423 struct workqueue_struct *workqueue;424 struct device *dma_device;425 void __iomem *uar_map;426 struct mlx4_uar priv_uar;427 struct mlx4_mr mr;428 u32 priv_pdn;429 spinlock_t uar_lock;430 u8 mac_removed[MLX4_MAX_PORTS + 1];431 u32 nominal_c_mult;432 struct cyclecounter cycles;433 seqlock_t clock_lock;434 struct timecounter clock;435 unsigned long last_overflow_check;436 struct ptp_clock *ptp_clock;437 struct ptp_clock_info ptp_clock_info;438 struct notifier_block netdev_nb;439 struct notifier_block mlx_nb;440};441 442 443struct mlx4_en_rss_map {444 int base_qpn;445 struct mlx4_qp qps[MAX_RX_RINGS];446 enum mlx4_qp_state state[MAX_RX_RINGS];447 struct mlx4_qp *indir_qp;448 enum mlx4_qp_state indir_state;449};450 451enum mlx4_en_port_flag {452 MLX4_EN_PORT_ANC = 1<<0, /* Auto-negotiation complete */453 MLX4_EN_PORT_ANE = 1<<1, /* Auto-negotiation enabled */454};455 456struct mlx4_en_port_state {457 int link_state;458 int link_speed;459 int transceiver;460 u32 flags;461};462 463enum mlx4_en_mclist_act {464 MCLIST_NONE,465 MCLIST_REM,466 MCLIST_ADD,467};468 469struct mlx4_en_mc_list {470 struct list_head list;471 enum mlx4_en_mclist_act action;472 u8 addr[ETH_ALEN];473 u64 reg_id;474 u64 tunnel_reg_id;475};476 477struct mlx4_en_frag_info {478 u16 frag_size;479 u32 frag_stride;480};481 482#ifdef CONFIG_MLX4_EN_DCB483/* Minimal TC BW - setting to 0 will block traffic */484#define MLX4_EN_BW_MIN 1485#define MLX4_EN_BW_MAX 100 /* Utilize 100% of the line */486 487#define MLX4_EN_TC_VENDOR 0488#define MLX4_EN_TC_ETS 7489 490enum dcb_pfc_type {491 pfc_disabled = 0,492 pfc_enabled_full,493 pfc_enabled_tx,494 pfc_enabled_rx495};496 497struct mlx4_en_cee_config {498 bool pfc_state;499 enum dcb_pfc_type dcb_pfc[MLX4_EN_NUM_UP_HIGH];500};501#endif502 503struct ethtool_flow_id {504 struct list_head list;505 struct ethtool_rx_flow_spec flow_spec;506 u64 id;507};508 509enum {510 MLX4_EN_FLAG_PROMISC = (1 << 0),511 MLX4_EN_FLAG_MC_PROMISC = (1 << 1),512 /* whether we need to enable hardware loopback by putting dmac513 * in Tx WQE514 */515 MLX4_EN_FLAG_ENABLE_HW_LOOPBACK = (1 << 2),516 /* whether we need to drop packets that hardware loopback-ed */517 MLX4_EN_FLAG_RX_FILTER_NEEDED = (1 << 3),518 MLX4_EN_FLAG_FORCE_PROMISC = (1 << 4),519 MLX4_EN_FLAG_RX_CSUM_NON_TCP_UDP = (1 << 5),520#ifdef CONFIG_MLX4_EN_DCB521 MLX4_EN_FLAG_DCB_ENABLED = (1 << 6),522#endif523};524 525#define PORT_BEACON_MAX_LIMIT (65535)526#define MLX4_EN_MAC_HASH_SIZE (1 << BITS_PER_BYTE)527#define MLX4_EN_MAC_HASH_IDX 5528 529struct mlx4_en_stats_bitmap {530 DECLARE_BITMAP(bitmap, NUM_ALL_STATS);531 struct mutex mutex; /* for mutual access to stats bitmap */532};533 534enum {535 MLX4_EN_STATE_FLAG_RESTARTING,536};537 538struct mlx4_en_priv {539 struct mlx4_en_dev *mdev;540 struct mlx4_en_port_profile *prof;541 struct net_device *dev;542 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];543 struct mlx4_en_port_state port_state;544 spinlock_t stats_lock;545 struct ethtool_flow_id ethtool_rules[MAX_NUM_OF_FS_RULES];546 /* To allow rules removal while port is going down */547 struct list_head ethtool_list;548 549 unsigned long last_moder_packets[MAX_RX_RINGS];550 unsigned long last_moder_tx_packets;551 unsigned long last_moder_bytes[MAX_RX_RINGS];552 unsigned long last_moder_jiffies;553 int last_moder_time[MAX_RX_RINGS];554 u16 rx_usecs;555 u16 rx_frames;556 u16 tx_usecs;557 u16 tx_frames;558 u32 pkt_rate_low;559 u16 rx_usecs_low;560 u32 pkt_rate_high;561 u16 rx_usecs_high;562 u32 sample_interval;563 u32 adaptive_rx_coal;564 u32 msg_enable;565 u32 loopback_ok;566 u32 validate_loopback;567 568 struct mlx4_hwq_resources res;569 int link_state;570 bool port_up;571 int port;572 int registered;573 int allocated;574 int stride;575 unsigned char current_mac[ETH_ALEN + 2];576 int mac_index;577 unsigned max_mtu;578 int base_qpn;579 int cqe_factor;580 int cqe_size;581 582 struct mlx4_en_rss_map rss_map;583 __be32 ctrl_flags;584 u32 flags;585 u8 num_tx_rings_p_up;586 u32 tx_work_limit;587 u32 tx_ring_num[MLX4_EN_NUM_TX_TYPES];588 u32 rx_ring_num;589 u32 rx_skb_size;590 struct mlx4_en_frag_info frag_info[MLX4_EN_MAX_RX_FRAGS];591 u8 num_frags;592 u8 log_rx_info;593 u8 dma_dir;594 u16 rx_headroom;595 596 struct mlx4_en_tx_ring **tx_ring[MLX4_EN_NUM_TX_TYPES];597 struct mlx4_en_rx_ring *rx_ring[MAX_RX_RINGS];598 struct mlx4_en_cq **tx_cq[MLX4_EN_NUM_TX_TYPES];599 struct mlx4_en_cq *rx_cq[MAX_RX_RINGS];600 struct mlx4_qp drop_qp;601 struct work_struct rx_mode_task;602 struct work_struct restart_task;603 struct work_struct linkstate_task;604 struct delayed_work stats_task;605 struct delayed_work service_task;606 struct mlx4_en_pkt_stats pkstats;607 struct mlx4_en_counter_stats pf_stats;608 struct mlx4_en_flow_stats_rx rx_priority_flowstats[MLX4_NUM_PRIORITIES];609 struct mlx4_en_flow_stats_tx tx_priority_flowstats[MLX4_NUM_PRIORITIES];610 struct mlx4_en_flow_stats_rx rx_flowstats;611 struct mlx4_en_flow_stats_tx tx_flowstats;612 struct mlx4_en_port_stats port_stats;613 struct mlx4_en_xdp_stats xdp_stats;614 struct mlx4_en_phy_stats phy_stats;615 struct mlx4_en_stats_bitmap stats_bitmap;616 struct list_head mc_list;617 struct list_head curr_list;618 u64 broadcast_id;619 struct mlx4_en_stat_out_mbox hw_stats;620 int vids[128];621 bool wol;622 struct device *ddev;623 struct hlist_head mac_hash[MLX4_EN_MAC_HASH_SIZE];624 struct hwtstamp_config hwtstamp_config;625 u32 counter_index;626 627#ifdef CONFIG_MLX4_EN_DCB628#define MLX4_EN_DCB_ENABLED 0x3629 struct ieee_ets ets;630 u16 maxrate[IEEE_8021QAZ_MAX_TCS];631 enum dcbnl_cndd_states cndd_state[IEEE_8021QAZ_MAX_TCS];632 struct mlx4_en_cee_config cee_config;633 u8 dcbx_cap;634#endif635#ifdef CONFIG_RFS_ACCEL636 spinlock_t filters_lock;637 int last_filter_id;638 struct list_head filters;639 struct hlist_head filter_hash[1 << MLX4_EN_FILTER_HASH_SHIFT];640#endif641 u64 tunnel_reg_id;642 __be16 vxlan_port;643 644 u32 pflags;645 u8 rss_key[MLX4_EN_RSS_KEY_SIZE];646 u8 rss_hash_fn;647 unsigned long state;648};649 650enum mlx4_en_wol {651 MLX4_EN_WOL_MAGIC = (1ULL << 61),652 MLX4_EN_WOL_ENABLED = (1ULL << 62),653};654 655struct mlx4_mac_entry {656 struct hlist_node hlist;657 unsigned char mac[ETH_ALEN + 2];658 u64 reg_id;659 struct rcu_head rcu;660};661 662static inline struct mlx4_cqe *mlx4_en_get_cqe(void *buf, int idx, int cqe_sz)663{664 return buf + idx * cqe_sz;665}666 667#define MLX4_EN_WOL_DO_MODIFY (1ULL << 63)668 669void mlx4_en_init_ptys2ethtool_map(void);670void mlx4_en_update_loopback_state(struct net_device *dev,671 netdev_features_t features);672 673void mlx4_en_destroy_netdev(struct net_device *dev);674int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port,675 struct mlx4_en_port_profile *prof);676 677int mlx4_en_start_port(struct net_device *dev);678void mlx4_en_stop_port(struct net_device *dev, int detach);679 680void mlx4_en_set_stats_bitmap(struct mlx4_dev *dev,681 struct mlx4_en_stats_bitmap *stats_bitmap,682 u8 rx_ppp, u8 rx_pause,683 u8 tx_ppp, u8 tx_pause);684 685int mlx4_en_try_alloc_resources(struct mlx4_en_priv *priv,686 struct mlx4_en_priv *tmp,687 struct mlx4_en_port_profile *prof,688 bool carry_xdp_prog);689void mlx4_en_safe_replace_resources(struct mlx4_en_priv *priv,690 struct mlx4_en_priv *tmp);691 692int mlx4_en_create_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq,693 int entries, int ring, enum cq_type mode, int node);694void mlx4_en_destroy_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq);695int mlx4_en_activate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq,696 int cq_idx);697void mlx4_en_deactivate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);698int mlx4_en_set_cq_moder(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);699void mlx4_en_arm_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);700 701void mlx4_en_tx_irq(struct mlx4_cq *mcq);702u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb,703 struct net_device *sb_dev);704netdev_tx_t mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev);705netdev_tx_t mlx4_en_xmit_frame(struct mlx4_en_rx_ring *rx_ring,706 struct mlx4_en_rx_alloc *frame,707 struct mlx4_en_priv *priv, unsigned int length,708 int tx_ind, bool *doorbell_pending);709void mlx4_en_xmit_doorbell(struct mlx4_en_tx_ring *ring);710bool mlx4_en_rx_recycle(struct mlx4_en_rx_ring *ring,711 struct mlx4_en_rx_alloc *frame);712 713int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv,714 struct mlx4_en_tx_ring **pring,715 u32 size, u16 stride,716 int node, int queue_index);717void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv,718 struct mlx4_en_tx_ring **pring);719void mlx4_en_init_tx_xdp_ring_descs(struct mlx4_en_priv *priv,720 struct mlx4_en_tx_ring *ring);721int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv,722 struct mlx4_en_tx_ring *ring,723 int cq, int user_prio);724void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv,725 struct mlx4_en_tx_ring *ring);726void mlx4_en_set_num_rx_rings(struct mlx4_en_dev *mdev);727void mlx4_en_recover_from_oom(struct mlx4_en_priv *priv);728int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv,729 struct mlx4_en_rx_ring **pring,730 u32 size, u16 stride, int node, int queue_index);731void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv,732 struct mlx4_en_rx_ring **pring,733 u32 size, u16 stride);734int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv);735void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv,736 struct mlx4_en_rx_ring *ring);737int mlx4_en_process_rx_cq(struct net_device *dev,738 struct mlx4_en_cq *cq,739 int budget);740int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget);741int mlx4_en_poll_tx_cq(struct napi_struct *napi, int budget);742int mlx4_en_process_tx_cq(struct net_device *dev,743 struct mlx4_en_cq *cq, int napi_budget);744u32 mlx4_en_free_tx_desc(struct mlx4_en_priv *priv,745 struct mlx4_en_tx_ring *ring,746 int index, u64 timestamp,747 int napi_mode);748u32 mlx4_en_recycle_tx_desc(struct mlx4_en_priv *priv,749 struct mlx4_en_tx_ring *ring,750 int index, u64 timestamp,751 int napi_mode);752void mlx4_en_fill_qp_context(struct mlx4_en_priv *priv, int size, int stride,753 int is_tx, int rss, int qpn, int cqn, int user_prio,754 struct mlx4_qp_context *context);755void mlx4_en_sqp_event(struct mlx4_qp *qp, enum mlx4_event event);756int mlx4_en_change_mcast_lb(struct mlx4_en_priv *priv, struct mlx4_qp *qp,757 int loopback);758void mlx4_en_calc_rx_buf(struct net_device *dev);759int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv);760void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv);761int mlx4_en_create_drop_qp(struct mlx4_en_priv *priv);762void mlx4_en_destroy_drop_qp(struct mlx4_en_priv *priv);763int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring);764void mlx4_en_rx_irq(struct mlx4_cq *mcq);765 766int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);767int mlx4_SET_VLAN_FLTR(struct mlx4_dev *dev, struct mlx4_en_priv *priv);768 769void mlx4_en_fold_software_stats(struct net_device *dev);770int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset);771int mlx4_en_QUERY_PORT(struct mlx4_en_dev *mdev, u8 port);772 773#ifdef CONFIG_MLX4_EN_DCB774extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_ops;775extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_pfc_ops;776#endif777 778int mlx4_en_setup_tc(struct net_device *dev, u8 up);779int mlx4_en_alloc_tx_queue_per_tc(struct net_device *dev, u8 tc);780 781#ifdef CONFIG_RFS_ACCEL782void mlx4_en_cleanup_filters(struct mlx4_en_priv *priv);783#endif784 785#define MLX4_EN_NUM_SELF_TEST 5786void mlx4_en_ex_selftest(struct net_device *dev, u32 *flags, u64 *buf);787void mlx4_en_ptp_overflow_check(struct mlx4_en_dev *mdev);788 789#define DEV_FEATURE_CHANGED(dev, new_features, feature) \790 ((dev->features & feature) ^ (new_features & feature))791 792int mlx4_en_moderation_update(struct mlx4_en_priv *priv);793int mlx4_en_reset_config(struct net_device *dev,794 struct hwtstamp_config ts_config,795 netdev_features_t new_features);796void mlx4_en_update_pfc_stats_bitmap(struct mlx4_dev *dev,797 struct mlx4_en_stats_bitmap *stats_bitmap,798 u8 rx_ppp, u8 rx_pause,799 u8 tx_ppp, u8 tx_pause);800int mlx4_en_netdev_event(struct notifier_block *this,801 unsigned long event, void *ptr);802 803struct xdp_md;804int mlx4_en_xdp_rx_timestamp(const struct xdp_md *ctx, u64 *timestamp);805int mlx4_en_xdp_rx_hash(const struct xdp_md *ctx, u32 *hash,806 enum xdp_rss_hash_type *rss_type);807 808/*809 * Functions for time stamping810 */811u64 mlx4_en_get_cqe_ts(struct mlx4_cqe *cqe);812u64 mlx4_en_get_hwtstamp(struct mlx4_en_dev *mdev, u64 timestamp);813void mlx4_en_fill_hwtstamps(struct mlx4_en_dev *mdev,814 struct skb_shared_hwtstamps *hwts,815 u64 timestamp);816void mlx4_en_init_timestamp(struct mlx4_en_dev *mdev);817void mlx4_en_remove_timestamp(struct mlx4_en_dev *mdev);818 819/* Globals820 */821extern const struct ethtool_ops mlx4_en_ethtool_ops;822 823 824 825/*826 * printk / logging functions827 */828 829__printf(3, 4)830void en_print(const char *level, const struct mlx4_en_priv *priv,831 const char *format, ...);832 833#define en_dbg(mlevel, priv, format, ...) \834do { \835 if (NETIF_MSG_##mlevel & (priv)->msg_enable) \836 en_print(KERN_DEBUG, priv, format, ##__VA_ARGS__); \837} while (0)838#define en_warn(priv, format, ...) \839 en_print(KERN_WARNING, priv, format, ##__VA_ARGS__)840#define en_err(priv, format, ...) \841 en_print(KERN_ERR, priv, format, ##__VA_ARGS__)842#define en_info(priv, format, ...) \843 en_print(KERN_INFO, priv, format, ##__VA_ARGS__)844 845#define mlx4_err(mdev, format, ...) \846 pr_err(DRV_NAME " %s: " format, \847 dev_name(&(mdev)->pdev->dev), ##__VA_ARGS__)848#define mlx4_info(mdev, format, ...) \849 pr_info(DRV_NAME " %s: " format, \850 dev_name(&(mdev)->pdev->dev), ##__VA_ARGS__)851#define mlx4_warn(mdev, format, ...) \852 pr_warn(DRV_NAME " %s: " format, \853 dev_name(&(mdev)->pdev->dev), ##__VA_ARGS__)854 855#endif856