1239 lines · c
1/*2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.3 *4 * This software is available to you under a choice of one of two5 * licenses. You may choose to be licensed under the terms of the GNU6 * General Public License (GPL) Version 2, available from the file7 * COPYING in the main directory of this source tree, or the8 * OpenIB.org BSD license below:9 *10 * Redistribution and use in source and binary forms, with or11 * without modification, are permitted provided that the following12 * conditions are met:13 *14 * - Redistributions of source code must retain the above15 * copyright notice, this list of conditions and the following16 * disclaimer.17 *18 * - Redistributions in binary form must reproduce the above19 * copyright notice, this list of conditions and the following20 * disclaimer in the documentation and/or other materials21 * provided with the distribution.22 *23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE30 * SOFTWARE.31 */32#ifndef __MLX5_EN_H__33#define __MLX5_EN_H__34 35#include <linux/if_vlan.h>36#include <linux/etherdevice.h>37#include <linux/timecounter.h>38#include <linux/net_tstamp.h>39#include <linux/crash_dump.h>40#include <linux/mlx5/driver.h>41#include <linux/mlx5/qp.h>42#include <linux/mlx5/cq.h>43#include <linux/mlx5/port.h>44#include <linux/mlx5/vport.h>45#include <linux/mlx5/transobj.h>46#include <linux/mlx5/fs.h>47#include <linux/rhashtable.h>48#include <net/udp_tunnel.h>49#include <net/switchdev.h>50#include <net/xdp.h>51#include <linux/dim.h>52#include <linux/bits.h>53#include "wq.h"54#include "mlx5_core.h"55#include "en_stats.h"56#include "en/dcbnl.h"57#include "en/fs.h"58#include "en/qos.h"59#include "lib/hv_vhca.h"60#include "lib/clock.h"61#include "en/rx_res.h"62#include "en/selq.h"63#include "lib/sd.h"64 65extern const struct net_device_ops mlx5e_netdev_ops;66struct page_pool;67 68#define MLX5E_METADATA_ETHER_TYPE (0x8CE4)69#define MLX5E_METADATA_ETHER_LEN 870 71#define MLX5E_ETH_HARD_MTU (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN)72 73#define MLX5E_HW2SW_MTU(params, hwmtu) ((hwmtu) - ((params)->hard_mtu))74#define MLX5E_SW2HW_MTU(params, swmtu) ((swmtu) + ((params)->hard_mtu))75 76#define MLX5E_MAX_NUM_MQPRIO_CH_TC TC_QOPT_MAX_QUEUE77 78#define MLX5_RX_HEADROOM NET_SKB_PAD79#define MLX5_SKB_FRAG_SZ(len) (SKB_DATA_ALIGN(len) + \80 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))81 82#define MLX5E_RX_MAX_HEAD (256)83#define MLX5E_SHAMPO_LOG_HEADER_ENTRY_SIZE (8)84#define MLX5E_SHAMPO_LOG_MAX_HEADER_ENTRY_SIZE (9)85#define MLX5E_SHAMPO_WQ_HEADER_PER_PAGE (PAGE_SIZE >> MLX5E_SHAMPO_LOG_MAX_HEADER_ENTRY_SIZE)86#define MLX5E_SHAMPO_WQ_BASE_HEAD_ENTRY_SIZE (64)87#define MLX5E_SHAMPO_WQ_RESRV_SIZE (64 * 1024)88#define MLX5E_SHAMPO_WQ_BASE_RESRV_SIZE (4096)89 90#define MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev) \91 (6 + MLX5_CAP_GEN(mdev, cache_line_128byte)) /* HW restriction */92#define MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, req) \93 max_t(u32, MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev), req)94#define MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(mdev) \95 MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, order_base_2(MLX5E_RX_MAX_HEAD))96 97#define MLX5_MPWRQ_MAX_LOG_WQE_SZ 1898 99/* Keep in sync with mlx5e_mpwrq_log_wqe_sz.100 * These are theoretical maximums, which can be further restricted by101 * capabilities. These values are used for static resource allocations and102 * sanity checks.103 * MLX5_SEND_WQE_MAX_SIZE is a bit bigger than the maximum cacheline-aligned WQE104 * size actually used at runtime, but it's not a problem when calculating static105 * array sizes.106 */107#define MLX5_UMR_MAX_FLEX_SPACE \108 (ALIGN_DOWN(MLX5_SEND_WQE_MAX_SIZE - sizeof(struct mlx5e_umr_wqe), \109 MLX5_UMR_FLEX_ALIGNMENT))110#define MLX5_MPWRQ_MAX_PAGES_PER_WQE \111 rounddown_pow_of_two(MLX5_UMR_MAX_FLEX_SPACE / sizeof(struct mlx5_mtt))112 113#define MLX5E_MAX_RQ_NUM_MTTS \114 (ALIGN_DOWN(U16_MAX, 4) * 2) /* Fits into u16 and aligned by WQEBB. */115#define MLX5E_MAX_RQ_NUM_KSMS (U16_MAX - 1) /* So that num_ksms fits into u16. */116#define MLX5E_ORDER2_MAX_PACKET_MTU (order_base_2(10 * 1024))117 118#define MLX5E_MIN_SKB_FRAG_SZ (MLX5_SKB_FRAG_SZ(MLX5_RX_HEADROOM))119#define MLX5E_LOG_MAX_RX_WQE_BULK \120 (ilog2(PAGE_SIZE / roundup_pow_of_two(MLX5E_MIN_SKB_FRAG_SZ)))121 122#define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x6123#define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa124#define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xd125 126#define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE (1 + MLX5E_LOG_MAX_RX_WQE_BULK)127#define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa128#define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE 0xd129 130#define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW 0x2131 132#define MLX5E_DEFAULT_LRO_TIMEOUT 32133#define MLX5E_DEFAULT_SHAMPO_TIMEOUT 1024134 135#define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10136#define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3137#define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20138#define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10139#define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE 0x10140#define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20141#define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80142#define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW 0x2143 144#define MLX5E_MIN_NUM_CHANNELS 0x1145#define MLX5E_MAX_NUM_CHANNELS 256146#define MLX5E_TX_CQ_POLL_BUDGET 128147#define MLX5E_TX_XSK_POLL_BUDGET 64148#define MLX5E_SQ_RECOVER_MIN_INTERVAL 500 /* msecs */149 150#define mlx5e_state_dereference(priv, p) \151 rcu_dereference_protected((p), lockdep_is_held(&(priv)->state_lock))152 153enum mlx5e_devcom_events {154 MPV_DEVCOM_MASTER_UP,155 MPV_DEVCOM_MASTER_DOWN,156 MPV_DEVCOM_IPSEC_MASTER_UP,157 MPV_DEVCOM_IPSEC_MASTER_DOWN,158};159 160static inline u8 mlx5e_get_num_lag_ports(struct mlx5_core_dev *mdev)161{162 if (mlx5_lag_is_lacp_owner(mdev))163 return 1;164 165 return clamp_t(u8, MLX5_CAP_GEN(mdev, num_lag_ports), 1, MLX5_MAX_PORTS);166}167 168static inline u16 mlx5_min_rx_wqes(int wq_type, u32 wq_size)169{170 switch (wq_type) {171 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:172 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW,173 wq_size / 2);174 default:175 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES,176 wq_size / 2);177 }178}179 180/* Use this function to get max num channels (rxqs/txqs) only to create netdev */181static inline int mlx5e_get_max_num_channels(struct mlx5_core_dev *mdev)182{183 return is_kdump_kernel() ?184 MLX5E_MIN_NUM_CHANNELS :185 min3(mlx5_comp_vectors_max(mdev), (u32)MLX5E_MAX_NUM_CHANNELS,186 (u32)(1 << MLX5_CAP_GEN(mdev, log_max_rqt_size)));187}188 189/* The maximum WQE size can be retrieved by max_wqe_sz_sq in190 * bytes units. Driver hardens the limitation to 1KB (16191 * WQEBBs), unless firmware capability is stricter.192 */193static inline u8 mlx5e_get_max_sq_wqebbs(struct mlx5_core_dev *mdev)194{195 BUILD_BUG_ON(MLX5_SEND_WQE_MAX_WQEBBS > U8_MAX);196 197 return (u8)min_t(u16, MLX5_SEND_WQE_MAX_WQEBBS,198 MLX5_CAP_GEN(mdev, max_wqe_sz_sq) / MLX5_SEND_WQE_BB);199}200 201static inline u8 mlx5e_get_max_sq_aligned_wqebbs(struct mlx5_core_dev *mdev)202{203/* The return value will be multiplied by MLX5_SEND_WQEBB_NUM_DS.204 * Since max_sq_wqebbs may be up to MLX5_SEND_WQE_MAX_WQEBBS == 16,205 * see mlx5e_get_max_sq_wqebbs(), the multiplication (16 * 4 == 64)206 * overflows the 6-bit DS field of Ctrl Segment. Use a bound lower207 * than MLX5_SEND_WQE_MAX_WQEBBS to let a full-session WQE be208 * cache-aligned.209 */210 u8 wqebbs = mlx5e_get_max_sq_wqebbs(mdev);211 212 wqebbs = min_t(u8, wqebbs, MLX5_SEND_WQE_MAX_WQEBBS - 1);213#if L1_CACHE_BYTES >= 128214 wqebbs = ALIGN_DOWN(wqebbs, 2);215#endif216 return wqebbs;217}218 219struct mlx5e_tx_wqe {220 struct mlx5_wqe_ctrl_seg ctrl;221 struct mlx5_wqe_eth_seg eth;222 struct mlx5_wqe_data_seg data[];223};224 225struct mlx5e_rx_wqe_ll {226 struct mlx5_wqe_srq_next_seg next;227 struct mlx5_wqe_data_seg data[];228};229 230struct mlx5e_rx_wqe_cyc {231 DECLARE_FLEX_ARRAY(struct mlx5_wqe_data_seg, data);232};233 234struct mlx5e_umr_wqe {235 struct mlx5_wqe_ctrl_seg ctrl;236 struct mlx5_wqe_umr_ctrl_seg uctrl;237 struct mlx5_mkey_seg mkc;238 union {239 DECLARE_FLEX_ARRAY(struct mlx5_mtt, inline_mtts);240 DECLARE_FLEX_ARRAY(struct mlx5_klm, inline_klms);241 DECLARE_FLEX_ARRAY(struct mlx5_ksm, inline_ksms);242 };243};244 245enum mlx5e_priv_flag {246 MLX5E_PFLAG_RX_CQE_BASED_MODER,247 MLX5E_PFLAG_TX_CQE_BASED_MODER,248 MLX5E_PFLAG_RX_CQE_COMPRESS,249 MLX5E_PFLAG_RX_STRIDING_RQ,250 MLX5E_PFLAG_RX_NO_CSUM_COMPLETE,251 MLX5E_PFLAG_XDP_TX_MPWQE,252 MLX5E_PFLAG_SKB_TX_MPWQE,253 MLX5E_PFLAG_TX_PORT_TS,254 MLX5E_NUM_PFLAGS, /* Keep last */255};256 257#define MLX5E_SET_PFLAG(params, pflag, enable) \258 do { \259 if (enable) \260 (params)->pflags |= BIT(pflag); \261 else \262 (params)->pflags &= ~(BIT(pflag)); \263 } while (0)264 265#define MLX5E_GET_PFLAG(params, pflag) (!!((params)->pflags & (BIT(pflag))))266 267enum packet_merge {268 MLX5E_PACKET_MERGE_NONE,269 MLX5E_PACKET_MERGE_LRO,270 MLX5E_PACKET_MERGE_SHAMPO,271};272 273struct mlx5e_packet_merge_param {274 enum packet_merge type;275 u32 timeout;276 struct {277 u8 match_criteria_type;278 u8 alignment_granularity;279 } shampo;280};281 282struct mlx5e_params {283 u8 log_sq_size;284 u8 rq_wq_type;285 u8 log_rq_mtu_frames;286 u16 num_channels;287 struct {288 u16 mode;289 u8 num_tc;290 struct netdev_tc_txq tc_to_txq[TC_MAX_QUEUE];291 struct {292 u64 max_rate[TC_MAX_QUEUE];293 u32 hw_id[TC_MAX_QUEUE];294 } channel;295 } mqprio;296 bool rx_cqe_compress_def;297 struct dim_cq_moder rx_cq_moderation;298 struct dim_cq_moder tx_cq_moderation;299 struct mlx5e_packet_merge_param packet_merge;300 u8 tx_min_inline_mode;301 bool vlan_strip_disable;302 bool scatter_fcs_en;303 bool rx_dim_enabled;304 bool tx_dim_enabled;305 bool rx_moder_use_cqe_mode;306 bool tx_moder_use_cqe_mode;307 u32 pflags;308 struct bpf_prog *xdp_prog;309 struct mlx5e_xsk *xsk;310 unsigned int sw_mtu;311 int hard_mtu;312 bool ptp_rx;313 __be32 terminate_lkey_be;314};315 316static inline u8 mlx5e_get_dcb_num_tc(struct mlx5e_params *params)317{318 return params->mqprio.mode == TC_MQPRIO_MODE_DCB ?319 params->mqprio.num_tc : 1;320}321 322/* Keep this enum consistent with the corresponding strings array323 * declared in en/reporter_rx.c324 */325enum {326 MLX5E_RQ_STATE_ENABLED = 0,327 MLX5E_RQ_STATE_RECOVERING,328 MLX5E_RQ_STATE_DIM,329 MLX5E_RQ_STATE_NO_CSUM_COMPLETE,330 MLX5E_RQ_STATE_CSUM_FULL, /* cqe_csum_full hw bit is set */331 MLX5E_RQ_STATE_MINI_CQE_HW_STRIDX, /* set when mini_cqe_resp_stride_index cap is used */332 MLX5E_RQ_STATE_SHAMPO, /* set when SHAMPO cap is used */333 MLX5E_RQ_STATE_MINI_CQE_ENHANCED, /* set when enhanced mini_cqe_cap is used */334 MLX5E_RQ_STATE_XSK, /* set to indicate an xsk rq */335 MLX5E_NUM_RQ_STATES, /* Must be kept last */336};337 338struct mlx5e_cq {339 /* data path - accessed per cqe */340 struct mlx5_cqwq wq;341 342 /* data path - accessed per napi poll */343 u16 event_ctr;344 struct napi_struct *napi;345 struct mlx5_core_cq mcq;346 struct mlx5e_ch_stats *ch_stats;347 348 /* control */349 struct net_device *netdev;350 struct mlx5_core_dev *mdev;351 struct workqueue_struct *workqueue;352 struct mlx5_wq_ctrl wq_ctrl;353} ____cacheline_aligned_in_smp;354 355struct mlx5e_cq_decomp {356 /* cqe decompression */357 struct mlx5_cqe64 title;358 struct mlx5_mini_cqe8 mini_arr[MLX5_MINI_CQE_ARRAY_SIZE];359 u8 mini_arr_idx;360 u16 left;361 u16 wqe_counter;362 bool last_cqe_title;363} ____cacheline_aligned_in_smp;364 365enum mlx5e_dma_map_type {366 MLX5E_DMA_MAP_SINGLE,367 MLX5E_DMA_MAP_PAGE368};369 370struct mlx5e_sq_dma {371 dma_addr_t addr;372 u32 size;373 enum mlx5e_dma_map_type type;374};375 376/* Keep this enum consistent with with the corresponding strings array377 * declared in en/reporter_tx.c378 */379enum {380 MLX5E_SQ_STATE_ENABLED = 0,381 MLX5E_SQ_STATE_MPWQE,382 MLX5E_SQ_STATE_RECOVERING,383 MLX5E_SQ_STATE_IPSEC,384 MLX5E_SQ_STATE_DIM,385 MLX5E_SQ_STATE_VLAN_NEED_L2_INLINE,386 MLX5E_SQ_STATE_PENDING_XSK_TX,387 MLX5E_SQ_STATE_PENDING_TLS_RX_RESYNC,388 MLX5E_SQ_STATE_XDP_MULTIBUF,389 MLX5E_NUM_SQ_STATES, /* Must be kept last */390};391 392struct mlx5e_tx_mpwqe {393 /* Current MPWQE session */394 struct mlx5e_tx_wqe *wqe;395 u32 bytes_count;396 u8 ds_count;397 u8 pkt_count;398 u8 inline_on;399};400 401struct mlx5e_skb_fifo {402 struct sk_buff **fifo;403 u16 *pc;404 u16 *cc;405 u16 mask;406};407 408struct mlx5e_ptpsq;409 410struct mlx5e_txqsq {411 /* data path */412 413 /* dirtied @completion */414 u16 cc;415 u16 skb_fifo_cc;416 u32 dma_fifo_cc;417 struct dim *dim; /* Adaptive Moderation */418 419 /* dirtied @xmit */420 u16 pc ____cacheline_aligned_in_smp;421 u16 skb_fifo_pc;422 u32 dma_fifo_pc;423 struct mlx5e_tx_mpwqe mpwqe;424 425 struct mlx5e_cq cq;426 427 /* read only */428 struct mlx5_wq_cyc wq;429 u32 dma_fifo_mask;430 struct mlx5e_sq_stats *stats;431 struct {432 struct mlx5e_sq_dma *dma_fifo;433 struct mlx5e_skb_fifo skb_fifo;434 struct mlx5e_tx_wqe_info *wqe_info;435 } db;436 void __iomem *uar_map;437 struct netdev_queue *txq;438 u32 sqn;439 u16 stop_room;440 u8 max_sq_mpw_wqebbs;441 u8 min_inline_mode;442 struct device *pdev;443 __be32 mkey_be;444 unsigned long state;445 unsigned int hw_mtu;446 struct mlx5_clock *clock;447 struct net_device *netdev;448 struct mlx5_core_dev *mdev;449 struct mlx5e_channel *channel;450 struct mlx5e_priv *priv;451 452 /* control path */453 struct mlx5_wq_ctrl wq_ctrl;454 int ch_ix;455 int txq_ix;456 u32 rate_limit;457 struct work_struct recover_work;458 struct mlx5e_ptpsq *ptpsq;459 cqe_ts_to_ns ptp_cyc2time;460} ____cacheline_aligned_in_smp;461 462struct mlx5e_xdp_info_fifo {463 union mlx5e_xdp_info *xi;464 u32 *cc;465 u32 *pc;466 u32 mask;467};468 469struct mlx5e_xdpsq;470struct mlx5e_xmit_data;471struct xsk_tx_metadata;472typedef int (*mlx5e_fp_xmit_xdp_frame_check)(struct mlx5e_xdpsq *);473typedef bool (*mlx5e_fp_xmit_xdp_frame)(struct mlx5e_xdpsq *,474 struct mlx5e_xmit_data *,475 int,476 struct xsk_tx_metadata *);477 478struct mlx5e_xdpsq {479 /* data path */480 481 /* dirtied @completion */482 u32 xdpi_fifo_cc;483 u16 cc;484 485 /* dirtied @xmit */486 u32 xdpi_fifo_pc ____cacheline_aligned_in_smp;487 u16 pc;488 struct mlx5_wqe_ctrl_seg *doorbell_cseg;489 struct mlx5e_tx_mpwqe mpwqe;490 491 struct mlx5e_cq cq;492 493 /* read only */494 struct xsk_buff_pool *xsk_pool;495 struct mlx5_wq_cyc wq;496 struct mlx5e_xdpsq_stats *stats;497 mlx5e_fp_xmit_xdp_frame_check xmit_xdp_frame_check;498 mlx5e_fp_xmit_xdp_frame xmit_xdp_frame;499 struct {500 struct mlx5e_xdp_wqe_info *wqe_info;501 struct mlx5e_xdp_info_fifo xdpi_fifo;502 } db;503 void __iomem *uar_map;504 u32 sqn;505 struct device *pdev;506 __be32 mkey_be;507 u16 stop_room;508 u8 max_sq_mpw_wqebbs;509 u8 min_inline_mode;510 unsigned long state;511 unsigned int hw_mtu;512 513 /* control path */514 struct mlx5_wq_ctrl wq_ctrl;515 struct mlx5e_channel *channel;516} ____cacheline_aligned_in_smp;517 518struct mlx5e_ktls_resync_resp;519 520struct mlx5e_icosq {521 /* data path */522 u16 cc;523 u16 pc;524 525 struct mlx5_wqe_ctrl_seg *doorbell_cseg;526 struct mlx5e_cq cq;527 528 /* write@xmit, read@completion */529 struct {530 struct mlx5e_icosq_wqe_info *wqe_info;531 } db;532 533 /* read only */534 struct mlx5_wq_cyc wq;535 void __iomem *uar_map;536 u32 sqn;537 u16 reserved_room;538 unsigned long state;539 struct mlx5e_ktls_resync_resp *ktls_resync;540 541 /* control path */542 struct mlx5_wq_ctrl wq_ctrl;543 struct mlx5e_channel *channel;544 545 struct work_struct recover_work;546} ____cacheline_aligned_in_smp;547 548struct mlx5e_frag_page {549 struct page *page;550 u16 frags;551};552 553enum mlx5e_wqe_frag_flag {554 MLX5E_WQE_FRAG_LAST_IN_PAGE,555 MLX5E_WQE_FRAG_SKIP_RELEASE,556};557 558struct mlx5e_wqe_frag_info {559 union {560 struct mlx5e_frag_page *frag_page;561 struct xdp_buff **xskp;562 };563 u32 offset;564 u8 flags;565};566 567union mlx5e_alloc_units {568 DECLARE_FLEX_ARRAY(struct mlx5e_frag_page, frag_pages);569 DECLARE_FLEX_ARRAY(struct page *, pages);570 DECLARE_FLEX_ARRAY(struct xdp_buff *, xsk_buffs);571};572 573struct mlx5e_mpw_info {574 u16 consumed_strides;575 DECLARE_BITMAP(skip_release_bitmap, MLX5_MPWRQ_MAX_PAGES_PER_WQE);576 struct mlx5e_frag_page linear_page;577 union mlx5e_alloc_units alloc_units;578};579 580#define MLX5E_MAX_RX_FRAGS 4581 582struct mlx5e_rq;583typedef void (*mlx5e_fp_handle_rx_cqe)(struct mlx5e_rq*, struct mlx5_cqe64*);584typedef struct sk_buff *585(*mlx5e_fp_skb_from_cqe_mpwrq)(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,586 struct mlx5_cqe64 *cqe, u16 cqe_bcnt,587 u32 head_offset, u32 page_idx);588typedef struct sk_buff *589(*mlx5e_fp_skb_from_cqe)(struct mlx5e_rq *rq, struct mlx5e_wqe_frag_info *wi,590 struct mlx5_cqe64 *cqe, u32 cqe_bcnt);591typedef bool (*mlx5e_fp_post_rx_wqes)(struct mlx5e_rq *rq);592typedef void (*mlx5e_fp_dealloc_wqe)(struct mlx5e_rq*, u16);593typedef void (*mlx5e_fp_shampo_dealloc_hd)(struct mlx5e_rq*, u16, u16, bool);594 595int mlx5e_rq_set_handlers(struct mlx5e_rq *rq, struct mlx5e_params *params, bool xsk);596void mlx5e_rq_set_trap_handlers(struct mlx5e_rq *rq, struct mlx5e_params *params);597 598enum mlx5e_rq_flag {599 MLX5E_RQ_FLAG_XDP_XMIT,600 MLX5E_RQ_FLAG_XDP_REDIRECT,601};602 603struct mlx5e_rq_frag_info {604 int frag_size;605 int frag_stride;606};607 608struct mlx5e_rq_frags_info {609 struct mlx5e_rq_frag_info arr[MLX5E_MAX_RX_FRAGS];610 u8 num_frags;611 u8 log_num_frags;612 u16 wqe_bulk;613 u16 refill_unit;614 u8 wqe_index_mask;615};616 617struct mlx5e_dma_info {618 dma_addr_t addr;619 union {620 struct mlx5e_frag_page *frag_page;621 struct page *page;622 };623};624 625struct mlx5e_shampo_hd {626 u32 mkey;627 struct mlx5e_dma_info *info;628 struct mlx5e_frag_page *pages;629 u16 curr_page_index;630 u32 hd_per_wq;631 u16 hd_per_wqe;632 unsigned long *bitmap;633 u16 pi;634 u16 ci;635 __be32 key;636 u64 last_addr;637};638 639struct mlx5e_hw_gro_data {640 struct sk_buff *skb;641 struct flow_keys fk;642 int second_ip_id;643};644 645enum mlx5e_mpwrq_umr_mode {646 MLX5E_MPWRQ_UMR_MODE_ALIGNED,647 MLX5E_MPWRQ_UMR_MODE_UNALIGNED,648 MLX5E_MPWRQ_UMR_MODE_OVERSIZED,649 MLX5E_MPWRQ_UMR_MODE_TRIPLE,650};651 652struct mlx5e_rq {653 /* data path */654 union {655 struct {656 struct mlx5_wq_cyc wq;657 struct mlx5e_wqe_frag_info *frags;658 union mlx5e_alloc_units *alloc_units;659 struct mlx5e_rq_frags_info info;660 mlx5e_fp_skb_from_cqe skb_from_cqe;661 } wqe;662 struct {663 struct mlx5_wq_ll wq;664 struct mlx5e_umr_wqe umr_wqe;665 struct mlx5e_mpw_info *info;666 mlx5e_fp_skb_from_cqe_mpwrq skb_from_cqe_mpwrq;667 __be32 umr_mkey_be;668 u16 num_strides;669 u16 actual_wq_head;670 u8 log_stride_sz;671 u8 umr_in_progress;672 u8 umr_last_bulk;673 u8 umr_completed;674 u8 min_wqe_bulk;675 u8 page_shift;676 u8 pages_per_wqe;677 u8 umr_wqebbs;678 u8 mtts_per_wqe;679 u8 umr_mode;680 struct mlx5e_shampo_hd *shampo;681 } mpwqe;682 };683 struct {684 u16 headroom;685 u32 frame0_sz;686 u8 map_dir; /* dma map direction */687 } buff;688 689 struct device *pdev;690 struct net_device *netdev;691 struct mlx5e_rq_stats *stats;692 struct mlx5e_cq cq;693 struct mlx5e_cq_decomp cqd;694 struct hwtstamp_config *tstamp;695 struct mlx5_clock *clock;696 struct mlx5e_icosq *icosq;697 struct mlx5e_priv *priv;698 699 struct mlx5e_hw_gro_data *hw_gro_data;700 701 mlx5e_fp_handle_rx_cqe handle_rx_cqe;702 mlx5e_fp_post_rx_wqes post_wqes;703 mlx5e_fp_dealloc_wqe dealloc_wqe;704 705 unsigned long state;706 int ix;707 unsigned int hw_mtu;708 709 struct dim *dim; /* Dynamic Interrupt Moderation */710 711 /* XDP */712 struct bpf_prog __rcu *xdp_prog;713 struct mlx5e_xdpsq *xdpsq;714 DECLARE_BITMAP(flags, 8);715 struct page_pool *page_pool;716 717 /* AF_XDP zero-copy */718 struct xsk_buff_pool *xsk_pool;719 720 struct work_struct recover_work;721 722 /* control */723 struct mlx5_wq_ctrl wq_ctrl;724 __be32 mkey_be;725 u8 wq_type;726 u32 rqn;727 struct mlx5_core_dev *mdev;728 struct mlx5e_channel *channel;729 struct mlx5e_dma_info wqe_overflow;730 731 /* XDP read-mostly */732 struct xdp_rxq_info xdp_rxq;733 cqe_ts_to_ns ptp_cyc2time;734} ____cacheline_aligned_in_smp;735 736enum mlx5e_channel_state {737 MLX5E_CHANNEL_STATE_XSK,738 MLX5E_CHANNEL_NUM_STATES739};740 741struct mlx5e_channel {742 /* data path */743 struct mlx5e_rq rq;744 struct mlx5e_xdpsq rq_xdpsq;745 struct mlx5e_txqsq sq[MLX5_MAX_NUM_TC];746 struct mlx5e_icosq icosq; /* internal control operations */747 struct mlx5e_txqsq __rcu * __rcu *qos_sqs;748 bool xdp;749 struct napi_struct napi;750 struct device *pdev;751 struct net_device *netdev;752 __be32 mkey_be;753 u16 qos_sqs_size;754 u8 num_tc;755 u8 lag_port;756 757 /* XDP_REDIRECT */758 struct mlx5e_xdpsq xdpsq;759 760 /* AF_XDP zero-copy */761 struct mlx5e_rq xskrq;762 struct mlx5e_xdpsq xsksq;763 764 /* Async ICOSQ */765 struct mlx5e_icosq async_icosq;766 /* async_icosq can be accessed from any CPU - the spinlock protects it. */767 spinlock_t async_icosq_lock;768 769 /* data path - accessed per napi poll */770 const struct cpumask *aff_mask;771 struct mlx5e_ch_stats *stats;772 773 /* control */774 struct mlx5e_priv *priv;775 struct mlx5_core_dev *mdev;776 struct hwtstamp_config *tstamp;777 DECLARE_BITMAP(state, MLX5E_CHANNEL_NUM_STATES);778 int ix;779 int vec_ix;780 int sd_ix;781 int cpu;782 /* Sync between icosq recovery and XSK enable/disable. */783 struct mutex icosq_recovery_lock;784 785 /* coalescing configuration */786 struct dim_cq_moder rx_cq_moder;787 struct dim_cq_moder tx_cq_moder;788};789 790struct mlx5e_ptp;791 792struct mlx5e_channels {793 struct mlx5e_channel **c;794 struct mlx5e_ptp *ptp;795 unsigned int num;796 struct mlx5e_params params;797};798 799struct mlx5e_channel_stats {800 struct mlx5e_ch_stats ch;801 struct mlx5e_sq_stats sq[MLX5_MAX_NUM_TC];802 struct mlx5e_rq_stats rq;803 struct mlx5e_rq_stats xskrq;804 struct mlx5e_xdpsq_stats rq_xdpsq;805 struct mlx5e_xdpsq_stats xdpsq;806 struct mlx5e_xdpsq_stats xsksq;807} ____cacheline_aligned_in_smp;808 809struct mlx5e_ptp_stats {810 struct mlx5e_ch_stats ch;811 struct mlx5e_sq_stats sq[MLX5_MAX_NUM_TC];812 struct mlx5e_ptp_cq_stats cq[MLX5_MAX_NUM_TC];813 struct mlx5e_rq_stats rq;814} ____cacheline_aligned_in_smp;815 816enum {817 MLX5E_STATE_OPENED,818 MLX5E_STATE_DESTROYING,819 MLX5E_STATE_XDP_TX_ENABLED,820 MLX5E_STATE_XDP_ACTIVE,821 MLX5E_STATE_CHANNELS_ACTIVE,822};823 824struct mlx5e_modify_sq_param {825 int curr_state;826 int next_state;827 int rl_update;828 int rl_index;829 bool qos_update;830 u16 qos_queue_group_id;831};832 833#if IS_ENABLED(CONFIG_PCI_HYPERV_INTERFACE)834struct mlx5e_hv_vhca_stats_agent {835 struct mlx5_hv_vhca_agent *agent;836 struct delayed_work work;837 u16 delay;838 void *buf;839};840#endif841 842struct mlx5e_xsk {843 /* XSK buffer pools are stored separately from channels,844 * because we don't want to lose them when channels are845 * recreated. The kernel also stores buffer pool, but it doesn't846 * distinguish between zero-copy and non-zero-copy UMEMs, so847 * rely on our mechanism.848 */849 struct xsk_buff_pool **pools;850 u16 refcnt;851 bool ever_used;852};853 854/* Temporary storage for variables that are allocated when struct mlx5e_priv is855 * initialized, and used where we can't allocate them because that functions856 * must not fail. Use with care and make sure the same variable is not used857 * simultaneously by multiple users.858 */859struct mlx5e_scratchpad {860 cpumask_var_t cpumask;861};862 863struct mlx5e_trap;864struct mlx5e_htb;865 866struct mlx5e_priv {867 /* priv data path fields - start */868 struct mlx5e_selq selq;869 struct mlx5e_txqsq **txq2sq;870 struct mlx5e_sq_stats **txq2sq_stats;871 872#ifdef CONFIG_MLX5_CORE_EN_DCB873 struct mlx5e_dcbx_dp dcbx_dp;874#endif875 /* priv data path fields - end */876 877 unsigned long state;878 struct mutex state_lock; /* Protects Interface state */879 struct mlx5e_rq drop_rq;880 881 struct mlx5e_channels channels;882 struct mlx5e_rx_res *rx_res;883 u32 *tx_rates;884 885 struct mlx5e_flow_steering *fs;886 887 struct workqueue_struct *wq;888 struct work_struct update_carrier_work;889 struct work_struct set_rx_mode_work;890 struct work_struct tx_timeout_work;891 struct work_struct update_stats_work;892 struct work_struct monitor_counters_work;893 struct mlx5_nb monitor_counters_nb;894 895 struct mlx5_core_dev *mdev;896 struct net_device *netdev;897 struct mlx5e_trap *en_trap;898 struct mlx5e_stats stats;899 struct mlx5e_channel_stats **channel_stats;900 struct mlx5e_channel_stats trap_stats;901 struct mlx5e_ptp_stats ptp_stats;902 struct mlx5e_sq_stats **htb_qos_sq_stats;903 u16 htb_max_qos_sqs;904 u16 stats_nch;905 u16 max_nch;906 u8 max_opened_tc;907 bool tx_ptp_opened;908 bool rx_ptp_opened;909 struct hwtstamp_config tstamp;910 u16 q_counter[MLX5_SD_MAX_GROUP_SZ];911 u16 drop_rq_q_counter;912 struct notifier_block events_nb;913 struct notifier_block blocking_events_nb;914 915 struct udp_tunnel_nic_info nic_info;916#ifdef CONFIG_MLX5_CORE_EN_DCB917 struct mlx5e_dcbx dcbx;918#endif919 920 const struct mlx5e_profile *profile;921 void *ppriv;922#ifdef CONFIG_MLX5_MACSEC923 struct mlx5e_macsec *macsec;924#endif925#ifdef CONFIG_MLX5_EN_IPSEC926 struct mlx5e_ipsec *ipsec;927#endif928#ifdef CONFIG_MLX5_EN_TLS929 struct mlx5e_tls *tls;930#endif931 struct devlink_health_reporter *tx_reporter;932 struct devlink_health_reporter *rx_reporter;933 struct mlx5e_xsk xsk;934#if IS_ENABLED(CONFIG_PCI_HYPERV_INTERFACE)935 struct mlx5e_hv_vhca_stats_agent stats_agent;936#endif937 struct mlx5e_scratchpad scratchpad;938 struct mlx5e_htb *htb;939 struct mlx5e_mqprio_rl *mqprio_rl;940 struct dentry *dfs_root;941 struct mlx5_devcom_comp_dev *devcom;942};943 944struct mlx5e_dev {945 struct mlx5e_priv *priv;946 struct devlink_port dl_port;947};948 949struct mlx5e_rx_handlers {950 mlx5e_fp_handle_rx_cqe handle_rx_cqe;951 mlx5e_fp_handle_rx_cqe handle_rx_cqe_mpwqe;952 mlx5e_fp_handle_rx_cqe handle_rx_cqe_mpwqe_shampo;953};954 955extern const struct mlx5e_rx_handlers mlx5e_rx_handlers_nic;956 957enum mlx5e_profile_feature {958 MLX5E_PROFILE_FEATURE_PTP_RX,959 MLX5E_PROFILE_FEATURE_PTP_TX,960 MLX5E_PROFILE_FEATURE_QOS_HTB,961 MLX5E_PROFILE_FEATURE_FS_VLAN,962 MLX5E_PROFILE_FEATURE_FS_TC,963};964 965struct mlx5e_profile {966 int (*init)(struct mlx5_core_dev *mdev,967 struct net_device *netdev);968 void (*cleanup)(struct mlx5e_priv *priv);969 int (*init_rx)(struct mlx5e_priv *priv);970 void (*cleanup_rx)(struct mlx5e_priv *priv);971 int (*init_tx)(struct mlx5e_priv *priv);972 void (*cleanup_tx)(struct mlx5e_priv *priv);973 void (*enable)(struct mlx5e_priv *priv);974 void (*disable)(struct mlx5e_priv *priv);975 int (*update_rx)(struct mlx5e_priv *priv);976 void (*update_stats)(struct mlx5e_priv *priv);977 void (*update_carrier)(struct mlx5e_priv *priv);978 int (*max_nch_limit)(struct mlx5_core_dev *mdev);979 u32 (*get_tisn)(struct mlx5_core_dev *mdev, struct mlx5e_priv *priv,980 u8 lag_port, u8 tc);981 unsigned int (*stats_grps_num)(struct mlx5e_priv *priv);982 mlx5e_stats_grp_t *stats_grps;983 const struct mlx5e_rx_handlers *rx_handlers;984 int max_tc;985 u32 features;986};987 988u32 mlx5e_profile_get_tisn(struct mlx5_core_dev *mdev,989 struct mlx5e_priv *priv,990 const struct mlx5e_profile *profile,991 u8 lag_port, u8 tc);992 993#define mlx5e_profile_feature_cap(profile, feature) \994 ((profile)->features & BIT(MLX5E_PROFILE_FEATURE_##feature))995 996void mlx5e_build_ptys2ethtool_map(void);997 998bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev, u8 page_shift,999 enum mlx5e_mpwrq_umr_mode umr_mode);1000 1001void mlx5e_shampo_fill_umr(struct mlx5e_rq *rq, int len);1002void mlx5e_shampo_dealloc_hd(struct mlx5e_rq *rq);1003void mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats);1004void mlx5e_fold_sw_stats64(struct mlx5e_priv *priv, struct rtnl_link_stats64 *s);1005 1006int mlx5e_self_test_num(struct mlx5e_priv *priv);1007int mlx5e_self_test_fill_strings(struct mlx5e_priv *priv, u8 *data);1008void mlx5e_self_test(struct net_device *ndev, struct ethtool_test *etest,1009 u64 *buf);1010void mlx5e_set_rx_mode_work(struct work_struct *work);1011 1012int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr);1013int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr);1014int mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool val, bool rx_filter);1015 1016int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto,1017 u16 vid);1018int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __always_unused __be16 proto,1019 u16 vid);1020void mlx5e_timestamp_init(struct mlx5e_priv *priv);1021 1022struct mlx5e_xsk_param;1023 1024struct mlx5e_rq_param;1025int mlx5e_open_rq(struct mlx5e_params *params, struct mlx5e_rq_param *param,1026 struct mlx5e_xsk_param *xsk, int node, u16 q_counter,1027 struct mlx5e_rq *rq);1028#define MLX5E_RQ_WQES_TIMEOUT 20000 /* msecs */1029int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq, int wait_time);1030void mlx5e_close_rq(struct mlx5e_rq *rq);1031int mlx5e_create_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param, u16 q_counter);1032void mlx5e_destroy_rq(struct mlx5e_rq *rq);1033 1034bool mlx5e_reset_rx_moderation(struct dim_cq_moder *cq_moder, u8 cq_period_mode,1035 bool dim_enabled);1036bool mlx5e_reset_rx_channels_moderation(struct mlx5e_channels *chs, u8 cq_period_mode,1037 bool dim_enabled, bool keep_dim_state);1038 1039struct mlx5e_sq_param;1040int mlx5e_open_xdpsq(struct mlx5e_channel *c, struct mlx5e_params *params,1041 struct mlx5e_sq_param *param, struct xsk_buff_pool *xsk_pool,1042 struct mlx5e_xdpsq *sq, bool is_redirect);1043void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq);1044 1045struct mlx5e_create_cq_param {1046 struct net_device *netdev;1047 struct workqueue_struct *wq;1048 struct napi_struct *napi;1049 struct mlx5e_ch_stats *ch_stats;1050 int node;1051 int ix;1052};1053 1054struct mlx5e_cq_param;1055int mlx5e_open_cq(struct mlx5_core_dev *mdev, struct dim_cq_moder moder,1056 struct mlx5e_cq_param *param, struct mlx5e_create_cq_param *ccp,1057 struct mlx5e_cq *cq);1058void mlx5e_close_cq(struct mlx5e_cq *cq);1059int mlx5e_modify_cq_period_mode(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq,1060 u8 cq_period_mode);1061int mlx5e_modify_cq_moderation(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq,1062 u16 cq_period, u16 cq_max_count, u8 cq_period_mode);1063 1064int mlx5e_open_locked(struct net_device *netdev);1065int mlx5e_close_locked(struct net_device *netdev);1066 1067void mlx5e_trigger_napi_icosq(struct mlx5e_channel *c);1068void mlx5e_trigger_napi_sched(struct napi_struct *napi);1069 1070int mlx5e_open_channels(struct mlx5e_priv *priv,1071 struct mlx5e_channels *chs);1072void mlx5e_close_channels(struct mlx5e_channels *chs);1073 1074/* Function pointer to be used to modify HW or kernel settings while1075 * switching channels1076 */1077typedef int (*mlx5e_fp_preactivate)(struct mlx5e_priv *priv, void *context);1078#define MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(fn) \1079int fn##_ctx(struct mlx5e_priv *priv, void *context) \1080{ \1081 return fn(priv); \1082}1083int mlx5e_safe_reopen_channels(struct mlx5e_priv *priv);1084int mlx5e_safe_switch_params(struct mlx5e_priv *priv,1085 struct mlx5e_params *new_params,1086 mlx5e_fp_preactivate preactivate,1087 void *context, bool reset);1088int mlx5e_update_tx_netdev_queues(struct mlx5e_priv *priv);1089int mlx5e_num_channels_changed_ctx(struct mlx5e_priv *priv, void *context);1090int mlx5e_update_tc_and_tx_queues_ctx(struct mlx5e_priv *priv, void *context);1091void mlx5e_activate_priv_channels(struct mlx5e_priv *priv);1092void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv);1093int mlx5e_ptp_rx_manage_fs_ctx(struct mlx5e_priv *priv, void *ctx);1094 1095int mlx5e_flush_rq(struct mlx5e_rq *rq, int curr_state);1096void mlx5e_activate_rq(struct mlx5e_rq *rq);1097void mlx5e_deactivate_rq(struct mlx5e_rq *rq);1098void mlx5e_activate_icosq(struct mlx5e_icosq *icosq);1099void mlx5e_deactivate_icosq(struct mlx5e_icosq *icosq);1100 1101int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,1102 struct mlx5e_modify_sq_param *p);1103int mlx5e_open_txqsq(struct mlx5e_channel *c, u32 tisn, int txq_ix,1104 struct mlx5e_params *params, struct mlx5e_sq_param *param,1105 struct mlx5e_txqsq *sq, int tc, u16 qos_queue_group_id,1106 struct mlx5e_sq_stats *sq_stats);1107void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq);1108void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq);1109void mlx5e_free_txqsq(struct mlx5e_txqsq *sq);1110void mlx5e_tx_disable_queue(struct netdev_queue *txq);1111int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa);1112void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq);1113struct mlx5e_create_sq_param;1114int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,1115 struct mlx5e_sq_param *param,1116 struct mlx5e_create_sq_param *csp,1117 u16 qos_queue_group_id,1118 u32 *sqn);1119void mlx5e_tx_err_cqe_work(struct work_struct *recover_work);1120void mlx5e_close_txqsq(struct mlx5e_txqsq *sq);1121 1122bool mlx5e_reset_tx_moderation(struct dim_cq_moder *cq_moder, u8 cq_period_mode,1123 bool dim_enabled);1124bool mlx5e_reset_tx_channels_moderation(struct mlx5e_channels *chs, u8 cq_period_mode,1125 bool dim_enabled, bool keep_dim_state);1126 1127static inline bool mlx5_tx_swp_supported(struct mlx5_core_dev *mdev)1128{1129 return MLX5_CAP_ETH(mdev, swp) &&1130 MLX5_CAP_ETH(mdev, swp_csum) && MLX5_CAP_ETH(mdev, swp_lso);1131}1132 1133extern const struct ethtool_ops mlx5e_ethtool_ops;1134 1135int mlx5e_create_mkey(struct mlx5_core_dev *mdev, u32 pdn, u32 *mkey);1136int mlx5e_create_mdev_resources(struct mlx5_core_dev *mdev, bool create_tises);1137void mlx5e_destroy_mdev_resources(struct mlx5_core_dev *mdev);1138int mlx5e_refresh_tirs(struct mlx5e_priv *priv, bool enable_uc_lb,1139 bool enable_mc_lb);1140void mlx5e_mkey_set_relaxed_ordering(struct mlx5_core_dev *mdev, void *mkc);1141 1142/* common netdev helpers */1143void mlx5e_create_q_counters(struct mlx5e_priv *priv);1144void mlx5e_destroy_q_counters(struct mlx5e_priv *priv);1145int mlx5e_open_drop_rq(struct mlx5e_priv *priv,1146 struct mlx5e_rq *drop_rq);1147void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq);1148 1149int mlx5e_create_tis(struct mlx5_core_dev *mdev, void *in, u32 *tisn);1150void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn);1151 1152void mlx5e_update_carrier(struct mlx5e_priv *priv);1153int mlx5e_close(struct net_device *netdev);1154int mlx5e_open(struct net_device *netdev);1155 1156void mlx5e_queue_update_stats(struct mlx5e_priv *priv);1157 1158int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv);1159int mlx5e_set_dev_port_mtu_ctx(struct mlx5e_priv *priv, void *context);1160int mlx5e_change_mtu(struct net_device *netdev, int new_mtu,1161 mlx5e_fp_preactivate preactivate);1162void mlx5e_vxlan_set_netdev_info(struct mlx5e_priv *priv);1163 1164/* ethtool helpers */1165void mlx5e_ethtool_get_drvinfo(struct mlx5e_priv *priv,1166 struct ethtool_drvinfo *drvinfo);1167void mlx5e_ethtool_get_strings(struct mlx5e_priv *priv,1168 u32 stringset, u8 *data);1169int mlx5e_ethtool_get_sset_count(struct mlx5e_priv *priv, int sset);1170void mlx5e_ethtool_get_ethtool_stats(struct mlx5e_priv *priv,1171 struct ethtool_stats *stats, u64 *data);1172void mlx5e_ethtool_get_ringparam(struct mlx5e_priv *priv,1173 struct ethtool_ringparam *param,1174 struct kernel_ethtool_ringparam *kernel_param);1175int mlx5e_ethtool_set_ringparam(struct mlx5e_priv *priv,1176 struct ethtool_ringparam *param,1177 struct netlink_ext_ack *extack);1178void mlx5e_ethtool_get_channels(struct mlx5e_priv *priv,1179 struct ethtool_channels *ch);1180int mlx5e_ethtool_set_channels(struct mlx5e_priv *priv,1181 struct ethtool_channels *ch);1182int mlx5e_ethtool_get_coalesce(struct mlx5e_priv *priv,1183 struct ethtool_coalesce *coal,1184 struct kernel_ethtool_coalesce *kernel_coal,1185 struct netlink_ext_ack *extack);1186int mlx5e_ethtool_set_coalesce(struct mlx5e_priv *priv,1187 struct ethtool_coalesce *coal,1188 struct kernel_ethtool_coalesce *kernel_coal,1189 struct netlink_ext_ack *extack);1190int mlx5e_get_per_queue_coalesce(struct net_device *dev, u32 queue,1191 struct ethtool_coalesce *coal);1192int mlx5e_set_per_queue_coalesce(struct net_device *dev, u32 queue,1193 struct ethtool_coalesce *coal);1194u32 mlx5e_ethtool_get_rxfh_key_size(struct mlx5e_priv *priv);1195u32 mlx5e_ethtool_get_rxfh_indir_size(struct mlx5e_priv *priv);1196int mlx5e_ethtool_get_ts_info(struct mlx5e_priv *priv,1197 struct kernel_ethtool_ts_info *info);1198int mlx5e_ethtool_flash_device(struct mlx5e_priv *priv,1199 struct ethtool_flash *flash);1200 1201/* mlx5e generic netdev management API */1202static inline bool1203mlx5e_tx_mpwqe_supported(struct mlx5_core_dev *mdev)1204{1205 return !is_kdump_kernel() &&1206 MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe);1207}1208 1209int mlx5e_get_pf_num_tirs(struct mlx5_core_dev *mdev);1210int mlx5e_priv_init(struct mlx5e_priv *priv,1211 const struct mlx5e_profile *profile,1212 struct net_device *netdev,1213 struct mlx5_core_dev *mdev);1214void mlx5e_priv_cleanup(struct mlx5e_priv *priv);1215struct net_device *1216mlx5e_create_netdev(struct mlx5_core_dev *mdev, const struct mlx5e_profile *profile);1217int mlx5e_attach_netdev(struct mlx5e_priv *priv);1218void mlx5e_detach_netdev(struct mlx5e_priv *priv);1219void mlx5e_destroy_netdev(struct mlx5e_priv *priv);1220int mlx5e_netdev_change_profile(struct mlx5e_priv *priv,1221 const struct mlx5e_profile *new_profile, void *new_ppriv);1222void mlx5e_netdev_attach_nic_profile(struct mlx5e_priv *priv);1223void mlx5e_set_netdev_mtu_boundaries(struct mlx5e_priv *priv);1224void mlx5e_build_nic_params(struct mlx5e_priv *priv, struct mlx5e_xsk *xsk, u16 mtu);1225 1226void mlx5e_set_xdp_feature(struct net_device *netdev);1227netdev_features_t mlx5e_features_check(struct sk_buff *skb,1228 struct net_device *netdev,1229 netdev_features_t features);1230int mlx5e_set_features(struct net_device *netdev, netdev_features_t features);1231#ifdef CONFIG_MLX5_ESWITCH1232int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac);1233int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate, int max_tx_rate);1234int mlx5e_get_vf_config(struct net_device *dev, int vf, struct ifla_vf_info *ivi);1235int mlx5e_get_vf_stats(struct net_device *dev, int vf, struct ifla_vf_stats *vf_stats);1236#endif1237int mlx5e_create_mkey(struct mlx5_core_dev *mdev, u32 pdn, u32 *mkey);1238#endif /* __MLX5_EN_H__ */1239