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1// SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause2 3/* Gigabit Ethernet driver for Mellanox BlueField SoC4 *5 * Copyright (C) 2020-2021 NVIDIA CORPORATION & AFFILIATES6 */7 8#include <linux/acpi.h>9#include <linux/device.h>10#include <linux/dma-mapping.h>11#include <linux/etherdevice.h>12#include <linux/interrupt.h>13#include <linux/iopoll.h>14#include <linux/module.h>15#include <linux/phy.h>16#include <linux/platform_device.h>17#include <linux/rtnetlink.h>18#include <linux/skbuff.h>19 20#include "mlxbf_gige.h"21#include "mlxbf_gige_regs.h"22 23/* Allocate SKB whose payload pointer aligns with the Bluefield24 * hardware DMA limitation, i.e. DMA operation can't cross25 * a 4KB boundary. A maximum packet size of 2KB is assumed in the26 * alignment formula. The alignment logic overallocates an SKB,27 * and then adjusts the headroom so that the SKB data pointer is28 * naturally aligned to a 2KB boundary.29 */30struct sk_buff *mlxbf_gige_alloc_skb(struct mlxbf_gige *priv,31 unsigned int map_len,32 dma_addr_t *buf_dma,33 enum dma_data_direction dir)34{35 struct sk_buff *skb;36 u64 addr, offset;37 38 /* Overallocate the SKB so that any headroom adjustment (to39 * provide 2KB natural alignment) does not exceed payload area40 */41 skb = netdev_alloc_skb(priv->netdev, MLXBF_GIGE_DEFAULT_BUF_SZ * 2);42 if (!skb)43 return NULL;44 45 /* Adjust the headroom so that skb->data is naturally aligned to46 * a 2KB boundary, which is the maximum packet size supported.47 */48 addr = (long)skb->data;49 offset = (addr + MLXBF_GIGE_DEFAULT_BUF_SZ - 1) &50 ~(MLXBF_GIGE_DEFAULT_BUF_SZ - 1);51 offset -= addr;52 if (offset)53 skb_reserve(skb, offset);54 55 /* Return streaming DMA mapping to caller */56 *buf_dma = dma_map_single(priv->dev, skb->data, map_len, dir);57 if (dma_mapping_error(priv->dev, *buf_dma)) {58 dev_kfree_skb(skb);59 *buf_dma = (dma_addr_t)0;60 return NULL;61 }62 63 return skb;64}65 66static void mlxbf_gige_initial_mac(struct mlxbf_gige *priv)67{68 u8 mac[ETH_ALEN];69 u64 local_mac;70 71 eth_zero_addr(mac);72 mlxbf_gige_get_mac_rx_filter(priv, MLXBF_GIGE_LOCAL_MAC_FILTER_IDX,73 &local_mac);74 u64_to_ether_addr(local_mac, mac);75 76 if (is_valid_ether_addr(mac)) {77 eth_hw_addr_set(priv->netdev, mac);78 } else {79 /* Provide a random MAC if for some reason the device has80 * not been configured with a valid MAC address already.81 */82 eth_hw_addr_random(priv->netdev);83 }84 85 local_mac = ether_addr_to_u64(priv->netdev->dev_addr);86 mlxbf_gige_set_mac_rx_filter(priv, MLXBF_GIGE_LOCAL_MAC_FILTER_IDX,87 local_mac);88}89 90static void mlxbf_gige_cache_stats(struct mlxbf_gige *priv)91{92 struct mlxbf_gige_stats *p;93 94 /* Cache stats that will be cleared by clean port operation */95 p = &priv->stats;96 p->rx_din_dropped_pkts += readq(priv->base +97 MLXBF_GIGE_RX_DIN_DROP_COUNTER);98 p->rx_filter_passed_pkts += readq(priv->base +99 MLXBF_GIGE_RX_PASS_COUNTER_ALL);100 p->rx_filter_discard_pkts += readq(priv->base +101 MLXBF_GIGE_RX_DISC_COUNTER_ALL);102}103 104static int mlxbf_gige_clean_port(struct mlxbf_gige *priv)105{106 u64 control;107 u64 temp;108 int err;109 110 /* Set the CLEAN_PORT_EN bit to trigger SW reset */111 control = readq(priv->base + MLXBF_GIGE_CONTROL);112 control |= MLXBF_GIGE_CONTROL_CLEAN_PORT_EN;113 writeq(control, priv->base + MLXBF_GIGE_CONTROL);114 115 /* Ensure completion of "clean port" write before polling status */116 mb();117 118 err = readq_poll_timeout_atomic(priv->base + MLXBF_GIGE_STATUS, temp,119 (temp & MLXBF_GIGE_STATUS_READY),120 100, 100000);121 122 /* Clear the CLEAN_PORT_EN bit at end of this loop */123 control = readq(priv->base + MLXBF_GIGE_CONTROL);124 control &= ~MLXBF_GIGE_CONTROL_CLEAN_PORT_EN;125 writeq(control, priv->base + MLXBF_GIGE_CONTROL);126 127 return err;128}129 130static int mlxbf_gige_open(struct net_device *netdev)131{132 struct mlxbf_gige *priv = netdev_priv(netdev);133 struct phy_device *phydev = netdev->phydev;134 u64 control;135 u64 int_en;136 int err;137 138 /* Perform general init of GigE block */139 control = readq(priv->base + MLXBF_GIGE_CONTROL);140 control |= MLXBF_GIGE_CONTROL_PORT_EN;141 writeq(control, priv->base + MLXBF_GIGE_CONTROL);142 143 mlxbf_gige_cache_stats(priv);144 err = mlxbf_gige_clean_port(priv);145 if (err)146 return err;147 148 /* Clear driver's valid_polarity to match hardware,149 * since the above call to clean_port() resets the150 * receive polarity used by hardware.151 */152 priv->valid_polarity = 0;153 154 phy_start(phydev);155 156 err = mlxbf_gige_tx_init(priv);157 if (err)158 goto phy_deinit;159 err = mlxbf_gige_rx_init(priv);160 if (err)161 goto tx_deinit;162 163 netif_napi_add(netdev, &priv->napi, mlxbf_gige_poll);164 napi_enable(&priv->napi);165 netif_start_queue(netdev);166 167 err = mlxbf_gige_request_irqs(priv);168 if (err)169 goto napi_deinit;170 171 mlxbf_gige_enable_mac_rx_filter(priv, MLXBF_GIGE_BCAST_MAC_FILTER_IDX);172 mlxbf_gige_enable_mac_rx_filter(priv, MLXBF_GIGE_LOCAL_MAC_FILTER_IDX);173 mlxbf_gige_enable_multicast_rx(priv);174 175 /* Set bits in INT_EN that we care about */176 int_en = MLXBF_GIGE_INT_EN_HW_ACCESS_ERROR |177 MLXBF_GIGE_INT_EN_TX_CHECKSUM_INPUTS |178 MLXBF_GIGE_INT_EN_TX_SMALL_FRAME_SIZE |179 MLXBF_GIGE_INT_EN_TX_PI_CI_EXCEED_WQ_SIZE |180 MLXBF_GIGE_INT_EN_SW_CONFIG_ERROR |181 MLXBF_GIGE_INT_EN_SW_ACCESS_ERROR |182 MLXBF_GIGE_INT_EN_RX_RECEIVE_PACKET;183 184 /* Ensure completion of all initialization before enabling interrupts */185 mb();186 187 writeq(int_en, priv->base + MLXBF_GIGE_INT_EN);188 189 return 0;190 191napi_deinit:192 netif_stop_queue(netdev);193 napi_disable(&priv->napi);194 netif_napi_del(&priv->napi);195 mlxbf_gige_rx_deinit(priv);196 197tx_deinit:198 mlxbf_gige_tx_deinit(priv);199 200phy_deinit:201 phy_stop(phydev);202 return err;203}204 205static int mlxbf_gige_stop(struct net_device *netdev)206{207 struct mlxbf_gige *priv = netdev_priv(netdev);208 209 writeq(0, priv->base + MLXBF_GIGE_INT_EN);210 netif_stop_queue(netdev);211 napi_disable(&priv->napi);212 netif_napi_del(&priv->napi);213 mlxbf_gige_free_irqs(priv);214 215 phy_stop(netdev->phydev);216 217 mlxbf_gige_rx_deinit(priv);218 mlxbf_gige_tx_deinit(priv);219 mlxbf_gige_cache_stats(priv);220 mlxbf_gige_clean_port(priv);221 222 return 0;223}224 225static int mlxbf_gige_eth_ioctl(struct net_device *netdev,226 struct ifreq *ifr, int cmd)227{228 if (!(netif_running(netdev)))229 return -EINVAL;230 231 return phy_mii_ioctl(netdev->phydev, ifr, cmd);232}233 234static void mlxbf_gige_set_rx_mode(struct net_device *netdev)235{236 struct mlxbf_gige *priv = netdev_priv(netdev);237 bool new_promisc_enabled;238 239 new_promisc_enabled = netdev->flags & IFF_PROMISC;240 241 /* Only write to the hardware registers if the new setting242 * of promiscuous mode is different from the current one.243 */244 if (new_promisc_enabled != priv->promisc_enabled) {245 priv->promisc_enabled = new_promisc_enabled;246 247 if (new_promisc_enabled)248 mlxbf_gige_enable_promisc(priv);249 else250 mlxbf_gige_disable_promisc(priv);251 }252}253 254static void mlxbf_gige_get_stats64(struct net_device *netdev,255 struct rtnl_link_stats64 *stats)256{257 struct mlxbf_gige *priv = netdev_priv(netdev);258 259 netdev_stats_to_stats64(stats, &netdev->stats);260 261 stats->rx_length_errors = priv->stats.rx_truncate_errors;262 stats->rx_fifo_errors = priv->stats.rx_din_dropped_pkts +263 readq(priv->base + MLXBF_GIGE_RX_DIN_DROP_COUNTER);264 stats->rx_crc_errors = priv->stats.rx_mac_errors;265 stats->rx_errors = stats->rx_length_errors +266 stats->rx_fifo_errors +267 stats->rx_crc_errors;268 269 stats->tx_fifo_errors = priv->stats.tx_fifo_full;270 stats->tx_errors = stats->tx_fifo_errors;271}272 273static const struct net_device_ops mlxbf_gige_netdev_ops = {274 .ndo_open = mlxbf_gige_open,275 .ndo_stop = mlxbf_gige_stop,276 .ndo_start_xmit = mlxbf_gige_start_xmit,277 .ndo_set_mac_address = eth_mac_addr,278 .ndo_validate_addr = eth_validate_addr,279 .ndo_eth_ioctl = mlxbf_gige_eth_ioctl,280 .ndo_set_rx_mode = mlxbf_gige_set_rx_mode,281 .ndo_get_stats64 = mlxbf_gige_get_stats64,282};283 284static void mlxbf_gige_bf2_adjust_link(struct net_device *netdev)285{286 struct phy_device *phydev = netdev->phydev;287 288 phy_print_status(phydev);289}290 291static void mlxbf_gige_bf3_adjust_link(struct net_device *netdev)292{293 struct mlxbf_gige *priv = netdev_priv(netdev);294 struct phy_device *phydev = netdev->phydev;295 u8 sgmii_mode;296 u16 ipg_size;297 u32 val;298 299 if (phydev->link && phydev->speed != priv->prev_speed) {300 switch (phydev->speed) {301 case 1000:302 ipg_size = MLXBF_GIGE_1G_IPG_SIZE;303 sgmii_mode = MLXBF_GIGE_1G_SGMII_MODE;304 break;305 case 100:306 ipg_size = MLXBF_GIGE_100M_IPG_SIZE;307 sgmii_mode = MLXBF_GIGE_100M_SGMII_MODE;308 break;309 case 10:310 ipg_size = MLXBF_GIGE_10M_IPG_SIZE;311 sgmii_mode = MLXBF_GIGE_10M_SGMII_MODE;312 break;313 default:314 return;315 }316 317 val = readl(priv->plu_base + MLXBF_GIGE_PLU_TX_REG0);318 val &= ~(MLXBF_GIGE_PLU_TX_IPG_SIZE_MASK | MLXBF_GIGE_PLU_TX_SGMII_MODE_MASK);319 val |= FIELD_PREP(MLXBF_GIGE_PLU_TX_IPG_SIZE_MASK, ipg_size);320 val |= FIELD_PREP(MLXBF_GIGE_PLU_TX_SGMII_MODE_MASK, sgmii_mode);321 writel(val, priv->plu_base + MLXBF_GIGE_PLU_TX_REG0);322 323 val = readl(priv->plu_base + MLXBF_GIGE_PLU_RX_REG0);324 val &= ~MLXBF_GIGE_PLU_RX_SGMII_MODE_MASK;325 val |= FIELD_PREP(MLXBF_GIGE_PLU_RX_SGMII_MODE_MASK, sgmii_mode);326 writel(val, priv->plu_base + MLXBF_GIGE_PLU_RX_REG0);327 328 priv->prev_speed = phydev->speed;329 }330 331 phy_print_status(phydev);332}333 334static void mlxbf_gige_bf2_set_phy_link_mode(struct phy_device *phydev)335{336 /* MAC only supports 1000T full duplex mode */337 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_1000baseT_Half_BIT);338 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_100baseT_Full_BIT);339 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_100baseT_Half_BIT);340 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Full_BIT);341 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Half_BIT);342 343 /* Only symmetric pause with flow control enabled is supported so no344 * need to negotiate pause.345 */346 linkmode_clear_bit(ETHTOOL_LINK_MODE_Pause_BIT, phydev->advertising);347 linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, phydev->advertising);348}349 350static void mlxbf_gige_bf3_set_phy_link_mode(struct phy_device *phydev)351{352 /* MAC only supports full duplex mode */353 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_1000baseT_Half_BIT);354 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_100baseT_Half_BIT);355 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Half_BIT);356 357 /* Only symmetric pause with flow control enabled is supported so no358 * need to negotiate pause.359 */360 linkmode_clear_bit(ETHTOOL_LINK_MODE_Pause_BIT, phydev->advertising);361 linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, phydev->advertising);362}363 364static struct mlxbf_gige_link_cfg mlxbf_gige_link_cfgs[] = {365 [MLXBF_GIGE_VERSION_BF2] = {366 .set_phy_link_mode = mlxbf_gige_bf2_set_phy_link_mode,367 .adjust_link = mlxbf_gige_bf2_adjust_link,368 .phy_mode = PHY_INTERFACE_MODE_GMII369 },370 [MLXBF_GIGE_VERSION_BF3] = {371 .set_phy_link_mode = mlxbf_gige_bf3_set_phy_link_mode,372 .adjust_link = mlxbf_gige_bf3_adjust_link,373 .phy_mode = PHY_INTERFACE_MODE_SGMII374 }375};376 377static int mlxbf_gige_probe(struct platform_device *pdev)378{379 struct phy_device *phydev;380 struct net_device *netdev;381 struct mlxbf_gige *priv;382 void __iomem *llu_base;383 void __iomem *plu_base;384 void __iomem *base;385 int addr, phy_irq;386 unsigned int i;387 int err;388 389 base = devm_platform_ioremap_resource(pdev, MLXBF_GIGE_RES_MAC);390 if (IS_ERR(base))391 return PTR_ERR(base);392 393 llu_base = devm_platform_ioremap_resource(pdev, MLXBF_GIGE_RES_LLU);394 if (IS_ERR(llu_base))395 return PTR_ERR(llu_base);396 397 plu_base = devm_platform_ioremap_resource(pdev, MLXBF_GIGE_RES_PLU);398 if (IS_ERR(plu_base))399 return PTR_ERR(plu_base);400 401 netdev = devm_alloc_etherdev(&pdev->dev, sizeof(*priv));402 if (!netdev)403 return -ENOMEM;404 405 SET_NETDEV_DEV(netdev, &pdev->dev);406 netdev->netdev_ops = &mlxbf_gige_netdev_ops;407 netdev->ethtool_ops = &mlxbf_gige_ethtool_ops;408 priv = netdev_priv(netdev);409 priv->netdev = netdev;410 411 platform_set_drvdata(pdev, priv);412 priv->dev = &pdev->dev;413 priv->pdev = pdev;414 415 spin_lock_init(&priv->lock);416 417 priv->hw_version = readq(base + MLXBF_GIGE_VERSION);418 419 /* Attach MDIO device */420 err = mlxbf_gige_mdio_probe(pdev, priv);421 if (err)422 return err;423 424 priv->base = base;425 priv->llu_base = llu_base;426 priv->plu_base = plu_base;427 428 priv->rx_q_entries = MLXBF_GIGE_DEFAULT_RXQ_SZ;429 priv->tx_q_entries = MLXBF_GIGE_DEFAULT_TXQ_SZ;430 431 for (i = 0; i <= MLXBF_GIGE_MAX_FILTER_IDX; i++)432 mlxbf_gige_disable_mac_rx_filter(priv, i);433 mlxbf_gige_disable_multicast_rx(priv);434 mlxbf_gige_disable_promisc(priv);435 436 /* Write initial MAC address to hardware */437 mlxbf_gige_initial_mac(priv);438 439 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));440 if (err) {441 dev_err(&pdev->dev, "DMA configuration failed: 0x%x\n", err);442 goto out;443 }444 445 priv->error_irq = platform_get_irq(pdev, MLXBF_GIGE_ERROR_INTR_IDX);446 priv->rx_irq = platform_get_irq(pdev, MLXBF_GIGE_RECEIVE_PKT_INTR_IDX);447 priv->llu_plu_irq = platform_get_irq(pdev, MLXBF_GIGE_LLU_PLU_INTR_IDX);448 449 phy_irq = acpi_dev_gpio_irq_get_by(ACPI_COMPANION(&pdev->dev), "phy", 0);450 if (phy_irq < 0) {451 dev_err(&pdev->dev, "Error getting PHY irq. Use polling instead");452 phy_irq = PHY_POLL;453 }454 455 phydev = phy_find_first(priv->mdiobus);456 if (!phydev) {457 err = -ENODEV;458 goto out;459 }460 461 addr = phydev->mdio.addr;462 priv->mdiobus->irq[addr] = phy_irq;463 phydev->irq = phy_irq;464 465 err = phy_connect_direct(netdev, phydev,466 mlxbf_gige_link_cfgs[priv->hw_version].adjust_link,467 mlxbf_gige_link_cfgs[priv->hw_version].phy_mode);468 if (err) {469 dev_err(&pdev->dev, "Could not attach to PHY\n");470 goto out;471 }472 473 mlxbf_gige_link_cfgs[priv->hw_version].set_phy_link_mode(phydev);474 475 /* Display information about attached PHY device */476 phy_attached_info(phydev);477 478 err = register_netdev(netdev);479 if (err) {480 dev_err(&pdev->dev, "Failed to register netdev\n");481 phy_disconnect(phydev);482 goto out;483 }484 485 return 0;486 487out:488 mlxbf_gige_mdio_remove(priv);489 return err;490}491 492static void mlxbf_gige_remove(struct platform_device *pdev)493{494 struct mlxbf_gige *priv = platform_get_drvdata(pdev);495 496 unregister_netdev(priv->netdev);497 phy_disconnect(priv->netdev->phydev);498 mlxbf_gige_mdio_remove(priv);499 platform_set_drvdata(pdev, NULL);500}501 502static void mlxbf_gige_shutdown(struct platform_device *pdev)503{504 struct mlxbf_gige *priv = platform_get_drvdata(pdev);505 506 rtnl_lock();507 netif_device_detach(priv->netdev);508 509 if (netif_running(priv->netdev))510 dev_close(priv->netdev);511 512 rtnl_unlock();513}514 515static const struct acpi_device_id __maybe_unused mlxbf_gige_acpi_match[] = {516 { "MLNXBF17", 0 },517 {},518};519MODULE_DEVICE_TABLE(acpi, mlxbf_gige_acpi_match);520 521static struct platform_driver mlxbf_gige_driver = {522 .probe = mlxbf_gige_probe,523 .remove_new = mlxbf_gige_remove,524 .shutdown = mlxbf_gige_shutdown,525 .driver = {526 .name = KBUILD_MODNAME,527 .acpi_match_table = ACPI_PTR(mlxbf_gige_acpi_match),528 },529};530 531module_platform_driver(mlxbf_gige_driver);532 533MODULE_DESCRIPTION("Mellanox BlueField SoC Gigabit Ethernet Driver");534MODULE_AUTHOR("David Thompson <davthompson@nvidia.com>");535MODULE_AUTHOR("Asmaa Mnebhi <asmaa@nvidia.com>");536MODULE_LICENSE("Dual BSD/GPL");537