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1/* SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause */2 3/* Header file for Mellanox BlueField GigE register defines4 *5 * Copyright (C) 2020-2021 NVIDIA CORPORATION & AFFILIATES6 */7 8#ifndef __MLXBF_GIGE_REGS_H__9#define __MLXBF_GIGE_REGS_H__10 11#include <linux/bitfield.h>12 13#define MLXBF_GIGE_VERSION 0x000014#define MLXBF_GIGE_VERSION_BF2 0x015#define MLXBF_GIGE_VERSION_BF3 0x116#define MLXBF_GIGE_STATUS 0x001017#define MLXBF_GIGE_STATUS_READY BIT(0)18#define MLXBF_GIGE_INT_STATUS 0x002819#define MLXBF_GIGE_INT_STATUS_RX_RECEIVE_PACKET BIT(0)20#define MLXBF_GIGE_INT_STATUS_RX_MAC_ERROR BIT(1)21#define MLXBF_GIGE_INT_STATUS_RX_TRN_ERROR BIT(2)22#define MLXBF_GIGE_INT_STATUS_SW_ACCESS_ERROR BIT(3)23#define MLXBF_GIGE_INT_STATUS_SW_CONFIG_ERROR BIT(4)24#define MLXBF_GIGE_INT_STATUS_TX_PI_CI_EXCEED_WQ_SIZE BIT(5)25#define MLXBF_GIGE_INT_STATUS_TX_SMALL_FRAME_SIZE BIT(6)26#define MLXBF_GIGE_INT_STATUS_TX_CHECKSUM_INPUTS BIT(7)27#define MLXBF_GIGE_INT_STATUS_HW_ACCESS_ERROR BIT(8)28#define MLXBF_GIGE_INT_EN 0x003029#define MLXBF_GIGE_INT_EN_RX_RECEIVE_PACKET BIT(0)30#define MLXBF_GIGE_INT_EN_RX_MAC_ERROR BIT(1)31#define MLXBF_GIGE_INT_EN_RX_TRN_ERROR BIT(2)32#define MLXBF_GIGE_INT_EN_SW_ACCESS_ERROR BIT(3)33#define MLXBF_GIGE_INT_EN_SW_CONFIG_ERROR BIT(4)34#define MLXBF_GIGE_INT_EN_TX_PI_CI_EXCEED_WQ_SIZE BIT(5)35#define MLXBF_GIGE_INT_EN_TX_SMALL_FRAME_SIZE BIT(6)36#define MLXBF_GIGE_INT_EN_TX_CHECKSUM_INPUTS BIT(7)37#define MLXBF_GIGE_INT_EN_HW_ACCESS_ERROR BIT(8)38#define MLXBF_GIGE_INT_MASK 0x003839#define MLXBF_GIGE_INT_MASK_RX_RECEIVE_PACKET BIT(0)40#define MLXBF_GIGE_CONTROL 0x004041#define MLXBF_GIGE_CONTROL_PORT_EN BIT(0)42#define MLXBF_GIGE_CONTROL_MAC_ID_RANGE_EN BIT(1)43#define MLXBF_GIGE_CONTROL_EN_SPECIFIC_MAC BIT(4)44#define MLXBF_GIGE_CONTROL_CLEAN_PORT_EN BIT(31)45#define MLXBF_GIGE_RX_WQ_BASE 0x020046#define MLXBF_GIGE_RX_WQE_SIZE_LOG2 0x020847#define MLXBF_GIGE_RX_WQE_SIZE_LOG2_RESET_VAL 748#define MLXBF_GIGE_RX_CQ_BASE 0x021049#define MLXBF_GIGE_TX_WQ_BASE 0x021850#define MLXBF_GIGE_TX_WQ_SIZE_LOG2 0x022051#define MLXBF_GIGE_TX_WQ_SIZE_LOG2_RESET_VAL 752#define MLXBF_GIGE_TX_CI_UPDATE_ADDRESS 0x022853#define MLXBF_GIGE_RX_WQE_PI 0x023054#define MLXBF_GIGE_TX_PRODUCER_INDEX 0x023855#define MLXBF_GIGE_RX_MAC_FILTER 0x024056#define MLXBF_GIGE_RX_MAC_FILTER_STRIDE 0x000857#define MLXBF_GIGE_RX_DIN_DROP_COUNTER 0x026058#define MLXBF_GIGE_TX_CONSUMER_INDEX 0x031059#define MLXBF_GIGE_TX_CONTROL 0x031860#define MLXBF_GIGE_TX_CONTROL_GRACEFUL_STOP BIT(0)61#define MLXBF_GIGE_TX_STATUS 0x038862#define MLXBF_GIGE_TX_STATUS_DATA_FIFO_FULL BIT(1)63#define MLXBF_GIGE_RX_MAC_FILTER_DMAC_RANGE_START 0x052064#define MLXBF_GIGE_RX_MAC_FILTER_DMAC_RANGE_END 0x052865#define MLXBF_GIGE_RX_MAC_FILTER_GENERAL 0x053066#define MLXBF_GIGE_RX_MAC_FILTER_EN_MULTICAST BIT(1)67#define MLXBF_GIGE_RX_MAC_FILTER_COUNT_DISC 0x054068#define MLXBF_GIGE_RX_MAC_FILTER_COUNT_DISC_EN BIT(0)69#define MLXBF_GIGE_RX_MAC_FILTER_COUNT_PASS 0x054870#define MLXBF_GIGE_RX_MAC_FILTER_COUNT_PASS_EN BIT(0)71#define MLXBF_GIGE_RX_PASS_COUNTER_ALL 0x055072#define MLXBF_GIGE_RX_DISC_COUNTER_ALL 0x056073#define MLXBF_GIGE_RX 0x057874#define MLXBF_GIGE_RX_STRIP_CRC_EN BIT(1)75#define MLXBF_GIGE_RX_DMA 0x058076#define MLXBF_GIGE_RX_DMA_EN BIT(0)77#define MLXBF_GIGE_RX_CQE_PACKET_CI 0x05b078#define MLXBF_GIGE_MAC_CFG 0x05e879 80/* NOTE: MLXBF_GIGE_MAC_CFG is the last defined register offset,81 * so use that plus size of single register to derive total size82 */83#define MLXBF_GIGE_MMIO_REG_SZ (MLXBF_GIGE_MAC_CFG + 8)84 85#define MLXBF_GIGE_PLU_TX_REG0 0x8086#define MLXBF_GIGE_PLU_TX_IPG_SIZE_MASK GENMASK(11, 0)87#define MLXBF_GIGE_PLU_TX_SGMII_MODE_MASK GENMASK(15, 14)88 89#define MLXBF_GIGE_PLU_RX_REG0 0x1090#define MLXBF_GIGE_PLU_RX_SGMII_MODE_MASK GENMASK(25, 24)91 92#define MLXBF_GIGE_1G_SGMII_MODE 0x093#define MLXBF_GIGE_10M_SGMII_MODE 0x194#define MLXBF_GIGE_100M_SGMII_MODE 0x295 96/* ipg_size default value for 1G is fixed by HW to 11 + End = 12.97 * So for 100M it is 12 * 10 - 1 = 11998 * For 10M, it is 12 * 100 - 1 = 119999 */100#define MLXBF_GIGE_1G_IPG_SIZE 11101#define MLXBF_GIGE_100M_IPG_SIZE 119102#define MLXBF_GIGE_10M_IPG_SIZE 1199103 104/* Offsets into OOB LLU block for pause frame counters */105#define MLXBF_GIGE_BF2_TX_PAUSE_CNT_HI 0x33d8106#define MLXBF_GIGE_BF2_TX_PAUSE_CNT_LO 0x33dc107#define MLXBF_GIGE_BF2_RX_PAUSE_CNT_HI 0x3210108#define MLXBF_GIGE_BF2_RX_PAUSE_CNT_LO 0x3214109 110#define MLXBF_GIGE_BF3_TX_PAUSE_CNT_HI 0x3a88111#define MLXBF_GIGE_BF3_TX_PAUSE_CNT_LO 0x3a8c112#define MLXBF_GIGE_BF3_RX_PAUSE_CNT_HI 0x38c0113#define MLXBF_GIGE_BF3_RX_PAUSE_CNT_LO 0x38c4114 115#define MLXBF_GIGE_TX_PAUSE_CNT_HI ((priv->hw_version == MLXBF_GIGE_VERSION_BF2) ? \116 MLXBF_GIGE_BF2_TX_PAUSE_CNT_HI : \117 MLXBF_GIGE_BF3_TX_PAUSE_CNT_HI)118#define MLXBF_GIGE_TX_PAUSE_CNT_LO ((priv->hw_version == MLXBF_GIGE_VERSION_BF2) ? \119 MLXBF_GIGE_BF2_TX_PAUSE_CNT_LO : \120 MLXBF_GIGE_BF3_TX_PAUSE_CNT_LO)121#define MLXBF_GIGE_RX_PAUSE_CNT_HI ((priv->hw_version == MLXBF_GIGE_VERSION_BF2) ? \122 MLXBF_GIGE_BF2_RX_PAUSE_CNT_HI : \123 MLXBF_GIGE_BF3_RX_PAUSE_CNT_HI)124#define MLXBF_GIGE_RX_PAUSE_CNT_LO ((priv->hw_version == MLXBF_GIGE_VERSION_BF2) ? \125 MLXBF_GIGE_BF2_RX_PAUSE_CNT_LO : \126 MLXBF_GIGE_BF3_RX_PAUSE_CNT_LO)127 128#define MLXBF_GIGE_BF2_LLU_GENERAL_CONFIG 0x2110129#define MLXBF_GIGE_BF3_LLU_GENERAL_CONFIG 0x2030130 131#define MLXBF_GIGE_BF2_LLU_COUNTERS_EN BIT(0)132#define MLXBF_GIGE_BF3_LLU_COUNTERS_EN BIT(4)133 134#endif /* !defined(__MLXBF_GIGE_REGS_H__) */135