417 lines · c
1/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */2/* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */3 4#ifndef _MLXSW_PCI_HW_H5#define _MLXSW_PCI_HW_H6 7#include <linux/bitops.h>8 9#include "item.h"10 11#define MLXSW_PCI_BAR0_SIZE (1024 * 1024) /* 1MB */12#define MLXSW_PCI_PAGE_SIZE 409613 14#define MLXSW_PCI_CIR_BASE 0x7100015#define MLXSW_PCI_CIR_IN_PARAM_HI MLXSW_PCI_CIR_BASE16#define MLXSW_PCI_CIR_IN_PARAM_LO (MLXSW_PCI_CIR_BASE + 0x04)17#define MLXSW_PCI_CIR_IN_MODIFIER (MLXSW_PCI_CIR_BASE + 0x08)18#define MLXSW_PCI_CIR_OUT_PARAM_HI (MLXSW_PCI_CIR_BASE + 0x0C)19#define MLXSW_PCI_CIR_OUT_PARAM_LO (MLXSW_PCI_CIR_BASE + 0x10)20#define MLXSW_PCI_CIR_TOKEN (MLXSW_PCI_CIR_BASE + 0x14)21#define MLXSW_PCI_CIR_CTRL (MLXSW_PCI_CIR_BASE + 0x18)22#define MLXSW_PCI_CIR_CTRL_GO_BIT BIT(23)23#define MLXSW_PCI_CIR_CTRL_EVREQ_BIT BIT(22)24#define MLXSW_PCI_CIR_CTRL_OPCODE_MOD_SHIFT 1225#define MLXSW_PCI_CIR_CTRL_STATUS_SHIFT 2426#define MLXSW_PCI_CIR_TIMEOUT_MSECS 100027 28#define MLXSW_PCI_SW_RESET_TIMEOUT_MSECS 90000029#define MLXSW_PCI_SW_RESET_WAIT_MSECS 40030#define MLXSW_PCI_FW_READY 0xA184431#define MLXSW_PCI_FW_READY_MASK 0xFFFF32#define MLXSW_PCI_FW_READY_MAGIC 0x5E33 34#define MLXSW_PCI_DOORBELL_SDQ_OFFSET 0x00035#define MLXSW_PCI_DOORBELL_RDQ_OFFSET 0x20036#define MLXSW_PCI_DOORBELL_CQ_OFFSET 0x40037#define MLXSW_PCI_DOORBELL_EQ_OFFSET 0x60038#define MLXSW_PCI_DOORBELL_ARM_CQ_OFFSET 0x80039#define MLXSW_PCI_DOORBELL_ARM_EQ_OFFSET 0xA0040 41#define MLXSW_PCI_DOORBELL(offset, type_offset, num) \42 ((offset) + (type_offset) + (num) * 4)43 44#define MLXSW_PCI_CQS_MAX 9645#define MLXSW_PCI_EQS_MAX 246#define MLXSW_PCI_EQS_COUNT 147#define MLXSW_PCI_EQ_COMP_NUM 148 49#define MLXSW_PCI_SDQS_MIN 2 /* EMAD and control traffic */50#define MLXSW_PCI_SDQ_EMAD_INDEX 051#define MLXSW_PCI_SDQ_EMAD_TC 052#define MLXSW_PCI_SDQ_CTL_TC 353 54#define MLXSW_PCI_AQ_PAGES 855#define MLXSW_PCI_AQ_SIZE (MLXSW_PCI_PAGE_SIZE * MLXSW_PCI_AQ_PAGES)56#define MLXSW_PCI_WQE_SIZE 32 /* 32 bytes per element */57#define MLXSW_PCI_CQE01_SIZE 16 /* 16 bytes per element */58#define MLXSW_PCI_CQE2_SIZE 32 /* 32 bytes per element */59#define MLXSW_PCI_CQE_SIZE_MAX MLXSW_PCI_CQE2_SIZE60#define MLXSW_PCI_EQE_SIZE 16 /* 16 bytes per element */61#define MLXSW_PCI_WQE_COUNT (MLXSW_PCI_AQ_SIZE / MLXSW_PCI_WQE_SIZE)62#define MLXSW_PCI_CQE01_COUNT (MLXSW_PCI_AQ_SIZE / MLXSW_PCI_CQE01_SIZE)63#define MLXSW_PCI_CQE2_COUNT (MLXSW_PCI_AQ_SIZE / MLXSW_PCI_CQE2_SIZE)64#define MLXSW_PCI_EQE_COUNT (MLXSW_PCI_AQ_SIZE / MLXSW_PCI_EQE_SIZE)65#define MLXSW_PCI_EQE_UPDATE_COUNT 0x8066 67#define MLXSW_PCI_WQE_SG_ENTRIES 368#define MLXSW_PCI_WQE_TYPE_ETHERNET 0xA69 70/* pci_wqe_c71 * If set it indicates that a completion should be reported upon72 * execution of this descriptor.73 */74MLXSW_ITEM32(pci, wqe, c, 0x00, 31, 1);75 76/* pci_wqe_lp77 * Local Processing, set if packet should be processed by the local78 * switch hardware:79 * For Ethernet EMAD (Direct Route and non Direct Route) -80 * must be set if packet destination is local device81 * For InfiniBand CTL - must be set if packet destination is local device82 * Otherwise it must be clear83 * Local Process packets must not exceed the size of 2K (including payload84 * and headers).85 */86MLXSW_ITEM32(pci, wqe, lp, 0x00, 30, 1);87 88/* pci_wqe_type89 * Packet type.90 */91MLXSW_ITEM32(pci, wqe, type, 0x00, 23, 4);92 93/* pci_wqe_byte_count94 * Size of i-th scatter/gather entry, 0 if entry is unused.95 */96MLXSW_ITEM16_INDEXED(pci, wqe, byte_count, 0x02, 0, 14, 0x02, 0x00, false);97 98/* pci_wqe_address99 * Physical address of i-th scatter/gather entry.100 * Gather Entries must be 2Byte aligned.101 */102MLXSW_ITEM64_INDEXED(pci, wqe, address, 0x08, 0, 64, 0x8, 0x0, false);103 104enum mlxsw_pci_cqe_v {105 MLXSW_PCI_CQE_V0,106 MLXSW_PCI_CQE_V1,107 MLXSW_PCI_CQE_V2,108};109 110#define mlxsw_pci_cqe_item_helpers(name, v0, v1, v2) \111static inline u32 mlxsw_pci_cqe_##name##_get(enum mlxsw_pci_cqe_v v, char *cqe) \112{ \113 switch (v) { \114 default: \115 case MLXSW_PCI_CQE_V0: \116 return mlxsw_pci_cqe##v0##_##name##_get(cqe); \117 case MLXSW_PCI_CQE_V1: \118 return mlxsw_pci_cqe##v1##_##name##_get(cqe); \119 case MLXSW_PCI_CQE_V2: \120 return mlxsw_pci_cqe##v2##_##name##_get(cqe); \121 } \122} \123static inline void mlxsw_pci_cqe_##name##_set(enum mlxsw_pci_cqe_v v, \124 char *cqe, u32 val) \125{ \126 switch (v) { \127 default: \128 case MLXSW_PCI_CQE_V0: \129 mlxsw_pci_cqe##v0##_##name##_set(cqe, val); \130 break; \131 case MLXSW_PCI_CQE_V1: \132 mlxsw_pci_cqe##v1##_##name##_set(cqe, val); \133 break; \134 case MLXSW_PCI_CQE_V2: \135 mlxsw_pci_cqe##v2##_##name##_set(cqe, val); \136 break; \137 } \138}139 140/* pci_cqe_lag141 * Packet arrives from a port which is a LAG142 */143MLXSW_ITEM32(pci, cqe0, lag, 0x00, 23, 1);144MLXSW_ITEM32(pci, cqe12, lag, 0x00, 24, 1);145mlxsw_pci_cqe_item_helpers(lag, 0, 12, 12);146 147/* pci_cqe_system_port/lag_id148 * When lag=0: System port on which the packet was received149 * When lag=1:150 * bits [15:4] LAG ID on which the packet was received151 * bits [3:0] sub_port on which the packet was received152 */153MLXSW_ITEM32(pci, cqe, system_port, 0x00, 0, 16);154MLXSW_ITEM32(pci, cqe0, lag_id, 0x00, 4, 12);155MLXSW_ITEM32(pci, cqe12, lag_id, 0x00, 0, 16);156mlxsw_pci_cqe_item_helpers(lag_id, 0, 12, 12);157MLXSW_ITEM32(pci, cqe0, lag_subport, 0x00, 0, 4);158MLXSW_ITEM32(pci, cqe12, lag_subport, 0x00, 16, 8);159mlxsw_pci_cqe_item_helpers(lag_subport, 0, 12, 12);160 161/* pci_cqe_wqe_counter162 * WQE count of the WQEs completed on the associated dqn163 */164MLXSW_ITEM32(pci, cqe, wqe_counter, 0x04, 16, 16);165 166/* pci_cqe_byte_count167 * Byte count of received packets including additional two168 * Reserved Bytes that are append to the end of the frame.169 * Reserved for Send CQE.170 */171MLXSW_ITEM32(pci, cqe, byte_count, 0x04, 0, 14);172 173#define MLXSW_PCI_CQE2_MIRROR_CONG_INVALID 0xFFFF174 175/* pci_cqe_mirror_cong_high176 * Congestion level in units of 8KB of the egress traffic class of the original177 * packet that does mirroring to the CPU. Value of 0xFFFF means that the178 * congestion level is invalid.179 */180MLXSW_ITEM32(pci, cqe2, mirror_cong_high, 0x08, 16, 4);181 182/* pci_cqe_trap_id183 * Trap ID that captured the packet.184 */185MLXSW_ITEM32(pci, cqe, trap_id, 0x08, 0, 10);186 187/* pci_cqe_crc188 * Length include CRC. Indicates the length field includes189 * the packet's CRC.190 */191MLXSW_ITEM32(pci, cqe0, crc, 0x0C, 8, 1);192MLXSW_ITEM32(pci, cqe12, crc, 0x0C, 9, 1);193mlxsw_pci_cqe_item_helpers(crc, 0, 12, 12);194 195/* pci_cqe_e196 * CQE with Error.197 */198MLXSW_ITEM32(pci, cqe0, e, 0x0C, 7, 1);199MLXSW_ITEM32(pci, cqe12, e, 0x00, 27, 1);200mlxsw_pci_cqe_item_helpers(e, 0, 12, 12);201 202/* pci_cqe_sr203 * 1 - Send Queue204 * 0 - Receive Queue205 */206MLXSW_ITEM32(pci, cqe0, sr, 0x0C, 6, 1);207MLXSW_ITEM32(pci, cqe12, sr, 0x00, 26, 1);208mlxsw_pci_cqe_item_helpers(sr, 0, 12, 12);209 210/* pci_cqe_dqn211 * Descriptor Queue (DQ) Number.212 */213MLXSW_ITEM32(pci, cqe0, dqn, 0x0C, 1, 5);214MLXSW_ITEM32(pci, cqe12, dqn, 0x0C, 1, 6);215mlxsw_pci_cqe_item_helpers(dqn, 0, 12, 12);216 217/* pci_cqe_time_stamp_low218 * Time stamp of the CQE219 * Format according to time_stamp_type:220 * 0: uSec - 1.024uSec (default for devices which do not support221 * time_stamp_type). Only bits 15:0 are valid222 * 1: FRC - Free Running Clock - units of 1nSec223 * 2: UTC - time_stamp[37:30] = Sec224 * - time_stamp[29:0] = nSec225 * 3: Mirror_UTC. UTC time stamp of the original packet that has226 * MIRROR_SESSION traps227 * - time_stamp[37:30] = Sec228 * - time_stamp[29:0] = nSec229 * Formats 0..2 are configured by230 * CONFIG_PROFILE.cqe_time_stamp_type for PTP traps231 * Format 3 is used for MIRROR_SESSION traps232 * Note that Spectrum does not reveal FRC, UTC and Mirror_UTC233 */234MLXSW_ITEM32(pci, cqe2, time_stamp_low, 0x0C, 16, 16);235 236#define MLXSW_PCI_CQE2_MIRROR_TCLASS_INVALID 0x1F237 238/* pci_cqe_mirror_tclass239 * The egress traffic class of the original packet that does mirroring to the240 * CPU. Value of 0x1F means that the traffic class is invalid.241 */242MLXSW_ITEM32(pci, cqe2, mirror_tclass, 0x10, 27, 5);243 244/* pci_cqe_tx_lag245 * The Tx port of a packet that is mirrored / sampled to the CPU is a LAG.246 */247MLXSW_ITEM32(pci, cqe2, tx_lag, 0x10, 24, 1);248 249/* pci_cqe_tx_lag_subport250 * The port index within the LAG of a packet that is mirrored / sampled to the251 * CPU. Reserved when tx_lag is 0.252 */253MLXSW_ITEM32(pci, cqe2, tx_lag_subport, 0x10, 16, 8);254 255#define MLXSW_PCI_CQE2_TX_PORT_MULTI_PORT 0xFFFE256#define MLXSW_PCI_CQE2_TX_PORT_INVALID 0xFFFF257 258/* pci_cqe_tx_lag_id259 * The Tx LAG ID of the original packet that is mirrored / sampled to the CPU.260 * Value of 0xFFFE means multi-port. Value fo 0xFFFF means that the Tx LAG ID261 * is invalid. Reserved when tx_lag is 0.262 */263MLXSW_ITEM32(pci, cqe2, tx_lag_id, 0x10, 0, 16);264 265/* pci_cqe_tx_system_port266 * The Tx port of the original packet that is mirrored / sampled to the CPU.267 * Value of 0xFFFE means multi-port. Value fo 0xFFFF means that the Tx port is268 * invalid. Reserved when tx_lag is 1.269 */270MLXSW_ITEM32(pci, cqe2, tx_system_port, 0x10, 0, 16);271 272/* pci_cqe_mirror_cong_low273 * Congestion level in units of 8KB of the egress traffic class of the original274 * packet that does mirroring to the CPU. Value of 0xFFFF means that the275 * congestion level is invalid.276 */277MLXSW_ITEM32(pci, cqe2, mirror_cong_low, 0x14, 20, 12);278 279#define MLXSW_PCI_CQE2_MIRROR_CONG_SHIFT 13 /* Units of 8KB. */280 281static inline u16 mlxsw_pci_cqe2_mirror_cong_get(const char *cqe)282{283 u16 cong_high = mlxsw_pci_cqe2_mirror_cong_high_get(cqe);284 u16 cong_low = mlxsw_pci_cqe2_mirror_cong_low_get(cqe);285 286 return cong_high << 12 | cong_low;287}288 289/* pci_cqe_user_def_val_orig_pkt_len290 * When trap_id is an ACL: User defined value from policy engine action.291 */292MLXSW_ITEM32(pci, cqe2, user_def_val_orig_pkt_len, 0x14, 0, 20);293 294/* pci_cqe_mirror_reason295 * Mirror reason.296 */297MLXSW_ITEM32(pci, cqe2, mirror_reason, 0x18, 24, 8);298 299enum mlxsw_pci_cqe_time_stamp_type {300 MLXSW_PCI_CQE_TIME_STAMP_TYPE_USEC,301 MLXSW_PCI_CQE_TIME_STAMP_TYPE_FRC,302 MLXSW_PCI_CQE_TIME_STAMP_TYPE_UTC,303 MLXSW_PCI_CQE_TIME_STAMP_TYPE_MIRROR_UTC,304};305 306/* pci_cqe_time_stamp_type307 * Time stamp type:308 * 0: uSec - 1.024uSec (default for devices which do not support309 * time_stamp_type)310 * 1: FRC - Free Running Clock - units of 1nSec311 * 2: UTC312 * 3: Mirror_UTC. UTC time stamp of the original packet that has313 * MIRROR_SESSION traps314 */315MLXSW_ITEM32(pci, cqe2, time_stamp_type, 0x18, 22, 2);316 317#define MLXSW_PCI_CQE2_MIRROR_LATENCY_INVALID 0xFFFFFF318 319/* pci_cqe_time_stamp_high320 * Time stamp of the CQE321 * Format according to time_stamp_type:322 * 0: uSec - 1.024uSec (default for devices which do not support323 * time_stamp_type). Only bits 15:0 are valid324 * 1: FRC - Free Running Clock - units of 1nSec325 * 2: UTC - time_stamp[37:30] = Sec326 * - time_stamp[29:0] = nSec327 * 3: Mirror_UTC. UTC time stamp of the original packet that has328 * MIRROR_SESSION traps329 * - time_stamp[37:30] = Sec330 * - time_stamp[29:0] = nSec331 * Formats 0..2 are configured by332 * CONFIG_PROFILE.cqe_time_stamp_type for PTP traps333 * Format 3 is used for MIRROR_SESSION traps334 * Note that Spectrum does not reveal FRC, UTC and Mirror_UTC335 */336MLXSW_ITEM32(pci, cqe2, time_stamp_high, 0x18, 0, 22);337 338static inline u64 mlxsw_pci_cqe2_time_stamp_get(const char *cqe)339{340 u64 ts_high = mlxsw_pci_cqe2_time_stamp_high_get(cqe);341 u64 ts_low = mlxsw_pci_cqe2_time_stamp_low_get(cqe);342 343 return ts_high << 16 | ts_low;344}345 346static inline u8 mlxsw_pci_cqe2_time_stamp_sec_get(const char *cqe)347{348 u64 full_ts = mlxsw_pci_cqe2_time_stamp_get(cqe);349 350 return full_ts >> 30 & 0xFF;351}352 353static inline u32 mlxsw_pci_cqe2_time_stamp_nsec_get(const char *cqe)354{355 u64 full_ts = mlxsw_pci_cqe2_time_stamp_get(cqe);356 357 return full_ts & 0x3FFFFFFF;358}359 360/* pci_cqe_mirror_latency361 * End-to-end latency of the original packet that does mirroring to the CPU.362 * Value of 0xFFFFFF means that the latency is invalid. Units are according to363 * MOGCR.mirror_latency_units.364 */365MLXSW_ITEM32(pci, cqe2, mirror_latency, 0x1C, 8, 24);366 367/* pci_cqe_owner368 * Ownership bit.369 */370MLXSW_ITEM32(pci, cqe01, owner, 0x0C, 0, 1);371MLXSW_ITEM32(pci, cqe2, owner, 0x1C, 0, 1);372mlxsw_pci_cqe_item_helpers(owner, 01, 01, 2);373 374/* pci_eqe_event_type375 * Event type.376 */377MLXSW_ITEM32(pci, eqe, event_type, 0x0C, 24, 8);378#define MLXSW_PCI_EQE_EVENT_TYPE_COMP 0x00379#define MLXSW_PCI_EQE_EVENT_TYPE_CMD 0x0A380 381/* pci_eqe_event_sub_type382 * Event type.383 */384MLXSW_ITEM32(pci, eqe, event_sub_type, 0x0C, 16, 8);385 386/* pci_eqe_cqn387 * Completion Queue that triggered this EQE.388 */389MLXSW_ITEM32(pci, eqe, cqn, 0x0C, 8, 7);390 391/* pci_eqe_owner392 * Ownership bit.393 */394MLXSW_ITEM32(pci, eqe, owner, 0x0C, 0, 1);395 396/* pci_eqe_cmd_token397 * Command completion event - token398 */399MLXSW_ITEM32(pci, eqe, cmd_token, 0x00, 16, 16);400 401/* pci_eqe_cmd_status402 * Command completion event - status403 */404MLXSW_ITEM32(pci, eqe, cmd_status, 0x00, 0, 8);405 406/* pci_eqe_cmd_out_param_h407 * Command completion event - output parameter - higher part408 */409MLXSW_ITEM32(pci, eqe, cmd_out_param_h, 0x04, 0, 32);410 411/* pci_eqe_cmd_out_param_l412 * Command completion event - output parameter - lower part413 */414MLXSW_ITEM32(pci, eqe, cmd_out_param_l, 0x08, 0, 32);415 416#endif417