brintos / linux-shallow public Read only

1/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */2/* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */3 4#ifndef _MLXSW_REG_H5#define _MLXSW_REG_H6 7#include <linux/kernel.h>8#include <linux/string.h>9#include <linux/bitops.h>10#include <linux/if_vlan.h>11 12#include "item.h"13#include "port.h"14 15struct mlxsw_reg_info {16	u16 id;17	u16 len; /* In u8 */18	const char *name;19};20 21#define MLXSW_REG_DEFINE(_name, _id, _len)				\22static const struct mlxsw_reg_info mlxsw_reg_##_name = {		\23	.id = _id,							\24	.len = _len,							\25	.name = #_name,							\26}27 28#define MLXSW_REG(type) (&mlxsw_reg_##type)29#define MLXSW_REG_LEN(type) MLXSW_REG(type)->len30#define MLXSW_REG_ZERO(type, payload) memset(payload, 0, MLXSW_REG(type)->len)31 32/* SGCR - Switch General Configuration Register33 * --------------------------------------------34 * This register is used for configuration of the switch capabilities.35 */36#define MLXSW_REG_SGCR_ID 0x200037#define MLXSW_REG_SGCR_LEN 0x1038 39MLXSW_REG_DEFINE(sgcr, MLXSW_REG_SGCR_ID, MLXSW_REG_SGCR_LEN);40 41/* reg_sgcr_lag_lookup_pgt_base42 * Base address used for lookup in PGT table43 * Supported when CONFIG_PROFILE.lag_mode = 144 * Note: when IGCR.ddd_lag_mode=0, the address shall be aligned to 8 entries.45 * Access: RW46 */47MLXSW_ITEM32(reg, sgcr, lag_lookup_pgt_base, 0x0C, 0, 16);48 49static inline void mlxsw_reg_sgcr_pack(char *payload, u16 lag_lookup_pgt_base)50{51	MLXSW_REG_ZERO(sgcr, payload);52	mlxsw_reg_sgcr_lag_lookup_pgt_base_set(payload, lag_lookup_pgt_base);53}54 55/* SPAD - Switch Physical Address Register56 * ---------------------------------------57 * The SPAD register configures the switch physical MAC address.58 */59#define MLXSW_REG_SPAD_ID 0x200260#define MLXSW_REG_SPAD_LEN 0x1061 62MLXSW_REG_DEFINE(spad, MLXSW_REG_SPAD_ID, MLXSW_REG_SPAD_LEN);63 64/* reg_spad_base_mac65 * Base MAC address for the switch partitions.66 * Per switch partition MAC address is equal to:67 * base_mac + swid68 * Access: RW69 */70MLXSW_ITEM_BUF(reg, spad, base_mac, 0x02, 6);71 72/* SSPR - Switch System Port Record Register73 * -----------------------------------------74 * Configures the system port to local port mapping.75 */76#define MLXSW_REG_SSPR_ID 0x200877#define MLXSW_REG_SSPR_LEN 0x878 79MLXSW_REG_DEFINE(sspr, MLXSW_REG_SSPR_ID, MLXSW_REG_SSPR_LEN);80 81/* reg_sspr_m82 * Master - if set, then the record describes the master system port.83 * This is needed in case a local port is mapped into several system ports84 * (for multipathing). That number will be reported as the source system85 * port when packets are forwarded to the CPU. Only one master port is allowed86 * per local port.87 *88 * Note: Must be set for Spectrum.89 * Access: RW90 */91MLXSW_ITEM32(reg, sspr, m, 0x00, 31, 1);92 93/* reg_sspr_local_port94 * Local port number.95 *96 * Access: RW97 */98MLXSW_ITEM32_LP(reg, sspr, 0x00, 16, 0x00, 12);99 100/* reg_sspr_system_port101 * Unique identifier within the stacking domain that represents all the ports102 * that are available in the system (external ports).103 *104 * Currently, only single-ASIC configurations are supported, so we default to105 * 1:1 mapping between system ports and local ports.106 * Access: Index107 */108MLXSW_ITEM32(reg, sspr, system_port, 0x04, 0, 16);109 110static inline void mlxsw_reg_sspr_pack(char *payload, u16 local_port)111{112	MLXSW_REG_ZERO(sspr, payload);113	mlxsw_reg_sspr_m_set(payload, 1);114	mlxsw_reg_sspr_local_port_set(payload, local_port);115	mlxsw_reg_sspr_system_port_set(payload, local_port);116}117 118/* SFDAT - Switch Filtering Database Aging Time119 * --------------------------------------------120 * Controls the Switch aging time. Aging time is able to be set per Switch121 * Partition.122 */123#define MLXSW_REG_SFDAT_ID 0x2009124#define MLXSW_REG_SFDAT_LEN 0x8125 126MLXSW_REG_DEFINE(sfdat, MLXSW_REG_SFDAT_ID, MLXSW_REG_SFDAT_LEN);127 128/* reg_sfdat_swid129 * Switch partition ID.130 * Access: Index131 */132MLXSW_ITEM32(reg, sfdat, swid, 0x00, 24, 8);133 134/* reg_sfdat_age_time135 * Aging time in seconds136 * Min - 10 seconds137 * Max - 1,000,000 seconds138 * Default is 300 seconds.139 * Access: RW140 */141MLXSW_ITEM32(reg, sfdat, age_time, 0x04, 0, 20);142 143static inline void mlxsw_reg_sfdat_pack(char *payload, u32 age_time)144{145	MLXSW_REG_ZERO(sfdat, payload);146	mlxsw_reg_sfdat_swid_set(payload, 0);147	mlxsw_reg_sfdat_age_time_set(payload, age_time);148}149 150/* SFD - Switch Filtering Database151 * -------------------------------152 * The following register defines the access to the filtering database.153 * The register supports querying, adding, removing and modifying the database.154 * The access is optimized for bulk updates in which case more than one155 * FDB record is present in the same command.156 */157#define MLXSW_REG_SFD_ID 0x200A158#define MLXSW_REG_SFD_BASE_LEN 0x10 /* base length, without records */159#define MLXSW_REG_SFD_REC_LEN 0x10 /* record length */160#define MLXSW_REG_SFD_REC_MAX_COUNT 64161#define MLXSW_REG_SFD_LEN (MLXSW_REG_SFD_BASE_LEN +	\162			   MLXSW_REG_SFD_REC_LEN * MLXSW_REG_SFD_REC_MAX_COUNT)163 164MLXSW_REG_DEFINE(sfd, MLXSW_REG_SFD_ID, MLXSW_REG_SFD_LEN);165 166/* reg_sfd_swid167 * Switch partition ID for queries. Reserved on Write.168 * Access: Index169 */170MLXSW_ITEM32(reg, sfd, swid, 0x00, 24, 8);171 172enum mlxsw_reg_sfd_op {173	/* Dump entire FDB a (process according to record_locator) */174	MLXSW_REG_SFD_OP_QUERY_DUMP = 0,175	/* Query records by {MAC, VID/FID} value */176	MLXSW_REG_SFD_OP_QUERY_QUERY = 1,177	/* Query and clear activity. Query records by {MAC, VID/FID} value */178	MLXSW_REG_SFD_OP_QUERY_QUERY_AND_CLEAR_ACTIVITY = 2,179	/* Test. Response indicates if each of the records could be180	 * added to the FDB.181	 */182	MLXSW_REG_SFD_OP_WRITE_TEST = 0,183	/* Add/modify. Aged-out records cannot be added. This command removes184	 * the learning notification of the {MAC, VID/FID}. Response includes185	 * the entries that were added to the FDB.186	 */187	MLXSW_REG_SFD_OP_WRITE_EDIT = 1,188	/* Remove record by {MAC, VID/FID}. This command also removes189	 * the learning notification and aged-out notifications190	 * of the {MAC, VID/FID}. The response provides current (pre-removal)191	 * entries as non-aged-out.192	 */193	MLXSW_REG_SFD_OP_WRITE_REMOVE = 2,194	/* Remove learned notification by {MAC, VID/FID}. The response provides195	 * the removed learning notification.196	 */197	MLXSW_REG_SFD_OP_WRITE_REMOVE_NOTIFICATION = 2,198};199 200/* reg_sfd_op201 * Operation.202 * Access: OP203 */204MLXSW_ITEM32(reg, sfd, op, 0x04, 30, 2);205 206/* reg_sfd_record_locator207 * Used for querying the FDB. Use record_locator=0 to initiate the208 * query. When a record is returned, a new record_locator is209 * returned to be used in the subsequent query.210 * Reserved for database update.211 * Access: Index212 */213MLXSW_ITEM32(reg, sfd, record_locator, 0x04, 0, 30);214 215/* reg_sfd_num_rec216 * Request: Number of records to read/add/modify/remove217 * Response: Number of records read/added/replaced/removed218 * See above description for more details.219 * Ranges 0..64220 * Access: RW221 */222MLXSW_ITEM32(reg, sfd, num_rec, 0x08, 0, 8);223 224static inline void mlxsw_reg_sfd_pack(char *payload, enum mlxsw_reg_sfd_op op,225				      u32 record_locator)226{227	MLXSW_REG_ZERO(sfd, payload);228	mlxsw_reg_sfd_op_set(payload, op);229	mlxsw_reg_sfd_record_locator_set(payload, record_locator);230}231 232/* reg_sfd_rec_swid233 * Switch partition ID.234 * Access: Index235 */236MLXSW_ITEM32_INDEXED(reg, sfd, rec_swid, MLXSW_REG_SFD_BASE_LEN, 24, 8,237		     MLXSW_REG_SFD_REC_LEN, 0x00, false);238 239enum mlxsw_reg_sfd_rec_type {240	MLXSW_REG_SFD_REC_TYPE_UNICAST = 0x0,241	MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG = 0x1,242	MLXSW_REG_SFD_REC_TYPE_MULTICAST = 0x2,243	MLXSW_REG_SFD_REC_TYPE_UNICAST_TUNNEL = 0xC,244};245 246/* reg_sfd_rec_type247 * FDB record type.248 * Access: RW249 */250MLXSW_ITEM32_INDEXED(reg, sfd, rec_type, MLXSW_REG_SFD_BASE_LEN, 20, 4,251		     MLXSW_REG_SFD_REC_LEN, 0x00, false);252 253enum mlxsw_reg_sfd_rec_policy {254	/* Replacement disabled, aging disabled. */255	MLXSW_REG_SFD_REC_POLICY_STATIC_ENTRY = 0,256	/* (mlag remote): Replacement enabled, aging disabled,257	 * learning notification enabled on this port.258	 */259	MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_MLAG = 1,260	/* (ingress device): Replacement enabled, aging enabled. */261	MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_INGRESS = 3,262};263 264/* reg_sfd_rec_policy265 * Policy.266 * Access: RW267 */268MLXSW_ITEM32_INDEXED(reg, sfd, rec_policy, MLXSW_REG_SFD_BASE_LEN, 18, 2,269		     MLXSW_REG_SFD_REC_LEN, 0x00, false);270 271/* reg_sfd_rec_a272 * Activity. Set for new static entries. Set for static entries if a frame SMAC273 * lookup hits on the entry.274 * To clear the a bit, use "query and clear activity" op.275 * Access: RO276 */277MLXSW_ITEM32_INDEXED(reg, sfd, rec_a, MLXSW_REG_SFD_BASE_LEN, 16, 1,278		     MLXSW_REG_SFD_REC_LEN, 0x00, false);279 280/* reg_sfd_rec_mac281 * MAC address.282 * Access: Index283 */284MLXSW_ITEM_BUF_INDEXED(reg, sfd, rec_mac, MLXSW_REG_SFD_BASE_LEN, 6,285		       MLXSW_REG_SFD_REC_LEN, 0x02);286 287enum mlxsw_reg_sfd_rec_action {288	/* forward */289	MLXSW_REG_SFD_REC_ACTION_NOP = 0,290	/* forward and trap, trap_id is FDB_TRAP */291	MLXSW_REG_SFD_REC_ACTION_MIRROR_TO_CPU = 1,292	/* trap and do not forward, trap_id is FDB_TRAP */293	MLXSW_REG_SFD_REC_ACTION_TRAP = 2,294	/* forward to IP router */295	MLXSW_REG_SFD_REC_ACTION_FORWARD_IP_ROUTER = 3,296	MLXSW_REG_SFD_REC_ACTION_DISCARD_ERROR = 15,297};298 299/* reg_sfd_rec_action300 * Action to apply on the packet.301 * Note: Dynamic entries can only be configured with NOP action.302 * Access: RW303 */304MLXSW_ITEM32_INDEXED(reg, sfd, rec_action, MLXSW_REG_SFD_BASE_LEN, 28, 4,305		     MLXSW_REG_SFD_REC_LEN, 0x0C, false);306 307/* reg_sfd_uc_sub_port308 * VEPA channel on local port.309 * Valid only if local port is a non-stacking port. Must be 0 if multichannel310 * VEPA is not enabled.311 * Access: RW312 */313MLXSW_ITEM32_INDEXED(reg, sfd, uc_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8,314		     MLXSW_REG_SFD_REC_LEN, 0x08, false);315 316/* reg_sfd_uc_set_vid317 * Set VID.318 * 0 - Do not update VID.319 * 1 - Set VID.320 * For Spectrum-2 when set_vid=0 and smpe_valid=1, the smpe will modify the vid.321 * Access: RW322 *323 * Note: Reserved when legacy bridge model is used.324 */325MLXSW_ITEM32_INDEXED(reg, sfd, uc_set_vid, MLXSW_REG_SFD_BASE_LEN, 31, 1,326		     MLXSW_REG_SFD_REC_LEN, 0x08, false);327 328/* reg_sfd_uc_fid_vid329 * Filtering ID or VLAN ID330 * For SwitchX and SwitchX-2:331 * - Dynamic entries (policy 2,3) use FID332 * - Static entries (policy 0) use VID333 * - When independent learning is configured, VID=FID334 * For Spectrum: use FID for both Dynamic and Static entries.335 * VID should not be used.336 * Access: Index337 */338MLXSW_ITEM32_INDEXED(reg, sfd, uc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16,339		     MLXSW_REG_SFD_REC_LEN, 0x08, false);340 341/* reg_sfd_uc_vid342 * New VID when set_vid=1.343 * Access: RW344 *345 * Note: Reserved when legacy bridge model is used and when set_vid=0.346 */347MLXSW_ITEM32_INDEXED(reg, sfd, uc_vid, MLXSW_REG_SFD_BASE_LEN, 16, 12,348		     MLXSW_REG_SFD_REC_LEN, 0x0C, false);349 350/* reg_sfd_uc_system_port351 * Unique port identifier for the final destination of the packet.352 * Access: RW353 */354MLXSW_ITEM32_INDEXED(reg, sfd, uc_system_port, MLXSW_REG_SFD_BASE_LEN, 0, 16,355		     MLXSW_REG_SFD_REC_LEN, 0x0C, false);356 357static inline void mlxsw_reg_sfd_rec_pack(char *payload, int rec_index,358					  enum mlxsw_reg_sfd_rec_type rec_type,359					  const char *mac,360					  enum mlxsw_reg_sfd_rec_action action)361{362	u8 num_rec = mlxsw_reg_sfd_num_rec_get(payload);363 364	if (rec_index >= num_rec)365		mlxsw_reg_sfd_num_rec_set(payload, rec_index + 1);366	mlxsw_reg_sfd_rec_swid_set(payload, rec_index, 0);367	mlxsw_reg_sfd_rec_type_set(payload, rec_index, rec_type);368	mlxsw_reg_sfd_rec_mac_memcpy_to(payload, rec_index, mac);369	mlxsw_reg_sfd_rec_action_set(payload, rec_index, action);370}371 372static inline void mlxsw_reg_sfd_uc_pack(char *payload, int rec_index,373					 enum mlxsw_reg_sfd_rec_policy policy,374					 const char *mac, u16 fid_vid, u16 vid,375					 enum mlxsw_reg_sfd_rec_action action,376					 u16 local_port)377{378	mlxsw_reg_sfd_rec_pack(payload, rec_index,379			       MLXSW_REG_SFD_REC_TYPE_UNICAST, mac, action);380	mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy);381	mlxsw_reg_sfd_uc_sub_port_set(payload, rec_index, 0);382	mlxsw_reg_sfd_uc_fid_vid_set(payload, rec_index, fid_vid);383	mlxsw_reg_sfd_uc_set_vid_set(payload, rec_index, vid ? true : false);384	mlxsw_reg_sfd_uc_vid_set(payload, rec_index, vid);385	mlxsw_reg_sfd_uc_system_port_set(payload, rec_index, local_port);386}387 388/* reg_sfd_uc_lag_sub_port389 * LAG sub port.390 * Must be 0 if multichannel VEPA is not enabled.391 * Access: RW392 */393MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8,394		     MLXSW_REG_SFD_REC_LEN, 0x08, false);395 396/* reg_sfd_uc_lag_set_vid397 * Set VID.398 * 0 - Do not update VID.399 * 1 - Set VID.400 * For Spectrum-2 when set_vid=0 and smpe_valid=1, the smpe will modify the vid.401 * Access: RW402 *403 * Note: Reserved when legacy bridge model is used.404 */405MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_set_vid, MLXSW_REG_SFD_BASE_LEN, 31, 1,406		     MLXSW_REG_SFD_REC_LEN, 0x08, false);407 408/* reg_sfd_uc_lag_fid_vid409 * Filtering ID or VLAN ID410 * For SwitchX and SwitchX-2:411 * - Dynamic entries (policy 2,3) use FID412 * - Static entries (policy 0) use VID413 * - When independent learning is configured, VID=FID414 * For Spectrum: use FID for both Dynamic and Static entries.415 * VID should not be used.416 * Access: Index417 */418MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16,419		     MLXSW_REG_SFD_REC_LEN, 0x08, false);420 421/* reg_sfd_uc_lag_lag_vid422 * New vlan ID.423 * Access: RW424 *425 * Note: Reserved when legacy bridge model is used and set_vid=0.426 */427MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_vid, MLXSW_REG_SFD_BASE_LEN, 16, 12,428		     MLXSW_REG_SFD_REC_LEN, 0x0C, false);429 430/* reg_sfd_uc_lag_lag_id431 * LAG Identifier - pointer into the LAG descriptor table.432 * Access: RW433 */434MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_id, MLXSW_REG_SFD_BASE_LEN, 0, 10,435		     MLXSW_REG_SFD_REC_LEN, 0x0C, false);436 437static inline void438mlxsw_reg_sfd_uc_lag_pack(char *payload, int rec_index,439			  enum mlxsw_reg_sfd_rec_policy policy,440			  const char *mac, u16 fid_vid,441			  enum mlxsw_reg_sfd_rec_action action, u16 lag_vid,442			  u16 lag_id)443{444	mlxsw_reg_sfd_rec_pack(payload, rec_index,445			       MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG,446			       mac, action);447	mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy);448	mlxsw_reg_sfd_uc_lag_sub_port_set(payload, rec_index, 0);449	mlxsw_reg_sfd_uc_lag_fid_vid_set(payload, rec_index, fid_vid);450	mlxsw_reg_sfd_uc_lag_set_vid_set(payload, rec_index, true);451	mlxsw_reg_sfd_uc_lag_lag_vid_set(payload, rec_index, lag_vid);452	mlxsw_reg_sfd_uc_lag_lag_id_set(payload, rec_index, lag_id);453}454 455/* reg_sfd_mc_pgi456 *457 * Multicast port group index - index into the port group table.458 * Value 0x1FFF indicates the pgi should point to the MID entry.459 * For Spectrum this value must be set to 0x1FFF460 * Access: RW461 */462MLXSW_ITEM32_INDEXED(reg, sfd, mc_pgi, MLXSW_REG_SFD_BASE_LEN, 16, 13,463		     MLXSW_REG_SFD_REC_LEN, 0x08, false);464 465/* reg_sfd_mc_fid_vid466 *467 * Filtering ID or VLAN ID468 * Access: Index469 */470MLXSW_ITEM32_INDEXED(reg, sfd, mc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16,471		     MLXSW_REG_SFD_REC_LEN, 0x08, false);472 473/* reg_sfd_mc_mid474 *475 * Multicast identifier - global identifier that represents the multicast476 * group across all devices.477 * Access: RW478 */479MLXSW_ITEM32_INDEXED(reg, sfd, mc_mid, MLXSW_REG_SFD_BASE_LEN, 0, 16,480		     MLXSW_REG_SFD_REC_LEN, 0x0C, false);481 482static inline void483mlxsw_reg_sfd_mc_pack(char *payload, int rec_index,484		      const char *mac, u16 fid_vid,485		      enum mlxsw_reg_sfd_rec_action action, u16 mid)486{487	mlxsw_reg_sfd_rec_pack(payload, rec_index,488			       MLXSW_REG_SFD_REC_TYPE_MULTICAST, mac, action);489	mlxsw_reg_sfd_mc_pgi_set(payload, rec_index, 0x1FFF);490	mlxsw_reg_sfd_mc_fid_vid_set(payload, rec_index, fid_vid);491	mlxsw_reg_sfd_mc_mid_set(payload, rec_index, mid);492}493 494/* reg_sfd_uc_tunnel_uip_msb495 * When protocol is IPv4, the most significant byte of the underlay IPv4496 * destination IP.497 * When protocol is IPv6, reserved.498 * Access: RW499 */500MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_uip_msb, MLXSW_REG_SFD_BASE_LEN, 24,501		     8, MLXSW_REG_SFD_REC_LEN, 0x08, false);502 503/* reg_sfd_uc_tunnel_fid504 * Filtering ID.505 * Access: Index506 */507MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_fid, MLXSW_REG_SFD_BASE_LEN, 0, 16,508		     MLXSW_REG_SFD_REC_LEN, 0x08, false);509 510enum mlxsw_reg_sfd_uc_tunnel_protocol {511	MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV4,512	MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV6,513};514 515/* reg_sfd_uc_tunnel_protocol516 * IP protocol.517 * Access: RW518 */519MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_protocol, MLXSW_REG_SFD_BASE_LEN, 27,520		     1, MLXSW_REG_SFD_REC_LEN, 0x0C, false);521 522/* reg_sfd_uc_tunnel_uip_lsb523 * When protocol is IPv4, the least significant bytes of the underlay524 * IPv4 destination IP.525 * When protocol is IPv6, pointer to the underlay IPv6 destination IP526 * which is configured by RIPS.527 * Access: RW528 */529MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_uip_lsb, MLXSW_REG_SFD_BASE_LEN, 0,530		     24, MLXSW_REG_SFD_REC_LEN, 0x0C, false);531 532static inline void533mlxsw_reg_sfd_uc_tunnel_pack(char *payload, int rec_index,534			     enum mlxsw_reg_sfd_rec_policy policy,535			     const char *mac, u16 fid,536			     enum mlxsw_reg_sfd_rec_action action,537			     enum mlxsw_reg_sfd_uc_tunnel_protocol proto)538{539	mlxsw_reg_sfd_rec_pack(payload, rec_index,540			       MLXSW_REG_SFD_REC_TYPE_UNICAST_TUNNEL, mac,541			       action);542	mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy);543	mlxsw_reg_sfd_uc_tunnel_fid_set(payload, rec_index, fid);544	mlxsw_reg_sfd_uc_tunnel_protocol_set(payload, rec_index, proto);545}546 547static inline void548mlxsw_reg_sfd_uc_tunnel_pack4(char *payload, int rec_index,549			      enum mlxsw_reg_sfd_rec_policy policy,550			      const char *mac, u16 fid,551			      enum mlxsw_reg_sfd_rec_action action, u32 uip)552{553	mlxsw_reg_sfd_uc_tunnel_uip_msb_set(payload, rec_index, uip >> 24);554	mlxsw_reg_sfd_uc_tunnel_uip_lsb_set(payload, rec_index, uip);555	mlxsw_reg_sfd_uc_tunnel_pack(payload, rec_index, policy, mac, fid,556				     action,557				     MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV4);558}559 560static inline void561mlxsw_reg_sfd_uc_tunnel_pack6(char *payload, int rec_index, const char *mac,562			      u16 fid, enum mlxsw_reg_sfd_rec_action action,563			      u32 uip_ptr)564{565	mlxsw_reg_sfd_uc_tunnel_uip_lsb_set(payload, rec_index, uip_ptr);566	/* Only static policy is supported for IPv6 unicast tunnel entry. */567	mlxsw_reg_sfd_uc_tunnel_pack(payload, rec_index,568				     MLXSW_REG_SFD_REC_POLICY_STATIC_ENTRY,569				     mac, fid, action,570				     MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV6);571}572 573enum mlxsw_reg_tunnel_port {574	MLXSW_REG_TUNNEL_PORT_NVE,575	MLXSW_REG_TUNNEL_PORT_VPLS,576	MLXSW_REG_TUNNEL_PORT_FLEX_TUNNEL0,577	MLXSW_REG_TUNNEL_PORT_FLEX_TUNNEL1,578};579 580/* SFN - Switch FDB Notification Register581 * -------------------------------------------582 * The switch provides notifications on newly learned FDB entries and583 * aged out entries. The notifications can be polled by software.584 */585#define MLXSW_REG_SFN_ID 0x200B586#define MLXSW_REG_SFN_BASE_LEN 0x10 /* base length, without records */587#define MLXSW_REG_SFN_REC_LEN 0x10 /* record length */588#define MLXSW_REG_SFN_REC_MAX_COUNT 64589#define MLXSW_REG_SFN_LEN (MLXSW_REG_SFN_BASE_LEN +	\590			   MLXSW_REG_SFN_REC_LEN * MLXSW_REG_SFN_REC_MAX_COUNT)591 592MLXSW_REG_DEFINE(sfn, MLXSW_REG_SFN_ID, MLXSW_REG_SFN_LEN);593 594/* reg_sfn_swid595 * Switch partition ID.596 * Access: Index597 */598MLXSW_ITEM32(reg, sfn, swid, 0x00, 24, 8);599 600/* reg_sfn_end601 * Forces the current session to end.602 * Access: OP603 */604MLXSW_ITEM32(reg, sfn, end, 0x04, 20, 1);605 606/* reg_sfn_num_rec607 * Request: Number of learned notifications and aged-out notification608 * records requested.609 * Response: Number of notification records returned (must be smaller610 * than or equal to the value requested)611 * Ranges 0..64612 * Access: OP613 */614MLXSW_ITEM32(reg, sfn, num_rec, 0x04, 0, 8);615 616static inline void mlxsw_reg_sfn_pack(char *payload)617{618	MLXSW_REG_ZERO(sfn, payload);619	mlxsw_reg_sfn_swid_set(payload, 0);620	mlxsw_reg_sfn_end_set(payload, 0);621	mlxsw_reg_sfn_num_rec_set(payload, MLXSW_REG_SFN_REC_MAX_COUNT);622}623 624/* reg_sfn_rec_swid625 * Switch partition ID.626 * Access: RO627 */628MLXSW_ITEM32_INDEXED(reg, sfn, rec_swid, MLXSW_REG_SFN_BASE_LEN, 24, 8,629		     MLXSW_REG_SFN_REC_LEN, 0x00, false);630 631enum mlxsw_reg_sfn_rec_type {632	/* MAC addresses learned on a regular port. */633	MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC = 0x5,634	/* MAC addresses learned on a LAG port. */635	MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC_LAG = 0x6,636	/* Aged-out MAC address on a regular port. */637	MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC = 0x7,638	/* Aged-out MAC address on a LAG port. */639	MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC_LAG = 0x8,640	/* Learned unicast tunnel record. */641	MLXSW_REG_SFN_REC_TYPE_LEARNED_UNICAST_TUNNEL = 0xD,642	/* Aged-out unicast tunnel record. */643	MLXSW_REG_SFN_REC_TYPE_AGED_OUT_UNICAST_TUNNEL = 0xE,644};645 646/* reg_sfn_rec_type647 * Notification record type.648 * Access: RO649 */650MLXSW_ITEM32_INDEXED(reg, sfn, rec_type, MLXSW_REG_SFN_BASE_LEN, 20, 4,651		     MLXSW_REG_SFN_REC_LEN, 0x00, false);652 653/* reg_sfn_rec_mac654 * MAC address.655 * Access: RO656 */657MLXSW_ITEM_BUF_INDEXED(reg, sfn, rec_mac, MLXSW_REG_SFN_BASE_LEN, 6,658		       MLXSW_REG_SFN_REC_LEN, 0x02);659 660/* reg_sfn_mac_sub_port661 * VEPA channel on the local port.662 * 0 if multichannel VEPA is not enabled.663 * Access: RO664 */665MLXSW_ITEM32_INDEXED(reg, sfn, mac_sub_port, MLXSW_REG_SFN_BASE_LEN, 16, 8,666		     MLXSW_REG_SFN_REC_LEN, 0x08, false);667 668/* reg_sfn_mac_fid669 * Filtering identifier.670 * Access: RO671 */672MLXSW_ITEM32_INDEXED(reg, sfn, mac_fid, MLXSW_REG_SFN_BASE_LEN, 0, 16,673		     MLXSW_REG_SFN_REC_LEN, 0x08, false);674 675/* reg_sfn_mac_system_port676 * Unique port identifier for the final destination of the packet.677 * Access: RO678 */679MLXSW_ITEM32_INDEXED(reg, sfn, mac_system_port, MLXSW_REG_SFN_BASE_LEN, 0, 16,680		     MLXSW_REG_SFN_REC_LEN, 0x0C, false);681 682static inline void mlxsw_reg_sfn_mac_unpack(char *payload, int rec_index,683					    char *mac, u16 *p_vid,684					    u16 *p_local_port)685{686	mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac);687	*p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index);688	*p_local_port = mlxsw_reg_sfn_mac_system_port_get(payload, rec_index);689}690 691/* reg_sfn_mac_lag_lag_id692 * LAG ID (pointer into the LAG descriptor table).693 * Access: RO694 */695MLXSW_ITEM32_INDEXED(reg, sfn, mac_lag_lag_id, MLXSW_REG_SFN_BASE_LEN, 0, 10,696		     MLXSW_REG_SFN_REC_LEN, 0x0C, false);697 698static inline void mlxsw_reg_sfn_mac_lag_unpack(char *payload, int rec_index,699						char *mac, u16 *p_vid,700						u16 *p_lag_id)701{702	mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac);703	*p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index);704	*p_lag_id = mlxsw_reg_sfn_mac_lag_lag_id_get(payload, rec_index);705}706 707/* reg_sfn_uc_tunnel_uip_msb708 * When protocol is IPv4, the most significant byte of the underlay IPv4709 * address of the remote VTEP.710 * When protocol is IPv6, reserved.711 * Access: RO712 */713MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_uip_msb, MLXSW_REG_SFN_BASE_LEN, 24,714		     8, MLXSW_REG_SFN_REC_LEN, 0x08, false);715 716enum mlxsw_reg_sfn_uc_tunnel_protocol {717	MLXSW_REG_SFN_UC_TUNNEL_PROTOCOL_IPV4,718	MLXSW_REG_SFN_UC_TUNNEL_PROTOCOL_IPV6,719};720 721/* reg_sfn_uc_tunnel_protocol722 * IP protocol.723 * Access: RO724 */725MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_protocol, MLXSW_REG_SFN_BASE_LEN, 27,726		     1, MLXSW_REG_SFN_REC_LEN, 0x0C, false);727 728/* reg_sfn_uc_tunnel_uip_lsb729 * When protocol is IPv4, the least significant bytes of the underlay730 * IPv4 address of the remote VTEP.731 * When protocol is IPv6, ipv6_id to be queried from TNIPSD.732 * Access: RO733 */734MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_uip_lsb, MLXSW_REG_SFN_BASE_LEN, 0,735		     24, MLXSW_REG_SFN_REC_LEN, 0x0C, false);736 737/* reg_sfn_uc_tunnel_port738 * Tunnel port.739 * Reserved on Spectrum.740 * Access: RO741 */742MLXSW_ITEM32_INDEXED(reg, sfn, tunnel_port, MLXSW_REG_SFN_BASE_LEN, 0, 4,743		     MLXSW_REG_SFN_REC_LEN, 0x10, false);744 745static inline void746mlxsw_reg_sfn_uc_tunnel_unpack(char *payload, int rec_index, char *mac,747			       u16 *p_fid, u32 *p_uip,748			       enum mlxsw_reg_sfn_uc_tunnel_protocol *p_proto)749{750	u32 uip_msb, uip_lsb;751 752	mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac);753	*p_fid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index);754	uip_msb = mlxsw_reg_sfn_uc_tunnel_uip_msb_get(payload, rec_index);755	uip_lsb = mlxsw_reg_sfn_uc_tunnel_uip_lsb_get(payload, rec_index);756	*p_uip = uip_msb << 24 | uip_lsb;757	*p_proto = mlxsw_reg_sfn_uc_tunnel_protocol_get(payload, rec_index);758}759 760/* SPMS - Switch Port MSTP/RSTP State Register761 * -------------------------------------------762 * Configures the spanning tree state of a physical port.763 */764#define MLXSW_REG_SPMS_ID 0x200D765#define MLXSW_REG_SPMS_LEN 0x404766 767MLXSW_REG_DEFINE(spms, MLXSW_REG_SPMS_ID, MLXSW_REG_SPMS_LEN);768 769/* reg_spms_local_port770 * Local port number.771 * Access: Index772 */773MLXSW_ITEM32_LP(reg, spms, 0x00, 16, 0x00, 12);774 775enum mlxsw_reg_spms_state {776	MLXSW_REG_SPMS_STATE_NO_CHANGE,777	MLXSW_REG_SPMS_STATE_DISCARDING,778	MLXSW_REG_SPMS_STATE_LEARNING,779	MLXSW_REG_SPMS_STATE_FORWARDING,780};781 782/* reg_spms_state783 * Spanning tree state of each VLAN ID (VID) of the local port.784 * 0 - Do not change spanning tree state (used only when writing).785 * 1 - Discarding. No learning or forwarding to/from this port (default).786 * 2 - Learning. Port is learning, but not forwarding.787 * 3 - Forwarding. Port is learning and forwarding.788 * Access: RW789 */790MLXSW_ITEM_BIT_ARRAY(reg, spms, state, 0x04, 0x400, 2);791 792static inline void mlxsw_reg_spms_pack(char *payload, u16 local_port)793{794	MLXSW_REG_ZERO(spms, payload);795	mlxsw_reg_spms_local_port_set(payload, local_port);796}797 798static inline void mlxsw_reg_spms_vid_pack(char *payload, u16 vid,799					   enum mlxsw_reg_spms_state state)800{801	mlxsw_reg_spms_state_set(payload, vid, state);802}803 804/* SPVID - Switch Port VID805 * -----------------------806 * The switch port VID configures the default VID for a port.807 */808#define MLXSW_REG_SPVID_ID 0x200E809#define MLXSW_REG_SPVID_LEN 0x08810 811MLXSW_REG_DEFINE(spvid, MLXSW_REG_SPVID_ID, MLXSW_REG_SPVID_LEN);812 813/* reg_spvid_tport814 * Port is tunnel port.815 * Reserved when SwitchX/-2 or Spectrum-1.816 * Access: Index817 */818MLXSW_ITEM32(reg, spvid, tport, 0x00, 24, 1);819 820/* reg_spvid_local_port821 * When tport = 0: Local port number. Not supported for CPU port.822 * When tport = 1: Tunnel port.823 * Access: Index824 */825MLXSW_ITEM32_LP(reg, spvid, 0x00, 16, 0x00, 12);826 827/* reg_spvid_sub_port828 * Virtual port within the physical port.829 * Should be set to 0 when virtual ports are not enabled on the port.830 * Access: Index831 */832MLXSW_ITEM32(reg, spvid, sub_port, 0x00, 8, 8);833 834/* reg_spvid_egr_et_set835 * When VLAN is pushed at ingress (for untagged packets or for836 * QinQ push mode) then the EtherType is decided at the egress port.837 * Reserved when Spectrum-1.838 * Access: RW839 */840MLXSW_ITEM32(reg, spvid, egr_et_set, 0x04, 24, 1);841 842/* reg_spvid_et_vlan843 * EtherType used for when VLAN is pushed at ingress (for untagged844 * packets or for QinQ push mode).845 * 0: ether_type0 - (default)846 * 1: ether_type1847 * 2: ether_type2 - Reserved when Spectrum-1, supported by Spectrum-2848 * Ethertype IDs are configured by SVER.849 * Reserved when egr_et_set = 1.850 * Access: RW851 */852MLXSW_ITEM32(reg, spvid, et_vlan, 0x04, 16, 2);853 854/* reg_spvid_pvid855 * Port default VID856 * Access: RW857 */858MLXSW_ITEM32(reg, spvid, pvid, 0x04, 0, 12);859 860static inline void mlxsw_reg_spvid_pack(char *payload, u16 local_port, u16 pvid,861					u8 et_vlan)862{863	MLXSW_REG_ZERO(spvid, payload);864	mlxsw_reg_spvid_local_port_set(payload, local_port);865	mlxsw_reg_spvid_pvid_set(payload, pvid);866	mlxsw_reg_spvid_et_vlan_set(payload, et_vlan);867}868 869/* SPVM - Switch Port VLAN Membership870 * ----------------------------------871 * The Switch Port VLAN Membership register configures the VLAN membership872 * of a port in a VLAN denoted by VID. VLAN membership is managed per873 * virtual port. The register can be used to add and remove VID(s) from a port.874 */875#define MLXSW_REG_SPVM_ID 0x200F876#define MLXSW_REG_SPVM_BASE_LEN 0x04 /* base length, without records */877#define MLXSW_REG_SPVM_REC_LEN 0x04 /* record length */878#define MLXSW_REG_SPVM_REC_MAX_COUNT 255879#define MLXSW_REG_SPVM_LEN (MLXSW_REG_SPVM_BASE_LEN +	\880		    MLXSW_REG_SPVM_REC_LEN * MLXSW_REG_SPVM_REC_MAX_COUNT)881 882MLXSW_REG_DEFINE(spvm, MLXSW_REG_SPVM_ID, MLXSW_REG_SPVM_LEN);883 884/* reg_spvm_pt885 * Priority tagged. If this bit is set, packets forwarded to the port with886 * untagged VLAN membership (u bit is set) will be tagged with priority tag887 * (VID=0)888 * Access: RW889 */890MLXSW_ITEM32(reg, spvm, pt, 0x00, 31, 1);891 892/* reg_spvm_pte893 * Priority Tagged Update Enable. On Write operations, if this bit is cleared,894 * the pt bit will NOT be updated. To update the pt bit, pte must be set.895 * Access: WO896 */897MLXSW_ITEM32(reg, spvm, pte, 0x00, 30, 1);898 899/* reg_spvm_local_port900 * Local port number.901 * Access: Index902 */903MLXSW_ITEM32_LP(reg, spvm, 0x00, 16, 0x00, 12);904 905/* reg_spvm_sub_port906 * Virtual port within the physical port.907 * Should be set to 0 when virtual ports are not enabled on the port.908 * Access: Index909 */910MLXSW_ITEM32(reg, spvm, sub_port, 0x00, 8, 8);911 912/* reg_spvm_num_rec913 * Number of records to update. Each record contains: i, e, u, vid.914 * Access: OP915 */916MLXSW_ITEM32(reg, spvm, num_rec, 0x00, 0, 8);917 918/* reg_spvm_rec_i919 * Ingress membership in VLAN ID.920 * Access: Index921 */922MLXSW_ITEM32_INDEXED(reg, spvm, rec_i,923		     MLXSW_REG_SPVM_BASE_LEN, 14, 1,924		     MLXSW_REG_SPVM_REC_LEN, 0, false);925 926/* reg_spvm_rec_e927 * Egress membership in VLAN ID.928 * Access: Index929 */930MLXSW_ITEM32_INDEXED(reg, spvm, rec_e,931		     MLXSW_REG_SPVM_BASE_LEN, 13, 1,932		     MLXSW_REG_SPVM_REC_LEN, 0, false);933 934/* reg_spvm_rec_u935 * Untagged - port is an untagged member - egress transmission uses untagged936 * frames on VID<n>937 * Access: Index938 */939MLXSW_ITEM32_INDEXED(reg, spvm, rec_u,940		     MLXSW_REG_SPVM_BASE_LEN, 12, 1,941		     MLXSW_REG_SPVM_REC_LEN, 0, false);942 943/* reg_spvm_rec_vid944 * Egress membership in VLAN ID.945 * Access: Index946 */947MLXSW_ITEM32_INDEXED(reg, spvm, rec_vid,948		     MLXSW_REG_SPVM_BASE_LEN, 0, 12,949		     MLXSW_REG_SPVM_REC_LEN, 0, false);950 951static inline void mlxsw_reg_spvm_pack(char *payload, u16 local_port,952				       u16 vid_begin, u16 vid_end,953				       bool is_member, bool untagged)954{955	int size = vid_end - vid_begin + 1;956	int i;957 958	MLXSW_REG_ZERO(spvm, payload);959	mlxsw_reg_spvm_local_port_set(payload, local_port);960	mlxsw_reg_spvm_num_rec_set(payload, size);961 962	for (i = 0; i < size; i++) {963		mlxsw_reg_spvm_rec_i_set(payload, i, is_member);964		mlxsw_reg_spvm_rec_e_set(payload, i, is_member);965		mlxsw_reg_spvm_rec_u_set(payload, i, untagged);966		mlxsw_reg_spvm_rec_vid_set(payload, i, vid_begin + i);967	}968}969 970/* SPAFT - Switch Port Acceptable Frame Types971 * ------------------------------------------972 * The Switch Port Acceptable Frame Types register configures the frame973 * admittance of the port.974 */975#define MLXSW_REG_SPAFT_ID 0x2010976#define MLXSW_REG_SPAFT_LEN 0x08977 978MLXSW_REG_DEFINE(spaft, MLXSW_REG_SPAFT_ID, MLXSW_REG_SPAFT_LEN);979 980/* reg_spaft_local_port981 * Local port number.982 * Access: Index983 *984 * Note: CPU port is not supported (all tag types are allowed).985 */986MLXSW_ITEM32_LP(reg, spaft, 0x00, 16, 0x00, 12);987 988/* reg_spaft_sub_port989 * Virtual port within the physical port.990 * Should be set to 0 when virtual ports are not enabled on the port.991 * Access: RW992 */993MLXSW_ITEM32(reg, spaft, sub_port, 0x00, 8, 8);994 995/* reg_spaft_allow_untagged996 * When set, untagged frames on the ingress are allowed (default).997 * Access: RW998 */999MLXSW_ITEM32(reg, spaft, allow_untagged, 0x04, 31, 1);1000 1001/* reg_spaft_allow_prio_tagged1002 * When set, priority tagged frames on the ingress are allowed (default).1003 * Access: RW1004 */1005MLXSW_ITEM32(reg, spaft, allow_prio_tagged, 0x04, 30, 1);1006 1007/* reg_spaft_allow_tagged1008 * When set, tagged frames on the ingress are allowed (default).1009 * Access: RW1010 */1011MLXSW_ITEM32(reg, spaft, allow_tagged, 0x04, 29, 1);1012 1013static inline void mlxsw_reg_spaft_pack(char *payload, u16 local_port,1014					bool allow_untagged)1015{1016	MLXSW_REG_ZERO(spaft, payload);1017	mlxsw_reg_spaft_local_port_set(payload, local_port);1018	mlxsw_reg_spaft_allow_untagged_set(payload, allow_untagged);1019	mlxsw_reg_spaft_allow_prio_tagged_set(payload, allow_untagged);1020	mlxsw_reg_spaft_allow_tagged_set(payload, true);1021}1022 1023/* SFGC - Switch Flooding Group Configuration1024 * ------------------------------------------1025 * The following register controls the association of flooding tables and MIDs1026 * to packet types used for flooding.1027 *1028 * Reserved when CONFIG_PROFILE.flood_mode = CFF.1029 */1030#define MLXSW_REG_SFGC_ID 0x20111031#define MLXSW_REG_SFGC_LEN 0x141032 1033MLXSW_REG_DEFINE(sfgc, MLXSW_REG_SFGC_ID, MLXSW_REG_SFGC_LEN);1034 1035enum mlxsw_reg_sfgc_type {1036	MLXSW_REG_SFGC_TYPE_BROADCAST,1037	MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST,1038	MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV4,1039	MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV6,1040	MLXSW_REG_SFGC_TYPE_RESERVED,1041	MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_NON_IP,1042	MLXSW_REG_SFGC_TYPE_IPV4_LINK_LOCAL,1043	MLXSW_REG_SFGC_TYPE_IPV6_ALL_HOST,1044	MLXSW_REG_SFGC_TYPE_MAX,1045};1046 1047/* reg_sfgc_type1048 * The traffic type to reach the flooding table.1049 * Access: Index1050 */1051MLXSW_ITEM32(reg, sfgc, type, 0x00, 0, 4);1052 1053/* bridge_type is used in SFGC and SFMR. */1054enum mlxsw_reg_bridge_type {1055	MLXSW_REG_BRIDGE_TYPE_0 = 0, /* Used for .1q FIDs. */1056	MLXSW_REG_BRIDGE_TYPE_1 = 1, /* Used for .1d FIDs. */1057};1058 1059/* reg_sfgc_bridge_type1060 * Access: Index1061 *1062 * Note: SwitchX-2 only supports 802.1Q mode.1063 */1064MLXSW_ITEM32(reg, sfgc, bridge_type, 0x04, 24, 3);1065 1066enum mlxsw_flood_table_type {1067	MLXSW_REG_SFGC_TABLE_TYPE_VID = 1,1068	MLXSW_REG_SFGC_TABLE_TYPE_SINGLE = 2,1069	MLXSW_REG_SFGC_TABLE_TYPE_ANY = 0,1070	MLXSW_REG_SFGC_TABLE_TYPE_FID_OFFSET = 3,1071	MLXSW_REG_SFGC_TABLE_TYPE_FID = 4,1072};1073 1074/* reg_sfgc_table_type1075 * See mlxsw_flood_table_type1076 * Access: RW1077 *1078 * Note: FID offset and FID types are not supported in SwitchX-2.1079 */1080MLXSW_ITEM32(reg, sfgc, table_type, 0x04, 16, 3);1081 1082/* reg_sfgc_flood_table1083 * Flooding table index to associate with the specific type on the specific1084 * switch partition.1085 * Access: RW1086 */1087MLXSW_ITEM32(reg, sfgc, flood_table, 0x04, 0, 6);1088 1089/* reg_sfgc_counter_set_type1090 * Counter Set Type for flow counters.1091 * Access: RW1092 */1093MLXSW_ITEM32(reg, sfgc, counter_set_type, 0x0C, 24, 8);1094 1095/* reg_sfgc_counter_index1096 * Counter Index for flow counters.1097 * Access: RW1098 */1099MLXSW_ITEM32(reg, sfgc, counter_index, 0x0C, 0, 24);1100 1101/* reg_sfgc_mid_base1102 * MID Base.1103 * Access: RW1104 *1105 * Note: Reserved when legacy bridge model is used.1106 */1107MLXSW_ITEM32(reg, sfgc, mid_base, 0x10, 0, 16);1108 1109static inline void1110mlxsw_reg_sfgc_pack(char *payload, enum mlxsw_reg_sfgc_type type,1111		    enum mlxsw_reg_bridge_type bridge_type,1112		    enum mlxsw_flood_table_type table_type,1113		    unsigned int flood_table, u16 mid_base)1114{1115	MLXSW_REG_ZERO(sfgc, payload);1116	mlxsw_reg_sfgc_type_set(payload, type);1117	mlxsw_reg_sfgc_bridge_type_set(payload, bridge_type);1118	mlxsw_reg_sfgc_table_type_set(payload, table_type);1119	mlxsw_reg_sfgc_flood_table_set(payload, flood_table);1120	mlxsw_reg_sfgc_mid_base_set(payload, mid_base);1121}1122 1123/* SFDF - Switch Filtering DB Flush1124 * --------------------------------1125 * The switch filtering DB flush register is used to flush the FDB.1126 * Note that FDB notifications are flushed as well.1127 */1128#define MLXSW_REG_SFDF_ID 0x20131129#define MLXSW_REG_SFDF_LEN 0x141130 1131MLXSW_REG_DEFINE(sfdf, MLXSW_REG_SFDF_ID, MLXSW_REG_SFDF_LEN);1132 1133/* reg_sfdf_swid1134 * Switch partition ID.1135 * Access: Index1136 */1137MLXSW_ITEM32(reg, sfdf, swid, 0x00, 24, 8);1138 1139enum mlxsw_reg_sfdf_flush_type {1140	MLXSW_REG_SFDF_FLUSH_PER_SWID,1141	MLXSW_REG_SFDF_FLUSH_PER_FID,1142	MLXSW_REG_SFDF_FLUSH_PER_PORT,1143	MLXSW_REG_SFDF_FLUSH_PER_PORT_AND_FID,1144	MLXSW_REG_SFDF_FLUSH_PER_LAG,1145	MLXSW_REG_SFDF_FLUSH_PER_LAG_AND_FID,1146	MLXSW_REG_SFDF_FLUSH_PER_NVE,1147	MLXSW_REG_SFDF_FLUSH_PER_NVE_AND_FID,1148};1149 1150/* reg_sfdf_flush_type1151 * Flush type.1152 * 0 - All SWID dynamic entries are flushed.1153 * 1 - All FID dynamic entries are flushed.1154 * 2 - All dynamic entries pointing to port are flushed.1155 * 3 - All FID dynamic entries pointing to port are flushed.1156 * 4 - All dynamic entries pointing to LAG are flushed.1157 * 5 - All FID dynamic entries pointing to LAG are flushed.1158 * 6 - All entries of type "Unicast Tunnel" or "Multicast Tunnel" are1159 *     flushed.1160 * 7 - All entries of type "Unicast Tunnel" or "Multicast Tunnel" are1161 *     flushed, per FID.1162 * Access: RW1163 */1164MLXSW_ITEM32(reg, sfdf, flush_type, 0x04, 28, 4);1165 1166/* reg_sfdf_flush_static1167 * Static.1168 * 0 - Flush only dynamic entries.1169 * 1 - Flush both dynamic and static entries.1170 * Access: RW1171 */1172MLXSW_ITEM32(reg, sfdf, flush_static, 0x04, 24, 1);1173 1174static inline void mlxsw_reg_sfdf_pack(char *payload,1175				       enum mlxsw_reg_sfdf_flush_type type)1176{1177	MLXSW_REG_ZERO(sfdf, payload);1178	mlxsw_reg_sfdf_flush_type_set(payload, type);1179	mlxsw_reg_sfdf_flush_static_set(payload, true);1180}1181 1182/* reg_sfdf_fid1183 * FID to flush.1184 * Access: RW1185 */1186MLXSW_ITEM32(reg, sfdf, fid, 0x0C, 0, 16);1187 1188/* reg_sfdf_system_port1189 * Port to flush.1190 * Access: RW1191 */1192MLXSW_ITEM32(reg, sfdf, system_port, 0x0C, 0, 16);1193 1194/* reg_sfdf_port_fid_system_port1195 * Port to flush, pointed to by FID.1196 * Access: RW1197 */1198MLXSW_ITEM32(reg, sfdf, port_fid_system_port, 0x08, 0, 16);1199 1200/* reg_sfdf_lag_id1201 * LAG ID to flush.1202 * Access: RW1203 */1204MLXSW_ITEM32(reg, sfdf, lag_id, 0x0C, 0, 10);1205 1206/* reg_sfdf_lag_fid_lag_id1207 * LAG ID to flush, pointed to by FID.1208 * Access: RW1209 */1210MLXSW_ITEM32(reg, sfdf, lag_fid_lag_id, 0x08, 0, 10);1211 1212/* SLDR - Switch LAG Descriptor Register1213 * -----------------------------------------1214 * The switch LAG descriptor register is populated by LAG descriptors.1215 * Each LAG descriptor is indexed by lag_id. The LAG ID runs from 0 to1216 * max_lag-1.1217 */1218#define MLXSW_REG_SLDR_ID 0x20141219#define MLXSW_REG_SLDR_LEN 0x0C /* counting in only one port in list */1220 1221MLXSW_REG_DEFINE(sldr, MLXSW_REG_SLDR_ID, MLXSW_REG_SLDR_LEN);1222 1223enum mlxsw_reg_sldr_op {1224	/* Indicates a creation of a new LAG-ID, lag_id must be valid */1225	MLXSW_REG_SLDR_OP_LAG_CREATE,1226	MLXSW_REG_SLDR_OP_LAG_DESTROY,1227	/* Ports that appear in the list have the Distributor enabled */1228	MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST,1229	/* Removes ports from the disributor list */1230	MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST,1231};1232 1233/* reg_sldr_op1234 * Operation.1235 * Access: RW1236 */1237MLXSW_ITEM32(reg, sldr, op, 0x00, 29, 3);1238 1239/* reg_sldr_lag_id1240 * LAG identifier. The lag_id is the index into the LAG descriptor table.1241 * Access: Index1242 */1243MLXSW_ITEM32(reg, sldr, lag_id, 0x00, 0, 10);1244 1245static inline void mlxsw_reg_sldr_lag_create_pack(char *payload, u8 lag_id)1246{1247	MLXSW_REG_ZERO(sldr, payload);1248	mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_CREATE);1249	mlxsw_reg_sldr_lag_id_set(payload, lag_id);1250}1251 1252static inline void mlxsw_reg_sldr_lag_destroy_pack(char *payload, u8 lag_id)1253{1254	MLXSW_REG_ZERO(sldr, payload);1255	mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_DESTROY);1256	mlxsw_reg_sldr_lag_id_set(payload, lag_id);1257}1258 1259/* reg_sldr_num_ports1260 * The number of member ports of the LAG.1261 * Reserved for Create / Destroy operations1262 * For Add / Remove operations - indicates the number of ports in the list.1263 * Access: RW1264 */1265MLXSW_ITEM32(reg, sldr, num_ports, 0x04, 24, 8);1266 1267/* reg_sldr_system_port1268 * System port.1269 * Access: RW1270 */1271MLXSW_ITEM32_INDEXED(reg, sldr, system_port, 0x08, 0, 16, 4, 0, false);1272 1273static inline void mlxsw_reg_sldr_lag_add_port_pack(char *payload, u8 lag_id,1274						    u16 local_port)1275{1276	MLXSW_REG_ZERO(sldr, payload);1277	mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST);1278	mlxsw_reg_sldr_lag_id_set(payload, lag_id);1279	mlxsw_reg_sldr_num_ports_set(payload, 1);1280	mlxsw_reg_sldr_system_port_set(payload, 0, local_port);1281}1282 1283static inline void mlxsw_reg_sldr_lag_remove_port_pack(char *payload, u8 lag_id,1284						       u16 local_port)1285{1286	MLXSW_REG_ZERO(sldr, payload);1287	mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST);1288	mlxsw_reg_sldr_lag_id_set(payload, lag_id);1289	mlxsw_reg_sldr_num_ports_set(payload, 1);1290	mlxsw_reg_sldr_system_port_set(payload, 0, local_port);1291}1292 1293/* SLCR - Switch LAG Configuration 2 Register1294 * -------------------------------------------1295 * The Switch LAG Configuration register is used for configuring the1296 * LAG properties of the switch.1297 */1298#define MLXSW_REG_SLCR_ID 0x20151299#define MLXSW_REG_SLCR_LEN 0x101300 1301MLXSW_REG_DEFINE(slcr, MLXSW_REG_SLCR_ID, MLXSW_REG_SLCR_LEN);1302 1303enum mlxsw_reg_slcr_pp {1304	/* Global Configuration (for all ports) */1305	MLXSW_REG_SLCR_PP_GLOBAL,1306	/* Per port configuration, based on local_port field */1307	MLXSW_REG_SLCR_PP_PER_PORT,1308};1309 1310/* reg_slcr_pp1311 * Per Port Configuration1312 * Note: Reading at Global mode results in reading port 1 configuration.1313 * Access: Index1314 */1315MLXSW_ITEM32(reg, slcr, pp, 0x00, 24, 1);1316 1317/* reg_slcr_local_port1318 * Local port number1319 * Supported from CPU port1320 * Not supported from router port1321 * Reserved when pp = Global Configuration1322 * Access: Index1323 */1324MLXSW_ITEM32_LP(reg, slcr, 0x00, 16, 0x00, 12);1325 1326enum mlxsw_reg_slcr_type {1327	MLXSW_REG_SLCR_TYPE_CRC, /* default */1328	MLXSW_REG_SLCR_TYPE_XOR,1329	MLXSW_REG_SLCR_TYPE_RANDOM,1330};1331 1332/* reg_slcr_type1333 * Hash type1334 * Access: RW1335 */1336MLXSW_ITEM32(reg, slcr, type, 0x00, 0, 4);1337 1338/* Ingress port */1339#define MLXSW_REG_SLCR_LAG_HASH_IN_PORT		BIT(0)1340/* SMAC - for IPv4 and IPv6 packets */1341#define MLXSW_REG_SLCR_LAG_HASH_SMAC_IP		BIT(1)1342/* SMAC - for non-IP packets */1343#define MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP	BIT(2)1344#define MLXSW_REG_SLCR_LAG_HASH_SMAC \1345	(MLXSW_REG_SLCR_LAG_HASH_SMAC_IP | \1346	 MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP)1347/* DMAC - for IPv4 and IPv6 packets */1348#define MLXSW_REG_SLCR_LAG_HASH_DMAC_IP		BIT(3)1349/* DMAC - for non-IP packets */1350#define MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP	BIT(4)1351#define MLXSW_REG_SLCR_LAG_HASH_DMAC \1352	(MLXSW_REG_SLCR_LAG_HASH_DMAC_IP | \1353	 MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP)1354/* Ethertype - for IPv4 and IPv6 packets */1355#define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP	BIT(5)1356/* Ethertype - for non-IP packets */1357#define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP	BIT(6)1358#define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE \1359	(MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP | \1360	 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP)1361/* VLAN ID - for IPv4 and IPv6 packets */1362#define MLXSW_REG_SLCR_LAG_HASH_VLANID_IP	BIT(7)1363/* VLAN ID - for non-IP packets */1364#define MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP	BIT(8)1365#define MLXSW_REG_SLCR_LAG_HASH_VLANID \1366	(MLXSW_REG_SLCR_LAG_HASH_VLANID_IP | \1367	 MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP)1368/* Source IP address (can be IPv4 or IPv6) */1369#define MLXSW_REG_SLCR_LAG_HASH_SIP		BIT(9)1370/* Destination IP address (can be IPv4 or IPv6) */1371#define MLXSW_REG_SLCR_LAG_HASH_DIP		BIT(10)1372/* TCP/UDP source port */1373#define MLXSW_REG_SLCR_LAG_HASH_SPORT		BIT(11)1374/* TCP/UDP destination port*/1375#define MLXSW_REG_SLCR_LAG_HASH_DPORT		BIT(12)1376/* IPv4 Protocol/IPv6 Next Header */1377#define MLXSW_REG_SLCR_LAG_HASH_IPPROTO		BIT(13)1378/* IPv6 Flow label */1379#define MLXSW_REG_SLCR_LAG_HASH_FLOWLABEL	BIT(14)1380/* SID - FCoE source ID */1381#define MLXSW_REG_SLCR_LAG_HASH_FCOE_SID	BIT(15)1382/* DID - FCoE destination ID */1383#define MLXSW_REG_SLCR_LAG_HASH_FCOE_DID	BIT(16)1384/* OXID - FCoE originator exchange ID */1385#define MLXSW_REG_SLCR_LAG_HASH_FCOE_OXID	BIT(17)1386/* Destination QP number - for RoCE packets */1387#define MLXSW_REG_SLCR_LAG_HASH_ROCE_DQP	BIT(19)1388 1389/* reg_slcr_lag_hash1390 * LAG hashing configuration. This is a bitmask, in which each set1391 * bit includes the corresponding item in the LAG hash calculation.1392 * The default lag_hash contains SMAC, DMAC, VLANID and1393 * Ethertype (for all packet types).1394 * Access: RW1395 */1396MLXSW_ITEM32(reg, slcr, lag_hash, 0x04, 0, 20);1397 1398/* reg_slcr_seed1399 * LAG seed value. The seed is the same for all ports.1400 * Access: RW1401 */1402MLXSW_ITEM32(reg, slcr, seed, 0x08, 0, 32);1403 1404static inline void mlxsw_reg_slcr_pack(char *payload, u16 lag_hash, u32 seed)1405{1406	MLXSW_REG_ZERO(slcr, payload);1407	mlxsw_reg_slcr_pp_set(payload, MLXSW_REG_SLCR_PP_GLOBAL);1408	mlxsw_reg_slcr_type_set(payload, MLXSW_REG_SLCR_TYPE_CRC);1409	mlxsw_reg_slcr_lag_hash_set(payload, lag_hash);1410	mlxsw_reg_slcr_seed_set(payload, seed);1411}1412 1413/* SLCOR - Switch LAG Collector Register1414 * -------------------------------------1415 * The Switch LAG Collector register controls the Local Port membership1416 * in a LAG and enablement of the collector.1417 */1418#define MLXSW_REG_SLCOR_ID 0x20161419#define MLXSW_REG_SLCOR_LEN 0x101420 1421MLXSW_REG_DEFINE(slcor, MLXSW_REG_SLCOR_ID, MLXSW_REG_SLCOR_LEN);1422 1423enum mlxsw_reg_slcor_col {1424	/* Port is added with collector disabled */1425	MLXSW_REG_SLCOR_COL_LAG_ADD_PORT,1426	MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED,1427	MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_DISABLED,1428	MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT,1429};1430 1431/* reg_slcor_col1432 * Collector configuration1433 * Access: RW1434 */1435MLXSW_ITEM32(reg, slcor, col, 0x00, 30, 2);1436 1437/* reg_slcor_local_port1438 * Local port number1439 * Not supported for CPU port1440 * Access: Index1441 */1442MLXSW_ITEM32_LP(reg, slcor, 0x00, 16, 0x00, 12);1443 1444/* reg_slcor_lag_id1445 * LAG Identifier. Index into the LAG descriptor table.1446 * Access: Index1447 */1448MLXSW_ITEM32(reg, slcor, lag_id, 0x00, 0, 10);1449 1450/* reg_slcor_port_index1451 * Port index in the LAG list. Only valid on Add Port to LAG col.1452 * Valid range is from 0 to cap_max_lag_members-11453 * Access: RW1454 */1455MLXSW_ITEM32(reg, slcor, port_index, 0x04, 0, 10);1456 1457static inline void mlxsw_reg_slcor_pack(char *payload,1458					u16 local_port, u16 lag_id,1459					enum mlxsw_reg_slcor_col col)1460{1461	MLXSW_REG_ZERO(slcor, payload);1462	mlxsw_reg_slcor_col_set(payload, col);1463	mlxsw_reg_slcor_local_port_set(payload, local_port);1464	mlxsw_reg_slcor_lag_id_set(payload, lag_id);1465}1466 1467static inline void mlxsw_reg_slcor_port_add_pack(char *payload,1468						 u16 local_port, u16 lag_id,1469						 u8 port_index)1470{1471	mlxsw_reg_slcor_pack(payload, local_port, lag_id,1472			     MLXSW_REG_SLCOR_COL_LAG_ADD_PORT);1473	mlxsw_reg_slcor_port_index_set(payload, port_index);1474}1475 1476static inline void mlxsw_reg_slcor_port_remove_pack(char *payload,1477						    u16 local_port, u16 lag_id)1478{1479	mlxsw_reg_slcor_pack(payload, local_port, lag_id,1480			     MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT);1481}1482 1483static inline void mlxsw_reg_slcor_col_enable_pack(char *payload,1484						   u16 local_port, u16 lag_id)1485{1486	mlxsw_reg_slcor_pack(payload, local_port, lag_id,1487			     MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED);1488}1489 1490static inline void mlxsw_reg_slcor_col_disable_pack(char *payload,1491						    u16 local_port, u16 lag_id)1492{1493	mlxsw_reg_slcor_pack(payload, local_port, lag_id,1494			     MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED);1495}1496 1497/* SPMLR - Switch Port MAC Learning Register1498 * -----------------------------------------1499 * Controls the Switch MAC learning policy per port.1500 */1501#define MLXSW_REG_SPMLR_ID 0x20181502#define MLXSW_REG_SPMLR_LEN 0x81503 1504MLXSW_REG_DEFINE(spmlr, MLXSW_REG_SPMLR_ID, MLXSW_REG_SPMLR_LEN);1505 1506/* reg_spmlr_local_port1507 * Local port number.1508 * Access: Index1509 */1510MLXSW_ITEM32_LP(reg, spmlr, 0x00, 16, 0x00, 12);1511 1512/* reg_spmlr_sub_port1513 * Virtual port within the physical port.1514 * Should be set to 0 when virtual ports are not enabled on the port.1515 * Access: Index1516 */1517MLXSW_ITEM32(reg, spmlr, sub_port, 0x00, 8, 8);1518 1519enum mlxsw_reg_spmlr_learn_mode {1520	MLXSW_REG_SPMLR_LEARN_MODE_DISABLE = 0,1521	MLXSW_REG_SPMLR_LEARN_MODE_ENABLE = 2,1522	MLXSW_REG_SPMLR_LEARN_MODE_SEC = 3,1523};1524 1525/* reg_spmlr_learn_mode1526 * Learning mode on the port.1527 * 0 - Learning disabled.1528 * 2 - Learning enabled.1529 * 3 - Security mode.1530 *1531 * In security mode the switch does not learn MACs on the port, but uses the1532 * SMAC to see if it exists on another ingress port. If so, the packet is1533 * classified as a bad packet and is discarded unless the software registers1534 * to receive port security error packets usign HPKT.1535 */1536MLXSW_ITEM32(reg, spmlr, learn_mode, 0x04, 30, 2);1537 1538static inline void mlxsw_reg_spmlr_pack(char *payload, u16 local_port,1539					enum mlxsw_reg_spmlr_learn_mode mode)1540{1541	MLXSW_REG_ZERO(spmlr, payload);1542	mlxsw_reg_spmlr_local_port_set(payload, local_port);1543	mlxsw_reg_spmlr_sub_port_set(payload, 0);1544	mlxsw_reg_spmlr_learn_mode_set(payload, mode);1545}1546 1547/* SVFA - Switch VID to FID Allocation Register1548 * --------------------------------------------1549 * Controls the VID to FID mapping and {Port, VID} to FID mapping for1550 * virtualized ports.1551 */1552#define MLXSW_REG_SVFA_ID 0x201C1553#define MLXSW_REG_SVFA_LEN 0x181554 1555MLXSW_REG_DEFINE(svfa, MLXSW_REG_SVFA_ID, MLXSW_REG_SVFA_LEN);1556 1557/* reg_svfa_swid1558 * Switch partition ID.1559 * Access: Index1560 */1561MLXSW_ITEM32(reg, svfa, swid, 0x00, 24, 8);1562 1563/* reg_svfa_local_port1564 * Local port number.1565 * Access: Index1566 *1567 * Note: Reserved for 802.1Q FIDs.1568 */1569MLXSW_ITEM32_LP(reg, svfa, 0x00, 16, 0x00, 12);1570 1571enum mlxsw_reg_svfa_mt {1572	MLXSW_REG_SVFA_MT_VID_TO_FID,1573	MLXSW_REG_SVFA_MT_PORT_VID_TO_FID,1574	MLXSW_REG_SVFA_MT_VNI_TO_FID,1575};1576 1577/* reg_svfa_mapping_table1578 * Mapping table:1579 * 0 - VID to FID1580 * 1 - {Port, VID} to FID1581 * Access: Index1582 *1583 * Note: Reserved for SwitchX-2.1584 */1585MLXSW_ITEM32(reg, svfa, mapping_table, 0x00, 8, 3);1586 1587/* reg_svfa_v1588 * Valid.1589 * Valid if set.1590 * Access: RW1591 *1592 * Note: Reserved for SwitchX-2.1593 */1594MLXSW_ITEM32(reg, svfa, v, 0x00, 0, 1);1595 1596/* reg_svfa_fid1597 * Filtering ID.1598 * Access: RW1599 */1600MLXSW_ITEM32(reg, svfa, fid, 0x04, 16, 16);1601 1602/* reg_svfa_vid1603 * VLAN ID.1604 * Access: Index1605 */1606MLXSW_ITEM32(reg, svfa, vid, 0x04, 0, 12);1607 1608/* reg_svfa_counter_set_type1609 * Counter set type for flow counters.1610 * Access: RW1611 *1612 * Note: Reserved for SwitchX-2.1613 */1614MLXSW_ITEM32(reg, svfa, counter_set_type, 0x08, 24, 8);1615 1616/* reg_svfa_counter_index1617 * Counter index for flow counters.1618 * Access: RW1619 *1620 * Note: Reserved for SwitchX-2.1621 */1622MLXSW_ITEM32(reg, svfa, counter_index, 0x08, 0, 24);1623 1624/* reg_svfa_vni1625 * Virtual Network Identifier.1626 * Access: Index1627 *1628 * Note: Reserved when mapping_table is not 2 (VNI mapping table).1629 */1630MLXSW_ITEM32(reg, svfa, vni, 0x10, 0, 24);1631 1632/* reg_svfa_irif_v1633 * Ingress RIF valid.1634 * 0 - Ingress RIF is not valid, no ingress RIF assigned.1635 * 1 - Ingress RIF valid.1636 * Must not be set for a non enabled RIF.1637 * Access: RW1638 *1639 * Note: Reserved when legacy bridge model is used.1640 */1641MLXSW_ITEM32(reg, svfa, irif_v, 0x14, 24, 1);1642 1643/* reg_svfa_irif1644 * Ingress RIF (Router Interface).1645 * Range is 0..cap_max_router_interfaces-1.1646 * Access: RW1647 *1648 * Note: Reserved when legacy bridge model is used and when irif_v=0.1649 */1650MLXSW_ITEM32(reg, svfa, irif, 0x14, 0, 16);1651 1652static inline void __mlxsw_reg_svfa_pack(char *payload,1653					 enum mlxsw_reg_svfa_mt mt, bool valid,1654					 u16 fid, bool irif_v, u16 irif)1655{1656	MLXSW_REG_ZERO(svfa, payload);1657	mlxsw_reg_svfa_swid_set(payload, 0);1658	mlxsw_reg_svfa_mapping_table_set(payload, mt);1659	mlxsw_reg_svfa_v_set(payload, valid);1660	mlxsw_reg_svfa_fid_set(payload, fid);1661	mlxsw_reg_svfa_irif_v_set(payload, irif_v);1662	mlxsw_reg_svfa_irif_set(payload, irif_v ? irif : 0);1663}1664 1665static inline void mlxsw_reg_svfa_port_vid_pack(char *payload, u16 local_port,1666						bool valid, u16 fid, u16 vid,1667						bool irif_v, u16 irif)1668{1669	enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_PORT_VID_TO_FID;1670 1671	__mlxsw_reg_svfa_pack(payload, mt, valid, fid, irif_v, irif);1672	mlxsw_reg_svfa_local_port_set(payload, local_port);1673	mlxsw_reg_svfa_vid_set(payload, vid);1674}1675 1676static inline void mlxsw_reg_svfa_vid_pack(char *payload, bool valid, u16 fid,1677					   u16 vid, bool irif_v, u16 irif)1678{1679	enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_VID_TO_FID;1680 1681	__mlxsw_reg_svfa_pack(payload, mt, valid, fid, irif_v, irif);1682	mlxsw_reg_svfa_vid_set(payload, vid);1683}1684 1685static inline void mlxsw_reg_svfa_vni_pack(char *payload, bool valid, u16 fid,1686					   u32 vni, bool irif_v, u16 irif)1687{1688	enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_VNI_TO_FID;1689 1690	__mlxsw_reg_svfa_pack(payload, mt, valid, fid, irif_v, irif);1691	mlxsw_reg_svfa_vni_set(payload, vni);1692}1693 1694/*  SPVTR - Switch Port VLAN Stacking Register1695 *  ------------------------------------------1696 *  The Switch Port VLAN Stacking register configures the VLAN mode of the port1697 *  to enable VLAN stacking.1698 */1699#define MLXSW_REG_SPVTR_ID 0x201D1700#define MLXSW_REG_SPVTR_LEN 0x101701 1702MLXSW_REG_DEFINE(spvtr, MLXSW_REG_SPVTR_ID, MLXSW_REG_SPVTR_LEN);1703 1704/* reg_spvtr_tport1705 * Port is tunnel port.1706 * Access: Index1707 *1708 * Note: Reserved when SwitchX/-2 or Spectrum-1.1709 */1710MLXSW_ITEM32(reg, spvtr, tport, 0x00, 24, 1);1711 1712/* reg_spvtr_local_port1713 * When tport = 0: local port number (Not supported from/to CPU).1714 * When tport = 1: tunnel port.1715 * Access: Index1716 */1717MLXSW_ITEM32_LP(reg, spvtr, 0x00, 16, 0x00, 12);1718 1719/* reg_spvtr_ippe1720 * Ingress Port Prio Mode Update Enable.1721 * When set, the Port Prio Mode is updated with the provided ipprio_mode field.1722 * Reserved on Get operations.1723 * Access: OP1724 */1725MLXSW_ITEM32(reg, spvtr, ippe, 0x04, 31, 1);1726 1727/* reg_spvtr_ipve1728 * Ingress Port VID Mode Update Enable.1729 * When set, the Ingress Port VID Mode is updated with the provided ipvid_mode1730 * field.1731 * Reserved on Get operations.1732 * Access: OP1733 */1734MLXSW_ITEM32(reg, spvtr, ipve, 0x04, 30, 1);1735 1736/* reg_spvtr_epve1737 * Egress Port VID Mode Update Enable.1738 * When set, the Egress Port VID Mode is updated with the provided epvid_mode1739 * field.1740 * Access: OP1741 */1742MLXSW_ITEM32(reg, spvtr, epve, 0x04, 29, 1);1743 1744/* reg_spvtr_ipprio_mode1745 * Ingress Port Priority Mode.1746 * This controls the PCP and DEI of the new outer VLAN1747 * Note: for SwitchX/-2 the DEI is not affected.1748 * 0: use port default PCP and DEI (configured by QPDPC).1749 * 1: use C-VLAN PCP and DEI.1750 * Has no effect when ipvid_mode = 0.1751 * Reserved when tport = 1.1752 * Access: RW1753 */1754MLXSW_ITEM32(reg, spvtr, ipprio_mode, 0x04, 20, 4);1755 1756enum mlxsw_reg_spvtr_ipvid_mode {1757	/* IEEE Compliant PVID (default) */1758	MLXSW_REG_SPVTR_IPVID_MODE_IEEE_COMPLIANT_PVID,1759	/* Push VLAN (for VLAN stacking, except prio tagged packets) */1760	MLXSW_REG_SPVTR_IPVID_MODE_PUSH_VLAN_FOR_UNTAGGED_PACKET,1761	/* Always push VLAN (also for prio tagged packets) */1762	MLXSW_REG_SPVTR_IPVID_MODE_ALWAYS_PUSH_VLAN,1763};1764 1765/* reg_spvtr_ipvid_mode1766 * Ingress Port VLAN-ID Mode.1767 * For Spectrum family, this affects the values of SPVM.i1768 * Access: RW1769 */1770MLXSW_ITEM32(reg, spvtr, ipvid_mode, 0x04, 16, 4);1771 1772enum mlxsw_reg_spvtr_epvid_mode {1773	/* IEEE Compliant VLAN membership */1774	MLXSW_REG_SPVTR_EPVID_MODE_IEEE_COMPLIANT_VLAN_MEMBERSHIP,1775	/* Pop VLAN (for VLAN stacking) */1776	MLXSW_REG_SPVTR_EPVID_MODE_POP_VLAN,1777};1778 1779/* reg_spvtr_epvid_mode1780 * Egress Port VLAN-ID Mode.1781 * For Spectrum family, this affects the values of SPVM.e,u,pt.1782 * Access: WO1783 */1784MLXSW_ITEM32(reg, spvtr, epvid_mode, 0x04, 0, 4);1785 1786static inline void mlxsw_reg_spvtr_pack(char *payload, bool tport,1787					u16 local_port,1788					enum mlxsw_reg_spvtr_ipvid_mode ipvid_mode)1789{1790	MLXSW_REG_ZERO(spvtr, payload);1791	mlxsw_reg_spvtr_tport_set(payload, tport);1792	mlxsw_reg_spvtr_local_port_set(payload, local_port);1793	mlxsw_reg_spvtr_ipvid_mode_set(payload, ipvid_mode);1794	mlxsw_reg_spvtr_ipve_set(payload, true);1795}1796 1797/* SVPE - Switch Virtual-Port Enabling Register1798 * --------------------------------------------1799 * Enables port virtualization.1800 */1801#define MLXSW_REG_SVPE_ID 0x201E1802#define MLXSW_REG_SVPE_LEN 0x41803 1804MLXSW_REG_DEFINE(svpe, MLXSW_REG_SVPE_ID, MLXSW_REG_SVPE_LEN);1805 1806/* reg_svpe_local_port1807 * Local port number1808 * Access: Index1809 *1810 * Note: CPU port is not supported (uses VLAN mode only).1811 */1812MLXSW_ITEM32_LP(reg, svpe, 0x00, 16, 0x00, 12);1813 1814/* reg_svpe_vp_en1815 * Virtual port enable.1816 * 0 - Disable, VLAN mode (VID to FID).1817 * 1 - Enable, Virtual port mode ({Port, VID} to FID).1818 * Access: RW1819 */1820MLXSW_ITEM32(reg, svpe, vp_en, 0x00, 8, 1);1821 1822static inline void mlxsw_reg_svpe_pack(char *payload, u16 local_port,1823				       bool enable)1824{1825	MLXSW_REG_ZERO(svpe, payload);1826	mlxsw_reg_svpe_local_port_set(payload, local_port);1827	mlxsw_reg_svpe_vp_en_set(payload, enable);1828}1829 1830/* SFMR - Switch FID Management Register1831 * -------------------------------------1832 * Creates and configures FIDs.1833 */1834#define MLXSW_REG_SFMR_ID 0x201F1835#define MLXSW_REG_SFMR_LEN 0x301836 1837MLXSW_REG_DEFINE(sfmr, MLXSW_REG_SFMR_ID, MLXSW_REG_SFMR_LEN);1838 1839enum mlxsw_reg_sfmr_op {1840	MLXSW_REG_SFMR_OP_CREATE_FID,1841	MLXSW_REG_SFMR_OP_DESTROY_FID,1842};1843 1844/* reg_sfmr_op1845 * Operation.1846 * 0 - Create or edit FID.1847 * 1 - Destroy FID.1848 * Access: WO1849 */1850MLXSW_ITEM32(reg, sfmr, op, 0x00, 24, 4);1851 1852/* reg_sfmr_fid1853 * Filtering ID.1854 * Access: Index1855 */1856MLXSW_ITEM32(reg, sfmr, fid, 0x00, 0, 16);1857 1858/* reg_sfmr_flood_rsp1859 * Router sub-port flooding table.1860 * 0 - Regular flooding table.1861 * 1 - Router sub-port flooding table. For this FID the flooding is per1862 * router-sub-port local_port. Must not be set for a FID which is not a1863 * router-sub-port and must be set prior to enabling the relevant RIF.1864 * Access: RW1865 *1866 * Note: Reserved when legacy bridge model is used.1867 * Reserved when CONFIG_PROFILE.flood_mode = CFF.1868 */1869MLXSW_ITEM32(reg, sfmr, flood_rsp, 0x08, 31, 1);1870 1871/* reg_sfmr_flood_bridge_type1872 * Flood bridge type (see SFGC.bridge_type).1873 * 0 - type_0.1874 * 1 - type_1.1875 * Access: RW1876 *1877 * Note: Reserved when legacy bridge model is used and when flood_rsp=1.1878 * Reserved when CONFIG_PROFILE.flood_mode = CFF1879 */1880MLXSW_ITEM32(reg, sfmr, flood_bridge_type, 0x08, 28, 1);1881 1882/* reg_sfmr_fid_offset1883 * FID offset.1884 * Used to point into the flooding table selected by SFGC register if1885 * the table is of type FID-Offset. Otherwise, this field is reserved.1886 * Access: RW1887 *1888 * Note: Reserved when CONFIG_PROFILE.flood_mode = CFF1889 */1890MLXSW_ITEM32(reg, sfmr, fid_offset, 0x08, 0, 16);1891 1892/* reg_sfmr_vtfp1893 * Valid Tunnel Flood Pointer.1894 * If not set, then nve_tunnel_flood_ptr is reserved and considered NULL.1895 * Access: RW1896 *1897 * Note: Reserved for 802.1Q FIDs.1898 */1899MLXSW_ITEM32(reg, sfmr, vtfp, 0x0C, 31, 1);1900 1901/* reg_sfmr_nve_tunnel_flood_ptr1902 * Underlay Flooding and BC Pointer.1903 * Used as a pointer to the first entry of the group based link lists of1904 * flooding or BC entries (for NVE tunnels).1905 * Access: RW1906 */1907MLXSW_ITEM32(reg, sfmr, nve_tunnel_flood_ptr, 0x0C, 0, 24);1908 1909/* reg_sfmr_vv1910 * VNI Valid.1911 * If not set, then vni is reserved.1912 * Access: RW1913 *1914 * Note: Reserved for 802.1Q FIDs.1915 */1916MLXSW_ITEM32(reg, sfmr, vv, 0x10, 31, 1);1917 1918/* reg_sfmr_vni1919 * Virtual Network Identifier.1920 * When legacy bridge model is used, a given VNI can only be assigned to one1921 * FID. When unified bridge model is used, it configures only the FID->VNI,1922 * the VNI->FID is done by SVFA.1923 * Access: RW1924 */1925MLXSW_ITEM32(reg, sfmr, vni, 0x10, 0, 24);1926 1927/* reg_sfmr_irif_v1928 * Ingress RIF valid.1929 * 0 - Ingress RIF is not valid, no ingress RIF assigned.1930 * 1 - Ingress RIF valid.1931 * Must not be set for a non valid RIF.1932 * Access: RW1933 *1934 * Note: Reserved when legacy bridge model is used.1935 */1936MLXSW_ITEM32(reg, sfmr, irif_v, 0x14, 24, 1);1937 1938/* reg_sfmr_irif1939 * Ingress RIF (Router Interface).1940 * Range is 0..cap_max_router_interfaces-1.1941 * Access: RW1942 *1943 * Note: Reserved when legacy bridge model is used and when irif_v=0.1944 */1945MLXSW_ITEM32(reg, sfmr, irif, 0x14, 0, 16);1946 1947/* reg_sfmr_cff_mid_base1948 * Pointer to PGT table.1949 * Range: 0..(cap_max_pgt-1)1950 * Access: RW1951 *1952 * Note: Reserved when SwitchX/-2 and Spectrum-1.1953 * Supported when CONFIG_PROFILE.flood_mode = CFF.1954 */1955MLXSW_ITEM32(reg, sfmr, cff_mid_base, 0x20, 0, 16);1956 1957/* reg_sfmr_nve_flood_prf_id1958 * FID flooding profile_id for NVE Encap1959 * Range 0..(max_cap_nve_flood_prf-1)1960 * Access: RW1961 *1962 * Note: Reserved when SwitchX/-2 and Spectrum-11963 */1964MLXSW_ITEM32(reg, sfmr, nve_flood_prf_id, 0x24, 8, 2);1965 1966/* reg_sfmr_cff_prf_id1967 * Compressed Fid Flooding profile_id1968 * Range 0..(max_cap_nve_flood_prf-1)1969 * Access: RW1970 *1971 * Note: Reserved when SwitchX/-2 and Spectrum-11972 * Supported only when CONFIG_PROFLE.flood_mode = CFF.1973 */1974MLXSW_ITEM32(reg, sfmr, cff_prf_id, 0x24, 0, 2);1975 1976/* reg_sfmr_smpe_valid1977 * SMPE is valid.1978 * Access: RW1979 *1980 * Note: Reserved when legacy bridge model is used, when flood_rsp=1 and on1981 * Spectrum-1.1982 */1983MLXSW_ITEM32(reg, sfmr, smpe_valid, 0x28, 20, 1);1984 1985/* reg_sfmr_smpe1986 * Switch multicast port to egress VID.1987 * Range is 0..cap_max_rmpe-11988 * Access: RW1989 *1990 * Note: Reserved when legacy bridge model is used, when flood_rsp=1 and on1991 * Spectrum-1.1992 */1993MLXSW_ITEM32(reg, sfmr, smpe, 0x28, 0, 16);1994 1995static inline void mlxsw_reg_sfmr_pack(char *payload,1996				       enum mlxsw_reg_sfmr_op op, u16 fid,1997				       bool smpe_valid, u16 smpe)1998{1999	MLXSW_REG_ZERO(sfmr, payload);2000	mlxsw_reg_sfmr_op_set(payload, op);2001	mlxsw_reg_sfmr_fid_set(payload, fid);2002	mlxsw_reg_sfmr_smpe_valid_set(payload, smpe_valid);2003	mlxsw_reg_sfmr_smpe_set(payload, smpe);2004}2005 2006/* SPVMLR - Switch Port VLAN MAC Learning Register2007 * -----------------------------------------------2008 * Controls the switch MAC learning policy per {Port, VID}.2009 */2010#define MLXSW_REG_SPVMLR_ID 0x20202011#define MLXSW_REG_SPVMLR_BASE_LEN 0x04 /* base length, without records */2012#define MLXSW_REG_SPVMLR_REC_LEN 0x04 /* record length */2013#define MLXSW_REG_SPVMLR_REC_MAX_COUNT 2552014#define MLXSW_REG_SPVMLR_LEN (MLXSW_REG_SPVMLR_BASE_LEN + \2015			      MLXSW_REG_SPVMLR_REC_LEN * \2016			      MLXSW_REG_SPVMLR_REC_MAX_COUNT)2017 2018MLXSW_REG_DEFINE(spvmlr, MLXSW_REG_SPVMLR_ID, MLXSW_REG_SPVMLR_LEN);2019 2020/* reg_spvmlr_local_port2021 * Local ingress port.2022 * Access: Index2023 *2024 * Note: CPU port is not supported.2025 */2026MLXSW_ITEM32_LP(reg, spvmlr, 0x00, 16, 0x00, 12);2027 2028/* reg_spvmlr_num_rec2029 * Number of records to update.2030 * Access: OP2031 */2032MLXSW_ITEM32(reg, spvmlr, num_rec, 0x00, 0, 8);2033 2034/* reg_spvmlr_rec_learn_enable2035 * 0 - Disable learning for {Port, VID}.2036 * 1 - Enable learning for {Port, VID}.2037 * Access: RW2038 */2039MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_learn_enable, MLXSW_REG_SPVMLR_BASE_LEN,2040		     31, 1, MLXSW_REG_SPVMLR_REC_LEN, 0x00, false);2041 2042/* reg_spvmlr_rec_vid2043 * VLAN ID to be added/removed from port or for querying.2044 * Access: Index2045 */2046MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_vid, MLXSW_REG_SPVMLR_BASE_LEN, 0, 12,2047		     MLXSW_REG_SPVMLR_REC_LEN, 0x00, false);2048 2049static inline void mlxsw_reg_spvmlr_pack(char *payload, u16 local_port,2050					 u16 vid_begin, u16 vid_end,2051					 bool learn_enable)2052{2053	int num_rec = vid_end - vid_begin + 1;2054	int i;2055 2056	WARN_ON(num_rec < 1 || num_rec > MLXSW_REG_SPVMLR_REC_MAX_COUNT);2057 2058	MLXSW_REG_ZERO(spvmlr, payload);2059	mlxsw_reg_spvmlr_local_port_set(payload, local_port);2060	mlxsw_reg_spvmlr_num_rec_set(payload, num_rec);2061 2062	for (i = 0; i < num_rec; i++) {2063		mlxsw_reg_spvmlr_rec_learn_enable_set(payload, i, learn_enable);2064		mlxsw_reg_spvmlr_rec_vid_set(payload, i, vid_begin + i);2065	}2066}2067 2068/* SPFSR - Switch Port FDB Security Register2069 * -----------------------------------------2070 * Configures the security mode per port.2071 */2072#define MLXSW_REG_SPFSR_ID 0x20232073#define MLXSW_REG_SPFSR_LEN 0x082074 2075MLXSW_REG_DEFINE(spfsr, MLXSW_REG_SPFSR_ID, MLXSW_REG_SPFSR_LEN);2076 2077/* reg_spfsr_local_port2078 * Local port.2079 * Access: Index2080 *2081 * Note: not supported for CPU port.2082 */2083MLXSW_ITEM32_LP(reg, spfsr, 0x00, 16, 0x00, 12);2084 2085/* reg_spfsr_security2086 * Security checks.2087 * 0: disabled (default)2088 * 1: enabled2089 * Access: RW2090 */2091MLXSW_ITEM32(reg, spfsr, security, 0x04, 31, 1);2092 2093static inline void mlxsw_reg_spfsr_pack(char *payload, u16 local_port,2094					bool security)2095{2096	MLXSW_REG_ZERO(spfsr, payload);2097	mlxsw_reg_spfsr_local_port_set(payload, local_port);2098	mlxsw_reg_spfsr_security_set(payload, security);2099}2100 2101/* SPVC - Switch Port VLAN Classification Register2102 * -----------------------------------------------2103 * Configures the port to identify packets as untagged / single tagged /2104 * double packets based on the packet EtherTypes.2105 * Ethertype IDs are configured by SVER.2106 */2107#define MLXSW_REG_SPVC_ID 0x20262108#define MLXSW_REG_SPVC_LEN 0x0C2109 2110MLXSW_REG_DEFINE(spvc, MLXSW_REG_SPVC_ID, MLXSW_REG_SPVC_LEN);2111 2112/* reg_spvc_local_port2113 * Local port.2114 * Access: Index2115 *2116 * Note: applies both to Rx port and Tx port, so if a packet traverses2117 * through Rx port i and a Tx port j then port i and port j must have the2118 * same configuration.2119 */2120MLXSW_ITEM32_LP(reg, spvc, 0x00, 16, 0x00, 12);2121 2122/* reg_spvc_inner_et22123 * Vlan Tag1 EtherType2 enable.2124 * Packet is initially classified as double VLAN Tag if in addition to2125 * being classified with a tag0 VLAN Tag its tag1 EtherType value is2126 * equal to ether_type2.2127 * 0: disable (default)2128 * 1: enable2129 * Access: RW2130 */2131MLXSW_ITEM32(reg, spvc, inner_et2, 0x08, 17, 1);2132 2133/* reg_spvc_et22134 * Vlan Tag0 EtherType2 enable.2135 * Packet is initially classified as VLAN Tag if its tag0 EtherType is2136 * equal to ether_type2.2137 * 0: disable (default)2138 * 1: enable2139 * Access: RW2140 */2141MLXSW_ITEM32(reg, spvc, et2, 0x08, 16, 1);2142 2143/* reg_spvc_inner_et12144 * Vlan Tag1 EtherType1 enable.2145 * Packet is initially classified as double VLAN Tag if in addition to2146 * being classified with a tag0 VLAN Tag its tag1 EtherType value is2147 * equal to ether_type1.2148 * 0: disable2149 * 1: enable (default)2150 * Access: RW2151 */2152MLXSW_ITEM32(reg, spvc, inner_et1, 0x08, 9, 1);2153 2154/* reg_spvc_et12155 * Vlan Tag0 EtherType1 enable.2156 * Packet is initially classified as VLAN Tag if its tag0 EtherType is2157 * equal to ether_type1.2158 * 0: disable2159 * 1: enable (default)2160 * Access: RW2161 */2162MLXSW_ITEM32(reg, spvc, et1, 0x08, 8, 1);2163 2164/* reg_inner_et02165 * Vlan Tag1 EtherType0 enable.2166 * Packet is initially classified as double VLAN Tag if in addition to2167 * being classified with a tag0 VLAN Tag its tag1 EtherType value is2168 * equal to ether_type0.2169 * 0: disable2170 * 1: enable (default)2171 * Access: RW2172 */2173MLXSW_ITEM32(reg, spvc, inner_et0, 0x08, 1, 1);2174 2175/* reg_et02176 * Vlan Tag0 EtherType0 enable.2177 * Packet is initially classified as VLAN Tag if its tag0 EtherType is2178 * equal to ether_type0.2179 * 0: disable2180 * 1: enable (default)2181 * Access: RW2182 */2183MLXSW_ITEM32(reg, spvc, et0, 0x08, 0, 1);2184 2185static inline void mlxsw_reg_spvc_pack(char *payload, u16 local_port, bool et1,2186				       bool et0)2187{2188	MLXSW_REG_ZERO(spvc, payload);2189	mlxsw_reg_spvc_local_port_set(payload, local_port);2190	/* Enable inner_et1 and inner_et0 to enable identification of double2191	 * tagged packets.2192	 */2193	mlxsw_reg_spvc_inner_et1_set(payload, 1);2194	mlxsw_reg_spvc_inner_et0_set(payload, 1);2195	mlxsw_reg_spvc_et1_set(payload, et1);2196	mlxsw_reg_spvc_et0_set(payload, et0);2197}2198 2199/* SFFP - Switch FID Flooding Profiles Register2200 * --------------------------------------------2201 * The SFFP register populates the fid flooding profile tables used for the NVE2202 * flooding and Compressed-FID Flooding (CFF).2203 *2204 * Reserved on Spectrum-1.2205 */2206#define MLXSW_REG_SFFP_ID 0x20292207#define MLXSW_REG_SFFP_LEN 0x0C2208 2209MLXSW_REG_DEFINE(sffp, MLXSW_REG_SFFP_ID, MLXSW_REG_SFFP_LEN);2210 2211/* reg_sffp_profile_id2212 * Profile ID a.k.a. SFMR.nve_flood_prf_id or SFMR.cff_prf_id2213 * Range 0..max_cap_nve_flood_prf-12214 * Access: Index2215 */2216MLXSW_ITEM32(reg, sffp, profile_id, 0x00, 16, 2);2217 2218/* reg_sffp_type2219 * The traffic type to reach the flooding table.2220 * Same as SFGC.type2221 * Access: Index2222 */2223MLXSW_ITEM32(reg, sffp, type, 0x00, 0, 4);2224 2225/* reg_sffp_flood_offset2226 * Flood offset. Offset to add to SFMR.cff_mid_base to get the final PGT address2227 * for FID flood; or offset to add to SFMR.nve_tunnel_flood_ptr to get KVD2228 * pointer for NVE underlay.2229 * Access: RW2230 */2231MLXSW_ITEM32(reg, sffp, flood_offset, 0x04, 0, 3);2232 2233static inline void mlxsw_reg_sffp_pack(char *payload, u8 profile_id,2234				       enum mlxsw_reg_sfgc_type type,2235				       u8 flood_offset)2236{2237	MLXSW_REG_ZERO(sffp, payload);2238	mlxsw_reg_sffp_profile_id_set(payload, profile_id);2239	mlxsw_reg_sffp_type_set(payload, type);2240	mlxsw_reg_sffp_flood_offset_set(payload, flood_offset);2241}2242 2243/* SPEVET - Switch Port Egress VLAN EtherType2244 * ------------------------------------------2245 * The switch port egress VLAN EtherType configures which EtherType to push at2246 * egress for packets incoming through a local port for which 'SPVID.egr_et_set'2247 * is set.2248 */2249#define MLXSW_REG_SPEVET_ID 0x202A2250#define MLXSW_REG_SPEVET_LEN 0x082251 2252MLXSW_REG_DEFINE(spevet, MLXSW_REG_SPEVET_ID, MLXSW_REG_SPEVET_LEN);2253 2254/* reg_spevet_local_port2255 * Egress Local port number.2256 * Not supported to CPU port.2257 * Access: Index2258 */2259MLXSW_ITEM32_LP(reg, spevet, 0x00, 16, 0x00, 12);2260 2261/* reg_spevet_et_vlan2262 * Egress EtherType VLAN to push when SPVID.egr_et_set field set for the packet:2263 * 0: ether_type0 - (default)2264 * 1: ether_type12265 * 2: ether_type22266 * Access: RW2267 */2268MLXSW_ITEM32(reg, spevet, et_vlan, 0x04, 16, 2);2269 2270static inline void mlxsw_reg_spevet_pack(char *payload, u16 local_port,2271					 u8 et_vlan)2272{2273	MLXSW_REG_ZERO(spevet, payload);2274	mlxsw_reg_spevet_local_port_set(payload, local_port);2275	mlxsw_reg_spevet_et_vlan_set(payload, et_vlan);2276}2277 2278/* SMPE - Switch Multicast Port to Egress VID2279 * ------------------------------------------2280 * The switch multicast port to egress VID maps2281 * {egress_port, SMPE index} -> {VID}.2282 */2283#define MLXSW_REG_SMPE_ID 0x202B2284#define MLXSW_REG_SMPE_LEN 0x0C2285 2286MLXSW_REG_DEFINE(smpe, MLXSW_REG_SMPE_ID, MLXSW_REG_SMPE_LEN);2287 2288/* reg_smpe_local_port2289 * Local port number.2290 * CPU port is not supported.2291 * Access: Index2292 */2293MLXSW_ITEM32_LP(reg, smpe, 0x00, 16, 0x00, 12);2294 2295/* reg_smpe_smpe_index2296 * Switch multicast port to egress VID.2297 * Range is 0..cap_max_rmpe-1.2298 * Access: Index2299 */2300MLXSW_ITEM32(reg, smpe, smpe_index, 0x04, 0, 16);2301 2302/* reg_smpe_evid2303 * Egress VID.2304 * Access: RW2305 */2306MLXSW_ITEM32(reg, smpe, evid, 0x08, 0, 12);2307 2308static inline void mlxsw_reg_smpe_pack(char *payload, u16 local_port,2309				       u16 smpe_index, u16 evid)2310{2311	MLXSW_REG_ZERO(smpe, payload);2312	mlxsw_reg_smpe_local_port_set(payload, local_port);2313	mlxsw_reg_smpe_smpe_index_set(payload, smpe_index);2314	mlxsw_reg_smpe_evid_set(payload, evid);2315}2316 2317/* SMID-V2 - Switch Multicast ID Version 2 Register2318 * ------------------------------------------------2319 * The MID record maps from a MID (Multicast ID), which is a unique identifier2320 * of the multicast group within the stacking domain, into a list of local2321 * ports into which the packet is replicated.2322 */2323#define MLXSW_REG_SMID2_ID 0x20342324#define MLXSW_REG_SMID2_LEN 0x1202325 2326MLXSW_REG_DEFINE(smid2, MLXSW_REG_SMID2_ID, MLXSW_REG_SMID2_LEN);2327 2328/* reg_smid2_swid2329 * Switch partition ID.2330 * Access: Index2331 */2332MLXSW_ITEM32(reg, smid2, swid, 0x00, 24, 8);2333 2334/* reg_smid2_mid2335 * Multicast identifier - global identifier that represents the multicast group2336 * across all devices.2337 * Access: Index2338 */2339MLXSW_ITEM32(reg, smid2, mid, 0x00, 0, 16);2340 2341/* reg_smid2_smpe_valid2342 * SMPE is valid.2343 * When not valid, the egress VID will not be modified by the SMPE table.2344 * Access: RW2345 *2346 * Note: Reserved when legacy bridge model is used and on Spectrum-2.2347 */2348MLXSW_ITEM32(reg, smid2, smpe_valid, 0x08, 20, 1);2349 2350/* reg_smid2_smpe2351 * Switch multicast port to egress VID.2352 * Access: RW2353 *2354 * Note: Reserved when legacy bridge model is used and on Spectrum-2.2355 */2356MLXSW_ITEM32(reg, smid2, smpe, 0x08, 0, 16);2357 2358/* reg_smid2_port2359 * Local port memebership (1 bit per port).2360 * Access: RW2361 */2362MLXSW_ITEM_BIT_ARRAY(reg, smid2, port, 0x20, 0x80, 1);2363 2364/* reg_smid2_port_mask2365 * Local port mask (1 bit per port).2366 * Access: WO2367 */2368MLXSW_ITEM_BIT_ARRAY(reg, smid2, port_mask, 0xA0, 0x80, 1);2369 2370static inline void mlxsw_reg_smid2_pack(char *payload, u16 mid, u16 port,2371					bool set, bool smpe_valid, u16 smpe)2372{2373	MLXSW_REG_ZERO(smid2, payload);2374	mlxsw_reg_smid2_swid_set(payload, 0);2375	mlxsw_reg_smid2_mid_set(payload, mid);2376	mlxsw_reg_smid2_port_set(payload, port, set);2377	mlxsw_reg_smid2_port_mask_set(payload, port, 1);2378	mlxsw_reg_smid2_smpe_valid_set(payload, smpe_valid);2379	mlxsw_reg_smid2_smpe_set(payload, smpe_valid ? smpe : 0);2380}2381 2382/* CWTP - Congetion WRED ECN TClass Profile2383 * ----------------------------------------2384 * Configures the profiles for queues of egress port and traffic class2385 */2386#define MLXSW_REG_CWTP_ID 0x28022387#define MLXSW_REG_CWTP_BASE_LEN 0x282388#define MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN 0x082389#define MLXSW_REG_CWTP_LEN 0x402390 2391MLXSW_REG_DEFINE(cwtp, MLXSW_REG_CWTP_ID, MLXSW_REG_CWTP_LEN);2392 2393/* reg_cwtp_local_port2394 * Local port number2395 * Not supported for CPU port2396 * Access: Index2397 */2398MLXSW_ITEM32_LP(reg, cwtp, 0x00, 16, 0x00, 12);2399 2400/* reg_cwtp_traffic_class2401 * Traffic Class to configure2402 * Access: Index2403 */2404MLXSW_ITEM32(reg, cwtp, traffic_class, 32, 0, 8);2405 2406/* reg_cwtp_profile_min2407 * Minimum Average Queue Size of the profile in cells.2408 * Access: RW2409 */2410MLXSW_ITEM32_INDEXED(reg, cwtp, profile_min, MLXSW_REG_CWTP_BASE_LEN,2411		     0, 20, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 0, false);2412 2413/* reg_cwtp_profile_percent2414 * Percentage of WRED and ECN marking for maximum Average Queue size2415 * Range is 0 to 100, units of integer percentage2416 * Access: RW2417 */2418MLXSW_ITEM32_INDEXED(reg, cwtp, profile_percent, MLXSW_REG_CWTP_BASE_LEN,2419		     24, 7, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 4, false);2420 2421/* reg_cwtp_profile_max2422 * Maximum Average Queue size of the profile in cells2423 * Access: RW2424 */2425MLXSW_ITEM32_INDEXED(reg, cwtp, profile_max, MLXSW_REG_CWTP_BASE_LEN,2426		     0, 20, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 4, false);2427 2428#define MLXSW_REG_CWTP_MIN_VALUE 642429#define MLXSW_REG_CWTP_MAX_PROFILE 22430#define MLXSW_REG_CWTP_DEFAULT_PROFILE 12431 2432static inline void mlxsw_reg_cwtp_pack(char *payload, u16 local_port,2433				       u8 traffic_class)2434{2435	int i;2436 2437	MLXSW_REG_ZERO(cwtp, payload);2438	mlxsw_reg_cwtp_local_port_set(payload, local_port);2439	mlxsw_reg_cwtp_traffic_class_set(payload, traffic_class);2440 2441	for (i = 0; i <= MLXSW_REG_CWTP_MAX_PROFILE; i++) {2442		mlxsw_reg_cwtp_profile_min_set(payload, i,2443					       MLXSW_REG_CWTP_MIN_VALUE);2444		mlxsw_reg_cwtp_profile_max_set(payload, i,2445					       MLXSW_REG_CWTP_MIN_VALUE);2446	}2447}2448 2449#define MLXSW_REG_CWTP_PROFILE_TO_INDEX(profile) (profile - 1)2450 2451static inline void2452mlxsw_reg_cwtp_profile_pack(char *payload, u8 profile, u32 min, u32 max,2453			    u32 probability)2454{2455	u8 index = MLXSW_REG_CWTP_PROFILE_TO_INDEX(profile);2456 2457	mlxsw_reg_cwtp_profile_min_set(payload, index, min);2458	mlxsw_reg_cwtp_profile_max_set(payload, index, max);2459	mlxsw_reg_cwtp_profile_percent_set(payload, index, probability);2460}2461 2462/* CWTPM - Congestion WRED ECN TClass and Pool Mapping2463 * ---------------------------------------------------2464 * The CWTPM register maps each egress port and traffic class to profile num.2465 */2466#define MLXSW_REG_CWTPM_ID 0x28032467#define MLXSW_REG_CWTPM_LEN 0x442468 2469MLXSW_REG_DEFINE(cwtpm, MLXSW_REG_CWTPM_ID, MLXSW_REG_CWTPM_LEN);2470 2471/* reg_cwtpm_local_port2472 * Local port number2473 * Not supported for CPU port2474 * Access: Index2475 */2476MLXSW_ITEM32_LP(reg, cwtpm, 0x00, 16, 0x00, 12);2477 2478/* reg_cwtpm_traffic_class2479 * Traffic Class to configure2480 * Access: Index2481 */2482MLXSW_ITEM32(reg, cwtpm, traffic_class, 32, 0, 8);2483 2484/* reg_cwtpm_ew2485 * Control enablement of WRED for traffic class:2486 * 0 - Disable2487 * 1 - Enable2488 * Access: RW2489 */2490MLXSW_ITEM32(reg, cwtpm, ew, 36, 1, 1);2491 2492/* reg_cwtpm_ee2493 * Control enablement of ECN for traffic class:2494 * 0 - Disable2495 * 1 - Enable2496 * Access: RW2497 */2498MLXSW_ITEM32(reg, cwtpm, ee, 36, 0, 1);2499 2500/* reg_cwtpm_tcp_g2501 * TCP Green Profile.2502 * Index of the profile within {port, traffic class} to use.2503 * 0 for disabling both WRED and ECN for this type of traffic.2504 * Access: RW2505 */2506MLXSW_ITEM32(reg, cwtpm, tcp_g, 52, 0, 2);2507 2508/* reg_cwtpm_tcp_y2509 * TCP Yellow Profile.2510 * Index of the profile within {port, traffic class} to use.2511 * 0 for disabling both WRED and ECN for this type of traffic.2512 * Access: RW2513 */2514MLXSW_ITEM32(reg, cwtpm, tcp_y, 56, 16, 2);2515 2516/* reg_cwtpm_tcp_r2517 * TCP Red Profile.2518 * Index of the profile within {port, traffic class} to use.2519 * 0 for disabling both WRED and ECN for this type of traffic.2520 * Access: RW2521 */2522MLXSW_ITEM32(reg, cwtpm, tcp_r, 56, 0, 2);2523 2524/* reg_cwtpm_ntcp_g2525 * Non-TCP Green Profile.2526 * Index of the profile within {port, traffic class} to use.2527 * 0 for disabling both WRED and ECN for this type of traffic.2528 * Access: RW2529 */2530MLXSW_ITEM32(reg, cwtpm, ntcp_g, 60, 0, 2);2531 2532/* reg_cwtpm_ntcp_y2533 * Non-TCP Yellow Profile.2534 * Index of the profile within {port, traffic class} to use.2535 * 0 for disabling both WRED and ECN for this type of traffic.2536 * Access: RW2537 */2538MLXSW_ITEM32(reg, cwtpm, ntcp_y, 64, 16, 2);2539 2540/* reg_cwtpm_ntcp_r2541 * Non-TCP Red Profile.2542 * Index of the profile within {port, traffic class} to use.2543 * 0 for disabling both WRED and ECN for this type of traffic.2544 * Access: RW2545 */2546MLXSW_ITEM32(reg, cwtpm, ntcp_r, 64, 0, 2);2547 2548#define MLXSW_REG_CWTPM_RESET_PROFILE 02549 2550static inline void mlxsw_reg_cwtpm_pack(char *payload, u16 local_port,2551					u8 traffic_class, u8 profile,2552					bool wred, bool ecn)2553{2554	MLXSW_REG_ZERO(cwtpm, payload);2555	mlxsw_reg_cwtpm_local_port_set(payload, local_port);2556	mlxsw_reg_cwtpm_traffic_class_set(payload, traffic_class);2557	mlxsw_reg_cwtpm_ew_set(payload, wred);2558	mlxsw_reg_cwtpm_ee_set(payload, ecn);2559	mlxsw_reg_cwtpm_tcp_g_set(payload, profile);2560	mlxsw_reg_cwtpm_tcp_y_set(payload, profile);2561	mlxsw_reg_cwtpm_tcp_r_set(payload, profile);2562	mlxsw_reg_cwtpm_ntcp_g_set(payload, profile);2563	mlxsw_reg_cwtpm_ntcp_y_set(payload, profile);2564	mlxsw_reg_cwtpm_ntcp_r_set(payload, profile);2565}2566 2567/* PGCR - Policy-Engine General Configuration Register2568 * ---------------------------------------------------2569 * This register configures general Policy-Engine settings.2570 */2571#define MLXSW_REG_PGCR_ID 0x30012572#define MLXSW_REG_PGCR_LEN 0x202573 2574MLXSW_REG_DEFINE(pgcr, MLXSW_REG_PGCR_ID, MLXSW_REG_PGCR_LEN);2575 2576/* reg_pgcr_default_action_pointer_base2577 * Default action pointer base. Each region has a default action pointer2578 * which is equal to default_action_pointer_base + region_id.2579 * Access: RW2580 */2581MLXSW_ITEM32(reg, pgcr, default_action_pointer_base, 0x1C, 0, 24);2582 2583static inline void mlxsw_reg_pgcr_pack(char *payload, u32 pointer_base)2584{2585	MLXSW_REG_ZERO(pgcr, payload);2586	mlxsw_reg_pgcr_default_action_pointer_base_set(payload, pointer_base);2587}2588 2589/* PPBT - Policy-Engine Port Binding Table2590 * ---------------------------------------2591 * This register is used for configuration of the Port Binding Table.2592 */2593#define MLXSW_REG_PPBT_ID 0x30022594#define MLXSW_REG_PPBT_LEN 0x142595 2596MLXSW_REG_DEFINE(ppbt, MLXSW_REG_PPBT_ID, MLXSW_REG_PPBT_LEN);2597 2598enum mlxsw_reg_pxbt_e {2599	MLXSW_REG_PXBT_E_IACL,2600	MLXSW_REG_PXBT_E_EACL,2601};2602 2603/* reg_ppbt_e2604 * Access: Index2605 */2606MLXSW_ITEM32(reg, ppbt, e, 0x00, 31, 1);2607 2608enum mlxsw_reg_pxbt_op {2609	MLXSW_REG_PXBT_OP_BIND,2610	MLXSW_REG_PXBT_OP_UNBIND,2611};2612 2613/* reg_ppbt_op2614 * Access: RW2615 */2616MLXSW_ITEM32(reg, ppbt, op, 0x00, 28, 3);2617 2618/* reg_ppbt_local_port2619 * Local port. Not including CPU port.2620 * Access: Index2621 */2622MLXSW_ITEM32_LP(reg, ppbt, 0x00, 16, 0x00, 12);2623 2624/* reg_ppbt_g2625 * group - When set, the binding is of an ACL group. When cleared,2626 * the binding is of an ACL.2627 * Must be set to 1 for Spectrum.2628 * Access: RW2629 */2630MLXSW_ITEM32(reg, ppbt, g, 0x10, 31, 1);2631 2632/* reg_ppbt_acl_info2633 * ACL/ACL group identifier. If the g bit is set, this field should hold2634 * the acl_group_id, else it should hold the acl_id.2635 * Access: RW2636 */2637MLXSW_ITEM32(reg, ppbt, acl_info, 0x10, 0, 16);2638 2639static inline void mlxsw_reg_ppbt_pack(char *payload, enum mlxsw_reg_pxbt_e e,2640				       enum mlxsw_reg_pxbt_op op,2641				       u16 local_port, u16 acl_info)2642{2643	MLXSW_REG_ZERO(ppbt, payload);2644	mlxsw_reg_ppbt_e_set(payload, e);2645	mlxsw_reg_ppbt_op_set(payload, op);2646	mlxsw_reg_ppbt_local_port_set(payload, local_port);2647	mlxsw_reg_ppbt_g_set(payload, true);2648	mlxsw_reg_ppbt_acl_info_set(payload, acl_info);2649}2650 2651/* PACL - Policy-Engine ACL Register2652 * ---------------------------------2653 * This register is used for configuration of the ACL.2654 */2655#define MLXSW_REG_PACL_ID 0x30042656#define MLXSW_REG_PACL_LEN 0x702657 2658MLXSW_REG_DEFINE(pacl, MLXSW_REG_PACL_ID, MLXSW_REG_PACL_LEN);2659 2660/* reg_pacl_v2661 * Valid. Setting the v bit makes the ACL valid. It should not be cleared2662 * while the ACL is bounded to either a port, VLAN or ACL rule.2663 * Access: RW2664 */2665MLXSW_ITEM32(reg, pacl, v, 0x00, 24, 1);2666 2667/* reg_pacl_acl_id2668 * An identifier representing the ACL (managed by software)2669 * Range 0 .. cap_max_acl_regions - 12670 * Access: Index2671 */2672MLXSW_ITEM32(reg, pacl, acl_id, 0x08, 0, 16);2673 2674#define MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN 162675 2676/* reg_pacl_tcam_region_info2677 * Opaque object that represents a TCAM region.2678 * Obtained through PTAR register.2679 * Access: RW2680 */2681MLXSW_ITEM_BUF(reg, pacl, tcam_region_info, 0x30,2682	       MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);2683 2684static inline void mlxsw_reg_pacl_pack(char *payload, u16 acl_id,2685				       bool valid, const char *tcam_region_info)2686{2687	MLXSW_REG_ZERO(pacl, payload);2688	mlxsw_reg_pacl_acl_id_set(payload, acl_id);2689	mlxsw_reg_pacl_v_set(payload, valid);2690	mlxsw_reg_pacl_tcam_region_info_memcpy_to(payload, tcam_region_info);2691}2692 2693/* PAGT - Policy-Engine ACL Group Table2694 * ------------------------------------2695 * This register is used for configuration of the ACL Group Table.2696 */2697#define MLXSW_REG_PAGT_ID 0x30052698#define MLXSW_REG_PAGT_BASE_LEN 0x302699#define MLXSW_REG_PAGT_ACL_LEN 42700#define MLXSW_REG_PAGT_ACL_MAX_NUM 162701#define MLXSW_REG_PAGT_LEN (MLXSW_REG_PAGT_BASE_LEN + \2702		MLXSW_REG_PAGT_ACL_MAX_NUM * MLXSW_REG_PAGT_ACL_LEN)2703 2704MLXSW_REG_DEFINE(pagt, MLXSW_REG_PAGT_ID, MLXSW_REG_PAGT_LEN);2705 2706/* reg_pagt_size2707 * Number of ACLs in the group.2708 * Size 0 invalidates a group.2709 * Range 0 .. cap_max_acl_group_size (hard coded to 16 for now)2710 * Total number of ACLs in all groups must be lower or equal2711 * to cap_max_acl_tot_groups2712 * Note: a group which is binded must not be invalidated2713 * Access: Index2714 */2715MLXSW_ITEM32(reg, pagt, size, 0x00, 0, 8);2716 2717/* reg_pagt_acl_group_id2718 * An identifier (numbered from 0..cap_max_acl_groups-1) representing2719 * the ACL Group identifier (managed by software).2720 * Access: Index2721 */2722MLXSW_ITEM32(reg, pagt, acl_group_id, 0x08, 0, 16);2723 2724/* reg_pagt_multi2725 * Multi-ACL2726 * 0 - This ACL is the last ACL in the multi-ACL2727 * 1 - This ACL is part of a multi-ACL2728 * Access: RW2729 */2730MLXSW_ITEM32_INDEXED(reg, pagt, multi, 0x30, 31, 1, 0x04, 0x00, false);2731 2732/* reg_pagt_acl_id2733 * ACL identifier2734 * Access: RW2735 */2736MLXSW_ITEM32_INDEXED(reg, pagt, acl_id, 0x30, 0, 16, 0x04, 0x00, false);2737 2738static inline void mlxsw_reg_pagt_pack(char *payload, u16 acl_group_id)2739{2740	MLXSW_REG_ZERO(pagt, payload);2741	mlxsw_reg_pagt_acl_group_id_set(payload, acl_group_id);2742}2743 2744static inline void mlxsw_reg_pagt_acl_id_pack(char *payload, int index,2745					      u16 acl_id, bool multi)2746{2747	u8 size = mlxsw_reg_pagt_size_get(payload);2748 2749	if (index >= size)2750		mlxsw_reg_pagt_size_set(payload, index + 1);2751	mlxsw_reg_pagt_multi_set(payload, index, multi);2752	mlxsw_reg_pagt_acl_id_set(payload, index, acl_id);2753}2754 2755/* PTAR - Policy-Engine TCAM Allocation Register2756 * ---------------------------------------------2757 * This register is used for allocation of regions in the TCAM.2758 * Note: Query method is not supported on this register.2759 */2760#define MLXSW_REG_PTAR_ID 0x30062761#define MLXSW_REG_PTAR_BASE_LEN 0x202762#define MLXSW_REG_PTAR_KEY_ID_LEN 12763#define MLXSW_REG_PTAR_KEY_ID_MAX_NUM 162764#define MLXSW_REG_PTAR_LEN (MLXSW_REG_PTAR_BASE_LEN + \2765		MLXSW_REG_PTAR_KEY_ID_MAX_NUM * MLXSW_REG_PTAR_KEY_ID_LEN)2766 2767MLXSW_REG_DEFINE(ptar, MLXSW_REG_PTAR_ID, MLXSW_REG_PTAR_LEN);2768 2769enum mlxsw_reg_ptar_op {2770	/* allocate a TCAM region */2771	MLXSW_REG_PTAR_OP_ALLOC,2772	/* resize a TCAM region */2773	MLXSW_REG_PTAR_OP_RESIZE,2774	/* deallocate TCAM region */2775	MLXSW_REG_PTAR_OP_FREE,2776	/* test allocation */2777	MLXSW_REG_PTAR_OP_TEST,2778};2779 2780/* reg_ptar_op2781 * Access: OP2782 */2783MLXSW_ITEM32(reg, ptar, op, 0x00, 28, 4);2784 2785/* reg_ptar_action_set_type2786 * Type of action set to be used on this region.2787 * For Spectrum and Spectrum-2, this is always type 2 - "flexible"2788 * Access: WO2789 */2790MLXSW_ITEM32(reg, ptar, action_set_type, 0x00, 16, 8);2791 2792enum mlxsw_reg_ptar_key_type {2793	MLXSW_REG_PTAR_KEY_TYPE_FLEX = 0x50, /* Spetrum */2794	MLXSW_REG_PTAR_KEY_TYPE_FLEX2 = 0x51, /* Spectrum-2 */2795};2796 2797/* reg_ptar_key_type2798 * TCAM key type for the region.2799 * Access: WO2800 */2801MLXSW_ITEM32(reg, ptar, key_type, 0x00, 0, 8);2802 2803/* reg_ptar_region_size2804 * TCAM region size. When allocating/resizing this is the requested size,2805 * the response is the actual size. Note that actual size may be2806 * larger than requested.2807 * Allowed range 1 .. cap_max_rules-12808 * Reserved during op deallocate.2809 * Access: WO2810 */2811MLXSW_ITEM32(reg, ptar, region_size, 0x04, 0, 16);2812 2813/* reg_ptar_region_id2814 * Region identifier2815 * Range 0 .. cap_max_regions-12816 * Access: Index2817 */2818MLXSW_ITEM32(reg, ptar, region_id, 0x08, 0, 16);2819 2820/* reg_ptar_tcam_region_info2821 * Opaque object that represents the TCAM region.2822 * Returned when allocating a region.2823 * Provided by software for ACL generation and region deallocation and resize.2824 * Access: RW2825 */2826MLXSW_ITEM_BUF(reg, ptar, tcam_region_info, 0x10,2827	       MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);2828 2829/* reg_ptar_flexible_key_id2830 * Identifier of the Flexible Key.2831 * Only valid if key_type == "FLEX_KEY"2832 * The key size will be rounded up to one of the following values:2833 * 9B, 18B, 36B, 54B.2834 * This field is reserved for in resize operation.2835 * Access: WO2836 */2837MLXSW_ITEM8_INDEXED(reg, ptar, flexible_key_id, 0x20, 0, 8,2838		    MLXSW_REG_PTAR_KEY_ID_LEN, 0x00, false);2839 2840static inline void mlxsw_reg_ptar_pack(char *payload, enum mlxsw_reg_ptar_op op,2841				       enum mlxsw_reg_ptar_key_type key_type,2842				       u16 region_size, u16 region_id,2843				       const char *tcam_region_info)2844{2845	MLXSW_REG_ZERO(ptar, payload);2846	mlxsw_reg_ptar_op_set(payload, op);2847	mlxsw_reg_ptar_action_set_type_set(payload, 2); /* "flexible" */2848	mlxsw_reg_ptar_key_type_set(payload, key_type);2849	mlxsw_reg_ptar_region_size_set(payload, region_size);2850	mlxsw_reg_ptar_region_id_set(payload, region_id);2851	mlxsw_reg_ptar_tcam_region_info_memcpy_to(payload, tcam_region_info);2852}2853 2854static inline void mlxsw_reg_ptar_key_id_pack(char *payload, int index,2855					      u16 key_id)2856{2857	mlxsw_reg_ptar_flexible_key_id_set(payload, index, key_id);2858}2859 2860static inline void mlxsw_reg_ptar_unpack(char *payload, char *tcam_region_info)2861{2862	mlxsw_reg_ptar_tcam_region_info_memcpy_from(payload, tcam_region_info);2863}2864 2865/* PPRR - Policy-Engine Port Range Register2866 * ----------------------------------------2867 * This register is used for configuring port range identification.2868 */2869#define MLXSW_REG_PPRR_ID 0x30082870#define MLXSW_REG_PPRR_LEN 0x142871 2872MLXSW_REG_DEFINE(pprr, MLXSW_REG_PPRR_ID, MLXSW_REG_PPRR_LEN);2873 2874/* reg_pprr_ipv42875 * Apply port range register to IPv4 packets.2876 * Access: RW2877 */2878MLXSW_ITEM32(reg, pprr, ipv4, 0x00, 31, 1);2879 2880/* reg_pprr_ipv62881 * Apply port range register to IPv6 packets.2882 * Access: RW2883 */2884MLXSW_ITEM32(reg, pprr, ipv6, 0x00, 30, 1);2885 2886/* reg_pprr_src2887 * Apply port range register to source L4 ports.2888 * Access: RW2889 */2890MLXSW_ITEM32(reg, pprr, src, 0x00, 29, 1);2891 2892/* reg_pprr_dst2893 * Apply port range register to destination L4 ports.2894 * Access: RW2895 */2896MLXSW_ITEM32(reg, pprr, dst, 0x00, 28, 1);2897 2898/* reg_pprr_tcp2899 * Apply port range register to TCP packets.2900 * Access: RW2901 */2902MLXSW_ITEM32(reg, pprr, tcp, 0x00, 27, 1);2903 2904/* reg_pprr_udp2905 * Apply port range register to UDP packets.2906 * Access: RW2907 */2908MLXSW_ITEM32(reg, pprr, udp, 0x00, 26, 1);2909 2910/* reg_pprr_register_index2911 * Index of Port Range Register being accessed.2912 * Range is 0..cap_max_acl_l4_port_range-1.2913 * Access: Index2914 */2915MLXSW_ITEM32(reg, pprr, register_index, 0x00, 0, 8);2916 2917/* reg_prrr_port_range_min2918 * Minimum port range for comparison.2919 * Match is defined as:2920 * port_range_min <= packet_port <= port_range_max.2921 * Access: RW2922 */2923MLXSW_ITEM32(reg, pprr, port_range_min, 0x04, 16, 16);2924 2925/* reg_prrr_port_range_max2926 * Maximum port range for comparison.2927 * Access: RW2928 */2929MLXSW_ITEM32(reg, pprr, port_range_max, 0x04, 0, 16);2930 2931static inline void mlxsw_reg_pprr_pack(char *payload, u8 register_index)2932{2933	MLXSW_REG_ZERO(pprr, payload);2934	mlxsw_reg_pprr_register_index_set(payload, register_index);2935}2936 2937/* PPBS - Policy-Engine Policy Based Switching Register2938 * ----------------------------------------------------2939 * This register retrieves and sets Policy Based Switching Table entries.2940 */2941#define MLXSW_REG_PPBS_ID 0x300C2942#define MLXSW_REG_PPBS_LEN 0x142943 2944MLXSW_REG_DEFINE(ppbs, MLXSW_REG_PPBS_ID, MLXSW_REG_PPBS_LEN);2945 2946/* reg_ppbs_pbs_ptr2947 * Index into the PBS table.2948 * For Spectrum, the index points to the KVD Linear.2949 * Access: Index2950 */2951MLXSW_ITEM32(reg, ppbs, pbs_ptr, 0x08, 0, 24);2952 2953/* reg_ppbs_system_port2954 * Unique port identifier for the final destination of the packet.2955 * Access: RW2956 */2957MLXSW_ITEM32(reg, ppbs, system_port, 0x10, 0, 16);2958 2959static inline void mlxsw_reg_ppbs_pack(char *payload, u32 pbs_ptr,2960				       u16 system_port)2961{2962	MLXSW_REG_ZERO(ppbs, payload);2963	mlxsw_reg_ppbs_pbs_ptr_set(payload, pbs_ptr);2964	mlxsw_reg_ppbs_system_port_set(payload, system_port);2965}2966 2967/* PRCR - Policy-Engine Rules Copy Register2968 * ----------------------------------------2969 * This register is used for accessing rules within a TCAM region.2970 */2971#define MLXSW_REG_PRCR_ID 0x300D2972#define MLXSW_REG_PRCR_LEN 0x402973 2974MLXSW_REG_DEFINE(prcr, MLXSW_REG_PRCR_ID, MLXSW_REG_PRCR_LEN);2975 2976enum mlxsw_reg_prcr_op {2977	/* Move rules. Moves the rules from "tcam_region_info" starting2978	 * at offset "offset" to "dest_tcam_region_info"2979	 * at offset "dest_offset."2980	 */2981	MLXSW_REG_PRCR_OP_MOVE,2982	/* Copy rules. Copies the rules from "tcam_region_info" starting2983	 * at offset "offset" to "dest_tcam_region_info"2984	 * at offset "dest_offset."2985	 */2986	MLXSW_REG_PRCR_OP_COPY,2987};2988 2989/* reg_prcr_op2990 * Access: OP2991 */2992MLXSW_ITEM32(reg, prcr, op, 0x00, 28, 4);2993 2994/* reg_prcr_offset2995 * Offset within the source region to copy/move from.2996 * Access: Index2997 */2998MLXSW_ITEM32(reg, prcr, offset, 0x00, 0, 16);2999 3000/* reg_prcr_size3001 * The number of rules to copy/move.3002 * Access: WO3003 */3004MLXSW_ITEM32(reg, prcr, size, 0x04, 0, 16);3005 3006/* reg_prcr_tcam_region_info3007 * Opaque object that represents the source TCAM region.3008 * Access: Index3009 */3010MLXSW_ITEM_BUF(reg, prcr, tcam_region_info, 0x10,3011	       MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);3012 3013/* reg_prcr_dest_offset3014 * Offset within the source region to copy/move to.3015 * Access: Index3016 */3017MLXSW_ITEM32(reg, prcr, dest_offset, 0x20, 0, 16);3018 3019/* reg_prcr_dest_tcam_region_info3020 * Opaque object that represents the destination TCAM region.3021 * Access: Index3022 */3023MLXSW_ITEM_BUF(reg, prcr, dest_tcam_region_info, 0x30,3024	       MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);3025 3026static inline void mlxsw_reg_prcr_pack(char *payload, enum mlxsw_reg_prcr_op op,3027				       const char *src_tcam_region_info,3028				       u16 src_offset,3029				       const char *dest_tcam_region_info,3030				       u16 dest_offset, u16 size)3031{3032	MLXSW_REG_ZERO(prcr, payload);3033	mlxsw_reg_prcr_op_set(payload, op);3034	mlxsw_reg_prcr_offset_set(payload, src_offset);3035	mlxsw_reg_prcr_size_set(payload, size);3036	mlxsw_reg_prcr_tcam_region_info_memcpy_to(payload,3037						  src_tcam_region_info);3038	mlxsw_reg_prcr_dest_offset_set(payload, dest_offset);3039	mlxsw_reg_prcr_dest_tcam_region_info_memcpy_to(payload,3040						       dest_tcam_region_info);3041}3042 3043/* PEFA - Policy-Engine Extended Flexible Action Register3044 * ------------------------------------------------------3045 * This register is used for accessing an extended flexible action entry3046 * in the central KVD Linear Database.3047 */3048#define MLXSW_REG_PEFA_ID 0x300F3049#define MLXSW_REG_PEFA_LEN 0xB03050 3051MLXSW_REG_DEFINE(pefa, MLXSW_REG_PEFA_ID, MLXSW_REG_PEFA_LEN);3052 3053/* reg_pefa_index3054 * Index in the KVD Linear Centralized Database.3055 * Access: Index3056 */3057MLXSW_ITEM32(reg, pefa, index, 0x00, 0, 24);3058 3059/* reg_pefa_a3060 * Index in the KVD Linear Centralized Database.3061 * Activity3062 * For a new entry: set if ca=0, clear if ca=13063 * Set if a packet lookup has hit on the specific entry3064 * Access: RO3065 */3066MLXSW_ITEM32(reg, pefa, a, 0x04, 29, 1);3067 3068/* reg_pefa_ca3069 * Clear activity3070 * When write: activity is according to this field3071 * When read: after reading the activity is cleared according to ca3072 * Access: OP3073 */3074MLXSW_ITEM32(reg, pefa, ca, 0x04, 24, 1);3075 3076#define MLXSW_REG_FLEX_ACTION_SET_LEN 0xA83077 3078/* reg_pefa_flex_action_set3079 * Action-set to perform when rule is matched.3080 * Must be zero padded if action set is shorter.3081 * Access: RW3082 */3083MLXSW_ITEM_BUF(reg, pefa, flex_action_set, 0x08, MLXSW_REG_FLEX_ACTION_SET_LEN);3084 3085static inline void mlxsw_reg_pefa_pack(char *payload, u32 index, bool ca,3086				       const char *flex_action_set)3087{3088	MLXSW_REG_ZERO(pefa, payload);3089	mlxsw_reg_pefa_index_set(payload, index);3090	mlxsw_reg_pefa_ca_set(payload, ca);3091	if (flex_action_set)3092		mlxsw_reg_pefa_flex_action_set_memcpy_to(payload,3093							 flex_action_set);3094}3095 3096static inline void mlxsw_reg_pefa_unpack(char *payload, bool *p_a)3097{3098	*p_a = mlxsw_reg_pefa_a_get(payload);3099}3100 3101/* PEMRBT - Policy-Engine Multicast Router Binding Table Register3102 * --------------------------------------------------------------3103 * This register is used for binding Multicast router to an ACL group3104 * that serves the MC router.3105 * This register is not supported by SwitchX/-2 and Spectrum.3106 */3107#define MLXSW_REG_PEMRBT_ID 0x30143108#define MLXSW_REG_PEMRBT_LEN 0x143109 3110MLXSW_REG_DEFINE(pemrbt, MLXSW_REG_PEMRBT_ID, MLXSW_REG_PEMRBT_LEN);3111 3112enum mlxsw_reg_pemrbt_protocol {3113	MLXSW_REG_PEMRBT_PROTO_IPV4,3114	MLXSW_REG_PEMRBT_PROTO_IPV6,3115};3116 3117/* reg_pemrbt_protocol3118 * Access: Index3119 */3120MLXSW_ITEM32(reg, pemrbt, protocol, 0x00, 0, 1);3121 3122/* reg_pemrbt_group_id3123 * ACL group identifier.3124 * Range 0..cap_max_acl_groups-13125 * Access: RW3126 */3127MLXSW_ITEM32(reg, pemrbt, group_id, 0x10, 0, 16);3128 3129static inline void3130mlxsw_reg_pemrbt_pack(char *payload, enum mlxsw_reg_pemrbt_protocol protocol,3131		      u16 group_id)3132{3133	MLXSW_REG_ZERO(pemrbt, payload);3134	mlxsw_reg_pemrbt_protocol_set(payload, protocol);3135	mlxsw_reg_pemrbt_group_id_set(payload, group_id);3136}3137 3138/* PTCE-V2 - Policy-Engine TCAM Entry Register Version 23139 * -----------------------------------------------------3140 * This register is used for accessing rules within a TCAM region.3141 * It is a new version of PTCE in order to support wider key,3142 * mask and action within a TCAM region. This register is not supported3143 * by SwitchX and SwitchX-2.3144 */3145#define MLXSW_REG_PTCE2_ID 0x30173146#define MLXSW_REG_PTCE2_LEN 0x1D83147 3148MLXSW_REG_DEFINE(ptce2, MLXSW_REG_PTCE2_ID, MLXSW_REG_PTCE2_LEN);3149 3150/* reg_ptce2_v3151 * Valid.3152 * Access: RW3153 */3154MLXSW_ITEM32(reg, ptce2, v, 0x00, 31, 1);3155 3156/* reg_ptce2_a3157 * Activity. Set if a packet lookup has hit on the specific entry.3158 * To clear the "a" bit, use "clear activity" op or "clear on read" op.3159 * Access: RO3160 */3161MLXSW_ITEM32(reg, ptce2, a, 0x00, 30, 1);3162 3163enum mlxsw_reg_ptce2_op {3164	/* Read operation. */3165	MLXSW_REG_PTCE2_OP_QUERY_READ = 0,3166	/* clear on read operation. Used to read entry3167	 * and clear Activity bit.3168	 */3169	MLXSW_REG_PTCE2_OP_QUERY_CLEAR_ON_READ = 1,3170	/* Write operation. Used to write a new entry to the table.3171	 * All R/W fields are relevant for new entry. Activity bit is set3172	 * for new entries - Note write with v = 0 will delete the entry.3173	 */3174	MLXSW_REG_PTCE2_OP_WRITE_WRITE = 0,3175	/* Update action. Only action set will be updated. */3176	MLXSW_REG_PTCE2_OP_WRITE_UPDATE = 1,3177	/* Clear activity. A bit is cleared for the entry. */3178	MLXSW_REG_PTCE2_OP_WRITE_CLEAR_ACTIVITY = 2,3179};3180 3181/* reg_ptce2_op3182 * Access: OP3183 */3184MLXSW_ITEM32(reg, ptce2, op, 0x00, 20, 3);3185 3186/* reg_ptce2_offset3187 * Access: Index3188 */3189MLXSW_ITEM32(reg, ptce2, offset, 0x00, 0, 16);3190 3191/* reg_ptce2_priority3192 * Priority of the rule, higher values win. The range is 1..cap_kvd_size-1.3193 * Note: priority does not have to be unique per rule.3194 * Within a region, higher priority should have lower offset (no limitation3195 * between regions in a multi-region).3196 * Access: RW3197 */3198MLXSW_ITEM32(reg, ptce2, priority, 0x04, 0, 24);3199 3200/* reg_ptce2_tcam_region_info3201 * Opaque object that represents the TCAM region.3202 * Access: Index3203 */3204MLXSW_ITEM_BUF(reg, ptce2, tcam_region_info, 0x10,3205	       MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);3206 3207#define MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN 963208 3209/* reg_ptce2_flex_key_blocks3210 * ACL Key.3211 * Access: RW3212 */3213MLXSW_ITEM_BUF(reg, ptce2, flex_key_blocks, 0x20,3214	       MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN);3215 3216/* reg_ptce2_mask3217 * mask- in the same size as key. A bit that is set directs the TCAM3218 * to compare the corresponding bit in key. A bit that is clear directs3219 * the TCAM to ignore the corresponding bit in key.3220 * Access: RW3221 */3222MLXSW_ITEM_BUF(reg, ptce2, mask, 0x80,3223	       MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN);3224 3225/* reg_ptce2_flex_action_set3226 * ACL action set.3227 * Access: RW3228 */3229MLXSW_ITEM_BUF(reg, ptce2, flex_action_set, 0xE0,3230	       MLXSW_REG_FLEX_ACTION_SET_LEN);3231 3232static inline void mlxsw_reg_ptce2_pack(char *payload, bool valid,3233					enum mlxsw_reg_ptce2_op op,3234					const char *tcam_region_info,3235					u16 offset, u32 priority)3236{3237	MLXSW_REG_ZERO(ptce2, payload);3238	mlxsw_reg_ptce2_v_set(payload, valid);3239	mlxsw_reg_ptce2_op_set(payload, op);3240	mlxsw_reg_ptce2_offset_set(payload, offset);3241	mlxsw_reg_ptce2_priority_set(payload, priority);3242	mlxsw_reg_ptce2_tcam_region_info_memcpy_to(payload, tcam_region_info);3243}3244 3245/* PERPT - Policy-Engine ERP Table Register3246 * ----------------------------------------3247 * This register adds and removes eRPs from the eRP table.3248 */3249#define MLXSW_REG_PERPT_ID 0x30213250#define MLXSW_REG_PERPT_LEN 0x803251 3252MLXSW_REG_DEFINE(perpt, MLXSW_REG_PERPT_ID, MLXSW_REG_PERPT_LEN);3253 3254/* reg_perpt_erpt_bank3255 * eRP table bank.3256 * Range 0 .. cap_max_erp_table_banks - 13257 * Access: Index3258 */3259MLXSW_ITEM32(reg, perpt, erpt_bank, 0x00, 16, 4);3260 3261/* reg_perpt_erpt_index3262 * Index to eRP table within the eRP bank.3263 * Range is 0 .. cap_max_erp_table_bank_size - 13264 * Access: Index3265 */3266MLXSW_ITEM32(reg, perpt, erpt_index, 0x00, 0, 8);3267 3268enum mlxsw_reg_perpt_key_size {3269	MLXSW_REG_PERPT_KEY_SIZE_2KB,3270	MLXSW_REG_PERPT_KEY_SIZE_4KB,3271	MLXSW_REG_PERPT_KEY_SIZE_8KB,3272	MLXSW_REG_PERPT_KEY_SIZE_12KB,3273};3274 3275/* reg_perpt_key_size3276 * Access: OP3277 */3278MLXSW_ITEM32(reg, perpt, key_size, 0x04, 0, 4);3279 3280/* reg_perpt_bf_bypass3281 * 0 - The eRP is used only if bloom filter state is set for the given3282 * rule.3283 * 1 - The eRP is used regardless of bloom filter state.3284 * The bypass is an OR condition of region_id or eRP. See PERCR.bf_bypass3285 * Access: RW3286 */3287MLXSW_ITEM32(reg, perpt, bf_bypass, 0x08, 8, 1);3288 3289/* reg_perpt_erp_id3290 * eRP ID for use by the rules.3291 * Access: RW3292 */3293MLXSW_ITEM32(reg, perpt, erp_id, 0x08, 0, 4);3294 3295/* reg_perpt_erpt_base_bank3296 * Base eRP table bank, points to head of erp_vector3297 * Range is 0 .. cap_max_erp_table_banks - 13298 * Access: OP3299 */3300MLXSW_ITEM32(reg, perpt, erpt_base_bank, 0x0C, 16, 4);3301 3302/* reg_perpt_erpt_base_index3303 * Base index to eRP table within the eRP bank3304 * Range is 0 .. cap_max_erp_table_bank_size - 13305 * Access: OP3306 */3307MLXSW_ITEM32(reg, perpt, erpt_base_index, 0x0C, 0, 8);3308 3309/* reg_perpt_erp_index_in_vector3310 * eRP index in the vector.3311 * Access: OP3312 */3313MLXSW_ITEM32(reg, perpt, erp_index_in_vector, 0x10, 0, 4);3314 3315/* reg_perpt_erp_vector3316 * eRP vector.3317 * Access: OP3318 */3319MLXSW_ITEM_BIT_ARRAY(reg, perpt, erp_vector, 0x14, 4, 1);3320 3321/* reg_perpt_mask3322 * Mask3323 * 0 - A-TCAM will ignore the bit in key3324 * 1 - A-TCAM will compare the bit in key3325 * Access: RW3326 */3327MLXSW_ITEM_BUF(reg, perpt, mask, 0x20, MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN);3328 3329static inline void mlxsw_reg_perpt_erp_vector_pack(char *payload,3330						   unsigned long *erp_vector,3331						   unsigned long size)3332{3333	unsigned long bit;3334 3335	for_each_set_bit(bit, erp_vector, size)3336		mlxsw_reg_perpt_erp_vector_set(payload, bit, true);3337}3338 3339static inline void3340mlxsw_reg_perpt_pack(char *payload, u8 erpt_bank, u8 erpt_index,3341		     enum mlxsw_reg_perpt_key_size key_size, u8 erp_id,3342		     u8 erpt_base_bank, u8 erpt_base_index, u8 erp_index,3343		     char *mask)3344{3345	MLXSW_REG_ZERO(perpt, payload);3346	mlxsw_reg_perpt_erpt_bank_set(payload, erpt_bank);3347	mlxsw_reg_perpt_erpt_index_set(payload, erpt_index);3348	mlxsw_reg_perpt_key_size_set(payload, key_size);3349	mlxsw_reg_perpt_bf_bypass_set(payload, false);3350	mlxsw_reg_perpt_erp_id_set(payload, erp_id);3351	mlxsw_reg_perpt_erpt_base_bank_set(payload, erpt_base_bank);3352	mlxsw_reg_perpt_erpt_base_index_set(payload, erpt_base_index);3353	mlxsw_reg_perpt_erp_index_in_vector_set(payload, erp_index);3354	mlxsw_reg_perpt_mask_memcpy_to(payload, mask);3355}3356 3357/* PERAR - Policy-Engine Region Association Register3358 * -------------------------------------------------3359 * This register associates a hw region for region_id's. Changing on the fly3360 * is supported by the device.3361 */3362#define MLXSW_REG_PERAR_ID 0x30263363#define MLXSW_REG_PERAR_LEN 0x083364 3365MLXSW_REG_DEFINE(perar, MLXSW_REG_PERAR_ID, MLXSW_REG_PERAR_LEN);3366 3367/* reg_perar_region_id3368 * Region identifier3369 * Range 0 .. cap_max_regions-13370 * Access: Index3371 */3372MLXSW_ITEM32(reg, perar, region_id, 0x00, 0, 16);3373 3374static inline unsigned int3375mlxsw_reg_perar_hw_regions_needed(unsigned int block_num)3376{3377	return DIV_ROUND_UP(block_num, 4);3378}3379 3380/* reg_perar_hw_region3381 * HW Region3382 * Range 0 .. cap_max_regions-13383 * Default: hw_region = region_id3384 * For a 8 key block region, 2 consecutive regions are used3385 * For a 12 key block region, 3 consecutive regions are used3386 * Access: RW3387 */3388MLXSW_ITEM32(reg, perar, hw_region, 0x04, 0, 16);3389 3390static inline void mlxsw_reg_perar_pack(char *payload, u16 region_id,3391					u16 hw_region)3392{3393	MLXSW_REG_ZERO(perar, payload);3394	mlxsw_reg_perar_region_id_set(payload, region_id);3395	mlxsw_reg_perar_hw_region_set(payload, hw_region);3396}3397 3398/* PTCE-V3 - Policy-Engine TCAM Entry Register Version 33399 * -----------------------------------------------------3400 * This register is a new version of PTCE-V2 in order to support the3401 * A-TCAM. This register is not supported by SwitchX/-2 and Spectrum.3402 */3403#define MLXSW_REG_PTCE3_ID 0x30273404#define MLXSW_REG_PTCE3_LEN 0xF03405 3406MLXSW_REG_DEFINE(ptce3, MLXSW_REG_PTCE3_ID, MLXSW_REG_PTCE3_LEN);3407 3408/* reg_ptce3_v3409 * Valid.3410 * Access: RW3411 */3412MLXSW_ITEM32(reg, ptce3, v, 0x00, 31, 1);3413 3414enum mlxsw_reg_ptce3_op {3415	/* Write operation. Used to write a new entry to the table.3416	 * All R/W fields are relevant for new entry. Activity bit is set3417	 * for new entries. Write with v = 0 will delete the entry. Must3418	 * not be used if an entry exists.3419	 */3420	 MLXSW_REG_PTCE3_OP_WRITE_WRITE = 0,3421	 /* Update operation */3422	 MLXSW_REG_PTCE3_OP_WRITE_UPDATE = 1,3423	 /* Read operation */3424	 MLXSW_REG_PTCE3_OP_QUERY_READ = 0,3425};3426 3427/* reg_ptce3_op3428 * Access: OP3429 */3430MLXSW_ITEM32(reg, ptce3, op, 0x00, 20, 3);3431 3432/* reg_ptce3_priority3433 * Priority of the rule. Higher values win.3434 * For Spectrum-2 range is 1..cap_kvd_size - 13435 * Note: Priority does not have to be unique per rule.3436 * Access: RW3437 */3438MLXSW_ITEM32(reg, ptce3, priority, 0x04, 0, 24);3439 3440/* reg_ptce3_tcam_region_info3441 * Opaque object that represents the TCAM region.3442 * Access: Index3443 */3444MLXSW_ITEM_BUF(reg, ptce3, tcam_region_info, 0x10,3445	       MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);3446 3447/* reg_ptce3_flex2_key_blocks3448 * ACL key. The key must be masked according to eRP (if exists) or3449 * according to master mask.3450 * Access: Index3451 */3452MLXSW_ITEM_BUF(reg, ptce3, flex2_key_blocks, 0x20,3453	       MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN);3454 3455/* reg_ptce3_erp_id3456 * eRP ID.3457 * Access: Index3458 */3459MLXSW_ITEM32(reg, ptce3, erp_id, 0x80, 0, 4);3460 3461/* reg_ptce3_delta_start3462 * Start point of delta_value and delta_mask, in bits. Must not exceed3463 * num_key_blocks * 36 - 8. Reserved when delta_mask = 0.3464 * Access: Index3465 */3466MLXSW_ITEM32(reg, ptce3, delta_start, 0x84, 0, 10);3467 3468/* reg_ptce3_delta_mask3469 * Delta mask.3470 * 0 - Ignore relevant bit in delta_value3471 * 1 - Compare relevant bit in delta_value3472 * Delta mask must not be set for reserved fields in the key blocks.3473 * Note: No delta when no eRPs. Thus, for regions with3474 * PERERP.erpt_pointer_valid = 0 the delta mask must be 0.3475 * Access: Index3476 */3477MLXSW_ITEM32(reg, ptce3, delta_mask, 0x88, 16, 8);3478 3479/* reg_ptce3_delta_value3480 * Delta value.3481 * Bits which are masked by delta_mask must be 0.3482 * Access: Index3483 */3484MLXSW_ITEM32(reg, ptce3, delta_value, 0x88, 0, 8);3485 3486/* reg_ptce3_prune_vector3487 * Pruning vector relative to the PERPT.erp_id.3488 * Used for reducing lookups.3489 * 0 - NEED: Do a lookup using the eRP.3490 * 1 - PRUNE: Do not perform a lookup using the eRP.3491 * Maybe be modified by PEAPBL and PEAPBM.3492 * Note: In Spectrum-2, a region of 8 key blocks must be set to either3493 * all 1's or all 0's.3494 * Access: RW3495 */3496MLXSW_ITEM_BIT_ARRAY(reg, ptce3, prune_vector, 0x90, 4, 1);3497 3498/* reg_ptce3_prune_ctcam3499 * Pruning on C-TCAM. Used for reducing lookups.3500 * 0 - NEED: Do a lookup in the C-TCAM.3501 * 1 - PRUNE: Do not perform a lookup in the C-TCAM.3502 * Access: RW3503 */3504MLXSW_ITEM32(reg, ptce3, prune_ctcam, 0x94, 31, 1);3505 3506/* reg_ptce3_large_exists3507 * Large entry key ID exists.3508 * Within the region:3509 * 0 - SINGLE: The large_entry_key_id is not currently in use.3510 * For rule insert: The MSB of the key (blocks 6..11) will be added.3511 * For rule delete: The MSB of the key will be removed.3512 * 1 - NON_SINGLE: The large_entry_key_id is currently in use.3513 * For rule insert: The MSB of the key (blocks 6..11) will not be added.3514 * For rule delete: The MSB of the key will not be removed.3515 * Access: WO3516 */3517MLXSW_ITEM32(reg, ptce3, large_exists, 0x98, 31, 1);3518 3519/* reg_ptce3_large_entry_key_id3520 * Large entry key ID.3521 * A key for 12 key blocks rules. Reserved when region has less than 12 key3522 * blocks. Must be different for different keys which have the same common3523 * 6 key blocks (MSB, blocks 6..11) key within a region.3524 * Range is 0..cap_max_pe_large_key_id - 13525 * Access: RW3526 */3527MLXSW_ITEM32(reg, ptce3, large_entry_key_id, 0x98, 0, 24);3528 3529/* reg_ptce3_action_pointer3530 * Pointer to action.3531 * Range is 0..cap_max_kvd_action_sets - 13532 * Access: RW3533 */3534MLXSW_ITEM32(reg, ptce3, action_pointer, 0xA0, 0, 24);3535 3536static inline void mlxsw_reg_ptce3_pack(char *payload, bool valid,3537					enum mlxsw_reg_ptce3_op op,3538					u32 priority,3539					const char *tcam_region_info,3540					const char *key, u8 erp_id,3541					u16 delta_start, u8 delta_mask,3542					u8 delta_value, bool large_exists,3543					u32 lkey_id, u32 action_pointer)3544{3545	MLXSW_REG_ZERO(ptce3, payload);3546	mlxsw_reg_ptce3_v_set(payload, valid);3547	mlxsw_reg_ptce3_op_set(payload, op);3548	mlxsw_reg_ptce3_priority_set(payload, priority);3549	mlxsw_reg_ptce3_tcam_region_info_memcpy_to(payload, tcam_region_info);3550	mlxsw_reg_ptce3_flex2_key_blocks_memcpy_to(payload, key);3551	mlxsw_reg_ptce3_erp_id_set(payload, erp_id);3552	mlxsw_reg_ptce3_delta_start_set(payload, delta_start);3553	mlxsw_reg_ptce3_delta_mask_set(payload, delta_mask);3554	mlxsw_reg_ptce3_delta_value_set(payload, delta_value);3555	mlxsw_reg_ptce3_large_exists_set(payload, large_exists);3556	mlxsw_reg_ptce3_large_entry_key_id_set(payload, lkey_id);3557	mlxsw_reg_ptce3_action_pointer_set(payload, action_pointer);3558}3559 3560/* PERCR - Policy-Engine Region Configuration Register3561 * ---------------------------------------------------3562 * This register configures the region parameters. The region_id must be3563 * allocated.3564 */3565#define MLXSW_REG_PERCR_ID 0x302A3566#define MLXSW_REG_PERCR_LEN 0x803567 3568MLXSW_REG_DEFINE(percr, MLXSW_REG_PERCR_ID, MLXSW_REG_PERCR_LEN);3569 3570/* reg_percr_region_id3571 * Region identifier.3572 * Range 0..cap_max_regions-13573 * Access: Index3574 */3575MLXSW_ITEM32(reg, percr, region_id, 0x00, 0, 16);3576 3577/* reg_percr_atcam_ignore_prune3578 * Ignore prune_vector by other A-TCAM rules. Used e.g., for a new rule.3579 * Access: RW3580 */3581MLXSW_ITEM32(reg, percr, atcam_ignore_prune, 0x04, 25, 1);3582 3583/* reg_percr_ctcam_ignore_prune3584 * Ignore prune_ctcam by other A-TCAM rules. Used e.g., for a new rule.3585 * Access: RW3586 */3587MLXSW_ITEM32(reg, percr, ctcam_ignore_prune, 0x04, 24, 1);3588 3589/* reg_percr_bf_bypass3590 * Bloom filter bypass.3591 * 0 - Bloom filter is used (default)3592 * 1 - Bloom filter is bypassed. The bypass is an OR condition of3593 * region_id or eRP. See PERPT.bf_bypass3594 * Access: RW3595 */3596MLXSW_ITEM32(reg, percr, bf_bypass, 0x04, 16, 1);3597 3598/* reg_percr_master_mask3599 * Master mask. Logical OR mask of all masks of all rules of a region3600 * (both A-TCAM and C-TCAM). When there are no eRPs3601 * (erpt_pointer_valid = 0), then this provides the mask.3602 * Access: RW3603 */3604MLXSW_ITEM_BUF(reg, percr, master_mask, 0x20, 96);3605 3606static inline void mlxsw_reg_percr_pack(char *payload, u16 region_id)3607{3608	MLXSW_REG_ZERO(percr, payload);3609	mlxsw_reg_percr_region_id_set(payload, region_id);3610	mlxsw_reg_percr_atcam_ignore_prune_set(payload, false);3611	mlxsw_reg_percr_ctcam_ignore_prune_set(payload, false);3612	mlxsw_reg_percr_bf_bypass_set(payload, false);3613}3614 3615/* PERERP - Policy-Engine Region eRP Register3616 * ------------------------------------------3617 * This register configures the region eRP. The region_id must be3618 * allocated.3619 */3620#define MLXSW_REG_PERERP_ID 0x302B3621#define MLXSW_REG_PERERP_LEN 0x1C3622 3623MLXSW_REG_DEFINE(pererp, MLXSW_REG_PERERP_ID, MLXSW_REG_PERERP_LEN);3624 3625/* reg_pererp_region_id3626 * Region identifier.3627 * Range 0..cap_max_regions-13628 * Access: Index3629 */3630MLXSW_ITEM32(reg, pererp, region_id, 0x00, 0, 16);3631 3632/* reg_pererp_ctcam_le3633 * C-TCAM lookup enable. Reserved when erpt_pointer_valid = 0.3634 * Access: RW3635 */3636MLXSW_ITEM32(reg, pererp, ctcam_le, 0x04, 28, 1);3637 3638/* reg_pererp_erpt_pointer_valid3639 * erpt_pointer is valid.3640 * Access: RW3641 */3642MLXSW_ITEM32(reg, pererp, erpt_pointer_valid, 0x10, 31, 1);3643 3644/* reg_pererp_erpt_bank_pointer3645 * Pointer to eRP table bank. May be modified at any time.3646 * Range 0..cap_max_erp_table_banks-13647 * Reserved when erpt_pointer_valid = 03648 */3649MLXSW_ITEM32(reg, pererp, erpt_bank_pointer, 0x10, 16, 4);3650 3651/* reg_pererp_erpt_pointer3652 * Pointer to eRP table within the eRP bank. Can be changed for an3653 * existing region.3654 * Range 0..cap_max_erp_table_size-13655 * Reserved when erpt_pointer_valid = 03656 * Access: RW3657 */3658MLXSW_ITEM32(reg, pererp, erpt_pointer, 0x10, 0, 8);3659 3660/* reg_pererp_erpt_vector3661 * Vector of allowed eRP indexes starting from erpt_pointer within the3662 * erpt_bank_pointer. Next entries will be in next bank.3663 * Note that eRP index is used and not eRP ID.3664 * Reserved when erpt_pointer_valid = 03665 * Access: RW3666 */3667MLXSW_ITEM_BIT_ARRAY(reg, pererp, erpt_vector, 0x14, 4, 1);3668 3669/* reg_pererp_master_rp_id3670 * Master RP ID. When there are no eRPs, then this provides the eRP ID3671 * for the lookup. Can be changed for an existing region.3672 * Reserved when erpt_pointer_valid = 13673 * Access: RW3674 */3675MLXSW_ITEM32(reg, pererp, master_rp_id, 0x18, 0, 4);3676 3677static inline void mlxsw_reg_pererp_erp_vector_pack(char *payload,3678						    unsigned long *erp_vector,3679						    unsigned long size)3680{3681	unsigned long bit;3682 3683	for_each_set_bit(bit, erp_vector, size)3684		mlxsw_reg_pererp_erpt_vector_set(payload, bit, true);3685}3686 3687static inline void mlxsw_reg_pererp_pack(char *payload, u16 region_id,3688					 bool ctcam_le, bool erpt_pointer_valid,3689					 u8 erpt_bank_pointer, u8 erpt_pointer,3690					 u8 master_rp_id)3691{3692	MLXSW_REG_ZERO(pererp, payload);3693	mlxsw_reg_pererp_region_id_set(payload, region_id);3694	mlxsw_reg_pererp_ctcam_le_set(payload, ctcam_le);3695	mlxsw_reg_pererp_erpt_pointer_valid_set(payload, erpt_pointer_valid);3696	mlxsw_reg_pererp_erpt_bank_pointer_set(payload, erpt_bank_pointer);3697	mlxsw_reg_pererp_erpt_pointer_set(payload, erpt_pointer);3698	mlxsw_reg_pererp_master_rp_id_set(payload, master_rp_id);3699}3700 3701/* PEABFE - Policy-Engine Algorithmic Bloom Filter Entries Register3702 * ----------------------------------------------------------------3703 * This register configures the Bloom filter entries.3704 */3705#define MLXSW_REG_PEABFE_ID 0x30223706#define MLXSW_REG_PEABFE_BASE_LEN 0x103707#define MLXSW_REG_PEABFE_BF_REC_LEN 0x43708#define MLXSW_REG_PEABFE_BF_REC_MAX_COUNT 2563709#define MLXSW_REG_PEABFE_LEN (MLXSW_REG_PEABFE_BASE_LEN + \3710			      MLXSW_REG_PEABFE_BF_REC_LEN * \3711			      MLXSW_REG_PEABFE_BF_REC_MAX_COUNT)3712 3713MLXSW_REG_DEFINE(peabfe, MLXSW_REG_PEABFE_ID, MLXSW_REG_PEABFE_LEN);3714 3715/* reg_peabfe_size3716 * Number of BF entries to be updated.3717 * Range 1..2563718 * Access: Op3719 */3720MLXSW_ITEM32(reg, peabfe, size, 0x00, 0, 9);3721 3722/* reg_peabfe_bf_entry_state3723 * Bloom filter state3724 * 0 - Clear3725 * 1 - Set3726 * Access: RW3727 */3728MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_state,3729		     MLXSW_REG_PEABFE_BASE_LEN,	31, 1,3730		     MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false);3731 3732/* reg_peabfe_bf_entry_bank3733 * Bloom filter bank ID3734 * Range 0..cap_max_erp_table_banks-13735 * Access: Index3736 */3737MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_bank,3738		     MLXSW_REG_PEABFE_BASE_LEN,	24, 4,3739		     MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false);3740 3741/* reg_peabfe_bf_entry_index3742 * Bloom filter entry index3743 * Range 0..2^cap_max_bf_log-13744 * Access: Index3745 */3746MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_index,3747		     MLXSW_REG_PEABFE_BASE_LEN,	0, 24,3748		     MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false);3749 3750static inline void mlxsw_reg_peabfe_pack(char *payload)3751{3752	MLXSW_REG_ZERO(peabfe, payload);3753}3754 3755static inline void mlxsw_reg_peabfe_rec_pack(char *payload, int rec_index,3756					     u8 state, u8 bank, u32 bf_index)3757{3758	u8 num_rec = mlxsw_reg_peabfe_size_get(payload);3759 3760	if (rec_index >= num_rec)3761		mlxsw_reg_peabfe_size_set(payload, rec_index + 1);3762	mlxsw_reg_peabfe_bf_entry_state_set(payload, rec_index, state);3763	mlxsw_reg_peabfe_bf_entry_bank_set(payload, rec_index, bank);3764	mlxsw_reg_peabfe_bf_entry_index_set(payload, rec_index, bf_index);3765}3766 3767/* IEDR - Infrastructure Entry Delete Register3768 * ----------------------------------------------------3769 * This register is used for deleting entries from the entry tables.3770 * It is legitimate to attempt to delete a nonexisting entry (the device will3771 * respond as a good flow).3772 */3773#define MLXSW_REG_IEDR_ID 0x38043774#define MLXSW_REG_IEDR_BASE_LEN 0x10 /* base length, without records */3775#define MLXSW_REG_IEDR_REC_LEN 0x8 /* record length */3776#define MLXSW_REG_IEDR_REC_MAX_COUNT 643777#define MLXSW_REG_IEDR_LEN (MLXSW_REG_IEDR_BASE_LEN +	\3778			    MLXSW_REG_IEDR_REC_LEN *	\3779			    MLXSW_REG_IEDR_REC_MAX_COUNT)3780 3781MLXSW_REG_DEFINE(iedr, MLXSW_REG_IEDR_ID, MLXSW_REG_IEDR_LEN);3782 3783/* reg_iedr_num_rec3784 * Number of records.3785 * Access: OP3786 */3787MLXSW_ITEM32(reg, iedr, num_rec, 0x00, 0, 8);3788 3789/* reg_iedr_rec_type3790 * Resource type.3791 * Access: OP3792 */3793MLXSW_ITEM32_INDEXED(reg, iedr, rec_type, MLXSW_REG_IEDR_BASE_LEN, 24, 8,3794		     MLXSW_REG_IEDR_REC_LEN, 0x00, false);3795 3796/* reg_iedr_rec_size3797 * Size of entries do be deleted. The unit is 1 entry, regardless of entry type.3798 * Access: OP3799 */3800MLXSW_ITEM32_INDEXED(reg, iedr, rec_size, MLXSW_REG_IEDR_BASE_LEN, 0, 13,3801		     MLXSW_REG_IEDR_REC_LEN, 0x00, false);3802 3803/* reg_iedr_rec_index_start3804 * Resource index start.3805 * Access: OP3806 */3807MLXSW_ITEM32_INDEXED(reg, iedr, rec_index_start, MLXSW_REG_IEDR_BASE_LEN, 0, 24,3808		     MLXSW_REG_IEDR_REC_LEN, 0x04, false);3809 3810static inline void mlxsw_reg_iedr_pack(char *payload)3811{3812	MLXSW_REG_ZERO(iedr, payload);3813}3814 3815static inline void mlxsw_reg_iedr_rec_pack(char *payload, int rec_index,3816					   u8 rec_type, u16 rec_size,3817					   u32 rec_index_start)3818{3819	u8 num_rec = mlxsw_reg_iedr_num_rec_get(payload);3820 3821	if (rec_index >= num_rec)3822		mlxsw_reg_iedr_num_rec_set(payload, rec_index + 1);3823	mlxsw_reg_iedr_rec_type_set(payload, rec_index, rec_type);3824	mlxsw_reg_iedr_rec_size_set(payload, rec_index, rec_size);3825	mlxsw_reg_iedr_rec_index_start_set(payload, rec_index, rec_index_start);3826}3827 3828/* QPTS - QoS Priority Trust State Register3829 * ----------------------------------------3830 * This register controls the port policy to calculate the switch priority and3831 * packet color based on incoming packet fields.3832 */3833#define MLXSW_REG_QPTS_ID 0x40023834#define MLXSW_REG_QPTS_LEN 0x83835 3836MLXSW_REG_DEFINE(qpts, MLXSW_REG_QPTS_ID, MLXSW_REG_QPTS_LEN);3837 3838/* reg_qpts_local_port3839 * Local port number.3840 * Access: Index3841 *3842 * Note: CPU port is supported.3843 */3844MLXSW_ITEM32_LP(reg, qpts, 0x00, 16, 0x00, 12);3845 3846enum mlxsw_reg_qpts_trust_state {3847	MLXSW_REG_QPTS_TRUST_STATE_PCP = 1,3848	MLXSW_REG_QPTS_TRUST_STATE_DSCP = 2, /* For MPLS, trust EXP. */3849};3850 3851/* reg_qpts_trust_state3852 * Trust state for a given port.3853 * Access: RW3854 */3855MLXSW_ITEM32(reg, qpts, trust_state, 0x04, 0, 3);3856 3857static inline void mlxsw_reg_qpts_pack(char *payload, u16 local_port,3858				       enum mlxsw_reg_qpts_trust_state ts)3859{3860	MLXSW_REG_ZERO(qpts, payload);3861 3862	mlxsw_reg_qpts_local_port_set(payload, local_port);3863	mlxsw_reg_qpts_trust_state_set(payload, ts);3864}3865 3866/* QPCR - QoS Policer Configuration Register3867 * -----------------------------------------3868 * The QPCR register is used to create policers - that limit3869 * the rate of bytes or packets via some trap group.3870 */3871#define MLXSW_REG_QPCR_ID 0x40043872#define MLXSW_REG_QPCR_LEN 0x283873 3874MLXSW_REG_DEFINE(qpcr, MLXSW_REG_QPCR_ID, MLXSW_REG_QPCR_LEN);3875 3876enum mlxsw_reg_qpcr_g {3877	MLXSW_REG_QPCR_G_GLOBAL = 2,3878	MLXSW_REG_QPCR_G_STORM_CONTROL = 3,3879};3880 3881/* reg_qpcr_g3882 * The policer type.3883 * Access: Index3884 */3885MLXSW_ITEM32(reg, qpcr, g, 0x00, 14, 2);3886 3887/* reg_qpcr_pid3888 * Policer ID.3889 * Access: Index3890 */3891MLXSW_ITEM32(reg, qpcr, pid, 0x00, 0, 14);3892 3893/* reg_qpcr_clear_counter3894 * Clear counters.3895 * Access: OP3896 */3897MLXSW_ITEM32(reg, qpcr, clear_counter, 0x04, 31, 1);3898 3899/* reg_qpcr_color_aware3900 * Is the policer aware of colors.3901 * Must be 0 (unaware) for cpu port.3902 * Access: RW for unbounded policer. RO for bounded policer.3903 */3904MLXSW_ITEM32(reg, qpcr, color_aware, 0x04, 15, 1);3905 3906/* reg_qpcr_bytes3907 * Is policer limit is for bytes per sec or packets per sec.3908 * 0 - packets3909 * 1 - bytes3910 * Access: RW for unbounded policer. RO for bounded policer.3911 */3912MLXSW_ITEM32(reg, qpcr, bytes, 0x04, 14, 1);3913 3914enum mlxsw_reg_qpcr_ir_units {3915	MLXSW_REG_QPCR_IR_UNITS_M,3916	MLXSW_REG_QPCR_IR_UNITS_K,3917};3918 3919/* reg_qpcr_ir_units3920 * Policer's units for cir and eir fields (for bytes limits only)3921 * 1 - 10^33922 * 0 - 10^63923 * Access: OP3924 */3925MLXSW_ITEM32(reg, qpcr, ir_units, 0x04, 12, 1);3926 3927enum mlxsw_reg_qpcr_rate_type {3928	MLXSW_REG_QPCR_RATE_TYPE_SINGLE = 1,3929	MLXSW_REG_QPCR_RATE_TYPE_DOUBLE = 2,3930};3931 3932/* reg_qpcr_rate_type3933 * Policer can have one limit (single rate) or 2 limits with specific operation3934 * for packets that exceed the lower rate but not the upper one.3935 * (For cpu port must be single rate)3936 * Access: RW for unbounded policer. RO for bounded policer.3937 */3938MLXSW_ITEM32(reg, qpcr, rate_type, 0x04, 8, 2);3939 3940/* reg_qpc_cbs3941 * Policer's committed burst size.3942 * The policer is working with time slices of 50 nano sec. By default every3943 * slice is granted the proportionate share of the committed rate. If we want to3944 * allow a slice to exceed that share (while still keeping the rate per sec) we3945 * can allow burst. The burst size is between the default proportionate share3946 * (and no lower than 8) to 32Gb. (Even though giving a number higher than the3947 * committed rate will result in exceeding the rate). The burst size must be a3948 * log of 2 and will be determined by 2^cbs.3949 * Access: RW3950 */3951MLXSW_ITEM32(reg, qpcr, cbs, 0x08, 24, 6);3952 3953/* reg_qpcr_cir3954 * Policer's committed rate.3955 * The rate used for sungle rate, the lower rate for double rate.3956 * For bytes limits, the rate will be this value * the unit from ir_units.3957 * (Resolution error is up to 1%).3958 * Access: RW3959 */3960MLXSW_ITEM32(reg, qpcr, cir, 0x0C, 0, 32);3961 3962/* reg_qpcr_eir3963 * Policer's exceed rate.3964 * The higher rate for double rate, reserved for single rate.3965 * Lower rate for double rate policer.3966 * For bytes limits, the rate will be this value * the unit from ir_units.3967 * (Resolution error is up to 1%).3968 * Access: RW3969 */3970MLXSW_ITEM32(reg, qpcr, eir, 0x10, 0, 32);3971 3972#define MLXSW_REG_QPCR_DOUBLE_RATE_ACTION 23973 3974/* reg_qpcr_exceed_action.3975 * What to do with packets between the 2 limits for double rate.3976 * Access: RW for unbounded policer. RO for bounded policer.3977 */3978MLXSW_ITEM32(reg, qpcr, exceed_action, 0x14, 0, 4);3979 3980enum mlxsw_reg_qpcr_action {3981	/* Discard */3982	MLXSW_REG_QPCR_ACTION_DISCARD = 1,3983	/* Forward and set color to red.3984	 * If the packet is intended to cpu port, it will be dropped.3985	 */3986	MLXSW_REG_QPCR_ACTION_FORWARD = 2,3987};3988 3989/* reg_qpcr_violate_action3990 * What to do with packets that cross the cir limit (for single rate) or the eir3991 * limit (for double rate).3992 * Access: RW for unbounded policer. RO for bounded policer.3993 */3994MLXSW_ITEM32(reg, qpcr, violate_action, 0x18, 0, 4);3995 3996/* reg_qpcr_violate_count3997 * Counts the number of times violate_action happened on this PID.3998 * Access: RW3999 */4000MLXSW_ITEM64(reg, qpcr, violate_count, 0x20, 0, 64);4001 4002/* Packets */4003#define MLXSW_REG_QPCR_LOWEST_CIR	14004#define MLXSW_REG_QPCR_HIGHEST_CIR	(2 * 1000 * 1000 * 1000) /* 2Gpps */4005#define MLXSW_REG_QPCR_LOWEST_CBS	44006#define MLXSW_REG_QPCR_HIGHEST_CBS	244007 4008/* Bandwidth */4009#define MLXSW_REG_QPCR_LOWEST_CIR_BITS		1024 /* bps */4010#define MLXSW_REG_QPCR_HIGHEST_CIR_BITS		2000000000000ULL /* 2Tbps */4011#define MLXSW_REG_QPCR_LOWEST_CBS_BITS_SP1	44012#define MLXSW_REG_QPCR_LOWEST_CBS_BITS_SP2	44013#define MLXSW_REG_QPCR_HIGHEST_CBS_BITS_SP1	254014#define MLXSW_REG_QPCR_HIGHEST_CBS_BITS_SP2	314015 4016static inline void mlxsw_reg_qpcr_pack(char *payload, u16 pid,4017				       enum mlxsw_reg_qpcr_ir_units ir_units,4018				       bool bytes, u32 cir, u16 cbs)4019{4020	MLXSW_REG_ZERO(qpcr, payload);4021	mlxsw_reg_qpcr_pid_set(payload, pid);4022	mlxsw_reg_qpcr_g_set(payload, MLXSW_REG_QPCR_G_GLOBAL);4023	mlxsw_reg_qpcr_rate_type_set(payload, MLXSW_REG_QPCR_RATE_TYPE_SINGLE);4024	mlxsw_reg_qpcr_violate_action_set(payload,4025					  MLXSW_REG_QPCR_ACTION_DISCARD);4026	mlxsw_reg_qpcr_cir_set(payload, cir);4027	mlxsw_reg_qpcr_ir_units_set(payload, ir_units);4028	mlxsw_reg_qpcr_bytes_set(payload, bytes);4029	mlxsw_reg_qpcr_cbs_set(payload, cbs);4030}4031 4032/* QTCT - QoS Switch Traffic Class Table4033 * -------------------------------------4034 * Configures the mapping between the packet switch priority and the4035 * traffic class on the transmit port.4036 */4037#define MLXSW_REG_QTCT_ID 0x400A4038#define MLXSW_REG_QTCT_LEN 0x084039 4040MLXSW_REG_DEFINE(qtct, MLXSW_REG_QTCT_ID, MLXSW_REG_QTCT_LEN);4041 4042/* reg_qtct_local_port4043 * Local port number.4044 * Access: Index4045 *4046 * Note: CPU port is not supported.4047 */4048MLXSW_ITEM32_LP(reg, qtct, 0x00, 16, 0x00, 12);4049 4050/* reg_qtct_sub_port4051 * Virtual port within the physical port.4052 * Should be set to 0 when virtual ports are not enabled on the port.4053 * Access: Index4054 */4055MLXSW_ITEM32(reg, qtct, sub_port, 0x00, 8, 8);4056 4057/* reg_qtct_switch_prio4058 * Switch priority.4059 * Access: Index4060 */4061MLXSW_ITEM32(reg, qtct, switch_prio, 0x00, 0, 4);4062 4063/* reg_qtct_tclass4064 * Traffic class.4065 * Default values:4066 * switch_prio 0 : tclass 14067 * switch_prio 1 : tclass 04068 * switch_prio i : tclass i, for i > 14069 * Access: RW4070 */4071MLXSW_ITEM32(reg, qtct, tclass, 0x04, 0, 4);4072 4073static inline void mlxsw_reg_qtct_pack(char *payload, u16 local_port,4074				       u8 switch_prio, u8 tclass)4075{4076	MLXSW_REG_ZERO(qtct, payload);4077	mlxsw_reg_qtct_local_port_set(payload, local_port);4078	mlxsw_reg_qtct_switch_prio_set(payload, switch_prio);4079	mlxsw_reg_qtct_tclass_set(payload, tclass);4080}4081 4082/* QEEC - QoS ETS Element Configuration Register4083 * ---------------------------------------------4084 * Configures the ETS elements.4085 */4086#define MLXSW_REG_QEEC_ID 0x400D4087#define MLXSW_REG_QEEC_LEN 0x204088 4089MLXSW_REG_DEFINE(qeec, MLXSW_REG_QEEC_ID, MLXSW_REG_QEEC_LEN);4090 4091/* reg_qeec_local_port4092 * Local port number.4093 * Access: Index4094 *4095 * Note: CPU port is supported.4096 */4097MLXSW_ITEM32_LP(reg, qeec, 0x00, 16, 0x00, 12);4098 4099enum mlxsw_reg_qeec_hr {4100	MLXSW_REG_QEEC_HR_PORT,4101	MLXSW_REG_QEEC_HR_GROUP,4102	MLXSW_REG_QEEC_HR_SUBGROUP,4103	MLXSW_REG_QEEC_HR_TC,4104};4105 4106/* reg_qeec_element_hierarchy4107 * 0 - Port4108 * 1 - Group4109 * 2 - Subgroup4110 * 3 - Traffic Class4111 * Access: Index4112 */4113MLXSW_ITEM32(reg, qeec, element_hierarchy, 0x04, 16, 4);4114 4115/* reg_qeec_element_index4116 * The index of the element in the hierarchy.4117 * Access: Index4118 */4119MLXSW_ITEM32(reg, qeec, element_index, 0x04, 0, 8);4120 4121/* reg_qeec_next_element_index4122 * The index of the next (lower) element in the hierarchy.4123 * Access: RW4124 *4125 * Note: Reserved for element_hierarchy 0.4126 */4127MLXSW_ITEM32(reg, qeec, next_element_index, 0x08, 0, 8);4128 4129/* reg_qeec_mise4130 * Min shaper configuration enable. Enables configuration of the min4131 * shaper on this ETS element4132 * 0 - Disable4133 * 1 - Enable4134 * Access: RW4135 */4136MLXSW_ITEM32(reg, qeec, mise, 0x0C, 31, 1);4137 4138/* reg_qeec_ptps4139 * PTP shaper4140 * 0: regular shaper mode4141 * 1: PTP oriented shaper4142 * Allowed only for hierarchy 04143 * Not supported for CPU port4144 * Note that ptps mode may affect the shaper rates of all hierarchies4145 * Supported only on Spectrum-14146 * Access: RW4147 */4148MLXSW_ITEM32(reg, qeec, ptps, 0x0C, 29, 1);4149 4150enum {4151	MLXSW_REG_QEEC_BYTES_MODE,4152	MLXSW_REG_QEEC_PACKETS_MODE,4153};4154 4155/* reg_qeec_pb4156 * Packets or bytes mode.4157 * 0 - Bytes mode4158 * 1 - Packets mode4159 * Access: RW4160 *4161 * Note: Used for max shaper configuration. For Spectrum, packets mode4162 * is supported only for traffic classes of CPU port.4163 */4164MLXSW_ITEM32(reg, qeec, pb, 0x0C, 28, 1);4165 4166/* The smallest permitted min shaper rate. */4167#define MLXSW_REG_QEEC_MIS_MIN	200000		/* Kbps */4168 4169/* reg_qeec_min_shaper_rate4170 * Min shaper information rate.4171 * For CPU port, can only be configured for port hierarchy.4172 * When in bytes mode, value is specified in units of 1000bps.4173 * Access: RW4174 */4175MLXSW_ITEM32(reg, qeec, min_shaper_rate, 0x0C, 0, 28);4176 4177/* reg_qeec_mase4178 * Max shaper configuration enable. Enables configuration of the max4179 * shaper on this ETS element.4180 * 0 - Disable4181 * 1 - Enable4182 * Access: RW4183 */4184MLXSW_ITEM32(reg, qeec, mase, 0x10, 31, 1);4185 4186/* The largest max shaper value possible to disable the shaper. */4187#define MLXSW_REG_QEEC_MAS_DIS	((1u << 31) - 1)	/* Kbps */4188 4189/* reg_qeec_max_shaper_rate4190 * Max shaper information rate.4191 * For CPU port, can only be configured for port hierarchy.4192 * When in bytes mode, value is specified in units of 1000bps.4193 * Access: RW4194 */4195MLXSW_ITEM32(reg, qeec, max_shaper_rate, 0x10, 0, 31);4196 4197/* reg_qeec_de4198 * DWRR configuration enable. Enables configuration of the dwrr and4199 * dwrr_weight.4200 * 0 - Disable4201 * 1 - Enable4202 * Access: RW4203 */4204MLXSW_ITEM32(reg, qeec, de, 0x18, 31, 1);4205 4206/* reg_qeec_dwrr4207 * Transmission selection algorithm to use on the link going down from4208 * the ETS element.4209 * 0 - Strict priority4210 * 1 - DWRR4211 * Access: RW4212 */4213MLXSW_ITEM32(reg, qeec, dwrr, 0x18, 15, 1);4214 4215/* reg_qeec_dwrr_weight4216 * DWRR weight on the link going down from the ETS element. The4217 * percentage of bandwidth guaranteed to an ETS element within4218 * its hierarchy. The sum of all weights across all ETS elements4219 * within one hierarchy should be equal to 100. Reserved when4220 * transmission selection algorithm is strict priority.4221 * Access: RW4222 */4223MLXSW_ITEM32(reg, qeec, dwrr_weight, 0x18, 0, 8);4224 4225/* reg_qeec_max_shaper_bs4226 * Max shaper burst size4227 * Burst size is 2^max_shaper_bs * 512 bits4228 * For Spectrum-1: Range is: 5..254229 * For Spectrum-2: Range is: 11..254230 * Reserved when ptps = 14231 * Access: RW4232 */4233MLXSW_ITEM32(reg, qeec, max_shaper_bs, 0x1C, 0, 6);4234 4235#define MLXSW_REG_QEEC_HIGHEST_SHAPER_BS	254236#define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP1	54237#define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP2	114238#define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP3	114239#define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP4	114240 4241static inline void mlxsw_reg_qeec_pack(char *payload, u16 local_port,4242				       enum mlxsw_reg_qeec_hr hr, u8 index,4243				       u8 next_index)4244{4245	MLXSW_REG_ZERO(qeec, payload);4246	mlxsw_reg_qeec_local_port_set(payload, local_port);4247	mlxsw_reg_qeec_element_hierarchy_set(payload, hr);4248	mlxsw_reg_qeec_element_index_set(payload, index);4249	mlxsw_reg_qeec_next_element_index_set(payload, next_index);4250}4251 4252static inline void mlxsw_reg_qeec_ptps_pack(char *payload, u16 local_port,4253					    bool ptps)4254{4255	MLXSW_REG_ZERO(qeec, payload);4256	mlxsw_reg_qeec_local_port_set(payload, local_port);4257	mlxsw_reg_qeec_element_hierarchy_set(payload, MLXSW_REG_QEEC_HR_PORT);4258	mlxsw_reg_qeec_ptps_set(payload, ptps);4259}4260 4261/* QRWE - QoS ReWrite Enable4262 * -------------------------4263 * This register configures the rewrite enable per receive port.4264 */4265#define MLXSW_REG_QRWE_ID 0x400F4266#define MLXSW_REG_QRWE_LEN 0x084267 4268MLXSW_REG_DEFINE(qrwe, MLXSW_REG_QRWE_ID, MLXSW_REG_QRWE_LEN);4269 4270/* reg_qrwe_local_port4271 * Local port number.4272 * Access: Index4273 *4274 * Note: CPU port is supported. No support for router port.4275 */4276MLXSW_ITEM32_LP(reg, qrwe, 0x00, 16, 0x00, 12);4277 4278/* reg_qrwe_dscp4279 * Whether to enable DSCP rewrite (default is 0, don't rewrite).4280 * Access: RW4281 */4282MLXSW_ITEM32(reg, qrwe, dscp, 0x04, 1, 1);4283 4284/* reg_qrwe_pcp4285 * Whether to enable PCP and DEI rewrite (default is 0, don't rewrite).4286 * Access: RW4287 */4288MLXSW_ITEM32(reg, qrwe, pcp, 0x04, 0, 1);4289 4290static inline void mlxsw_reg_qrwe_pack(char *payload, u16 local_port,4291				       bool rewrite_pcp, bool rewrite_dscp)4292{4293	MLXSW_REG_ZERO(qrwe, payload);4294	mlxsw_reg_qrwe_local_port_set(payload, local_port);4295	mlxsw_reg_qrwe_pcp_set(payload, rewrite_pcp);4296	mlxsw_reg_qrwe_dscp_set(payload, rewrite_dscp);4297}4298 4299/* QPDSM - QoS Priority to DSCP Mapping4300 * ------------------------------------4301 * QoS Priority to DSCP Mapping Register4302 */4303#define MLXSW_REG_QPDSM_ID 0x40114304#define MLXSW_REG_QPDSM_BASE_LEN 0x04 /* base length, without records */4305#define MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN 0x4 /* record length */4306#define MLXSW_REG_QPDSM_PRIO_ENTRY_REC_MAX_COUNT 164307#define MLXSW_REG_QPDSM_LEN (MLXSW_REG_QPDSM_BASE_LEN +			\4308			     MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN *	\4309			     MLXSW_REG_QPDSM_PRIO_ENTRY_REC_MAX_COUNT)4310 4311MLXSW_REG_DEFINE(qpdsm, MLXSW_REG_QPDSM_ID, MLXSW_REG_QPDSM_LEN);4312 4313/* reg_qpdsm_local_port4314 * Local Port. Supported for data packets from CPU port.4315 * Access: Index4316 */4317MLXSW_ITEM32_LP(reg, qpdsm, 0x00, 16, 0x00, 12);4318 4319/* reg_qpdsm_prio_entry_color0_e4320 * Enable update of the entry for color 0 and a given port.4321 * Access: WO4322 */4323MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color0_e,4324		     MLXSW_REG_QPDSM_BASE_LEN, 31, 1,4325		     MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);4326 4327/* reg_qpdsm_prio_entry_color0_dscp4328 * DSCP field in the outer label of the packet for color 0 and a given port.4329 * Reserved when e=0.4330 * Access: RW4331 */4332MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color0_dscp,4333		     MLXSW_REG_QPDSM_BASE_LEN, 24, 6,4334		     MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);4335 4336/* reg_qpdsm_prio_entry_color1_e4337 * Enable update of the entry for color 1 and a given port.4338 * Access: WO4339 */4340MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color1_e,4341		     MLXSW_REG_QPDSM_BASE_LEN, 23, 1,4342		     MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);4343 4344/* reg_qpdsm_prio_entry_color1_dscp4345 * DSCP field in the outer label of the packet for color 1 and a given port.4346 * Reserved when e=0.4347 * Access: RW4348 */4349MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color1_dscp,4350		     MLXSW_REG_QPDSM_BASE_LEN, 16, 6,4351		     MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);4352 4353/* reg_qpdsm_prio_entry_color2_e4354 * Enable update of the entry for color 2 and a given port.4355 * Access: WO4356 */4357MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color2_e,4358		     MLXSW_REG_QPDSM_BASE_LEN, 15, 1,4359		     MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);4360 4361/* reg_qpdsm_prio_entry_color2_dscp4362 * DSCP field in the outer label of the packet for color 2 and a given port.4363 * Reserved when e=0.4364 * Access: RW4365 */4366MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color2_dscp,4367		     MLXSW_REG_QPDSM_BASE_LEN, 8, 6,4368		     MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);4369 4370static inline void mlxsw_reg_qpdsm_pack(char *payload, u16 local_port)4371{4372	MLXSW_REG_ZERO(qpdsm, payload);4373	mlxsw_reg_qpdsm_local_port_set(payload, local_port);4374}4375 4376static inline void4377mlxsw_reg_qpdsm_prio_pack(char *payload, unsigned short prio, u8 dscp)4378{4379	mlxsw_reg_qpdsm_prio_entry_color0_e_set(payload, prio, 1);4380	mlxsw_reg_qpdsm_prio_entry_color0_dscp_set(payload, prio, dscp);4381	mlxsw_reg_qpdsm_prio_entry_color1_e_set(payload, prio, 1);4382	mlxsw_reg_qpdsm_prio_entry_color1_dscp_set(payload, prio, dscp);4383	mlxsw_reg_qpdsm_prio_entry_color2_e_set(payload, prio, 1);4384	mlxsw_reg_qpdsm_prio_entry_color2_dscp_set(payload, prio, dscp);4385}4386 4387/* QPDP - QoS Port DSCP to Priority Mapping Register4388 * -------------------------------------------------4389 * This register controls the port default Switch Priority and Color. The4390 * default Switch Priority and Color are used for frames where the trust state4391 * uses default values. All member ports of a LAG should be configured with the4392 * same default values.4393 */4394#define MLXSW_REG_QPDP_ID 0x40074395#define MLXSW_REG_QPDP_LEN 0x84396 4397MLXSW_REG_DEFINE(qpdp, MLXSW_REG_QPDP_ID, MLXSW_REG_QPDP_LEN);4398 4399/* reg_qpdp_local_port4400 * Local Port. Supported for data packets from CPU port.4401 * Access: Index4402 */4403MLXSW_ITEM32_LP(reg, qpdp, 0x00, 16, 0x00, 12);4404 4405/* reg_qpdp_switch_prio4406 * Default port Switch Priority (default 0)4407 * Access: RW4408 */4409MLXSW_ITEM32(reg, qpdp, switch_prio, 0x04, 0, 4);4410 4411static inline void mlxsw_reg_qpdp_pack(char *payload, u16 local_port,4412				       u8 switch_prio)4413{4414	MLXSW_REG_ZERO(qpdp, payload);4415	mlxsw_reg_qpdp_local_port_set(payload, local_port);4416	mlxsw_reg_qpdp_switch_prio_set(payload, switch_prio);4417}4418 4419/* QPDPM - QoS Port DSCP to Priority Mapping Register4420 * --------------------------------------------------4421 * This register controls the mapping from DSCP field to4422 * Switch Priority for IP packets.4423 */4424#define MLXSW_REG_QPDPM_ID 0x40134425#define MLXSW_REG_QPDPM_BASE_LEN 0x4 /* base length, without records */4426#define MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN 0x2 /* record length */4427#define MLXSW_REG_QPDPM_DSCP_ENTRY_REC_MAX_COUNT 644428#define MLXSW_REG_QPDPM_LEN (MLXSW_REG_QPDPM_BASE_LEN +			\4429			     MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN *	\4430			     MLXSW_REG_QPDPM_DSCP_ENTRY_REC_MAX_COUNT)4431 4432MLXSW_REG_DEFINE(qpdpm, MLXSW_REG_QPDPM_ID, MLXSW_REG_QPDPM_LEN);4433 4434/* reg_qpdpm_local_port4435 * Local Port. Supported for data packets from CPU port.4436 * Access: Index4437 */4438MLXSW_ITEM32_LP(reg, qpdpm, 0x00, 16, 0x00, 12);4439 4440/* reg_qpdpm_dscp_e4441 * Enable update of the specific entry. When cleared, the switch_prio and color4442 * fields are ignored and the previous switch_prio and color values are4443 * preserved.4444 * Access: WO4445 */4446MLXSW_ITEM16_INDEXED(reg, qpdpm, dscp_entry_e, MLXSW_REG_QPDPM_BASE_LEN, 15, 1,4447		     MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN, 0x00, false);4448 4449/* reg_qpdpm_dscp_prio4450 * The new Switch Priority value for the relevant DSCP value.4451 * Access: RW4452 */4453MLXSW_ITEM16_INDEXED(reg, qpdpm, dscp_entry_prio,4454		     MLXSW_REG_QPDPM_BASE_LEN, 0, 4,4455		     MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN, 0x00, false);4456 4457static inline void mlxsw_reg_qpdpm_pack(char *payload, u16 local_port)4458{4459	MLXSW_REG_ZERO(qpdpm, payload);4460	mlxsw_reg_qpdpm_local_port_set(payload, local_port);4461}4462 4463static inline void4464mlxsw_reg_qpdpm_dscp_pack(char *payload, unsigned short dscp, u8 prio)4465{4466	mlxsw_reg_qpdpm_dscp_entry_e_set(payload, dscp, 1);4467	mlxsw_reg_qpdpm_dscp_entry_prio_set(payload, dscp, prio);4468}4469 4470/* QTCTM - QoS Switch Traffic Class Table is Multicast-Aware Register4471 * ------------------------------------------------------------------4472 * This register configures if the Switch Priority to Traffic Class mapping is4473 * based on Multicast packet indication. If so, then multicast packets will get4474 * a Traffic Class that is plus (cap_max_tclass_data/2) the value configured by4475 * QTCT.4476 * By default, Switch Priority to Traffic Class mapping is not based on4477 * Multicast packet indication.4478 */4479#define MLXSW_REG_QTCTM_ID 0x401A4480#define MLXSW_REG_QTCTM_LEN 0x084481 4482MLXSW_REG_DEFINE(qtctm, MLXSW_REG_QTCTM_ID, MLXSW_REG_QTCTM_LEN);4483 4484/* reg_qtctm_local_port4485 * Local port number.4486 * No support for CPU port.4487 * Access: Index4488 */4489MLXSW_ITEM32_LP(reg, qtctm, 0x00, 16, 0x00, 12);4490 4491/* reg_qtctm_mc4492 * Multicast Mode4493 * Whether Switch Priority to Traffic Class mapping is based on Multicast packet4494 * indication (default is 0, not based on Multicast packet indication).4495 */4496MLXSW_ITEM32(reg, qtctm, mc, 0x04, 0, 1);4497 4498static inline void4499mlxsw_reg_qtctm_pack(char *payload, u16 local_port, bool mc)4500{4501	MLXSW_REG_ZERO(qtctm, payload);4502	mlxsw_reg_qtctm_local_port_set(payload, local_port);4503	mlxsw_reg_qtctm_mc_set(payload, mc);4504}4505 4506/* QPSC - QoS PTP Shaper Configuration Register4507 * --------------------------------------------4508 * The QPSC allows advanced configuration of the shapers when QEEC.ptps=1.4509 * Supported only on Spectrum-1.4510 */4511#define MLXSW_REG_QPSC_ID 0x401B4512#define MLXSW_REG_QPSC_LEN 0x284513 4514MLXSW_REG_DEFINE(qpsc, MLXSW_REG_QPSC_ID, MLXSW_REG_QPSC_LEN);4515 4516enum mlxsw_reg_qpsc_port_speed {4517	MLXSW_REG_QPSC_PORT_SPEED_100M,4518	MLXSW_REG_QPSC_PORT_SPEED_1G,4519	MLXSW_REG_QPSC_PORT_SPEED_10G,4520	MLXSW_REG_QPSC_PORT_SPEED_25G,4521};4522 4523/* reg_qpsc_port_speed4524 * Port speed.4525 * Access: Index4526 */4527MLXSW_ITEM32(reg, qpsc, port_speed, 0x00, 0, 4);4528 4529/* reg_qpsc_shaper_time_exp4530 * The base-time-interval for updating the shapers tokens (for all hierarchies).4531 * shaper_update_rate = 2 ^ shaper_time_exp * (1 + shaper_time_mantissa) * 32nSec4532 * shaper_rate = 64bit * shaper_inc / shaper_update_rate4533 * Access: RW4534 */4535MLXSW_ITEM32(reg, qpsc, shaper_time_exp, 0x04, 16, 4);4536 4537/* reg_qpsc_shaper_time_mantissa4538 * The base-time-interval for updating the shapers tokens (for all hierarchies).4539 * shaper_update_rate = 2 ^ shaper_time_exp * (1 + shaper_time_mantissa) * 32nSec4540 * shaper_rate = 64bit * shaper_inc / shaper_update_rate4541 * Access: RW4542 */4543MLXSW_ITEM32(reg, qpsc, shaper_time_mantissa, 0x04, 0, 5);4544 4545/* reg_qpsc_shaper_inc4546 * Number of tokens added to shaper on each update.4547 * Units of 8B.4548 * Access: RW4549 */4550MLXSW_ITEM32(reg, qpsc, shaper_inc, 0x08, 0, 5);4551 4552/* reg_qpsc_shaper_bs4553 * Max shaper Burst size.4554 * Burst size is 2 ^ max_shaper_bs * 512 [bits]4555 * Range is: 5..25 (from 2KB..2GB)4556 * Access: RW4557 */4558MLXSW_ITEM32(reg, qpsc, shaper_bs, 0x0C, 0, 6);4559 4560/* reg_qpsc_ptsc_we4561 * Write enable to port_to_shaper_credits.4562 * Access: WO4563 */4564MLXSW_ITEM32(reg, qpsc, ptsc_we, 0x10, 31, 1);4565 4566/* reg_qpsc_port_to_shaper_credits4567 * For split ports: range 1..574568 * For non-split ports: range 1..1124569 * Written only when ptsc_we is set.4570 * Access: RW4571 */4572MLXSW_ITEM32(reg, qpsc, port_to_shaper_credits, 0x10, 0, 8);4573 4574/* reg_qpsc_ing_timestamp_inc4575 * Ingress timestamp increment.4576 * 2's complement.4577 * The timestamp of MTPPTR at ingress will be incremented by this value. Global4578 * value for all ports.4579 * Same units as used by MTPPTR.4580 * Access: RW4581 */4582MLXSW_ITEM32(reg, qpsc, ing_timestamp_inc, 0x20, 0, 32);4583 4584/* reg_qpsc_egr_timestamp_inc4585 * Egress timestamp increment.4586 * 2's complement.4587 * The timestamp of MTPPTR at egress will be incremented by this value. Global4588 * value for all ports.4589 * Same units as used by MTPPTR.4590 * Access: RW4591 */4592MLXSW_ITEM32(reg, qpsc, egr_timestamp_inc, 0x24, 0, 32);4593 4594static inline void4595mlxsw_reg_qpsc_pack(char *payload, enum mlxsw_reg_qpsc_port_speed port_speed,4596		    u8 shaper_time_exp, u8 shaper_time_mantissa, u8 shaper_inc,4597		    u8 shaper_bs, u8 port_to_shaper_credits,4598		    int ing_timestamp_inc, int egr_timestamp_inc)4599{4600	MLXSW_REG_ZERO(qpsc, payload);4601	mlxsw_reg_qpsc_port_speed_set(payload, port_speed);4602	mlxsw_reg_qpsc_shaper_time_exp_set(payload, shaper_time_exp);4603	mlxsw_reg_qpsc_shaper_time_mantissa_set(payload, shaper_time_mantissa);4604	mlxsw_reg_qpsc_shaper_inc_set(payload, shaper_inc);4605	mlxsw_reg_qpsc_shaper_bs_set(payload, shaper_bs);4606	mlxsw_reg_qpsc_ptsc_we_set(payload, true);4607	mlxsw_reg_qpsc_port_to_shaper_credits_set(payload, port_to_shaper_credits);4608	mlxsw_reg_qpsc_ing_timestamp_inc_set(payload, ing_timestamp_inc);4609	mlxsw_reg_qpsc_egr_timestamp_inc_set(payload, egr_timestamp_inc);4610}4611 4612/* PMLP - Ports Module to Local Port Register4613 * ------------------------------------------4614 * Configures the assignment of modules to local ports.4615 */4616#define MLXSW_REG_PMLP_ID 0x50024617#define MLXSW_REG_PMLP_LEN 0x404618 4619MLXSW_REG_DEFINE(pmlp, MLXSW_REG_PMLP_ID, MLXSW_REG_PMLP_LEN);4620 4621/* reg_pmlp_rxtx4622 * 0 - Tx value is used for both Tx and Rx.4623 * 1 - Rx value is taken from a separte field.4624 * Access: RW4625 */4626MLXSW_ITEM32(reg, pmlp, rxtx, 0x00, 31, 1);4627 4628/* reg_pmlp_local_port4629 * Local port number.4630 * Access: Index4631 */4632MLXSW_ITEM32_LP(reg, pmlp, 0x00, 16, 0x00, 12);4633 4634/* reg_pmlp_width4635 * 0 - Unmap local port.4636 * 1 - Lane 0 is used.4637 * 2 - Lanes 0 and 1 are used.4638 * 4 - Lanes 0, 1, 2 and 3 are used.4639 * 8 - Lanes 0-7 are used.4640 * Access: RW4641 */4642MLXSW_ITEM32(reg, pmlp, width, 0x00, 0, 8);4643 4644/* reg_pmlp_module4645 * Module number.4646 * Access: RW4647 */4648MLXSW_ITEM32_INDEXED(reg, pmlp, module, 0x04, 0, 8, 0x04, 0x00, false);4649 4650/* reg_pmlp_slot_index4651 * Module number.4652 * Slot_index4653 * Slot_index = 0 represent the onboard (motherboard).4654 * In case of non-modular system only slot_index = 0 is available.4655 * Access: RW4656 */4657MLXSW_ITEM32_INDEXED(reg, pmlp, slot_index, 0x04, 8, 4, 0x04, 0x00, false);4658 4659/* reg_pmlp_tx_lane4660 * Tx Lane. When rxtx field is cleared, this field is used for Rx as well.4661 * Access: RW4662 */4663MLXSW_ITEM32_INDEXED(reg, pmlp, tx_lane, 0x04, 16, 4, 0x04, 0x00, false);4664 4665/* reg_pmlp_rx_lane4666 * Rx Lane. When rxtx field is cleared, this field is ignored and Rx lane is4667 * equal to Tx lane.4668 * Access: RW4669 */4670MLXSW_ITEM32_INDEXED(reg, pmlp, rx_lane, 0x04, 24, 4, 0x04, 0x00, false);4671 4672static inline void mlxsw_reg_pmlp_pack(char *payload, u16 local_port)4673{4674	MLXSW_REG_ZERO(pmlp, payload);4675	mlxsw_reg_pmlp_local_port_set(payload, local_port);4676}4677 4678/* PMTU - Port MTU Register4679 * ------------------------4680 * Configures and reports the port MTU.4681 */4682#define MLXSW_REG_PMTU_ID 0x50034683#define MLXSW_REG_PMTU_LEN 0x104684 4685MLXSW_REG_DEFINE(pmtu, MLXSW_REG_PMTU_ID, MLXSW_REG_PMTU_LEN);4686 4687/* reg_pmtu_local_port4688 * Local port number.4689 * Access: Index4690 */4691MLXSW_ITEM32_LP(reg, pmtu, 0x00, 16, 0x00, 12);4692 4693/* reg_pmtu_max_mtu4694 * Maximum MTU.4695 * When port type (e.g. Ethernet) is configured, the relevant MTU is4696 * reported, otherwise the minimum between the max_mtu of the different4697 * types is reported.4698 * Access: RO4699 */4700MLXSW_ITEM32(reg, pmtu, max_mtu, 0x04, 16, 16);4701 4702/* reg_pmtu_admin_mtu4703 * MTU value to set port to. Must be smaller or equal to max_mtu.4704 * Note: If port type is Infiniband, then port must be disabled, when its4705 * MTU is set.4706 * Access: RW4707 */4708MLXSW_ITEM32(reg, pmtu, admin_mtu, 0x08, 16, 16);4709 4710/* reg_pmtu_oper_mtu4711 * The actual MTU configured on the port. Packets exceeding this size4712 * will be dropped.4713 * Note: In Ethernet and FC oper_mtu == admin_mtu, however, in Infiniband4714 * oper_mtu might be smaller than admin_mtu.4715 * Access: RO4716 */4717MLXSW_ITEM32(reg, pmtu, oper_mtu, 0x0C, 16, 16);4718 4719static inline void mlxsw_reg_pmtu_pack(char *payload, u16 local_port,4720				       u16 new_mtu)4721{4722	MLXSW_REG_ZERO(pmtu, payload);4723	mlxsw_reg_pmtu_local_port_set(payload, local_port);4724	mlxsw_reg_pmtu_max_mtu_set(payload, 0);4725	mlxsw_reg_pmtu_admin_mtu_set(payload, new_mtu);4726	mlxsw_reg_pmtu_oper_mtu_set(payload, 0);4727}4728 4729/* PTYS - Port Type and Speed Register4730 * -----------------------------------4731 * Configures and reports the port speed type.4732 *4733 * Note: When set while the link is up, the changes will not take effect4734 * until the port transitions from down to up state.4735 */4736#define MLXSW_REG_PTYS_ID 0x50044737#define MLXSW_REG_PTYS_LEN 0x404738 4739MLXSW_REG_DEFINE(ptys, MLXSW_REG_PTYS_ID, MLXSW_REG_PTYS_LEN);4740 4741/* an_disable_admin4742 * Auto negotiation disable administrative configuration4743 * 0 - Device doesn't support AN disable.4744 * 1 - Device supports AN disable.4745 * Access: RW4746 */4747MLXSW_ITEM32(reg, ptys, an_disable_admin, 0x00, 30, 1);4748 4749/* reg_ptys_local_port4750 * Local port number.4751 * Access: Index4752 */4753MLXSW_ITEM32_LP(reg, ptys, 0x00, 16, 0x00, 12);4754 4755#define MLXSW_REG_PTYS_PROTO_MASK_IB	BIT(0)4756#define MLXSW_REG_PTYS_PROTO_MASK_ETH	BIT(2)4757 4758/* reg_ptys_proto_mask4759 * Protocol mask. Indicates which protocol is used.4760 * 0 - Infiniband.4761 * 1 - Fibre Channel.4762 * 2 - Ethernet.4763 * Access: Index4764 */4765MLXSW_ITEM32(reg, ptys, proto_mask, 0x00, 0, 3);4766 4767enum {4768	MLXSW_REG_PTYS_AN_STATUS_NA,4769	MLXSW_REG_PTYS_AN_STATUS_OK,4770	MLXSW_REG_PTYS_AN_STATUS_FAIL,4771};4772 4773/* reg_ptys_an_status4774 * Autonegotiation status.4775 * Access: RO4776 */4777MLXSW_ITEM32(reg, ptys, an_status, 0x04, 28, 4);4778 4779#define MLXSW_REG_PTYS_EXT_ETH_SPEED_SGMII_100M				BIT(0)4780#define MLXSW_REG_PTYS_EXT_ETH_SPEED_1000BASE_X_SGMII			BIT(1)4781#define MLXSW_REG_PTYS_EXT_ETH_SPEED_5GBASE_R				BIT(3)4782#define MLXSW_REG_PTYS_EXT_ETH_SPEED_XFI_XAUI_1_10G			BIT(4)4783#define MLXSW_REG_PTYS_EXT_ETH_SPEED_XLAUI_4_XLPPI_4_40G		BIT(5)4784#define MLXSW_REG_PTYS_EXT_ETH_SPEED_25GAUI_1_25GBASE_CR_KR		BIT(6)4785#define MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_2_LAUI_2_50GBASE_CR2_KR2	BIT(7)4786#define MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_1_LAUI_1_50GBASE_CR_KR	BIT(8)4787#define MLXSW_REG_PTYS_EXT_ETH_SPEED_CAUI_4_100GBASE_CR4_KR4		BIT(9)4788#define MLXSW_REG_PTYS_EXT_ETH_SPEED_100GAUI_2_100GBASE_CR2_KR2		BIT(10)4789#define MLXSW_REG_PTYS_EXT_ETH_SPEED_100GAUI_1_100GBASE_CR_KR		BIT(11)4790#define MLXSW_REG_PTYS_EXT_ETH_SPEED_200GAUI_4_200GBASE_CR4_KR4		BIT(12)4791#define MLXSW_REG_PTYS_EXT_ETH_SPEED_200GAUI_2_200GBASE_CR2_KR2		BIT(13)4792#define MLXSW_REG_PTYS_EXT_ETH_SPEED_400GAUI_8				BIT(15)4793#define MLXSW_REG_PTYS_EXT_ETH_SPEED_400GAUI_4_400GBASE_CR4_KR4		BIT(16)4794#define MLXSW_REG_PTYS_EXT_ETH_SPEED_800GAUI_8				BIT(19)4795 4796/* reg_ptys_ext_eth_proto_cap4797 * Extended Ethernet port supported speeds and protocols.4798 * Access: RO4799 */4800MLXSW_ITEM32(reg, ptys, ext_eth_proto_cap, 0x08, 0, 32);4801 4802#define MLXSW_REG_PTYS_ETH_SPEED_SGMII			BIT(0)4803#define MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX		BIT(1)4804#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4		BIT(2)4805#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4		BIT(3)4806#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR		BIT(4)4807#define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4		BIT(6)4808#define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4		BIT(7)4809#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR		BIT(12)4810#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR		BIT(13)4811#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR		BIT(14)4812#define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4		BIT(15)4813#define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4	BIT(16)4814#define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2		BIT(18)4815#define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR4		BIT(19)4816#define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4		BIT(20)4817#define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4		BIT(21)4818#define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4		BIT(22)4819#define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4	BIT(23)4820#define MLXSW_REG_PTYS_ETH_SPEED_100BASE_T		BIT(24)4821#define MLXSW_REG_PTYS_ETH_SPEED_1000BASE_T		BIT(25)4822#define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR		BIT(27)4823#define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR		BIT(28)4824#define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR		BIT(29)4825#define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2		BIT(30)4826#define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2		BIT(31)4827 4828/* reg_ptys_eth_proto_cap4829 * Ethernet port supported speeds and protocols.4830 * Access: RO4831 */4832MLXSW_ITEM32(reg, ptys, eth_proto_cap, 0x0C, 0, 32);4833 4834/* reg_ptys_ext_eth_proto_admin4835 * Extended speed and protocol to set port to.4836 * Access: RW4837 */4838MLXSW_ITEM32(reg, ptys, ext_eth_proto_admin, 0x14, 0, 32);4839 4840/* reg_ptys_eth_proto_admin4841 * Speed and protocol to set port to.4842 * Access: RW4843 */4844MLXSW_ITEM32(reg, ptys, eth_proto_admin, 0x18, 0, 32);4845 4846/* reg_ptys_ext_eth_proto_oper4847 * The extended current speed and protocol configured for the port.4848 * Access: RO4849 */4850MLXSW_ITEM32(reg, ptys, ext_eth_proto_oper, 0x20, 0, 32);4851 4852/* reg_ptys_eth_proto_oper4853 * The current speed and protocol configured for the port.4854 * Access: RO4855 */4856MLXSW_ITEM32(reg, ptys, eth_proto_oper, 0x24, 0, 32);4857 4858enum mlxsw_reg_ptys_connector_type {4859	MLXSW_REG_PTYS_CONNECTOR_TYPE_UNKNOWN_OR_NO_CONNECTOR,4860	MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_NONE,4861	MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_TP,4862	MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_AUI,4863	MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_BNC,4864	MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_MII,4865	MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_FIBRE,4866	MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_DA,4867	MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_OTHER,4868};4869 4870/* reg_ptys_connector_type4871 * Connector type indication.4872 * Access: RO4873 */4874MLXSW_ITEM32(reg, ptys, connector_type, 0x2C, 0, 4);4875 4876static inline void mlxsw_reg_ptys_eth_pack(char *payload, u16 local_port,4877					   u32 proto_admin, bool autoneg)4878{4879	MLXSW_REG_ZERO(ptys, payload);4880	mlxsw_reg_ptys_local_port_set(payload, local_port);4881	mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH);4882	mlxsw_reg_ptys_eth_proto_admin_set(payload, proto_admin);4883	mlxsw_reg_ptys_an_disable_admin_set(payload, !autoneg);4884}4885 4886static inline void mlxsw_reg_ptys_ext_eth_pack(char *payload, u16 local_port,4887					       u32 proto_admin, bool autoneg)4888{4889	MLXSW_REG_ZERO(ptys, payload);4890	mlxsw_reg_ptys_local_port_set(payload, local_port);4891	mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH);4892	mlxsw_reg_ptys_ext_eth_proto_admin_set(payload, proto_admin);4893	mlxsw_reg_ptys_an_disable_admin_set(payload, !autoneg);4894}4895 4896static inline void mlxsw_reg_ptys_eth_unpack(char *payload,4897					     u32 *p_eth_proto_cap,4898					     u32 *p_eth_proto_admin,4899					     u32 *p_eth_proto_oper)4900{4901	if (p_eth_proto_cap)4902		*p_eth_proto_cap =4903			mlxsw_reg_ptys_eth_proto_cap_get(payload);4904	if (p_eth_proto_admin)4905		*p_eth_proto_admin =4906			mlxsw_reg_ptys_eth_proto_admin_get(payload);4907	if (p_eth_proto_oper)4908		*p_eth_proto_oper =4909			mlxsw_reg_ptys_eth_proto_oper_get(payload);4910}4911 4912static inline void mlxsw_reg_ptys_ext_eth_unpack(char *payload,4913						 u32 *p_eth_proto_cap,4914						 u32 *p_eth_proto_admin,4915						 u32 *p_eth_proto_oper)4916{4917	if (p_eth_proto_cap)4918		*p_eth_proto_cap =4919			mlxsw_reg_ptys_ext_eth_proto_cap_get(payload);4920	if (p_eth_proto_admin)4921		*p_eth_proto_admin =4922			mlxsw_reg_ptys_ext_eth_proto_admin_get(payload);4923	if (p_eth_proto_oper)4924		*p_eth_proto_oper =4925			mlxsw_reg_ptys_ext_eth_proto_oper_get(payload);4926}4927 4928/* PPAD - Port Physical Address Register4929 * -------------------------------------4930 * The PPAD register configures the per port physical MAC address.4931 */4932#define MLXSW_REG_PPAD_ID 0x50054933#define MLXSW_REG_PPAD_LEN 0x104934 4935MLXSW_REG_DEFINE(ppad, MLXSW_REG_PPAD_ID, MLXSW_REG_PPAD_LEN);4936 4937/* reg_ppad_single_base_mac4938 * 0: base_mac, local port should be 0 and mac[7:0] is4939 * reserved. HW will set incremental4940 * 1: single_mac - mac of the local_port4941 * Access: RW4942 */4943MLXSW_ITEM32(reg, ppad, single_base_mac, 0x00, 28, 1);4944 4945/* reg_ppad_local_port4946 * port number, if single_base_mac = 0 then local_port is reserved4947 * Access: RW4948 */4949MLXSW_ITEM32_LP(reg, ppad, 0x00, 16, 0x00, 24);4950 4951/* reg_ppad_mac4952 * If single_base_mac = 0 - base MAC address, mac[7:0] is reserved.4953 * If single_base_mac = 1 - the per port MAC address4954 * Access: RW4955 */4956MLXSW_ITEM_BUF(reg, ppad, mac, 0x02, 6);4957 4958static inline void mlxsw_reg_ppad_pack(char *payload, bool single_base_mac,4959				       u16 local_port)4960{4961	MLXSW_REG_ZERO(ppad, payload);4962	mlxsw_reg_ppad_single_base_mac_set(payload, !!single_base_mac);4963	mlxsw_reg_ppad_local_port_set(payload, local_port);4964}4965 4966/* PAOS - Ports Administrative and Operational Status Register4967 * -----------------------------------------------------------4968 * Configures and retrieves per port administrative and operational status.4969 */4970#define MLXSW_REG_PAOS_ID 0x50064971#define MLXSW_REG_PAOS_LEN 0x104972 4973MLXSW_REG_DEFINE(paos, MLXSW_REG_PAOS_ID, MLXSW_REG_PAOS_LEN);4974 4975/* reg_paos_swid4976 * Switch partition ID with which to associate the port.4977 * Note: while external ports uses unique local port numbers (and thus swid is4978 * redundant), router ports use the same local port number where swid is the4979 * only indication for the relevant port.4980 * Access: Index4981 */4982MLXSW_ITEM32(reg, paos, swid, 0x00, 24, 8);4983 4984/* reg_paos_local_port4985 * Local port number.4986 * Access: Index4987 */4988MLXSW_ITEM32_LP(reg, paos, 0x00, 16, 0x00, 12);4989 4990/* reg_paos_admin_status4991 * Port administrative state (the desired state of the port):4992 * 1 - Up.4993 * 2 - Down.4994 * 3 - Up once. This means that in case of link failure, the port won't go4995 *     into polling mode, but will wait to be re-enabled by software.4996 * 4 - Disabled by system. Can only be set by hardware.4997 * Access: RW4998 */4999MLXSW_ITEM32(reg, paos, admin_status, 0x00, 8, 4);5000 5001/* reg_paos_oper_status5002 * Port operational state (the current state):5003 * 1 - Up.5004 * 2 - Down.5005 * 3 - Down by port failure. This means that the device will not let the5006 *     port up again until explicitly specified by software.5007 * Access: RO5008 */5009MLXSW_ITEM32(reg, paos, oper_status, 0x00, 0, 4);5010 5011/* reg_paos_ase5012 * Admin state update enabled.5013 * Access: WO5014 */5015MLXSW_ITEM32(reg, paos, ase, 0x04, 31, 1);5016 5017/* reg_paos_ee5018 * Event update enable. If this bit is set, event generation will be5019 * updated based on the e field.5020 * Access: WO5021 */5022MLXSW_ITEM32(reg, paos, ee, 0x04, 30, 1);5023 5024/* reg_paos_e5025 * Event generation on operational state change:5026 * 0 - Do not generate event.5027 * 1 - Generate Event.5028 * 2 - Generate Single Event.5029 * Access: RW5030 */5031MLXSW_ITEM32(reg, paos, e, 0x04, 0, 2);5032 5033static inline void mlxsw_reg_paos_pack(char *payload, u16 local_port,5034				       enum mlxsw_port_admin_status status)5035{5036	MLXSW_REG_ZERO(paos, payload);5037	mlxsw_reg_paos_swid_set(payload, 0);5038	mlxsw_reg_paos_local_port_set(payload, local_port);5039	mlxsw_reg_paos_admin_status_set(payload, status);5040	mlxsw_reg_paos_oper_status_set(payload, 0);5041	mlxsw_reg_paos_ase_set(payload, 1);5042	mlxsw_reg_paos_ee_set(payload, 1);5043	mlxsw_reg_paos_e_set(payload, 1);5044}5045 5046/* PFCC - Ports Flow Control Configuration Register5047 * ------------------------------------------------5048 * Configures and retrieves the per port flow control configuration.5049 */5050#define MLXSW_REG_PFCC_ID 0x50075051#define MLXSW_REG_PFCC_LEN 0x205052 5053MLXSW_REG_DEFINE(pfcc, MLXSW_REG_PFCC_ID, MLXSW_REG_PFCC_LEN);5054 5055/* reg_pfcc_local_port5056 * Local port number.5057 * Access: Index5058 */5059MLXSW_ITEM32_LP(reg, pfcc, 0x00, 16, 0x00, 12);5060 5061/* reg_pfcc_pnat5062 * Port number access type. Determines the way local_port is interpreted:5063 * 0 - Local port number.5064 * 1 - IB / label port number.5065 * Access: Index5066 */5067MLXSW_ITEM32(reg, pfcc, pnat, 0x00, 14, 2);5068 5069/* reg_pfcc_shl_cap5070 * Send to higher layers capabilities:5071 * 0 - No capability of sending Pause and PFC frames to higher layers.5072 * 1 - Device has capability of sending Pause and PFC frames to higher5073 *     layers.5074 * Access: RO5075 */5076MLXSW_ITEM32(reg, pfcc, shl_cap, 0x00, 1, 1);5077 5078/* reg_pfcc_shl_opr5079 * Send to higher layers operation:5080 * 0 - Pause and PFC frames are handled by the port (default).5081 * 1 - Pause and PFC frames are handled by the port and also sent to5082 *     higher layers. Only valid if shl_cap = 1.5083 * Access: RW5084 */5085MLXSW_ITEM32(reg, pfcc, shl_opr, 0x00, 0, 1);5086 5087/* reg_pfcc_ppan5088 * Pause policy auto negotiation.5089 * 0 - Disabled. Generate / ignore Pause frames based on pptx / pprtx.5090 * 1 - Enabled. When auto-negotiation is performed, set the Pause policy5091 *     based on the auto-negotiation resolution.5092 * Access: RW5093 *5094 * Note: The auto-negotiation advertisement is set according to pptx and5095 * pprtx. When PFC is set on Tx / Rx, ppan must be set to 0.5096 */5097MLXSW_ITEM32(reg, pfcc, ppan, 0x04, 28, 4);5098 5099/* reg_pfcc_prio_mask_tx5100 * Bit per priority indicating if Tx flow control policy should be5101 * updated based on bit pfctx.5102 * Access: WO5103 */5104MLXSW_ITEM32(reg, pfcc, prio_mask_tx, 0x04, 16, 8);5105 5106/* reg_pfcc_prio_mask_rx5107 * Bit per priority indicating if Rx flow control policy should be5108 * updated based on bit pfcrx.5109 * Access: WO5110 */5111MLXSW_ITEM32(reg, pfcc, prio_mask_rx, 0x04, 0, 8);5112 5113/* reg_pfcc_pptx5114 * Admin Pause policy on Tx.5115 * 0 - Never generate Pause frames (default).5116 * 1 - Generate Pause frames according to Rx buffer threshold.5117 * Access: RW5118 */5119MLXSW_ITEM32(reg, pfcc, pptx, 0x08, 31, 1);5120 5121/* reg_pfcc_aptx5122 * Active (operational) Pause policy on Tx.5123 * 0 - Never generate Pause frames.5124 * 1 - Generate Pause frames according to Rx buffer threshold.5125 * Access: RO5126 */5127MLXSW_ITEM32(reg, pfcc, aptx, 0x08, 30, 1);5128 5129/* reg_pfcc_pfctx5130 * Priority based flow control policy on Tx[7:0]. Per-priority bit mask:5131 * 0 - Never generate priority Pause frames on the specified priority5132 *     (default).5133 * 1 - Generate priority Pause frames according to Rx buffer threshold on5134 *     the specified priority.5135 * Access: RW5136 *5137 * Note: pfctx and pptx must be mutually exclusive.5138 */5139MLXSW_ITEM32(reg, pfcc, pfctx, 0x08, 16, 8);5140 5141/* reg_pfcc_pprx5142 * Admin Pause policy on Rx.5143 * 0 - Ignore received Pause frames (default).5144 * 1 - Respect received Pause frames.5145 * Access: RW5146 */5147MLXSW_ITEM32(reg, pfcc, pprx, 0x0C, 31, 1);5148 5149/* reg_pfcc_aprx5150 * Active (operational) Pause policy on Rx.5151 * 0 - Ignore received Pause frames.5152 * 1 - Respect received Pause frames.5153 * Access: RO5154 */5155MLXSW_ITEM32(reg, pfcc, aprx, 0x0C, 30, 1);5156 5157/* reg_pfcc_pfcrx5158 * Priority based flow control policy on Rx[7:0]. Per-priority bit mask:5159 * 0 - Ignore incoming priority Pause frames on the specified priority5160 *     (default).5161 * 1 - Respect incoming priority Pause frames on the specified priority.5162 * Access: RW5163 */5164MLXSW_ITEM32(reg, pfcc, pfcrx, 0x0C, 16, 8);5165 5166#define MLXSW_REG_PFCC_ALL_PRIO 0xFF5167 5168static inline void mlxsw_reg_pfcc_prio_pack(char *payload, u8 pfc_en)5169{5170	mlxsw_reg_pfcc_prio_mask_tx_set(payload, MLXSW_REG_PFCC_ALL_PRIO);5171	mlxsw_reg_pfcc_prio_mask_rx_set(payload, MLXSW_REG_PFCC_ALL_PRIO);5172	mlxsw_reg_pfcc_pfctx_set(payload, pfc_en);5173	mlxsw_reg_pfcc_pfcrx_set(payload, pfc_en);5174}5175 5176static inline void mlxsw_reg_pfcc_pack(char *payload, u16 local_port)5177{5178	MLXSW_REG_ZERO(pfcc, payload);5179	mlxsw_reg_pfcc_local_port_set(payload, local_port);5180}5181 5182/* PPCNT - Ports Performance Counters Register5183 * -------------------------------------------5184 * The PPCNT register retrieves per port performance counters.5185 */5186#define MLXSW_REG_PPCNT_ID 0x50085187#define MLXSW_REG_PPCNT_LEN 0x1005188#define MLXSW_REG_PPCNT_COUNTERS_OFFSET 0x085189 5190MLXSW_REG_DEFINE(ppcnt, MLXSW_REG_PPCNT_ID, MLXSW_REG_PPCNT_LEN);5191 5192/* reg_ppcnt_swid5193 * For HCA: must be always 0.5194 * Switch partition ID to associate port with.5195 * Switch partitions are numbered from 0 to 7 inclusively.5196 * Switch partition 254 indicates stacking ports.5197 * Switch partition 255 indicates all switch partitions.5198 * Only valid on Set() operation with local_port=255.5199 * Access: Index5200 */5201MLXSW_ITEM32(reg, ppcnt, swid, 0x00, 24, 8);5202 5203/* reg_ppcnt_local_port5204 * Local port number.5205 * Access: Index5206 */5207MLXSW_ITEM32_LP(reg, ppcnt, 0x00, 16, 0x00, 12);5208 5209/* reg_ppcnt_pnat5210 * Port number access type:5211 * 0 - Local port number5212 * 1 - IB port number5213 * Access: Index5214 */5215MLXSW_ITEM32(reg, ppcnt, pnat, 0x00, 14, 2);5216 5217enum mlxsw_reg_ppcnt_grp {5218	MLXSW_REG_PPCNT_IEEE_8023_CNT = 0x0,5219	MLXSW_REG_PPCNT_RFC_2863_CNT = 0x1,5220	MLXSW_REG_PPCNT_RFC_2819_CNT = 0x2,5221	MLXSW_REG_PPCNT_RFC_3635_CNT = 0x3,5222	MLXSW_REG_PPCNT_EXT_CNT = 0x5,5223	MLXSW_REG_PPCNT_DISCARD_CNT = 0x6,5224	MLXSW_REG_PPCNT_PRIO_CNT = 0x10,5225	MLXSW_REG_PPCNT_TC_CNT = 0x11,5226	MLXSW_REG_PPCNT_TC_CONG_CNT = 0x13,5227};5228 5229/* reg_ppcnt_grp5230 * Performance counter group.5231 * Group 63 indicates all groups. Only valid on Set() operation with5232 * clr bit set.5233 * 0x0: IEEE 802.3 Counters5234 * 0x1: RFC 2863 Counters5235 * 0x2: RFC 2819 Counters5236 * 0x3: RFC 3635 Counters5237 * 0x5: Ethernet Extended Counters5238 * 0x6: Ethernet Discard Counters5239 * 0x8: Link Level Retransmission Counters5240 * 0x10: Per Priority Counters5241 * 0x11: Per Traffic Class Counters5242 * 0x12: Physical Layer Counters5243 * 0x13: Per Traffic Class Congestion Counters5244 * Access: Index5245 */5246MLXSW_ITEM32(reg, ppcnt, grp, 0x00, 0, 6);5247 5248/* reg_ppcnt_clr5249 * Clear counters. Setting the clr bit will reset the counter value5250 * for all counters in the counter group. This bit can be set5251 * for both Set() and Get() operation.5252 * Access: OP5253 */5254MLXSW_ITEM32(reg, ppcnt, clr, 0x04, 31, 1);5255 5256/* reg_ppcnt_lp_gl5257 * Local port global variable.5258 * 0: local_port 255 = all ports of the device.5259 * 1: local_port indicates local port number for all ports.5260 * Access: OP5261 */5262MLXSW_ITEM32(reg, ppcnt, lp_gl, 0x04, 30, 1);5263 5264/* reg_ppcnt_prio_tc5265 * Priority for counter set that support per priority, valid values: 0-7.5266 * Traffic class for counter set that support per traffic class,5267 * valid values: 0- cap_max_tclass-1 .5268 * For HCA: cap_max_tclass is always 8.5269 * Otherwise must be 0.5270 * Access: Index5271 */5272MLXSW_ITEM32(reg, ppcnt, prio_tc, 0x04, 0, 5);5273 5274/* Ethernet IEEE 802.3 Counter Group */5275 5276/* reg_ppcnt_a_frames_transmitted_ok5277 * Access: RO5278 */5279MLXSW_ITEM64(reg, ppcnt, a_frames_transmitted_ok,5280	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64);5281 5282/* reg_ppcnt_a_frames_received_ok5283 * Access: RO5284 */5285MLXSW_ITEM64(reg, ppcnt, a_frames_received_ok,5286	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64);5287 5288/* reg_ppcnt_a_frame_check_sequence_errors5289 * Access: RO5290 */5291MLXSW_ITEM64(reg, ppcnt, a_frame_check_sequence_errors,5292	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64);5293 5294/* reg_ppcnt_a_alignment_errors5295 * Access: RO5296 */5297MLXSW_ITEM64(reg, ppcnt, a_alignment_errors,5298	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x18, 0, 64);5299 5300/* reg_ppcnt_a_octets_transmitted_ok5301 * Access: RO5302 */5303MLXSW_ITEM64(reg, ppcnt, a_octets_transmitted_ok,5304	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64);5305 5306/* reg_ppcnt_a_octets_received_ok5307 * Access: RO5308 */5309MLXSW_ITEM64(reg, ppcnt, a_octets_received_ok,5310	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64);5311 5312/* reg_ppcnt_a_multicast_frames_xmitted_ok5313 * Access: RO5314 */5315MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_xmitted_ok,5316	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64);5317 5318/* reg_ppcnt_a_broadcast_frames_xmitted_ok5319 * Access: RO5320 */5321MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_xmitted_ok,5322	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64);5323 5324/* reg_ppcnt_a_multicast_frames_received_ok5325 * Access: RO5326 */5327MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_received_ok,5328	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64);5329 5330/* reg_ppcnt_a_broadcast_frames_received_ok5331 * Access: RO5332 */5333MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_received_ok,5334	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x48, 0, 64);5335 5336/* reg_ppcnt_a_in_range_length_errors5337 * Access: RO5338 */5339MLXSW_ITEM64(reg, ppcnt, a_in_range_length_errors,5340	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64);5341 5342/* reg_ppcnt_a_out_of_range_length_field5343 * Access: RO5344 */5345MLXSW_ITEM64(reg, ppcnt, a_out_of_range_length_field,5346	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64);5347 5348/* reg_ppcnt_a_frame_too_long_errors5349 * Access: RO5350 */5351MLXSW_ITEM64(reg, ppcnt, a_frame_too_long_errors,5352	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64);5353 5354/* reg_ppcnt_a_symbol_error_during_carrier5355 * Access: RO5356 */5357MLXSW_ITEM64(reg, ppcnt, a_symbol_error_during_carrier,5358	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64);5359 5360/* reg_ppcnt_a_mac_control_frames_transmitted5361 * Access: RO5362 */5363MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_transmitted,5364	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64);5365 5366/* reg_ppcnt_a_mac_control_frames_received5367 * Access: RO5368 */5369MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_received,5370	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x78, 0, 64);5371 5372/* reg_ppcnt_a_unsupported_opcodes_received5373 * Access: RO5374 */5375MLXSW_ITEM64(reg, ppcnt, a_unsupported_opcodes_received,5376	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x80, 0, 64);5377 5378/* reg_ppcnt_a_pause_mac_ctrl_frames_received5379 * Access: RO5380 */5381MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_received,5382	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x88, 0, 64);5383 5384/* reg_ppcnt_a_pause_mac_ctrl_frames_transmitted5385 * Access: RO5386 */5387MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_transmitted,5388	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x90, 0, 64);5389 5390/* Ethernet RFC 2863 Counter Group */5391 5392/* reg_ppcnt_if_in_discards5393 * Access: RO5394 */5395MLXSW_ITEM64(reg, ppcnt, if_in_discards,5396	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64);5397 5398/* reg_ppcnt_if_out_discards5399 * Access: RO5400 */5401MLXSW_ITEM64(reg, ppcnt, if_out_discards,5402	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64);5403 5404/* reg_ppcnt_if_out_errors5405 * Access: RO5406 */5407MLXSW_ITEM64(reg, ppcnt, if_out_errors,5408	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64);5409 5410/* Ethernet RFC 2819 Counter Group */5411 5412/* reg_ppcnt_ether_stats_undersize_pkts5413 * Access: RO5414 */5415MLXSW_ITEM64(reg, ppcnt, ether_stats_undersize_pkts,5416	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64);5417 5418/* reg_ppcnt_ether_stats_oversize_pkts5419 * Access: RO5420 */5421MLXSW_ITEM64(reg, ppcnt, ether_stats_oversize_pkts,5422	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64);5423 5424/* reg_ppcnt_ether_stats_fragments5425 * Access: RO5426 */5427MLXSW_ITEM64(reg, ppcnt, ether_stats_fragments,5428	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64);5429 5430/* reg_ppcnt_ether_stats_pkts64octets5431 * Access: RO5432 */5433MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts64octets,5434	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64);5435 5436/* reg_ppcnt_ether_stats_pkts65to127octets5437 * Access: RO5438 */5439MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts65to127octets,5440	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64);5441 5442/* reg_ppcnt_ether_stats_pkts128to255octets5443 * Access: RO5444 */5445MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts128to255octets,5446	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64);5447 5448/* reg_ppcnt_ether_stats_pkts256to511octets5449 * Access: RO5450 */5451MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts256to511octets,5452	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64);5453 5454/* reg_ppcnt_ether_stats_pkts512to1023octets5455 * Access: RO5456 */5457MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts512to1023octets,5458	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x78, 0, 64);5459 5460/* reg_ppcnt_ether_stats_pkts1024to1518octets5461 * Access: RO5462 */5463MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts1024to1518octets,5464	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x80, 0, 64);5465 5466/* reg_ppcnt_ether_stats_pkts1519to2047octets5467 * Access: RO5468 */5469MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts1519to2047octets,5470	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x88, 0, 64);5471 5472/* reg_ppcnt_ether_stats_pkts2048to4095octets5473 * Access: RO5474 */5475MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts2048to4095octets,5476	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x90, 0, 64);5477 5478/* reg_ppcnt_ether_stats_pkts4096to8191octets5479 * Access: RO5480 */5481MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts4096to8191octets,5482	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x98, 0, 64);5483 5484/* reg_ppcnt_ether_stats_pkts8192to10239octets5485 * Access: RO5486 */5487MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts8192to10239octets,5488	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0xA0, 0, 64);5489 5490/* Ethernet RFC 3635 Counter Group */5491 5492/* reg_ppcnt_dot3stats_fcs_errors5493 * Access: RO5494 */5495MLXSW_ITEM64(reg, ppcnt, dot3stats_fcs_errors,5496	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64);5497 5498/* reg_ppcnt_dot3stats_symbol_errors5499 * Access: RO5500 */5501MLXSW_ITEM64(reg, ppcnt, dot3stats_symbol_errors,5502	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64);5503 5504/* reg_ppcnt_dot3control_in_unknown_opcodes5505 * Access: RO5506 */5507MLXSW_ITEM64(reg, ppcnt, dot3control_in_unknown_opcodes,5508	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64);5509 5510/* reg_ppcnt_dot3in_pause_frames5511 * Access: RO5512 */5513MLXSW_ITEM64(reg, ppcnt, dot3in_pause_frames,5514	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64);5515 5516/* Ethernet Extended Counter Group Counters */5517 5518/* reg_ppcnt_ecn_marked5519 * Access: RO5520 */5521MLXSW_ITEM64(reg, ppcnt, ecn_marked,5522	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64);5523 5524/* Ethernet Discard Counter Group Counters */5525 5526/* reg_ppcnt_ingress_general5527 * Access: RO5528 */5529MLXSW_ITEM64(reg, ppcnt, ingress_general,5530	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64);5531 5532/* reg_ppcnt_ingress_policy_engine5533 * Access: RO5534 */5535MLXSW_ITEM64(reg, ppcnt, ingress_policy_engine,5536	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64);5537 5538/* reg_ppcnt_ingress_vlan_membership5539 * Access: RO5540 */5541MLXSW_ITEM64(reg, ppcnt, ingress_vlan_membership,5542	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64);5543 5544/* reg_ppcnt_ingress_tag_frame_type5545 * Access: RO5546 */5547MLXSW_ITEM64(reg, ppcnt, ingress_tag_frame_type,5548	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x18, 0, 64);5549 5550/* reg_ppcnt_egress_vlan_membership5551 * Access: RO5552 */5553MLXSW_ITEM64(reg, ppcnt, egress_vlan_membership,5554	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64);5555 5556/* reg_ppcnt_loopback_filter5557 * Access: RO5558 */5559MLXSW_ITEM64(reg, ppcnt, loopback_filter,5560	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64);5561 5562/* reg_ppcnt_egress_general5563 * Access: RO5564 */5565MLXSW_ITEM64(reg, ppcnt, egress_general,5566	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64);5567 5568/* reg_ppcnt_egress_hoq5569 * Access: RO5570 */5571MLXSW_ITEM64(reg, ppcnt, egress_hoq,5572	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64);5573 5574/* reg_ppcnt_egress_policy_engine5575 * Access: RO5576 */5577MLXSW_ITEM64(reg, ppcnt, egress_policy_engine,5578	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64);5579 5580/* reg_ppcnt_ingress_tx_link_down5581 * Access: RO5582 */5583MLXSW_ITEM64(reg, ppcnt, ingress_tx_link_down,5584	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64);5585 5586/* reg_ppcnt_egress_stp_filter5587 * Access: RO5588 */5589MLXSW_ITEM64(reg, ppcnt, egress_stp_filter,5590	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64);5591 5592/* reg_ppcnt_egress_sll5593 * Access: RO5594 */5595MLXSW_ITEM64(reg, ppcnt, egress_sll,5596	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64);5597 5598/* Ethernet Per Priority Group Counters */5599 5600/* reg_ppcnt_rx_octets5601 * Access: RO5602 */5603MLXSW_ITEM64(reg, ppcnt, rx_octets,5604	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64);5605 5606/* reg_ppcnt_rx_frames5607 * Access: RO5608 */5609MLXSW_ITEM64(reg, ppcnt, rx_frames,5610	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64);5611 5612/* reg_ppcnt_tx_octets5613 * Access: RO5614 */5615MLXSW_ITEM64(reg, ppcnt, tx_octets,5616	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64);5617 5618/* reg_ppcnt_tx_frames5619 * Access: RO5620 */5621MLXSW_ITEM64(reg, ppcnt, tx_frames,5622	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x48, 0, 64);5623 5624/* reg_ppcnt_rx_pause5625 * Access: RO5626 */5627MLXSW_ITEM64(reg, ppcnt, rx_pause,5628	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64);5629 5630/* reg_ppcnt_rx_pause_duration5631 * Access: RO5632 */5633MLXSW_ITEM64(reg, ppcnt, rx_pause_duration,5634	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64);5635 5636/* reg_ppcnt_tx_pause5637 * Access: RO5638 */5639MLXSW_ITEM64(reg, ppcnt, tx_pause,5640	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64);5641 5642/* reg_ppcnt_tx_pause_duration5643 * Access: RO5644 */5645MLXSW_ITEM64(reg, ppcnt, tx_pause_duration,5646	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64);5647 5648/* reg_ppcnt_rx_pause_transition5649 * Access: RO5650 */5651MLXSW_ITEM64(reg, ppcnt, tx_pause_transition,5652	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64);5653 5654/* Ethernet Per Traffic Class Counters */5655 5656/* reg_ppcnt_tc_transmit_queue5657 * Contains the transmit queue depth in cells of traffic class5658 * selected by prio_tc and the port selected by local_port.5659 * The field cannot be cleared.5660 * Access: RO5661 */5662MLXSW_ITEM64(reg, ppcnt, tc_transmit_queue,5663	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64);5664 5665/* reg_ppcnt_tc_no_buffer_discard_uc5666 * The number of unicast packets dropped due to lack of shared5667 * buffer resources.5668 * Access: RO5669 */5670MLXSW_ITEM64(reg, ppcnt, tc_no_buffer_discard_uc,5671	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64);5672 5673/* Ethernet Per Traffic Class Congestion Group Counters */5674 5675/* reg_ppcnt_wred_discard5676 * Access: RO5677 */5678MLXSW_ITEM64(reg, ppcnt, wred_discard,5679	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64);5680 5681/* reg_ppcnt_ecn_marked_tc5682 * Access: RO5683 */5684MLXSW_ITEM64(reg, ppcnt, ecn_marked_tc,5685	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64);5686 5687static inline void mlxsw_reg_ppcnt_pack(char *payload, u16 local_port,5688					enum mlxsw_reg_ppcnt_grp grp,5689					u8 prio_tc)5690{5691	MLXSW_REG_ZERO(ppcnt, payload);5692	mlxsw_reg_ppcnt_swid_set(payload, 0);5693	mlxsw_reg_ppcnt_local_port_set(payload, local_port);5694	mlxsw_reg_ppcnt_pnat_set(payload, 0);5695	mlxsw_reg_ppcnt_grp_set(payload, grp);5696	mlxsw_reg_ppcnt_clr_set(payload, 0);5697	mlxsw_reg_ppcnt_lp_gl_set(payload, 1);5698	mlxsw_reg_ppcnt_prio_tc_set(payload, prio_tc);5699}5700 5701/* PPTB - Port Prio To Buffer Register5702 * -----------------------------------5703 * Configures the switch priority to buffer table.5704 */5705#define MLXSW_REG_PPTB_ID 0x500B5706#define MLXSW_REG_PPTB_LEN 0x105707 5708MLXSW_REG_DEFINE(pptb, MLXSW_REG_PPTB_ID, MLXSW_REG_PPTB_LEN);5709 5710enum {5711	MLXSW_REG_PPTB_MM_UM,5712	MLXSW_REG_PPTB_MM_UNICAST,5713	MLXSW_REG_PPTB_MM_MULTICAST,5714};5715 5716/* reg_pptb_mm5717 * Mapping mode.5718 * 0 - Map both unicast and multicast packets to the same buffer.5719 * 1 - Map only unicast packets.5720 * 2 - Map only multicast packets.5721 * Access: Index5722 *5723 * Note: SwitchX-2 only supports the first option.5724 */5725MLXSW_ITEM32(reg, pptb, mm, 0x00, 28, 2);5726 5727/* reg_pptb_local_port5728 * Local port number.5729 * Access: Index5730 */5731MLXSW_ITEM32_LP(reg, pptb, 0x00, 16, 0x00, 12);5732 5733/* reg_pptb_um5734 * Enables the update of the untagged_buf field.5735 * Access: RW5736 */5737MLXSW_ITEM32(reg, pptb, um, 0x00, 8, 1);5738 5739/* reg_pptb_pm5740 * Enables the update of the prio_to_buff field.5741 * Bit <i> is a flag for updating the mapping for switch priority <i>.5742 * Access: RW5743 */5744MLXSW_ITEM32(reg, pptb, pm, 0x00, 0, 8);5745 5746/* reg_pptb_prio_to_buff5747 * Mapping of switch priority <i> to one of the allocated receive port5748 * buffers.5749 * Access: RW5750 */5751MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff, 0x04, 0x04, 4);5752 5753/* reg_pptb_pm_msb5754 * Enables the update of the prio_to_buff field.5755 * Bit <i> is a flag for updating the mapping for switch priority <i+8>.5756 * Access: RW5757 */5758MLXSW_ITEM32(reg, pptb, pm_msb, 0x08, 24, 8);5759 5760/* reg_pptb_untagged_buff5761 * Mapping of untagged frames to one of the allocated receive port buffers.5762 * Access: RW5763 *5764 * Note: In SwitchX-2 this field must be mapped to buffer 8. Reserved for5765 * Spectrum, as it maps untagged packets based on the default switch priority.5766 */5767MLXSW_ITEM32(reg, pptb, untagged_buff, 0x08, 0, 4);5768 5769/* reg_pptb_prio_to_buff_msb5770 * Mapping of switch priority <i+8> to one of the allocated receive port5771 * buffers.5772 * Access: RW5773 */5774MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff_msb, 0x0C, 0x04, 4);5775 5776#define MLXSW_REG_PPTB_ALL_PRIO 0xFF5777 5778static inline void mlxsw_reg_pptb_pack(char *payload, u16 local_port)5779{5780	MLXSW_REG_ZERO(pptb, payload);5781	mlxsw_reg_pptb_mm_set(payload, MLXSW_REG_PPTB_MM_UM);5782	mlxsw_reg_pptb_local_port_set(payload, local_port);5783	mlxsw_reg_pptb_pm_set(payload, MLXSW_REG_PPTB_ALL_PRIO);5784	mlxsw_reg_pptb_pm_msb_set(payload, MLXSW_REG_PPTB_ALL_PRIO);5785}5786 5787static inline void mlxsw_reg_pptb_prio_to_buff_pack(char *payload, u8 prio,5788						    u8 buff)5789{5790	mlxsw_reg_pptb_prio_to_buff_set(payload, prio, buff);5791	mlxsw_reg_pptb_prio_to_buff_msb_set(payload, prio, buff);5792}5793 5794/* PBMC - Port Buffer Management Control Register5795 * ----------------------------------------------5796 * The PBMC register configures and retrieves the port packet buffer5797 * allocation for different Prios, and the Pause threshold management.5798 */5799#define MLXSW_REG_PBMC_ID 0x500C5800#define MLXSW_REG_PBMC_LEN 0x6C5801 5802MLXSW_REG_DEFINE(pbmc, MLXSW_REG_PBMC_ID, MLXSW_REG_PBMC_LEN);5803 5804/* reg_pbmc_local_port5805 * Local port number.5806 * Access: Index5807 */5808MLXSW_ITEM32_LP(reg, pbmc, 0x00, 16, 0x00, 12);5809 5810/* reg_pbmc_xoff_timer_value5811 * When device generates a pause frame, it uses this value as the pause5812 * timer (time for the peer port to pause in quota-512 bit time).5813 * Access: RW5814 */5815MLXSW_ITEM32(reg, pbmc, xoff_timer_value, 0x04, 16, 16);5816 5817/* reg_pbmc_xoff_refresh5818 * The time before a new pause frame should be sent to refresh the pause RW5819 * state. Using the same units as xoff_timer_value above (in quota-512 bit5820 * time).5821 * Access: RW5822 */5823MLXSW_ITEM32(reg, pbmc, xoff_refresh, 0x04, 0, 16);5824 5825#define MLXSW_REG_PBMC_PORT_SHARED_BUF_IDX 115826 5827/* reg_pbmc_buf_lossy5828 * The field indicates if the buffer is lossy.5829 * 0 - Lossless5830 * 1 - Lossy5831 * Access: RW5832 */5833MLXSW_ITEM32_INDEXED(reg, pbmc, buf_lossy, 0x0C, 25, 1, 0x08, 0x00, false);5834 5835/* reg_pbmc_buf_epsb5836 * Eligible for Port Shared buffer.5837 * If epsb is set, packets assigned to buffer are allowed to insert the port5838 * shared buffer.5839 * When buf_lossy is MLXSW_REG_PBMC_LOSSY_LOSSY this field is reserved.5840 * Access: RW5841 */5842MLXSW_ITEM32_INDEXED(reg, pbmc, buf_epsb, 0x0C, 24, 1, 0x08, 0x00, false);5843 5844/* reg_pbmc_buf_size5845 * The part of the packet buffer array is allocated for the specific buffer.5846 * Units are represented in cells.5847 * Access: RW5848 */5849MLXSW_ITEM32_INDEXED(reg, pbmc, buf_size, 0x0C, 0, 16, 0x08, 0x00, false);5850 5851/* reg_pbmc_buf_xoff_threshold5852 * Once the amount of data in the buffer goes above this value, device5853 * starts sending PFC frames for all priorities associated with the5854 * buffer. Units are represented in cells. Reserved in case of lossy5855 * buffer.5856 * Access: RW5857 *5858 * Note: In Spectrum, reserved for buffer[9].5859 */5860MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xoff_threshold, 0x0C, 16, 16,5861		     0x08, 0x04, false);5862 5863/* reg_pbmc_buf_xon_threshold5864 * When the amount of data in the buffer goes below this value, device5865 * stops sending PFC frames for the priorities associated with the5866 * buffer. Units are represented in cells. Reserved in case of lossy5867 * buffer.5868 * Access: RW5869 *5870 * Note: In Spectrum, reserved for buffer[9].5871 */5872MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xon_threshold, 0x0C, 0, 16,5873		     0x08, 0x04, false);5874 5875static inline void mlxsw_reg_pbmc_pack(char *payload, u16 local_port,5876				       u16 xoff_timer_value, u16 xoff_refresh)5877{5878	MLXSW_REG_ZERO(pbmc, payload);5879	mlxsw_reg_pbmc_local_port_set(payload, local_port);5880	mlxsw_reg_pbmc_xoff_timer_value_set(payload, xoff_timer_value);5881	mlxsw_reg_pbmc_xoff_refresh_set(payload, xoff_refresh);5882}5883 5884static inline void mlxsw_reg_pbmc_lossy_buffer_pack(char *payload,5885						    int buf_index,5886						    u16 size)5887{5888	mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 1);5889	mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0);5890	mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size);5891}5892 5893static inline void mlxsw_reg_pbmc_lossless_buffer_pack(char *payload,5894						       int buf_index, u16 size,5895						       u16 threshold)5896{5897	mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 0);5898	mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0);5899	mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size);5900	mlxsw_reg_pbmc_buf_xoff_threshold_set(payload, buf_index, threshold);5901	mlxsw_reg_pbmc_buf_xon_threshold_set(payload, buf_index, threshold);5902}5903 5904/* PSPA - Port Switch Partition Allocation5905 * ---------------------------------------5906 * Controls the association of a port with a switch partition and enables5907 * configuring ports as stacking ports.5908 */5909#define MLXSW_REG_PSPA_ID 0x500D5910#define MLXSW_REG_PSPA_LEN 0x85911 5912MLXSW_REG_DEFINE(pspa, MLXSW_REG_PSPA_ID, MLXSW_REG_PSPA_LEN);5913 5914/* reg_pspa_swid5915 * Switch partition ID.5916 * Access: RW5917 */5918MLXSW_ITEM32(reg, pspa, swid, 0x00, 24, 8);5919 5920/* reg_pspa_local_port5921 * Local port number.5922 * Access: Index5923 */5924MLXSW_ITEM32_LP(reg, pspa, 0x00, 16, 0x00, 0);5925 5926/* reg_pspa_sub_port5927 * Virtual port within the local port. Set to 0 when virtual ports are5928 * disabled on the local port.5929 * Access: Index5930 */5931MLXSW_ITEM32(reg, pspa, sub_port, 0x00, 8, 8);5932 5933static inline void mlxsw_reg_pspa_pack(char *payload, u8 swid, u16 local_port)5934{5935	MLXSW_REG_ZERO(pspa, payload);5936	mlxsw_reg_pspa_swid_set(payload, swid);5937	mlxsw_reg_pspa_local_port_set(payload, local_port);5938	mlxsw_reg_pspa_sub_port_set(payload, 0);5939}5940 5941/* PMAOS - Ports Module Administrative and Operational Status5942 * ----------------------------------------------------------5943 * This register configures and retrieves the per module status.5944 */5945#define MLXSW_REG_PMAOS_ID 0x50125946#define MLXSW_REG_PMAOS_LEN 0x105947 5948MLXSW_REG_DEFINE(pmaos, MLXSW_REG_PMAOS_ID, MLXSW_REG_PMAOS_LEN);5949 5950/* reg_pmaos_rst5951 * Module reset toggle.5952 * Note: Setting reset while module is plugged-in will result in transition to5953 * "initializing" operational state.5954 * Access: OP5955 */5956MLXSW_ITEM32(reg, pmaos, rst, 0x00, 31, 1);5957 5958/* reg_pmaos_slot_index5959 * Slot index.5960 * Access: Index5961 */5962MLXSW_ITEM32(reg, pmaos, slot_index, 0x00, 24, 4);5963 5964/* reg_pmaos_module5965 * Module number.5966 * Access: Index5967 */5968MLXSW_ITEM32(reg, pmaos, module, 0x00, 16, 8);5969 5970enum mlxsw_reg_pmaos_admin_status {5971	MLXSW_REG_PMAOS_ADMIN_STATUS_ENABLED = 1,5972	MLXSW_REG_PMAOS_ADMIN_STATUS_DISABLED = 2,5973	/* If the module is active and then unplugged, or experienced an error5974	 * event, the operational status should go to "disabled" and can only5975	 * be enabled upon explicit enable command.5976	 */5977	MLXSW_REG_PMAOS_ADMIN_STATUS_ENABLED_ONCE = 3,5978};5979 5980/* reg_pmaos_admin_status5981 * Module administrative state (the desired state of the module).5982 * Note: To disable a module, all ports associated with the port must be5983 * administatively down first.5984 * Access: RW5985 */5986MLXSW_ITEM32(reg, pmaos, admin_status, 0x00, 8, 4);5987 5988/* reg_pmaos_ase5989 * Admin state update enable.5990 * If this bit is set, admin state will be updated based on admin_state field.5991 * Only relevant on Set() operations.5992 * Access: WO5993 */5994MLXSW_ITEM32(reg, pmaos, ase, 0x04, 31, 1);5995 5996/* reg_pmaos_ee5997 * Event update enable.5998 * If this bit is set, event generation will be updated based on the e field.5999 * Only relevant on Set operations.6000 * Access: WO6001 */6002MLXSW_ITEM32(reg, pmaos, ee, 0x04, 30, 1);6003 6004enum mlxsw_reg_pmaos_e {6005	MLXSW_REG_PMAOS_E_DO_NOT_GENERATE_EVENT,6006	MLXSW_REG_PMAOS_E_GENERATE_EVENT,6007	MLXSW_REG_PMAOS_E_GENERATE_SINGLE_EVENT,6008};6009 6010/* reg_pmaos_e6011 * Event Generation on operational state change.6012 * Access: RW6013 */6014MLXSW_ITEM32(reg, pmaos, e, 0x04, 0, 2);6015 6016static inline void mlxsw_reg_pmaos_pack(char *payload, u8 slot_index, u8 module)6017{6018	MLXSW_REG_ZERO(pmaos, payload);6019	mlxsw_reg_pmaos_slot_index_set(payload, slot_index);6020	mlxsw_reg_pmaos_module_set(payload, module);6021}6022 6023/* PPLR - Port Physical Loopback Register6024 * --------------------------------------6025 * This register allows configuration of the port's loopback mode.6026 */6027#define MLXSW_REG_PPLR_ID 0x50186028#define MLXSW_REG_PPLR_LEN 0x86029 6030MLXSW_REG_DEFINE(pplr, MLXSW_REG_PPLR_ID, MLXSW_REG_PPLR_LEN);6031 6032/* reg_pplr_local_port6033 * Local port number.6034 * Access: Index6035 */6036MLXSW_ITEM32_LP(reg, pplr, 0x00, 16, 0x00, 12);6037 6038/* Phy local loopback. When set the port's egress traffic is looped back6039 * to the receiver and the port transmitter is disabled.6040 */6041#define MLXSW_REG_PPLR_LB_TYPE_BIT_PHY_LOCAL BIT(1)6042 6043/* reg_pplr_lb_en6044 * Loopback enable.6045 * Access: RW6046 */6047MLXSW_ITEM32(reg, pplr, lb_en, 0x04, 0, 8);6048 6049static inline void mlxsw_reg_pplr_pack(char *payload, u16 local_port,6050				       bool phy_local)6051{6052	MLXSW_REG_ZERO(pplr, payload);6053	mlxsw_reg_pplr_local_port_set(payload, local_port);6054	mlxsw_reg_pplr_lb_en_set(payload,6055				 phy_local ?6056				 MLXSW_REG_PPLR_LB_TYPE_BIT_PHY_LOCAL : 0);6057}6058 6059/* PMTDB - Port Module To local DataBase Register6060 * ----------------------------------------------6061 * The PMTDB register allows to query the possible module<->local port6062 * mapping than can be used in PMLP. It does not represent the actual/current6063 * mapping of the local to module. Actual mapping is only defined by PMLP.6064 */6065#define MLXSW_REG_PMTDB_ID 0x501A6066#define MLXSW_REG_PMTDB_LEN 0x406067 6068MLXSW_REG_DEFINE(pmtdb, MLXSW_REG_PMTDB_ID, MLXSW_REG_PMTDB_LEN);6069 6070/* reg_pmtdb_slot_index6071 * Slot index (0: Main board).6072 * Access: Index6073 */6074MLXSW_ITEM32(reg, pmtdb, slot_index, 0x00, 24, 4);6075 6076/* reg_pmtdb_module6077 * Module number.6078 * Access: Index6079 */6080MLXSW_ITEM32(reg, pmtdb, module, 0x00, 16, 8);6081 6082/* reg_pmtdb_ports_width6083 * Port's width6084 * Access: Index6085 */6086MLXSW_ITEM32(reg, pmtdb, ports_width, 0x00, 12, 4);6087 6088/* reg_pmtdb_num_ports6089 * Number of ports in a single module (split/breakout)6090 * Access: Index6091 */6092MLXSW_ITEM32(reg, pmtdb, num_ports, 0x00, 8, 4);6093 6094enum mlxsw_reg_pmtdb_status {6095	MLXSW_REG_PMTDB_STATUS_SUCCESS,6096};6097 6098/* reg_pmtdb_status6099 * Status6100 * Access: RO6101 */6102MLXSW_ITEM32(reg, pmtdb, status, 0x00, 0, 4);6103 6104/* reg_pmtdb_port_num6105 * The local_port value which can be assigned to the module.6106 * In case of more than one port, port<x> represent the /<x> port of6107 * the module.6108 * Access: RO6109 */6110MLXSW_ITEM16_INDEXED(reg, pmtdb, port_num, 0x04, 0, 10, 0x02, 0x00, false);6111 6112static inline void mlxsw_reg_pmtdb_pack(char *payload, u8 slot_index, u8 module,6113					u8 ports_width, u8 num_ports)6114{6115	MLXSW_REG_ZERO(pmtdb, payload);6116	mlxsw_reg_pmtdb_slot_index_set(payload, slot_index);6117	mlxsw_reg_pmtdb_module_set(payload, module);6118	mlxsw_reg_pmtdb_ports_width_set(payload, ports_width);6119	mlxsw_reg_pmtdb_num_ports_set(payload, num_ports);6120}6121 6122/* PMECR - Ports Mapping Event Configuration Register6123 * --------------------------------------------------6124 * The PMECR register is used to enable/disable event triggering6125 * in case of local port mapping change.6126 */6127#define MLXSW_REG_PMECR_ID 0x501B6128#define MLXSW_REG_PMECR_LEN 0x206129 6130MLXSW_REG_DEFINE(pmecr, MLXSW_REG_PMECR_ID, MLXSW_REG_PMECR_LEN);6131 6132/* reg_pmecr_local_port6133 * Local port number.6134 * Access: Index6135 */6136MLXSW_ITEM32_LP(reg, pmecr, 0x00, 16, 0x00, 12);6137 6138/* reg_pmecr_ee6139 * Event update enable. If this bit is set, event generation will be updated6140 * based on the e field. Only relevant on Set operations.6141 * Access: WO6142 */6143MLXSW_ITEM32(reg, pmecr, ee, 0x04, 30, 1);6144 6145/* reg_pmecr_eswi6146 * Software ignore enable bit. If this bit is set, the value of swi is used.6147 * If this bit is clear, the value of swi is ignored.6148 * Only relevant on Set operations.6149 * Access: WO6150 */6151MLXSW_ITEM32(reg, pmecr, eswi, 0x04, 24, 1);6152 6153/* reg_pmecr_swi6154 * Software ignore. If this bit is set, the device shouldn't generate events6155 * in case of PMLP SET operation but only upon self local port mapping change6156 * (if applicable according to e configuration). This is supplementary6157 * configuration on top of e value.6158 * Access: RW6159 */6160MLXSW_ITEM32(reg, pmecr, swi, 0x04, 8, 1);6161 6162enum mlxsw_reg_pmecr_e {6163	MLXSW_REG_PMECR_E_DO_NOT_GENERATE_EVENT,6164	MLXSW_REG_PMECR_E_GENERATE_EVENT,6165	MLXSW_REG_PMECR_E_GENERATE_SINGLE_EVENT,6166};6167 6168/* reg_pmecr_e6169 * Event generation on local port mapping change.6170 * Access: RW6171 */6172MLXSW_ITEM32(reg, pmecr, e, 0x04, 0, 2);6173 6174static inline void mlxsw_reg_pmecr_pack(char *payload, u16 local_port,6175					enum mlxsw_reg_pmecr_e e)6176{6177	MLXSW_REG_ZERO(pmecr, payload);6178	mlxsw_reg_pmecr_local_port_set(payload, local_port);6179	mlxsw_reg_pmecr_e_set(payload, e);6180	mlxsw_reg_pmecr_ee_set(payload, true);6181	mlxsw_reg_pmecr_swi_set(payload, true);6182	mlxsw_reg_pmecr_eswi_set(payload, true);6183}6184 6185/* PMPE - Port Module Plug/Unplug Event Register6186 * ---------------------------------------------6187 * This register reports any operational status change of a module.6188 * A change in the module’s state will generate an event only if the change6189 * happens after arming the event mechanism. Any changes to the module state6190 * while the event mechanism is not armed will not be reported. Software can6191 * query the PMPE register for module status.6192 */6193#define MLXSW_REG_PMPE_ID 0x50246194#define MLXSW_REG_PMPE_LEN 0x106195 6196MLXSW_REG_DEFINE(pmpe, MLXSW_REG_PMPE_ID, MLXSW_REG_PMPE_LEN);6197 6198/* reg_pmpe_slot_index6199 * Slot index.6200 * Access: Index6201 */6202MLXSW_ITEM32(reg, pmpe, slot_index, 0x00, 24, 4);6203 6204/* reg_pmpe_module6205 * Module number.6206 * Access: Index6207 */6208MLXSW_ITEM32(reg, pmpe, module, 0x00, 16, 8);6209 6210enum mlxsw_reg_pmpe_module_status {6211	MLXSW_REG_PMPE_MODULE_STATUS_PLUGGED_ENABLED = 1,6212	MLXSW_REG_PMPE_MODULE_STATUS_UNPLUGGED,6213	MLXSW_REG_PMPE_MODULE_STATUS_PLUGGED_ERROR,6214	MLXSW_REG_PMPE_MODULE_STATUS_PLUGGED_DISABLED,6215};6216 6217/* reg_pmpe_module_status6218 * Module status.6219 * Access: RO6220 */6221MLXSW_ITEM32(reg, pmpe, module_status, 0x00, 0, 4);6222 6223/* reg_pmpe_error_type6224 * Module error details.6225 * Access: RO6226 */6227MLXSW_ITEM32(reg, pmpe, error_type, 0x04, 8, 4);6228 6229/* PDDR - Port Diagnostics Database Register6230 * -----------------------------------------6231 * The PDDR enables to read the Phy debug database6232 */6233#define MLXSW_REG_PDDR_ID 0x50316234#define MLXSW_REG_PDDR_LEN 0x1006235 6236MLXSW_REG_DEFINE(pddr, MLXSW_REG_PDDR_ID, MLXSW_REG_PDDR_LEN);6237 6238/* reg_pddr_local_port6239 * Local port number.6240 * Access: Index6241 */6242MLXSW_ITEM32_LP(reg, pddr, 0x00, 16, 0x00, 12);6243 6244enum mlxsw_reg_pddr_page_select {6245	MLXSW_REG_PDDR_PAGE_SELECT_TROUBLESHOOTING_INFO = 1,6246};6247 6248/* reg_pddr_page_select6249 * Page select index.6250 * Access: Index6251 */6252MLXSW_ITEM32(reg, pddr, page_select, 0x04, 0, 8);6253 6254enum mlxsw_reg_pddr_trblsh_group_opcode {6255	/* Monitor opcodes */6256	MLXSW_REG_PDDR_TRBLSH_GROUP_OPCODE_MONITOR,6257};6258 6259/* reg_pddr_group_opcode6260 * Group selector.6261 * Access: Index6262 */6263MLXSW_ITEM32(reg, pddr, trblsh_group_opcode, 0x08, 0, 16);6264 6265/* reg_pddr_status_opcode6266 * Group selector.6267 * Access: RO6268 */6269MLXSW_ITEM32(reg, pddr, trblsh_status_opcode, 0x0C, 0, 16);6270 6271static inline void mlxsw_reg_pddr_pack(char *payload, u16 local_port,6272				       u8 page_select)6273{6274	MLXSW_REG_ZERO(pddr, payload);6275	mlxsw_reg_pddr_local_port_set(payload, local_port);6276	mlxsw_reg_pddr_page_select_set(payload, page_select);6277}6278 6279/* PMMP - Port Module Memory Map Properties Register6280 * -------------------------------------------------6281 * The PMMP register allows to override the module memory map advertisement.6282 * The register can only be set when the module is disabled by PMAOS register.6283 */6284#define MLXSW_REG_PMMP_ID 0x50446285#define MLXSW_REG_PMMP_LEN 0x2C6286 6287MLXSW_REG_DEFINE(pmmp, MLXSW_REG_PMMP_ID, MLXSW_REG_PMMP_LEN);6288 6289/* reg_pmmp_module6290 * Module number.6291 * Access: Index6292 */6293MLXSW_ITEM32(reg, pmmp, module, 0x00, 16, 8);6294 6295/* reg_pmmp_slot_index6296 * Slot index.6297 * Access: Index6298 */6299MLXSW_ITEM32(reg, pmmp, slot_index, 0x00, 24, 4);6300 6301/* reg_pmmp_sticky6302 * When set, will keep eeprom_override values after plug-out event.6303 * Access: OP6304 */6305MLXSW_ITEM32(reg, pmmp, sticky, 0x00, 0, 1);6306 6307/* reg_pmmp_eeprom_override_mask6308 * Write mask bit (negative polarity).6309 * 0 - Allow write6310 * 1 - Ignore write6311 * On write, indicates which of the bits from eeprom_override field are6312 * updated.6313 * Access: WO6314 */6315MLXSW_ITEM32(reg, pmmp, eeprom_override_mask, 0x04, 16, 16);6316 6317enum {6318	/* Set module to low power mode */6319	MLXSW_REG_PMMP_EEPROM_OVERRIDE_LOW_POWER_MASK = BIT(8),6320};6321 6322/* reg_pmmp_eeprom_override6323 * Override / ignore EEPROM advertisement properties bitmask6324 * Access: RW6325 */6326MLXSW_ITEM32(reg, pmmp, eeprom_override, 0x04, 0, 16);6327 6328static inline void mlxsw_reg_pmmp_pack(char *payload, u8 slot_index, u8 module)6329{6330	MLXSW_REG_ZERO(pmmp, payload);6331	mlxsw_reg_pmmp_slot_index_set(payload, slot_index);6332	mlxsw_reg_pmmp_module_set(payload, module);6333}6334 6335/* PLLP - Port Local port to Label Port mapping Register6336 * -----------------------------------------------------6337 * The PLLP register returns the mapping from Local Port into Label Port.6338 */6339#define MLXSW_REG_PLLP_ID 0x504A6340#define MLXSW_REG_PLLP_LEN 0x106341 6342MLXSW_REG_DEFINE(pllp, MLXSW_REG_PLLP_ID, MLXSW_REG_PLLP_LEN);6343 6344/* reg_pllp_local_port6345 * Local port number.6346 * Access: Index6347 */6348MLXSW_ITEM32_LP(reg, pllp, 0x00, 16, 0x00, 12);6349 6350/* reg_pllp_label_port6351 * Front panel label of the port.6352 * Access: RO6353 */6354MLXSW_ITEM32(reg, pllp, label_port, 0x00, 0, 8);6355 6356/* reg_pllp_split_num6357 * Label split mapping for local_port.6358 * Access: RO6359 */6360MLXSW_ITEM32(reg, pllp, split_num, 0x04, 0, 4);6361 6362/* reg_pllp_slot_index6363 * Slot index (0: Main board).6364 * Access: RO6365 */6366MLXSW_ITEM32(reg, pllp, slot_index, 0x08, 0, 4);6367 6368static inline void mlxsw_reg_pllp_pack(char *payload, u16 local_port)6369{6370	MLXSW_REG_ZERO(pllp, payload);6371	mlxsw_reg_pllp_local_port_set(payload, local_port);6372}6373 6374static inline void mlxsw_reg_pllp_unpack(char *payload, u8 *label_port,6375					 u8 *split_num, u8 *slot_index)6376{6377	*label_port = mlxsw_reg_pllp_label_port_get(payload);6378	*split_num = mlxsw_reg_pllp_split_num_get(payload);6379	*slot_index = mlxsw_reg_pllp_slot_index_get(payload);6380}6381 6382/* PMTM - Port Module Type Mapping Register6383 * ----------------------------------------6384 * The PMTM register allows query or configuration of module types.6385 * The register can only be set when the module is disabled by PMAOS register6386 */6387#define MLXSW_REG_PMTM_ID 0x50676388#define MLXSW_REG_PMTM_LEN 0x106389 6390MLXSW_REG_DEFINE(pmtm, MLXSW_REG_PMTM_ID, MLXSW_REG_PMTM_LEN);6391 6392/* reg_pmtm_slot_index6393 * Slot index.6394 * Access: Index6395 */6396MLXSW_ITEM32(reg, pmtm, slot_index, 0x00, 24, 4);6397 6398/* reg_pmtm_module6399 * Module number.6400 * Access: Index6401 */6402MLXSW_ITEM32(reg, pmtm, module, 0x00, 16, 8);6403 6404enum mlxsw_reg_pmtm_module_type {6405	MLXSW_REG_PMTM_MODULE_TYPE_BACKPLANE_4_LANES = 0,6406	MLXSW_REG_PMTM_MODULE_TYPE_QSFP = 1,6407	MLXSW_REG_PMTM_MODULE_TYPE_SFP = 2,6408	MLXSW_REG_PMTM_MODULE_TYPE_BACKPLANE_SINGLE_LANE = 4,6409	MLXSW_REG_PMTM_MODULE_TYPE_BACKPLANE_2_LANES = 8,6410	MLXSW_REG_PMTM_MODULE_TYPE_CHIP2CHIP4X = 10,6411	MLXSW_REG_PMTM_MODULE_TYPE_CHIP2CHIP2X = 11,6412	MLXSW_REG_PMTM_MODULE_TYPE_CHIP2CHIP1X = 12,6413	MLXSW_REG_PMTM_MODULE_TYPE_QSFP_DD = 14,6414	MLXSW_REG_PMTM_MODULE_TYPE_OSFP = 15,6415	MLXSW_REG_PMTM_MODULE_TYPE_SFP_DD = 16,6416	MLXSW_REG_PMTM_MODULE_TYPE_DSFP = 17,6417	MLXSW_REG_PMTM_MODULE_TYPE_CHIP2CHIP8X = 18,6418	MLXSW_REG_PMTM_MODULE_TYPE_TWISTED_PAIR = 19,6419};6420 6421/* reg_pmtm_module_type6422 * Module type.6423 * Access: RW6424 */6425MLXSW_ITEM32(reg, pmtm, module_type, 0x04, 0, 5);6426 6427static inline void mlxsw_reg_pmtm_pack(char *payload, u8 slot_index, u8 module)6428{6429	MLXSW_REG_ZERO(pmtm, payload);6430	mlxsw_reg_pmtm_slot_index_set(payload, slot_index);6431	mlxsw_reg_pmtm_module_set(payload, module);6432}6433 6434/* HTGT - Host Trap Group Table6435 * ----------------------------6436 * Configures the properties for forwarding to CPU.6437 */6438#define MLXSW_REG_HTGT_ID 0x70026439#define MLXSW_REG_HTGT_LEN 0x206440 6441MLXSW_REG_DEFINE(htgt, MLXSW_REG_HTGT_ID, MLXSW_REG_HTGT_LEN);6442 6443/* reg_htgt_swid6444 * Switch partition ID.6445 * Access: Index6446 */6447MLXSW_ITEM32(reg, htgt, swid, 0x00, 24, 8);6448 6449#define MLXSW_REG_HTGT_PATH_TYPE_LOCAL 0x0	/* For locally attached CPU */6450 6451/* reg_htgt_type6452 * CPU path type.6453 * Access: RW6454 */6455MLXSW_ITEM32(reg, htgt, type, 0x00, 8, 4);6456 6457enum mlxsw_reg_htgt_trap_group {6458	MLXSW_REG_HTGT_TRAP_GROUP_EMAD,6459	MLXSW_REG_HTGT_TRAP_GROUP_CORE_EVENT,6460	MLXSW_REG_HTGT_TRAP_GROUP_SP_STP,6461	MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP,6462	MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP,6463	MLXSW_REG_HTGT_TRAP_GROUP_SP_MC_SNOOPING,6464	MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP,6465	MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF,6466	MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM,6467	MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST,6468	MLXSW_REG_HTGT_TRAP_GROUP_SP_NEIGH_DISCOVERY,6469	MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP,6470	MLXSW_REG_HTGT_TRAP_GROUP_SP_EXTERNAL_ROUTE,6471	MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME,6472	MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP,6473	MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT,6474	MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6,6475	MLXSW_REG_HTGT_TRAP_GROUP_SP_LBERROR,6476	MLXSW_REG_HTGT_TRAP_GROUP_SP_PTP0,6477	MLXSW_REG_HTGT_TRAP_GROUP_SP_PTP1,6478	MLXSW_REG_HTGT_TRAP_GROUP_SP_VRRP,6479	MLXSW_REG_HTGT_TRAP_GROUP_SP_PKT_SAMPLE,6480	MLXSW_REG_HTGT_TRAP_GROUP_SP_FLOW_LOGGING,6481	MLXSW_REG_HTGT_TRAP_GROUP_SP_FID_MISS,6482	MLXSW_REG_HTGT_TRAP_GROUP_SP_BFD,6483	MLXSW_REG_HTGT_TRAP_GROUP_SP_DUMMY,6484	MLXSW_REG_HTGT_TRAP_GROUP_SP_L2_DISCARDS,6485	MLXSW_REG_HTGT_TRAP_GROUP_SP_L3_DISCARDS,6486	MLXSW_REG_HTGT_TRAP_GROUP_SP_L3_EXCEPTIONS,6487	MLXSW_REG_HTGT_TRAP_GROUP_SP_TUNNEL_DISCARDS,6488	MLXSW_REG_HTGT_TRAP_GROUP_SP_ACL_DISCARDS,6489	MLXSW_REG_HTGT_TRAP_GROUP_SP_BUFFER_DISCARDS,6490	MLXSW_REG_HTGT_TRAP_GROUP_SP_EAPOL,6491 6492	__MLXSW_REG_HTGT_TRAP_GROUP_MAX,6493	MLXSW_REG_HTGT_TRAP_GROUP_MAX = __MLXSW_REG_HTGT_TRAP_GROUP_MAX - 16494};6495 6496/* reg_htgt_trap_group6497 * Trap group number. User defined number specifying which trap groups6498 * should be forwarded to the CPU. The mapping between trap IDs and trap6499 * groups is configured using HPKT register.6500 * Access: Index6501 */6502MLXSW_ITEM32(reg, htgt, trap_group, 0x00, 0, 8);6503 6504enum {6505	MLXSW_REG_HTGT_POLICER_DISABLE,6506	MLXSW_REG_HTGT_POLICER_ENABLE,6507};6508 6509/* reg_htgt_pide6510 * Enable policer ID specified using 'pid' field.6511 * Access: RW6512 */6513MLXSW_ITEM32(reg, htgt, pide, 0x04, 15, 1);6514 6515#define MLXSW_REG_HTGT_INVALID_POLICER 0xff6516 6517/* reg_htgt_pid6518 * Policer ID for the trap group.6519 * Access: RW6520 */6521MLXSW_ITEM32(reg, htgt, pid, 0x04, 0, 8);6522 6523#define MLXSW_REG_HTGT_TRAP_TO_CPU 0x06524 6525/* reg_htgt_mirror_action6526 * Mirror action to use.6527 * 0 - Trap to CPU.6528 * 1 - Trap to CPU and mirror to a mirroring agent.6529 * 2 - Mirror to a mirroring agent and do not trap to CPU.6530 * Access: RW6531 *6532 * Note: Mirroring to a mirroring agent is only supported in Spectrum.6533 */6534MLXSW_ITEM32(reg, htgt, mirror_action, 0x08, 8, 2);6535 6536/* reg_htgt_mirroring_agent6537 * Mirroring agent.6538 * Access: RW6539 */6540MLXSW_ITEM32(reg, htgt, mirroring_agent, 0x08, 0, 3);6541 6542#define MLXSW_REG_HTGT_DEFAULT_PRIORITY 06543 6544/* reg_htgt_priority6545 * Trap group priority.6546 * In case a packet matches multiple classification rules, the packet will6547 * only be trapped once, based on the trap ID associated with the group (via6548 * register HPKT) with the highest priority.6549 * Supported values are 0-7, with 7 represnting the highest priority.6550 * Access: RW6551 *6552 * Note: In SwitchX-2 this field is ignored and the priority value is replaced6553 * by the 'trap_group' field.6554 */6555MLXSW_ITEM32(reg, htgt, priority, 0x0C, 0, 4);6556 6557#define MLXSW_REG_HTGT_DEFAULT_TC 76558 6559/* reg_htgt_local_path_cpu_tclass6560 * CPU ingress traffic class for the trap group.6561 * Access: RW6562 */6563MLXSW_ITEM32(reg, htgt, local_path_cpu_tclass, 0x10, 16, 6);6564 6565enum mlxsw_reg_htgt_local_path_rdq {6566	MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_CTRL = 0x13,6567	MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_RX = 0x14,6568	MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_EMAD = 0x15,6569	MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SIB_EMAD = 0x15,6570};6571/* reg_htgt_local_path_rdq6572 * Receive descriptor queue (RDQ) to use for the trap group.6573 * Access: RW6574 */6575MLXSW_ITEM32(reg, htgt, local_path_rdq, 0x10, 0, 6);6576 6577static inline void mlxsw_reg_htgt_pack(char *payload, u8 group, u8 policer_id,6578				       u8 priority, u8 tc)6579{6580	MLXSW_REG_ZERO(htgt, payload);6581 6582	if (policer_id == MLXSW_REG_HTGT_INVALID_POLICER) {6583		mlxsw_reg_htgt_pide_set(payload,6584					MLXSW_REG_HTGT_POLICER_DISABLE);6585	} else {6586		mlxsw_reg_htgt_pide_set(payload,6587					MLXSW_REG_HTGT_POLICER_ENABLE);6588		mlxsw_reg_htgt_pid_set(payload, policer_id);6589	}6590 6591	mlxsw_reg_htgt_type_set(payload, MLXSW_REG_HTGT_PATH_TYPE_LOCAL);6592	mlxsw_reg_htgt_trap_group_set(payload, group);6593	mlxsw_reg_htgt_mirror_action_set(payload, MLXSW_REG_HTGT_TRAP_TO_CPU);6594	mlxsw_reg_htgt_mirroring_agent_set(payload, 0);6595	mlxsw_reg_htgt_priority_set(payload, priority);6596	mlxsw_reg_htgt_local_path_cpu_tclass_set(payload, tc);6597	mlxsw_reg_htgt_local_path_rdq_set(payload, group);6598}6599 6600/* HPKT - Host Packet Trap6601 * -----------------------6602 * Configures trap IDs inside trap groups.6603 */6604#define MLXSW_REG_HPKT_ID 0x70036605#define MLXSW_REG_HPKT_LEN 0x106606 6607MLXSW_REG_DEFINE(hpkt, MLXSW_REG_HPKT_ID, MLXSW_REG_HPKT_LEN);6608 6609enum {6610	MLXSW_REG_HPKT_ACK_NOT_REQUIRED,6611	MLXSW_REG_HPKT_ACK_REQUIRED,6612};6613 6614/* reg_hpkt_ack6615 * Require acknowledgements from the host for events.6616 * If set, then the device will wait for the event it sent to be acknowledged6617 * by the host. This option is only relevant for event trap IDs.6618 * Access: RW6619 *6620 * Note: Currently not supported by firmware.6621 */6622MLXSW_ITEM32(reg, hpkt, ack, 0x00, 24, 1);6623 6624enum mlxsw_reg_hpkt_action {6625	MLXSW_REG_HPKT_ACTION_FORWARD,6626	MLXSW_REG_HPKT_ACTION_TRAP_TO_CPU,6627	MLXSW_REG_HPKT_ACTION_MIRROR_TO_CPU,6628	MLXSW_REG_HPKT_ACTION_DISCARD,6629	MLXSW_REG_HPKT_ACTION_SOFT_DISCARD,6630	MLXSW_REG_HPKT_ACTION_TRAP_AND_SOFT_DISCARD,6631	MLXSW_REG_HPKT_ACTION_TRAP_EXCEPTION_TO_CPU,6632	MLXSW_REG_HPKT_ACTION_SET_FW_DEFAULT = 15,6633};6634 6635/* reg_hpkt_action6636 * Action to perform on packet when trapped.6637 * 0 - No action. Forward to CPU based on switching rules.6638 * 1 - Trap to CPU (CPU receives sole copy).6639 * 2 - Mirror to CPU (CPU receives a replica of the packet).6640 * 3 - Discard.6641 * 4 - Soft discard (allow other traps to act on the packet).6642 * 5 - Trap and soft discard (allow other traps to overwrite this trap).6643 * 6 - Trap to CPU (CPU receives sole copy) and count it as error.6644 * 15 - Restore the firmware's default action.6645 * Access: RW6646 *6647 * Note: Must be set to 0 (forward) for event trap IDs, as they are already6648 * addressed to the CPU.6649 */6650MLXSW_ITEM32(reg, hpkt, action, 0x00, 20, 3);6651 6652/* reg_hpkt_trap_group6653 * Trap group to associate the trap with.6654 * Access: RW6655 */6656MLXSW_ITEM32(reg, hpkt, trap_group, 0x00, 12, 6);6657 6658/* reg_hpkt_trap_id6659 * Trap ID.6660 * Access: Index6661 *6662 * Note: A trap ID can only be associated with a single trap group. The device6663 * will associate the trap ID with the last trap group configured.6664 */6665MLXSW_ITEM32(reg, hpkt, trap_id, 0x00, 0, 10);6666 6667enum {6668	MLXSW_REG_HPKT_CTRL_PACKET_DEFAULT,6669	MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER,6670	MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER,6671};6672 6673/* reg_hpkt_ctrl6674 * Configure dedicated buffer resources for control packets.6675 * Ignored by SwitchX-2.6676 * 0 - Keep factory defaults.6677 * 1 - Do not use control buffer for this trap ID.6678 * 2 - Use control buffer for this trap ID.6679 * Access: RW6680 */6681MLXSW_ITEM32(reg, hpkt, ctrl, 0x04, 16, 2);6682 6683static inline void mlxsw_reg_hpkt_pack(char *payload, u8 action, u16 trap_id,6684				       enum mlxsw_reg_htgt_trap_group trap_group,6685				       bool is_ctrl)6686{6687	MLXSW_REG_ZERO(hpkt, payload);6688	mlxsw_reg_hpkt_ack_set(payload, MLXSW_REG_HPKT_ACK_NOT_REQUIRED);6689	mlxsw_reg_hpkt_action_set(payload, action);6690	mlxsw_reg_hpkt_trap_group_set(payload, trap_group);6691	mlxsw_reg_hpkt_trap_id_set(payload, trap_id);6692	mlxsw_reg_hpkt_ctrl_set(payload, is_ctrl ?6693				MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER :6694				MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER);6695}6696 6697/* RGCR - Router General Configuration Register6698 * --------------------------------------------6699 * The register is used for setting up the router configuration.6700 */6701#define MLXSW_REG_RGCR_ID 0x80016702#define MLXSW_REG_RGCR_LEN 0x286703 6704MLXSW_REG_DEFINE(rgcr, MLXSW_REG_RGCR_ID, MLXSW_REG_RGCR_LEN);6705 6706/* reg_rgcr_ipv4_en6707 * IPv4 router enable.6708 * Access: RW6709 */6710MLXSW_ITEM32(reg, rgcr, ipv4_en, 0x00, 31, 1);6711 6712/* reg_rgcr_ipv6_en6713 * IPv6 router enable.6714 * Access: RW6715 */6716MLXSW_ITEM32(reg, rgcr, ipv6_en, 0x00, 30, 1);6717 6718/* reg_rgcr_max_router_interfaces6719 * Defines the maximum number of active router interfaces for all virtual6720 * routers.6721 * Access: RW6722 */6723MLXSW_ITEM32(reg, rgcr, max_router_interfaces, 0x10, 0, 16);6724 6725/* reg_rgcr_usp6726 * Update switch priority and packet color.6727 * 0 - Preserve the value of Switch Priority and packet color.6728 * 1 - Recalculate the value of Switch Priority and packet color.6729 * Access: RW6730 *6731 * Note: Not supported by SwitchX and SwitchX-2.6732 */6733MLXSW_ITEM32(reg, rgcr, usp, 0x18, 20, 1);6734 6735/* reg_rgcr_pcp_rw6736 * Indicates how to handle the pcp_rewrite_en value:6737 * 0 - Preserve the value of pcp_rewrite_en.6738 * 2 - Disable PCP rewrite.6739 * 3 - Enable PCP rewrite.6740 * Access: RW6741 *6742 * Note: Not supported by SwitchX and SwitchX-2.6743 */6744MLXSW_ITEM32(reg, rgcr, pcp_rw, 0x18, 16, 2);6745 6746/* reg_rgcr_activity_dis6747 * Activity disable:6748 * 0 - Activity will be set when an entry is hit (default).6749 * 1 - Activity will not be set when an entry is hit.6750 *6751 * Bit 0 - Disable activity bit in Router Algorithmic LPM Unicast Entry6752 * (RALUE).6753 * Bit 1 - Disable activity bit in Router Algorithmic LPM Unicast Host6754 * Entry (RAUHT).6755 * Bits 2:7 are reserved.6756 * Access: RW6757 *6758 * Note: Not supported by SwitchX, SwitchX-2 and Switch-IB.6759 */6760MLXSW_ITEM32(reg, rgcr, activity_dis, 0x20, 0, 8);6761 6762static inline void mlxsw_reg_rgcr_pack(char *payload, bool ipv4_en,6763				       bool ipv6_en)6764{6765	MLXSW_REG_ZERO(rgcr, payload);6766	mlxsw_reg_rgcr_ipv4_en_set(payload, ipv4_en);6767	mlxsw_reg_rgcr_ipv6_en_set(payload, ipv6_en);6768}6769 6770/* RITR - Router Interface Table Register6771 * --------------------------------------6772 * The register is used to configure the router interface table.6773 */6774#define MLXSW_REG_RITR_ID 0x80026775#define MLXSW_REG_RITR_LEN 0x406776 6777MLXSW_REG_DEFINE(ritr, MLXSW_REG_RITR_ID, MLXSW_REG_RITR_LEN);6778 6779/* reg_ritr_enable6780 * Enables routing on the router interface.6781 * Access: RW6782 */6783MLXSW_ITEM32(reg, ritr, enable, 0x00, 31, 1);6784 6785/* reg_ritr_ipv46786 * IPv4 routing enable. Enables routing of IPv4 traffic on the router6787 * interface.6788 * Access: RW6789 */6790MLXSW_ITEM32(reg, ritr, ipv4, 0x00, 29, 1);6791 6792/* reg_ritr_ipv66793 * IPv6 routing enable. Enables routing of IPv6 traffic on the router6794 * interface.6795 * Access: RW6796 */6797MLXSW_ITEM32(reg, ritr, ipv6, 0x00, 28, 1);6798 6799/* reg_ritr_ipv4_mc6800 * IPv4 multicast routing enable.6801 * Access: RW6802 */6803MLXSW_ITEM32(reg, ritr, ipv4_mc, 0x00, 27, 1);6804 6805/* reg_ritr_ipv6_mc6806 * IPv6 multicast routing enable.6807 * Access: RW6808 */6809MLXSW_ITEM32(reg, ritr, ipv6_mc, 0x00, 26, 1);6810 6811enum mlxsw_reg_ritr_if_type {6812	/* VLAN interface. */6813	MLXSW_REG_RITR_VLAN_IF,6814	/* FID interface. */6815	MLXSW_REG_RITR_FID_IF,6816	/* Sub-port interface. */6817	MLXSW_REG_RITR_SP_IF,6818	/* Loopback Interface. */6819	MLXSW_REG_RITR_LOOPBACK_IF,6820};6821 6822/* reg_ritr_type6823 * Router interface type as per enum mlxsw_reg_ritr_if_type.6824 * Access: RW6825 */6826MLXSW_ITEM32(reg, ritr, type, 0x00, 23, 3);6827 6828enum {6829	MLXSW_REG_RITR_RIF_CREATE,6830	MLXSW_REG_RITR_RIF_DEL,6831};6832 6833/* reg_ritr_op6834 * Opcode:6835 * 0 - Create or edit RIF.6836 * 1 - Delete RIF.6837 * Reserved for SwitchX-2. For Spectrum, editing of interface properties6838 * is not supported. An interface must be deleted and re-created in order6839 * to update properties.6840 * Access: WO6841 */6842MLXSW_ITEM32(reg, ritr, op, 0x00, 20, 2);6843 6844/* reg_ritr_rif6845 * Router interface index. A pointer to the Router Interface Table.6846 * Access: Index6847 */6848MLXSW_ITEM32(reg, ritr, rif, 0x00, 0, 16);6849 6850/* reg_ritr_ipv4_fe6851 * IPv4 Forwarding Enable.6852 * Enables routing of IPv4 traffic on the router interface. When disabled,6853 * forwarding is blocked but local traffic (traps and IP2ME) will be enabled.6854 * Not supported in SwitchX-2.6855 * Access: RW6856 */6857MLXSW_ITEM32(reg, ritr, ipv4_fe, 0x04, 29, 1);6858 6859/* reg_ritr_ipv6_fe6860 * IPv6 Forwarding Enable.6861 * Enables routing of IPv6 traffic on the router interface. When disabled,6862 * forwarding is blocked but local traffic (traps and IP2ME) will be enabled.6863 * Not supported in SwitchX-2.6864 * Access: RW6865 */6866MLXSW_ITEM32(reg, ritr, ipv6_fe, 0x04, 28, 1);6867 6868/* reg_ritr_ipv4_mc_fe6869 * IPv4 Multicast Forwarding Enable.6870 * When disabled, forwarding is blocked but local traffic (traps and IP to me)6871 * will be enabled.6872 * Access: RW6873 */6874MLXSW_ITEM32(reg, ritr, ipv4_mc_fe, 0x04, 27, 1);6875 6876/* reg_ritr_ipv6_mc_fe6877 * IPv6 Multicast Forwarding Enable.6878 * When disabled, forwarding is blocked but local traffic (traps and IP to me)6879 * will be enabled.6880 * Access: RW6881 */6882MLXSW_ITEM32(reg, ritr, ipv6_mc_fe, 0x04, 26, 1);6883 6884/* reg_ritr_lb_en6885 * Loop-back filter enable for unicast packets.6886 * If the flag is set then loop-back filter for unicast packets is6887 * implemented on the RIF. Multicast packets are always subject to6888 * loop-back filtering.6889 * Access: RW6890 */6891MLXSW_ITEM32(reg, ritr, lb_en, 0x04, 24, 1);6892 6893/* reg_ritr_virtual_router6894 * Virtual router ID associated with the router interface.6895 * Access: RW6896 */6897MLXSW_ITEM32(reg, ritr, virtual_router, 0x04, 0, 16);6898 6899/* reg_ritr_mtu6900 * Router interface MTU.6901 * Access: RW6902 */6903MLXSW_ITEM32(reg, ritr, mtu, 0x34, 0, 16);6904 6905/* reg_ritr_if_swid6906 * Switch partition ID.6907 * Access: RW6908 */6909MLXSW_ITEM32(reg, ritr, if_swid, 0x08, 24, 8);6910 6911/* reg_ritr_if_mac_profile_id6912 * MAC msb profile ID.6913 * Access: RW6914 */6915MLXSW_ITEM32(reg, ritr, if_mac_profile_id, 0x10, 16, 4);6916 6917/* reg_ritr_if_mac6918 * Router interface MAC address.6919 * In Spectrum, all MAC addresses must have the same 38 MSBits.6920 * Access: RW6921 */6922MLXSW_ITEM_BUF(reg, ritr, if_mac, 0x12, 6);6923 6924/* reg_ritr_if_vrrp_id_ipv66925 * VRRP ID for IPv66926 * Note: Reserved for RIF types other than VLAN, FID and Sub-port.6927 * Access: RW6928 */6929MLXSW_ITEM32(reg, ritr, if_vrrp_id_ipv6, 0x1C, 8, 8);6930 6931/* reg_ritr_if_vrrp_id_ipv46932 * VRRP ID for IPv46933 * Note: Reserved for RIF types other than VLAN, FID and Sub-port.6934 * Access: RW6935 */6936MLXSW_ITEM32(reg, ritr, if_vrrp_id_ipv4, 0x1C, 0, 8);6937 6938/* VLAN Interface */6939 6940/* reg_ritr_vlan_if_vlan_id6941 * VLAN ID.6942 * Access: RW6943 */6944MLXSW_ITEM32(reg, ritr, vlan_if_vlan_id, 0x08, 0, 12);6945 6946/* reg_ritr_vlan_if_efid6947 * Egress FID.6948 * Used to connect the RIF to a bridge.6949 * Access: RW6950 *6951 * Note: Reserved when legacy bridge model is used and on Spectrum-1.6952 */6953MLXSW_ITEM32(reg, ritr, vlan_if_efid, 0x0C, 0, 16);6954 6955/* FID Interface */6956 6957/* reg_ritr_fid_if_fid6958 * Filtering ID. Used to connect a bridge to the router.6959 * When legacy bridge model is used, only FIDs from the vFID range are6960 * supported. When unified bridge model is used, this is the egress FID for6961 * router to bridge.6962 * Access: RW6963 */6964MLXSW_ITEM32(reg, ritr, fid_if_fid, 0x08, 0, 16);6965 6966/* Sub-port Interface */6967 6968/* reg_ritr_sp_if_lag6969 * LAG indication. When this bit is set the system_port field holds the6970 * LAG identifier.6971 * Access: RW6972 */6973MLXSW_ITEM32(reg, ritr, sp_if_lag, 0x08, 24, 1);6974 6975/* reg_ritr_sp_system_port6976 * Port unique indentifier. When lag bit is set, this field holds the6977 * lag_id in bits 0:9.6978 * Access: RW6979 */6980MLXSW_ITEM32(reg, ritr, sp_if_system_port, 0x08, 0, 16);6981 6982/* reg_ritr_sp_if_efid6983 * Egress filtering ID.6984 * Used to connect the eRIF to a bridge if eRIF-ACL has modified the DMAC or6985 * the VID.6986 * Access: RW6987 *6988 * Note: Reserved when legacy bridge model is used.6989 */6990MLXSW_ITEM32(reg, ritr, sp_if_efid, 0x0C, 0, 16);6991 6992/* reg_ritr_sp_if_vid6993 * VLAN ID.6994 * Access: RW6995 */6996MLXSW_ITEM32(reg, ritr, sp_if_vid, 0x18, 0, 12);6997 6998/* Loopback Interface */6999 7000enum mlxsw_reg_ritr_loopback_protocol {7001	/* IPinIP IPv4 underlay Unicast */7002	MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV4,7003	/* IPinIP IPv6 underlay Unicast */7004	MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV6,7005	/* IPinIP generic - used for Spectrum-2 underlay RIF */7006	MLXSW_REG_RITR_LOOPBACK_GENERIC,7007};7008 7009/* reg_ritr_loopback_protocol7010 * Access: RW7011 */7012MLXSW_ITEM32(reg, ritr, loopback_protocol, 0x08, 28, 4);7013 7014enum mlxsw_reg_ritr_loopback_ipip_type {7015	/* Tunnel is IPinIP. */7016	MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_IP,7017	/* Tunnel is GRE, no key. */7018	MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_GRE_IN_IP,7019	/* Tunnel is GRE, with a key. */7020	MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_GRE_KEY_IN_IP,7021};7022 7023/* reg_ritr_loopback_ipip_type7024 * Encapsulation type.7025 * Access: RW7026 */7027MLXSW_ITEM32(reg, ritr, loopback_ipip_type, 0x10, 24, 4);7028 7029enum mlxsw_reg_ritr_loopback_ipip_options {7030	/* The key is defined by gre_key. */7031	MLXSW_REG_RITR_LOOPBACK_IPIP_OPTIONS_GRE_KEY_PRESET,7032};7033 7034/* reg_ritr_loopback_ipip_options7035 * Access: RW7036 */7037MLXSW_ITEM32(reg, ritr, loopback_ipip_options, 0x10, 20, 4);7038 7039/* reg_ritr_loopback_ipip_uvr7040 * Underlay Virtual Router ID.7041 * Range is 0..cap_max_virtual_routers-1.7042 * Reserved for Spectrum-2.7043 * Access: RW7044 */7045MLXSW_ITEM32(reg, ritr, loopback_ipip_uvr, 0x10, 0, 16);7046 7047/* reg_ritr_loopback_ipip_underlay_rif7048 * Underlay ingress router interface.7049 * Reserved for Spectrum.7050 * Access: RW7051 */7052MLXSW_ITEM32(reg, ritr, loopback_ipip_underlay_rif, 0x14, 0, 16);7053 7054/* reg_ritr_loopback_ipip_usip*7055 * Encapsulation Underlay source IP.7056 * Access: RW7057 */7058MLXSW_ITEM_BUF(reg, ritr, loopback_ipip_usip6, 0x18, 16);7059MLXSW_ITEM32(reg, ritr, loopback_ipip_usip4, 0x24, 0, 32);7060 7061/* reg_ritr_loopback_ipip_gre_key7062 * GRE Key.7063 * Reserved when ipip_type is not IP_IN_GRE_KEY_IN_IP.7064 * Access: RW7065 */7066MLXSW_ITEM32(reg, ritr, loopback_ipip_gre_key, 0x28, 0, 32);7067 7068/* Shared between ingress/egress */7069enum mlxsw_reg_ritr_counter_set_type {7070	/* No Count. */7071	MLXSW_REG_RITR_COUNTER_SET_TYPE_NO_COUNT = 0x0,7072	/* Basic. Used for router interfaces, counting the following:7073	 *	- Error and Discard counters.7074	 *	- Unicast, Multicast and Broadcast counters. Sharing the7075	 *	  same set of counters for the different type of traffic7076	 *	  (IPv4, IPv6 and mpls).7077	 */7078	MLXSW_REG_RITR_COUNTER_SET_TYPE_BASIC = 0x9,7079};7080 7081/* reg_ritr_ingress_counter_index7082 * Counter Index for flow counter.7083 * Access: RW7084 */7085MLXSW_ITEM32(reg, ritr, ingress_counter_index, 0x38, 0, 24);7086 7087/* reg_ritr_ingress_counter_set_type7088 * Igress Counter Set Type for router interface counter.7089 * Access: RW7090 */7091MLXSW_ITEM32(reg, ritr, ingress_counter_set_type, 0x38, 24, 8);7092 7093/* reg_ritr_egress_counter_index7094 * Counter Index for flow counter.7095 * Access: RW7096 */7097MLXSW_ITEM32(reg, ritr, egress_counter_index, 0x3C, 0, 24);7098 7099/* reg_ritr_egress_counter_set_type7100 * Egress Counter Set Type for router interface counter.7101 * Access: RW7102 */7103MLXSW_ITEM32(reg, ritr, egress_counter_set_type, 0x3C, 24, 8);7104 7105static inline void mlxsw_reg_ritr_counter_pack(char *payload, u32 index,7106					       bool enable, bool egress)7107{7108	enum mlxsw_reg_ritr_counter_set_type set_type;7109 7110	if (enable)7111		set_type = MLXSW_REG_RITR_COUNTER_SET_TYPE_BASIC;7112	else7113		set_type = MLXSW_REG_RITR_COUNTER_SET_TYPE_NO_COUNT;7114 7115	if (egress) {7116		mlxsw_reg_ritr_egress_counter_set_type_set(payload, set_type);7117		mlxsw_reg_ritr_egress_counter_index_set(payload, index);7118	} else {7119		mlxsw_reg_ritr_ingress_counter_set_type_set(payload, set_type);7120		mlxsw_reg_ritr_ingress_counter_index_set(payload, index);7121	}7122}7123 7124static inline void mlxsw_reg_ritr_rif_pack(char *payload, u16 rif)7125{7126	MLXSW_REG_ZERO(ritr, payload);7127	mlxsw_reg_ritr_rif_set(payload, rif);7128}7129 7130static inline void mlxsw_reg_ritr_sp_if_pack(char *payload, bool lag,7131					     u16 system_port, u16 efid, u16 vid)7132{7133	mlxsw_reg_ritr_sp_if_lag_set(payload, lag);7134	mlxsw_reg_ritr_sp_if_system_port_set(payload, system_port);7135	mlxsw_reg_ritr_sp_if_efid_set(payload, efid);7136	mlxsw_reg_ritr_sp_if_vid_set(payload, vid);7137}7138 7139static inline void mlxsw_reg_ritr_pack(char *payload, bool enable,7140				       enum mlxsw_reg_ritr_if_type type,7141				       u16 rif, u16 vr_id, u16 mtu)7142{7143	bool op = enable ? MLXSW_REG_RITR_RIF_CREATE : MLXSW_REG_RITR_RIF_DEL;7144 7145	MLXSW_REG_ZERO(ritr, payload);7146	mlxsw_reg_ritr_enable_set(payload, enable);7147	mlxsw_reg_ritr_ipv4_set(payload, 1);7148	mlxsw_reg_ritr_ipv6_set(payload, 1);7149	mlxsw_reg_ritr_ipv4_mc_set(payload, 1);7150	mlxsw_reg_ritr_ipv6_mc_set(payload, 1);7151	mlxsw_reg_ritr_type_set(payload, type);7152	mlxsw_reg_ritr_op_set(payload, op);7153	mlxsw_reg_ritr_rif_set(payload, rif);7154	mlxsw_reg_ritr_ipv4_fe_set(payload, 1);7155	mlxsw_reg_ritr_ipv6_fe_set(payload, 1);7156	mlxsw_reg_ritr_ipv4_mc_fe_set(payload, 1);7157	mlxsw_reg_ritr_ipv6_mc_fe_set(payload, 1);7158	mlxsw_reg_ritr_lb_en_set(payload, 1);7159	mlxsw_reg_ritr_virtual_router_set(payload, vr_id);7160	mlxsw_reg_ritr_mtu_set(payload, mtu);7161}7162 7163static inline void mlxsw_reg_ritr_mac_pack(char *payload, const char *mac)7164{7165	mlxsw_reg_ritr_if_mac_memcpy_to(payload, mac);7166}7167 7168static inline void7169mlxsw_reg_ritr_vlan_if_pack(char *payload, bool enable, u16 rif, u16 vr_id,7170			    u16 mtu, const char *mac, u8 mac_profile_id,7171			    u16 vlan_id, u16 efid)7172{7173	enum mlxsw_reg_ritr_if_type type = MLXSW_REG_RITR_VLAN_IF;7174 7175	mlxsw_reg_ritr_pack(payload, enable, type, rif, vr_id, mtu);7176	mlxsw_reg_ritr_if_mac_memcpy_to(payload, mac);7177	mlxsw_reg_ritr_if_mac_profile_id_set(payload, mac_profile_id);7178	mlxsw_reg_ritr_vlan_if_vlan_id_set(payload, vlan_id);7179	mlxsw_reg_ritr_vlan_if_efid_set(payload, efid);7180}7181 7182static inline void7183mlxsw_reg_ritr_loopback_ipip_common_pack(char *payload,7184			    enum mlxsw_reg_ritr_loopback_ipip_type ipip_type,7185			    enum mlxsw_reg_ritr_loopback_ipip_options options,7186			    u16 uvr_id, u16 underlay_rif, u32 gre_key)7187{7188	mlxsw_reg_ritr_loopback_ipip_type_set(payload, ipip_type);7189	mlxsw_reg_ritr_loopback_ipip_options_set(payload, options);7190	mlxsw_reg_ritr_loopback_ipip_uvr_set(payload, uvr_id);7191	mlxsw_reg_ritr_loopback_ipip_underlay_rif_set(payload, underlay_rif);7192	mlxsw_reg_ritr_loopback_ipip_gre_key_set(payload, gre_key);7193}7194 7195static inline void7196mlxsw_reg_ritr_loopback_ipip4_pack(char *payload,7197			    enum mlxsw_reg_ritr_loopback_ipip_type ipip_type,7198			    enum mlxsw_reg_ritr_loopback_ipip_options options,7199			    u16 uvr_id, u16 underlay_rif, u32 usip, u32 gre_key)7200{7201	mlxsw_reg_ritr_loopback_protocol_set(payload,7202				    MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV4);7203	mlxsw_reg_ritr_loopback_ipip_common_pack(payload, ipip_type, options,7204						 uvr_id, underlay_rif, gre_key);7205	mlxsw_reg_ritr_loopback_ipip_usip4_set(payload, usip);7206}7207 7208static inline void7209mlxsw_reg_ritr_loopback_ipip6_pack(char *payload,7210				   enum mlxsw_reg_ritr_loopback_ipip_type ipip_type,7211				   enum mlxsw_reg_ritr_loopback_ipip_options options,7212				   u16 uvr_id, u16 underlay_rif,7213				   const struct in6_addr *usip, u32 gre_key)7214{7215	enum mlxsw_reg_ritr_loopback_protocol protocol =7216		MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV6;7217 7218	mlxsw_reg_ritr_loopback_protocol_set(payload, protocol);7219	mlxsw_reg_ritr_loopback_ipip_common_pack(payload, ipip_type, options,7220						 uvr_id, underlay_rif, gre_key);7221	mlxsw_reg_ritr_loopback_ipip_usip6_memcpy_to(payload,7222						     (const char *)usip);7223}7224 7225/* RTAR - Router TCAM Allocation Register7226 * --------------------------------------7227 * This register is used for allocation of regions in the TCAM table.7228 */7229#define MLXSW_REG_RTAR_ID 0x80047230#define MLXSW_REG_RTAR_LEN 0x207231 7232MLXSW_REG_DEFINE(rtar, MLXSW_REG_RTAR_ID, MLXSW_REG_RTAR_LEN);7233 7234enum mlxsw_reg_rtar_op {7235	MLXSW_REG_RTAR_OP_ALLOCATE,7236	MLXSW_REG_RTAR_OP_RESIZE,7237	MLXSW_REG_RTAR_OP_DEALLOCATE,7238};7239 7240/* reg_rtar_op7241 * Access: WO7242 */7243MLXSW_ITEM32(reg, rtar, op, 0x00, 28, 4);7244 7245enum mlxsw_reg_rtar_key_type {7246	MLXSW_REG_RTAR_KEY_TYPE_IPV4_MULTICAST = 1,7247	MLXSW_REG_RTAR_KEY_TYPE_IPV6_MULTICAST = 37248};7249 7250/* reg_rtar_key_type7251 * TCAM key type for the region.7252 * Access: WO7253 */7254MLXSW_ITEM32(reg, rtar, key_type, 0x00, 0, 8);7255 7256/* reg_rtar_region_size7257 * TCAM region size. When allocating/resizing this is the requested7258 * size, the response is the actual size.7259 * Note: Actual size may be larger than requested.7260 * Reserved for op = Deallocate7261 * Access: WO7262 */7263MLXSW_ITEM32(reg, rtar, region_size, 0x04, 0, 16);7264 7265static inline void mlxsw_reg_rtar_pack(char *payload,7266				       enum mlxsw_reg_rtar_op op,7267				       enum mlxsw_reg_rtar_key_type key_type,7268				       u16 region_size)7269{7270	MLXSW_REG_ZERO(rtar, payload);7271	mlxsw_reg_rtar_op_set(payload, op);7272	mlxsw_reg_rtar_key_type_set(payload, key_type);7273	mlxsw_reg_rtar_region_size_set(payload, region_size);7274}7275 7276/* RATR - Router Adjacency Table Register7277 * --------------------------------------7278 * The RATR register is used to configure the Router Adjacency (next-hop)7279 * Table.7280 */7281#define MLXSW_REG_RATR_ID 0x80087282#define MLXSW_REG_RATR_LEN 0x2C7283 7284MLXSW_REG_DEFINE(ratr, MLXSW_REG_RATR_ID, MLXSW_REG_RATR_LEN);7285 7286enum mlxsw_reg_ratr_op {7287	/* Read */7288	MLXSW_REG_RATR_OP_QUERY_READ = 0,7289	/* Read and clear activity */7290	MLXSW_REG_RATR_OP_QUERY_READ_CLEAR = 2,7291	/* Write Adjacency entry */7292	MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY = 1,7293	/* Write Adjacency entry only if the activity is cleared.7294	 * The write may not succeed if the activity is set. There is not7295	 * direct feedback if the write has succeeded or not, however7296	 * the get will reveal the actual entry (SW can compare the get7297	 * response to the set command).7298	 */7299	MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY_ON_ACTIVITY = 3,7300};7301 7302/* reg_ratr_op7303 * Note that Write operation may also be used for updating7304 * counter_set_type and counter_index. In this case all other7305 * fields must not be updated.7306 * Access: OP7307 */7308MLXSW_ITEM32(reg, ratr, op, 0x00, 28, 4);7309 7310/* reg_ratr_v7311 * Valid bit. Indicates if the adjacency entry is valid.7312 * Note: the device may need some time before reusing an invalidated7313 * entry. During this time the entry can not be reused. It is7314 * recommended to use another entry before reusing an invalidated7315 * entry (e.g. software can put it at the end of the list for7316 * reusing). Trying to access an invalidated entry not yet cleared7317 * by the device results with failure indicating "Try Again" status.7318 * When valid is '0' then egress_router_interface,trap_action,7319 * adjacency_parameters and counters are reserved7320 * Access: RW7321 */7322MLXSW_ITEM32(reg, ratr, v, 0x00, 24, 1);7323 7324/* reg_ratr_a7325 * Activity. Set for new entries. Set if a packet lookup has hit on7326 * the specific entry. To clear the a bit, use "clear activity".7327 * Access: RO7328 */7329MLXSW_ITEM32(reg, ratr, a, 0x00, 16, 1);7330 7331enum mlxsw_reg_ratr_type {7332	/* Ethernet */7333	MLXSW_REG_RATR_TYPE_ETHERNET,7334	/* IPoIB Unicast without GRH.7335	 * Reserved for Spectrum.7336	 */7337	MLXSW_REG_RATR_TYPE_IPOIB_UC,7338	/* IPoIB Unicast with GRH. Supported only in table 0 (Ethernet unicast7339	 * adjacency).7340	 * Reserved for Spectrum.7341	 */7342	MLXSW_REG_RATR_TYPE_IPOIB_UC_W_GRH,7343	/* IPoIB Multicast.7344	 * Reserved for Spectrum.7345	 */7346	MLXSW_REG_RATR_TYPE_IPOIB_MC,7347	/* MPLS.7348	 * Reserved for SwitchX/-2.7349	 */7350	MLXSW_REG_RATR_TYPE_MPLS,7351	/* IPinIP Encap.7352	 * Reserved for SwitchX/-2.7353	 */7354	MLXSW_REG_RATR_TYPE_IPIP,7355};7356 7357/* reg_ratr_type7358 * Adjacency entry type.7359 * Access: RW7360 */7361MLXSW_ITEM32(reg, ratr, type, 0x04, 28, 4);7362 7363/* reg_ratr_adjacency_index_low7364 * Bits 15:0 of index into the adjacency table.7365 * For SwitchX and SwitchX-2, the adjacency table is linear and7366 * used for adjacency entries only.7367 * For Spectrum, the index is to the KVD linear.7368 * Access: Index7369 */7370MLXSW_ITEM32(reg, ratr, adjacency_index_low, 0x04, 0, 16);7371 7372/* reg_ratr_egress_router_interface7373 * Range is 0 .. cap_max_router_interfaces - 17374 * Access: RW7375 */7376MLXSW_ITEM32(reg, ratr, egress_router_interface, 0x08, 0, 16);7377 7378enum mlxsw_reg_ratr_trap_action {7379	MLXSW_REG_RATR_TRAP_ACTION_NOP,7380	MLXSW_REG_RATR_TRAP_ACTION_TRAP,7381	MLXSW_REG_RATR_TRAP_ACTION_MIRROR_TO_CPU,7382	MLXSW_REG_RATR_TRAP_ACTION_MIRROR,7383	MLXSW_REG_RATR_TRAP_ACTION_DISCARD_ERRORS,7384};7385 7386/* reg_ratr_trap_action7387 * see mlxsw_reg_ratr_trap_action7388 * Access: RW7389 */7390MLXSW_ITEM32(reg, ratr, trap_action, 0x0C, 28, 4);7391 7392/* reg_ratr_adjacency_index_high7393 * Bits 23:16 of the adjacency_index.7394 * Access: Index7395 */7396MLXSW_ITEM32(reg, ratr, adjacency_index_high, 0x0C, 16, 8);7397 7398enum mlxsw_reg_ratr_trap_id {7399	MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS0,7400	MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS1,7401};7402 7403/* reg_ratr_trap_id7404 * Trap ID to be reported to CPU.7405 * Trap-ID is RTR_EGRESS0 or RTR_EGRESS1.7406 * For trap_action of NOP, MIRROR and DISCARD_ERROR7407 * Access: RW7408 */7409MLXSW_ITEM32(reg, ratr, trap_id, 0x0C, 0, 8);7410 7411/* reg_ratr_eth_destination_mac7412 * MAC address of the destination next-hop.7413 * Access: RW7414 */7415MLXSW_ITEM_BUF(reg, ratr, eth_destination_mac, 0x12, 6);7416 7417enum mlxsw_reg_ratr_ipip_type {7418	/* IPv4, address set by mlxsw_reg_ratr_ipip_ipv4_udip. */7419	MLXSW_REG_RATR_IPIP_TYPE_IPV4,7420	/* IPv6, address set by mlxsw_reg_ratr_ipip_ipv6_ptr. */7421	MLXSW_REG_RATR_IPIP_TYPE_IPV6,7422};7423 7424/* reg_ratr_ipip_type7425 * Underlay destination ip type.7426 * Note: the type field must match the protocol of the router interface.7427 * Access: RW7428 */7429MLXSW_ITEM32(reg, ratr, ipip_type, 0x10, 16, 4);7430 7431/* reg_ratr_ipip_ipv4_udip7432 * Underlay ipv4 dip.7433 * Reserved when ipip_type is IPv6.7434 * Access: RW7435 */7436MLXSW_ITEM32(reg, ratr, ipip_ipv4_udip, 0x18, 0, 32);7437 7438/* reg_ratr_ipip_ipv6_ptr7439 * Pointer to IPv6 underlay destination ip address.7440 * For Spectrum: Pointer to KVD linear space.7441 * Access: RW7442 */7443MLXSW_ITEM32(reg, ratr, ipip_ipv6_ptr, 0x1C, 0, 24);7444 7445enum mlxsw_reg_flow_counter_set_type {7446	/* No count */7447	MLXSW_REG_FLOW_COUNTER_SET_TYPE_NO_COUNT = 0x00,7448	/* Count packets and bytes */7449	MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES = 0x03,7450	/* Count only packets */7451	MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS = 0x05,7452};7453 7454/* reg_ratr_counter_set_type7455 * Counter set type for flow counters7456 * Access: RW7457 */7458MLXSW_ITEM32(reg, ratr, counter_set_type, 0x28, 24, 8);7459 7460/* reg_ratr_counter_index7461 * Counter index for flow counters7462 * Access: RW7463 */7464MLXSW_ITEM32(reg, ratr, counter_index, 0x28, 0, 24);7465 7466static inline void7467mlxsw_reg_ratr_pack(char *payload,7468		    enum mlxsw_reg_ratr_op op, bool valid,7469		    enum mlxsw_reg_ratr_type type,7470		    u32 adjacency_index, u16 egress_rif)7471{7472	MLXSW_REG_ZERO(ratr, payload);7473	mlxsw_reg_ratr_op_set(payload, op);7474	mlxsw_reg_ratr_v_set(payload, valid);7475	mlxsw_reg_ratr_type_set(payload, type);7476	mlxsw_reg_ratr_adjacency_index_low_set(payload, adjacency_index);7477	mlxsw_reg_ratr_adjacency_index_high_set(payload, adjacency_index >> 16);7478	mlxsw_reg_ratr_egress_router_interface_set(payload, egress_rif);7479}7480 7481static inline void mlxsw_reg_ratr_eth_entry_pack(char *payload,7482						 const char *dest_mac)7483{7484	mlxsw_reg_ratr_eth_destination_mac_memcpy_to(payload, dest_mac);7485}7486 7487static inline void mlxsw_reg_ratr_ipip4_entry_pack(char *payload, u32 ipv4_udip)7488{7489	mlxsw_reg_ratr_ipip_type_set(payload, MLXSW_REG_RATR_IPIP_TYPE_IPV4);7490	mlxsw_reg_ratr_ipip_ipv4_udip_set(payload, ipv4_udip);7491}7492 7493static inline void mlxsw_reg_ratr_ipip6_entry_pack(char *payload, u32 ipv6_ptr)7494{7495	mlxsw_reg_ratr_ipip_type_set(payload, MLXSW_REG_RATR_IPIP_TYPE_IPV6);7496	mlxsw_reg_ratr_ipip_ipv6_ptr_set(payload, ipv6_ptr);7497}7498 7499static inline void mlxsw_reg_ratr_counter_pack(char *payload, u64 counter_index,7500					       bool counter_enable)7501{7502	enum mlxsw_reg_flow_counter_set_type set_type;7503 7504	if (counter_enable)7505		set_type = MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES;7506	else7507		set_type = MLXSW_REG_FLOW_COUNTER_SET_TYPE_NO_COUNT;7508 7509	mlxsw_reg_ratr_counter_index_set(payload, counter_index);7510	mlxsw_reg_ratr_counter_set_type_set(payload, set_type);7511}7512 7513/* RDPM - Router DSCP to Priority Mapping7514 * --------------------------------------7515 * Controls the mapping from DSCP field to switch priority on routed packets7516 */7517#define MLXSW_REG_RDPM_ID 0x80097518#define MLXSW_REG_RDPM_BASE_LEN 0x007519#define MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN 0x017520#define MLXSW_REG_RDPM_DSCP_ENTRY_REC_MAX_COUNT 647521#define MLXSW_REG_RDPM_LEN 0x407522#define MLXSW_REG_RDPM_LAST_ENTRY (MLXSW_REG_RDPM_BASE_LEN + \7523				   MLXSW_REG_RDPM_LEN - \7524				   MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN)7525 7526MLXSW_REG_DEFINE(rdpm, MLXSW_REG_RDPM_ID, MLXSW_REG_RDPM_LEN);7527 7528/* reg_dscp_entry_e7529 * Enable update of the specific entry7530 * Access: Index7531 */7532MLXSW_ITEM8_INDEXED(reg, rdpm, dscp_entry_e, MLXSW_REG_RDPM_LAST_ENTRY, 7, 1,7533		    -MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN, 0x00, false);7534 7535/* reg_dscp_entry_prio7536 * Switch Priority7537 * Access: RW7538 */7539MLXSW_ITEM8_INDEXED(reg, rdpm, dscp_entry_prio, MLXSW_REG_RDPM_LAST_ENTRY, 0, 4,7540		    -MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN, 0x00, false);7541 7542static inline void mlxsw_reg_rdpm_pack(char *payload, unsigned short index,7543				       u8 prio)7544{7545	mlxsw_reg_rdpm_dscp_entry_e_set(payload, index, 1);7546	mlxsw_reg_rdpm_dscp_entry_prio_set(payload, index, prio);7547}7548 7549/* RICNT - Router Interface Counter Register7550 * -----------------------------------------7551 * The RICNT register retrieves per port performance counters7552 */7553#define MLXSW_REG_RICNT_ID 0x800B7554#define MLXSW_REG_RICNT_LEN 0x1007555 7556MLXSW_REG_DEFINE(ricnt, MLXSW_REG_RICNT_ID, MLXSW_REG_RICNT_LEN);7557 7558/* reg_ricnt_counter_index7559 * Counter index7560 * Access: RW7561 */7562MLXSW_ITEM32(reg, ricnt, counter_index, 0x04, 0, 24);7563 7564enum mlxsw_reg_ricnt_counter_set_type {7565	/* No Count. */7566	MLXSW_REG_RICNT_COUNTER_SET_TYPE_NO_COUNT = 0x00,7567	/* Basic. Used for router interfaces, counting the following:7568	 *	- Error and Discard counters.7569	 *	- Unicast, Multicast and Broadcast counters. Sharing the7570	 *	  same set of counters for the different type of traffic7571	 *	  (IPv4, IPv6 and mpls).7572	 */7573	MLXSW_REG_RICNT_COUNTER_SET_TYPE_BASIC = 0x09,7574};7575 7576/* reg_ricnt_counter_set_type7577 * Counter Set Type for router interface counter7578 * Access: RW7579 */7580MLXSW_ITEM32(reg, ricnt, counter_set_type, 0x04, 24, 8);7581 7582enum mlxsw_reg_ricnt_opcode {7583	/* Nop. Supported only for read access*/7584	MLXSW_REG_RICNT_OPCODE_NOP = 0x00,7585	/* Clear. Setting the clr bit will reset the counter value for7586	 * all counters of the specified Router Interface.7587	 */7588	MLXSW_REG_RICNT_OPCODE_CLEAR = 0x08,7589};7590 7591/* reg_ricnt_opcode7592 * Opcode7593 * Access: RW7594 */7595MLXSW_ITEM32(reg, ricnt, op, 0x00, 28, 4);7596 7597/* reg_ricnt_good_unicast_packets7598 * good unicast packets.7599 * Access: RW7600 */7601MLXSW_ITEM64(reg, ricnt, good_unicast_packets, 0x08, 0, 64);7602 7603/* reg_ricnt_good_multicast_packets7604 * good multicast packets.7605 * Access: RW7606 */7607MLXSW_ITEM64(reg, ricnt, good_multicast_packets, 0x10, 0, 64);7608 7609/* reg_ricnt_good_broadcast_packets7610 * good broadcast packets7611 * Access: RW7612 */7613MLXSW_ITEM64(reg, ricnt, good_broadcast_packets, 0x18, 0, 64);7614 7615/* reg_ricnt_good_unicast_bytes7616 * A count of L3 data and padding octets not including L2 headers7617 * for good unicast frames.7618 * Access: RW7619 */7620MLXSW_ITEM64(reg, ricnt, good_unicast_bytes, 0x20, 0, 64);7621 7622/* reg_ricnt_good_multicast_bytes7623 * A count of L3 data and padding octets not including L2 headers7624 * for good multicast frames.7625 * Access: RW7626 */7627MLXSW_ITEM64(reg, ricnt, good_multicast_bytes, 0x28, 0, 64);7628 7629/* reg_ritr_good_broadcast_bytes7630 * A count of L3 data and padding octets not including L2 headers7631 * for good broadcast frames.7632 * Access: RW7633 */7634MLXSW_ITEM64(reg, ricnt, good_broadcast_bytes, 0x30, 0, 64);7635 7636/* reg_ricnt_error_packets7637 * A count of errored frames that do not pass the router checks.7638 * Access: RW7639 */7640MLXSW_ITEM64(reg, ricnt, error_packets, 0x38, 0, 64);7641 7642/* reg_ricnt_discrad_packets7643 * A count of non-errored frames that do not pass the router checks.7644 * Access: RW7645 */7646MLXSW_ITEM64(reg, ricnt, discard_packets, 0x40, 0, 64);7647 7648/* reg_ricnt_error_bytes7649 * A count of L3 data and padding octets not including L2 headers7650 * for errored frames.7651 * Access: RW7652 */7653MLXSW_ITEM64(reg, ricnt, error_bytes, 0x48, 0, 64);7654 7655/* reg_ricnt_discard_bytes7656 * A count of L3 data and padding octets not including L2 headers7657 * for non-errored frames that do not pass the router checks.7658 * Access: RW7659 */7660MLXSW_ITEM64(reg, ricnt, discard_bytes, 0x50, 0, 64);7661 7662static inline void mlxsw_reg_ricnt_pack(char *payload, u32 index,7663					enum mlxsw_reg_ricnt_opcode op)7664{7665	MLXSW_REG_ZERO(ricnt, payload);7666	mlxsw_reg_ricnt_op_set(payload, op);7667	mlxsw_reg_ricnt_counter_index_set(payload, index);7668	mlxsw_reg_ricnt_counter_set_type_set(payload,7669					     MLXSW_REG_RICNT_COUNTER_SET_TYPE_BASIC);7670}7671 7672/* RRCR - Router Rules Copy Register Layout7673 * ----------------------------------------7674 * This register is used for moving and copying route entry rules.7675 */7676#define MLXSW_REG_RRCR_ID 0x800F7677#define MLXSW_REG_RRCR_LEN 0x247678 7679MLXSW_REG_DEFINE(rrcr, MLXSW_REG_RRCR_ID, MLXSW_REG_RRCR_LEN);7680 7681enum mlxsw_reg_rrcr_op {7682	/* Move rules */7683	MLXSW_REG_RRCR_OP_MOVE,7684	/* Copy rules */7685	MLXSW_REG_RRCR_OP_COPY,7686};7687 7688/* reg_rrcr_op7689 * Access: WO7690 */7691MLXSW_ITEM32(reg, rrcr, op, 0x00, 28, 4);7692 7693/* reg_rrcr_offset7694 * Offset within the region from which to copy/move.7695 * Access: Index7696 */7697MLXSW_ITEM32(reg, rrcr, offset, 0x00, 0, 16);7698 7699/* reg_rrcr_size7700 * The number of rules to copy/move.7701 * Access: WO7702 */7703MLXSW_ITEM32(reg, rrcr, size, 0x04, 0, 16);7704 7705/* reg_rrcr_table_id7706 * Identifier of the table on which to perform the operation. Encoding is the7707 * same as in RTAR.key_type7708 * Access: Index7709 */7710MLXSW_ITEM32(reg, rrcr, table_id, 0x10, 0, 4);7711 7712/* reg_rrcr_dest_offset7713 * Offset within the region to which to copy/move7714 * Access: Index7715 */7716MLXSW_ITEM32(reg, rrcr, dest_offset, 0x20, 0, 16);7717 7718static inline void mlxsw_reg_rrcr_pack(char *payload, enum mlxsw_reg_rrcr_op op,7719				       u16 offset, u16 size,7720				       enum mlxsw_reg_rtar_key_type table_id,7721				       u16 dest_offset)7722{7723	MLXSW_REG_ZERO(rrcr, payload);7724	mlxsw_reg_rrcr_op_set(payload, op);7725	mlxsw_reg_rrcr_offset_set(payload, offset);7726	mlxsw_reg_rrcr_size_set(payload, size);7727	mlxsw_reg_rrcr_table_id_set(payload, table_id);7728	mlxsw_reg_rrcr_dest_offset_set(payload, dest_offset);7729}7730 7731/* RALTA - Router Algorithmic LPM Tree Allocation Register7732 * -------------------------------------------------------7733 * RALTA is used to allocate the LPM trees of the SHSPM method.7734 */7735#define MLXSW_REG_RALTA_ID 0x80107736#define MLXSW_REG_RALTA_LEN 0x047737 7738MLXSW_REG_DEFINE(ralta, MLXSW_REG_RALTA_ID, MLXSW_REG_RALTA_LEN);7739 7740/* reg_ralta_op7741 * opcode (valid for Write, must be 0 on Read)7742 * 0 - allocate a tree7743 * 1 - deallocate a tree7744 * Access: OP7745 */7746MLXSW_ITEM32(reg, ralta, op, 0x00, 28, 2);7747 7748enum mlxsw_reg_ralxx_protocol {7749	MLXSW_REG_RALXX_PROTOCOL_IPV4,7750	MLXSW_REG_RALXX_PROTOCOL_IPV6,7751};7752 7753/* reg_ralta_protocol7754 * Protocol.7755 * Deallocation opcode: Reserved.7756 * Access: RW7757 */7758MLXSW_ITEM32(reg, ralta, protocol, 0x00, 24, 4);7759 7760/* reg_ralta_tree_id7761 * An identifier (numbered from 1..cap_shspm_max_trees-1) representing7762 * the tree identifier (managed by software).7763 * Note that tree_id 0 is allocated for a default-route tree.7764 * Access: Index7765 */7766MLXSW_ITEM32(reg, ralta, tree_id, 0x00, 0, 8);7767 7768static inline void mlxsw_reg_ralta_pack(char *payload, bool alloc,7769					enum mlxsw_reg_ralxx_protocol protocol,7770					u8 tree_id)7771{7772	MLXSW_REG_ZERO(ralta, payload);7773	mlxsw_reg_ralta_op_set(payload, !alloc);7774	mlxsw_reg_ralta_protocol_set(payload, protocol);7775	mlxsw_reg_ralta_tree_id_set(payload, tree_id);7776}7777 7778/* RALST - Router Algorithmic LPM Structure Tree Register7779 * ------------------------------------------------------7780 * RALST is used to set and query the structure of an LPM tree.7781 * The structure of the tree must be sorted as a sorted binary tree, while7782 * each node is a bin that is tagged as the length of the prefixes the lookup7783 * will refer to. Therefore, bin X refers to a set of entries with prefixes7784 * of X bits to match with the destination address. The bin 0 indicates7785 * the default action, when there is no match of any prefix.7786 */7787#define MLXSW_REG_RALST_ID 0x80117788#define MLXSW_REG_RALST_LEN 0x1047789 7790MLXSW_REG_DEFINE(ralst, MLXSW_REG_RALST_ID, MLXSW_REG_RALST_LEN);7791 7792/* reg_ralst_root_bin7793 * The bin number of the root bin.7794 * 0<root_bin=<(length of IP address)7795 * For a default-route tree configure 0xff7796 * Access: RW7797 */7798MLXSW_ITEM32(reg, ralst, root_bin, 0x00, 16, 8);7799 7800/* reg_ralst_tree_id7801 * Tree identifier numbered from 1..(cap_shspm_max_trees-1).7802 * Access: Index7803 */7804MLXSW_ITEM32(reg, ralst, tree_id, 0x00, 0, 8);7805 7806#define MLXSW_REG_RALST_BIN_NO_CHILD 0xff7807#define MLXSW_REG_RALST_BIN_OFFSET 0x047808#define MLXSW_REG_RALST_BIN_COUNT 1287809 7810/* reg_ralst_left_child_bin7811 * Holding the children of the bin according to the stored tree's structure.7812 * For trees composed of less than 4 blocks, the bins in excess are reserved.7813 * Note that tree_id 0 is allocated for a default-route tree, bins are 0xff7814 * Access: RW7815 */7816MLXSW_ITEM16_INDEXED(reg, ralst, left_child_bin, 0x04, 8, 8, 0x02, 0x00, false);7817 7818/* reg_ralst_right_child_bin7819 * Holding the children of the bin according to the stored tree's structure.7820 * For trees composed of less than 4 blocks, the bins in excess are reserved.7821 * Note that tree_id 0 is allocated for a default-route tree, bins are 0xff7822 * Access: RW7823 */7824MLXSW_ITEM16_INDEXED(reg, ralst, right_child_bin, 0x04, 0, 8, 0x02, 0x00,7825		     false);7826 7827static inline void mlxsw_reg_ralst_pack(char *payload, u8 root_bin, u8 tree_id)7828{7829	MLXSW_REG_ZERO(ralst, payload);7830 7831	/* Initialize all bins to have no left or right child */7832	memset(payload + MLXSW_REG_RALST_BIN_OFFSET,7833	       MLXSW_REG_RALST_BIN_NO_CHILD, MLXSW_REG_RALST_BIN_COUNT * 2);7834 7835	mlxsw_reg_ralst_root_bin_set(payload, root_bin);7836	mlxsw_reg_ralst_tree_id_set(payload, tree_id);7837}7838 7839static inline void mlxsw_reg_ralst_bin_pack(char *payload, u8 bin_number,7840					    u8 left_child_bin,7841					    u8 right_child_bin)7842{7843	int bin_index = bin_number - 1;7844 7845	mlxsw_reg_ralst_left_child_bin_set(payload, bin_index, left_child_bin);7846	mlxsw_reg_ralst_right_child_bin_set(payload, bin_index,7847					    right_child_bin);7848}7849 7850/* RALTB - Router Algorithmic LPM Tree Binding Register7851 * ----------------------------------------------------7852 * RALTB is used to bind virtual router and protocol to an allocated LPM tree.7853 */7854#define MLXSW_REG_RALTB_ID 0x80127855#define MLXSW_REG_RALTB_LEN 0x047856 7857MLXSW_REG_DEFINE(raltb, MLXSW_REG_RALTB_ID, MLXSW_REG_RALTB_LEN);7858 7859/* reg_raltb_virtual_router7860 * Virtual Router ID7861 * Range is 0..cap_max_virtual_routers-17862 * Access: Index7863 */7864MLXSW_ITEM32(reg, raltb, virtual_router, 0x00, 16, 16);7865 7866/* reg_raltb_protocol7867 * Protocol.7868 * Access: Index7869 */7870MLXSW_ITEM32(reg, raltb, protocol, 0x00, 12, 4);7871 7872/* reg_raltb_tree_id7873 * Tree to be used for the {virtual_router, protocol}7874 * Tree identifier numbered from 1..(cap_shspm_max_trees-1).7875 * By default, all Unicast IPv4 and IPv6 are bound to tree_id 0.7876 * Access: RW7877 */7878MLXSW_ITEM32(reg, raltb, tree_id, 0x00, 0, 8);7879 7880static inline void mlxsw_reg_raltb_pack(char *payload, u16 virtual_router,7881					enum mlxsw_reg_ralxx_protocol protocol,7882					u8 tree_id)7883{7884	MLXSW_REG_ZERO(raltb, payload);7885	mlxsw_reg_raltb_virtual_router_set(payload, virtual_router);7886	mlxsw_reg_raltb_protocol_set(payload, protocol);7887	mlxsw_reg_raltb_tree_id_set(payload, tree_id);7888}7889 7890/* RALUE - Router Algorithmic LPM Unicast Entry Register7891 * -----------------------------------------------------7892 * RALUE is used to configure and query LPM entries that serve7893 * the Unicast protocols.7894 */7895#define MLXSW_REG_RALUE_ID 0x80137896#define MLXSW_REG_RALUE_LEN 0x387897 7898MLXSW_REG_DEFINE(ralue, MLXSW_REG_RALUE_ID, MLXSW_REG_RALUE_LEN);7899 7900/* reg_ralue_protocol7901 * Protocol.7902 * Access: Index7903 */7904MLXSW_ITEM32(reg, ralue, protocol, 0x00, 24, 4);7905 7906enum mlxsw_reg_ralue_op {7907	/* Read operation. If entry doesn't exist, the operation fails. */7908	MLXSW_REG_RALUE_OP_QUERY_READ = 0,7909	/* Clear on read operation. Used to read entry and7910	 * clear Activity bit.7911	 */7912	MLXSW_REG_RALUE_OP_QUERY_CLEAR = 1,7913	/* Write operation. Used to write a new entry to the table. All RW7914	 * fields are written for new entry. Activity bit is set7915	 * for new entries.7916	 */7917	MLXSW_REG_RALUE_OP_WRITE_WRITE = 0,7918	/* Update operation. Used to update an existing route entry and7919	 * only update the RW fields that are detailed in the field7920	 * op_u_mask. If entry doesn't exist, the operation fails.7921	 */7922	MLXSW_REG_RALUE_OP_WRITE_UPDATE = 1,7923	/* Clear activity. The Activity bit (the field a) is cleared7924	 * for the entry.7925	 */7926	MLXSW_REG_RALUE_OP_WRITE_CLEAR = 2,7927	/* Delete operation. Used to delete an existing entry. If entry7928	 * doesn't exist, the operation fails.7929	 */7930	MLXSW_REG_RALUE_OP_WRITE_DELETE = 3,7931};7932 7933/* reg_ralue_op7934 * Operation.7935 * Access: OP7936 */7937MLXSW_ITEM32(reg, ralue, op, 0x00, 20, 3);7938 7939/* reg_ralue_a7940 * Activity. Set for new entries. Set if a packet lookup has hit on the7941 * specific entry, only if the entry is a route. To clear the a bit, use7942 * "clear activity" op.7943 * Enabled by activity_dis in RGCR7944 * Access: RO7945 */7946MLXSW_ITEM32(reg, ralue, a, 0x00, 16, 1);7947 7948/* reg_ralue_virtual_router7949 * Virtual Router ID7950 * Range is 0..cap_max_virtual_routers-17951 * Access: Index7952 */7953MLXSW_ITEM32(reg, ralue, virtual_router, 0x04, 16, 16);7954 7955#define MLXSW_REG_RALUE_OP_U_MASK_ENTRY_TYPE	BIT(0)7956#define MLXSW_REG_RALUE_OP_U_MASK_BMP_LEN	BIT(1)7957#define MLXSW_REG_RALUE_OP_U_MASK_ACTION	BIT(2)7958 7959/* reg_ralue_op_u_mask7960 * opcode update mask.7961 * On read operation, this field is reserved.7962 * This field is valid for update opcode, otherwise - reserved.7963 * This field is a bitmask of the fields that should be updated.7964 * Access: WO7965 */7966MLXSW_ITEM32(reg, ralue, op_u_mask, 0x04, 8, 3);7967 7968/* reg_ralue_prefix_len7969 * Number of bits in the prefix of the LPM route.7970 * Note that for IPv6 prefixes, if prefix_len>64 the entry consumes7971 * two entries in the physical HW table.7972 * Access: Index7973 */7974MLXSW_ITEM32(reg, ralue, prefix_len, 0x08, 0, 8);7975 7976/* reg_ralue_dip*7977 * The prefix of the route or of the marker that the object of the LPM7978 * is compared with. The most significant bits of the dip are the prefix.7979 * The least significant bits must be '0' if the prefix_len is smaller7980 * than 128 for IPv6 or smaller than 32 for IPv4.7981 * IPv4 address uses bits dip[31:0] and bits dip[127:32] are reserved.7982 * Access: Index7983 */7984MLXSW_ITEM32(reg, ralue, dip4, 0x18, 0, 32);7985MLXSW_ITEM_BUF(reg, ralue, dip6, 0x0C, 16);7986 7987enum mlxsw_reg_ralue_entry_type {7988	MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_ENTRY = 1,7989	MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY = 2,7990	MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_AND_ROUTE_ENTRY = 3,7991};7992 7993/* reg_ralue_entry_type7994 * Entry type.7995 * Note - for Marker entries, the action_type and action fields are reserved.7996 * Access: RW7997 */7998MLXSW_ITEM32(reg, ralue, entry_type, 0x1C, 30, 2);7999 8000/* reg_ralue_bmp_len8001 * The best match prefix length in the case that there is no match for8002 * longer prefixes.8003 * If (entry_type != MARKER_ENTRY), bmp_len must be equal to prefix_len8004 * Note for any update operation with entry_type modification this8005 * field must be set.8006 * Access: RW8007 */8008MLXSW_ITEM32(reg, ralue, bmp_len, 0x1C, 16, 8);8009 8010enum mlxsw_reg_ralue_action_type {8011	MLXSW_REG_RALUE_ACTION_TYPE_REMOTE,8012	MLXSW_REG_RALUE_ACTION_TYPE_LOCAL,8013	MLXSW_REG_RALUE_ACTION_TYPE_IP2ME,8014};8015 8016/* reg_ralue_action_type8017 * Action Type8018 * Indicates how the IP address is connected.8019 * It can be connected to a local subnet through local_erif or can be8020 * on a remote subnet connected through a next-hop router,8021 * or transmitted to the CPU.8022 * Reserved when entry_type = MARKER_ENTRY8023 * Access: RW8024 */8025MLXSW_ITEM32(reg, ralue, action_type, 0x1C, 0, 2);8026 8027enum mlxsw_reg_ralue_trap_action {8028	MLXSW_REG_RALUE_TRAP_ACTION_NOP,8029	MLXSW_REG_RALUE_TRAP_ACTION_TRAP,8030	MLXSW_REG_RALUE_TRAP_ACTION_MIRROR_TO_CPU,8031	MLXSW_REG_RALUE_TRAP_ACTION_MIRROR,8032	MLXSW_REG_RALUE_TRAP_ACTION_DISCARD_ERROR,8033};8034 8035/* reg_ralue_trap_action8036 * Trap action.8037 * For IP2ME action, only NOP and MIRROR are possible.8038 * Access: RW8039 */8040MLXSW_ITEM32(reg, ralue, trap_action, 0x20, 28, 4);8041 8042/* reg_ralue_trap_id8043 * Trap ID to be reported to CPU.8044 * Trap ID is RTR_INGRESS0 or RTR_INGRESS1.8045 * For trap_action of NOP, MIRROR and DISCARD_ERROR, trap_id is reserved.8046 * Access: RW8047 */8048MLXSW_ITEM32(reg, ralue, trap_id, 0x20, 0, 9);8049 8050/* reg_ralue_adjacency_index8051 * Points to the first entry of the group-based ECMP.8052 * Only relevant in case of REMOTE action.8053 * Access: RW8054 */8055MLXSW_ITEM32(reg, ralue, adjacency_index, 0x24, 0, 24);8056 8057/* reg_ralue_ecmp_size8058 * Amount of sequential entries starting8059 * from the adjacency_index (the number of ECMPs).8060 * The valid range is 1-64, 512, 1024, 2048 and 4096.8061 * Reserved when trap_action is TRAP or DISCARD_ERROR.8062 * Only relevant in case of REMOTE action.8063 * Access: RW8064 */8065MLXSW_ITEM32(reg, ralue, ecmp_size, 0x28, 0, 13);8066 8067/* reg_ralue_local_erif8068 * Egress Router Interface.8069 * Only relevant in case of LOCAL action.8070 * Access: RW8071 */8072MLXSW_ITEM32(reg, ralue, local_erif, 0x24, 0, 16);8073 8074/* reg_ralue_ip2me_v8075 * Valid bit for the tunnel_ptr field.8076 * If valid = 0 then trap to CPU as IP2ME trap ID.8077 * If valid = 1 and the packet format allows NVE or IPinIP tunnel8078 * decapsulation then tunnel decapsulation is done.8079 * If valid = 1 and packet format does not allow NVE or IPinIP tunnel8080 * decapsulation then trap as IP2ME trap ID.8081 * Only relevant in case of IP2ME action.8082 * Access: RW8083 */8084MLXSW_ITEM32(reg, ralue, ip2me_v, 0x24, 31, 1);8085 8086/* reg_ralue_ip2me_tunnel_ptr8087 * Tunnel Pointer for NVE or IPinIP tunnel decapsulation.8088 * For Spectrum, pointer to KVD Linear.8089 * Only relevant in case of IP2ME action.8090 * Access: RW8091 */8092MLXSW_ITEM32(reg, ralue, ip2me_tunnel_ptr, 0x24, 0, 24);8093 8094static inline void mlxsw_reg_ralue_pack(char *payload,8095					enum mlxsw_reg_ralxx_protocol protocol,8096					enum mlxsw_reg_ralue_op op,8097					u16 virtual_router, u8 prefix_len)8098{8099	MLXSW_REG_ZERO(ralue, payload);8100	mlxsw_reg_ralue_protocol_set(payload, protocol);8101	mlxsw_reg_ralue_op_set(payload, op);8102	mlxsw_reg_ralue_virtual_router_set(payload, virtual_router);8103	mlxsw_reg_ralue_prefix_len_set(payload, prefix_len);8104	mlxsw_reg_ralue_entry_type_set(payload,8105				       MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY);8106	mlxsw_reg_ralue_bmp_len_set(payload, prefix_len);8107}8108 8109static inline void mlxsw_reg_ralue_pack4(char *payload,8110					 enum mlxsw_reg_ralxx_protocol protocol,8111					 enum mlxsw_reg_ralue_op op,8112					 u16 virtual_router, u8 prefix_len,8113					 u32 dip)8114{8115	mlxsw_reg_ralue_pack(payload, protocol, op, virtual_router, prefix_len);8116	mlxsw_reg_ralue_dip4_set(payload, dip);8117}8118 8119static inline void mlxsw_reg_ralue_pack6(char *payload,8120					 enum mlxsw_reg_ralxx_protocol protocol,8121					 enum mlxsw_reg_ralue_op op,8122					 u16 virtual_router, u8 prefix_len,8123					 const void *dip)8124{8125	mlxsw_reg_ralue_pack(payload, protocol, op, virtual_router, prefix_len);8126	mlxsw_reg_ralue_dip6_memcpy_to(payload, dip);8127}8128 8129static inline void8130mlxsw_reg_ralue_act_remote_pack(char *payload,8131				enum mlxsw_reg_ralue_trap_action trap_action,8132				u16 trap_id, u32 adjacency_index, u16 ecmp_size)8133{8134	mlxsw_reg_ralue_action_type_set(payload,8135					MLXSW_REG_RALUE_ACTION_TYPE_REMOTE);8136	mlxsw_reg_ralue_trap_action_set(payload, trap_action);8137	mlxsw_reg_ralue_trap_id_set(payload, trap_id);8138	mlxsw_reg_ralue_adjacency_index_set(payload, adjacency_index);8139	mlxsw_reg_ralue_ecmp_size_set(payload, ecmp_size);8140}8141 8142static inline void8143mlxsw_reg_ralue_act_local_pack(char *payload,8144			       enum mlxsw_reg_ralue_trap_action trap_action,8145			       u16 trap_id, u16 local_erif)8146{8147	mlxsw_reg_ralue_action_type_set(payload,8148					MLXSW_REG_RALUE_ACTION_TYPE_LOCAL);8149	mlxsw_reg_ralue_trap_action_set(payload, trap_action);8150	mlxsw_reg_ralue_trap_id_set(payload, trap_id);8151	mlxsw_reg_ralue_local_erif_set(payload, local_erif);8152}8153 8154static inline void8155mlxsw_reg_ralue_act_ip2me_pack(char *payload)8156{8157	mlxsw_reg_ralue_action_type_set(payload,8158					MLXSW_REG_RALUE_ACTION_TYPE_IP2ME);8159}8160 8161static inline void8162mlxsw_reg_ralue_act_ip2me_tun_pack(char *payload, u32 tunnel_ptr)8163{8164	mlxsw_reg_ralue_action_type_set(payload,8165					MLXSW_REG_RALUE_ACTION_TYPE_IP2ME);8166	mlxsw_reg_ralue_ip2me_v_set(payload, 1);8167	mlxsw_reg_ralue_ip2me_tunnel_ptr_set(payload, tunnel_ptr);8168}8169 8170/* RAUHT - Router Algorithmic LPM Unicast Host Table Register8171 * ----------------------------------------------------------8172 * The RAUHT register is used to configure and query the Unicast Host table in8173 * devices that implement the Algorithmic LPM.8174 */8175#define MLXSW_REG_RAUHT_ID 0x80148176#define MLXSW_REG_RAUHT_LEN 0x748177 8178MLXSW_REG_DEFINE(rauht, MLXSW_REG_RAUHT_ID, MLXSW_REG_RAUHT_LEN);8179 8180enum mlxsw_reg_rauht_type {8181	MLXSW_REG_RAUHT_TYPE_IPV4,8182	MLXSW_REG_RAUHT_TYPE_IPV6,8183};8184 8185/* reg_rauht_type8186 * Access: Index8187 */8188MLXSW_ITEM32(reg, rauht, type, 0x00, 24, 2);8189 8190enum mlxsw_reg_rauht_op {8191	MLXSW_REG_RAUHT_OP_QUERY_READ = 0,8192	/* Read operation */8193	MLXSW_REG_RAUHT_OP_QUERY_CLEAR_ON_READ = 1,8194	/* Clear on read operation. Used to read entry and clear8195	 * activity bit.8196	 */8197	MLXSW_REG_RAUHT_OP_WRITE_ADD = 0,8198	/* Add. Used to write a new entry to the table. All R/W fields are8199	 * relevant for new entry. Activity bit is set for new entries.8200	 */8201	MLXSW_REG_RAUHT_OP_WRITE_UPDATE = 1,8202	/* Update action. Used to update an existing route entry and8203	 * only update the following fields:8204	 * trap_action, trap_id, mac, counter_set_type, counter_index8205	 */8206	MLXSW_REG_RAUHT_OP_WRITE_CLEAR_ACTIVITY = 2,8207	/* Clear activity. A bit is cleared for the entry. */8208	MLXSW_REG_RAUHT_OP_WRITE_DELETE = 3,8209	/* Delete entry */8210	MLXSW_REG_RAUHT_OP_WRITE_DELETE_ALL = 4,8211	/* Delete all host entries on a RIF. In this command, dip8212	 * field is reserved.8213	 */8214};8215 8216/* reg_rauht_op8217 * Access: OP8218 */8219MLXSW_ITEM32(reg, rauht, op, 0x00, 20, 3);8220 8221/* reg_rauht_a8222 * Activity. Set for new entries. Set if a packet lookup has hit on8223 * the specific entry.8224 * To clear the a bit, use "clear activity" op.8225 * Enabled by activity_dis in RGCR8226 * Access: RO8227 */8228MLXSW_ITEM32(reg, rauht, a, 0x00, 16, 1);8229 8230/* reg_rauht_rif8231 * Router Interface8232 * Access: Index8233 */8234MLXSW_ITEM32(reg, rauht, rif, 0x00, 0, 16);8235 8236/* reg_rauht_dip*8237 * Destination address.8238 * Access: Index8239 */8240MLXSW_ITEM32(reg, rauht, dip4, 0x1C, 0x0, 32);8241MLXSW_ITEM_BUF(reg, rauht, dip6, 0x10, 16);8242 8243enum mlxsw_reg_rauht_trap_action {8244	MLXSW_REG_RAUHT_TRAP_ACTION_NOP,8245	MLXSW_REG_RAUHT_TRAP_ACTION_TRAP,8246	MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR_TO_CPU,8247	MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR,8248	MLXSW_REG_RAUHT_TRAP_ACTION_DISCARD_ERRORS,8249};8250 8251/* reg_rauht_trap_action8252 * Access: RW8253 */8254MLXSW_ITEM32(reg, rauht, trap_action, 0x60, 28, 4);8255 8256enum mlxsw_reg_rauht_trap_id {8257	MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS0,8258	MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS1,8259};8260 8261/* reg_rauht_trap_id8262 * Trap ID to be reported to CPU.8263 * Trap-ID is RTR_EGRESS0 or RTR_EGRESS1.8264 * For trap_action of NOP, MIRROR and DISCARD_ERROR,8265 * trap_id is reserved.8266 * Access: RW8267 */8268MLXSW_ITEM32(reg, rauht, trap_id, 0x60, 0, 9);8269 8270/* reg_rauht_counter_set_type8271 * Counter set type for flow counters8272 * Access: RW8273 */8274MLXSW_ITEM32(reg, rauht, counter_set_type, 0x68, 24, 8);8275 8276/* reg_rauht_counter_index8277 * Counter index for flow counters8278 * Access: RW8279 */8280MLXSW_ITEM32(reg, rauht, counter_index, 0x68, 0, 24);8281 8282/* reg_rauht_mac8283 * MAC address.8284 * Access: RW8285 */8286MLXSW_ITEM_BUF(reg, rauht, mac, 0x6E, 6);8287 8288static inline void mlxsw_reg_rauht_pack(char *payload,8289					enum mlxsw_reg_rauht_op op, u16 rif,8290					const char *mac)8291{8292	MLXSW_REG_ZERO(rauht, payload);8293	mlxsw_reg_rauht_op_set(payload, op);8294	mlxsw_reg_rauht_rif_set(payload, rif);8295	mlxsw_reg_rauht_mac_memcpy_to(payload, mac);8296}8297 8298static inline void mlxsw_reg_rauht_pack4(char *payload,8299					 enum mlxsw_reg_rauht_op op, u16 rif,8300					 const char *mac, u32 dip)8301{8302	mlxsw_reg_rauht_pack(payload, op, rif, mac);8303	mlxsw_reg_rauht_dip4_set(payload, dip);8304}8305 8306static inline void mlxsw_reg_rauht_pack6(char *payload,8307					 enum mlxsw_reg_rauht_op op, u16 rif,8308					 const char *mac, const char *dip)8309{8310	mlxsw_reg_rauht_pack(payload, op, rif, mac);8311	mlxsw_reg_rauht_type_set(payload, MLXSW_REG_RAUHT_TYPE_IPV6);8312	mlxsw_reg_rauht_dip6_memcpy_to(payload, dip);8313}8314 8315static inline void mlxsw_reg_rauht_pack_counter(char *payload,8316						u64 counter_index)8317{8318	mlxsw_reg_rauht_counter_index_set(payload, counter_index);8319	mlxsw_reg_rauht_counter_set_type_set(payload,8320					     MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES);8321}8322 8323/* RALEU - Router Algorithmic LPM ECMP Update Register8324 * ---------------------------------------------------8325 * The register enables updating the ECMP section in the action for multiple8326 * LPM Unicast entries in a single operation. The update is executed to8327 * all entries of a {virtual router, protocol} tuple using the same ECMP group.8328 */8329#define MLXSW_REG_RALEU_ID 0x80158330#define MLXSW_REG_RALEU_LEN 0x288331 8332MLXSW_REG_DEFINE(raleu, MLXSW_REG_RALEU_ID, MLXSW_REG_RALEU_LEN);8333 8334/* reg_raleu_protocol8335 * Protocol.8336 * Access: Index8337 */8338MLXSW_ITEM32(reg, raleu, protocol, 0x00, 24, 4);8339 8340/* reg_raleu_virtual_router8341 * Virtual Router ID8342 * Range is 0..cap_max_virtual_routers-18343 * Access: Index8344 */8345MLXSW_ITEM32(reg, raleu, virtual_router, 0x00, 0, 16);8346 8347/* reg_raleu_adjacency_index8348 * Adjacency Index used for matching on the existing entries.8349 * Access: Index8350 */8351MLXSW_ITEM32(reg, raleu, adjacency_index, 0x10, 0, 24);8352 8353/* reg_raleu_ecmp_size8354 * ECMP Size used for matching on the existing entries.8355 * Access: Index8356 */8357MLXSW_ITEM32(reg, raleu, ecmp_size, 0x14, 0, 13);8358 8359/* reg_raleu_new_adjacency_index8360 * New Adjacency Index.8361 * Access: WO8362 */8363MLXSW_ITEM32(reg, raleu, new_adjacency_index, 0x20, 0, 24);8364 8365/* reg_raleu_new_ecmp_size8366 * New ECMP Size.8367 * Access: WO8368 */8369MLXSW_ITEM32(reg, raleu, new_ecmp_size, 0x24, 0, 13);8370 8371static inline void mlxsw_reg_raleu_pack(char *payload,8372					enum mlxsw_reg_ralxx_protocol protocol,8373					u16 virtual_router,8374					u32 adjacency_index, u16 ecmp_size,8375					u32 new_adjacency_index,8376					u16 new_ecmp_size)8377{8378	MLXSW_REG_ZERO(raleu, payload);8379	mlxsw_reg_raleu_protocol_set(payload, protocol);8380	mlxsw_reg_raleu_virtual_router_set(payload, virtual_router);8381	mlxsw_reg_raleu_adjacency_index_set(payload, adjacency_index);8382	mlxsw_reg_raleu_ecmp_size_set(payload, ecmp_size);8383	mlxsw_reg_raleu_new_adjacency_index_set(payload, new_adjacency_index);8384	mlxsw_reg_raleu_new_ecmp_size_set(payload, new_ecmp_size);8385}8386 8387/* RAUHTD - Router Algorithmic LPM Unicast Host Table Dump Register8388 * ----------------------------------------------------------------8389 * The RAUHTD register allows dumping entries from the Router Unicast Host8390 * Table. For a given session an entry is dumped no more than one time. The8391 * first RAUHTD access after reset is a new session. A session ends when the8392 * num_rec response is smaller than num_rec request or for IPv4 when the8393 * num_entries is smaller than 4. The clear activity affect the current session8394 * or the last session if a new session has not started.8395 */8396#define MLXSW_REG_RAUHTD_ID 0x80188397#define MLXSW_REG_RAUHTD_BASE_LEN 0x208398#define MLXSW_REG_RAUHTD_REC_LEN 0x208399#define MLXSW_REG_RAUHTD_REC_MAX_NUM 328400#define MLXSW_REG_RAUHTD_LEN (MLXSW_REG_RAUHTD_BASE_LEN + \8401		MLXSW_REG_RAUHTD_REC_MAX_NUM * MLXSW_REG_RAUHTD_REC_LEN)8402#define MLXSW_REG_RAUHTD_IPV4_ENT_PER_REC 48403 8404MLXSW_REG_DEFINE(rauhtd, MLXSW_REG_RAUHTD_ID, MLXSW_REG_RAUHTD_LEN);8405 8406#define MLXSW_REG_RAUHTD_FILTER_A BIT(0)8407#define MLXSW_REG_RAUHTD_FILTER_RIF BIT(3)8408 8409/* reg_rauhtd_filter_fields8410 * if a bit is '0' then the relevant field is ignored and dump is done8411 * regardless of the field value8412 * Bit0 - filter by activity: entry_a8413 * Bit3 - filter by entry rip: entry_rif8414 * Access: Index8415 */8416MLXSW_ITEM32(reg, rauhtd, filter_fields, 0x00, 0, 8);8417 8418enum mlxsw_reg_rauhtd_op {8419	MLXSW_REG_RAUHTD_OP_DUMP,8420	MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR,8421};8422 8423/* reg_rauhtd_op8424 * Access: OP8425 */8426MLXSW_ITEM32(reg, rauhtd, op, 0x04, 24, 2);8427 8428/* reg_rauhtd_num_rec8429 * At request: number of records requested8430 * At response: number of records dumped8431 * For IPv4, each record has 4 entries at request and up to 4 entries8432 * at response8433 * Range is 0..MLXSW_REG_RAUHTD_REC_MAX_NUM8434 * Access: Index8435 */8436MLXSW_ITEM32(reg, rauhtd, num_rec, 0x04, 0, 8);8437 8438/* reg_rauhtd_entry_a8439 * Dump only if activity has value of entry_a8440 * Reserved if filter_fields bit0 is '0'8441 * Access: Index8442 */8443MLXSW_ITEM32(reg, rauhtd, entry_a, 0x08, 16, 1);8444 8445enum mlxsw_reg_rauhtd_type {8446	MLXSW_REG_RAUHTD_TYPE_IPV4,8447	MLXSW_REG_RAUHTD_TYPE_IPV6,8448};8449 8450/* reg_rauhtd_type8451 * Dump only if record type is:8452 * 0 - IPv48453 * 1 - IPv68454 * Access: Index8455 */8456MLXSW_ITEM32(reg, rauhtd, type, 0x08, 0, 4);8457 8458/* reg_rauhtd_entry_rif8459 * Dump only if RIF has value of entry_rif8460 * Reserved if filter_fields bit3 is '0'8461 * Access: Index8462 */8463MLXSW_ITEM32(reg, rauhtd, entry_rif, 0x0C, 0, 16);8464 8465static inline void mlxsw_reg_rauhtd_pack(char *payload,8466					 enum mlxsw_reg_rauhtd_type type)8467{8468	MLXSW_REG_ZERO(rauhtd, payload);8469	mlxsw_reg_rauhtd_filter_fields_set(payload, MLXSW_REG_RAUHTD_FILTER_A);8470	mlxsw_reg_rauhtd_op_set(payload, MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR);8471	mlxsw_reg_rauhtd_num_rec_set(payload, MLXSW_REG_RAUHTD_REC_MAX_NUM);8472	mlxsw_reg_rauhtd_entry_a_set(payload, 1);8473	mlxsw_reg_rauhtd_type_set(payload, type);8474}8475 8476/* reg_rauhtd_ipv4_rec_num_entries8477 * Number of valid entries in this record:8478 * 0 - 1 valid entry8479 * 1 - 2 valid entries8480 * 2 - 3 valid entries8481 * 3 - 4 valid entries8482 * Access: RO8483 */8484MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_rec_num_entries,8485		     MLXSW_REG_RAUHTD_BASE_LEN, 28, 2,8486		     MLXSW_REG_RAUHTD_REC_LEN, 0x00, false);8487 8488/* reg_rauhtd_rec_type8489 * Record type.8490 * 0 - IPv48491 * 1 - IPv68492 * Access: RO8493 */8494MLXSW_ITEM32_INDEXED(reg, rauhtd, rec_type, MLXSW_REG_RAUHTD_BASE_LEN, 24, 2,8495		     MLXSW_REG_RAUHTD_REC_LEN, 0x00, false);8496 8497#define MLXSW_REG_RAUHTD_IPV4_ENT_LEN 0x88498 8499/* reg_rauhtd_ipv4_ent_a8500 * Activity. Set for new entries. Set if a packet lookup has hit on the8501 * specific entry.8502 * Access: RO8503 */8504MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1,8505		     MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false);8506 8507/* reg_rauhtd_ipv4_ent_rif8508 * Router interface.8509 * Access: RO8510 */8511MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0,8512		     16, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false);8513 8514/* reg_rauhtd_ipv4_ent_dip8515 * Destination IPv4 address.8516 * Access: RO8517 */8518MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN, 0,8519		     32, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x04, false);8520 8521#define MLXSW_REG_RAUHTD_IPV6_ENT_LEN 0x208522 8523/* reg_rauhtd_ipv6_ent_a8524 * Activity. Set for new entries. Set if a packet lookup has hit on the8525 * specific entry.8526 * Access: RO8527 */8528MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv6_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1,8529		     MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x00, false);8530 8531/* reg_rauhtd_ipv6_ent_rif8532 * Router interface.8533 * Access: RO8534 */8535MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv6_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0,8536		     16, MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x00, false);8537 8538/* reg_rauhtd_ipv6_ent_dip8539 * Destination IPv6 address.8540 * Access: RO8541 */8542MLXSW_ITEM_BUF_INDEXED(reg, rauhtd, ipv6_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN,8543		       16, MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x10);8544 8545static inline void mlxsw_reg_rauhtd_ent_ipv4_unpack(char *payload,8546						    int ent_index, u16 *p_rif,8547						    u32 *p_dip)8548{8549	*p_rif = mlxsw_reg_rauhtd_ipv4_ent_rif_get(payload, ent_index);8550	*p_dip = mlxsw_reg_rauhtd_ipv4_ent_dip_get(payload, ent_index);8551}8552 8553static inline void mlxsw_reg_rauhtd_ent_ipv6_unpack(char *payload,8554						    int rec_index, u16 *p_rif,8555						    char *p_dip)8556{8557	*p_rif = mlxsw_reg_rauhtd_ipv6_ent_rif_get(payload, rec_index);8558	mlxsw_reg_rauhtd_ipv6_ent_dip_memcpy_from(payload, rec_index, p_dip);8559}8560 8561/* RTDP - Routing Tunnel Decap Properties Register8562 * -----------------------------------------------8563 * The RTDP register is used for configuring the tunnel decap properties of NVE8564 * and IPinIP.8565 */8566#define MLXSW_REG_RTDP_ID 0x80208567#define MLXSW_REG_RTDP_LEN 0x448568 8569MLXSW_REG_DEFINE(rtdp, MLXSW_REG_RTDP_ID, MLXSW_REG_RTDP_LEN);8570 8571enum mlxsw_reg_rtdp_type {8572	MLXSW_REG_RTDP_TYPE_NVE,8573	MLXSW_REG_RTDP_TYPE_IPIP,8574};8575 8576/* reg_rtdp_type8577 * Type of the RTDP entry as per enum mlxsw_reg_rtdp_type.8578 * Access: RW8579 */8580MLXSW_ITEM32(reg, rtdp, type, 0x00, 28, 4);8581 8582/* reg_rtdp_tunnel_index8583 * Index to the Decap entry.8584 * For Spectrum, Index to KVD Linear.8585 * Access: Index8586 */8587MLXSW_ITEM32(reg, rtdp, tunnel_index, 0x00, 0, 24);8588 8589/* reg_rtdp_egress_router_interface8590 * Underlay egress router interface.8591 * Valid range is from 0 to cap_max_router_interfaces - 18592 * Access: RW8593 */8594MLXSW_ITEM32(reg, rtdp, egress_router_interface, 0x40, 0, 16);8595 8596/* IPinIP */8597 8598/* reg_rtdp_ipip_irif8599 * Ingress Router Interface for the overlay router8600 * Access: RW8601 */8602MLXSW_ITEM32(reg, rtdp, ipip_irif, 0x04, 16, 16);8603 8604enum mlxsw_reg_rtdp_ipip_sip_check {8605	/* No sip checks. */8606	MLXSW_REG_RTDP_IPIP_SIP_CHECK_NO,8607	/* Filter packet if underlay is not IPv4 or if underlay SIP does not8608	 * equal ipv4_usip.8609	 */8610	MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV4,8611	/* Filter packet if underlay is not IPv6 or if underlay SIP does not8612	 * equal ipv6_usip.8613	 */8614	MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV6 = 3,8615};8616 8617/* reg_rtdp_ipip_sip_check8618 * SIP check to perform. If decapsulation failed due to these configurations8619 * then trap_id is IPIP_DECAP_ERROR.8620 * Access: RW8621 */8622MLXSW_ITEM32(reg, rtdp, ipip_sip_check, 0x04, 0, 3);8623 8624/* If set, allow decapsulation of IPinIP (without GRE). */8625#define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_IPIP	BIT(0)8626/* If set, allow decapsulation of IPinGREinIP without a key. */8627#define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_GRE	BIT(1)8628/* If set, allow decapsulation of IPinGREinIP with a key. */8629#define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_GRE_KEY	BIT(2)8630 8631/* reg_rtdp_ipip_type_check8632 * Flags as per MLXSW_REG_RTDP_IPIP_TYPE_CHECK_*. If decapsulation failed due to8633 * these configurations then trap_id is IPIP_DECAP_ERROR.8634 * Access: RW8635 */8636MLXSW_ITEM32(reg, rtdp, ipip_type_check, 0x08, 24, 3);8637 8638/* reg_rtdp_ipip_gre_key_check8639 * Whether GRE key should be checked. When check is enabled:8640 * - A packet received as IPinIP (without GRE) will always pass.8641 * - A packet received as IPinGREinIP without a key will not pass the check.8642 * - A packet received as IPinGREinIP with a key will pass the check only if the8643 *   key in the packet is equal to expected_gre_key.8644 * If decapsulation failed due to GRE key then trap_id is IPIP_DECAP_ERROR.8645 * Access: RW8646 */8647MLXSW_ITEM32(reg, rtdp, ipip_gre_key_check, 0x08, 23, 1);8648 8649/* reg_rtdp_ipip_ipv4_usip8650 * Underlay IPv4 address for ipv4 source address check.8651 * Reserved when sip_check is not '1'.8652 * Access: RW8653 */8654MLXSW_ITEM32(reg, rtdp, ipip_ipv4_usip, 0x0C, 0, 32);8655 8656/* reg_rtdp_ipip_ipv6_usip_ptr8657 * This field is valid when sip_check is "sipv6 check explicitly". This is a8658 * pointer to the IPv6 DIP which is configured by RIPS. For Spectrum, the index8659 * is to the KVD linear.8660 * Reserved when sip_check is not MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV6.8661 * Access: RW8662 */8663MLXSW_ITEM32(reg, rtdp, ipip_ipv6_usip_ptr, 0x10, 0, 24);8664 8665/* reg_rtdp_ipip_expected_gre_key8666 * GRE key for checking.8667 * Reserved when gre_key_check is '0'.8668 * Access: RW8669 */8670MLXSW_ITEM32(reg, rtdp, ipip_expected_gre_key, 0x14, 0, 32);8671 8672static inline void mlxsw_reg_rtdp_pack(char *payload,8673				       enum mlxsw_reg_rtdp_type type,8674				       u32 tunnel_index)8675{8676	MLXSW_REG_ZERO(rtdp, payload);8677	mlxsw_reg_rtdp_type_set(payload, type);8678	mlxsw_reg_rtdp_tunnel_index_set(payload, tunnel_index);8679}8680 8681static inline void8682mlxsw_reg_rtdp_ipip_pack(char *payload, u16 irif,8683			 enum mlxsw_reg_rtdp_ipip_sip_check sip_check,8684			 unsigned int type_check, bool gre_key_check,8685			 u32 expected_gre_key)8686{8687	mlxsw_reg_rtdp_ipip_irif_set(payload, irif);8688	mlxsw_reg_rtdp_ipip_sip_check_set(payload, sip_check);8689	mlxsw_reg_rtdp_ipip_type_check_set(payload, type_check);8690	mlxsw_reg_rtdp_ipip_gre_key_check_set(payload, gre_key_check);8691	mlxsw_reg_rtdp_ipip_expected_gre_key_set(payload, expected_gre_key);8692}8693 8694static inline void8695mlxsw_reg_rtdp_ipip4_pack(char *payload, u16 irif,8696			  enum mlxsw_reg_rtdp_ipip_sip_check sip_check,8697			  unsigned int type_check, bool gre_key_check,8698			  u32 ipv4_usip, u32 expected_gre_key)8699{8700	mlxsw_reg_rtdp_ipip_pack(payload, irif, sip_check, type_check,8701				 gre_key_check, expected_gre_key);8702	mlxsw_reg_rtdp_ipip_ipv4_usip_set(payload, ipv4_usip);8703}8704 8705static inline void8706mlxsw_reg_rtdp_ipip6_pack(char *payload, u16 irif,8707			  enum mlxsw_reg_rtdp_ipip_sip_check sip_check,8708			  unsigned int type_check, bool gre_key_check,8709			  u32 ipv6_usip_ptr, u32 expected_gre_key)8710{8711	mlxsw_reg_rtdp_ipip_pack(payload, irif, sip_check, type_check,8712				 gre_key_check, expected_gre_key);8713	mlxsw_reg_rtdp_ipip_ipv6_usip_ptr_set(payload, ipv6_usip_ptr);8714}8715 8716/* RIPS - Router IP version Six Register8717 * -------------------------------------8718 * The RIPS register is used to store IPv6 addresses for use by the NVE and8719 * IPinIP8720 */8721#define MLXSW_REG_RIPS_ID 0x80218722#define MLXSW_REG_RIPS_LEN 0x148723 8724MLXSW_REG_DEFINE(rips, MLXSW_REG_RIPS_ID, MLXSW_REG_RIPS_LEN);8725 8726/* reg_rips_index8727 * Index to IPv6 address.8728 * For Spectrum, the index is to the KVD linear.8729 * Access: Index8730 */8731MLXSW_ITEM32(reg, rips, index, 0x00, 0, 24);8732 8733/* reg_rips_ipv68734 * IPv6 address8735 * Access: RW8736 */8737MLXSW_ITEM_BUF(reg, rips, ipv6, 0x04, 16);8738 8739static inline void mlxsw_reg_rips_pack(char *payload, u32 index,8740				       const struct in6_addr *ipv6)8741{8742	MLXSW_REG_ZERO(rips, payload);8743	mlxsw_reg_rips_index_set(payload, index);8744	mlxsw_reg_rips_ipv6_memcpy_to(payload, (const char *)ipv6);8745}8746 8747/* RATRAD - Router Adjacency Table Activity Dump Register8748 * ------------------------------------------------------8749 * The RATRAD register is used to dump and optionally clear activity bits of8750 * router adjacency table entries.8751 */8752#define MLXSW_REG_RATRAD_ID 0x80228753#define MLXSW_REG_RATRAD_LEN 0x2108754 8755MLXSW_REG_DEFINE(ratrad, MLXSW_REG_RATRAD_ID, MLXSW_REG_RATRAD_LEN);8756 8757enum {8758	/* Read activity */8759	MLXSW_REG_RATRAD_OP_READ_ACTIVITY,8760	/* Read and clear activity */8761	MLXSW_REG_RATRAD_OP_READ_CLEAR_ACTIVITY,8762};8763 8764/* reg_ratrad_op8765 * Access: Operation8766 */8767MLXSW_ITEM32(reg, ratrad, op, 0x00, 30, 2);8768 8769/* reg_ratrad_ecmp_size8770 * ecmp_size is the amount of sequential entries from adjacency_index. Valid8771 * ranges:8772 * Spectrum-1: 32-64, 512, 1024, 2048, 40968773 * Spectrum-2/3: 32-128, 256, 512, 1024, 2048, 40968774 * Access: Index8775 */8776MLXSW_ITEM32(reg, ratrad, ecmp_size, 0x00, 0, 13);8777 8778/* reg_ratrad_adjacency_index8779 * Index into the adjacency table.8780 * Access: Index8781 */8782MLXSW_ITEM32(reg, ratrad, adjacency_index, 0x04, 0, 24);8783 8784/* reg_ratrad_activity_vector8785 * Activity bit per adjacency index.8786 * Bits higher than ecmp_size are reserved.8787 * Access: RO8788 */8789MLXSW_ITEM_BIT_ARRAY(reg, ratrad, activity_vector, 0x10, 0x200, 1);8790 8791static inline void mlxsw_reg_ratrad_pack(char *payload, u32 adjacency_index,8792					 u16 ecmp_size)8793{8794	MLXSW_REG_ZERO(ratrad, payload);8795	mlxsw_reg_ratrad_op_set(payload,8796				MLXSW_REG_RATRAD_OP_READ_CLEAR_ACTIVITY);8797	mlxsw_reg_ratrad_ecmp_size_set(payload, ecmp_size);8798	mlxsw_reg_ratrad_adjacency_index_set(payload, adjacency_index);8799}8800 8801/* RIGR-V2 - Router Interface Group Register Version 28802 * ---------------------------------------------------8803 * The RIGR_V2 register is used to add, remove and query egress interface list8804 * of a multicast forwarding entry.8805 */8806#define MLXSW_REG_RIGR2_ID 0x80238807#define MLXSW_REG_RIGR2_LEN 0xB08808 8809#define MLXSW_REG_RIGR2_MAX_ERIFS 328810 8811MLXSW_REG_DEFINE(rigr2, MLXSW_REG_RIGR2_ID, MLXSW_REG_RIGR2_LEN);8812 8813/* reg_rigr2_rigr_index8814 * KVD Linear index.8815 * Access: Index8816 */8817MLXSW_ITEM32(reg, rigr2, rigr_index, 0x04, 0, 24);8818 8819/* reg_rigr2_vnext8820 * Next RIGR Index is valid.8821 * Access: RW8822 */8823MLXSW_ITEM32(reg, rigr2, vnext, 0x08, 31, 1);8824 8825/* reg_rigr2_next_rigr_index8826 * Next RIGR Index. The index is to the KVD linear.8827 * Reserved when vnxet = '0'.8828 * Access: RW8829 */8830MLXSW_ITEM32(reg, rigr2, next_rigr_index, 0x08, 0, 24);8831 8832/* reg_rigr2_vrmid8833 * RMID Index is valid.8834 * Access: RW8835 */8836MLXSW_ITEM32(reg, rigr2, vrmid, 0x20, 31, 1);8837 8838/* reg_rigr2_rmid_index8839 * RMID Index.8840 * Range 0 .. max_mid - 18841 * Reserved when vrmid = '0'.8842 * The index is to the Port Group Table (PGT)8843 * Access: RW8844 */8845MLXSW_ITEM32(reg, rigr2, rmid_index, 0x20, 0, 16);8846 8847/* reg_rigr2_erif_entry_v8848 * Egress Router Interface is valid.8849 * Note that low-entries must be set if high-entries are set. For8850 * example: if erif_entry[2].v is set then erif_entry[1].v and8851 * erif_entry[0].v must be set.8852 * Index can be from 0 to cap_mc_erif_list_entries-18853 * Access: RW8854 */8855MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_v, 0x24, 31, 1, 4, 0, false);8856 8857/* reg_rigr2_erif_entry_erif8858 * Egress Router Interface.8859 * Valid range is from 0 to cap_max_router_interfaces - 18860 * Index can be from 0 to MLXSW_REG_RIGR2_MAX_ERIFS - 18861 * Access: RW8862 */8863MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_erif, 0x24, 0, 16, 4, 0, false);8864 8865static inline void mlxsw_reg_rigr2_pack(char *payload, u32 rigr_index,8866					bool vnext, u32 next_rigr_index)8867{8868	MLXSW_REG_ZERO(rigr2, payload);8869	mlxsw_reg_rigr2_rigr_index_set(payload, rigr_index);8870	mlxsw_reg_rigr2_vnext_set(payload, vnext);8871	mlxsw_reg_rigr2_next_rigr_index_set(payload, next_rigr_index);8872	mlxsw_reg_rigr2_vrmid_set(payload, 0);8873	mlxsw_reg_rigr2_rmid_index_set(payload, 0);8874}8875 8876static inline void mlxsw_reg_rigr2_erif_entry_pack(char *payload, int index,8877						   bool v, u16 erif)8878{8879	mlxsw_reg_rigr2_erif_entry_v_set(payload, index, v);8880	mlxsw_reg_rigr2_erif_entry_erif_set(payload, index, erif);8881}8882 8883/* RECR-V2 - Router ECMP Configuration Version 2 Register8884 * ------------------------------------------------------8885 */8886#define MLXSW_REG_RECR2_ID 0x80258887#define MLXSW_REG_RECR2_LEN 0x388888 8889MLXSW_REG_DEFINE(recr2, MLXSW_REG_RECR2_ID, MLXSW_REG_RECR2_LEN);8890 8891/* reg_recr2_pp8892 * Per-port configuration8893 * Access: Index8894 */8895MLXSW_ITEM32(reg, recr2, pp, 0x00, 24, 1);8896 8897/* reg_recr2_sh8898 * Symmetric hash8899 * Access: RW8900 */8901MLXSW_ITEM32(reg, recr2, sh, 0x00, 8, 1);8902 8903/* reg_recr2_seed8904 * Seed8905 * Access: RW8906 */8907MLXSW_ITEM32(reg, recr2, seed, 0x08, 0, 32);8908 8909enum {8910	/* Enable IPv4 fields if packet is not TCP and not UDP */8911	MLXSW_REG_RECR2_IPV4_EN_NOT_TCP_NOT_UDP	= 3,8912	/* Enable IPv4 fields if packet is TCP or UDP */8913	MLXSW_REG_RECR2_IPV4_EN_TCP_UDP		= 4,8914	/* Enable IPv6 fields if packet is not TCP and not UDP */8915	MLXSW_REG_RECR2_IPV6_EN_NOT_TCP_NOT_UDP	= 5,8916	/* Enable IPv6 fields if packet is TCP or UDP */8917	MLXSW_REG_RECR2_IPV6_EN_TCP_UDP		= 6,8918	/* Enable TCP/UDP header fields if packet is IPv4 */8919	MLXSW_REG_RECR2_TCP_UDP_EN_IPV4		= 7,8920	/* Enable TCP/UDP header fields if packet is IPv6 */8921	MLXSW_REG_RECR2_TCP_UDP_EN_IPV6		= 8,8922 8923	__MLXSW_REG_RECR2_HEADER_CNT,8924};8925 8926/* reg_recr2_outer_header_enables8927 * Bit mask where each bit enables a specific layer to be included in8928 * the hash calculation.8929 * Access: RW8930 */8931MLXSW_ITEM_BIT_ARRAY(reg, recr2, outer_header_enables, 0x10, 0x04, 1);8932 8933enum {8934	/* IPv4 Source IP */8935	MLXSW_REG_RECR2_IPV4_SIP0			= 9,8936	MLXSW_REG_RECR2_IPV4_SIP3			= 12,8937	/* IPv4 Destination IP */8938	MLXSW_REG_RECR2_IPV4_DIP0			= 13,8939	MLXSW_REG_RECR2_IPV4_DIP3			= 16,8940	/* IP Protocol */8941	MLXSW_REG_RECR2_IPV4_PROTOCOL			= 17,8942	/* IPv6 Source IP */8943	MLXSW_REG_RECR2_IPV6_SIP0_7			= 21,8944	MLXSW_REG_RECR2_IPV6_SIP8			= 29,8945	MLXSW_REG_RECR2_IPV6_SIP15			= 36,8946	/* IPv6 Destination IP */8947	MLXSW_REG_RECR2_IPV6_DIP0_7			= 37,8948	MLXSW_REG_RECR2_IPV6_DIP8			= 45,8949	MLXSW_REG_RECR2_IPV6_DIP15			= 52,8950	/* IPv6 Next Header */8951	MLXSW_REG_RECR2_IPV6_NEXT_HEADER		= 53,8952	/* IPv6 Flow Label */8953	MLXSW_REG_RECR2_IPV6_FLOW_LABEL			= 57,8954	/* TCP/UDP Source Port */8955	MLXSW_REG_RECR2_TCP_UDP_SPORT			= 74,8956	/* TCP/UDP Destination Port */8957	MLXSW_REG_RECR2_TCP_UDP_DPORT			= 75,8958 8959	__MLXSW_REG_RECR2_FIELD_CNT,8960};8961 8962/* reg_recr2_outer_header_fields_enable8963 * Packet fields to enable for ECMP hash subject to outer_header_enable.8964 * Access: RW8965 */8966MLXSW_ITEM_BIT_ARRAY(reg, recr2, outer_header_fields_enable, 0x14, 0x14, 1);8967 8968/* reg_recr2_inner_header_enables8969 * Bit mask where each bit enables a specific inner layer to be included in the8970 * hash calculation. Same values as reg_recr2_outer_header_enables.8971 * Access: RW8972 */8973MLXSW_ITEM_BIT_ARRAY(reg, recr2, inner_header_enables, 0x2C, 0x04, 1);8974 8975enum {8976	/* Inner IPv4 Source IP */8977	MLXSW_REG_RECR2_INNER_IPV4_SIP0			= 3,8978	MLXSW_REG_RECR2_INNER_IPV4_SIP3			= 6,8979	/* Inner IPv4 Destination IP */8980	MLXSW_REG_RECR2_INNER_IPV4_DIP0			= 7,8981	MLXSW_REG_RECR2_INNER_IPV4_DIP3			= 10,8982	/* Inner IP Protocol */8983	MLXSW_REG_RECR2_INNER_IPV4_PROTOCOL		= 11,8984	/* Inner IPv6 Source IP */8985	MLXSW_REG_RECR2_INNER_IPV6_SIP0_7		= 12,8986	MLXSW_REG_RECR2_INNER_IPV6_SIP8			= 20,8987	MLXSW_REG_RECR2_INNER_IPV6_SIP15		= 27,8988	/* Inner IPv6 Destination IP */8989	MLXSW_REG_RECR2_INNER_IPV6_DIP0_7		= 28,8990	MLXSW_REG_RECR2_INNER_IPV6_DIP8			= 36,8991	MLXSW_REG_RECR2_INNER_IPV6_DIP15		= 43,8992	/* Inner IPv6 Next Header */8993	MLXSW_REG_RECR2_INNER_IPV6_NEXT_HEADER		= 44,8994	/* Inner IPv6 Flow Label */8995	MLXSW_REG_RECR2_INNER_IPV6_FLOW_LABEL		= 45,8996	/* Inner TCP/UDP Source Port */8997	MLXSW_REG_RECR2_INNER_TCP_UDP_SPORT		= 46,8998	/* Inner TCP/UDP Destination Port */8999	MLXSW_REG_RECR2_INNER_TCP_UDP_DPORT		= 47,9000 9001	__MLXSW_REG_RECR2_INNER_FIELD_CNT,9002};9003 9004/* reg_recr2_inner_header_fields_enable9005 * Inner packet fields to enable for ECMP hash subject to inner_header_enables.9006 * Access: RW9007 */9008MLXSW_ITEM_BIT_ARRAY(reg, recr2, inner_header_fields_enable, 0x30, 0x08, 1);9009 9010static inline void mlxsw_reg_recr2_pack(char *payload, u32 seed)9011{9012	MLXSW_REG_ZERO(recr2, payload);9013	mlxsw_reg_recr2_pp_set(payload, false);9014	mlxsw_reg_recr2_sh_set(payload, true);9015	mlxsw_reg_recr2_seed_set(payload, seed);9016}9017 9018/* RMFT-V2 - Router Multicast Forwarding Table Version 2 Register9019 * --------------------------------------------------------------9020 * The RMFT_V2 register is used to configure and query the multicast table.9021 */9022#define MLXSW_REG_RMFT2_ID 0x80279023#define MLXSW_REG_RMFT2_LEN 0x1749024 9025MLXSW_REG_DEFINE(rmft2, MLXSW_REG_RMFT2_ID, MLXSW_REG_RMFT2_LEN);9026 9027/* reg_rmft2_v9028 * Valid9029 * Access: RW9030 */9031MLXSW_ITEM32(reg, rmft2, v, 0x00, 31, 1);9032 9033enum mlxsw_reg_rmft2_type {9034	MLXSW_REG_RMFT2_TYPE_IPV4,9035	MLXSW_REG_RMFT2_TYPE_IPV69036};9037 9038/* reg_rmft2_type9039 * Access: Index9040 */9041MLXSW_ITEM32(reg, rmft2, type, 0x00, 28, 2);9042 9043enum mlxsw_sp_reg_rmft2_op {9044	/* For Write:9045	 * Write operation. Used to write a new entry to the table. All RW9046	 * fields are relevant for new entry. Activity bit is set for new9047	 * entries - Note write with v (Valid) 0 will delete the entry.9048	 * For Query:9049	 * Read operation9050	 */9051	MLXSW_REG_RMFT2_OP_READ_WRITE,9052};9053 9054/* reg_rmft2_op9055 * Operation.9056 * Access: OP9057 */9058MLXSW_ITEM32(reg, rmft2, op, 0x00, 20, 2);9059 9060/* reg_rmft2_a9061 * Activity. Set for new entries. Set if a packet lookup has hit on the specific9062 * entry.9063 * Access: RO9064 */9065MLXSW_ITEM32(reg, rmft2, a, 0x00, 16, 1);9066 9067/* reg_rmft2_offset9068 * Offset within the multicast forwarding table to write to.9069 * Access: Index9070 */9071MLXSW_ITEM32(reg, rmft2, offset, 0x00, 0, 16);9072 9073/* reg_rmft2_virtual_router9074 * Virtual Router ID. Range from 0..cap_max_virtual_routers-19075 * Access: RW9076 */9077MLXSW_ITEM32(reg, rmft2, virtual_router, 0x04, 0, 16);9078 9079enum mlxsw_reg_rmft2_irif_mask {9080	MLXSW_REG_RMFT2_IRIF_MASK_IGNORE,9081	MLXSW_REG_RMFT2_IRIF_MASK_COMPARE9082};9083 9084/* reg_rmft2_irif_mask9085 * Ingress RIF mask.9086 * Access: RW9087 */9088MLXSW_ITEM32(reg, rmft2, irif_mask, 0x08, 24, 1);9089 9090/* reg_rmft2_irif9091 * Ingress RIF index.9092 * Access: RW9093 */9094MLXSW_ITEM32(reg, rmft2, irif, 0x08, 0, 16);9095 9096/* reg_rmft2_dip{4,6}9097 * Destination IPv4/6 address9098 * Access: RW9099 */9100MLXSW_ITEM_BUF(reg, rmft2, dip6, 0x10, 16);9101MLXSW_ITEM32(reg, rmft2, dip4, 0x1C, 0, 32);9102 9103/* reg_rmft2_dip{4,6}_mask9104 * A bit that is set directs the TCAM to compare the corresponding bit in key. A9105 * bit that is clear directs the TCAM to ignore the corresponding bit in key.9106 * Access: RW9107 */9108MLXSW_ITEM_BUF(reg, rmft2, dip6_mask, 0x20, 16);9109MLXSW_ITEM32(reg, rmft2, dip4_mask, 0x2C, 0, 32);9110 9111/* reg_rmft2_sip{4,6}9112 * Source IPv4/6 address9113 * Access: RW9114 */9115MLXSW_ITEM_BUF(reg, rmft2, sip6, 0x30, 16);9116MLXSW_ITEM32(reg, rmft2, sip4, 0x3C, 0, 32);9117 9118/* reg_rmft2_sip{4,6}_mask9119 * A bit that is set directs the TCAM to compare the corresponding bit in key. A9120 * bit that is clear directs the TCAM to ignore the corresponding bit in key.9121 * Access: RW9122 */9123MLXSW_ITEM_BUF(reg, rmft2, sip6_mask, 0x40, 16);9124MLXSW_ITEM32(reg, rmft2, sip4_mask, 0x4C, 0, 32);9125 9126/* reg_rmft2_flexible_action_set9127 * ACL action set. The only supported action types in this field and in any9128 * action-set pointed from here are as follows:9129 * 00h: ACTION_NULL9130 * 01h: ACTION_MAC_TTL, only TTL configuration is supported.9131 * 03h: ACTION_TRAP9132 * 06h: ACTION_QOS9133 * 08h: ACTION_POLICING_MONITORING9134 * 10h: ACTION_ROUTER_MC9135 * Access: RW9136 */9137MLXSW_ITEM_BUF(reg, rmft2, flexible_action_set, 0x80,9138	       MLXSW_REG_FLEX_ACTION_SET_LEN);9139 9140static inline void9141mlxsw_reg_rmft2_common_pack(char *payload, bool v, u16 offset,9142			    u16 virtual_router,9143			    enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif,9144			    const char *flex_action_set)9145{9146	MLXSW_REG_ZERO(rmft2, payload);9147	mlxsw_reg_rmft2_v_set(payload, v);9148	mlxsw_reg_rmft2_op_set(payload, MLXSW_REG_RMFT2_OP_READ_WRITE);9149	mlxsw_reg_rmft2_offset_set(payload, offset);9150	mlxsw_reg_rmft2_virtual_router_set(payload, virtual_router);9151	mlxsw_reg_rmft2_irif_mask_set(payload, irif_mask);9152	mlxsw_reg_rmft2_irif_set(payload, irif);9153	if (flex_action_set)9154		mlxsw_reg_rmft2_flexible_action_set_memcpy_to(payload,9155							      flex_action_set);9156}9157 9158static inline void9159mlxsw_reg_rmft2_ipv4_pack(char *payload, bool v, u16 offset, u16 virtual_router,9160			  enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif,9161			  u32 dip4, u32 dip4_mask, u32 sip4, u32 sip4_mask,9162			  const char *flexible_action_set)9163{9164	mlxsw_reg_rmft2_common_pack(payload, v, offset, virtual_router,9165				    irif_mask, irif, flexible_action_set);9166	mlxsw_reg_rmft2_type_set(payload, MLXSW_REG_RMFT2_TYPE_IPV4);9167	mlxsw_reg_rmft2_dip4_set(payload, dip4);9168	mlxsw_reg_rmft2_dip4_mask_set(payload, dip4_mask);9169	mlxsw_reg_rmft2_sip4_set(payload, sip4);9170	mlxsw_reg_rmft2_sip4_mask_set(payload, sip4_mask);9171}9172 9173static inline void9174mlxsw_reg_rmft2_ipv6_pack(char *payload, bool v, u16 offset, u16 virtual_router,9175			  enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif,9176			  struct in6_addr dip6, struct in6_addr dip6_mask,9177			  struct in6_addr sip6, struct in6_addr sip6_mask,9178			  const char *flexible_action_set)9179{9180	mlxsw_reg_rmft2_common_pack(payload, v, offset, virtual_router,9181				    irif_mask, irif, flexible_action_set);9182	mlxsw_reg_rmft2_type_set(payload, MLXSW_REG_RMFT2_TYPE_IPV6);9183	mlxsw_reg_rmft2_dip6_memcpy_to(payload, (void *)&dip6);9184	mlxsw_reg_rmft2_dip6_mask_memcpy_to(payload, (void *)&dip6_mask);9185	mlxsw_reg_rmft2_sip6_memcpy_to(payload, (void *)&sip6);9186	mlxsw_reg_rmft2_sip6_mask_memcpy_to(payload, (void *)&sip6_mask);9187}9188 9189/* REIV - Router Egress Interface to VID Register9190 * ----------------------------------------------9191 * The REIV register maps {eRIF, egress_port} -> VID.9192 * This mapping is done at the egress, after the ACLs.9193 * This mapping always takes effect after router, regardless of cast9194 * (for unicast/multicast/port-base multicast), regardless of eRIF type and9195 * regardless of bridge decisions (e.g. SFD for unicast or SMPE).9196 * Reserved when the RIF is a loopback RIF.9197 *9198 * Note: Reserved when legacy bridge model is used.9199 */9200#define MLXSW_REG_REIV_ID 0x80349201#define MLXSW_REG_REIV_BASE_LEN 0x20 /* base length, without records */9202#define MLXSW_REG_REIV_REC_LEN 0x04 /* record length */9203#define MLXSW_REG_REIV_REC_MAX_COUNT 256 /* firmware limitation */9204#define MLXSW_REG_REIV_LEN (MLXSW_REG_REIV_BASE_LEN +	\9205			    MLXSW_REG_REIV_REC_LEN *	\9206			    MLXSW_REG_REIV_REC_MAX_COUNT)9207 9208MLXSW_REG_DEFINE(reiv, MLXSW_REG_REIV_ID, MLXSW_REG_REIV_LEN);9209 9210/* reg_reiv_port_page9211 * Port page - elport_record[0] is 256*port_page.9212 * Access: Index9213 */9214MLXSW_ITEM32(reg, reiv, port_page, 0x00, 0, 4);9215 9216/* reg_reiv_erif9217 * Egress RIF.9218 * Range is 0..cap_max_router_interfaces-1.9219 * Access: Index9220 */9221MLXSW_ITEM32(reg, reiv, erif, 0x04, 0, 16);9222 9223/* reg_reiv_rec_update9224 * Update enable (when write):9225 * 0 - Do not update the entry.9226 * 1 - Update the entry.9227 * Access: OP9228 */9229MLXSW_ITEM32_INDEXED(reg, reiv, rec_update, MLXSW_REG_REIV_BASE_LEN, 31, 1,9230		     MLXSW_REG_REIV_REC_LEN, 0x00, false);9231 9232/* reg_reiv_rec_evid9233 * Egress VID.9234 * Range is 0..4095.9235 * Access: RW9236 */9237MLXSW_ITEM32_INDEXED(reg, reiv, rec_evid, MLXSW_REG_REIV_BASE_LEN, 0, 12,9238		     MLXSW_REG_REIV_REC_LEN, 0x00, false);9239 9240static inline void mlxsw_reg_reiv_pack(char *payload, u8 port_page, u16 erif)9241{9242	MLXSW_REG_ZERO(reiv, payload);9243	mlxsw_reg_reiv_port_page_set(payload, port_page);9244	mlxsw_reg_reiv_erif_set(payload, erif);9245}9246 9247/* MFCR - Management Fan Control Register9248 * --------------------------------------9249 * This register controls the settings of the Fan Speed PWM mechanism.9250 */9251#define MLXSW_REG_MFCR_ID 0x90019252#define MLXSW_REG_MFCR_LEN 0x089253 9254MLXSW_REG_DEFINE(mfcr, MLXSW_REG_MFCR_ID, MLXSW_REG_MFCR_LEN);9255 9256enum mlxsw_reg_mfcr_pwm_frequency {9257	MLXSW_REG_MFCR_PWM_FEQ_11HZ = 0x00,9258	MLXSW_REG_MFCR_PWM_FEQ_14_7HZ = 0x01,9259	MLXSW_REG_MFCR_PWM_FEQ_22_1HZ = 0x02,9260	MLXSW_REG_MFCR_PWM_FEQ_1_4KHZ = 0x40,9261	MLXSW_REG_MFCR_PWM_FEQ_5KHZ = 0x41,9262	MLXSW_REG_MFCR_PWM_FEQ_20KHZ = 0x42,9263	MLXSW_REG_MFCR_PWM_FEQ_22_5KHZ = 0x43,9264	MLXSW_REG_MFCR_PWM_FEQ_25KHZ = 0x44,9265};9266 9267/* reg_mfcr_pwm_frequency9268 * Controls the frequency of the PWM signal.9269 * Access: RW9270 */9271MLXSW_ITEM32(reg, mfcr, pwm_frequency, 0x00, 0, 7);9272 9273#define MLXSW_MFCR_TACHOS_MAX 109274 9275/* reg_mfcr_tacho_active9276 * Indicates which of the tachometer is active (bit per tachometer).9277 * Access: RO9278 */9279MLXSW_ITEM32(reg, mfcr, tacho_active, 0x04, 16, MLXSW_MFCR_TACHOS_MAX);9280 9281#define MLXSW_MFCR_PWMS_MAX 59282 9283/* reg_mfcr_pwm_active9284 * Indicates which of the PWM control is active (bit per PWM).9285 * Access: RO9286 */9287MLXSW_ITEM32(reg, mfcr, pwm_active, 0x04, 0, MLXSW_MFCR_PWMS_MAX);9288 9289static inline void9290mlxsw_reg_mfcr_pack(char *payload,9291		    enum mlxsw_reg_mfcr_pwm_frequency pwm_frequency)9292{9293	MLXSW_REG_ZERO(mfcr, payload);9294	mlxsw_reg_mfcr_pwm_frequency_set(payload, pwm_frequency);9295}9296 9297static inline void9298mlxsw_reg_mfcr_unpack(char *payload,9299		      enum mlxsw_reg_mfcr_pwm_frequency *p_pwm_frequency,9300		      u16 *p_tacho_active, u8 *p_pwm_active)9301{9302	*p_pwm_frequency = mlxsw_reg_mfcr_pwm_frequency_get(payload);9303	*p_tacho_active = mlxsw_reg_mfcr_tacho_active_get(payload);9304	*p_pwm_active = mlxsw_reg_mfcr_pwm_active_get(payload);9305}9306 9307/* MFSC - Management Fan Speed Control Register9308 * --------------------------------------------9309 * This register controls the settings of the Fan Speed PWM mechanism.9310 */9311#define MLXSW_REG_MFSC_ID 0x90029312#define MLXSW_REG_MFSC_LEN 0x089313 9314MLXSW_REG_DEFINE(mfsc, MLXSW_REG_MFSC_ID, MLXSW_REG_MFSC_LEN);9315 9316/* reg_mfsc_pwm9317 * Fan pwm to control / monitor.9318 * Access: Index9319 */9320MLXSW_ITEM32(reg, mfsc, pwm, 0x00, 24, 3);9321 9322/* reg_mfsc_pwm_duty_cycle9323 * Controls the duty cycle of the PWM. Value range from 0..255 to9324 * represent duty cycle of 0%...100%.9325 * Access: RW9326 */9327MLXSW_ITEM32(reg, mfsc, pwm_duty_cycle, 0x04, 0, 8);9328 9329static inline void mlxsw_reg_mfsc_pack(char *payload, u8 pwm,9330				       u8 pwm_duty_cycle)9331{9332	MLXSW_REG_ZERO(mfsc, payload);9333	mlxsw_reg_mfsc_pwm_set(payload, pwm);9334	mlxsw_reg_mfsc_pwm_duty_cycle_set(payload, pwm_duty_cycle);9335}9336 9337/* MFSM - Management Fan Speed Measurement9338 * ---------------------------------------9339 * This register controls the settings of the Tacho measurements and9340 * enables reading the Tachometer measurements.9341 */9342#define MLXSW_REG_MFSM_ID 0x90039343#define MLXSW_REG_MFSM_LEN 0x089344 9345MLXSW_REG_DEFINE(mfsm, MLXSW_REG_MFSM_ID, MLXSW_REG_MFSM_LEN);9346 9347/* reg_mfsm_tacho9348 * Fan tachometer index.9349 * Access: Index9350 */9351MLXSW_ITEM32(reg, mfsm, tacho, 0x00, 24, 4);9352 9353/* reg_mfsm_rpm9354 * Fan speed (round per minute).9355 * Access: RO9356 */9357MLXSW_ITEM32(reg, mfsm, rpm, 0x04, 0, 16);9358 9359static inline void mlxsw_reg_mfsm_pack(char *payload, u8 tacho)9360{9361	MLXSW_REG_ZERO(mfsm, payload);9362	mlxsw_reg_mfsm_tacho_set(payload, tacho);9363}9364 9365/* MFSL - Management Fan Speed Limit Register9366 * ------------------------------------------9367 * The Fan Speed Limit register is used to configure the fan speed9368 * event / interrupt notification mechanism. Fan speed threshold are9369 * defined for both under-speed and over-speed.9370 */9371#define MLXSW_REG_MFSL_ID 0x90049372#define MLXSW_REG_MFSL_LEN 0x0C9373 9374MLXSW_REG_DEFINE(mfsl, MLXSW_REG_MFSL_ID, MLXSW_REG_MFSL_LEN);9375 9376/* reg_mfsl_tacho9377 * Fan tachometer index.9378 * Access: Index9379 */9380MLXSW_ITEM32(reg, mfsl, tacho, 0x00, 24, 4);9381 9382/* reg_mfsl_tach_min9383 * Tachometer minimum value (minimum RPM).9384 * Access: RW9385 */9386MLXSW_ITEM32(reg, mfsl, tach_min, 0x04, 0, 16);9387 9388/* reg_mfsl_tach_max9389 * Tachometer maximum value (maximum RPM).9390 * Access: RW9391 */9392MLXSW_ITEM32(reg, mfsl, tach_max, 0x08, 0, 16);9393 9394static inline void mlxsw_reg_mfsl_pack(char *payload, u8 tacho,9395				       u16 tach_min, u16 tach_max)9396{9397	MLXSW_REG_ZERO(mfsl, payload);9398	mlxsw_reg_mfsl_tacho_set(payload, tacho);9399	mlxsw_reg_mfsl_tach_min_set(payload, tach_min);9400	mlxsw_reg_mfsl_tach_max_set(payload, tach_max);9401}9402 9403static inline void mlxsw_reg_mfsl_unpack(char *payload, u8 tacho,9404					 u16 *p_tach_min, u16 *p_tach_max)9405{9406	if (p_tach_min)9407		*p_tach_min = mlxsw_reg_mfsl_tach_min_get(payload);9408 9409	if (p_tach_max)9410		*p_tach_max = mlxsw_reg_mfsl_tach_max_get(payload);9411}9412 9413/* FORE - Fan Out of Range Event Register9414 * --------------------------------------9415 * This register reports the status of the controlled fans compared to the9416 * range defined by the MFSL register.9417 */9418#define MLXSW_REG_FORE_ID 0x90079419#define MLXSW_REG_FORE_LEN 0x0C9420 9421MLXSW_REG_DEFINE(fore, MLXSW_REG_FORE_ID, MLXSW_REG_FORE_LEN);9422 9423/* fan_under_limit9424 * Fan speed is below the low limit defined in MFSL register. Each bit relates9425 * to a single tachometer and indicates the specific tachometer reading is9426 * below the threshold.9427 * Access: RO9428 */9429MLXSW_ITEM32(reg, fore, fan_under_limit, 0x00, 16, 10);9430 9431static inline void mlxsw_reg_fore_unpack(char *payload, u8 tacho,9432					 bool *fault)9433{9434	u16 limit;9435 9436	if (fault) {9437		limit = mlxsw_reg_fore_fan_under_limit_get(payload);9438		*fault = limit & BIT(tacho);9439	}9440}9441 9442/* MTCAP - Management Temperature Capabilities9443 * -------------------------------------------9444 * This register exposes the capabilities of the device and9445 * system temperature sensing.9446 */9447#define MLXSW_REG_MTCAP_ID 0x90099448#define MLXSW_REG_MTCAP_LEN 0x089449 9450MLXSW_REG_DEFINE(mtcap, MLXSW_REG_MTCAP_ID, MLXSW_REG_MTCAP_LEN);9451 9452/* reg_mtcap_sensor_count9453 * Number of sensors supported by the device.9454 * This includes the QSFP module sensors (if exists in the QSFP module).9455 * Access: RO9456 */9457MLXSW_ITEM32(reg, mtcap, sensor_count, 0x00, 0, 7);9458 9459/* MTMP - Management Temperature9460 * -----------------------------9461 * This register controls the settings of the temperature measurements9462 * and enables reading the temperature measurements. Note that temperature9463 * is in 0.125 degrees Celsius.9464 */9465#define MLXSW_REG_MTMP_ID 0x900A9466#define MLXSW_REG_MTMP_LEN 0x209467 9468MLXSW_REG_DEFINE(mtmp, MLXSW_REG_MTMP_ID, MLXSW_REG_MTMP_LEN);9469 9470/* reg_mtmp_slot_index9471 * Slot index (0: Main board).9472 * Access: Index9473 */9474MLXSW_ITEM32(reg, mtmp, slot_index, 0x00, 16, 4);9475 9476#define MLXSW_REG_MTMP_MODULE_INDEX_MIN 649477#define MLXSW_REG_MTMP_GBOX_INDEX_MIN 2569478/* reg_mtmp_sensor_index9479 * Sensors index to access.9480 * 64-127 of sensor_index are mapped to the SFP+/QSFP modules sequentially9481 * (module 0 is mapped to sensor_index 64).9482 * Access: Index9483 */9484MLXSW_ITEM32(reg, mtmp, sensor_index, 0x00, 0, 12);9485 9486/* Convert to milli degrees Celsius */9487#define MLXSW_REG_MTMP_TEMP_TO_MC(val) ({ typeof(val) v_ = (val); \9488					  ((v_) >= 0) ? ((v_) * 125) : \9489					  ((s16)((GENMASK(15, 0) + (v_) + 1) \9490					   * 125)); })9491 9492/* reg_mtmp_max_operational_temperature9493 * The highest temperature in the nominal operational range. Reading is in9494 * 0.125 Celsius degrees units.9495 * In case of module this is SFF critical temperature threshold.9496 * Access: RO9497 */9498MLXSW_ITEM32(reg, mtmp, max_operational_temperature, 0x04, 16, 16);9499 9500/* reg_mtmp_temperature9501 * Temperature reading from the sensor. Reading is in 0.125 Celsius9502 * degrees units.9503 * Access: RO9504 */9505MLXSW_ITEM32(reg, mtmp, temperature, 0x04, 0, 16);9506 9507/* reg_mtmp_mte9508 * Max Temperature Enable - enables measuring the max temperature on a sensor.9509 * Access: RW9510 */9511MLXSW_ITEM32(reg, mtmp, mte, 0x08, 31, 1);9512 9513/* reg_mtmp_mtr9514 * Max Temperature Reset - clears the value of the max temperature register.9515 * Access: WO9516 */9517MLXSW_ITEM32(reg, mtmp, mtr, 0x08, 30, 1);9518 9519/* reg_mtmp_max_temperature9520 * The highest measured temperature from the sensor.9521 * When the bit mte is cleared, the field max_temperature is reserved.9522 * Access: RO9523 */9524MLXSW_ITEM32(reg, mtmp, max_temperature, 0x08, 0, 16);9525 9526/* reg_mtmp_tee9527 * Temperature Event Enable.9528 * 0 - Do not generate event9529 * 1 - Generate event9530 * 2 - Generate single event9531 * Access: RW9532 */9533 9534enum mlxsw_reg_mtmp_tee {9535	MLXSW_REG_MTMP_TEE_NO_EVENT,9536	MLXSW_REG_MTMP_TEE_GENERATE_EVENT,9537	MLXSW_REG_MTMP_TEE_GENERATE_SINGLE_EVENT,9538};9539 9540MLXSW_ITEM32(reg, mtmp, tee, 0x0C, 30, 2);9541 9542#define MLXSW_REG_MTMP_THRESH_HI 0x348	/* 105 Celsius */9543 9544/* reg_mtmp_temperature_threshold_hi9545 * High threshold for Temperature Warning Event. In 0.125 Celsius.9546 * Access: RW9547 */9548MLXSW_ITEM32(reg, mtmp, temperature_threshold_hi, 0x0C, 0, 16);9549 9550#define MLXSW_REG_MTMP_HYSTERESIS_TEMP 0x28 /* 5 Celsius */9551/* reg_mtmp_temperature_threshold_lo9552 * Low threshold for Temperature Warning Event. In 0.125 Celsius.9553 * Access: RW9554 */9555MLXSW_ITEM32(reg, mtmp, temperature_threshold_lo, 0x10, 0, 16);9556 9557#define MLXSW_REG_MTMP_SENSOR_NAME_SIZE 89558 9559/* reg_mtmp_sensor_name9560 * Sensor Name9561 * Access: RO9562 */9563MLXSW_ITEM_BUF(reg, mtmp, sensor_name, 0x18, MLXSW_REG_MTMP_SENSOR_NAME_SIZE);9564 9565static inline void mlxsw_reg_mtmp_pack(char *payload, u8 slot_index,9566				       u16 sensor_index, bool max_temp_enable,9567				       bool max_temp_reset)9568{9569	MLXSW_REG_ZERO(mtmp, payload);9570	mlxsw_reg_mtmp_slot_index_set(payload, slot_index);9571	mlxsw_reg_mtmp_sensor_index_set(payload, sensor_index);9572	mlxsw_reg_mtmp_mte_set(payload, max_temp_enable);9573	mlxsw_reg_mtmp_mtr_set(payload, max_temp_reset);9574	mlxsw_reg_mtmp_temperature_threshold_hi_set(payload,9575						    MLXSW_REG_MTMP_THRESH_HI);9576}9577 9578static inline void mlxsw_reg_mtmp_unpack(char *payload, int *p_temp,9579					 int *p_max_temp, int *p_temp_hi,9580					 int *p_max_oper_temp,9581					 char *sensor_name)9582{9583	s16 temp;9584 9585	if (p_temp) {9586		temp = mlxsw_reg_mtmp_temperature_get(payload);9587		*p_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp);9588	}9589	if (p_max_temp) {9590		temp = mlxsw_reg_mtmp_max_temperature_get(payload);9591		*p_max_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp);9592	}9593	if (p_temp_hi) {9594		temp = mlxsw_reg_mtmp_temperature_threshold_hi_get(payload);9595		*p_temp_hi = MLXSW_REG_MTMP_TEMP_TO_MC(temp);9596	}9597	if (p_max_oper_temp) {9598		temp = mlxsw_reg_mtmp_max_operational_temperature_get(payload);9599		*p_max_oper_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp);9600	}9601	if (sensor_name)9602		mlxsw_reg_mtmp_sensor_name_memcpy_from(payload, sensor_name);9603}9604 9605/* MTWE - Management Temperature Warning Event9606 * -------------------------------------------9607 * This register is used for over temperature warning.9608 */9609#define MLXSW_REG_MTWE_ID 0x900B9610#define MLXSW_REG_MTWE_LEN 0x109611 9612MLXSW_REG_DEFINE(mtwe, MLXSW_REG_MTWE_ID, MLXSW_REG_MTWE_LEN);9613 9614/* reg_mtwe_sensor_warning9615 * Bit vector indicating which of the sensor reading is above threshold.9616 * Address 00h bit31 is sensor_warning[127].9617 * Address 0Ch bit0 is sensor_warning[0].9618 * Access: RO9619 */9620MLXSW_ITEM_BIT_ARRAY(reg, mtwe, sensor_warning, 0x0, 0x10, 1);9621 9622/* MTBR - Management Temperature Bulk Register9623 * -------------------------------------------9624 * This register is used for bulk temperature reading.9625 */9626#define MLXSW_REG_MTBR_ID 0x900F9627#define MLXSW_REG_MTBR_BASE_LEN 0x10 /* base length, without records */9628#define MLXSW_REG_MTBR_REC_LEN 0x04 /* record length */9629#define MLXSW_REG_MTBR_REC_MAX_COUNT 19630#define MLXSW_REG_MTBR_LEN (MLXSW_REG_MTBR_BASE_LEN +	\9631			    MLXSW_REG_MTBR_REC_LEN *	\9632			    MLXSW_REG_MTBR_REC_MAX_COUNT)9633 9634MLXSW_REG_DEFINE(mtbr, MLXSW_REG_MTBR_ID, MLXSW_REG_MTBR_LEN);9635 9636/* reg_mtbr_slot_index9637 * Slot index (0: Main board).9638 * Access: Index9639 */9640MLXSW_ITEM32(reg, mtbr, slot_index, 0x00, 16, 4);9641 9642/* reg_mtbr_base_sensor_index9643 * Base sensors index to access (0 - ASIC sensor, 1-63 - ambient sensors,9644 * 64-127 are mapped to the SFP+/QSFP modules sequentially).9645 * Access: Index9646 */9647MLXSW_ITEM32(reg, mtbr, base_sensor_index, 0x00, 0, 12);9648 9649/* reg_mtbr_num_rec9650 * Request: Number of records to read9651 * Response: Number of records read9652 * See above description for more details.9653 * Range 1..2559654 * Access: RW9655 */9656MLXSW_ITEM32(reg, mtbr, num_rec, 0x04, 0, 8);9657 9658/* reg_mtbr_rec_max_temp9659 * The highest measured temperature from the sensor.9660 * When the bit mte is cleared, the field max_temperature is reserved.9661 * Access: RO9662 */9663MLXSW_ITEM32_INDEXED(reg, mtbr, rec_max_temp, MLXSW_REG_MTBR_BASE_LEN, 16,9664		     16, MLXSW_REG_MTBR_REC_LEN, 0x00, false);9665 9666/* reg_mtbr_rec_temp9667 * Temperature reading from the sensor. Reading is in 0..125 Celsius9668 * degrees units.9669 * Access: RO9670 */9671MLXSW_ITEM32_INDEXED(reg, mtbr, rec_temp, MLXSW_REG_MTBR_BASE_LEN, 0, 16,9672		     MLXSW_REG_MTBR_REC_LEN, 0x00, false);9673 9674static inline void mlxsw_reg_mtbr_pack(char *payload, u8 slot_index,9675				       u16 base_sensor_index)9676{9677	MLXSW_REG_ZERO(mtbr, payload);9678	mlxsw_reg_mtbr_slot_index_set(payload, slot_index);9679	mlxsw_reg_mtbr_base_sensor_index_set(payload, base_sensor_index);9680	mlxsw_reg_mtbr_num_rec_set(payload, 1);9681}9682 9683/* Error codes from temperatute reading */9684enum mlxsw_reg_mtbr_temp_status {9685	MLXSW_REG_MTBR_NO_CONN		= 0x8000,9686	MLXSW_REG_MTBR_NO_TEMP_SENS	= 0x8001,9687	MLXSW_REG_MTBR_INDEX_NA		= 0x8002,9688	MLXSW_REG_MTBR_BAD_SENS_INFO	= 0x8003,9689};9690 9691/* Base index for reading modules temperature */9692#define MLXSW_REG_MTBR_BASE_MODULE_INDEX 649693 9694static inline void mlxsw_reg_mtbr_temp_unpack(char *payload, int rec_ind,9695					      u16 *p_temp, u16 *p_max_temp)9696{9697	if (p_temp)9698		*p_temp = mlxsw_reg_mtbr_rec_temp_get(payload, rec_ind);9699	if (p_max_temp)9700		*p_max_temp = mlxsw_reg_mtbr_rec_max_temp_get(payload, rec_ind);9701}9702 9703/* MCIA - Management Cable Info Access9704 * -----------------------------------9705 * MCIA register is used to access the SFP+ and QSFP connector's EPROM.9706 */9707 9708#define MLXSW_REG_MCIA_ID 0x90149709#define MLXSW_REG_MCIA_LEN 0x949710 9711MLXSW_REG_DEFINE(mcia, MLXSW_REG_MCIA_ID, MLXSW_REG_MCIA_LEN);9712 9713/* reg_mcia_module9714 * Module number.9715 * Access: Index9716 */9717MLXSW_ITEM32(reg, mcia, module, 0x00, 16, 8);9718 9719/* reg_mcia_slot_index9720 * Slot index (0: Main board)9721 * Access: Index9722 */9723MLXSW_ITEM32(reg, mcia, slot, 0x00, 12, 4);9724 9725enum {9726	MLXSW_REG_MCIA_STATUS_GOOD = 0,9727	/* No response from module's EEPROM. */9728	MLXSW_REG_MCIA_STATUS_NO_EEPROM_MODULE = 1,9729	/* Module type not supported by the device. */9730	MLXSW_REG_MCIA_STATUS_MODULE_NOT_SUPPORTED = 2,9731	/* No module present indication. */9732	MLXSW_REG_MCIA_STATUS_MODULE_NOT_CONNECTED = 3,9733	/* Error occurred while trying to access module's EEPROM using I2C. */9734	MLXSW_REG_MCIA_STATUS_I2C_ERROR = 9,9735	/* Module is disabled. */9736	MLXSW_REG_MCIA_STATUS_MODULE_DISABLED = 16,9737};9738 9739/* reg_mcia_status9740 * Module status.9741 * Access: RO9742 */9743MLXSW_ITEM32(reg, mcia, status, 0x00, 0, 8);9744 9745/* reg_mcia_i2c_device_address9746 * I2C device address.9747 * Access: RW9748 */9749MLXSW_ITEM32(reg, mcia, i2c_device_address, 0x04, 24, 8);9750 9751/* reg_mcia_page_number9752 * Page number.9753 * Access: RW9754 */9755MLXSW_ITEM32(reg, mcia, page_number, 0x04, 16, 8);9756 9757/* reg_mcia_device_address9758 * Device address.9759 * Access: RW9760 */9761MLXSW_ITEM32(reg, mcia, device_address, 0x04, 0, 16);9762 9763/* reg_mcia_bank_number9764 * Bank number.9765 * Access: Index9766 */9767MLXSW_ITEM32(reg, mcia, bank_number, 0x08, 16, 8);9768 9769/* reg_mcia_size9770 * Number of bytes to read/write (up to 48 bytes).9771 * Access: RW9772 */9773MLXSW_ITEM32(reg, mcia, size, 0x08, 0, 16);9774 9775#define MLXSW_REG_MCIA_EEPROM_PAGE_LENGTH	2569776#define MLXSW_REG_MCIA_EEPROM_UP_PAGE_LENGTH	1289777#define MLXSW_REG_MCIA_I2C_ADDR_LOW		0x509778#define MLXSW_REG_MCIA_I2C_ADDR_HIGH		0x519779#define MLXSW_REG_MCIA_PAGE0_LO_OFF		0xa09780#define MLXSW_REG_MCIA_TH_ITEM_SIZE		29781#define MLXSW_REG_MCIA_TH_PAGE_NUM		39782#define MLXSW_REG_MCIA_TH_PAGE_CMIS_NUM		29783#define MLXSW_REG_MCIA_PAGE0_LO			09784#define MLXSW_REG_MCIA_TH_PAGE_OFF		0x809785#define MLXSW_REG_MCIA_EEPROM_CMIS_FLAT_MEMORY	BIT(7)9786 9787enum mlxsw_reg_mcia_eeprom_module_info_rev_id {9788	MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_UNSPC	= 0x00,9789	MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_8436	= 0x01,9790	MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_8636	= 0x03,9791};9792 9793enum mlxsw_reg_mcia_eeprom_module_info_id {9794	MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_SFP	= 0x03,9795	MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP	= 0x0C,9796	MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP_PLUS	= 0x0D,9797	MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP28	= 0x11,9798	MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP_DD	= 0x18,9799	MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_OSFP	= 0x19,9800};9801 9802enum mlxsw_reg_mcia_eeprom_module_info {9803	MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID,9804	MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID,9805	MLXSW_REG_MCIA_EEPROM_MODULE_INFO_TYPE_ID,9806	MLXSW_REG_MCIA_EEPROM_MODULE_INFO_SIZE,9807};9808 9809/* reg_mcia_eeprom9810 * Bytes to read/write.9811 * Access: RW9812 */9813MLXSW_ITEM_BUF(reg, mcia, eeprom, 0x10, 128);9814 9815/* This is used to access the optional upper pages (1-3) in the QSFP+9816 * memory map. Page 1 is available on offset 256 through 383, page 2 -9817 * on offset 384 through 511, page 3 - on offset 512 through 639.9818 */9819#define MLXSW_REG_MCIA_PAGE_GET(off) (((off) - \9820				MLXSW_REG_MCIA_EEPROM_PAGE_LENGTH) / \9821				MLXSW_REG_MCIA_EEPROM_UP_PAGE_LENGTH + 1)9822 9823static inline void mlxsw_reg_mcia_pack(char *payload, u8 slot_index, u8 module,9824				       u8 page_number, u16 device_addr, u8 size,9825				       u8 i2c_device_addr)9826{9827	MLXSW_REG_ZERO(mcia, payload);9828	mlxsw_reg_mcia_slot_set(payload, slot_index);9829	mlxsw_reg_mcia_module_set(payload, module);9830	mlxsw_reg_mcia_page_number_set(payload, page_number);9831	mlxsw_reg_mcia_device_address_set(payload, device_addr);9832	mlxsw_reg_mcia_size_set(payload, size);9833	mlxsw_reg_mcia_i2c_device_address_set(payload, i2c_device_addr);9834}9835 9836/* MPAT - Monitoring Port Analyzer Table9837 * -------------------------------------9838 * MPAT Register is used to query and configure the Switch PortAnalyzer Table.9839 * For an enabled analyzer, all fields except e (enable) cannot be modified.9840 */9841#define MLXSW_REG_MPAT_ID 0x901A9842#define MLXSW_REG_MPAT_LEN 0x789843 9844MLXSW_REG_DEFINE(mpat, MLXSW_REG_MPAT_ID, MLXSW_REG_MPAT_LEN);9845 9846/* reg_mpat_pa_id9847 * Port Analyzer ID.9848 * Access: Index9849 */9850MLXSW_ITEM32(reg, mpat, pa_id, 0x00, 28, 4);9851 9852/* reg_mpat_session_id9853 * Mirror Session ID.9854 * Used for MIRROR_SESSION<i> trap.9855 * Access: RW9856 */9857MLXSW_ITEM32(reg, mpat, session_id, 0x00, 24, 4);9858 9859/* reg_mpat_system_port9860 * A unique port identifier for the final destination of the packet.9861 * Access: RW9862 */9863MLXSW_ITEM32(reg, mpat, system_port, 0x00, 0, 16);9864 9865/* reg_mpat_e9866 * Enable. Indicating the Port Analyzer is enabled.9867 * Access: RW9868 */9869MLXSW_ITEM32(reg, mpat, e, 0x04, 31, 1);9870 9871/* reg_mpat_qos9872 * Quality Of Service Mode.9873 * 0: CONFIGURED - QoS parameters (Switch Priority, and encapsulation9874 * PCP, DEI, DSCP or VL) are configured.9875 * 1: MAINTAIN - QoS parameters (Switch Priority, Color) are the9876 * same as in the original packet that has triggered the mirroring. For9877 * SPAN also the pcp,dei are maintained.9878 * Access: RW9879 */9880MLXSW_ITEM32(reg, mpat, qos, 0x04, 26, 1);9881 9882/* reg_mpat_be9883 * Best effort mode. Indicates mirroring traffic should not cause packet9884 * drop or back pressure, but will discard the mirrored packets. Mirrored9885 * packets will be forwarded on a best effort manner.9886 * 0: Do not discard mirrored packets9887 * 1: Discard mirrored packets if causing congestion9888 * Access: RW9889 */9890MLXSW_ITEM32(reg, mpat, be, 0x04, 25, 1);9891 9892enum mlxsw_reg_mpat_span_type {9893	/* Local SPAN Ethernet.9894	 * The original packet is not encapsulated.9895	 */9896	MLXSW_REG_MPAT_SPAN_TYPE_LOCAL_ETH = 0x0,9897 9898	/* Remote SPAN Ethernet VLAN.9899	 * The packet is forwarded to the monitoring port on the monitoring9900	 * VLAN.9901	 */9902	MLXSW_REG_MPAT_SPAN_TYPE_REMOTE_ETH = 0x1,9903 9904	/* Encapsulated Remote SPAN Ethernet L3 GRE.9905	 * The packet is encapsulated with GRE header.9906	 */9907	MLXSW_REG_MPAT_SPAN_TYPE_REMOTE_ETH_L3 = 0x3,9908};9909 9910/* reg_mpat_span_type9911 * SPAN type.9912 * Access: RW9913 */9914MLXSW_ITEM32(reg, mpat, span_type, 0x04, 0, 4);9915 9916/* reg_mpat_pide9917 * Policer enable.9918 * Access: RW9919 */9920MLXSW_ITEM32(reg, mpat, pide, 0x0C, 15, 1);9921 9922/* reg_mpat_pid9923 * Policer ID.9924 * Access: RW9925 */9926MLXSW_ITEM32(reg, mpat, pid, 0x0C, 0, 14);9927 9928/* Remote SPAN - Ethernet VLAN9929 * - - - - - - - - - - - - - -9930 */9931 9932/* reg_mpat_eth_rspan_vid9933 * Encapsulation header VLAN ID.9934 * Access: RW9935 */9936MLXSW_ITEM32(reg, mpat, eth_rspan_vid, 0x18, 0, 12);9937 9938/* Encapsulated Remote SPAN - Ethernet L29939 * - - - - - - - - - - - - - - - - - - -9940 */9941 9942enum mlxsw_reg_mpat_eth_rspan_version {9943	MLXSW_REG_MPAT_ETH_RSPAN_VERSION_NO_HEADER = 15,9944};9945 9946/* reg_mpat_eth_rspan_version9947 * RSPAN mirror header version.9948 * Access: RW9949 */9950MLXSW_ITEM32(reg, mpat, eth_rspan_version, 0x10, 18, 4);9951 9952/* reg_mpat_eth_rspan_mac9953 * Destination MAC address.9954 * Access: RW9955 */9956MLXSW_ITEM_BUF(reg, mpat, eth_rspan_mac, 0x12, 6);9957 9958/* reg_mpat_eth_rspan_tp9959 * Tag Packet. Indicates whether the mirroring header should be VLAN tagged.9960 * Access: RW9961 */9962MLXSW_ITEM32(reg, mpat, eth_rspan_tp, 0x18, 16, 1);9963 9964/* Encapsulated Remote SPAN - Ethernet L39965 * - - - - - - - - - - - - - - - - - - -9966 */9967 9968enum mlxsw_reg_mpat_eth_rspan_protocol {9969	MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV4,9970	MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV6,9971};9972 9973/* reg_mpat_eth_rspan_protocol9974 * SPAN encapsulation protocol.9975 * Access: RW9976 */9977MLXSW_ITEM32(reg, mpat, eth_rspan_protocol, 0x18, 24, 4);9978 9979/* reg_mpat_eth_rspan_ttl9980 * Encapsulation header Time-to-Live/HopLimit.9981 * Access: RW9982 */9983MLXSW_ITEM32(reg, mpat, eth_rspan_ttl, 0x1C, 4, 8);9984 9985/* reg_mpat_eth_rspan_smac9986 * Source MAC address9987 * Access: RW9988 */9989MLXSW_ITEM_BUF(reg, mpat, eth_rspan_smac, 0x22, 6);9990 9991/* reg_mpat_eth_rspan_dip*9992 * Destination IP address. The IP version is configured by protocol.9993 * Access: RW9994 */9995MLXSW_ITEM32(reg, mpat, eth_rspan_dip4, 0x4C, 0, 32);9996MLXSW_ITEM_BUF(reg, mpat, eth_rspan_dip6, 0x40, 16);9997 9998/* reg_mpat_eth_rspan_sip*9999 * Source IP address. The IP version is configured by protocol.10000 * Access: RW10001 */10002MLXSW_ITEM32(reg, mpat, eth_rspan_sip4, 0x5C, 0, 32);10003MLXSW_ITEM_BUF(reg, mpat, eth_rspan_sip6, 0x50, 16);10004 10005static inline void mlxsw_reg_mpat_pack(char *payload, u8 pa_id,10006				       u16 system_port, bool e,10007				       enum mlxsw_reg_mpat_span_type span_type)10008{10009	MLXSW_REG_ZERO(mpat, payload);10010	mlxsw_reg_mpat_pa_id_set(payload, pa_id);10011	mlxsw_reg_mpat_system_port_set(payload, system_port);10012	mlxsw_reg_mpat_e_set(payload, e);10013	mlxsw_reg_mpat_qos_set(payload, 1);10014	mlxsw_reg_mpat_be_set(payload, 1);10015	mlxsw_reg_mpat_span_type_set(payload, span_type);10016}10017 10018static inline void mlxsw_reg_mpat_eth_rspan_pack(char *payload, u16 vid)10019{10020	mlxsw_reg_mpat_eth_rspan_vid_set(payload, vid);10021}10022 10023static inline void10024mlxsw_reg_mpat_eth_rspan_l2_pack(char *payload,10025				 enum mlxsw_reg_mpat_eth_rspan_version version,10026				 const char *mac,10027				 bool tp)10028{10029	mlxsw_reg_mpat_eth_rspan_version_set(payload, version);10030	mlxsw_reg_mpat_eth_rspan_mac_memcpy_to(payload, mac);10031	mlxsw_reg_mpat_eth_rspan_tp_set(payload, tp);10032}10033 10034static inline void10035mlxsw_reg_mpat_eth_rspan_l3_ipv4_pack(char *payload, u8 ttl,10036				      const char *smac,10037				      u32 sip, u32 dip)10038{10039	mlxsw_reg_mpat_eth_rspan_ttl_set(payload, ttl);10040	mlxsw_reg_mpat_eth_rspan_smac_memcpy_to(payload, smac);10041	mlxsw_reg_mpat_eth_rspan_protocol_set(payload,10042				    MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV4);10043	mlxsw_reg_mpat_eth_rspan_sip4_set(payload, sip);10044	mlxsw_reg_mpat_eth_rspan_dip4_set(payload, dip);10045}10046 10047static inline void10048mlxsw_reg_mpat_eth_rspan_l3_ipv6_pack(char *payload, u8 ttl,10049				      const char *smac,10050				      struct in6_addr sip, struct in6_addr dip)10051{10052	mlxsw_reg_mpat_eth_rspan_ttl_set(payload, ttl);10053	mlxsw_reg_mpat_eth_rspan_smac_memcpy_to(payload, smac);10054	mlxsw_reg_mpat_eth_rspan_protocol_set(payload,10055				    MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV6);10056	mlxsw_reg_mpat_eth_rspan_sip6_memcpy_to(payload, (void *)&sip);10057	mlxsw_reg_mpat_eth_rspan_dip6_memcpy_to(payload, (void *)&dip);10058}10059 10060/* MPAR - Monitoring Port Analyzer Register10061 * ----------------------------------------10062 * MPAR register is used to query and configure the port analyzer port mirroring10063 * properties.10064 */10065#define MLXSW_REG_MPAR_ID 0x901B10066#define MLXSW_REG_MPAR_LEN 0x0C10067 10068MLXSW_REG_DEFINE(mpar, MLXSW_REG_MPAR_ID, MLXSW_REG_MPAR_LEN);10069 10070/* reg_mpar_local_port10071 * The local port to mirror the packets from.10072 * Access: Index10073 */10074MLXSW_ITEM32_LP(reg, mpar, 0x00, 16, 0x00, 4);10075 10076enum mlxsw_reg_mpar_i_e {10077	MLXSW_REG_MPAR_TYPE_EGRESS,10078	MLXSW_REG_MPAR_TYPE_INGRESS,10079};10080 10081/* reg_mpar_i_e10082 * Ingress/Egress10083 * Access: Index10084 */10085MLXSW_ITEM32(reg, mpar, i_e, 0x00, 0, 4);10086 10087/* reg_mpar_enable10088 * Enable mirroring10089 * By default, port mirroring is disabled for all ports.10090 * Access: RW10091 */10092MLXSW_ITEM32(reg, mpar, enable, 0x04, 31, 1);10093 10094/* reg_mpar_pa_id10095 * Port Analyzer ID.10096 * Access: RW10097 */10098MLXSW_ITEM32(reg, mpar, pa_id, 0x04, 0, 4);10099 10100#define MLXSW_REG_MPAR_RATE_MAX 3500000000UL10101 10102/* reg_mpar_probability_rate10103 * Sampling rate.10104 * Valid values are: 1 to 3.5*10^910105 * Value of 1 means "sample all". Default is 1.10106 * Reserved when Spectrum-1.10107 * Access: RW10108 */10109MLXSW_ITEM32(reg, mpar, probability_rate, 0x08, 0, 32);10110 10111static inline void mlxsw_reg_mpar_pack(char *payload, u16 local_port,10112				       enum mlxsw_reg_mpar_i_e i_e,10113				       bool enable, u8 pa_id,10114				       u32 probability_rate)10115{10116	MLXSW_REG_ZERO(mpar, payload);10117	mlxsw_reg_mpar_local_port_set(payload, local_port);10118	mlxsw_reg_mpar_enable_set(payload, enable);10119	mlxsw_reg_mpar_i_e_set(payload, i_e);10120	mlxsw_reg_mpar_pa_id_set(payload, pa_id);10121	mlxsw_reg_mpar_probability_rate_set(payload, probability_rate);10122}10123 10124/* MGIR - Management General Information Register10125 * ----------------------------------------------10126 * MGIR register allows software to query the hardware and firmware general10127 * information.10128 */10129#define MLXSW_REG_MGIR_ID 0x902010130#define MLXSW_REG_MGIR_LEN 0x9C10131 10132MLXSW_REG_DEFINE(mgir, MLXSW_REG_MGIR_ID, MLXSW_REG_MGIR_LEN);10133 10134/* reg_mgir_hw_info_device_hw_revision10135 * Access: RO10136 */10137MLXSW_ITEM32(reg, mgir, hw_info_device_hw_revision, 0x0, 16, 16);10138 10139/* reg_mgir_fw_info_latency_tlv10140 * When set, latency-TLV is supported.10141 * Access: RO10142 */10143MLXSW_ITEM32(reg, mgir, fw_info_latency_tlv, 0x20, 29, 1);10144 10145/* reg_mgir_fw_info_string_tlv10146 * When set, string-TLV is supported.10147 * Access: RO10148 */10149MLXSW_ITEM32(reg, mgir, fw_info_string_tlv, 0x20, 28, 1);10150 10151#define MLXSW_REG_MGIR_FW_INFO_PSID_SIZE 1610152 10153/* reg_mgir_fw_info_psid10154 * PSID (ASCII string).10155 * Access: RO10156 */10157MLXSW_ITEM_BUF(reg, mgir, fw_info_psid, 0x30, MLXSW_REG_MGIR_FW_INFO_PSID_SIZE);10158 10159/* reg_mgir_fw_info_extended_major10160 * Access: RO10161 */10162MLXSW_ITEM32(reg, mgir, fw_info_extended_major, 0x44, 0, 32);10163 10164/* reg_mgir_fw_info_extended_minor10165 * Access: RO10166 */10167MLXSW_ITEM32(reg, mgir, fw_info_extended_minor, 0x48, 0, 32);10168 10169/* reg_mgir_fw_info_extended_sub_minor10170 * Access: RO10171 */10172MLXSW_ITEM32(reg, mgir, fw_info_extended_sub_minor, 0x4C, 0, 32);10173 10174static inline void mlxsw_reg_mgir_pack(char *payload)10175{10176	MLXSW_REG_ZERO(mgir, payload);10177}10178 10179static inline void10180mlxsw_reg_mgir_unpack(char *payload, u32 *hw_rev, char *fw_info_psid,10181		      u32 *fw_major, u32 *fw_minor, u32 *fw_sub_minor)10182{10183	*hw_rev = mlxsw_reg_mgir_hw_info_device_hw_revision_get(payload);10184	mlxsw_reg_mgir_fw_info_psid_memcpy_from(payload, fw_info_psid);10185	*fw_major = mlxsw_reg_mgir_fw_info_extended_major_get(payload);10186	*fw_minor = mlxsw_reg_mgir_fw_info_extended_minor_get(payload);10187	*fw_sub_minor = mlxsw_reg_mgir_fw_info_extended_sub_minor_get(payload);10188}10189 10190/* MRSR - Management Reset and Shutdown Register10191 * ---------------------------------------------10192 * MRSR register is used to reset or shutdown the switch or10193 * the entire system (when applicable).10194 */10195#define MLXSW_REG_MRSR_ID 0x902310196#define MLXSW_REG_MRSR_LEN 0x0810197 10198MLXSW_REG_DEFINE(mrsr, MLXSW_REG_MRSR_ID, MLXSW_REG_MRSR_LEN);10199 10200enum mlxsw_reg_mrsr_command {10201	/* Switch soft reset, does not reset PCI firmware. */10202	MLXSW_REG_MRSR_COMMAND_SOFTWARE_RESET = 1,10203	/* Reset will be done when PCI link will be disabled.10204	 * This command will reset PCI firmware also.10205	 */10206	MLXSW_REG_MRSR_COMMAND_RESET_AT_PCI_DISABLE = 6,10207};10208 10209/* reg_mrsr_command10210 * Reset/shutdown command10211 * 0 - do nothing10212 * 1 - software reset10213 * Access: WO10214 */10215MLXSW_ITEM32(reg, mrsr, command, 0x00, 0, 4);10216 10217static inline void mlxsw_reg_mrsr_pack(char *payload,10218				       enum mlxsw_reg_mrsr_command command)10219{10220	MLXSW_REG_ZERO(mrsr, payload);10221	mlxsw_reg_mrsr_command_set(payload, command);10222}10223 10224/* MLCR - Management LED Control Register10225 * --------------------------------------10226 * Controls the system LEDs.10227 */10228#define MLXSW_REG_MLCR_ID 0x902B10229#define MLXSW_REG_MLCR_LEN 0x0C10230 10231MLXSW_REG_DEFINE(mlcr, MLXSW_REG_MLCR_ID, MLXSW_REG_MLCR_LEN);10232 10233/* reg_mlcr_local_port10234 * Local port number.10235 * Access: RW10236 */10237MLXSW_ITEM32_LP(reg, mlcr, 0x00, 16, 0x00, 24);10238 10239#define MLXSW_REG_MLCR_DURATION_MAX 0xFFFF10240 10241/* reg_mlcr_beacon_duration10242 * Duration of the beacon to be active, in seconds.10243 * 0x0 - Will turn off the beacon.10244 * 0xFFFF - Will turn on the beacon until explicitly turned off.10245 * Access: RW10246 */10247MLXSW_ITEM32(reg, mlcr, beacon_duration, 0x04, 0, 16);10248 10249/* reg_mlcr_beacon_remain10250 * Remaining duration of the beacon, in seconds.10251 * 0xFFFF indicates an infinite amount of time.10252 * Access: RO10253 */10254MLXSW_ITEM32(reg, mlcr, beacon_remain, 0x08, 0, 16);10255 10256static inline void mlxsw_reg_mlcr_pack(char *payload, u16 local_port,10257				       bool active)10258{10259	MLXSW_REG_ZERO(mlcr, payload);10260	mlxsw_reg_mlcr_local_port_set(payload, local_port);10261	mlxsw_reg_mlcr_beacon_duration_set(payload, active ?10262					   MLXSW_REG_MLCR_DURATION_MAX : 0);10263}10264 10265/* MCION - Management Cable IO and Notifications Register10266 * ------------------------------------------------------10267 * The MCION register is used to query transceiver modules' IO pins and other10268 * notifications.10269 */10270#define MLXSW_REG_MCION_ID 0x905210271#define MLXSW_REG_MCION_LEN 0x1810272 10273MLXSW_REG_DEFINE(mcion, MLXSW_REG_MCION_ID, MLXSW_REG_MCION_LEN);10274 10275/* reg_mcion_module10276 * Module number.10277 * Access: Index10278 */10279MLXSW_ITEM32(reg, mcion, module, 0x00, 16, 8);10280 10281/* reg_mcion_slot_index10282 * Slot index.10283 * Access: Index10284 */10285MLXSW_ITEM32(reg, mcion, slot_index, 0x00, 12, 4);10286 10287enum {10288	MLXSW_REG_MCION_MODULE_STATUS_BITS_PRESENT_MASK = BIT(0),10289	MLXSW_REG_MCION_MODULE_STATUS_BITS_LOW_POWER_MASK = BIT(8),10290};10291 10292/* reg_mcion_module_status_bits10293 * Module IO status as defined by SFF.10294 * Access: RO10295 */10296MLXSW_ITEM32(reg, mcion, module_status_bits, 0x04, 0, 16);10297 10298static inline void mlxsw_reg_mcion_pack(char *payload, u8 slot_index, u8 module)10299{10300	MLXSW_REG_ZERO(mcion, payload);10301	mlxsw_reg_mcion_slot_index_set(payload, slot_index);10302	mlxsw_reg_mcion_module_set(payload, module);10303}10304 10305/* MTPPS - Management Pulse Per Second Register10306 * --------------------------------------------10307 * This register provides the device PPS capabilities, configure the PPS in and10308 * out modules and holds the PPS in time stamp.10309 */10310#define MLXSW_REG_MTPPS_ID 0x905310311#define MLXSW_REG_MTPPS_LEN 0x3C10312 10313MLXSW_REG_DEFINE(mtpps, MLXSW_REG_MTPPS_ID, MLXSW_REG_MTPPS_LEN);10314 10315/* reg_mtpps_enable10316 * Enables the PPS functionality the specific pin.10317 * A boolean variable.10318 * Access: RW10319 */10320MLXSW_ITEM32(reg, mtpps, enable, 0x20, 31, 1);10321 10322enum mlxsw_reg_mtpps_pin_mode {10323	MLXSW_REG_MTPPS_PIN_MODE_VIRTUAL_PIN = 0x2,10324};10325 10326/* reg_mtpps_pin_mode10327 * Pin mode to be used. The mode must comply with the supported modes of the10328 * requested pin.10329 * Access: RW10330 */10331MLXSW_ITEM32(reg, mtpps, pin_mode, 0x20, 8, 4);10332 10333#define MLXSW_REG_MTPPS_PIN_SP_VIRTUAL_PIN	710334 10335/* reg_mtpps_pin10336 * Pin to be configured or queried out of the supported pins.10337 * Access: Index10338 */10339MLXSW_ITEM32(reg, mtpps, pin, 0x20, 0, 8);10340 10341/* reg_mtpps_time_stamp10342 * When pin_mode = pps_in, the latched device time when it was triggered from10343 * the external GPIO pin.10344 * When pin_mode = pps_out or virtual_pin or pps_out_and_virtual_pin, the target10345 * time to generate next output signal.10346 * Time is in units of device clock.10347 * Access: RW10348 */10349MLXSW_ITEM64(reg, mtpps, time_stamp, 0x28, 0, 64);10350 10351static inline void10352mlxsw_reg_mtpps_vpin_pack(char *payload, u64 time_stamp)10353{10354	MLXSW_REG_ZERO(mtpps, payload);10355	mlxsw_reg_mtpps_pin_set(payload, MLXSW_REG_MTPPS_PIN_SP_VIRTUAL_PIN);10356	mlxsw_reg_mtpps_pin_mode_set(payload,10357				     MLXSW_REG_MTPPS_PIN_MODE_VIRTUAL_PIN);10358	mlxsw_reg_mtpps_enable_set(payload, true);10359	mlxsw_reg_mtpps_time_stamp_set(payload, time_stamp);10360}10361 10362/* MTUTC - Management UTC Register10363 * -------------------------------10364 * Configures the HW UTC counter.10365 */10366#define MLXSW_REG_MTUTC_ID 0x905510367#define MLXSW_REG_MTUTC_LEN 0x1C10368 10369MLXSW_REG_DEFINE(mtutc, MLXSW_REG_MTUTC_ID, MLXSW_REG_MTUTC_LEN);10370 10371enum mlxsw_reg_mtutc_operation {10372	MLXSW_REG_MTUTC_OPERATION_SET_TIME_AT_NEXT_SEC = 0,10373	MLXSW_REG_MTUTC_OPERATION_SET_TIME_IMMEDIATE = 1,10374	MLXSW_REG_MTUTC_OPERATION_ADJUST_TIME = 2,10375	MLXSW_REG_MTUTC_OPERATION_ADJUST_FREQ = 3,10376};10377 10378/* reg_mtutc_operation10379 * Operation.10380 * Access: OP10381 */10382MLXSW_ITEM32(reg, mtutc, operation, 0x00, 0, 4);10383 10384/* reg_mtutc_freq_adjustment10385 * Frequency adjustment: Every PPS the HW frequency will be10386 * adjusted by this value. Units of HW clock, where HW counts10387 * 10^9 HW clocks for 1 HW second. Range is from -50,000,000 to +50,000,000.10388 * In Spectrum-2, the field is reversed, positive values mean to decrease the10389 * frequency.10390 * Access: RW10391 */10392MLXSW_ITEM32(reg, mtutc, freq_adjustment, 0x04, 0, 32);10393 10394#define MLXSW_REG_MTUTC_MAX_FREQ_ADJ (50 * 1000 * 1000)10395 10396/* reg_mtutc_utc_sec10397 * UTC seconds.10398 * Access: WO10399 */10400MLXSW_ITEM32(reg, mtutc, utc_sec, 0x10, 0, 32);10401 10402/* reg_mtutc_utc_nsec10403 * UTC nSecs.10404 * Range 0..(10^9-1)10405 * Updated when operation is SET_TIME_IMMEDIATE.10406 * Reserved on Spectrum-1.10407 * Access: WO10408 */10409MLXSW_ITEM32(reg, mtutc, utc_nsec, 0x14, 0, 30);10410 10411/* reg_mtutc_time_adjustment10412 * Time adjustment.10413 * Units of nSec.10414 * Range is from -32768 to +32767.10415 * Updated when operation is ADJUST_TIME.10416 * Reserved on Spectrum-1.10417 * Access: WO10418 */10419MLXSW_ITEM32(reg, mtutc, time_adjustment, 0x18, 0, 32);10420 10421static inline void10422mlxsw_reg_mtutc_pack(char *payload, enum mlxsw_reg_mtutc_operation oper,10423		     u32 freq_adj, u32 utc_sec, u32 utc_nsec, u32 time_adj)10424{10425	MLXSW_REG_ZERO(mtutc, payload);10426	mlxsw_reg_mtutc_operation_set(payload, oper);10427	mlxsw_reg_mtutc_freq_adjustment_set(payload, freq_adj);10428	mlxsw_reg_mtutc_utc_sec_set(payload, utc_sec);10429	mlxsw_reg_mtutc_utc_nsec_set(payload, utc_nsec);10430	mlxsw_reg_mtutc_time_adjustment_set(payload, time_adj);10431}10432 10433/* MCQI - Management Component Query Information10434 * ---------------------------------------------10435 * This register allows querying information about firmware components.10436 */10437#define MLXSW_REG_MCQI_ID 0x906110438#define MLXSW_REG_MCQI_BASE_LEN 0x1810439#define MLXSW_REG_MCQI_CAP_LEN 0x1410440#define MLXSW_REG_MCQI_LEN (MLXSW_REG_MCQI_BASE_LEN + MLXSW_REG_MCQI_CAP_LEN)10441 10442MLXSW_REG_DEFINE(mcqi, MLXSW_REG_MCQI_ID, MLXSW_REG_MCQI_LEN);10443 10444/* reg_mcqi_component_index10445 * Index of the accessed component.10446 * Access: Index10447 */10448MLXSW_ITEM32(reg, mcqi, component_index, 0x00, 0, 16);10449 10450enum mlxfw_reg_mcqi_info_type {10451	MLXSW_REG_MCQI_INFO_TYPE_CAPABILITIES,10452};10453 10454/* reg_mcqi_info_type10455 * Component properties set.10456 * Access: RW10457 */10458MLXSW_ITEM32(reg, mcqi, info_type, 0x08, 0, 5);10459 10460/* reg_mcqi_offset10461 * The requested/returned data offset from the section start, given in bytes.10462 * Must be DWORD aligned.10463 * Access: RW10464 */10465MLXSW_ITEM32(reg, mcqi, offset, 0x10, 0, 32);10466 10467/* reg_mcqi_data_size10468 * The requested/returned data size, given in bytes. If data_size is not DWORD10469 * aligned, the last bytes are zero padded.10470 * Access: RW10471 */10472MLXSW_ITEM32(reg, mcqi, data_size, 0x14, 0, 16);10473 10474/* reg_mcqi_cap_max_component_size10475 * Maximum size for this component, given in bytes.10476 * Access: RO10477 */10478MLXSW_ITEM32(reg, mcqi, cap_max_component_size, 0x20, 0, 32);10479 10480/* reg_mcqi_cap_log_mcda_word_size10481 * Log 2 of the access word size in bytes. Read and write access must be aligned10482 * to the word size. Write access must be done for an integer number of words.10483 * Access: RO10484 */10485MLXSW_ITEM32(reg, mcqi, cap_log_mcda_word_size, 0x24, 28, 4);10486 10487/* reg_mcqi_cap_mcda_max_write_size10488 * Maximal write size for MCDA register10489 * Access: RO10490 */10491MLXSW_ITEM32(reg, mcqi, cap_mcda_max_write_size, 0x24, 0, 16);10492 10493static inline void mlxsw_reg_mcqi_pack(char *payload, u16 component_index)10494{10495	MLXSW_REG_ZERO(mcqi, payload);10496	mlxsw_reg_mcqi_component_index_set(payload, component_index);10497	mlxsw_reg_mcqi_info_type_set(payload,10498				     MLXSW_REG_MCQI_INFO_TYPE_CAPABILITIES);10499	mlxsw_reg_mcqi_offset_set(payload, 0);10500	mlxsw_reg_mcqi_data_size_set(payload, MLXSW_REG_MCQI_CAP_LEN);10501}10502 10503static inline void mlxsw_reg_mcqi_unpack(char *payload,10504					 u32 *p_cap_max_component_size,10505					 u8 *p_cap_log_mcda_word_size,10506					 u16 *p_cap_mcda_max_write_size)10507{10508	*p_cap_max_component_size =10509		mlxsw_reg_mcqi_cap_max_component_size_get(payload);10510	*p_cap_log_mcda_word_size =10511		mlxsw_reg_mcqi_cap_log_mcda_word_size_get(payload);10512	*p_cap_mcda_max_write_size =10513		mlxsw_reg_mcqi_cap_mcda_max_write_size_get(payload);10514}10515 10516/* MCC - Management Component Control10517 * ----------------------------------10518 * Controls the firmware component and updates the FSM.10519 */10520#define MLXSW_REG_MCC_ID 0x906210521#define MLXSW_REG_MCC_LEN 0x1C10522 10523MLXSW_REG_DEFINE(mcc, MLXSW_REG_MCC_ID, MLXSW_REG_MCC_LEN);10524 10525enum mlxsw_reg_mcc_instruction {10526	MLXSW_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE = 0x01,10527	MLXSW_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE = 0x02,10528	MLXSW_REG_MCC_INSTRUCTION_UPDATE_COMPONENT = 0x03,10529	MLXSW_REG_MCC_INSTRUCTION_VERIFY_COMPONENT = 0x04,10530	MLXSW_REG_MCC_INSTRUCTION_ACTIVATE = 0x06,10531	MLXSW_REG_MCC_INSTRUCTION_CANCEL = 0x08,10532};10533 10534/* reg_mcc_instruction10535 * Command to be executed by the FSM.10536 * Applicable for write operation only.10537 * Access: RW10538 */10539MLXSW_ITEM32(reg, mcc, instruction, 0x00, 0, 8);10540 10541/* reg_mcc_component_index10542 * Index of the accessed component. Applicable only for commands that10543 * refer to components. Otherwise, this field is reserved.10544 * Access: Index10545 */10546MLXSW_ITEM32(reg, mcc, component_index, 0x04, 0, 16);10547 10548/* reg_mcc_update_handle10549 * Token representing the current flow executed by the FSM.10550 * Access: WO10551 */10552MLXSW_ITEM32(reg, mcc, update_handle, 0x08, 0, 24);10553 10554/* reg_mcc_error_code10555 * Indicates the successful completion of the instruction, or the reason it10556 * failed10557 * Access: RO10558 */10559MLXSW_ITEM32(reg, mcc, error_code, 0x0C, 8, 8);10560 10561/* reg_mcc_control_state10562 * Current FSM state10563 * Access: RO10564 */10565MLXSW_ITEM32(reg, mcc, control_state, 0x0C, 0, 4);10566 10567/* reg_mcc_component_size10568 * Component size in bytes. Valid for UPDATE_COMPONENT instruction. Specifying10569 * the size may shorten the update time. Value 0x0 means that size is10570 * unspecified.10571 * Access: WO10572 */10573MLXSW_ITEM32(reg, mcc, component_size, 0x10, 0, 32);10574 10575static inline void mlxsw_reg_mcc_pack(char *payload,10576				      enum mlxsw_reg_mcc_instruction instr,10577				      u16 component_index, u32 update_handle,10578				      u32 component_size)10579{10580	MLXSW_REG_ZERO(mcc, payload);10581	mlxsw_reg_mcc_instruction_set(payload, instr);10582	mlxsw_reg_mcc_component_index_set(payload, component_index);10583	mlxsw_reg_mcc_update_handle_set(payload, update_handle);10584	mlxsw_reg_mcc_component_size_set(payload, component_size);10585}10586 10587static inline void mlxsw_reg_mcc_unpack(char *payload, u32 *p_update_handle,10588					u8 *p_error_code, u8 *p_control_state)10589{10590	if (p_update_handle)10591		*p_update_handle = mlxsw_reg_mcc_update_handle_get(payload);10592	if (p_error_code)10593		*p_error_code = mlxsw_reg_mcc_error_code_get(payload);10594	if (p_control_state)10595		*p_control_state = mlxsw_reg_mcc_control_state_get(payload);10596}10597 10598/* MCDA - Management Component Data Access10599 * ---------------------------------------10600 * This register allows reading and writing a firmware component.10601 */10602#define MLXSW_REG_MCDA_ID 0x906310603#define MLXSW_REG_MCDA_BASE_LEN 0x1010604#define MLXSW_REG_MCDA_MAX_DATA_LEN 0x8010605#define MLXSW_REG_MCDA_LEN \10606		(MLXSW_REG_MCDA_BASE_LEN + MLXSW_REG_MCDA_MAX_DATA_LEN)10607 10608MLXSW_REG_DEFINE(mcda, MLXSW_REG_MCDA_ID, MLXSW_REG_MCDA_LEN);10609 10610/* reg_mcda_update_handle10611 * Token representing the current flow executed by the FSM.10612 * Access: RW10613 */10614MLXSW_ITEM32(reg, mcda, update_handle, 0x00, 0, 24);10615 10616/* reg_mcda_offset10617 * Offset of accessed address relative to component start. Accesses must be in10618 * accordance to log_mcda_word_size in MCQI reg.10619 * Access: RW10620 */10621MLXSW_ITEM32(reg, mcda, offset, 0x04, 0, 32);10622 10623/* reg_mcda_size10624 * Size of the data accessed, given in bytes.10625 * Access: RW10626 */10627MLXSW_ITEM32(reg, mcda, size, 0x08, 0, 16);10628 10629/* reg_mcda_data10630 * Data block accessed.10631 * Access: RW10632 */10633MLXSW_ITEM32_INDEXED(reg, mcda, data, 0x10, 0, 32, 4, 0, false);10634 10635static inline void mlxsw_reg_mcda_pack(char *payload, u32 update_handle,10636				       u32 offset, u16 size, u8 *data)10637{10638	int i;10639 10640	MLXSW_REG_ZERO(mcda, payload);10641	mlxsw_reg_mcda_update_handle_set(payload, update_handle);10642	mlxsw_reg_mcda_offset_set(payload, offset);10643	mlxsw_reg_mcda_size_set(payload, size);10644 10645	for (i = 0; i < size / 4; i++)10646		mlxsw_reg_mcda_data_set(payload, i, *(u32 *) &data[i * 4]);10647}10648 10649/* MCAM - Management Capabilities Mask Register10650 * --------------------------------------------10651 * Reports the device supported management features.10652 */10653#define MLXSW_REG_MCAM_ID 0x907F10654#define MLXSW_REG_MCAM_LEN 0x4810655 10656MLXSW_REG_DEFINE(mcam, MLXSW_REG_MCAM_ID, MLXSW_REG_MCAM_LEN);10657 10658enum mlxsw_reg_mcam_feature_group {10659	/* Enhanced features. */10660	MLXSW_REG_MCAM_FEATURE_GROUP_ENHANCED_FEATURES,10661};10662 10663/* reg_mcam_feature_group10664 * Feature list mask index.10665 * Access: Index10666 */10667MLXSW_ITEM32(reg, mcam, feature_group, 0x00, 16, 8);10668 10669enum mlxsw_reg_mcam_mng_feature_cap_mask_bits {10670	/* If set, MCIA supports 128 bytes payloads. Otherwise, 48 bytes. */10671	MLXSW_REG_MCAM_MCIA_128B = 34,10672	/* If set, MRSR.command=6 is supported. */10673	MLXSW_REG_MCAM_PCI_RESET = 48,10674	/* If set, MRSR.command=6 is supported with Secondary Bus Reset. */10675	MLXSW_REG_MCAM_PCI_RESET_SBR = 67,10676};10677 10678#define MLXSW_REG_BYTES_PER_DWORD 0x410679 10680/* reg_mcam_mng_feature_cap_mask10681 * Supported port's enhanced features.10682 * Based on feature_group index.10683 * When bit is set, the feature is supported in the device.10684 * Access: RO10685 */10686#define MLXSW_REG_MCAM_MNG_FEATURE_CAP_MASK_DWORD(_dw_num, _offset)	 \10687	MLXSW_ITEM_BIT_ARRAY(reg, mcam, mng_feature_cap_mask_dw##_dw_num, \10688			     _offset, MLXSW_REG_BYTES_PER_DWORD, 1)10689 10690/* The access to the bits in the field 'mng_feature_cap_mask' is not same to10691 * other mask fields in other registers. In most of the cases bit #0 is the10692 * first one in the last dword. In MCAM register, the first dword contains bits10693 * #0-#31 and so on, so the access to the bits is simpler using bit array per10694 * dword. Declare each dword of 'mng_feature_cap_mask' field separately.10695 */10696MLXSW_REG_MCAM_MNG_FEATURE_CAP_MASK_DWORD(0, 0x28);10697MLXSW_REG_MCAM_MNG_FEATURE_CAP_MASK_DWORD(1, 0x2C);10698MLXSW_REG_MCAM_MNG_FEATURE_CAP_MASK_DWORD(2, 0x30);10699MLXSW_REG_MCAM_MNG_FEATURE_CAP_MASK_DWORD(3, 0x34);10700 10701static inline void10702mlxsw_reg_mcam_pack(char *payload, enum mlxsw_reg_mcam_feature_group feat_group)10703{10704	MLXSW_REG_ZERO(mcam, payload);10705	mlxsw_reg_mcam_feature_group_set(payload, feat_group);10706}10707 10708static inline void10709mlxsw_reg_mcam_unpack(char *payload,10710		      enum mlxsw_reg_mcam_mng_feature_cap_mask_bits bit,10711		      bool *p_mng_feature_cap_val)10712{10713	int offset = bit % (MLXSW_REG_BYTES_PER_DWORD * BITS_PER_BYTE);10714	int dword = bit / (MLXSW_REG_BYTES_PER_DWORD * BITS_PER_BYTE);10715	u8 (*getters[])(const char *, u16) = {10716		mlxsw_reg_mcam_mng_feature_cap_mask_dw0_get,10717		mlxsw_reg_mcam_mng_feature_cap_mask_dw1_get,10718		mlxsw_reg_mcam_mng_feature_cap_mask_dw2_get,10719		mlxsw_reg_mcam_mng_feature_cap_mask_dw3_get,10720	};10721 10722	if (!WARN_ON_ONCE(dword >= ARRAY_SIZE(getters)))10723		*p_mng_feature_cap_val = getters[dword](payload, offset);10724}10725 10726/* MPSC - Monitoring Packet Sampling Configuration Register10727 * --------------------------------------------------------10728 * MPSC Register is used to configure the Packet Sampling mechanism.10729 */10730#define MLXSW_REG_MPSC_ID 0x908010731#define MLXSW_REG_MPSC_LEN 0x1C10732 10733MLXSW_REG_DEFINE(mpsc, MLXSW_REG_MPSC_ID, MLXSW_REG_MPSC_LEN);10734 10735/* reg_mpsc_local_port10736 * Local port number10737 * Not supported for CPU port10738 * Access: Index10739 */10740MLXSW_ITEM32_LP(reg, mpsc, 0x00, 16, 0x00, 12);10741 10742/* reg_mpsc_e10743 * Enable sampling on port local_port10744 * Access: RW10745 */10746MLXSW_ITEM32(reg, mpsc, e, 0x04, 30, 1);10747 10748#define MLXSW_REG_MPSC_RATE_MAX 3500000000UL10749 10750/* reg_mpsc_rate10751 * Sampling rate = 1 out of rate packets (with randomization around10752 * the point). Valid values are: 1 to MLXSW_REG_MPSC_RATE_MAX10753 * Access: RW10754 */10755MLXSW_ITEM32(reg, mpsc, rate, 0x08, 0, 32);10756 10757static inline void mlxsw_reg_mpsc_pack(char *payload, u16 local_port, bool e,10758				       u32 rate)10759{10760	MLXSW_REG_ZERO(mpsc, payload);10761	mlxsw_reg_mpsc_local_port_set(payload, local_port);10762	mlxsw_reg_mpsc_e_set(payload, e);10763	mlxsw_reg_mpsc_rate_set(payload, rate);10764}10765 10766/* MGPC - Monitoring General Purpose Counter Set Register10767 * The MGPC register retrieves and sets the General Purpose Counter Set.10768 */10769#define MLXSW_REG_MGPC_ID 0x908110770#define MLXSW_REG_MGPC_LEN 0x1810771 10772MLXSW_REG_DEFINE(mgpc, MLXSW_REG_MGPC_ID, MLXSW_REG_MGPC_LEN);10773 10774/* reg_mgpc_counter_set_type10775 * Counter set type.10776 * Access: OP10777 */10778MLXSW_ITEM32(reg, mgpc, counter_set_type, 0x00, 24, 8);10779 10780/* reg_mgpc_counter_index10781 * Counter index.10782 * Access: Index10783 */10784MLXSW_ITEM32(reg, mgpc, counter_index, 0x00, 0, 24);10785 10786enum mlxsw_reg_mgpc_opcode {10787	/* Nop */10788	MLXSW_REG_MGPC_OPCODE_NOP = 0x00,10789	/* Clear counters */10790	MLXSW_REG_MGPC_OPCODE_CLEAR = 0x08,10791};10792 10793/* reg_mgpc_opcode10794 * Opcode.10795 * Access: OP10796 */10797MLXSW_ITEM32(reg, mgpc, opcode, 0x04, 28, 4);10798 10799/* reg_mgpc_byte_counter10800 * Byte counter value.10801 * Access: RW10802 */10803MLXSW_ITEM64(reg, mgpc, byte_counter, 0x08, 0, 64);10804 10805/* reg_mgpc_packet_counter10806 * Packet counter value.10807 * Access: RW10808 */10809MLXSW_ITEM64(reg, mgpc, packet_counter, 0x10, 0, 64);10810 10811static inline void mlxsw_reg_mgpc_pack(char *payload, u32 counter_index,10812				       enum mlxsw_reg_mgpc_opcode opcode,10813				       enum mlxsw_reg_flow_counter_set_type set_type)10814{10815	MLXSW_REG_ZERO(mgpc, payload);10816	mlxsw_reg_mgpc_counter_index_set(payload, counter_index);10817	mlxsw_reg_mgpc_counter_set_type_set(payload, set_type);10818	mlxsw_reg_mgpc_opcode_set(payload, opcode);10819}10820 10821/* MPRS - Monitoring Parsing State Register10822 * ----------------------------------------10823 * The MPRS register is used for setting up the parsing for hash,10824 * policy-engine and routing.10825 */10826#define MLXSW_REG_MPRS_ID 0x908310827#define MLXSW_REG_MPRS_LEN 0x1410828 10829MLXSW_REG_DEFINE(mprs, MLXSW_REG_MPRS_ID, MLXSW_REG_MPRS_LEN);10830 10831/* reg_mprs_parsing_depth10832 * Minimum parsing depth.10833 * Need to enlarge parsing depth according to L3, MPLS, tunnels, ACL10834 * rules, traps, hash, etc. Default is 96 bytes. Reserved when SwitchX-2.10835 * Access: RW10836 */10837MLXSW_ITEM32(reg, mprs, parsing_depth, 0x00, 0, 16);10838 10839/* reg_mprs_parsing_en10840 * Parsing enable.10841 * Bit 0 - Enable parsing of NVE of types VxLAN, VxLAN-GPE, GENEVE and10842 * NVGRE. Default is enabled. Reserved when SwitchX-2.10843 * Access: RW10844 */10845MLXSW_ITEM32(reg, mprs, parsing_en, 0x04, 0, 16);10846 10847/* reg_mprs_vxlan_udp_dport10848 * VxLAN UDP destination port.10849 * Used for identifying VxLAN packets and for dport field in10850 * encapsulation. Default is 4789.10851 * Access: RW10852 */10853MLXSW_ITEM32(reg, mprs, vxlan_udp_dport, 0x10, 0, 16);10854 10855static inline void mlxsw_reg_mprs_pack(char *payload, u16 parsing_depth,10856				       u16 vxlan_udp_dport)10857{10858	MLXSW_REG_ZERO(mprs, payload);10859	mlxsw_reg_mprs_parsing_depth_set(payload, parsing_depth);10860	mlxsw_reg_mprs_parsing_en_set(payload, true);10861	mlxsw_reg_mprs_vxlan_udp_dport_set(payload, vxlan_udp_dport);10862}10863 10864/* MOGCR - Monitoring Global Configuration Register10865 * ------------------------------------------------10866 */10867#define MLXSW_REG_MOGCR_ID 0x908610868#define MLXSW_REG_MOGCR_LEN 0x2010869 10870MLXSW_REG_DEFINE(mogcr, MLXSW_REG_MOGCR_ID, MLXSW_REG_MOGCR_LEN);10871 10872/* reg_mogcr_ptp_iftc10873 * PTP Ingress FIFO Trap Clear10874 * The PTP_ING_FIFO trap provides MTPPTR with clr according10875 * to this value. Default 0.10876 * Reserved when IB switches and when SwitchX/-2, Spectrum-210877 * Access: RW10878 */10879MLXSW_ITEM32(reg, mogcr, ptp_iftc, 0x00, 1, 1);10880 10881/* reg_mogcr_ptp_eftc10882 * PTP Egress FIFO Trap Clear10883 * The PTP_EGR_FIFO trap provides MTPPTR with clr according10884 * to this value. Default 0.10885 * Reserved when IB switches and when SwitchX/-2, Spectrum-210886 * Access: RW10887 */10888MLXSW_ITEM32(reg, mogcr, ptp_eftc, 0x00, 0, 1);10889 10890/* reg_mogcr_mirroring_pid_base10891 * Base policer id for mirroring policers.10892 * Must have an even value (e.g. 1000, not 1001).10893 * Reserved when SwitchX/-2, Switch-IB/2, Spectrum-1 and Quantum.10894 * Access: RW10895 */10896MLXSW_ITEM32(reg, mogcr, mirroring_pid_base, 0x0C, 0, 14);10897 10898/* MPAGR - Monitoring Port Analyzer Global Register10899 * ------------------------------------------------10900 * This register is used for global port analyzer configurations.10901 * Note: This register is not supported by current FW versions for Spectrum-1.10902 */10903#define MLXSW_REG_MPAGR_ID 0x908910904#define MLXSW_REG_MPAGR_LEN 0x0C10905 10906MLXSW_REG_DEFINE(mpagr, MLXSW_REG_MPAGR_ID, MLXSW_REG_MPAGR_LEN);10907 10908enum mlxsw_reg_mpagr_trigger {10909	MLXSW_REG_MPAGR_TRIGGER_EGRESS,10910	MLXSW_REG_MPAGR_TRIGGER_INGRESS,10911	MLXSW_REG_MPAGR_TRIGGER_INGRESS_WRED,10912	MLXSW_REG_MPAGR_TRIGGER_INGRESS_SHARED_BUFFER,10913	MLXSW_REG_MPAGR_TRIGGER_INGRESS_ING_CONG,10914	MLXSW_REG_MPAGR_TRIGGER_INGRESS_EGR_CONG,10915	MLXSW_REG_MPAGR_TRIGGER_EGRESS_ECN,10916	MLXSW_REG_MPAGR_TRIGGER_EGRESS_HIGH_LATENCY,10917};10918 10919/* reg_mpagr_trigger10920 * Mirror trigger.10921 * Access: Index10922 */10923MLXSW_ITEM32(reg, mpagr, trigger, 0x00, 0, 4);10924 10925/* reg_mpagr_pa_id10926 * Port analyzer ID.10927 * Access: RW10928 */10929MLXSW_ITEM32(reg, mpagr, pa_id, 0x04, 0, 4);10930 10931#define MLXSW_REG_MPAGR_RATE_MAX 3500000000UL10932 10933/* reg_mpagr_probability_rate10934 * Sampling rate.10935 * Valid values are: 1 to 3.5*10^910936 * Value of 1 means "sample all". Default is 1.10937 * Access: RW10938 */10939MLXSW_ITEM32(reg, mpagr, probability_rate, 0x08, 0, 32);10940 10941static inline void mlxsw_reg_mpagr_pack(char *payload,10942					enum mlxsw_reg_mpagr_trigger trigger,10943					u8 pa_id, u32 probability_rate)10944{10945	MLXSW_REG_ZERO(mpagr, payload);10946	mlxsw_reg_mpagr_trigger_set(payload, trigger);10947	mlxsw_reg_mpagr_pa_id_set(payload, pa_id);10948	mlxsw_reg_mpagr_probability_rate_set(payload, probability_rate);10949}10950 10951/* MOMTE - Monitoring Mirror Trigger Enable Register10952 * -------------------------------------------------10953 * This register is used to configure the mirror enable for different mirror10954 * reasons.10955 */10956#define MLXSW_REG_MOMTE_ID 0x908D10957#define MLXSW_REG_MOMTE_LEN 0x1010958 10959MLXSW_REG_DEFINE(momte, MLXSW_REG_MOMTE_ID, MLXSW_REG_MOMTE_LEN);10960 10961/* reg_momte_local_port10962 * Local port number.10963 * Access: Index10964 */10965MLXSW_ITEM32_LP(reg, momte, 0x00, 16, 0x00, 12);10966 10967enum mlxsw_reg_momte_type {10968	MLXSW_REG_MOMTE_TYPE_WRED = 0x20,10969	MLXSW_REG_MOMTE_TYPE_SHARED_BUFFER_TCLASS = 0x31,10970	MLXSW_REG_MOMTE_TYPE_SHARED_BUFFER_TCLASS_DESCRIPTORS = 0x32,10971	MLXSW_REG_MOMTE_TYPE_SHARED_BUFFER_EGRESS_PORT = 0x33,10972	MLXSW_REG_MOMTE_TYPE_ING_CONG = 0x40,10973	MLXSW_REG_MOMTE_TYPE_EGR_CONG = 0x50,10974	MLXSW_REG_MOMTE_TYPE_ECN = 0x60,10975	MLXSW_REG_MOMTE_TYPE_HIGH_LATENCY = 0x70,10976};10977 10978/* reg_momte_type10979 * Type of mirroring.10980 * Access: Index10981 */10982MLXSW_ITEM32(reg, momte, type, 0x04, 0, 8);10983 10984/* reg_momte_tclass_en10985 * TClass/PG mirror enable. Each bit represents corresponding tclass.10986 * 0: disable (default)10987 * 1: enable10988 * Access: RW10989 */10990MLXSW_ITEM_BIT_ARRAY(reg, momte, tclass_en, 0x08, 0x08, 1);10991 10992static inline void mlxsw_reg_momte_pack(char *payload, u16 local_port,10993					enum mlxsw_reg_momte_type type)10994{10995	MLXSW_REG_ZERO(momte, payload);10996	mlxsw_reg_momte_local_port_set(payload, local_port);10997	mlxsw_reg_momte_type_set(payload, type);10998}10999 11000/* MTPPPC - Time Precision Packet Port Configuration11001 * -------------------------------------------------11002 * This register serves for configuration of which PTP messages should be11003 * timestamped. This is a global configuration, despite the register name.11004 *11005 * Reserved when Spectrum-2.11006 */11007#define MLXSW_REG_MTPPPC_ID 0x909011008#define MLXSW_REG_MTPPPC_LEN 0x2811009 11010MLXSW_REG_DEFINE(mtpppc, MLXSW_REG_MTPPPC_ID, MLXSW_REG_MTPPPC_LEN);11011 11012/* reg_mtpppc_ing_timestamp_message_type11013 * Bitwise vector of PTP message types to timestamp at ingress.11014 * MessageType field as defined by IEEE 158811015 * Each bit corresponds to a value (e.g. Bit0: Sync, Bit1: Delay_Req)11016 * Default all 011017 * Access: RW11018 */11019MLXSW_ITEM32(reg, mtpppc, ing_timestamp_message_type, 0x08, 0, 16);11020 11021/* reg_mtpppc_egr_timestamp_message_type11022 * Bitwise vector of PTP message types to timestamp at egress.11023 * MessageType field as defined by IEEE 158811024 * Each bit corresponds to a value (e.g. Bit0: Sync, Bit1: Delay_Req)11025 * Default all 011026 * Access: RW11027 */11028MLXSW_ITEM32(reg, mtpppc, egr_timestamp_message_type, 0x0C, 0, 16);11029 11030static inline void mlxsw_reg_mtpppc_pack(char *payload, u16 ing, u16 egr)11031{11032	MLXSW_REG_ZERO(mtpppc, payload);11033	mlxsw_reg_mtpppc_ing_timestamp_message_type_set(payload, ing);11034	mlxsw_reg_mtpppc_egr_timestamp_message_type_set(payload, egr);11035}11036 11037/* MTPPTR - Time Precision Packet Timestamping Reading11038 * ---------------------------------------------------11039 * The MTPPTR is used for reading the per port PTP timestamp FIFO.11040 * There is a trap for packets which are latched to the timestamp FIFO, thus the11041 * SW knows which FIFO to read. Note that packets enter the FIFO before been11042 * trapped. The sequence number is used to synchronize the timestamp FIFO11043 * entries and the trapped packets.11044 * Reserved when Spectrum-2.11045 */11046 11047#define MLXSW_REG_MTPPTR_ID 0x909111048#define MLXSW_REG_MTPPTR_BASE_LEN 0x10 /* base length, without records */11049#define MLXSW_REG_MTPPTR_REC_LEN 0x10 /* record length */11050#define MLXSW_REG_MTPPTR_REC_MAX_COUNT 411051#define MLXSW_REG_MTPPTR_LEN (MLXSW_REG_MTPPTR_BASE_LEN +		\11052		    MLXSW_REG_MTPPTR_REC_LEN * MLXSW_REG_MTPPTR_REC_MAX_COUNT)11053 11054MLXSW_REG_DEFINE(mtpptr, MLXSW_REG_MTPPTR_ID, MLXSW_REG_MTPPTR_LEN);11055 11056/* reg_mtpptr_local_port11057 * Not supported for CPU port.11058 * Access: Index11059 */11060MLXSW_ITEM32_LP(reg, mtpptr, 0x00, 16, 0x00, 12);11061 11062enum mlxsw_reg_mtpptr_dir {11063	MLXSW_REG_MTPPTR_DIR_INGRESS,11064	MLXSW_REG_MTPPTR_DIR_EGRESS,11065};11066 11067/* reg_mtpptr_dir11068 * Direction.11069 * Access: Index11070 */11071MLXSW_ITEM32(reg, mtpptr, dir, 0x00, 0, 1);11072 11073/* reg_mtpptr_clr11074 * Clear the records.11075 * Access: OP11076 */11077MLXSW_ITEM32(reg, mtpptr, clr, 0x04, 31, 1);11078 11079/* reg_mtpptr_num_rec11080 * Number of valid records in the response11081 * Range 0.. cap_ptp_timestamp_fifo11082 * Access: RO11083 */11084MLXSW_ITEM32(reg, mtpptr, num_rec, 0x08, 0, 4);11085 11086/* reg_mtpptr_rec_message_type11087 * MessageType field as defined by IEEE 1588 Each bit corresponds to a value11088 * (e.g. Bit0: Sync, Bit1: Delay_Req)11089 * Access: RO11090 */11091MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_message_type,11092		     MLXSW_REG_MTPPTR_BASE_LEN, 8, 4,11093		     MLXSW_REG_MTPPTR_REC_LEN, 0, false);11094 11095/* reg_mtpptr_rec_domain_number11096 * DomainNumber field as defined by IEEE 158811097 * Access: RO11098 */11099MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_domain_number,11100		     MLXSW_REG_MTPPTR_BASE_LEN, 0, 8,11101		     MLXSW_REG_MTPPTR_REC_LEN, 0, false);11102 11103/* reg_mtpptr_rec_sequence_id11104 * SequenceId field as defined by IEEE 158811105 * Access: RO11106 */11107MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_sequence_id,11108		     MLXSW_REG_MTPPTR_BASE_LEN, 0, 16,11109		     MLXSW_REG_MTPPTR_REC_LEN, 0x4, false);11110 11111/* reg_mtpptr_rec_timestamp_high11112 * Timestamp of when the PTP packet has passed through the port Units of PLL11113 * clock time.11114 * For Spectrum-1 the PLL clock is 156.25Mhz and PLL clock time is 6.4nSec.11115 * Access: RO11116 */11117MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_timestamp_high,11118		     MLXSW_REG_MTPPTR_BASE_LEN, 0, 32,11119		     MLXSW_REG_MTPPTR_REC_LEN, 0x8, false);11120 11121/* reg_mtpptr_rec_timestamp_low11122 * See rec_timestamp_high.11123 * Access: RO11124 */11125MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_timestamp_low,11126		     MLXSW_REG_MTPPTR_BASE_LEN, 0, 32,11127		     MLXSW_REG_MTPPTR_REC_LEN, 0xC, false);11128 11129static inline void mlxsw_reg_mtpptr_unpack(const char *payload,11130					   unsigned int rec,11131					   u8 *p_message_type,11132					   u8 *p_domain_number,11133					   u16 *p_sequence_id,11134					   u64 *p_timestamp)11135{11136	u32 timestamp_high, timestamp_low;11137 11138	*p_message_type = mlxsw_reg_mtpptr_rec_message_type_get(payload, rec);11139	*p_domain_number = mlxsw_reg_mtpptr_rec_domain_number_get(payload, rec);11140	*p_sequence_id = mlxsw_reg_mtpptr_rec_sequence_id_get(payload, rec);11141	timestamp_high = mlxsw_reg_mtpptr_rec_timestamp_high_get(payload, rec);11142	timestamp_low = mlxsw_reg_mtpptr_rec_timestamp_low_get(payload, rec);11143	*p_timestamp = (u64)timestamp_high << 32 | timestamp_low;11144}11145 11146/* MTPTPT - Monitoring Precision Time Protocol Trap Register11147 * ---------------------------------------------------------11148 * This register is used for configuring under which trap to deliver PTP11149 * packets depending on type of the packet.11150 */11151#define MLXSW_REG_MTPTPT_ID 0x909211152#define MLXSW_REG_MTPTPT_LEN 0x0811153 11154MLXSW_REG_DEFINE(mtptpt, MLXSW_REG_MTPTPT_ID, MLXSW_REG_MTPTPT_LEN);11155 11156enum mlxsw_reg_mtptpt_trap_id {11157	MLXSW_REG_MTPTPT_TRAP_ID_PTP0,11158	MLXSW_REG_MTPTPT_TRAP_ID_PTP1,11159};11160 11161/* reg_mtptpt_trap_id11162 * Trap id.11163 * Access: Index11164 */11165MLXSW_ITEM32(reg, mtptpt, trap_id, 0x00, 0, 4);11166 11167/* reg_mtptpt_message_type11168 * Bitwise vector of PTP message types to trap. This is a necessary but11169 * non-sufficient condition since need to enable also per port. See MTPPPC.11170 * Message types are defined by IEEE 1588 Each bit corresponds to a value (e.g.11171 * Bit0: Sync, Bit1: Delay_Req)11172 */11173MLXSW_ITEM32(reg, mtptpt, message_type, 0x04, 0, 16);11174 11175static inline void mlxsw_reg_mtptpt_pack(char *payload,11176					 enum mlxsw_reg_mtptpt_trap_id trap_id,11177					 u16 message_type)11178{11179	MLXSW_REG_ZERO(mtptpt, payload);11180	mlxsw_reg_mtptpt_trap_id_set(payload, trap_id);11181	mlxsw_reg_mtptpt_message_type_set(payload, message_type);11182}11183 11184/* MTPCPC - Monitoring Time Precision Correction Port Configuration Register11185 * -------------------------------------------------------------------------11186 */11187#define MLXSW_REG_MTPCPC_ID 0x909311188#define MLXSW_REG_MTPCPC_LEN 0x2C11189 11190MLXSW_REG_DEFINE(mtpcpc, MLXSW_REG_MTPCPC_ID, MLXSW_REG_MTPCPC_LEN);11191 11192/* reg_mtpcpc_pport11193 * Per port:11194 * 0: config is global. When reading - the local_port is 1.11195 * 1: config is per port.11196 * Access: Index11197 */11198MLXSW_ITEM32(reg, mtpcpc, pport, 0x00, 31, 1);11199 11200/* reg_mtpcpc_local_port11201 * Local port number.11202 * Supported to/from CPU port.11203 * Reserved when pport = 0.11204 * Access: Index11205 */11206MLXSW_ITEM32_LP(reg, mtpcpc, 0x00, 16, 0x00, 12);11207 11208/* reg_mtpcpc_ptp_trap_en11209 * Enable PTP traps.11210 * The trap_id is configured by MTPTPT.11211 * Access: RW11212 */11213MLXSW_ITEM32(reg, mtpcpc, ptp_trap_en, 0x04, 0, 1);11214 11215/* reg_mtpcpc_ing_correction_message_type11216 * Bitwise vector of PTP message types to update correction-field at ingress.11217 * MessageType field as defined by IEEE 1588 Each bit corresponds to a value11218 * (e.g. Bit0: Sync, Bit1: Delay_Req). Supported also from CPU port.11219 * Default all 011220 * Access: RW11221 */11222MLXSW_ITEM32(reg, mtpcpc, ing_correction_message_type, 0x10, 0, 16);11223 11224/* reg_mtpcpc_egr_correction_message_type11225 * Bitwise vector of PTP message types to update correction-field at egress.11226 * MessageType field as defined by IEEE 1588 Each bit corresponds to a value11227 * (e.g. Bit0: Sync, Bit1: Delay_Req). Supported also from CPU port.11228 * Default all 011229 * Access: RW11230 */11231MLXSW_ITEM32(reg, mtpcpc, egr_correction_message_type, 0x14, 0, 16);11232 11233static inline void mlxsw_reg_mtpcpc_pack(char *payload, bool pport,11234					 u16 local_port, bool ptp_trap_en,11235					 u16 ing, u16 egr)11236{11237	MLXSW_REG_ZERO(mtpcpc, payload);11238	mlxsw_reg_mtpcpc_pport_set(payload, pport);11239	mlxsw_reg_mtpcpc_local_port_set(payload, pport ? local_port : 0);11240	mlxsw_reg_mtpcpc_ptp_trap_en_set(payload, ptp_trap_en);11241	mlxsw_reg_mtpcpc_ing_correction_message_type_set(payload, ing);11242	mlxsw_reg_mtpcpc_egr_correction_message_type_set(payload, egr);11243}11244 11245/* MFGD - Monitoring FW General Debug Register11246 * -------------------------------------------11247 */11248#define MLXSW_REG_MFGD_ID 0x90F011249#define MLXSW_REG_MFGD_LEN 0x0C11250 11251MLXSW_REG_DEFINE(mfgd, MLXSW_REG_MFGD_ID, MLXSW_REG_MFGD_LEN);11252 11253/* reg_mfgd_fw_fatal_event_mode11254 * 0 - don't check FW fatal (default)11255 * 1 - check FW fatal - enable MFDE trap11256 * Access: RW11257 */11258MLXSW_ITEM32(reg, mfgd, fatal_event_mode, 0x00, 9, 2);11259 11260/* reg_mfgd_trigger_test11261 * Access: WO11262 */11263MLXSW_ITEM32(reg, mfgd, trigger_test, 0x00, 11, 1);11264 11265/* MGPIR - Management General Peripheral Information Register11266 * ----------------------------------------------------------11267 * MGPIR register allows software to query the hardware and11268 * firmware general information of peripheral entities.11269 */11270#define MLXSW_REG_MGPIR_ID 0x910011271#define MLXSW_REG_MGPIR_LEN 0xA011272 11273MLXSW_REG_DEFINE(mgpir, MLXSW_REG_MGPIR_ID, MLXSW_REG_MGPIR_LEN);11274 11275enum mlxsw_reg_mgpir_device_type {11276	MLXSW_REG_MGPIR_DEVICE_TYPE_NONE,11277	MLXSW_REG_MGPIR_DEVICE_TYPE_GEARBOX_DIE,11278};11279 11280/* mgpir_slot_index11281 * Slot index (0: Main board).11282 * Access: Index11283 */11284MLXSW_ITEM32(reg, mgpir, slot_index, 0x00, 28, 4);11285 11286/* mgpir_device_type11287 * Access: RO11288 */11289MLXSW_ITEM32(reg, mgpir, device_type, 0x00, 24, 4);11290 11291/* mgpir_devices_per_flash11292 * Number of devices of device_type per flash (can be shared by few devices).11293 * Access: RO11294 */11295MLXSW_ITEM32(reg, mgpir, devices_per_flash, 0x00, 16, 8);11296 11297/* mgpir_num_of_devices11298 * Number of devices of device_type.11299 * Access: RO11300 */11301MLXSW_ITEM32(reg, mgpir, num_of_devices, 0x00, 0, 8);11302 11303/* max_modules_per_slot11304 * Maximum number of modules that can be connected per slot.11305 * Access: RO11306 */11307MLXSW_ITEM32(reg, mgpir, max_modules_per_slot, 0x04, 16, 8);11308 11309/* mgpir_num_of_slots11310 * Number of slots in the system.11311 * Access: RO11312 */11313MLXSW_ITEM32(reg, mgpir, num_of_slots, 0x04, 8, 8);11314 11315/* mgpir_num_of_modules11316 * Number of modules.11317 * Access: RO11318 */11319MLXSW_ITEM32(reg, mgpir, num_of_modules, 0x04, 0, 8);11320 11321static inline void mlxsw_reg_mgpir_pack(char *payload, u8 slot_index)11322{11323	MLXSW_REG_ZERO(mgpir, payload);11324	mlxsw_reg_mgpir_slot_index_set(payload, slot_index);11325}11326 11327static inline void11328mlxsw_reg_mgpir_unpack(char *payload, u8 *num_of_devices,11329		       enum mlxsw_reg_mgpir_device_type *device_type,11330		       u8 *devices_per_flash, u8 *num_of_modules,11331		       u8 *num_of_slots)11332{11333	if (num_of_devices)11334		*num_of_devices = mlxsw_reg_mgpir_num_of_devices_get(payload);11335	if (device_type)11336		*device_type = mlxsw_reg_mgpir_device_type_get(payload);11337	if (devices_per_flash)11338		*devices_per_flash =11339				mlxsw_reg_mgpir_devices_per_flash_get(payload);11340	if (num_of_modules)11341		*num_of_modules = mlxsw_reg_mgpir_num_of_modules_get(payload);11342	if (num_of_slots)11343		*num_of_slots = mlxsw_reg_mgpir_num_of_slots_get(payload);11344}11345 11346/* MBCT - Management Binary Code Transfer Register11347 * -----------------------------------------------11348 * This register allows to transfer binary codes from the host to11349 * the management FW by transferring it by chunks of maximum 1KB.11350 */11351#define MLXSW_REG_MBCT_ID 0x912011352#define MLXSW_REG_MBCT_LEN 0x42011353 11354MLXSW_REG_DEFINE(mbct, MLXSW_REG_MBCT_ID, MLXSW_REG_MBCT_LEN);11355 11356/* reg_mbct_slot_index11357 * Slot index. 0 is reserved.11358 * Access: Index11359 */11360MLXSW_ITEM32(reg, mbct, slot_index, 0x00, 0, 4);11361 11362/* reg_mbct_data_size11363 * Actual data field size in bytes for the current data transfer.11364 * Access: WO11365 */11366MLXSW_ITEM32(reg, mbct, data_size, 0x04, 0, 11);11367 11368enum mlxsw_reg_mbct_op {11369	MLXSW_REG_MBCT_OP_ERASE_INI_IMAGE = 1,11370	MLXSW_REG_MBCT_OP_DATA_TRANSFER, /* Download */11371	MLXSW_REG_MBCT_OP_ACTIVATE,11372	MLXSW_REG_MBCT_OP_CLEAR_ERRORS = 6,11373	MLXSW_REG_MBCT_OP_QUERY_STATUS,11374};11375 11376/* reg_mbct_op11377 * Access: WO11378 */11379MLXSW_ITEM32(reg, mbct, op, 0x08, 28, 4);11380 11381/* reg_mbct_last11382 * Indicates that the current data field is the last chunk of the INI.11383 * Access: WO11384 */11385MLXSW_ITEM32(reg, mbct, last, 0x08, 26, 1);11386 11387/* reg_mbct_oee11388 * Opcode Event Enable. When set a BCTOE event will be sent once the opcode11389 * was executed and the fsm_state has changed.11390 * Access: WO11391 */11392MLXSW_ITEM32(reg, mbct, oee, 0x08, 25, 1);11393 11394enum mlxsw_reg_mbct_status {11395	/* Partial data transfer completed successfully and ready for next11396	 * data transfer.11397	 */11398	MLXSW_REG_MBCT_STATUS_PART_DATA = 2,11399	MLXSW_REG_MBCT_STATUS_LAST_DATA,11400	MLXSW_REG_MBCT_STATUS_ERASE_COMPLETE,11401	/* Error - trying to erase INI while it being used. */11402	MLXSW_REG_MBCT_STATUS_ERROR_INI_IN_USE,11403	/* Last data transfer completed, applying magic pattern. */11404	MLXSW_REG_MBCT_STATUS_ERASE_FAILED = 7,11405	MLXSW_REG_MBCT_STATUS_INI_ERROR,11406	MLXSW_REG_MBCT_STATUS_ACTIVATION_FAILED,11407	MLXSW_REG_MBCT_STATUS_ILLEGAL_OPERATION = 11,11408};11409 11410/* reg_mbct_status11411 * Status.11412 * Access: RO11413 */11414MLXSW_ITEM32(reg, mbct, status, 0x0C, 24, 5);11415 11416enum mlxsw_reg_mbct_fsm_state {11417	MLXSW_REG_MBCT_FSM_STATE_INI_IN_USE = 5,11418	MLXSW_REG_MBCT_FSM_STATE_ERROR,11419};11420 11421/* reg_mbct_fsm_state11422 * FSM state.11423 * Access: RO11424 */11425MLXSW_ITEM32(reg, mbct, fsm_state,  0x0C, 16, 4);11426 11427#define MLXSW_REG_MBCT_DATA_LEN 102411428 11429/* reg_mbct_data11430 * Up to 1KB of data.11431 * Access: WO11432 */11433MLXSW_ITEM_BUF(reg, mbct, data, 0x20, MLXSW_REG_MBCT_DATA_LEN);11434 11435static inline void mlxsw_reg_mbct_pack(char *payload, u8 slot_index,11436				       enum mlxsw_reg_mbct_op op, bool oee)11437{11438	MLXSW_REG_ZERO(mbct, payload);11439	mlxsw_reg_mbct_slot_index_set(payload, slot_index);11440	mlxsw_reg_mbct_op_set(payload, op);11441	mlxsw_reg_mbct_oee_set(payload, oee);11442}11443 11444static inline void mlxsw_reg_mbct_dt_pack(char *payload,11445					  u16 data_size, bool last,11446					  const char *data)11447{11448	if (WARN_ON(data_size > MLXSW_REG_MBCT_DATA_LEN))11449		return;11450	mlxsw_reg_mbct_data_size_set(payload, data_size);11451	mlxsw_reg_mbct_last_set(payload, last);11452	mlxsw_reg_mbct_data_memcpy_to(payload, data);11453}11454 11455static inline void11456mlxsw_reg_mbct_unpack(const char *payload, u8 *p_slot_index,11457		      enum mlxsw_reg_mbct_status *p_status,11458		      enum mlxsw_reg_mbct_fsm_state *p_fsm_state)11459{11460	if (p_slot_index)11461		*p_slot_index = mlxsw_reg_mbct_slot_index_get(payload);11462	*p_status = mlxsw_reg_mbct_status_get(payload);11463	if (p_fsm_state)11464		*p_fsm_state = mlxsw_reg_mbct_fsm_state_get(payload);11465}11466 11467/* MDDT - Management DownStream Device Tunneling Register11468 * ------------------------------------------------------11469 * This register allows to deliver query and request messages (PRM registers,11470 * commands) to a DownStream device.11471 */11472#define MLXSW_REG_MDDT_ID 0x916011473#define MLXSW_REG_MDDT_LEN 0x11011474 11475MLXSW_REG_DEFINE(mddt, MLXSW_REG_MDDT_ID, MLXSW_REG_MDDT_LEN);11476 11477/* reg_mddt_slot_index11478 * Slot index.11479 * Access: Index11480 */11481MLXSW_ITEM32(reg, mddt, slot_index, 0x00, 8, 4);11482 11483/* reg_mddt_device_index11484 * Device index.11485 * Access: Index11486 */11487MLXSW_ITEM32(reg, mddt, device_index, 0x00, 0, 8);11488 11489/* reg_mddt_read_size11490 * Read size in D-Words.11491 * Access: OP11492 */11493MLXSW_ITEM32(reg, mddt, read_size, 0x04, 24, 8);11494 11495/* reg_mddt_write_size11496 * Write size in D-Words.11497 * Access: OP11498 */11499MLXSW_ITEM32(reg, mddt, write_size, 0x04, 16, 8);11500 11501enum mlxsw_reg_mddt_status {11502	MLXSW_REG_MDDT_STATUS_OK,11503};11504 11505/* reg_mddt_status11506 * Return code of the Downstream Device to the register that was sent.11507 * Access: RO11508 */11509MLXSW_ITEM32(reg, mddt, status, 0x0C, 24, 8);11510 11511enum mlxsw_reg_mddt_method {11512	MLXSW_REG_MDDT_METHOD_QUERY,11513	MLXSW_REG_MDDT_METHOD_WRITE,11514};11515 11516/* reg_mddt_method11517 * Access: OP11518 */11519MLXSW_ITEM32(reg, mddt, method, 0x0C, 22, 2);11520 11521/* reg_mddt_register_id11522 * Access: Index11523 */11524MLXSW_ITEM32(reg, mddt, register_id, 0x0C, 0, 16);11525 11526#define MLXSW_REG_MDDT_PAYLOAD_OFFSET 0x0C11527#define MLXSW_REG_MDDT_PRM_REGISTER_HEADER_LEN 411528 11529static inline char *mlxsw_reg_mddt_inner_payload(char *payload)11530{11531	return payload + MLXSW_REG_MDDT_PAYLOAD_OFFSET +11532	       MLXSW_REG_MDDT_PRM_REGISTER_HEADER_LEN;11533}11534 11535static inline void mlxsw_reg_mddt_pack(char *payload, u8 slot_index,11536				       u8 device_index,11537				       enum mlxsw_reg_mddt_method method,11538				       const struct mlxsw_reg_info *reg,11539				       char **inner_payload)11540{11541	int len = reg->len + MLXSW_REG_MDDT_PRM_REGISTER_HEADER_LEN;11542 11543	if (WARN_ON(len + MLXSW_REG_MDDT_PAYLOAD_OFFSET > MLXSW_REG_MDDT_LEN))11544		len = MLXSW_REG_MDDT_LEN - MLXSW_REG_MDDT_PAYLOAD_OFFSET;11545 11546	MLXSW_REG_ZERO(mddt, payload);11547	mlxsw_reg_mddt_slot_index_set(payload, slot_index);11548	mlxsw_reg_mddt_device_index_set(payload, device_index);11549	mlxsw_reg_mddt_method_set(payload, method);11550	mlxsw_reg_mddt_register_id_set(payload, reg->id);11551	mlxsw_reg_mddt_read_size_set(payload, len / 4);11552	mlxsw_reg_mddt_write_size_set(payload, len / 4);11553	*inner_payload = mlxsw_reg_mddt_inner_payload(payload);11554}11555 11556/* MDDQ - Management DownStream Device Query Register11557 * --------------------------------------------------11558 * This register allows to query the DownStream device properties. The desired11559 * information is chosen upon the query_type field and is delivered by 32B11560 * of data blocks.11561 */11562#define MLXSW_REG_MDDQ_ID 0x916111563#define MLXSW_REG_MDDQ_LEN 0x3011564 11565MLXSW_REG_DEFINE(mddq, MLXSW_REG_MDDQ_ID, MLXSW_REG_MDDQ_LEN);11566 11567/* reg_mddq_sie11568 * Slot info event enable.11569 * When set to '1', each change in the slot_info.provisioned / sr_valid /11570 * active / ready will generate a DSDSC event.11571 * Access: RW11572 */11573MLXSW_ITEM32(reg, mddq, sie, 0x00, 31, 1);11574 11575enum mlxsw_reg_mddq_query_type {11576	MLXSW_REG_MDDQ_QUERY_TYPE_SLOT_INFO = 1,11577	MLXSW_REG_MDDQ_QUERY_TYPE_DEVICE_INFO, /* If there are no devices11578						* on the slot, data_valid11579						* will be '0'.11580						*/11581	MLXSW_REG_MDDQ_QUERY_TYPE_SLOT_NAME,11582};11583 11584/* reg_mddq_query_type11585 * Access: Index11586 */11587MLXSW_ITEM32(reg, mddq, query_type, 0x00, 16, 8);11588 11589/* reg_mddq_slot_index11590 * Slot index. 0 is reserved.11591 * Access: Index11592 */11593MLXSW_ITEM32(reg, mddq, slot_index, 0x00, 0, 4);11594 11595/* reg_mddq_response_msg_seq11596 * Response message sequential number. For a specific request, the response11597 * message sequential number is the following one. In addition, the last11598 * message should be 0.11599 * Access: RO11600 */11601MLXSW_ITEM32(reg, mddq, response_msg_seq, 0x04, 16, 8);11602 11603/* reg_mddq_request_msg_seq11604 * Request message sequential number.11605 * The first message number should be 0.11606 * Access: Index11607 */11608MLXSW_ITEM32(reg, mddq, request_msg_seq, 0x04, 0, 8);11609 11610/* reg_mddq_data_valid11611 * If set, the data in the data field is valid and contain the information11612 * for the queried index.11613 * Access: RO11614 */11615MLXSW_ITEM32(reg, mddq, data_valid, 0x08, 31, 1);11616 11617/* reg_mddq_slot_info_provisioned11618 * If set, the INI file is applied and the card is provisioned.11619 * Access: RO11620 */11621MLXSW_ITEM32(reg, mddq, slot_info_provisioned, 0x10, 31, 1);11622 11623/* reg_mddq_slot_info_sr_valid11624 * If set, Shift Register is valid (after being provisioned) and data11625 * can be sent from the switch ASIC to the line-card CPLD over Shift-Register.11626 * Access: RO11627 */11628MLXSW_ITEM32(reg, mddq, slot_info_sr_valid, 0x10, 30, 1);11629 11630enum mlxsw_reg_mddq_slot_info_ready {11631	MLXSW_REG_MDDQ_SLOT_INFO_READY_NOT_READY,11632	MLXSW_REG_MDDQ_SLOT_INFO_READY_READY,11633	MLXSW_REG_MDDQ_SLOT_INFO_READY_ERROR,11634};11635 11636/* reg_mddq_slot_info_lc_ready11637 * If set, the LC is powered on, matching the INI version and a new FW11638 * version can be burnt (if necessary).11639 * Access: RO11640 */11641MLXSW_ITEM32(reg, mddq, slot_info_lc_ready, 0x10, 28, 2);11642 11643/* reg_mddq_slot_info_active11644 * If set, the FW has completed the MDDC.device_enable command.11645 * Access: RO11646 */11647MLXSW_ITEM32(reg, mddq, slot_info_active, 0x10, 27, 1);11648 11649/* reg_mddq_slot_info_hw_revision11650 * Major user-configured version number of the current INI file.11651 * Valid only when active or ready are '1'.11652 * Access: RO11653 */11654MLXSW_ITEM32(reg, mddq, slot_info_hw_revision, 0x14, 16, 16);11655 11656/* reg_mddq_slot_info_ini_file_version11657 * User-configured version number of the current INI file.11658 * Valid only when active or lc_ready are '1'.11659 * Access: RO11660 */11661MLXSW_ITEM32(reg, mddq, slot_info_ini_file_version, 0x14, 0, 16);11662 11663/* reg_mddq_slot_info_card_type11664 * Access: RO11665 */11666MLXSW_ITEM32(reg, mddq, slot_info_card_type, 0x18, 0, 8);11667 11668static inline void11669__mlxsw_reg_mddq_pack(char *payload, u8 slot_index,11670		      enum mlxsw_reg_mddq_query_type query_type)11671{11672	MLXSW_REG_ZERO(mddq, payload);11673	mlxsw_reg_mddq_slot_index_set(payload, slot_index);11674	mlxsw_reg_mddq_query_type_set(payload, query_type);11675}11676 11677static inline void11678mlxsw_reg_mddq_slot_info_pack(char *payload, u8 slot_index, bool sie)11679{11680	__mlxsw_reg_mddq_pack(payload, slot_index,11681			      MLXSW_REG_MDDQ_QUERY_TYPE_SLOT_INFO);11682	mlxsw_reg_mddq_sie_set(payload, sie);11683}11684 11685static inline void11686mlxsw_reg_mddq_slot_info_unpack(const char *payload, u8 *p_slot_index,11687				bool *p_provisioned, bool *p_sr_valid,11688				enum mlxsw_reg_mddq_slot_info_ready *p_lc_ready,11689				bool *p_active, u16 *p_hw_revision,11690				u16 *p_ini_file_version,11691				u8 *p_card_type)11692{11693	*p_slot_index = mlxsw_reg_mddq_slot_index_get(payload);11694	*p_provisioned = mlxsw_reg_mddq_slot_info_provisioned_get(payload);11695	*p_sr_valid = mlxsw_reg_mddq_slot_info_sr_valid_get(payload);11696	*p_lc_ready = mlxsw_reg_mddq_slot_info_lc_ready_get(payload);11697	*p_active = mlxsw_reg_mddq_slot_info_active_get(payload);11698	*p_hw_revision = mlxsw_reg_mddq_slot_info_hw_revision_get(payload);11699	*p_ini_file_version = mlxsw_reg_mddq_slot_info_ini_file_version_get(payload);11700	*p_card_type = mlxsw_reg_mddq_slot_info_card_type_get(payload);11701}11702 11703/* reg_mddq_device_info_flash_owner11704 * If set, the device is the flash owner. Otherwise, a shared flash11705 * is used by this device (another device is the flash owner).11706 * Access: RO11707 */11708MLXSW_ITEM32(reg, mddq, device_info_flash_owner, 0x10, 30, 1);11709 11710/* reg_mddq_device_info_device_index11711 * Device index. The first device should number 0.11712 * Access: RO11713 */11714MLXSW_ITEM32(reg, mddq, device_info_device_index, 0x10, 0, 8);11715 11716/* reg_mddq_device_info_fw_major11717 * Major FW version number.11718 * Access: RO11719 */11720MLXSW_ITEM32(reg, mddq, device_info_fw_major, 0x14, 16, 16);11721 11722/* reg_mddq_device_info_fw_minor11723 * Minor FW version number.11724 * Access: RO11725 */11726MLXSW_ITEM32(reg, mddq, device_info_fw_minor, 0x18, 16, 16);11727 11728/* reg_mddq_device_info_fw_sub_minor11729 * Sub-minor FW version number.11730 * Access: RO11731 */11732MLXSW_ITEM32(reg, mddq, device_info_fw_sub_minor, 0x18, 0, 16);11733 11734static inline void11735mlxsw_reg_mddq_device_info_pack(char *payload, u8 slot_index,11736				u8 request_msg_seq)11737{11738	__mlxsw_reg_mddq_pack(payload, slot_index,11739			      MLXSW_REG_MDDQ_QUERY_TYPE_DEVICE_INFO);11740	mlxsw_reg_mddq_request_msg_seq_set(payload, request_msg_seq);11741}11742 11743static inline void11744mlxsw_reg_mddq_device_info_unpack(const char *payload, u8 *p_response_msg_seq,11745				  bool *p_data_valid, bool *p_flash_owner,11746				  u8 *p_device_index, u16 *p_fw_major,11747				  u16 *p_fw_minor, u16 *p_fw_sub_minor)11748{11749	*p_response_msg_seq = mlxsw_reg_mddq_response_msg_seq_get(payload);11750	*p_data_valid = mlxsw_reg_mddq_data_valid_get(payload);11751	*p_flash_owner = mlxsw_reg_mddq_device_info_flash_owner_get(payload);11752	*p_device_index = mlxsw_reg_mddq_device_info_device_index_get(payload);11753	*p_fw_major = mlxsw_reg_mddq_device_info_fw_major_get(payload);11754	*p_fw_minor = mlxsw_reg_mddq_device_info_fw_minor_get(payload);11755	*p_fw_sub_minor = mlxsw_reg_mddq_device_info_fw_sub_minor_get(payload);11756}11757 11758#define MLXSW_REG_MDDQ_SLOT_ASCII_NAME_LEN 2011759 11760/* reg_mddq_slot_ascii_name11761 * Slot's ASCII name.11762 * Access: RO11763 */11764MLXSW_ITEM_BUF(reg, mddq, slot_ascii_name, 0x10,11765	       MLXSW_REG_MDDQ_SLOT_ASCII_NAME_LEN);11766 11767static inline void11768mlxsw_reg_mddq_slot_name_pack(char *payload, u8 slot_index)11769{11770	__mlxsw_reg_mddq_pack(payload, slot_index,11771			      MLXSW_REG_MDDQ_QUERY_TYPE_SLOT_NAME);11772}11773 11774static inline void11775mlxsw_reg_mddq_slot_name_unpack(const char *payload, char *slot_ascii_name)11776{11777	mlxsw_reg_mddq_slot_ascii_name_memcpy_from(payload, slot_ascii_name);11778}11779 11780/* MDDC - Management DownStream Device Control Register11781 * ----------------------------------------------------11782 * This register allows to control downstream devices and line cards.11783 */11784#define MLXSW_REG_MDDC_ID 0x916311785#define MLXSW_REG_MDDC_LEN 0x3011786 11787MLXSW_REG_DEFINE(mddc, MLXSW_REG_MDDC_ID, MLXSW_REG_MDDC_LEN);11788 11789/* reg_mddc_slot_index11790 * Slot index. 0 is reserved.11791 * Access: Index11792 */11793MLXSW_ITEM32(reg, mddc, slot_index, 0x00, 0, 4);11794 11795/* reg_mddc_rst11796 * Reset request.11797 * Access: OP11798 */11799MLXSW_ITEM32(reg, mddc, rst, 0x04, 29, 1);11800 11801/* reg_mddc_device_enable11802 * When set, FW is the manager and allowed to program the downstream device.11803 * Access: RW11804 */11805MLXSW_ITEM32(reg, mddc, device_enable, 0x04, 28, 1);11806 11807static inline void mlxsw_reg_mddc_pack(char *payload, u8 slot_index, bool rst,11808				       bool device_enable)11809{11810	MLXSW_REG_ZERO(mddc, payload);11811	mlxsw_reg_mddc_slot_index_set(payload, slot_index);11812	mlxsw_reg_mddc_rst_set(payload, rst);11813	mlxsw_reg_mddc_device_enable_set(payload, device_enable);11814}11815 11816/* MFDE - Monitoring FW Debug Register11817 * -----------------------------------11818 */11819#define MLXSW_REG_MFDE_ID 0x920011820#define MLXSW_REG_MFDE_LEN 0x3011821 11822MLXSW_REG_DEFINE(mfde, MLXSW_REG_MFDE_ID, MLXSW_REG_MFDE_LEN);11823 11824/* reg_mfde_irisc_id11825 * Which irisc triggered the event11826 * Access: RO11827 */11828MLXSW_ITEM32(reg, mfde, irisc_id, 0x00, 24, 8);11829 11830enum mlxsw_reg_mfde_severity {11831	/* Unrecoverable switch behavior */11832	MLXSW_REG_MFDE_SEVERITY_FATL = 2,11833	/* Unexpected state with possible systemic failure */11834	MLXSW_REG_MFDE_SEVERITY_NRML = 3,11835	/* Unexpected state without systemic failure */11836	MLXSW_REG_MFDE_SEVERITY_INTR = 5,11837};11838 11839/* reg_mfde_severity11840 * The severity of the event.11841 * Access: RO11842 */11843MLXSW_ITEM32(reg, mfde, severity, 0x00, 16, 8);11844 11845enum mlxsw_reg_mfde_event_id {11846	/* CRspace timeout */11847	MLXSW_REG_MFDE_EVENT_ID_CRSPACE_TO = 1,11848	/* KVD insertion machine stopped */11849	MLXSW_REG_MFDE_EVENT_ID_KVD_IM_STOP,11850	/* Triggered by MFGD.trigger_test */11851	MLXSW_REG_MFDE_EVENT_ID_TEST,11852	/* Triggered when firmware hits an assert */11853	MLXSW_REG_MFDE_EVENT_ID_FW_ASSERT,11854	/* Fatal error interrupt from hardware */11855	MLXSW_REG_MFDE_EVENT_ID_FATAL_CAUSE,11856};11857 11858/* reg_mfde_event_id11859 * Access: RO11860 */11861MLXSW_ITEM32(reg, mfde, event_id, 0x00, 0, 16);11862 11863enum mlxsw_reg_mfde_method {11864	MLXSW_REG_MFDE_METHOD_QUERY,11865	MLXSW_REG_MFDE_METHOD_WRITE,11866};11867 11868/* reg_mfde_method11869 * Access: RO11870 */11871MLXSW_ITEM32(reg, mfde, method, 0x04, 29, 1);11872 11873/* reg_mfde_long_process11874 * Indicates if the command is in long_process mode.11875 * Access: RO11876 */11877MLXSW_ITEM32(reg, mfde, long_process, 0x04, 28, 1);11878 11879enum mlxsw_reg_mfde_command_type {11880	MLXSW_REG_MFDE_COMMAND_TYPE_MAD,11881	MLXSW_REG_MFDE_COMMAND_TYPE_EMAD,11882	MLXSW_REG_MFDE_COMMAND_TYPE_CMDIF,11883};11884 11885/* reg_mfde_command_type11886 * Access: RO11887 */11888MLXSW_ITEM32(reg, mfde, command_type, 0x04, 24, 2);11889 11890/* reg_mfde_reg_attr_id11891 * EMAD - register id, MAD - attibute id11892 * Access: RO11893 */11894MLXSW_ITEM32(reg, mfde, reg_attr_id, 0x04, 0, 16);11895 11896/* reg_mfde_crspace_to_log_address11897 * crspace address accessed, which resulted in timeout.11898 * Access: RO11899 */11900MLXSW_ITEM32(reg, mfde, crspace_to_log_address, 0x10, 0, 32);11901 11902/* reg_mfde_crspace_to_oe11903 * 0 - New event11904 * 1 - Old event, occurred before MFGD activation.11905 * Access: RO11906 */11907MLXSW_ITEM32(reg, mfde, crspace_to_oe, 0x14, 24, 1);11908 11909/* reg_mfde_crspace_to_log_id11910 * Which irisc triggered the timeout.11911 * Access: RO11912 */11913MLXSW_ITEM32(reg, mfde, crspace_to_log_id, 0x14, 0, 4);11914 11915/* reg_mfde_crspace_to_log_ip11916 * IP (instruction pointer) that triggered the timeout.11917 * Access: RO11918 */11919MLXSW_ITEM64(reg, mfde, crspace_to_log_ip, 0x18, 0, 64);11920 11921/* reg_mfde_kvd_im_stop_oe11922 * 0 - New event11923 * 1 - Old event, occurred before MFGD activation.11924 * Access: RO11925 */11926MLXSW_ITEM32(reg, mfde, kvd_im_stop_oe, 0x10, 24, 1);11927 11928/* reg_mfde_kvd_im_stop_pipes_mask11929 * Bit per kvh pipe.11930 * Access: RO11931 */11932MLXSW_ITEM32(reg, mfde, kvd_im_stop_pipes_mask, 0x10, 0, 16);11933 11934/* reg_mfde_fw_assert_var0-411935 * Variables passed to assert.11936 * Access: RO11937 */11938MLXSW_ITEM32(reg, mfde, fw_assert_var0, 0x10, 0, 32);11939MLXSW_ITEM32(reg, mfde, fw_assert_var1, 0x14, 0, 32);11940MLXSW_ITEM32(reg, mfde, fw_assert_var2, 0x18, 0, 32);11941MLXSW_ITEM32(reg, mfde, fw_assert_var3, 0x1C, 0, 32);11942MLXSW_ITEM32(reg, mfde, fw_assert_var4, 0x20, 0, 32);11943 11944/* reg_mfde_fw_assert_existptr11945 * The instruction pointer when assert was triggered.11946 * Access: RO11947 */11948MLXSW_ITEM32(reg, mfde, fw_assert_existptr, 0x24, 0, 32);11949 11950/* reg_mfde_fw_assert_callra11951 * The return address after triggering assert.11952 * Access: RO11953 */11954MLXSW_ITEM32(reg, mfde, fw_assert_callra, 0x28, 0, 32);11955 11956/* reg_mfde_fw_assert_oe11957 * 0 - New event11958 * 1 - Old event, occurred before MFGD activation.11959 * Access: RO11960 */11961MLXSW_ITEM32(reg, mfde, fw_assert_oe, 0x2C, 24, 1);11962 11963/* reg_mfde_fw_assert_tile_v11964 * 0: The assert was from main11965 * 1: The assert was from a tile11966 * Access: RO11967 */11968MLXSW_ITEM32(reg, mfde, fw_assert_tile_v, 0x2C, 23, 1);11969 11970/* reg_mfde_fw_assert_tile_index11971 * When tile_v=1, the tile_index that caused the assert.11972 * Access: RO11973 */11974MLXSW_ITEM32(reg, mfde, fw_assert_tile_index, 0x2C, 16, 6);11975 11976/* reg_mfde_fw_assert_ext_synd11977 * A generated one-to-one identifier which is specific per-assert.11978 * Access: RO11979 */11980MLXSW_ITEM32(reg, mfde, fw_assert_ext_synd, 0x2C, 0, 16);11981 11982/* reg_mfde_fatal_cause_id11983 * HW interrupt cause id.11984 * Access: RO11985 */11986MLXSW_ITEM32(reg, mfde, fatal_cause_id, 0x10, 0, 18);11987 11988/* reg_mfde_fatal_cause_tile_v11989 * 0: The assert was from main11990 * 1: The assert was from a tile11991 * Access: RO11992 */11993MLXSW_ITEM32(reg, mfde, fatal_cause_tile_v, 0x14, 23, 1);11994 11995/* reg_mfde_fatal_cause_tile_index11996 * When tile_v=1, the tile_index that caused the assert.11997 * Access: RO11998 */11999MLXSW_ITEM32(reg, mfde, fatal_cause_tile_index, 0x14, 16, 6);12000 12001/* TNGCR - Tunneling NVE General Configuration Register12002 * ----------------------------------------------------12003 * The TNGCR register is used for setting up the NVE Tunneling configuration.12004 */12005#define MLXSW_REG_TNGCR_ID 0xA00112006#define MLXSW_REG_TNGCR_LEN 0x4412007 12008MLXSW_REG_DEFINE(tngcr, MLXSW_REG_TNGCR_ID, MLXSW_REG_TNGCR_LEN);12009 12010enum mlxsw_reg_tngcr_type {12011	MLXSW_REG_TNGCR_TYPE_VXLAN,12012	MLXSW_REG_TNGCR_TYPE_VXLAN_GPE,12013	MLXSW_REG_TNGCR_TYPE_GENEVE,12014	MLXSW_REG_TNGCR_TYPE_NVGRE,12015};12016 12017/* reg_tngcr_type12018 * Tunnel type for encapsulation and decapsulation. The types are mutually12019 * exclusive.12020 * Note: For Spectrum the NVE parsing must be enabled in MPRS.12021 * Access: RW12022 */12023MLXSW_ITEM32(reg, tngcr, type, 0x00, 0, 4);12024 12025/* reg_tngcr_nve_valid12026 * The VTEP is valid. Allows adding FDB entries for tunnel encapsulation.12027 * Access: RW12028 */12029MLXSW_ITEM32(reg, tngcr, nve_valid, 0x04, 31, 1);12030 12031/* reg_tngcr_nve_ttl_uc12032 * The TTL for NVE tunnel encapsulation underlay unicast packets.12033 * Access: RW12034 */12035MLXSW_ITEM32(reg, tngcr, nve_ttl_uc, 0x04, 0, 8);12036 12037/* reg_tngcr_nve_ttl_mc12038 * The TTL for NVE tunnel encapsulation underlay multicast packets.12039 * Access: RW12040 */12041MLXSW_ITEM32(reg, tngcr, nve_ttl_mc, 0x08, 0, 8);12042 12043enum {12044	/* Do not copy flow label. Calculate flow label using nve_flh. */12045	MLXSW_REG_TNGCR_FL_NO_COPY,12046	/* Copy flow label from inner packet if packet is IPv6 and12047	 * encapsulation is by IPv6. Otherwise, calculate flow label using12048	 * nve_flh.12049	 */12050	MLXSW_REG_TNGCR_FL_COPY,12051};12052 12053/* reg_tngcr_nve_flc12054 * For NVE tunnel encapsulation: Flow label copy from inner packet.12055 * Access: RW12056 */12057MLXSW_ITEM32(reg, tngcr, nve_flc, 0x0C, 25, 1);12058 12059enum {12060	/* Flow label is static. In Spectrum this means '0'. Spectrum-212061	 * uses {nve_fl_prefix, nve_fl_suffix}.12062	 */12063	MLXSW_REG_TNGCR_FL_NO_HASH,12064	/* 8 LSBs of the flow label are calculated from ECMP hash of the12065	 * inner packet. 12 MSBs are configured by nve_fl_prefix.12066	 */12067	MLXSW_REG_TNGCR_FL_HASH,12068};12069 12070/* reg_tngcr_nve_flh12071 * NVE flow label hash.12072 * Access: RW12073 */12074MLXSW_ITEM32(reg, tngcr, nve_flh, 0x0C, 24, 1);12075 12076/* reg_tngcr_nve_fl_prefix12077 * NVE flow label prefix. Constant 12 MSBs of the flow label.12078 * Access: RW12079 */12080MLXSW_ITEM32(reg, tngcr, nve_fl_prefix, 0x0C, 8, 12);12081 12082/* reg_tngcr_nve_fl_suffix12083 * NVE flow label suffix. Constant 8 LSBs of the flow label.12084 * Reserved when nve_flh=1 and for Spectrum.12085 * Access: RW12086 */12087MLXSW_ITEM32(reg, tngcr, nve_fl_suffix, 0x0C, 0, 8);12088 12089enum {12090	/* Source UDP port is fixed (default '0') */12091	MLXSW_REG_TNGCR_UDP_SPORT_NO_HASH,12092	/* Source UDP port is calculated based on hash */12093	MLXSW_REG_TNGCR_UDP_SPORT_HASH,12094};12095 12096/* reg_tngcr_nve_udp_sport_type12097 * NVE UDP source port type.12098 * Spectrum uses LAG hash (SLCRv2). Spectrum-2 uses ECMP hash (RECRv2).12099 * When the source UDP port is calculated based on hash, then the 8 LSBs12100 * are calculated from hash the 8 MSBs are configured by12101 * nve_udp_sport_prefix.12102 * Access: RW12103 */12104MLXSW_ITEM32(reg, tngcr, nve_udp_sport_type, 0x10, 24, 1);12105 12106/* reg_tngcr_nve_udp_sport_prefix12107 * NVE UDP source port prefix. Constant 8 MSBs of the UDP source port.12108 * Reserved when NVE type is NVGRE.12109 * Access: RW12110 */12111MLXSW_ITEM32(reg, tngcr, nve_udp_sport_prefix, 0x10, 8, 8);12112 12113/* reg_tngcr_nve_group_size_mc12114 * The amount of sequential linked lists of MC entries. The first linked12115 * list is configured by SFD.underlay_mc_ptr.12116 * Valid values: 1, 2, 4, 8, 16, 32, 6412117 * The linked list are configured by TNUMT.12118 * The hash is set by LAG hash.12119 * Access: RW12120 */12121MLXSW_ITEM32(reg, tngcr, nve_group_size_mc, 0x18, 0, 8);12122 12123/* reg_tngcr_nve_group_size_flood12124 * The amount of sequential linked lists of flooding entries. The first12125 * linked list is configured by SFMR.nve_tunnel_flood_ptr12126 * Valid values: 1, 2, 4, 8, 16, 32, 6412127 * The linked list are configured by TNUMT.12128 * The hash is set by LAG hash.12129 * Access: RW12130 */12131MLXSW_ITEM32(reg, tngcr, nve_group_size_flood, 0x1C, 0, 8);12132 12133/* reg_tngcr_learn_enable12134 * During decapsulation, whether to learn from NVE port.12135 * Reserved when Spectrum-2. See TNPC.12136 * Access: RW12137 */12138MLXSW_ITEM32(reg, tngcr, learn_enable, 0x20, 31, 1);12139 12140/* reg_tngcr_underlay_virtual_router12141 * Underlay virtual router.12142 * Reserved when Spectrum-2.12143 * Access: RW12144 */12145MLXSW_ITEM32(reg, tngcr, underlay_virtual_router, 0x20, 0, 16);12146 12147/* reg_tngcr_underlay_rif12148 * Underlay ingress router interface. RIF type should be loopback generic.12149 * Reserved when Spectrum.12150 * Access: RW12151 */12152MLXSW_ITEM32(reg, tngcr, underlay_rif, 0x24, 0, 16);12153 12154/* reg_tngcr_usipv412155 * Underlay source IPv4 address of the NVE.12156 * Access: RW12157 */12158MLXSW_ITEM32(reg, tngcr, usipv4, 0x28, 0, 32);12159 12160/* reg_tngcr_usipv612161 * Underlay source IPv6 address of the NVE. For Spectrum, must not be12162 * modified under traffic of NVE tunneling encapsulation.12163 * Access: RW12164 */12165MLXSW_ITEM_BUF(reg, tngcr, usipv6, 0x30, 16);12166 12167static inline void mlxsw_reg_tngcr_pack(char *payload,12168					enum mlxsw_reg_tngcr_type type,12169					bool valid, u8 ttl)12170{12171	MLXSW_REG_ZERO(tngcr, payload);12172	mlxsw_reg_tngcr_type_set(payload, type);12173	mlxsw_reg_tngcr_nve_valid_set(payload, valid);12174	mlxsw_reg_tngcr_nve_ttl_uc_set(payload, ttl);12175	mlxsw_reg_tngcr_nve_ttl_mc_set(payload, ttl);12176	mlxsw_reg_tngcr_nve_flc_set(payload, MLXSW_REG_TNGCR_FL_NO_COPY);12177	mlxsw_reg_tngcr_nve_flh_set(payload, 0);12178	mlxsw_reg_tngcr_nve_udp_sport_type_set(payload,12179					       MLXSW_REG_TNGCR_UDP_SPORT_HASH);12180	mlxsw_reg_tngcr_nve_udp_sport_prefix_set(payload, 0);12181	mlxsw_reg_tngcr_nve_group_size_mc_set(payload, 1);12182	mlxsw_reg_tngcr_nve_group_size_flood_set(payload, 1);12183}12184 12185/* TNUMT - Tunneling NVE Underlay Multicast Table Register12186 * -------------------------------------------------------12187 * The TNUMT register is for building the underlay MC table. It is used12188 * for MC, flooding and BC traffic into the NVE tunnel.12189 */12190#define MLXSW_REG_TNUMT_ID 0xA00312191#define MLXSW_REG_TNUMT_LEN 0x2012192 12193MLXSW_REG_DEFINE(tnumt, MLXSW_REG_TNUMT_ID, MLXSW_REG_TNUMT_LEN);12194 12195enum mlxsw_reg_tnumt_record_type {12196	MLXSW_REG_TNUMT_RECORD_TYPE_IPV4,12197	MLXSW_REG_TNUMT_RECORD_TYPE_IPV6,12198	MLXSW_REG_TNUMT_RECORD_TYPE_LABEL,12199};12200 12201/* reg_tnumt_record_type12202 * Record type.12203 * Access: RW12204 */12205MLXSW_ITEM32(reg, tnumt, record_type, 0x00, 28, 4);12206 12207/* reg_tnumt_tunnel_port12208 * Tunnel port.12209 * Access: RW12210 */12211MLXSW_ITEM32(reg, tnumt, tunnel_port, 0x00, 24, 4);12212 12213/* reg_tnumt_underlay_mc_ptr12214 * Index to the underlay multicast table.12215 * For Spectrum the index is to the KVD linear.12216 * Access: Index12217 */12218MLXSW_ITEM32(reg, tnumt, underlay_mc_ptr, 0x00, 0, 24);12219 12220/* reg_tnumt_vnext12221 * The next_underlay_mc_ptr is valid.12222 * Access: RW12223 */12224MLXSW_ITEM32(reg, tnumt, vnext, 0x04, 31, 1);12225 12226/* reg_tnumt_next_underlay_mc_ptr12227 * The next index to the underlay multicast table.12228 * Access: RW12229 */12230MLXSW_ITEM32(reg, tnumt, next_underlay_mc_ptr, 0x04, 0, 24);12231 12232/* reg_tnumt_record_size12233 * Number of IP addresses in the record.12234 * Range is 1..cap_max_nve_mc_entries_ipv{4,6}12235 * Access: RW12236 */12237MLXSW_ITEM32(reg, tnumt, record_size, 0x08, 0, 3);12238 12239/* reg_tnumt_udip12240 * The underlay IPv4 addresses. udip[i] is reserved if i >= size12241 * Access: RW12242 */12243MLXSW_ITEM32_INDEXED(reg, tnumt, udip, 0x0C, 0, 32, 0x04, 0x00, false);12244 12245/* reg_tnumt_udip_ptr12246 * The pointer to the underlay IPv6 addresses. udip_ptr[i] is reserved if12247 * i >= size. The IPv6 addresses are configured by RIPS.12248 * Access: RW12249 */12250MLXSW_ITEM32_INDEXED(reg, tnumt, udip_ptr, 0x0C, 0, 24, 0x04, 0x00, false);12251 12252static inline void mlxsw_reg_tnumt_pack(char *payload,12253					enum mlxsw_reg_tnumt_record_type type,12254					enum mlxsw_reg_tunnel_port tport,12255					u32 underlay_mc_ptr, bool vnext,12256					u32 next_underlay_mc_ptr,12257					u8 record_size)12258{12259	MLXSW_REG_ZERO(tnumt, payload);12260	mlxsw_reg_tnumt_record_type_set(payload, type);12261	mlxsw_reg_tnumt_tunnel_port_set(payload, tport);12262	mlxsw_reg_tnumt_underlay_mc_ptr_set(payload, underlay_mc_ptr);12263	mlxsw_reg_tnumt_vnext_set(payload, vnext);12264	mlxsw_reg_tnumt_next_underlay_mc_ptr_set(payload, next_underlay_mc_ptr);12265	mlxsw_reg_tnumt_record_size_set(payload, record_size);12266}12267 12268/* TNQCR - Tunneling NVE QoS Configuration Register12269 * ------------------------------------------------12270 * The TNQCR register configures how QoS is set in encapsulation into the12271 * underlay network.12272 */12273#define MLXSW_REG_TNQCR_ID 0xA01012274#define MLXSW_REG_TNQCR_LEN 0x0C12275 12276MLXSW_REG_DEFINE(tnqcr, MLXSW_REG_TNQCR_ID, MLXSW_REG_TNQCR_LEN);12277 12278/* reg_tnqcr_enc_set_dscp12279 * For encapsulation: How to set DSCP field:12280 * 0 - Copy the DSCP from the overlay (inner) IP header to the underlay12281 * (outer) IP header. If there is no IP header, use TNQDR.dscp12282 * 1 - Set the DSCP field as TNQDR.dscp12283 * Access: RW12284 */12285MLXSW_ITEM32(reg, tnqcr, enc_set_dscp, 0x04, 28, 1);12286 12287static inline void mlxsw_reg_tnqcr_pack(char *payload)12288{12289	MLXSW_REG_ZERO(tnqcr, payload);12290	mlxsw_reg_tnqcr_enc_set_dscp_set(payload, 0);12291}12292 12293/* TNQDR - Tunneling NVE QoS Default Register12294 * ------------------------------------------12295 * The TNQDR register configures the default QoS settings for NVE12296 * encapsulation.12297 */12298#define MLXSW_REG_TNQDR_ID 0xA01112299#define MLXSW_REG_TNQDR_LEN 0x0812300 12301MLXSW_REG_DEFINE(tnqdr, MLXSW_REG_TNQDR_ID, MLXSW_REG_TNQDR_LEN);12302 12303/* reg_tnqdr_local_port12304 * Local port number (receive port). CPU port is supported.12305 * Access: Index12306 */12307MLXSW_ITEM32_LP(reg, tnqdr, 0x00, 16, 0x00, 12);12308 12309/* reg_tnqdr_dscp12310 * For encapsulation, the default DSCP.12311 * Access: RW12312 */12313MLXSW_ITEM32(reg, tnqdr, dscp, 0x04, 0, 6);12314 12315static inline void mlxsw_reg_tnqdr_pack(char *payload, u16 local_port)12316{12317	MLXSW_REG_ZERO(tnqdr, payload);12318	mlxsw_reg_tnqdr_local_port_set(payload, local_port);12319	mlxsw_reg_tnqdr_dscp_set(payload, 0);12320}12321 12322/* TNEEM - Tunneling NVE Encapsulation ECN Mapping Register12323 * --------------------------------------------------------12324 * The TNEEM register maps ECN of the IP header at the ingress to the12325 * encapsulation to the ECN of the underlay network.12326 */12327#define MLXSW_REG_TNEEM_ID 0xA01212328#define MLXSW_REG_TNEEM_LEN 0x0C12329 12330MLXSW_REG_DEFINE(tneem, MLXSW_REG_TNEEM_ID, MLXSW_REG_TNEEM_LEN);12331 12332/* reg_tneem_overlay_ecn12333 * ECN of the IP header in the overlay network.12334 * Access: Index12335 */12336MLXSW_ITEM32(reg, tneem, overlay_ecn, 0x04, 24, 2);12337 12338/* reg_tneem_underlay_ecn12339 * ECN of the IP header in the underlay network.12340 * Access: RW12341 */12342MLXSW_ITEM32(reg, tneem, underlay_ecn, 0x04, 16, 2);12343 12344static inline void mlxsw_reg_tneem_pack(char *payload, u8 overlay_ecn,12345					u8 underlay_ecn)12346{12347	MLXSW_REG_ZERO(tneem, payload);12348	mlxsw_reg_tneem_overlay_ecn_set(payload, overlay_ecn);12349	mlxsw_reg_tneem_underlay_ecn_set(payload, underlay_ecn);12350}12351 12352/* TNDEM - Tunneling NVE Decapsulation ECN Mapping Register12353 * --------------------------------------------------------12354 * The TNDEM register configures the actions that are done in the12355 * decapsulation.12356 */12357#define MLXSW_REG_TNDEM_ID 0xA01312358#define MLXSW_REG_TNDEM_LEN 0x0C12359 12360MLXSW_REG_DEFINE(tndem, MLXSW_REG_TNDEM_ID, MLXSW_REG_TNDEM_LEN);12361 12362/* reg_tndem_underlay_ecn12363 * ECN field of the IP header in the underlay network.12364 * Access: Index12365 */12366MLXSW_ITEM32(reg, tndem, underlay_ecn, 0x04, 24, 2);12367 12368/* reg_tndem_overlay_ecn12369 * ECN field of the IP header in the overlay network.12370 * Access: Index12371 */12372MLXSW_ITEM32(reg, tndem, overlay_ecn, 0x04, 16, 2);12373 12374/* reg_tndem_eip_ecn12375 * Egress IP ECN. ECN field of the IP header of the packet which goes out12376 * from the decapsulation.12377 * Access: RW12378 */12379MLXSW_ITEM32(reg, tndem, eip_ecn, 0x04, 8, 2);12380 12381/* reg_tndem_trap_en12382 * Trap enable:12383 * 0 - No trap due to decap ECN12384 * 1 - Trap enable with trap_id12385 * Access: RW12386 */12387MLXSW_ITEM32(reg, tndem, trap_en, 0x08, 28, 4);12388 12389/* reg_tndem_trap_id12390 * Trap ID. Either DECAP_ECN0 or DECAP_ECN1.12391 * Reserved when trap_en is '0'.12392 * Access: RW12393 */12394MLXSW_ITEM32(reg, tndem, trap_id, 0x08, 0, 9);12395 12396static inline void mlxsw_reg_tndem_pack(char *payload, u8 underlay_ecn,12397					u8 overlay_ecn, u8 ecn, bool trap_en,12398					u16 trap_id)12399{12400	MLXSW_REG_ZERO(tndem, payload);12401	mlxsw_reg_tndem_underlay_ecn_set(payload, underlay_ecn);12402	mlxsw_reg_tndem_overlay_ecn_set(payload, overlay_ecn);12403	mlxsw_reg_tndem_eip_ecn_set(payload, ecn);12404	mlxsw_reg_tndem_trap_en_set(payload, trap_en);12405	mlxsw_reg_tndem_trap_id_set(payload, trap_id);12406}12407 12408/* TNPC - Tunnel Port Configuration Register12409 * -----------------------------------------12410 * The TNPC register is used for tunnel port configuration.12411 * Reserved when Spectrum.12412 */12413#define MLXSW_REG_TNPC_ID 0xA02012414#define MLXSW_REG_TNPC_LEN 0x1812415 12416MLXSW_REG_DEFINE(tnpc, MLXSW_REG_TNPC_ID, MLXSW_REG_TNPC_LEN);12417 12418/* reg_tnpc_tunnel_port12419 * Tunnel port.12420 * Access: Index12421 */12422MLXSW_ITEM32(reg, tnpc, tunnel_port, 0x00, 0, 4);12423 12424/* reg_tnpc_learn_enable_v612425 * During IPv6 underlay decapsulation, whether to learn from tunnel port.12426 * Access: RW12427 */12428MLXSW_ITEM32(reg, tnpc, learn_enable_v6, 0x04, 1, 1);12429 12430/* reg_tnpc_learn_enable_v412431 * During IPv4 underlay decapsulation, whether to learn from tunnel port.12432 * Access: RW12433 */12434MLXSW_ITEM32(reg, tnpc, learn_enable_v4, 0x04, 0, 1);12435 12436static inline void mlxsw_reg_tnpc_pack(char *payload,12437				       enum mlxsw_reg_tunnel_port tport,12438				       bool learn_enable)12439{12440	MLXSW_REG_ZERO(tnpc, payload);12441	mlxsw_reg_tnpc_tunnel_port_set(payload, tport);12442	mlxsw_reg_tnpc_learn_enable_v4_set(payload, learn_enable);12443	mlxsw_reg_tnpc_learn_enable_v6_set(payload, learn_enable);12444}12445 12446/* TIGCR - Tunneling IPinIP General Configuration Register12447 * -------------------------------------------------------12448 * The TIGCR register is used for setting up the IPinIP Tunnel configuration.12449 */12450#define MLXSW_REG_TIGCR_ID 0xA80112451#define MLXSW_REG_TIGCR_LEN 0x1012452 12453MLXSW_REG_DEFINE(tigcr, MLXSW_REG_TIGCR_ID, MLXSW_REG_TIGCR_LEN);12454 12455/* reg_tigcr_ipip_ttlc12456 * For IPinIP Tunnel encapsulation: whether to copy the ttl from the packet12457 * header.12458 * Access: RW12459 */12460MLXSW_ITEM32(reg, tigcr, ttlc, 0x04, 8, 1);12461 12462/* reg_tigcr_ipip_ttl_uc12463 * The TTL for IPinIP Tunnel encapsulation of unicast packets if12464 * reg_tigcr_ipip_ttlc is unset.12465 * Access: RW12466 */12467MLXSW_ITEM32(reg, tigcr, ttl_uc, 0x04, 0, 8);12468 12469static inline void mlxsw_reg_tigcr_pack(char *payload, bool ttlc, u8 ttl_uc)12470{12471	MLXSW_REG_ZERO(tigcr, payload);12472	mlxsw_reg_tigcr_ttlc_set(payload, ttlc);12473	mlxsw_reg_tigcr_ttl_uc_set(payload, ttl_uc);12474}12475 12476/* TIEEM - Tunneling IPinIP Encapsulation ECN Mapping Register12477 * -----------------------------------------------------------12478 * The TIEEM register maps ECN of the IP header at the ingress to the12479 * encapsulation to the ECN of the underlay network.12480 */12481#define MLXSW_REG_TIEEM_ID 0xA81212482#define MLXSW_REG_TIEEM_LEN 0x0C12483 12484MLXSW_REG_DEFINE(tieem, MLXSW_REG_TIEEM_ID, MLXSW_REG_TIEEM_LEN);12485 12486/* reg_tieem_overlay_ecn12487 * ECN of the IP header in the overlay network.12488 * Access: Index12489 */12490MLXSW_ITEM32(reg, tieem, overlay_ecn, 0x04, 24, 2);12491 12492/* reg_tineem_underlay_ecn12493 * ECN of the IP header in the underlay network.12494 * Access: RW12495 */12496MLXSW_ITEM32(reg, tieem, underlay_ecn, 0x04, 16, 2);12497 12498static inline void mlxsw_reg_tieem_pack(char *payload, u8 overlay_ecn,12499					u8 underlay_ecn)12500{12501	MLXSW_REG_ZERO(tieem, payload);12502	mlxsw_reg_tieem_overlay_ecn_set(payload, overlay_ecn);12503	mlxsw_reg_tieem_underlay_ecn_set(payload, underlay_ecn);12504}12505 12506/* TIDEM - Tunneling IPinIP Decapsulation ECN Mapping Register12507 * -----------------------------------------------------------12508 * The TIDEM register configures the actions that are done in the12509 * decapsulation.12510 */12511#define MLXSW_REG_TIDEM_ID 0xA81312512#define MLXSW_REG_TIDEM_LEN 0x0C12513 12514MLXSW_REG_DEFINE(tidem, MLXSW_REG_TIDEM_ID, MLXSW_REG_TIDEM_LEN);12515 12516/* reg_tidem_underlay_ecn12517 * ECN field of the IP header in the underlay network.12518 * Access: Index12519 */12520MLXSW_ITEM32(reg, tidem, underlay_ecn, 0x04, 24, 2);12521 12522/* reg_tidem_overlay_ecn12523 * ECN field of the IP header in the overlay network.12524 * Access: Index12525 */12526MLXSW_ITEM32(reg, tidem, overlay_ecn, 0x04, 16, 2);12527 12528/* reg_tidem_eip_ecn12529 * Egress IP ECN. ECN field of the IP header of the packet which goes out12530 * from the decapsulation.12531 * Access: RW12532 */12533MLXSW_ITEM32(reg, tidem, eip_ecn, 0x04, 8, 2);12534 12535/* reg_tidem_trap_en12536 * Trap enable:12537 * 0 - No trap due to decap ECN12538 * 1 - Trap enable with trap_id12539 * Access: RW12540 */12541MLXSW_ITEM32(reg, tidem, trap_en, 0x08, 28, 4);12542 12543/* reg_tidem_trap_id12544 * Trap ID. Either DECAP_ECN0 or DECAP_ECN1.12545 * Reserved when trap_en is '0'.12546 * Access: RW12547 */12548MLXSW_ITEM32(reg, tidem, trap_id, 0x08, 0, 9);12549 12550static inline void mlxsw_reg_tidem_pack(char *payload, u8 underlay_ecn,12551					u8 overlay_ecn, u8 eip_ecn,12552					bool trap_en, u16 trap_id)12553{12554	MLXSW_REG_ZERO(tidem, payload);12555	mlxsw_reg_tidem_underlay_ecn_set(payload, underlay_ecn);12556	mlxsw_reg_tidem_overlay_ecn_set(payload, overlay_ecn);12557	mlxsw_reg_tidem_eip_ecn_set(payload, eip_ecn);12558	mlxsw_reg_tidem_trap_en_set(payload, trap_en);12559	mlxsw_reg_tidem_trap_id_set(payload, trap_id);12560}12561 12562/* SBPR - Shared Buffer Pools Register12563 * -----------------------------------12564 * The SBPR configures and retrieves the shared buffer pools and configuration.12565 */12566#define MLXSW_REG_SBPR_ID 0xB00112567#define MLXSW_REG_SBPR_LEN 0x1412568 12569MLXSW_REG_DEFINE(sbpr, MLXSW_REG_SBPR_ID, MLXSW_REG_SBPR_LEN);12570 12571/* reg_sbpr_desc12572 * When set, configures descriptor buffer.12573 * Access: Index12574 */12575MLXSW_ITEM32(reg, sbpr, desc, 0x00, 31, 1);12576 12577/* shared direstion enum for SBPR, SBCM, SBPM */12578enum mlxsw_reg_sbxx_dir {12579	MLXSW_REG_SBXX_DIR_INGRESS,12580	MLXSW_REG_SBXX_DIR_EGRESS,12581};12582 12583/* reg_sbpr_dir12584 * Direction.12585 * Access: Index12586 */12587MLXSW_ITEM32(reg, sbpr, dir, 0x00, 24, 2);12588 12589/* reg_sbpr_pool12590 * Pool index.12591 * Access: Index12592 */12593MLXSW_ITEM32(reg, sbpr, pool, 0x00, 0, 4);12594 12595/* reg_sbpr_infi_size12596 * Size is infinite.12597 * Access: RW12598 */12599MLXSW_ITEM32(reg, sbpr, infi_size, 0x04, 31, 1);12600 12601/* reg_sbpr_size12602 * Pool size in buffer cells.12603 * Reserved when infi_size = 1.12604 * Access: RW12605 */12606MLXSW_ITEM32(reg, sbpr, size, 0x04, 0, 24);12607 12608enum mlxsw_reg_sbpr_mode {12609	MLXSW_REG_SBPR_MODE_STATIC,12610	MLXSW_REG_SBPR_MODE_DYNAMIC,12611};12612 12613/* reg_sbpr_mode12614 * Pool quota calculation mode.12615 * Access: RW12616 */12617MLXSW_ITEM32(reg, sbpr, mode, 0x08, 0, 4);12618 12619static inline void mlxsw_reg_sbpr_pack(char *payload, u8 pool,12620				       enum mlxsw_reg_sbxx_dir dir,12621				       enum mlxsw_reg_sbpr_mode mode, u32 size,12622				       bool infi_size)12623{12624	MLXSW_REG_ZERO(sbpr, payload);12625	mlxsw_reg_sbpr_pool_set(payload, pool);12626	mlxsw_reg_sbpr_dir_set(payload, dir);12627	mlxsw_reg_sbpr_mode_set(payload, mode);12628	mlxsw_reg_sbpr_size_set(payload, size);12629	mlxsw_reg_sbpr_infi_size_set(payload, infi_size);12630}12631 12632/* SBCM - Shared Buffer Class Management Register12633 * ----------------------------------------------12634 * The SBCM register configures and retrieves the shared buffer allocation12635 * and configuration according to Port-PG, including the binding to pool12636 * and definition of the associated quota.12637 */12638#define MLXSW_REG_SBCM_ID 0xB00212639#define MLXSW_REG_SBCM_LEN 0x2812640 12641MLXSW_REG_DEFINE(sbcm, MLXSW_REG_SBCM_ID, MLXSW_REG_SBCM_LEN);12642 12643/* reg_sbcm_local_port12644 * Local port number.12645 * For Ingress: excludes CPU port and Router port12646 * For Egress: excludes IP Router12647 * Access: Index12648 */12649MLXSW_ITEM32_LP(reg, sbcm, 0x00, 16, 0x00, 4);12650 12651/* reg_sbcm_pg_buff12652 * PG buffer - Port PG (dir=ingress) / traffic class (dir=egress)12653 * For PG buffer: range is 0..cap_max_pg_buffers - 112654 * For traffic class: range is 0..cap_max_tclass - 112655 * Note that when traffic class is in MC aware mode then the traffic12656 * classes which are MC aware cannot be configured.12657 * Access: Index12658 */12659MLXSW_ITEM32(reg, sbcm, pg_buff, 0x00, 8, 6);12660 12661/* reg_sbcm_dir12662 * Direction.12663 * Access: Index12664 */12665MLXSW_ITEM32(reg, sbcm, dir, 0x00, 0, 2);12666 12667/* reg_sbcm_min_buff12668 * Minimum buffer size for the limiter, in cells.12669 * Access: RW12670 */12671MLXSW_ITEM32(reg, sbcm, min_buff, 0x18, 0, 24);12672 12673/* shared max_buff limits for dynamic threshold for SBCM, SBPM */12674#define MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN 112675#define MLXSW_REG_SBXX_DYN_MAX_BUFF_MAX 1412676 12677/* reg_sbcm_infi_max12678 * Max buffer is infinite.12679 * Access: RW12680 */12681MLXSW_ITEM32(reg, sbcm, infi_max, 0x1C, 31, 1);12682 12683/* reg_sbcm_max_buff12684 * When the pool associated to the port-pg/tclass is configured to12685 * static, Maximum buffer size for the limiter configured in cells.12686 * When the pool associated to the port-pg/tclass is configured to12687 * dynamic, the max_buff holds the "alpha" parameter, supporting12688 * the following values:12689 * 0: 012690 * i: (1/128)*2^(i-1), for i=1..1412691 * 0xFF: Infinity12692 * Reserved when infi_max = 1.12693 * Access: RW12694 */12695MLXSW_ITEM32(reg, sbcm, max_buff, 0x1C, 0, 24);12696 12697/* reg_sbcm_pool12698 * Association of the port-priority to a pool.12699 * Access: RW12700 */12701MLXSW_ITEM32(reg, sbcm, pool, 0x24, 0, 4);12702 12703static inline void mlxsw_reg_sbcm_pack(char *payload, u16 local_port, u8 pg_buff,12704				       enum mlxsw_reg_sbxx_dir dir,12705				       u32 min_buff, u32 max_buff,12706				       bool infi_max, u8 pool)12707{12708	MLXSW_REG_ZERO(sbcm, payload);12709	mlxsw_reg_sbcm_local_port_set(payload, local_port);12710	mlxsw_reg_sbcm_pg_buff_set(payload, pg_buff);12711	mlxsw_reg_sbcm_dir_set(payload, dir);12712	mlxsw_reg_sbcm_min_buff_set(payload, min_buff);12713	mlxsw_reg_sbcm_max_buff_set(payload, max_buff);12714	mlxsw_reg_sbcm_infi_max_set(payload, infi_max);12715	mlxsw_reg_sbcm_pool_set(payload, pool);12716}12717 12718/* SBPM - Shared Buffer Port Management Register12719 * ---------------------------------------------12720 * The SBPM register configures and retrieves the shared buffer allocation12721 * and configuration according to Port-Pool, including the definition12722 * of the associated quota.12723 */12724#define MLXSW_REG_SBPM_ID 0xB00312725#define MLXSW_REG_SBPM_LEN 0x2812726 12727MLXSW_REG_DEFINE(sbpm, MLXSW_REG_SBPM_ID, MLXSW_REG_SBPM_LEN);12728 12729/* reg_sbpm_local_port12730 * Local port number.12731 * For Ingress: excludes CPU port and Router port12732 * For Egress: excludes IP Router12733 * Access: Index12734 */12735MLXSW_ITEM32_LP(reg, sbpm, 0x00, 16, 0x00, 12);12736 12737/* reg_sbpm_pool12738 * The pool associated to quota counting on the local_port.12739 * Access: Index12740 */12741MLXSW_ITEM32(reg, sbpm, pool, 0x00, 8, 4);12742 12743/* reg_sbpm_dir12744 * Direction.12745 * Access: Index12746 */12747MLXSW_ITEM32(reg, sbpm, dir, 0x00, 0, 2);12748 12749/* reg_sbpm_buff_occupancy12750 * Current buffer occupancy in cells.12751 * Access: RO12752 */12753MLXSW_ITEM32(reg, sbpm, buff_occupancy, 0x10, 0, 24);12754 12755/* reg_sbpm_clr12756 * Clear Max Buffer Occupancy12757 * When this bit is set, max_buff_occupancy field is cleared (and a12758 * new max value is tracked from the time the clear was performed).12759 * Access: OP12760 */12761MLXSW_ITEM32(reg, sbpm, clr, 0x14, 31, 1);12762 12763/* reg_sbpm_max_buff_occupancy12764 * Maximum value of buffer occupancy in cells monitored. Cleared by12765 * writing to the clr field.12766 * Access: RO12767 */12768MLXSW_ITEM32(reg, sbpm, max_buff_occupancy, 0x14, 0, 24);12769 12770/* reg_sbpm_min_buff12771 * Minimum buffer size for the limiter, in cells.12772 * Access: RW12773 */12774MLXSW_ITEM32(reg, sbpm, min_buff, 0x18, 0, 24);12775 12776/* reg_sbpm_max_buff12777 * When the pool associated to the port-pg/tclass is configured to12778 * static, Maximum buffer size for the limiter configured in cells.12779 * When the pool associated to the port-pg/tclass is configured to12780 * dynamic, the max_buff holds the "alpha" parameter, supporting12781 * the following values:12782 * 0: 012783 * i: (1/128)*2^(i-1), for i=1..1412784 * 0xFF: Infinity12785 * Access: RW12786 */12787MLXSW_ITEM32(reg, sbpm, max_buff, 0x1C, 0, 24);12788 12789static inline void mlxsw_reg_sbpm_pack(char *payload, u16 local_port, u8 pool,12790				       enum mlxsw_reg_sbxx_dir dir, bool clr,12791				       u32 min_buff, u32 max_buff)12792{12793	MLXSW_REG_ZERO(sbpm, payload);12794	mlxsw_reg_sbpm_local_port_set(payload, local_port);12795	mlxsw_reg_sbpm_pool_set(payload, pool);12796	mlxsw_reg_sbpm_dir_set(payload, dir);12797	mlxsw_reg_sbpm_clr_set(payload, clr);12798	mlxsw_reg_sbpm_min_buff_set(payload, min_buff);12799	mlxsw_reg_sbpm_max_buff_set(payload, max_buff);12800}12801 12802static inline void mlxsw_reg_sbpm_unpack(char *payload, u32 *p_buff_occupancy,12803					 u32 *p_max_buff_occupancy)12804{12805	*p_buff_occupancy = mlxsw_reg_sbpm_buff_occupancy_get(payload);12806	*p_max_buff_occupancy = mlxsw_reg_sbpm_max_buff_occupancy_get(payload);12807}12808 12809/* SBMM - Shared Buffer Multicast Management Register12810 * --------------------------------------------------12811 * The SBMM register configures and retrieves the shared buffer allocation12812 * and configuration for MC packets according to Switch-Priority, including12813 * the binding to pool and definition of the associated quota.12814 */12815#define MLXSW_REG_SBMM_ID 0xB00412816#define MLXSW_REG_SBMM_LEN 0x2812817 12818MLXSW_REG_DEFINE(sbmm, MLXSW_REG_SBMM_ID, MLXSW_REG_SBMM_LEN);12819 12820/* reg_sbmm_prio12821 * Switch Priority.12822 * Access: Index12823 */12824MLXSW_ITEM32(reg, sbmm, prio, 0x00, 8, 4);12825 12826/* reg_sbmm_min_buff12827 * Minimum buffer size for the limiter, in cells.12828 * Access: RW12829 */12830MLXSW_ITEM32(reg, sbmm, min_buff, 0x18, 0, 24);12831 12832/* reg_sbmm_max_buff12833 * When the pool associated to the port-pg/tclass is configured to12834 * static, Maximum buffer size for the limiter configured in cells.12835 * When the pool associated to the port-pg/tclass is configured to12836 * dynamic, the max_buff holds the "alpha" parameter, supporting12837 * the following values:12838 * 0: 012839 * i: (1/128)*2^(i-1), for i=1..1412840 * 0xFF: Infinity12841 * Access: RW12842 */12843MLXSW_ITEM32(reg, sbmm, max_buff, 0x1C, 0, 24);12844 12845/* reg_sbmm_pool12846 * Association of the port-priority to a pool.12847 * Access: RW12848 */12849MLXSW_ITEM32(reg, sbmm, pool, 0x24, 0, 4);12850 12851static inline void mlxsw_reg_sbmm_pack(char *payload, u8 prio, u32 min_buff,12852				       u32 max_buff, u8 pool)12853{12854	MLXSW_REG_ZERO(sbmm, payload);12855	mlxsw_reg_sbmm_prio_set(payload, prio);12856	mlxsw_reg_sbmm_min_buff_set(payload, min_buff);12857	mlxsw_reg_sbmm_max_buff_set(payload, max_buff);12858	mlxsw_reg_sbmm_pool_set(payload, pool);12859}12860 12861/* SBSR - Shared Buffer Status Register12862 * ------------------------------------12863 * The SBSR register retrieves the shared buffer occupancy according to12864 * Port-Pool. Note that this register enables reading a large amount of data.12865 * It is the user's responsibility to limit the amount of data to ensure the12866 * response can match the maximum transfer unit. In case the response exceeds12867 * the maximum transport unit, it will be truncated with no special notice.12868 */12869#define MLXSW_REG_SBSR_ID 0xB00512870#define MLXSW_REG_SBSR_BASE_LEN 0x5C /* base length, without records */12871#define MLXSW_REG_SBSR_REC_LEN 0x8 /* record length */12872#define MLXSW_REG_SBSR_REC_MAX_COUNT 12012873#define MLXSW_REG_SBSR_LEN (MLXSW_REG_SBSR_BASE_LEN +	\12874			    MLXSW_REG_SBSR_REC_LEN *	\12875			    MLXSW_REG_SBSR_REC_MAX_COUNT)12876 12877MLXSW_REG_DEFINE(sbsr, MLXSW_REG_SBSR_ID, MLXSW_REG_SBSR_LEN);12878 12879/* reg_sbsr_clr12880 * Clear Max Buffer Occupancy. When this bit is set, the max_buff_occupancy12881 * field is cleared (and a new max value is tracked from the time the clear12882 * was performed).12883 * Access: OP12884 */12885MLXSW_ITEM32(reg, sbsr, clr, 0x00, 31, 1);12886 12887#define MLXSW_REG_SBSR_NUM_PORTS_IN_PAGE 25612888 12889/* reg_sbsr_port_page12890 * Determines the range of the ports specified in the 'ingress_port_mask'12891 * and 'egress_port_mask' bit masks.12892 * {ingress,egress}_port_mask[x] is (256 * port_page) + x12893 * Access: Index12894 */12895MLXSW_ITEM32(reg, sbsr, port_page, 0x04, 0, 4);12896 12897/* reg_sbsr_ingress_port_mask12898 * Bit vector for all ingress network ports.12899 * Indicates which of the ports (for which the relevant bit is set)12900 * are affected by the set operation. Configuration of any other port12901 * does not change.12902 * Access: Index12903 */12904MLXSW_ITEM_BIT_ARRAY(reg, sbsr, ingress_port_mask, 0x10, 0x20, 1);12905 12906/* reg_sbsr_pg_buff_mask12907 * Bit vector for all switch priority groups.12908 * Indicates which of the priorities (for which the relevant bit is set)12909 * are affected by the set operation. Configuration of any other priority12910 * does not change.12911 * Range is 0..cap_max_pg_buffers - 112912 * Access: Index12913 */12914MLXSW_ITEM_BIT_ARRAY(reg, sbsr, pg_buff_mask, 0x30, 0x4, 1);12915 12916/* reg_sbsr_egress_port_mask12917 * Bit vector for all egress network ports.12918 * Indicates which of the ports (for which the relevant bit is set)12919 * are affected by the set operation. Configuration of any other port12920 * does not change.12921 * Access: Index12922 */12923MLXSW_ITEM_BIT_ARRAY(reg, sbsr, egress_port_mask, 0x34, 0x20, 1);12924 12925/* reg_sbsr_tclass_mask12926 * Bit vector for all traffic classes.12927 * Indicates which of the traffic classes (for which the relevant bit is12928 * set) are affected by the set operation. Configuration of any other12929 * traffic class does not change.12930 * Range is 0..cap_max_tclass - 112931 * Access: Index12932 */12933MLXSW_ITEM_BIT_ARRAY(reg, sbsr, tclass_mask, 0x54, 0x8, 1);12934 12935static inline void mlxsw_reg_sbsr_pack(char *payload, bool clr)12936{12937	MLXSW_REG_ZERO(sbsr, payload);12938	mlxsw_reg_sbsr_clr_set(payload, clr);12939}12940 12941/* reg_sbsr_rec_buff_occupancy12942 * Current buffer occupancy in cells.12943 * Access: RO12944 */12945MLXSW_ITEM32_INDEXED(reg, sbsr, rec_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN,12946		     0, 24, MLXSW_REG_SBSR_REC_LEN, 0x00, false);12947 12948/* reg_sbsr_rec_max_buff_occupancy12949 * Maximum value of buffer occupancy in cells monitored. Cleared by12950 * writing to the clr field.12951 * Access: RO12952 */12953MLXSW_ITEM32_INDEXED(reg, sbsr, rec_max_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN,12954		     0, 24, MLXSW_REG_SBSR_REC_LEN, 0x04, false);12955 12956static inline void mlxsw_reg_sbsr_rec_unpack(char *payload, int rec_index,12957					     u32 *p_buff_occupancy,12958					     u32 *p_max_buff_occupancy)12959{12960	*p_buff_occupancy =12961		mlxsw_reg_sbsr_rec_buff_occupancy_get(payload, rec_index);12962	*p_max_buff_occupancy =12963		mlxsw_reg_sbsr_rec_max_buff_occupancy_get(payload, rec_index);12964}12965 12966/* SBIB - Shared Buffer Internal Buffer Register12967 * ---------------------------------------------12968 * The SBIB register configures per port buffers for internal use. The internal12969 * buffers consume memory on the port buffers (note that the port buffers are12970 * used also by PBMC).12971 *12972 * For Spectrum this is used for egress mirroring.12973 */12974#define MLXSW_REG_SBIB_ID 0xB00612975#define MLXSW_REG_SBIB_LEN 0x1012976 12977MLXSW_REG_DEFINE(sbib, MLXSW_REG_SBIB_ID, MLXSW_REG_SBIB_LEN);12978 12979/* reg_sbib_local_port12980 * Local port number12981 * Not supported for CPU port and router port12982 * Access: Index12983 */12984MLXSW_ITEM32_LP(reg, sbib, 0x00, 16, 0x00, 12);12985 12986/* reg_sbib_buff_size12987 * Units represented in cells12988 * Allowed range is 0 to (cap_max_headroom_size - 1)12989 * Default is 012990 * Access: RW12991 */12992MLXSW_ITEM32(reg, sbib, buff_size, 0x08, 0, 24);12993 12994static inline void mlxsw_reg_sbib_pack(char *payload, u16 local_port,12995				       u32 buff_size)12996{12997	MLXSW_REG_ZERO(sbib, payload);12998	mlxsw_reg_sbib_local_port_set(payload, local_port);12999	mlxsw_reg_sbib_buff_size_set(payload, buff_size);13000}13001 13002static const struct mlxsw_reg_info *mlxsw_reg_infos[] = {13003	MLXSW_REG(sgcr),13004	MLXSW_REG(spad),13005	MLXSW_REG(sspr),13006	MLXSW_REG(sfdat),13007	MLXSW_REG(sfd),13008	MLXSW_REG(sfn),13009	MLXSW_REG(spms),13010	MLXSW_REG(spvid),13011	MLXSW_REG(spvm),13012	MLXSW_REG(spaft),13013	MLXSW_REG(sfgc),13014	MLXSW_REG(sfdf),13015	MLXSW_REG(sldr),13016	MLXSW_REG(slcr),13017	MLXSW_REG(slcor),13018	MLXSW_REG(spmlr),13019	MLXSW_REG(svfa),13020	MLXSW_REG(spvtr),13021	MLXSW_REG(svpe),13022	MLXSW_REG(sfmr),13023	MLXSW_REG(spvmlr),13024	MLXSW_REG(spfsr),13025	MLXSW_REG(spvc),13026	MLXSW_REG(sffp),13027	MLXSW_REG(spevet),13028	MLXSW_REG(smpe),13029	MLXSW_REG(smid2),13030	MLXSW_REG(cwtp),13031	MLXSW_REG(cwtpm),13032	MLXSW_REG(pgcr),13033	MLXSW_REG(ppbt),13034	MLXSW_REG(pacl),13035	MLXSW_REG(pagt),13036	MLXSW_REG(ptar),13037	MLXSW_REG(pprr),13038	MLXSW_REG(ppbs),13039	MLXSW_REG(prcr),13040	MLXSW_REG(pefa),13041	MLXSW_REG(pemrbt),13042	MLXSW_REG(ptce2),13043	MLXSW_REG(perpt),13044	MLXSW_REG(peabfe),13045	MLXSW_REG(perar),13046	MLXSW_REG(ptce3),13047	MLXSW_REG(percr),13048	MLXSW_REG(pererp),13049	MLXSW_REG(iedr),13050	MLXSW_REG(qpts),13051	MLXSW_REG(qpcr),13052	MLXSW_REG(qtct),13053	MLXSW_REG(qeec),13054	MLXSW_REG(qrwe),13055	MLXSW_REG(qpdsm),13056	MLXSW_REG(qpdp),13057	MLXSW_REG(qpdpm),13058	MLXSW_REG(qtctm),13059	MLXSW_REG(qpsc),13060	MLXSW_REG(pmlp),13061	MLXSW_REG(pmtu),13062	MLXSW_REG(ptys),13063	MLXSW_REG(ppad),13064	MLXSW_REG(paos),13065	MLXSW_REG(pfcc),13066	MLXSW_REG(ppcnt),13067	MLXSW_REG(pptb),13068	MLXSW_REG(pbmc),13069	MLXSW_REG(pspa),13070	MLXSW_REG(pmaos),13071	MLXSW_REG(pplr),13072	MLXSW_REG(pmtdb),13073	MLXSW_REG(pmecr),13074	MLXSW_REG(pmpe),13075	MLXSW_REG(pddr),13076	MLXSW_REG(pmmp),13077	MLXSW_REG(pllp),13078	MLXSW_REG(pmtm),13079	MLXSW_REG(htgt),13080	MLXSW_REG(hpkt),13081	MLXSW_REG(rgcr),13082	MLXSW_REG(ritr),13083	MLXSW_REG(rtar),13084	MLXSW_REG(ratr),13085	MLXSW_REG(rtdp),13086	MLXSW_REG(rips),13087	MLXSW_REG(ratrad),13088	MLXSW_REG(rdpm),13089	MLXSW_REG(ricnt),13090	MLXSW_REG(rrcr),13091	MLXSW_REG(ralta),13092	MLXSW_REG(ralst),13093	MLXSW_REG(raltb),13094	MLXSW_REG(ralue),13095	MLXSW_REG(rauht),13096	MLXSW_REG(raleu),13097	MLXSW_REG(rauhtd),13098	MLXSW_REG(rigr2),13099	MLXSW_REG(recr2),13100	MLXSW_REG(rmft2),13101	MLXSW_REG(reiv),13102	MLXSW_REG(mfcr),13103	MLXSW_REG(mfsc),13104	MLXSW_REG(mfsm),13105	MLXSW_REG(mfsl),13106	MLXSW_REG(fore),13107	MLXSW_REG(mtcap),13108	MLXSW_REG(mtmp),13109	MLXSW_REG(mtwe),13110	MLXSW_REG(mtbr),13111	MLXSW_REG(mcia),13112	MLXSW_REG(mpat),13113	MLXSW_REG(mpar),13114	MLXSW_REG(mgir),13115	MLXSW_REG(mrsr),13116	MLXSW_REG(mlcr),13117	MLXSW_REG(mcion),13118	MLXSW_REG(mtpps),13119	MLXSW_REG(mtutc),13120	MLXSW_REG(mcqi),13121	MLXSW_REG(mcc),13122	MLXSW_REG(mcda),13123	MLXSW_REG(mcam),13124	MLXSW_REG(mpsc),13125	MLXSW_REG(mgpc),13126	MLXSW_REG(mprs),13127	MLXSW_REG(mogcr),13128	MLXSW_REG(mpagr),13129	MLXSW_REG(momte),13130	MLXSW_REG(mtpppc),13131	MLXSW_REG(mtpptr),13132	MLXSW_REG(mtptpt),13133	MLXSW_REG(mtpcpc),13134	MLXSW_REG(mfgd),13135	MLXSW_REG(mgpir),13136	MLXSW_REG(mbct),13137	MLXSW_REG(mddt),13138	MLXSW_REG(mddq),13139	MLXSW_REG(mddc),13140	MLXSW_REG(mfde),13141	MLXSW_REG(tngcr),13142	MLXSW_REG(tnumt),13143	MLXSW_REG(tnqcr),13144	MLXSW_REG(tnqdr),13145	MLXSW_REG(tneem),13146	MLXSW_REG(tndem),13147	MLXSW_REG(tnpc),13148	MLXSW_REG(tigcr),13149	MLXSW_REG(tieem),13150	MLXSW_REG(tidem),13151	MLXSW_REG(sbpr),13152	MLXSW_REG(sbcm),13153	MLXSW_REG(sbpm),13154	MLXSW_REG(sbmm),13155	MLXSW_REG(sbsr),13156	MLXSW_REG(sbib),13157};13158 13159static inline const char *mlxsw_reg_id_str(u16 reg_id)13160{13161	const struct mlxsw_reg_info *reg_info;13162	int i;13163 13164	for (i = 0; i < ARRAY_SIZE(mlxsw_reg_infos); i++) {13165		reg_info = mlxsw_reg_infos[i];13166		if (reg_info->id == reg_id)13167			return reg_info->name;13168	}13169	return "*UNKNOWN*";13170}13171 13172/* PUDE - Port Up / Down Event13173 * ---------------------------13174 * Reports the operational state change of a port.13175 */13176#define MLXSW_REG_PUDE_LEN 0x1013177 13178/* reg_pude_swid13179 * Switch partition ID with which to associate the port.13180 * Access: Index13181 */13182MLXSW_ITEM32(reg, pude, swid, 0x00, 24, 8);13183 13184/* reg_pude_local_port13185 * Local port number.13186 * Access: Index13187 */13188MLXSW_ITEM32_LP(reg, pude, 0x00, 16, 0x00, 12);13189 13190/* reg_pude_admin_status13191 * Port administrative state (the desired state).13192 * 1 - Up.13193 * 2 - Down.13194 * 3 - Up once. This means that in case of link failure, the port won't go13195 *     into polling mode, but will wait to be re-enabled by software.13196 * 4 - Disabled by system. Can only be set by hardware.13197 * Access: RO13198 */13199MLXSW_ITEM32(reg, pude, admin_status, 0x00, 8, 4);13200 13201/* reg_pude_oper_status13202 * Port operatioanl state.13203 * 1 - Up.13204 * 2 - Down.13205 * 3 - Down by port failure. This means that the device will not let the13206 *     port up again until explicitly specified by software.13207 * Access: RO13208 */13209MLXSW_ITEM32(reg, pude, oper_status, 0x00, 0, 4);13210 13211#endif13212