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1/* SPDX-License-Identifier: GPL-2.0 */2/* Copyright (c) Meta Platforms, Inc. and affiliates. */3 4#ifndef _FBNIC_CSR_H_5#define _FBNIC_CSR_H_6 7#include <linux/bitops.h>8 9#define CSR_BIT(nr) (1u << (nr))10#define CSR_GENMASK(h, l) GENMASK(h, l)11 12#define DESC_BIT(nr) BIT_ULL(nr)13#define DESC_GENMASK(h, l) GENMASK_ULL(h, l)14 15/* Defines the minimum firmware version required by the driver */16#define MIN_FW_MAJOR_VERSION 017#define MIN_FW_MINOR_VERSION 1018#define MIN_FW_BUILD_VERSION 619#define MIN_FW_VERSION_CODE (MIN_FW_MAJOR_VERSION * (1u << 24) + \20 MIN_FW_MINOR_VERSION * (1u << 16) + \21 MIN_FW_BUILD_VERSION)22 23#define PCI_DEVICE_ID_META_FBNIC_ASIC 0x001324 25#define FBNIC_CLOCK_FREQ (600 * (1000 * 1000))26 27/* Transmit Work Descriptor Format */28/* Length, Type, Offset Masks and Shifts */29#define FBNIC_TWD_L2_HLEN_MASK DESC_GENMASK(5, 0)30 31#define FBNIC_TWD_L3_TYPE_MASK DESC_GENMASK(7, 6)32enum {33 FBNIC_TWD_L3_TYPE_OTHER = 0,34 FBNIC_TWD_L3_TYPE_IPV4 = 1,35 FBNIC_TWD_L3_TYPE_IPV6 = 2,36 FBNIC_TWD_L3_TYPE_V6V6 = 3,37};38 39#define FBNIC_TWD_L3_OHLEN_MASK DESC_GENMASK(15, 8)40#define FBNIC_TWD_L3_IHLEN_MASK DESC_GENMASK(23, 16)41 42enum {43 FBNIC_TWD_L4_TYPE_OTHER = 0,44 FBNIC_TWD_L4_TYPE_TCP = 1,45 FBNIC_TWD_L4_TYPE_UDP = 2,46};47 48#define FBNIC_TWD_CSUM_OFFSET_MASK DESC_GENMASK(27, 24)49#define FBNIC_TWD_L4_HLEN_MASK DESC_GENMASK(31, 28)50 51/* Flags and Type */52#define FBNIC_TWD_L4_TYPE_MASK DESC_GENMASK(33, 32)53#define FBNIC_TWD_FLAG_REQ_TS DESC_BIT(34)54#define FBNIC_TWD_FLAG_REQ_LSO DESC_BIT(35)55#define FBNIC_TWD_FLAG_REQ_CSO DESC_BIT(36)56#define FBNIC_TWD_FLAG_REQ_COMPLETION DESC_BIT(37)57#define FBNIC_TWD_FLAG_DEST_MAC DESC_BIT(43)58#define FBNIC_TWD_FLAG_DEST_BMC DESC_BIT(44)59#define FBNIC_TWD_FLAG_DEST_FW DESC_BIT(45)60#define FBNIC_TWD_TYPE_MASK DESC_GENMASK(47, 46)61enum {62 FBNIC_TWD_TYPE_META = 0,63 FBNIC_TWD_TYPE_OPT_META = 1,64 FBNIC_TWD_TYPE_AL = 2,65 FBNIC_TWD_TYPE_LAST_AL = 3,66};67 68/* MSS and Completion Req */69#define FBNIC_TWD_MSS_MASK DESC_GENMASK(61, 48)70 71#define FBNIC_TWD_TS_MASK DESC_GENMASK(39, 0)72#define FBNIC_TWD_ADDR_MASK DESC_GENMASK(45, 0)73#define FBNIC_TWD_LEN_MASK DESC_GENMASK(63, 48)74 75/* Tx Completion Descriptor Format */76#define FBNIC_TCD_TYPE0_HEAD0_MASK DESC_GENMASK(15, 0)77#define FBNIC_TCD_TYPE0_HEAD1_MASK DESC_GENMASK(31, 16)78 79#define FBNIC_TCD_TYPE1_TS_MASK DESC_GENMASK(39, 0)80 81#define FBNIC_TCD_STATUS_MASK DESC_GENMASK(59, 48)82#define FBNIC_TCD_STATUS_TS_INVALID DESC_BIT(48)83#define FBNIC_TCD_STATUS_ILLEGAL_TS_REQ DESC_BIT(49)84#define FBNIC_TCD_TWQ1 DESC_BIT(60)85#define FBNIC_TCD_TYPE_MASK DESC_GENMASK(62, 61)86enum {87 FBNIC_TCD_TYPE_0 = 0,88 FBNIC_TCD_TYPE_1 = 1,89};90 91#define FBNIC_TCD_DONE DESC_BIT(63)92 93/* Rx Buffer Descriptor Format94 *95 * The layout of this can vary depending on the page size of the system.96 *97 * If the page size is 4K then the layout will simply consist of ID for98 * the 16 most significant bits, and the lower 46 are essentially the page99 * address with the lowest 12 bits being reserved 0 due to the fact that100 * a page will be aligned.101 *102 * If the page size is larger than 4K then the lower n bits of the ID and103 * page address will be reserved for the fragment ID. This fragment will104 * be 4K in size and will be used to index both the DMA address and the ID105 * by the same amount.106 */107#define FBNIC_BD_DESC_ADDR_MASK DESC_GENMASK(45, 12)108#define FBNIC_BD_DESC_ID_MASK DESC_GENMASK(63, 48)109#define FBNIC_BD_FRAG_SIZE \110 (FBNIC_BD_DESC_ADDR_MASK & ~(FBNIC_BD_DESC_ADDR_MASK - 1))111#define FBNIC_BD_FRAG_COUNT \112 (PAGE_SIZE / FBNIC_BD_FRAG_SIZE)113#define FBNIC_BD_FRAG_ADDR_MASK \114 (FBNIC_BD_DESC_ADDR_MASK & \115 ~(FBNIC_BD_DESC_ADDR_MASK * FBNIC_BD_FRAG_COUNT))116#define FBNIC_BD_FRAG_ID_MASK \117 (FBNIC_BD_DESC_ID_MASK & \118 ~(FBNIC_BD_DESC_ID_MASK * FBNIC_BD_FRAG_COUNT))119#define FBNIC_BD_PAGE_ADDR_MASK \120 (FBNIC_BD_DESC_ADDR_MASK & ~FBNIC_BD_FRAG_ADDR_MASK)121#define FBNIC_BD_PAGE_ID_MASK \122 (FBNIC_BD_DESC_ID_MASK & ~FBNIC_BD_FRAG_ID_MASK)123 124/* Rx Completion Queue Descriptors */125#define FBNIC_RCD_TYPE_MASK DESC_GENMASK(62, 61)126enum {127 FBNIC_RCD_TYPE_HDR_AL = 0,128 FBNIC_RCD_TYPE_PAY_AL = 1,129 FBNIC_RCD_TYPE_OPT_META = 2,130 FBNIC_RCD_TYPE_META = 3,131};132 133#define FBNIC_RCD_DONE DESC_BIT(63)134 135/* Address/Length Completion Descriptors */136#define FBNIC_RCD_AL_BUFF_ID_MASK DESC_GENMASK(15, 0)137#define FBNIC_RCD_AL_BUFF_FRAG_MASK (FBNIC_BD_FRAG_COUNT - 1)138#define FBNIC_RCD_AL_BUFF_PAGE_MASK \139 (FBNIC_RCD_AL_BUFF_ID_MASK & ~FBNIC_RCD_AL_BUFF_FRAG_MASK)140#define FBNIC_RCD_AL_BUFF_LEN_MASK DESC_GENMASK(28, 16)141#define FBNIC_RCD_AL_BUFF_OFF_MASK DESC_GENMASK(43, 32)142#define FBNIC_RCD_AL_PAGE_FIN DESC_BIT(60)143 144/* Header AL specific values */145#define FBNIC_RCD_HDR_AL_OVERFLOW DESC_BIT(53)146#define FBNIC_RCD_HDR_AL_DMA_HINT_MASK DESC_GENMASK(59, 54)147enum {148 FBNIC_RCD_HDR_AL_DMA_HINT_NONE = 0,149 FBNIC_RCD_HDR_AL_DMA_HINT_L2 = 1,150 FBNIC_RCD_HDR_AL_DMA_HINT_L3 = 2,151 FBNIC_RCD_HDR_AL_DMA_HINT_L4 = 4,152};153 154/* Optional Metadata Completion Descriptors */155#define FBNIC_RCD_OPT_META_TS_MASK DESC_GENMASK(39, 0)156#define FBNIC_RCD_OPT_META_ACTION_MASK DESC_GENMASK(45, 40)157#define FBNIC_RCD_OPT_META_ACTION DESC_BIT(57)158#define FBNIC_RCD_OPT_META_TS DESC_BIT(58)159#define FBNIC_RCD_OPT_META_TYPE_MASK DESC_GENMASK(60, 59)160 161/* Metadata Completion Descriptors */162#define FBNIC_RCD_META_RSS_HASH_MASK DESC_GENMASK(31, 0)163#define FBNIC_RCD_META_L2_CSUM_MASK DESC_GENMASK(47, 32)164#define FBNIC_RCD_META_L3_TYPE_MASK DESC_GENMASK(49, 48)165enum {166 FBNIC_RCD_META_L3_TYPE_OTHER = 0,167 FBNIC_RCD_META_L3_TYPE_IPV4 = 1,168 FBNIC_RCD_META_L3_TYPE_IPV6 = 2,169 FBNIC_RCD_META_L3_TYPE_V6V6 = 3,170};171 172#define FBNIC_RCD_META_L4_TYPE_MASK DESC_GENMASK(51, 50)173enum {174 FBNIC_RCD_META_L4_TYPE_OTHER = 0,175 FBNIC_RCD_META_L4_TYPE_TCP = 1,176 FBNIC_RCD_META_L4_TYPE_UDP = 2,177};178 179#define FBNIC_RCD_META_L4_CSUM_UNNECESSARY DESC_BIT(52)180#define FBNIC_RCD_META_ERR_MAC_EOP DESC_BIT(53)181#define FBNIC_RCD_META_ERR_TRUNCATED_FRAME DESC_BIT(54)182#define FBNIC_RCD_META_ERR_PARSER DESC_BIT(55)183#define FBNIC_RCD_META_UNCORRECTABLE_ERR_MASK \184 (FBNIC_RCD_META_ERR_MAC_EOP | FBNIC_RCD_META_ERR_TRUNCATED_FRAME)185#define FBNIC_RCD_META_ECN DESC_BIT(60)186 187/* Register Definitions188 *189 * The registers are laid as indexes into an le32 array. As such the actual190 * address is 4 times the index value. Below each register is defined as 3191 * fields, name, index, and Address.192 *193 * Name Index Address194 *************************************************************************/195/* Interrupt Registers */196#define FBNIC_CSR_START_INTR 0x00000 /* CSR section delimiter */197#define FBNIC_INTR_STATUS(n) (0x00000 + (n)) /* 0x00000 + 4*n */198#define FBNIC_INTR_STATUS_CNT 8199#define FBNIC_INTR_MASK(n) (0x00008 + (n)) /* 0x00020 + 4*n */200#define FBNIC_INTR_MASK_CNT 8201#define FBNIC_INTR_SET(n) (0x00010 + (n)) /* 0x00040 + 4*n */202#define FBNIC_INTR_SET_CNT 8203#define FBNIC_INTR_CLEAR(n) (0x00018 + (n)) /* 0x00060 + 4*n */204#define FBNIC_INTR_CLEAR_CNT 8205#define FBNIC_INTR_SW_STATUS(n) (0x00020 + (n)) /* 0x00080 + 4*n */206#define FBNIC_INTR_SW_STATUS_CNT 8207#define FBNIC_INTR_SW_AC_MODE(n) (0x00028 + (n)) /* 0x000a0 + 4*n */208#define FBNIC_INTR_SW_AC_MODE_CNT 8209#define FBNIC_INTR_MASK_SET(n) (0x00030 + (n)) /* 0x000c0 + 4*n */210#define FBNIC_INTR_MASK_SET_CNT 8211#define FBNIC_INTR_MASK_CLEAR(n) (0x00038 + (n)) /* 0x000e0 + 4*n */212#define FBNIC_INTR_MASK_CLEAR_CNT 8213#define FBNIC_MAX_MSIX_VECS 256U214#define FBNIC_INTR_MSIX_CTRL(n) (0x00040 + (n)) /* 0x00100 + 4*n */215#define FBNIC_INTR_MSIX_CTRL_VECTOR_MASK CSR_GENMASK(7, 0)216#define FBNIC_INTR_MSIX_CTRL_ENABLE CSR_BIT(31)217enum {218 FBNIC_INTR_MSIX_CTRL_PCS_IDX = 34,219};220 221#define FBNIC_CSR_END_INTR 0x0005f /* CSR section delimiter */222 223/* Interrupt MSIX Registers */224#define FBNIC_CSR_START_INTR_CQ 0x00400 /* CSR section delimiter */225#define FBNIC_INTR_CQ_REARM(n) \226 (0x00400 + 4 * (n)) /* 0x01000 + 16*n */227#define FBNIC_INTR_CQ_REARM_CNT 256228#define FBNIC_INTR_CQ_REARM_RCQ_TIMEOUT CSR_GENMASK(13, 0)229#define FBNIC_INTR_CQ_REARM_RCQ_TIMEOUT_UPD_EN CSR_BIT(14)230#define FBNIC_INTR_CQ_REARM_TCQ_TIMEOUT CSR_GENMASK(28, 15)231#define FBNIC_INTR_CQ_REARM_TCQ_TIMEOUT_UPD_EN CSR_BIT(29)232#define FBNIC_INTR_CQ_REARM_INTR_RELOAD CSR_BIT(30)233#define FBNIC_INTR_CQ_REARM_INTR_UNMASK CSR_BIT(31)234 235#define FBNIC_INTR_RCQ_TIMEOUT(n) \236 (0x00401 + 4 * (n)) /* 0x01004 + 16*n */237#define FBNIC_INTR_RCQ_TIMEOUT_CNT 256238#define FBNIC_INTR_TCQ_TIMEOUT(n) \239 (0x00402 + 4 * (n)) /* 0x01008 + 16*n */240#define FBNIC_INTR_TCQ_TIMEOUT_CNT 256241#define FBNIC_CSR_END_INTR_CQ 0x007fe /* CSR section delimiter */242 243/* Global QM Tx registers */244#define FBNIC_CSR_START_QM_TX 0x00800 /* CSR section delimiter */245#define FBNIC_QM_TWQ_IDLE(n) (0x00800 + (n)) /* 0x02000 + 4*n */246#define FBNIC_QM_TWQ_IDLE_CNT 8247#define FBNIC_QM_TWQ_DEFAULT_META_L 0x00818 /* 0x02060 */248#define FBNIC_QM_TWQ_DEFAULT_META_H 0x00819 /* 0x02064 */249 250#define FBNIC_QM_TQS_CTL0 0x0081b /* 0x0206c */251#define FBNIC_QM_TQS_CTL0_LSO_TS_MASK CSR_BIT(0)252enum {253 FBNIC_QM_TQS_CTL0_LSO_TS_FIRST = 0,254 FBNIC_QM_TQS_CTL0_LSO_TS_LAST = 1,255};256 257#define FBNIC_QM_TQS_CTL0_PREFETCH_THRESH CSR_GENMASK(7, 1)258enum {259 FBNIC_QM_TQS_CTL0_PREFETCH_THRESH_MIN = 16,260};261 262#define FBNIC_QM_TQS_CTL1 0x0081c /* 0x02070 */263#define FBNIC_QM_TQS_CTL1_MC_MAX_CREDITS CSR_GENMASK(7, 0)264#define FBNIC_QM_TQS_CTL1_BULK_MAX_CREDITS CSR_GENMASK(15, 8)265#define FBNIC_QM_TQS_MTU_CTL0 0x0081d /* 0x02074 */266#define FBNIC_QM_TQS_MTU_CTL1 0x0081e /* 0x02078 */267#define FBNIC_QM_TQS_MTU_CTL1_BULK CSR_GENMASK(13, 0)268#define FBNIC_QM_TCQ_IDLE(n) (0x00821 + (n)) /* 0x02084 + 4*n */269#define FBNIC_QM_TCQ_IDLE_CNT 4270#define FBNIC_QM_TCQ_CTL0 0x0082d /* 0x020b4 */271#define FBNIC_QM_TCQ_CTL0_COAL_WAIT CSR_GENMASK(15, 0)272#define FBNIC_QM_TCQ_CTL0_TICK_CYCLES CSR_GENMASK(26, 16)273#define FBNIC_QM_TQS_IDLE(n) (0x00830 + (n)) /* 0x020c0 + 4*n */274#define FBNIC_QM_TQS_IDLE_CNT 8275#define FBNIC_QM_TQS_EDT_TS_RANGE 0x00849 /* 0x2124 */276#define FBNIC_QM_TDE_IDLE(n) (0x00853 + (n)) /* 0x0214c + 4*n */277#define FBNIC_QM_TDE_IDLE_CNT 8278#define FBNIC_QM_TNI_TDF_CTL 0x0086c /* 0x021b0 */279#define FBNIC_QM_TNI_TDF_CTL_MRRS CSR_GENMASK(1, 0)280#define FBNIC_QM_TNI_TDF_CTL_CLS CSR_GENMASK(3, 2)281#define FBNIC_QM_TNI_TDF_CTL_MAX_OT CSR_GENMASK(11, 4)282#define FBNIC_QM_TNI_TDF_CTL_MAX_OB CSR_GENMASK(23, 12)283#define FBNIC_QM_TNI_TDE_CTL 0x0086d /* 0x021b4 */284#define FBNIC_QM_TNI_TDE_CTL_MRRS CSR_GENMASK(1, 0)285#define FBNIC_QM_TNI_TDE_CTL_CLS CSR_GENMASK(3, 2)286#define FBNIC_QM_TNI_TDE_CTL_MAX_OT CSR_GENMASK(11, 4)287#define FBNIC_QM_TNI_TDE_CTL_MAX_OB CSR_GENMASK(24, 12)288#define FBNIC_QM_TNI_TDE_CTL_MRRS_1K CSR_BIT(25)289#define FBNIC_QM_TNI_TCM_CTL 0x0086e /* 0x021b8 */290#define FBNIC_QM_TNI_TCM_CTL_MPS CSR_GENMASK(1, 0)291#define FBNIC_QM_TNI_TCM_CTL_CLS CSR_GENMASK(3, 2)292#define FBNIC_QM_TNI_TCM_CTL_MAX_OT CSR_GENMASK(11, 4)293#define FBNIC_QM_TNI_TCM_CTL_MAX_OB CSR_GENMASK(23, 12)294#define FBNIC_CSR_END_QM_TX 0x00873 /* CSR section delimiter */295 296/* Global QM Rx registers */297#define FBNIC_CSR_START_QM_RX 0x00c00 /* CSR section delimiter */298#define FBNIC_QM_RCQ_IDLE(n) (0x00c00 + (n)) /* 0x03000 + 4*n */299#define FBNIC_QM_RCQ_IDLE_CNT 4300#define FBNIC_QM_RCQ_CTL0 0x00c0c /* 0x03030 */301#define FBNIC_QM_RCQ_CTL0_COAL_WAIT CSR_GENMASK(15, 0)302#define FBNIC_QM_RCQ_CTL0_TICK_CYCLES CSR_GENMASK(26, 16)303#define FBNIC_QM_HPQ_IDLE(n) (0x00c0f + (n)) /* 0x0303c + 4*n */304#define FBNIC_QM_HPQ_IDLE_CNT 4305#define FBNIC_QM_PPQ_IDLE(n) (0x00c13 + (n)) /* 0x0304c + 4*n */306#define FBNIC_QM_PPQ_IDLE_CNT 4307#define FBNIC_QM_RNI_RBP_CTL 0x00c2d /* 0x030b4 */308#define FBNIC_QM_RNI_RBP_CTL_MRRS CSR_GENMASK(1, 0)309#define FBNIC_QM_RNI_RBP_CTL_CLS CSR_GENMASK(3, 2)310#define FBNIC_QM_RNI_RBP_CTL_MAX_OT CSR_GENMASK(11, 4)311#define FBNIC_QM_RNI_RBP_CTL_MAX_OB CSR_GENMASK(23, 12)312#define FBNIC_QM_RNI_RDE_CTL 0x00c2e /* 0x030b8 */313#define FBNIC_QM_RNI_RDE_CTL_MPS CSR_GENMASK(1, 0)314#define FBNIC_QM_RNI_RDE_CTL_CLS CSR_GENMASK(3, 2)315#define FBNIC_QM_RNI_RDE_CTL_MAX_OT CSR_GENMASK(11, 4)316#define FBNIC_QM_RNI_RDE_CTL_MAX_OB CSR_GENMASK(23, 12)317#define FBNIC_QM_RNI_RCM_CTL 0x00c2f /* 0x030bc */318#define FBNIC_QM_RNI_RCM_CTL_MPS CSR_GENMASK(1, 0)319#define FBNIC_QM_RNI_RCM_CTL_CLS CSR_GENMASK(3, 2)320#define FBNIC_QM_RNI_RCM_CTL_MAX_OT CSR_GENMASK(11, 4)321#define FBNIC_QM_RNI_RCM_CTL_MAX_OB CSR_GENMASK(23, 12)322#define FBNIC_CSR_END_QM_RX 0x00c34 /* CSR section delimiter */323 324/* TCE registers */325#define FBNIC_CSR_START_TCE 0x04000 /* CSR section delimiter */326#define FBNIC_TCE_REG_BASE 0x04000 /* 0x10000 */327 328#define FBNIC_TCE_LSO_CTRL 0x04000 /* 0x10000 */329#define FBNIC_TCE_LSO_CTRL_TCPF_CLR_1ST CSR_GENMASK(8, 0)330#define FBNIC_TCE_LSO_CTRL_TCPF_CLR_MID CSR_GENMASK(17, 9)331#define FBNIC_TCE_LSO_CTRL_TCPF_CLR_END CSR_GENMASK(26, 18)332#define FBNIC_TCE_LSO_CTRL_IPID_MODE_INC CSR_BIT(27)333 334#define FBNIC_TCE_CSO_CTRL 0x04001 /* 0x10004 */335#define FBNIC_TCE_CSO_CTRL_TCP_ZERO_CSUM CSR_BIT(0)336 337#define FBNIC_TCE_TXB_CTRL 0x04002 /* 0x10008 */338#define FBNIC_TCE_TXB_CTRL_LOAD CSR_BIT(0)339#define FBNIC_TCE_TXB_CTRL_TCAM_ENABLE CSR_BIT(1)340#define FBNIC_TCE_TXB_CTRL_DISABLE CSR_BIT(2)341 342#define FBNIC_TCE_TXB_ENQ_WRR_CTRL 0x04003 /* 0x1000c */343#define FBNIC_TCE_TXB_ENQ_WRR_CTRL_WEIGHT0 CSR_GENMASK(7, 0)344#define FBNIC_TCE_TXB_ENQ_WRR_CTRL_WEIGHT1 CSR_GENMASK(15, 8)345#define FBNIC_TCE_TXB_ENQ_WRR_CTRL_WEIGHT2 CSR_GENMASK(23, 16)346 347#define FBNIC_TCE_TXB_TEI_Q0_CTRL 0x04004 /* 0x10010 */348#define FBNIC_TCE_TXB_TEI_Q1_CTRL 0x04005 /* 0x10014 */349#define FBNIC_TCE_TXB_MC_Q_CTRL 0x04006 /* 0x10018 */350#define FBNIC_TCE_TXB_RX_TEI_Q_CTRL 0x04007 /* 0x1001c */351#define FBNIC_TCE_TXB_RX_BMC_Q_CTRL 0x04008 /* 0x10020 */352#define FBNIC_TCE_TXB_Q_CTRL_START CSR_GENMASK(10, 0)353#define FBNIC_TCE_TXB_Q_CTRL_SIZE CSR_GENMASK(22, 11)354 355#define FBNIC_TCE_TXB_TEI_DWRR_CTRL 0x04009 /* 0x10024 */356#define FBNIC_TCE_TXB_TEI_DWRR_CTRL_QUANTUM0 CSR_GENMASK(7, 0)357#define FBNIC_TCE_TXB_TEI_DWRR_CTRL_QUANTUM1 CSR_GENMASK(15, 8)358#define FBNIC_TCE_TXB_NTWRK_DWRR_CTRL 0x0400a /* 0x10028 */359#define FBNIC_TCE_TXB_NTWRK_DWRR_CTRL_QUANTUM0 CSR_GENMASK(7, 0)360#define FBNIC_TCE_TXB_NTWRK_DWRR_CTRL_QUANTUM1 CSR_GENMASK(15, 8)361#define FBNIC_TCE_TXB_NTWRK_DWRR_CTRL_QUANTUM2 CSR_GENMASK(23, 16)362 363#define FBNIC_TCE_TXB_CLDR_CFG 0x0400b /* 0x1002c */364#define FBNIC_TCE_TXB_CLDR_CFG_NUM_SLOT CSR_GENMASK(5, 0)365#define FBNIC_TCE_TXB_CLDR_SLOT_CFG(n) (0x0400c + (n)) /* 0x10030 + 4*n */366#define FBNIC_TCE_TXB_CLDR_SLOT_CFG_CNT 16367#define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_0_0 CSR_GENMASK(1, 0)368#define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_0_1 CSR_GENMASK(3, 2)369#define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_0_2 CSR_GENMASK(5, 4)370#define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_0_3 CSR_GENMASK(7, 6)371#define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_1_0 CSR_GENMASK(9, 8)372#define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_1_1 CSR_GENMASK(11, 10)373#define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_1_2 CSR_GENMASK(13, 12)374#define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_1_3 CSR_GENMASK(15, 14)375#define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_2_0 CSR_GENMASK(17, 16)376#define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_2_1 CSR_GENMASK(19, 18)377#define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_2_2 CSR_GENMASK(21, 20)378#define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_2_3 CSR_GENMASK(23, 22)379#define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_3_0 CSR_GENMASK(25, 24)380#define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_3_1 CSR_GENMASK(27, 26)381#define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_3_2 CSR_GENMASK(29, 28)382#define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_3_3 CSR_GENMASK(31, 30)383 384#define FBNIC_TCE_BMC_MAX_PKTSZ 0x0403a /* 0x100e8 */385#define FBNIC_TCE_BMC_MAX_PKTSZ_TX CSR_GENMASK(13, 0)386#define FBNIC_TCE_BMC_MAX_PKTSZ_RX CSR_GENMASK(27, 14)387#define FBNIC_TCE_MC_MAX_PKTSZ 0x0403b /* 0x100ec */388#define FBNIC_TCE_MC_MAX_PKTSZ_TMI CSR_GENMASK(13, 0)389 390#define FBNIC_TCE_SOP_PROT_CTRL 0x0403c /* 0x100f0 */391#define FBNIC_TCE_SOP_PROT_CTRL_TBI CSR_GENMASK(7, 0)392#define FBNIC_TCE_SOP_PROT_CTRL_TTI_FRM CSR_GENMASK(14, 8)393#define FBNIC_TCE_SOP_PROT_CTRL_TTI_CM CSR_GENMASK(18, 15)394 395#define FBNIC_TCE_DROP_CTRL 0x0403d /* 0x100f4 */396#define FBNIC_TCE_DROP_CTRL_TTI_CM_DROP_EN CSR_BIT(0)397#define FBNIC_TCE_DROP_CTRL_TTI_FRM_DROP_EN CSR_BIT(1)398#define FBNIC_TCE_DROP_CTRL_TTI_TBI_DROP_EN CSR_BIT(2)399 400#define FBNIC_TCE_TXB_TX_BMC_Q_CTRL 0x0404B /* 0x1012c */401#define FBNIC_TCE_TXB_BMC_DWRR_CTRL 0x0404C /* 0x10130 */402#define FBNIC_TCE_TXB_BMC_DWRR_CTRL_QUANTUM0 CSR_GENMASK(7, 0)403#define FBNIC_TCE_TXB_BMC_DWRR_CTRL_QUANTUM1 CSR_GENMASK(15, 8)404#define FBNIC_TCE_TXB_TEI_DWRR_CTRL_EXT 0x0404D /* 0x10134 */405#define FBNIC_TCE_TXB_NTWRK_DWRR_CTRL_EXT \406 0x0404E /* 0x10138 */407#define FBNIC_TCE_TXB_BMC_DWRR_CTRL_EXT 0x0404F /* 0x1013c */408#define FBNIC_CSR_END_TCE 0x04050 /* CSR section delimiter */409 410/* TMI registers */411#define FBNIC_CSR_START_TMI 0x04400 /* CSR section delimiter */412#define FBNIC_TMI_SOP_PROT_CTRL 0x04400 /* 0x11000 */413#define FBNIC_TMI_DROP_CTRL 0x04401 /* 0x11004 */414#define FBNIC_TMI_DROP_CTRL_EN CSR_BIT(0)415#define FBNIC_CSR_END_TMI 0x0443f /* CSR section delimiter */416/* Rx Buffer Registers */417#define FBNIC_CSR_START_RXB 0x08000 /* CSR section delimiter */418enum {419 FBNIC_RXB_FIFO_MC = 0,420 /* Unused */421 /* Unused */422 FBNIC_RXB_FIFO_NET_TO_BMC = 3,423 FBNIC_RXB_FIFO_HOST = 4,424 /* Unused */425 FBNIC_RXB_FIFO_BMC_TO_HOST = 6,426 /* Unused */427 FBNIC_RXB_FIFO_INDICES = 8428};429 430#define FBNIC_RXB_CT_SIZE(n) (0x08000 + (n)) /* 0x20000 + 4*n */431#define FBNIC_RXB_CT_SIZE_CNT 8432#define FBNIC_RXB_CT_SIZE_HEADER CSR_GENMASK(5, 0)433#define FBNIC_RXB_CT_SIZE_PAYLOAD CSR_GENMASK(11, 6)434#define FBNIC_RXB_CT_SIZE_ENABLE CSR_BIT(12)435#define FBNIC_RXB_PAUSE_DROP_CTRL 0x08008 /* 0x20020 */436#define FBNIC_RXB_PAUSE_DROP_CTRL_DROP_ENABLE CSR_GENMASK(7, 0)437#define FBNIC_RXB_PAUSE_DROP_CTRL_PAUSE_ENABLE CSR_GENMASK(15, 8)438#define FBNIC_RXB_PAUSE_DROP_CTRL_ECN_ENABLE CSR_GENMASK(23, 16)439#define FBNIC_RXB_PAUSE_DROP_CTRL_PS_ENABLE CSR_GENMASK(27, 24)440#define FBNIC_RXB_PAUSE_THLD(n) (0x08009 + (n)) /* 0x20024 + 4*n */441#define FBNIC_RXB_PAUSE_THLD_CNT 8442#define FBNIC_RXB_PAUSE_THLD_ON CSR_GENMASK(12, 0)443#define FBNIC_RXB_PAUSE_THLD_OFF CSR_GENMASK(25, 13)444#define FBNIC_RXB_DROP_THLD(n) (0x08011 + (n)) /* 0x20044 + 4*n */445#define FBNIC_RXB_DROP_THLD_CNT 8446#define FBNIC_RXB_DROP_THLD_ON CSR_GENMASK(12, 0)447#define FBNIC_RXB_DROP_THLD_OFF CSR_GENMASK(25, 13)448#define FBNIC_RXB_ECN_THLD(n) (0x0801e + (n)) /* 0x20078 + 4*n */449#define FBNIC_RXB_ECN_THLD_CNT 8450#define FBNIC_RXB_ECN_THLD_ON CSR_GENMASK(12, 0)451#define FBNIC_RXB_ECN_THLD_OFF CSR_GENMASK(25, 13)452#define FBNIC_RXB_PBUF_CFG(n) (0x08027 + (n)) /* 0x2009c + 4*n */453#define FBNIC_RXB_PBUF_CFG_CNT 8454#define FBNIC_RXB_PBUF_BASE_ADDR CSR_GENMASK(12, 0)455#define FBNIC_RXB_PBUF_SIZE CSR_GENMASK(21, 13)456#define FBNIC_RXB_DWRR_RDE_WEIGHT0 0x0802f /* 0x200bc */457#define FBNIC_RXB_DWRR_RDE_WEIGHT0_QUANTUM0 CSR_GENMASK(7, 0)458#define FBNIC_RXB_DWRR_RDE_WEIGHT0_QUANTUM1 CSR_GENMASK(15, 8)459#define FBNIC_RXB_DWRR_RDE_WEIGHT0_QUANTUM2 CSR_GENMASK(23, 16)460#define FBNIC_RXB_DWRR_RDE_WEIGHT0_QUANTUM3 CSR_GENMASK(31, 24)461#define FBNIC_RXB_DWRR_RDE_WEIGHT1 0x08030 /* 0x200c0 */462#define FBNIC_RXB_DWRR_RDE_WEIGHT1_QUANTUM4 CSR_GENMASK(7, 0)463#define FBNIC_RXB_DWRR_BMC_WEIGHT 0x08031 /* 0x200c4 */464#define FBNIC_RXB_CLDR_PRIO_CFG(n) (0x8034 + (n)) /* 0x200d0 + 4*n */465#define FBNIC_RXB_CLDR_PRIO_CFG_CNT 16466#define FBNIC_RXB_ENDIAN_FCS 0x08044 /* 0x20110 */467enum {468 /* Unused */469 /* Unused */470 FBNIC_RXB_DEQUEUE_BMC = 2,471 FBNIC_RXB_DEQUEUE_HOST = 3,472 FBNIC_RXB_DEQUEUE_INDICES = 4473};474 475#define FBNIC_RXB_PBUF_CREDIT(n) (0x08047 + (n)) /* 0x2011C + 4*n */476#define FBNIC_RXB_PBUF_CREDIT_CNT 8477#define FBNIC_RXB_PBUF_CREDIT_MASK CSR_GENMASK(13, 0)478#define FBNIC_RXB_INTF_CREDIT 0x0804f /* 0x2013C */479#define FBNIC_RXB_INTF_CREDIT_MASK0 CSR_GENMASK(3, 0)480#define FBNIC_RXB_INTF_CREDIT_MASK1 CSR_GENMASK(7, 4)481#define FBNIC_RXB_INTF_CREDIT_MASK2 CSR_GENMASK(11, 8)482#define FBNIC_RXB_INTF_CREDIT_MASK3 CSR_GENMASK(15, 12)483 484#define FBNIC_RXB_PAUSE_EVENT_CNT(n) (0x08053 + (n)) /* 0x2014c + 4*n */485#define FBNIC_RXB_DROP_FRMS_STS(n) (0x08057 + (n)) /* 0x2015c + 4*n */486#define FBNIC_RXB_DROP_BYTES_STS_L(n) \487 (0x08080 + 2 * (n)) /* 0x20200 + 8*n */488#define FBNIC_RXB_DROP_BYTES_STS_H(n) \489 (0x08081 + 2 * (n)) /* 0x20204 + 8*n */490#define FBNIC_RXB_TRUN_FRMS_STS(n) (0x08091 + (n)) /* 0x20244 + 4*n */491#define FBNIC_RXB_TRUN_BYTES_STS_L(n) \492 (0x080c0 + 2 * (n)) /* 0x20300 + 8*n */493#define FBNIC_RXB_TRUN_BYTES_STS_H(n) \494 (0x080c1 + 2 * (n)) /* 0x20304 + 8*n */495#define FBNIC_RXB_TRANS_PAUSE_STS(n) (0x080d1 + (n)) /* 0x20344 + 4*n */496#define FBNIC_RXB_TRANS_DROP_STS(n) (0x080d9 + (n)) /* 0x20364 + 4*n */497#define FBNIC_RXB_TRANS_ECN_STS(n) (0x080e1 + (n)) /* 0x20384 + 4*n */498enum {499 FBNIC_RXB_ENQUEUE_NET = 0,500 FBNIC_RXB_ENQUEUE_BMC = 1,501 /* Unused */502 /* Unused */503 FBNIC_RXB_ENQUEUE_INDICES = 4504};505 506#define FBNIC_RXB_DRBO_FRM_CNT_SRC(n) (0x080f9 + (n)) /* 0x203e4 + 4*n */507#define FBNIC_RXB_DRBO_BYTE_CNT_SRC_L(n) \508 (0x080fd + (n)) /* 0x203f4 + 4*n */509#define FBNIC_RXB_DRBO_BYTE_CNT_SRC_H(n) \510 (0x08101 + (n)) /* 0x20404 + 4*n */511#define FBNIC_RXB_INTF_FRM_CNT_DST(n) (0x08105 + (n)) /* 0x20414 + 4*n */512#define FBNIC_RXB_INTF_BYTE_CNT_DST_L(n) \513 (0x08109 + (n)) /* 0x20424 + 4*n */514#define FBNIC_RXB_INTF_BYTE_CNT_DST_H(n) \515 (0x0810d + (n)) /* 0x20434 + 4*n */516#define FBNIC_RXB_PBUF_FRM_CNT_DST(n) (0x08111 + (n)) /* 0x20444 + 4*n */517#define FBNIC_RXB_PBUF_BYTE_CNT_DST_L(n) \518 (0x08115 + (n)) /* 0x20454 + 4*n */519#define FBNIC_RXB_PBUF_BYTE_CNT_DST_H(n) \520 (0x08119 + (n)) /* 0x20464 + 4*n */521 522#define FBNIC_RXB_PBUF_FIFO_LEVEL(n) (0x0811d + (n)) /* 0x20474 + 4*n */523 524#define FBNIC_RXB_INTEGRITY_ERR(n) (0x0812f + (n)) /* 0x204bc + 4*n */525#define FBNIC_RXB_MAC_ERR(n) (0x08133 + (n)) /* 0x204cc + 4*n */526#define FBNIC_RXB_PARSER_ERR(n) (0x08137 + (n)) /* 0x204dc + 4*n */527#define FBNIC_RXB_FRM_ERR(n) (0x0813b + (n)) /* 0x204ec + 4*n */528 529#define FBNIC_RXB_DWRR_RDE_WEIGHT0_EXT 0x08143 /* 0x2050c */530#define FBNIC_RXB_DWRR_RDE_WEIGHT1_EXT 0x08144 /* 0x20510 */531#define FBNIC_CSR_END_RXB 0x081b1 /* CSR section delimiter */532 533/* Rx Parser and Classifier Registers */534#define FBNIC_CSR_START_RPC 0x08400 /* CSR section delimiter */535#define FBNIC_RPC_RMI_CONFIG 0x08400 /* 0x21000 */536#define FBNIC_RPC_RMI_CONFIG_OH_BYTES CSR_GENMASK(4, 0)537#define FBNIC_RPC_RMI_CONFIG_FCS_PRESENT CSR_BIT(8)538#define FBNIC_RPC_RMI_CONFIG_ENABLE CSR_BIT(12)539#define FBNIC_RPC_RMI_CONFIG_MTU CSR_GENMASK(31, 16)540 541#define FBNIC_RPC_ACT_TBL0_DEFAULT 0x0840a /* 0x21028 */542#define FBNIC_RPC_ACT_TBL0_DROP CSR_BIT(0)543#define FBNIC_RPC_ACT_TBL0_DEST_MASK CSR_GENMASK(3, 1)544enum {545 FBNIC_RPC_ACT_TBL0_DEST_HOST = 1,546 FBNIC_RPC_ACT_TBL0_DEST_BMC = 2,547 FBNIC_RPC_ACT_TBL0_DEST_EI = 4,548};549 550#define FBNIC_RPC_ACT_TBL0_DMA_HINT CSR_GENMASK(24, 16)551#define FBNIC_RPC_ACT_TBL0_RSS_CTXT_ID CSR_BIT(30)552 553#define FBNIC_RPC_ACT_TBL1_DEFAULT 0x0840b /* 0x2102c */554#define FBNIC_RPC_ACT_TBL1_RSS_ENA_MASK CSR_GENMASK(15, 0)555enum {556 FBNIC_RPC_ACT_TBL1_RSS_ENA_IP_SRC = 1,557 FBNIC_RPC_ACT_TBL1_RSS_ENA_IP_DST = 2,558 FBNIC_RPC_ACT_TBL1_RSS_ENA_L4_SRC = 4,559 FBNIC_RPC_ACT_TBL1_RSS_ENA_L4_DST = 8,560 FBNIC_RPC_ACT_TBL1_RSS_ENA_L2_DA = 16,561 FBNIC_RPC_ACT_TBL1_RSS_ENA_L4_RSS_BYTE = 32,562 FBNIC_RPC_ACT_TBL1_RSS_ENA_IV6_FL_LBL = 64,563 FBNIC_RPC_ACT_TBL1_RSS_ENA_OV6_FL_LBL = 128,564 FBNIC_RPC_ACT_TBL1_RSS_ENA_DSCP = 256,565 FBNIC_RPC_ACT_TBL1_RSS_ENA_L3_PROT = 512,566 FBNIC_RPC_ACT_TBL1_RSS_ENA_L4_PROT = 1024,567};568 569#define FBNIC_RPC_RSS_KEY(n) (0x0840c + (n)) /* 0x21030 + 4*n */570#define FBNIC_RPC_RSS_KEY_BIT_LEN 425571#define FBNIC_RPC_RSS_KEY_BYTE_LEN \572 DIV_ROUND_UP(FBNIC_RPC_RSS_KEY_BIT_LEN, 8)573#define FBNIC_RPC_RSS_KEY_DWORD_LEN \574 DIV_ROUND_UP(FBNIC_RPC_RSS_KEY_BIT_LEN, 32)575#define FBNIC_RPC_RSS_KEY_LAST_IDX \576 (FBNIC_RPC_RSS_KEY_DWORD_LEN - 1)577#define FBNIC_RPC_RSS_KEY_LAST_MASK \578 CSR_GENMASK(31, \579 FBNIC_RPC_RSS_KEY_DWORD_LEN * 32 - \580 FBNIC_RPC_RSS_KEY_BIT_LEN)581 582#define FBNIC_RPC_TCAM_MACDA_VALIDATE 0x0852d /* 0x214b4 */583#define FBNIC_CSR_END_RPC 0x0856b /* CSR section delimiter */584 585/* RPC RAM Registers */586 587#define FBNIC_CSR_START_RPC_RAM 0x08800 /* CSR section delimiter */588#define FBNIC_RPC_ACT_TBL0(n) (0x08800 + (n)) /* 0x22000 + 4*n */589#define FBNIC_RPC_ACT_TBL1(n) (0x08840 + (n)) /* 0x22100 + 4*n */590#define FBNIC_RPC_ACT_TBL_NUM_ENTRIES 64591 592/* TCAM Tables */593#define FBNIC_RPC_TCAM_VALIDATE CSR_BIT(31)594 595/* 64 Action TCAM Entries, 12 registers596 * 3 mixed, src port, dst port, 6 L4 words, and Validate597 */598#define FBNIC_RPC_TCAM_ACT(m, n) \599 (0x08880 + 0x40 * (n) + (m)) /* 0x22200 + 256*n + 4*m */600 601#define FBNIC_RPC_TCAM_ACT_VALUE CSR_GENMASK(15, 0)602#define FBNIC_RPC_TCAM_ACT_MASK CSR_GENMASK(31, 16)603 604#define FBNIC_RPC_TCAM_MACDA(m, n) \605 (0x08b80 + 0x20 * (n) + (m)) /* 0x022e00 + 128*n + 4*m */606#define FBNIC_RPC_TCAM_MACDA_VALUE CSR_GENMASK(15, 0)607#define FBNIC_RPC_TCAM_MACDA_MASK CSR_GENMASK(31, 16)608 609#define FBNIC_RPC_RSS_TBL(n, m) \610 (0x08d20 + 0x100 * (n) + (m)) /* 0x023480 + 1024*n + 4*m */611#define FBNIC_RPC_RSS_TBL_COUNT 2612#define FBNIC_RPC_RSS_TBL_SIZE 256613#define FBNIC_CSR_END_RPC_RAM 0x08f1f /* CSR section delimiter */614 615/* Fab Registers */616#define FBNIC_CSR_START_FAB 0x0C000 /* CSR section delimiter */617#define FBNIC_FAB_AXI4_AR_SPACER_2_CFG 0x0C005 /* 0x30014 */618#define FBNIC_FAB_AXI4_AR_SPACER_MASK CSR_BIT(16)619#define FBNIC_FAB_AXI4_AR_SPACER_THREADSHOLD CSR_GENMASK(15, 0)620#define FBNIC_CSR_END_FAB 0x0C020 /* CSR section delimiter */621 622/* Master Registers */623#define FBNIC_CSR_START_MASTER 0x0C400 /* CSR section delimiter */624#define FBNIC_MASTER_SPARE_0 0x0C41B /* 0x3106c */625#define FBNIC_CSR_END_MASTER 0x0C452 /* CSR section delimiter */626 627/* MAC MAC registers (ASIC only) */628#define FBNIC_CSR_START_MAC_MAC 0x11000 /* CSR section delimiter */629#define FBNIC_MAC_COMMAND_CONFIG 0x11002 /* 0x44008 */630#define FBNIC_MAC_COMMAND_CONFIG_RX_PAUSE_DIS CSR_BIT(29)631#define FBNIC_MAC_COMMAND_CONFIG_TX_PAUSE_DIS CSR_BIT(28)632#define FBNIC_MAC_COMMAND_CONFIG_FLT_HDL_DIS CSR_BIT(27)633#define FBNIC_MAC_COMMAND_CONFIG_TX_PAD_EN CSR_BIT(11)634#define FBNIC_MAC_COMMAND_CONFIG_LOOPBACK_EN CSR_BIT(10)635#define FBNIC_MAC_COMMAND_CONFIG_PROMISC_EN CSR_BIT(4)636#define FBNIC_MAC_COMMAND_CONFIG_RX_ENA CSR_BIT(1)637#define FBNIC_MAC_COMMAND_CONFIG_TX_ENA CSR_BIT(0)638#define FBNIC_MAC_CL01_PAUSE_QUANTA 0x11015 /* 0x44054 */639#define FBNIC_MAC_CL01_QUANTA_THRESH 0x11019 /* 0x44064 */640#define FBNIC_CSR_END_MAC_MAC 0x11028 /* CSR section delimiter */641 642/* Signals from MAC, AN, PCS, and LED CSR registers (ASIC only) */643#define FBNIC_CSR_START_SIG 0x11800 /* CSR section delimiter */644#define FBNIC_SIG_MAC_IN0 0x11800 /* 0x46000 */645#define FBNIC_SIG_MAC_IN0_RESET_FF_TX_CLK CSR_BIT(14)646#define FBNIC_SIG_MAC_IN0_RESET_FF_RX_CLK CSR_BIT(13)647#define FBNIC_SIG_MAC_IN0_RESET_TX_CLK CSR_BIT(12)648#define FBNIC_SIG_MAC_IN0_RESET_RX_CLK CSR_BIT(11)649#define FBNIC_SIG_MAC_IN0_TX_CRC CSR_BIT(8)650#define FBNIC_SIG_MAC_IN0_CFG_MODE128 CSR_BIT(10)651#define FBNIC_SIG_PCS_OUT0 0x11808 /* 0x46020 */652#define FBNIC_SIG_PCS_OUT0_LINK CSR_BIT(27)653#define FBNIC_SIG_PCS_OUT0_BLOCK_LOCK CSR_GENMASK(24, 5)654#define FBNIC_SIG_PCS_OUT0_AMPS_LOCK CSR_GENMASK(4, 1)655#define FBNIC_SIG_PCS_OUT1 0x11809 /* 0x46024 */656#define FBNIC_SIG_PCS_OUT1_FCFEC_LOCK CSR_GENMASK(11, 8)657#define FBNIC_SIG_PCS_INTR_STS 0x11814 /* 0x46050 */658#define FBNIC_SIG_PCS_INTR_LINK_DOWN CSR_BIT(1)659#define FBNIC_SIG_PCS_INTR_LINK_UP CSR_BIT(0)660#define FBNIC_SIG_PCS_INTR_MASK 0x11816 /* 0x46058 */661#define FBNIC_CSR_END_SIG 0x1184e /* CSR section delimiter */662 663#define FBNIC_CSR_START_MAC_STAT 0x11a00664#define FBNIC_MAC_STAT_RX_BYTE_COUNT_L 0x11a08 /* 0x46820 */665#define FBNIC_MAC_STAT_RX_BYTE_COUNT_H 0x11a09 /* 0x46824 */666#define FBNIC_MAC_STAT_RX_ALIGN_ERROR_L \667 0x11a0a /* 0x46828 */668#define FBNIC_MAC_STAT_RX_ALIGN_ERROR_H \669 0x11a0b /* 0x4682c */670#define FBNIC_MAC_STAT_RX_TOOLONG_L 0x11a0e /* 0x46838 */671#define FBNIC_MAC_STAT_RX_TOOLONG_H 0x11a0f /* 0x4683c */672#define FBNIC_MAC_STAT_RX_RECEIVED_OK_L \673 0x11a12 /* 0x46848 */674#define FBNIC_MAC_STAT_RX_RECEIVED_OK_H \675 0x11a13 /* 0x4684c */676#define FBNIC_MAC_STAT_RX_PACKET_BAD_FCS_L \677 0x11a14 /* 0x46850 */678#define FBNIC_MAC_STAT_RX_PACKET_BAD_FCS_H \679 0x11a15 /* 0x46854 */680#define FBNIC_MAC_STAT_RX_IFINERRORS_L 0x11a18 /* 0x46860 */681#define FBNIC_MAC_STAT_RX_IFINERRORS_H 0x11a19 /* 0x46864 */682#define FBNIC_MAC_STAT_RX_MULTICAST_L 0x11a1c /* 0x46870 */683#define FBNIC_MAC_STAT_RX_MULTICAST_H 0x11a1d /* 0x46874 */684#define FBNIC_MAC_STAT_RX_BROADCAST_L 0x11a1e /* 0x46878 */685#define FBNIC_MAC_STAT_RX_BROADCAST_H 0x11a1f /* 0x4687c */686#define FBNIC_MAC_STAT_TX_BYTE_COUNT_L 0x11a3e /* 0x468f8 */687#define FBNIC_MAC_STAT_TX_BYTE_COUNT_H 0x11a3f /* 0x468fc */688#define FBNIC_MAC_STAT_TX_TRANSMITTED_OK_L \689 0x11a42 /* 0x46908 */690#define FBNIC_MAC_STAT_TX_TRANSMITTED_OK_H \691 0x11a43 /* 0x4690c */692#define FBNIC_MAC_STAT_TX_IFOUTERRORS_L \693 0x11a46 /* 0x46918 */694#define FBNIC_MAC_STAT_TX_IFOUTERRORS_H \695 0x11a47 /* 0x4691c */696#define FBNIC_MAC_STAT_TX_MULTICAST_L 0x11a4a /* 0x46928 */697#define FBNIC_MAC_STAT_TX_MULTICAST_H 0x11a4b /* 0x4692c */698#define FBNIC_MAC_STAT_TX_BROADCAST_L 0x11a4c /* 0x46930 */699#define FBNIC_MAC_STAT_TX_BROADCAST_H 0x11a4d /* 0x46934 */700/* PUL User Registers */701#define FBNIC_CSR_START_PUL_USER 0x31000 /* CSR section delimiter */702#define FBNIC_PUL_OB_TLP_HDR_AW_CFG 0x3103d /* 0xc40f4 */703#define FBNIC_PUL_OB_TLP_HDR_AW_CFG_BME CSR_BIT(18)704#define FBNIC_PUL_OB_TLP_HDR_AR_CFG 0x3103e /* 0xc40f8 */705#define FBNIC_PUL_OB_TLP_HDR_AR_CFG_BME CSR_BIT(18)706#define FBNIC_CSR_END_PUL_USER 0x31080 /* CSR section delimiter */707 708/* Queue Registers709 *710 * The queue register offsets are specific for a given queue grouping. So to711 * find the actual register offset it is necessary to combine FBNIC_QUEUE(n)712 * with the register to get the actual register offset like so:713 * FBNIC_QUEUE_TWQ0_CTL(n) == FBNIC_QUEUE(n) + FBNIC_QUEUE_TWQ0_CTL714 */715#define FBNIC_CSR_START_QUEUE 0x40000 /* CSR section delimiter */716#define FBNIC_QUEUE_STRIDE 0x400 /* 0x1000 */717#define FBNIC_QUEUE(n)\718 (0x40000 + FBNIC_QUEUE_STRIDE * (n)) /* 0x100000 + 4096*n */719 720#define FBNIC_QUEUE_TWQ0_CTL 0x000 /* 0x000 */721#define FBNIC_QUEUE_TWQ1_CTL 0x001 /* 0x004 */722#define FBNIC_QUEUE_TWQ_CTL_RESET CSR_BIT(0)723#define FBNIC_QUEUE_TWQ_CTL_ENABLE CSR_BIT(1)724#define FBNIC_QUEUE_TWQ0_TAIL 0x002 /* 0x008 */725#define FBNIC_QUEUE_TWQ1_TAIL 0x003 /* 0x00c */726 727#define FBNIC_QUEUE_TWQ0_SIZE 0x00a /* 0x028 */728#define FBNIC_QUEUE_TWQ1_SIZE 0x00b /* 0x02c */729#define FBNIC_QUEUE_TWQ_SIZE_MASK CSR_GENMASK(3, 0)730 731#define FBNIC_QUEUE_TWQ0_BAL 0x020 /* 0x080 */732#define FBNIC_QUEUE_BAL_MASK CSR_GENMASK(31, 7)733#define FBNIC_QUEUE_TWQ0_BAH 0x021 /* 0x084 */734#define FBNIC_QUEUE_TWQ1_BAL 0x022 /* 0x088 */735#define FBNIC_QUEUE_TWQ1_BAH 0x023 /* 0x08c */736 737/* Tx Completion Queue Registers */738#define FBNIC_QUEUE_TCQ_CTL 0x080 /* 0x200 */739#define FBNIC_QUEUE_TCQ_CTL_RESET CSR_BIT(0)740#define FBNIC_QUEUE_TCQ_CTL_ENABLE CSR_BIT(1)741 742#define FBNIC_QUEUE_TCQ_HEAD 0x081 /* 0x204 */743 744#define FBNIC_QUEUE_TCQ_SIZE 0x084 /* 0x210 */745#define FBNIC_QUEUE_TCQ_SIZE_MASK CSR_GENMASK(3, 0)746 747#define FBNIC_QUEUE_TCQ_BAL 0x0a0 /* 0x280 */748#define FBNIC_QUEUE_TCQ_BAH 0x0a1 /* 0x284 */749 750/* Tx Interrupt Manager Registers */751#define FBNIC_QUEUE_TIM_CTL 0x0c0 /* 0x300 */752#define FBNIC_QUEUE_TIM_CTL_MSIX_MASK CSR_GENMASK(7, 0)753 754#define FBNIC_QUEUE_TIM_THRESHOLD 0x0c1 /* 0x304 */755#define FBNIC_QUEUE_TIM_THRESHOLD_TWD_MASK CSR_GENMASK(14, 0)756 757#define FBNIC_QUEUE_TIM_CLEAR 0x0c2 /* 0x308 */758#define FBNIC_QUEUE_TIM_CLEAR_MASK CSR_BIT(0)759#define FBNIC_QUEUE_TIM_SET 0x0c3 /* 0x30c */760#define FBNIC_QUEUE_TIM_SET_MASK CSR_BIT(0)761#define FBNIC_QUEUE_TIM_MASK 0x0c4 /* 0x310 */762#define FBNIC_QUEUE_TIM_MASK_MASK CSR_BIT(0)763 764#define FBNIC_QUEUE_TIM_TIMER 0x0c5 /* 0x314 */765 766#define FBNIC_QUEUE_TIM_COUNTS 0x0c6 /* 0x318 */767#define FBNIC_QUEUE_TIM_COUNTS_CNT1_MASK CSR_GENMASK(30, 16)768#define FBNIC_QUEUE_TIM_COUNTS_CNT0_MASK CSR_GENMASK(14, 0)769 770/* Rx Completion Queue Registers */771#define FBNIC_QUEUE_RCQ_CTL 0x200 /* 0x800 */772#define FBNIC_QUEUE_RCQ_CTL_RESET CSR_BIT(0)773#define FBNIC_QUEUE_RCQ_CTL_ENABLE CSR_BIT(1)774 775#define FBNIC_QUEUE_RCQ_HEAD 0x201 /* 0x804 */776 777#define FBNIC_QUEUE_RCQ_SIZE 0x204 /* 0x810 */778#define FBNIC_QUEUE_RCQ_SIZE_MASK CSR_GENMASK(3, 0)779 780#define FBNIC_QUEUE_RCQ_BAL 0x220 /* 0x880 */781#define FBNIC_QUEUE_RCQ_BAH 0x221 /* 0x884 */782 783/* Rx Buffer Descriptor Queue Registers */784#define FBNIC_QUEUE_BDQ_CTL 0x240 /* 0x900 */785#define FBNIC_QUEUE_BDQ_CTL_RESET CSR_BIT(0)786#define FBNIC_QUEUE_BDQ_CTL_ENABLE CSR_BIT(1)787#define FBNIC_QUEUE_BDQ_CTL_PPQ_ENABLE CSR_BIT(30)788 789#define FBNIC_QUEUE_BDQ_HPQ_TAIL 0x241 /* 0x904 */790#define FBNIC_QUEUE_BDQ_PPQ_TAIL 0x242 /* 0x908 */791 792#define FBNIC_QUEUE_BDQ_HPQ_SIZE 0x247 /* 0x91c */793#define FBNIC_QUEUE_BDQ_PPQ_SIZE 0x248 /* 0x920 */794#define FBNIC_QUEUE_BDQ_SIZE_MASK CSR_GENMASK(3, 0)795 796#define FBNIC_QUEUE_BDQ_HPQ_BAL 0x260 /* 0x980 */797#define FBNIC_QUEUE_BDQ_HPQ_BAH 0x261 /* 0x984 */798#define FBNIC_QUEUE_BDQ_PPQ_BAL 0x262 /* 0x988 */799#define FBNIC_QUEUE_BDQ_PPQ_BAH 0x263 /* 0x98c */800 801/* Rx DMA Engine Configuration */802#define FBNIC_QUEUE_RDE_CTL0 0x2a0 /* 0xa80 */803#define FBNIC_QUEUE_RDE_CTL0_EN_HDR_SPLIT CSR_BIT(31)804#define FBNIC_QUEUE_RDE_CTL0_DROP_MODE_MASK CSR_GENMASK(30, 29)805enum {806 FBNIC_QUEUE_RDE_CTL0_DROP_IMMEDIATE = 0,807 FBNIC_QUEUE_RDE_CTL0_DROP_WAIT = 1,808 FBNIC_QUEUE_RDE_CTL0_DROP_NEVER = 2,809};810 811#define FBNIC_QUEUE_RDE_CTL0_MIN_HROOM_MASK CSR_GENMASK(28, 20)812#define FBNIC_QUEUE_RDE_CTL0_MIN_TROOM_MASK CSR_GENMASK(19, 11)813 814#define FBNIC_QUEUE_RDE_CTL1 0x2a1 /* 0xa84 */815#define FBNIC_QUEUE_RDE_CTL1_MAX_HDR_MASK CSR_GENMASK(24, 12)816#define FBNIC_QUEUE_RDE_CTL1_PAYLD_OFF_MASK CSR_GENMASK(11, 9)817#define FBNIC_QUEUE_RDE_CTL1_PAYLD_PG_CL_MASK CSR_GENMASK(8, 6)818#define FBNIC_QUEUE_RDE_CTL1_PADLEN_MASK CSR_GENMASK(5, 2)819#define FBNIC_QUEUE_RDE_CTL1_PAYLD_PACK_MASK CSR_GENMASK(1, 0)820enum {821 FBNIC_QUEUE_RDE_CTL1_PAYLD_PACK_NONE = 0,822 FBNIC_QUEUE_RDE_CTL1_PAYLD_PACK_ALL = 1,823 FBNIC_QUEUE_RDE_CTL1_PAYLD_PACK_RSS = 2,824};825 826/* Rx Interrupt Manager Registers */827#define FBNIC_QUEUE_RIM_CTL 0x2c0 /* 0xb00 */828#define FBNIC_QUEUE_RIM_CTL_MSIX_MASK CSR_GENMASK(7, 0)829 830#define FBNIC_QUEUE_RIM_THRESHOLD 0x2c1 /* 0xb04 */831#define FBNIC_QUEUE_RIM_THRESHOLD_RCD_MASK CSR_GENMASK(14, 0)832 833#define FBNIC_QUEUE_RIM_CLEAR 0x2c2 /* 0xb08 */834#define FBNIC_QUEUE_RIM_CLEAR_MASK CSR_BIT(0)835#define FBNIC_QUEUE_RIM_SET 0x2c3 /* 0xb0c */836#define FBNIC_QUEUE_RIM_SET_MASK CSR_BIT(0)837#define FBNIC_QUEUE_RIM_MASK 0x2c4 /* 0xb10 */838#define FBNIC_QUEUE_RIM_MASK_MASK CSR_BIT(0)839 840#define FBNIC_QUEUE_RIM_COAL_STATUS 0x2c5 /* 0xb14 */841#define FBNIC_QUEUE_RIM_RCD_COUNT_MASK CSR_GENMASK(30, 16)842#define FBNIC_QUEUE_RIM_TIMER_MASK CSR_GENMASK(13, 0)843#define FBNIC_MAX_QUEUES 128844#define FBNIC_CSR_END_QUEUE (0x40000 + 0x400 * FBNIC_MAX_QUEUES - 1)845 846/* BAR 4 CSRs */847 848/* The IPC mailbox consists of 32 mailboxes, with each mailbox consisting849 * of 32 4 byte registers. We will use 2 registers per descriptor so the850 * length of the mailbox is reduced to 16.851 *852 * Currently we use an offset of 0x6000 on BAR4 for the mailbox so we just853 * have to do the math and determine the offset based on the mailbox854 * direction and index inside that mailbox.855 */856#define FBNIC_IPC_MBX_DESC_LEN 16857#define FBNIC_IPC_MBX(mbx_idx, desc_idx) \858 ((((mbx_idx) * FBNIC_IPC_MBX_DESC_LEN + (desc_idx)) * 2) + 0x6000)859 860/* Use first register in mailbox to flush writes */861#define FBNIC_FW_ZERO_REG FBNIC_IPC_MBX(0, 0)862 863enum {864 FBNIC_IPC_MBX_RX_IDX,865 FBNIC_IPC_MBX_TX_IDX,866 FBNIC_IPC_MBX_INDICES,867};868 869#define FBNIC_IPC_MBX_DESC_LEN_MASK DESC_GENMASK(63, 48)870#define FBNIC_IPC_MBX_DESC_EOM DESC_BIT(46)871#define FBNIC_IPC_MBX_DESC_ADDR_MASK DESC_GENMASK(45, 3)872#define FBNIC_IPC_MBX_DESC_FW_CMPL DESC_BIT(1)873#define FBNIC_IPC_MBX_DESC_HOST_CMPL DESC_BIT(0)874 875#endif /* _FBNIC_CSR_H_ */876