1212 lines · c
1/* SPDX-License-Identifier: GPL-2.0+ */2/* Copyright (C) 2018 Microchip Technology Inc. */3 4#ifndef _LAN743X_H5#define _LAN743X_H6 7#include <linux/phy.h>8#include <linux/phylink.h>9#include "lan743x_ptp.h"10 11#define DRIVER_AUTHOR "Bryan Whitehead <Bryan.Whitehead@microchip.com>"12#define DRIVER_DESC "LAN743x PCIe Gigabit Ethernet Driver"13#define DRIVER_NAME "lan743x"14 15/* Register Definitions */16#define ID_REV (0x00)17#define ID_REV_ID_MASK_ (0xFFFF0000)18#define ID_REV_ID_LAN7430_ (0x74300000)19#define ID_REV_ID_LAN7431_ (0x74310000)20#define ID_REV_ID_LAN743X_ (0x74300000)21#define ID_REV_ID_A011_ (0xA0110000) // PCI1101022#define ID_REV_ID_A041_ (0xA0410000) // PCI1141423#define ID_REV_ID_A0X1_ (0xA0010000)24#define ID_REV_IS_VALID_CHIP_ID_(id_rev) \25 ((((id_rev) & 0xFFF00000) == ID_REV_ID_LAN743X_) || \26 (((id_rev) & 0xFF0F0000) == ID_REV_ID_A0X1_))27#define ID_REV_CHIP_REV_MASK_ (0x0000FFFF)28#define ID_REV_CHIP_REV_A0_ (0x00000000)29#define ID_REV_CHIP_REV_B0_ (0x00000010)30#define ID_REV_CHIP_REV_PCI11X1X_B0_ (0x000000B0)31 32#define FPGA_REV (0x04)33#define FPGA_REV_GET_MINOR_(fpga_rev) (((fpga_rev) >> 8) & 0x000000FF)34#define FPGA_REV_GET_MAJOR_(fpga_rev) ((fpga_rev) & 0x000000FF)35#define FPGA_SGMII_OP BIT(24)36 37#define STRAP_READ (0x0C)38#define STRAP_READ_USE_SGMII_EN_ BIT(22)39#define STRAP_READ_SGMII_EN_ BIT(6)40#define STRAP_READ_SGMII_REFCLK_ BIT(5)41#define STRAP_READ_SGMII_2_5G_ BIT(4)42#define STRAP_READ_BASE_X_ BIT(3)43#define STRAP_READ_RGMII_TXC_DELAY_EN_ BIT(2)44#define STRAP_READ_RGMII_RXC_DELAY_EN_ BIT(1)45#define STRAP_READ_ADV_PM_DISABLE_ BIT(0)46 47#define HW_CFG (0x010)48#define HW_CFG_RST_PROTECT_PCIE_ BIT(19)49#define HW_CFG_HOT_RESET_DIS_ BIT(15)50#define HW_CFG_D3_VAUX_OVR_ BIT(14)51#define HW_CFG_D3_RESET_DIS_ BIT(13)52#define HW_CFG_RST_PROTECT_ BIT(12)53#define HW_CFG_RELOAD_TYPE_ALL_ (0x00000FC0)54#define HW_CFG_EE_OTP_RELOAD_ BIT(4)55#define HW_CFG_LRST_ BIT(1)56 57#define PMT_CTL (0x014)58#define PMT_CTL_ETH_PHY_D3_COLD_OVR_ BIT(27)59#define PMT_CTL_MAC_D3_RX_CLK_OVR_ BIT(25)60#define PMT_CTL_ETH_PHY_EDPD_PLL_CTL_ BIT(24)61#define PMT_CTL_ETH_PHY_D3_OVR_ BIT(23)62#define PMT_CTL_RX_FCT_RFE_D3_CLK_OVR_ BIT(18)63#define PMT_CTL_GPIO_WAKEUP_EN_ BIT(15)64#define PMT_CTL_EEE_WAKEUP_EN_ BIT(13)65#define PMT_CTL_RES_CLR_WKP_MASK_ GENMASK(9, 8)66#define PMT_CTL_READY_ BIT(7)67#define PMT_CTL_ETH_PHY_RST_ BIT(4)68#define PMT_CTL_WOL_EN_ BIT(3)69#define PMT_CTL_ETH_PHY_WAKE_EN_ BIT(2)70#define PMT_CTL_WUPS_MASK_ (0x00000003)71 72#define DP_SEL (0x024)73#define DP_SEL_DPRDY_ BIT(31)74#define DP_SEL_MASK_ (0x0000001F)75#define DP_SEL_RFE_RAM (0x00000001)76 77#define DP_SEL_VHF_HASH_LEN (16)78#define DP_SEL_VHF_VLAN_LEN (128)79 80#define DP_CMD (0x028)81#define DP_CMD_WRITE_ (0x00000001)82 83#define DP_ADDR (0x02C)84 85#define DP_DATA_0 (0x030)86 87#define E2P_CMD (0x040)88#define E2P_CMD_EPC_BUSY_ BIT(31)89#define E2P_CMD_EPC_CMD_WRITE_ (0x30000000)90#define E2P_CMD_EPC_CMD_EWEN_ (0x20000000)91#define E2P_CMD_EPC_CMD_READ_ (0x00000000)92#define E2P_CMD_EPC_TIMEOUT_ BIT(10)93#define E2P_CMD_EPC_ADDR_MASK_ (0x000001FF)94 95#define E2P_DATA (0x044)96 97/* Hearthstone top level & System Reg Addresses */98#define ETH_CTRL_REG_ADDR_BASE (0x0000)99#define ETH_SYS_REG_ADDR_BASE (0x4000)100#define CONFIG_REG_ADDR_BASE (0x0000)101#define ETH_EEPROM_REG_ADDR_BASE (0x0E00)102#define ETH_OTP_REG_ADDR_BASE (0x1000)103#define GEN_SYS_CONFIG_LOAD_STARTED_REG (0x0078)104#define ETH_SYS_CONFIG_LOAD_STARTED_REG (ETH_SYS_REG_ADDR_BASE + \105 CONFIG_REG_ADDR_BASE + \106 GEN_SYS_CONFIG_LOAD_STARTED_REG)107#define GEN_SYS_LOAD_STARTED_REG_ETH_ BIT(4)108#define SYS_LOCK_REG (0x00A0)109#define SYS_LOCK_REG_MAIN_LOCK_ BIT(7)110#define SYS_LOCK_REG_GEN_PERI_LOCK_ BIT(5)111#define SYS_LOCK_REG_SPI_PERI_LOCK_ BIT(4)112#define SYS_LOCK_REG_SMBUS_PERI_LOCK_ BIT(3)113#define SYS_LOCK_REG_UART_SS_LOCK_ BIT(2)114#define SYS_LOCK_REG_ENET_SS_LOCK_ BIT(1)115#define SYS_LOCK_REG_USB_SS_LOCK_ BIT(0)116#define ETH_SYSTEM_SYS_LOCK_REG (ETH_SYS_REG_ADDR_BASE + \117 CONFIG_REG_ADDR_BASE + \118 SYS_LOCK_REG)119#define HS_EEPROM_REG_ADDR_BASE (ETH_SYS_REG_ADDR_BASE + \120 ETH_EEPROM_REG_ADDR_BASE)121#define HS_E2P_CMD (HS_EEPROM_REG_ADDR_BASE + 0x0000)122#define HS_E2P_CMD_EPC_BUSY_ BIT(31)123#define HS_E2P_CMD_EPC_CMD_WRITE_ GENMASK(29, 28)124#define HS_E2P_CMD_EPC_CMD_READ_ (0x0)125#define HS_E2P_CMD_EPC_TIMEOUT_ BIT(17)126#define HS_E2P_CMD_EPC_ADDR_MASK_ GENMASK(15, 0)127#define HS_E2P_DATA (HS_EEPROM_REG_ADDR_BASE + 0x0004)128#define HS_E2P_DATA_MASK_ GENMASK(7, 0)129#define HS_E2P_CFG (HS_EEPROM_REG_ADDR_BASE + 0x0008)130#define HS_E2P_CFG_I2C_PULSE_MASK_ GENMASK(19, 16)131#define HS_E2P_CFG_EEPROM_SIZE_SEL_ BIT(12)132#define HS_E2P_CFG_I2C_BAUD_RATE_MASK_ GENMASK(9, 8)133#define HS_E2P_CFG_TEST_EEPR_TO_BYP_ BIT(0)134#define HS_E2P_PAD_CTL (HS_EEPROM_REG_ADDR_BASE + 0x000C)135 136#define GPIO_CFG0 (0x050)137#define GPIO_CFG0_GPIO_DIR_BIT_(bit) BIT(16 + (bit))138#define GPIO_CFG0_GPIO_DATA_BIT_(bit) BIT(0 + (bit))139 140#define GPIO_CFG1 (0x054)141#define GPIO_CFG1_GPIOEN_BIT_(bit) BIT(16 + (bit))142#define GPIO_CFG1_GPIOBUF_BIT_(bit) BIT(0 + (bit))143 144#define GPIO_CFG2 (0x058)145#define GPIO_CFG2_1588_POL_BIT_(bit) BIT(0 + (bit))146 147#define GPIO_CFG3 (0x05C)148#define GPIO_CFG3_1588_CH_SEL_BIT_(bit) BIT(16 + (bit))149#define GPIO_CFG3_1588_OE_BIT_(bit) BIT(0 + (bit))150 151#define FCT_RX_CTL (0xAC)152#define FCT_RX_CTL_EN_(channel) BIT(28 + (channel))153#define FCT_RX_CTL_DIS_(channel) BIT(24 + (channel))154#define FCT_RX_CTL_RESET_(channel) BIT(20 + (channel))155 156#define FCT_TX_CTL (0xC4)157#define FCT_TX_CTL_EN_(channel) BIT(28 + (channel))158#define FCT_TX_CTL_DIS_(channel) BIT(24 + (channel))159#define FCT_TX_CTL_RESET_(channel) BIT(20 + (channel))160 161#define FCT_FLOW(rx_channel) (0xE0 + ((rx_channel) << 2))162#define FCT_FLOW_CTL_OFF_THRESHOLD_ (0x00007F00)163#define FCT_FLOW_CTL_OFF_THRESHOLD_SET_(value) \164 ((value << 8) & FCT_FLOW_CTL_OFF_THRESHOLD_)165#define FCT_FLOW_CTL_REQ_EN_ BIT(7)166#define FCT_FLOW_CTL_ON_THRESHOLD_ (0x0000007F)167#define FCT_FLOW_CTL_ON_THRESHOLD_SET_(value) \168 ((value << 0) & FCT_FLOW_CTL_ON_THRESHOLD_)169 170#define MAC_CR (0x100)171#define MAC_CR_MII_EN_ BIT(19)172#define MAC_CR_EEE_EN_ BIT(17)173#define MAC_CR_ADD_ BIT(12)174#define MAC_CR_ASD_ BIT(11)175#define MAC_CR_CNTR_RST_ BIT(5)176#define MAC_CR_DPX_ BIT(3)177#define MAC_CR_CFG_H_ BIT(2)178#define MAC_CR_CFG_L_ BIT(1)179#define MAC_CR_RST_ BIT(0)180 181#define MAC_RX (0x104)182#define MAC_RX_MAX_SIZE_SHIFT_ (16)183#define MAC_RX_MAX_SIZE_MASK_ (0x3FFF0000)184#define MAC_RX_RXD_ BIT(1)185#define MAC_RX_RXEN_ BIT(0)186 187#define MAC_TX (0x108)188#define MAC_TX_TXD_ BIT(1)189#define MAC_TX_TXEN_ BIT(0)190 191#define MAC_FLOW (0x10C)192#define MAC_FLOW_CR_TX_FCEN_ BIT(30)193#define MAC_FLOW_CR_RX_FCEN_ BIT(29)194#define MAC_FLOW_CR_FCPT_MASK_ (0x0000FFFF)195 196#define MAC_RX_ADDRH (0x118)197 198#define MAC_RX_ADDRL (0x11C)199 200#define MAC_MII_ACC (0x120)201#define MAC_MII_ACC_MDC_CYCLE_SHIFT_ (16)202#define MAC_MII_ACC_MDC_CYCLE_MASK_ (0x00070000)203#define MAC_MII_ACC_MDC_CYCLE_2_5MHZ_ (0)204#define MAC_MII_ACC_MDC_CYCLE_5MHZ_ (1)205#define MAC_MII_ACC_MDC_CYCLE_12_5MHZ_ (2)206#define MAC_MII_ACC_MDC_CYCLE_25MHZ_ (3)207#define MAC_MII_ACC_MDC_CYCLE_1_25MHZ_ (4)208#define MAC_MII_ACC_PHY_ADDR_SHIFT_ (11)209#define MAC_MII_ACC_PHY_ADDR_MASK_ (0x0000F800)210#define MAC_MII_ACC_MIIRINDA_SHIFT_ (6)211#define MAC_MII_ACC_MIIRINDA_MASK_ (0x000007C0)212#define MAC_MII_ACC_MII_READ_ (0x00000000)213#define MAC_MII_ACC_MII_WRITE_ (0x00000002)214#define MAC_MII_ACC_MII_BUSY_ BIT(0)215 216#define MAC_MII_ACC_MIIMMD_SHIFT_ (6)217#define MAC_MII_ACC_MIIMMD_MASK_ (0x000007C0)218#define MAC_MII_ACC_MIICL45_ BIT(3)219#define MAC_MII_ACC_MIICMD_MASK_ (0x00000006)220#define MAC_MII_ACC_MIICMD_ADDR_ (0x00000000)221#define MAC_MII_ACC_MIICMD_WRITE_ (0x00000002)222#define MAC_MII_ACC_MIICMD_READ_ (0x00000004)223#define MAC_MII_ACC_MIICMD_READ_INC_ (0x00000006)224 225#define MAC_MII_DATA (0x124)226 227#define MAC_EEE_TX_LPI_REQ_DLY_CNT (0x130)228 229#define MAC_WUCSR (0x140)230#define MAC_MP_SO_EN_ BIT(21)231#define MAC_WUCSR_RFE_WAKE_EN_ BIT(14)232#define MAC_WUCSR_EEE_TX_WAKE_ BIT(13)233#define MAC_WUCSR_EEE_RX_WAKE_ BIT(11)234#define MAC_WUCSR_RFE_WAKE_FR_ BIT(9)235#define MAC_WUCSR_PFDA_FR_ BIT(7)236#define MAC_WUCSR_WUFR_ BIT(6)237#define MAC_WUCSR_MPR_ BIT(5)238#define MAC_WUCSR_BCAST_FR_ BIT(4)239#define MAC_WUCSR_PFDA_EN_ BIT(3)240#define MAC_WUCSR_WAKE_EN_ BIT(2)241#define MAC_WUCSR_MPEN_ BIT(1)242#define MAC_WUCSR_BCST_EN_ BIT(0)243 244#define MAC_WK_SRC (0x144)245#define MAC_WK_SRC_ETH_PHY_WK_ BIT(17)246#define MAC_WK_SRC_IPV6_TCPSYN_RCD_WK_ BIT(16)247#define MAC_WK_SRC_IPV4_TCPSYN_RCD_WK_ BIT(15)248#define MAC_WK_SRC_EEE_TX_WK_ BIT(14)249#define MAC_WK_SRC_EEE_RX_WK_ BIT(13)250#define MAC_WK_SRC_RFE_FR_WK_ BIT(12)251#define MAC_WK_SRC_PFDA_FR_WK_ BIT(11)252#define MAC_WK_SRC_MP_FR_WK_ BIT(10)253#define MAC_WK_SRC_BCAST_FR_WK_ BIT(9)254#define MAC_WK_SRC_WU_FR_WK_ BIT(8)255#define MAC_WK_SRC_WK_FR_SAVED_ BIT(7)256 257#define MAC_MP_SO_HI (0x148)258#define MAC_MP_SO_LO (0x14C)259 260#define MAC_WUF_CFG0 (0x150)261#define MAC_NUM_OF_WUF_CFG (32)262#define MAC_WUF_CFG_BEGIN (MAC_WUF_CFG0)263#define MAC_WUF_CFG(index) (MAC_WUF_CFG_BEGIN + (4 * (index)))264#define MAC_WUF_CFG_EN_ BIT(31)265#define MAC_WUF_CFG_TYPE_MCAST_ (0x02000000)266#define MAC_WUF_CFG_TYPE_ALL_ (0x01000000)267#define MAC_WUF_CFG_OFFSET_SHIFT_ (16)268#define MAC_WUF_CFG_CRC16_MASK_ (0x0000FFFF)269 270#define MAC_WUF_MASK0_0 (0x200)271#define MAC_WUF_MASK0_1 (0x204)272#define MAC_WUF_MASK0_2 (0x208)273#define MAC_WUF_MASK0_3 (0x20C)274#define MAC_WUF_MASK0_BEGIN (MAC_WUF_MASK0_0)275#define MAC_WUF_MASK1_BEGIN (MAC_WUF_MASK0_1)276#define MAC_WUF_MASK2_BEGIN (MAC_WUF_MASK0_2)277#define MAC_WUF_MASK3_BEGIN (MAC_WUF_MASK0_3)278#define MAC_WUF_MASK0(index) (MAC_WUF_MASK0_BEGIN + (0x10 * (index)))279#define MAC_WUF_MASK1(index) (MAC_WUF_MASK1_BEGIN + (0x10 * (index)))280#define MAC_WUF_MASK2(index) (MAC_WUF_MASK2_BEGIN + (0x10 * (index)))281#define MAC_WUF_MASK3(index) (MAC_WUF_MASK3_BEGIN + (0x10 * (index)))282 283/* offset 0x400 - 0x500, x may range from 0 to 32, for a total of 33 entries */284#define RFE_ADDR_FILT_HI(x) (0x400 + (8 * (x)))285#define RFE_ADDR_FILT_HI_VALID_ BIT(31)286 287/* offset 0x404 - 0x504, x may range from 0 to 32, for a total of 33 entries */288#define RFE_ADDR_FILT_LO(x) (0x404 + (8 * (x)))289 290#define RFE_CTL (0x508)291#define RFE_CTL_TCP_UDP_COE_ BIT(12)292#define RFE_CTL_IP_COE_ BIT(11)293#define RFE_CTL_AB_ BIT(10)294#define RFE_CTL_AM_ BIT(9)295#define RFE_CTL_AU_ BIT(8)296#define RFE_CTL_MCAST_HASH_ BIT(3)297#define RFE_CTL_DA_PERFECT_ BIT(1)298 299#define RFE_RSS_CFG (0x554)300#define RFE_RSS_CFG_UDP_IPV6_EX_ BIT(16)301#define RFE_RSS_CFG_TCP_IPV6_EX_ BIT(15)302#define RFE_RSS_CFG_IPV6_EX_ BIT(14)303#define RFE_RSS_CFG_UDP_IPV6_ BIT(13)304#define RFE_RSS_CFG_TCP_IPV6_ BIT(12)305#define RFE_RSS_CFG_IPV6_ BIT(11)306#define RFE_RSS_CFG_UDP_IPV4_ BIT(10)307#define RFE_RSS_CFG_TCP_IPV4_ BIT(9)308#define RFE_RSS_CFG_IPV4_ BIT(8)309#define RFE_RSS_CFG_VALID_HASH_BITS_ (0x000000E0)310#define RFE_RSS_CFG_RSS_QUEUE_ENABLE_ BIT(2)311#define RFE_RSS_CFG_RSS_HASH_STORE_ BIT(1)312#define RFE_RSS_CFG_RSS_ENABLE_ BIT(0)313 314#define RFE_HASH_KEY(index) (0x558 + (index << 2))315 316#define RFE_INDX(index) (0x580 + (index << 2))317 318#define MAC_WUCSR2 (0x600)319#define MAC_WUCSR2_NS_RCD_ BIT(7)320#define MAC_WUCSR2_ARP_RCD_ BIT(6)321#define MAC_WUCSR2_IPV6_TCPSYN_RCD_ BIT(5)322#define MAC_WUCSR2_IPV4_TCPSYN_RCD_ BIT(4)323 324#define SGMII_ACC (0x720)325#define SGMII_ACC_SGMII_BZY_ BIT(31)326#define SGMII_ACC_SGMII_WR_ BIT(30)327#define SGMII_ACC_SGMII_MMD_SHIFT_ (16)328#define SGMII_ACC_SGMII_MMD_MASK_ GENMASK(20, 16)329#define SGMII_ACC_SGMII_MMD_VSR_ BIT(15)330#define SGMII_ACC_SGMII_ADDR_SHIFT_ (0)331#define SGMII_ACC_SGMII_ADDR_MASK_ GENMASK(15, 0)332#define SGMII_DATA (0x724)333#define SGMII_DATA_SHIFT_ (0)334#define SGMII_DATA_MASK_ GENMASK(15, 0)335#define SGMII_CTL (0x728)336#define SGMII_CTL_SGMII_ENABLE_ BIT(31)337#define SGMII_CTL_LINK_STATUS_SOURCE_ BIT(8)338#define SGMII_CTL_SGMII_POWER_DN_ BIT(1)339 340#define MISC_CTL_0 (0x920)341#define MISC_CTL_0_RFE_READ_FIFO_MASK_ GENMASK(6, 4)342 343/* Vendor Specific SGMII MMD details */344#define SR_VSMMD_PCS_ID1 0x0004345#define SR_VSMMD_PCS_ID2 0x0005346#define SR_VSMMD_STS 0x0008347#define SR_VSMMD_CTRL 0x0009348 349#define VR_MII_DIG_CTRL1 0x8000350#define VR_MII_DIG_CTRL1_VR_RST_ BIT(15)351#define VR_MII_DIG_CTRL1_R2TLBE_ BIT(14)352#define VR_MII_DIG_CTRL1_EN_VSMMD1_ BIT(13)353#define VR_MII_DIG_CTRL1_CS_EN_ BIT(10)354#define VR_MII_DIG_CTRL1_MAC_AUTO_SW_ BIT(9)355#define VR_MII_DIG_CTRL1_INIT_ BIT(8)356#define VR_MII_DIG_CTRL1_DTXLANED_0_ BIT(4)357#define VR_MII_DIG_CTRL1_CL37_TMR_OVR_RIDE_ BIT(3)358#define VR_MII_DIG_CTRL1_EN_2_5G_MODE_ BIT(2)359#define VR_MII_DIG_CTRL1_BYP_PWRUP_ BIT(1)360#define VR_MII_DIG_CTRL1_PHY_MODE_CTRL_ BIT(0)361#define VR_MII_AN_CTRL 0x8001362#define VR_MII_AN_CTRL_MII_CTRL_ BIT(8)363#define VR_MII_AN_CTRL_SGMII_LINK_STS_ BIT(4)364#define VR_MII_AN_CTRL_TX_CONFIG_ BIT(3)365#define VR_MII_AN_CTRL_1000BASE_X_ (0)366#define VR_MII_AN_CTRL_SGMII_MODE_ (2)367#define VR_MII_AN_CTRL_QSGMII_MODE_ (3)368#define VR_MII_AN_CTRL_PCS_MODE_SHIFT_ (1)369#define VR_MII_AN_CTRL_PCS_MODE_MASK_ GENMASK(2, 1)370#define VR_MII_AN_CTRL_MII_AN_INTR_EN_ BIT(0)371#define VR_MII_AN_INTR_STS 0x8002372#define VR_MII_AN_INTR_STS_LINK_UP_ BIT(4)373#define VR_MII_AN_INTR_STS_SPEED_MASK_ GENMASK(3, 2)374#define VR_MII_AN_INTR_STS_1000_MBPS_ BIT(3)375#define VR_MII_AN_INTR_STS_100_MBPS_ BIT(2)376#define VR_MII_AN_INTR_STS_10_MBPS_ (0)377#define VR_MII_AN_INTR_STS_FDX_ BIT(1)378#define VR_MII_AN_INTR_STS_CL37_ANCMPLT_INTR_ BIT(0)379 380#define VR_MII_LINK_TIMER_CTRL 0x800A381#define VR_MII_DIG_STS 0x8010382#define VR_MII_DIG_STS_PSEQ_STATE_MASK_ GENMASK(4, 2)383#define VR_MII_DIG_STS_PSEQ_STATE_POS_ (2)384#define VR_MII_GEN2_4_MPLL_CTRL0 0x8078385#define VR_MII_MPLL_CTRL0_REF_CLK_DIV2_ BIT(12)386#define VR_MII_MPLL_CTRL0_USE_REFCLK_PAD_ BIT(4)387#define VR_MII_GEN2_4_MPLL_CTRL1 0x8079388#define VR_MII_MPLL_CTRL1_MPLL_MULTIPLIER_ GENMASK(6, 0)389#define VR_MII_BAUD_RATE_3P125GBPS (3125)390#define VR_MII_BAUD_RATE_1P25GBPS (1250)391#define VR_MII_MPLL_MULTIPLIER_125 (125)392#define VR_MII_MPLL_MULTIPLIER_100 (100)393#define VR_MII_MPLL_MULTIPLIER_50 (50)394#define VR_MII_MPLL_MULTIPLIER_40 (40)395#define VR_MII_GEN2_4_MISC_CTRL1 0x809A396#define VR_MII_CTRL1_RX_RATE_0_MASK_ GENMASK(3, 2)397#define VR_MII_CTRL1_RX_RATE_0_SHIFT_ (2)398#define VR_MII_CTRL1_TX_RATE_0_MASK_ GENMASK(1, 0)399#define VR_MII_MPLL_BAUD_CLK (0)400#define VR_MII_MPLL_BAUD_CLK_DIV_2 (1)401#define VR_MII_MPLL_BAUD_CLK_DIV_4 (2)402 403#define INT_STS (0x780)404#define INT_BIT_DMA_RX_(channel) BIT(24 + (channel))405#define INT_BIT_ALL_RX_ (0x0F000000)406#define INT_BIT_DMA_TX_(channel) BIT(16 + (channel))407#define INT_BIT_ALL_TX_ (0x000F0000)408#define INT_BIT_SW_GP_ BIT(9)409#define INT_BIT_1588_ BIT(7)410#define INT_BIT_ALL_OTHER_ (INT_BIT_SW_GP_ | INT_BIT_1588_)411#define INT_BIT_MAS_ BIT(0)412 413#define INT_SET (0x784)414 415#define INT_EN_SET (0x788)416 417#define INT_EN_CLR (0x78C)418 419#define INT_STS_R2C (0x790)420 421#define INT_VEC_EN_SET (0x794)422#define INT_VEC_EN_CLR (0x798)423#define INT_VEC_EN_AUTO_CLR (0x79C)424#define INT_VEC_EN_(vector_index) BIT(0 + vector_index)425 426#define INT_VEC_MAP0 (0x7A0)427#define INT_VEC_MAP0_RX_VEC_(channel, vector) \428 (((u32)(vector)) << ((channel) << 2))429 430#define INT_VEC_MAP1 (0x7A4)431#define INT_VEC_MAP1_TX_VEC_(channel, vector) \432 (((u32)(vector)) << ((channel) << 2))433 434#define INT_VEC_MAP2 (0x7A8)435 436#define INT_MOD_MAP0 (0x7B0)437 438#define INT_MOD_MAP1 (0x7B4)439 440#define INT_MOD_MAP2 (0x7B8)441 442#define INT_MOD_CFG0 (0x7C0)443#define INT_MOD_CFG1 (0x7C4)444#define INT_MOD_CFG2 (0x7C8)445#define INT_MOD_CFG3 (0x7CC)446#define INT_MOD_CFG4 (0x7D0)447#define INT_MOD_CFG5 (0x7D4)448#define INT_MOD_CFG6 (0x7D8)449#define INT_MOD_CFG7 (0x7DC)450#define INT_MOD_CFG8 (0x7E0)451#define INT_MOD_CFG9 (0x7E4)452 453#define PTP_CMD_CTL (0x0A00)454#define PTP_CMD_CTL_PTP_LTC_TARGET_READ_ BIT(13)455#define PTP_CMD_CTL_PTP_CLK_STP_NSEC_ BIT(6)456#define PTP_CMD_CTL_PTP_CLOCK_STEP_SEC_ BIT(5)457#define PTP_CMD_CTL_PTP_CLOCK_LOAD_ BIT(4)458#define PTP_CMD_CTL_PTP_CLOCK_READ_ BIT(3)459#define PTP_CMD_CTL_PTP_ENABLE_ BIT(2)460#define PTP_CMD_CTL_PTP_DISABLE_ BIT(1)461#define PTP_CMD_CTL_PTP_RESET_ BIT(0)462#define PTP_GENERAL_CONFIG (0x0A04)463#define PTP_GENERAL_CONFIG_CLOCK_EVENT_X_MASK_(channel) \464 (0x7 << (1 + ((channel) << 2)))465#define PTP_GENERAL_CONFIG_CLOCK_EVENT_100NS_ (0)466#define PTP_GENERAL_CONFIG_CLOCK_EVENT_10US_ (1)467#define PTP_GENERAL_CONFIG_CLOCK_EVENT_100US_ (2)468#define PTP_GENERAL_CONFIG_CLOCK_EVENT_1MS_ (3)469#define PTP_GENERAL_CONFIG_CLOCK_EVENT_10MS_ (4)470#define PTP_GENERAL_CONFIG_CLOCK_EVENT_200MS_ (5)471#define PTP_GENERAL_CONFIG_CLOCK_EVENT_TOGGLE_ (6)472#define PTP_GENERAL_CONFIG_CLOCK_EVENT_X_SET_(channel, value) \473 (((value) & 0x7) << (1 + ((channel) << 2)))474#define PTP_GENERAL_CONFIG_RELOAD_ADD_X_(channel) (BIT((channel) << 2))475 476#define HS_PTP_GENERAL_CONFIG (0x0A04)477#define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_X_MASK_(channel) \478 (0xf << (4 + ((channel) << 2)))479#define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_100NS_ (0)480#define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_500NS_ (1)481#define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_1US_ (2)482#define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_5US_ (3)483#define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_10US_ (4)484#define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_50US_ (5)485#define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_100US_ (6)486#define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_500US_ (7)487#define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_1MS_ (8)488#define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_5MS_ (9)489#define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_10MS_ (10)490#define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_50MS_ (11)491#define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_100MS_ (12)492#define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_200MS_ (13)493#define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_TOGG_ (14)494#define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_INT_ (15)495#define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_X_SET_(channel, value) \496 (((value) & 0xf) << (4 + ((channel) << 2)))497#define HS_PTP_GENERAL_CONFIG_EVENT_POL_X_(channel) (BIT(1 + ((channel) * 2)))498#define HS_PTP_GENERAL_CONFIG_RELOAD_ADD_X_(channel) (BIT((channel) * 2))499 500#define PTP_INT_STS (0x0A08)501#define PTP_INT_IO_FE_MASK_ GENMASK(31, 24)502#define PTP_INT_IO_FE_SHIFT_ (24)503#define PTP_INT_IO_FE_SET_(channel) BIT(24 + (channel))504#define PTP_INT_IO_RE_MASK_ GENMASK(23, 16)505#define PTP_INT_IO_RE_SHIFT_ (16)506#define PTP_INT_IO_RE_SET_(channel) BIT(16 + (channel))507#define PTP_INT_TX_TS_OVRFL_INT_ BIT(14)508#define PTP_INT_TX_SWTS_ERR_INT_ BIT(13)509#define PTP_INT_TX_TS_INT_ BIT(12)510#define PTP_INT_RX_TS_OVRFL_INT_ BIT(9)511#define PTP_INT_RX_TS_INT_ BIT(8)512#define PTP_INT_TIMER_INT_B_ BIT(1)513#define PTP_INT_TIMER_INT_A_ BIT(0)514#define PTP_INT_EN_SET (0x0A0C)515#define PTP_INT_EN_FE_EN_SET_(channel) BIT(24 + (channel))516#define PTP_INT_EN_RE_EN_SET_(channel) BIT(16 + (channel))517#define PTP_INT_EN_TIMER_SET_(channel) BIT(channel)518#define PTP_INT_EN_CLR (0x0A10)519#define PTP_INT_EN_FE_EN_CLR_(channel) BIT(24 + (channel))520#define PTP_INT_EN_RE_EN_CLR_(channel) BIT(16 + (channel))521#define PTP_INT_BIT_TX_SWTS_ERR_ BIT(13)522#define PTP_INT_BIT_TX_TS_ BIT(12)523#define PTP_INT_BIT_TIMER_B_ BIT(1)524#define PTP_INT_BIT_TIMER_A_ BIT(0)525 526#define PTP_CLOCK_SEC (0x0A14)527#define PTP_CLOCK_NS (0x0A18)528#define PTP_CLOCK_SUBNS (0x0A1C)529#define PTP_CLOCK_RATE_ADJ (0x0A20)530#define PTP_CLOCK_RATE_ADJ_DIR_ BIT(31)531#define PTP_CLOCK_STEP_ADJ (0x0A2C)532#define PTP_CLOCK_STEP_ADJ_DIR_ BIT(31)533#define PTP_CLOCK_STEP_ADJ_VALUE_MASK_ (0x3FFFFFFF)534#define PTP_CLOCK_TARGET_SEC_X(channel) (0x0A30 + ((channel) << 4))535#define PTP_CLOCK_TARGET_NS_X(channel) (0x0A34 + ((channel) << 4))536#define PTP_CLOCK_TARGET_RELOAD_SEC_X(channel) (0x0A38 + ((channel) << 4))537#define PTP_CLOCK_TARGET_RELOAD_NS_X(channel) (0x0A3C + ((channel) << 4))538#define PTP_LTC_SET_SEC_HI (0x0A50)539#define PTP_LTC_SET_SEC_HI_SEC_47_32_MASK_ GENMASK(15, 0)540#define PTP_VERSION (0x0A54)541#define PTP_VERSION_TX_UP_MASK_ GENMASK(31, 24)542#define PTP_VERSION_TX_LO_MASK_ GENMASK(23, 16)543#define PTP_VERSION_RX_UP_MASK_ GENMASK(15, 8)544#define PTP_VERSION_RX_LO_MASK_ GENMASK(7, 0)545#define PTP_IO_SEL (0x0A58)546#define PTP_IO_SEL_MASK_ GENMASK(10, 8)547#define PTP_IO_SEL_SHIFT_ (8)548#define PTP_LATENCY (0x0A5C)549#define PTP_LATENCY_TX_SET_(tx_latency) (((u32)(tx_latency)) << 16)550#define PTP_LATENCY_RX_SET_(rx_latency) \551 (((u32)(rx_latency)) & 0x0000FFFF)552#define PTP_CAP_INFO (0x0A60)553#define PTP_CAP_INFO_TX_TS_CNT_GET_(reg_val) (((reg_val) & 0x00000070) >> 4)554#define PTP_RX_TS_CFG (0x0A68)555#define PTP_RX_TS_CFG_EVENT_MSGS_ GENMASK(3, 0)556 557#define PTP_TX_MOD (0x0AA4)558#define PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_ (0x10000000)559 560#define PTP_TX_MOD2 (0x0AA8)561#define PTP_TX_MOD2_TX_PTP_CLR_UDPV4_CHKSUM_ (0x00000001)562 563#define PTP_TX_EGRESS_SEC (0x0AAC)564#define PTP_TX_EGRESS_NS (0x0AB0)565#define PTP_TX_EGRESS_NS_CAPTURE_CAUSE_MASK_ (0xC0000000)566#define PTP_TX_EGRESS_NS_CAPTURE_CAUSE_AUTO_ (0x00000000)567#define PTP_TX_EGRESS_NS_CAPTURE_CAUSE_SW_ (0x40000000)568#define PTP_TX_EGRESS_NS_TS_NS_MASK_ (0x3FFFFFFF)569 570#define PTP_TX_MSG_HEADER (0x0AB4)571#define PTP_TX_MSG_HEADER_MSG_TYPE_ (0x000F0000)572#define PTP_TX_MSG_HEADER_MSG_TYPE_SYNC_ (0x00000000)573 574#define PTP_TX_CAP_INFO (0x0AB8)575#define PTP_TX_CAP_INFO_TX_CH_MASK_ GENMASK(1, 0)576#define PTP_TX_DOMAIN (0x0ABC)577#define PTP_TX_DOMAIN_MASK_ GENMASK(23, 16)578#define PTP_TX_DOMAIN_RANGE_EN_ BIT(15)579#define PTP_TX_DOMAIN_RANGE_MASK_ GENMASK(7, 0)580#define PTP_TX_SDOID (0x0AC0)581#define PTP_TX_SDOID_MASK_ GENMASK(23, 16)582#define PTP_TX_SDOID_RANGE_EN_ BIT(15)583#define PTP_TX_SDOID_11_0_MASK_ GENMASK(7, 0)584#define PTP_IO_CAP_CONFIG (0x0AC4)585#define PTP_IO_CAP_CONFIG_LOCK_FE_(channel) BIT(24 + (channel))586#define PTP_IO_CAP_CONFIG_LOCK_RE_(channel) BIT(16 + (channel))587#define PTP_IO_CAP_CONFIG_FE_CAP_EN_(channel) BIT(8 + (channel))588#define PTP_IO_CAP_CONFIG_RE_CAP_EN_(channel) BIT(0 + (channel))589#define PTP_IO_RE_LTC_SEC_CAP_X (0x0AC8)590#define PTP_IO_RE_LTC_NS_CAP_X (0x0ACC)591#define PTP_IO_FE_LTC_SEC_CAP_X (0x0AD0)592#define PTP_IO_FE_LTC_NS_CAP_X (0x0AD4)593#define PTP_IO_EVENT_OUTPUT_CFG (0x0AD8)594#define PTP_IO_EVENT_OUTPUT_CFG_SEL_(channel) BIT(16 + (channel))595#define PTP_IO_EVENT_OUTPUT_CFG_EN_(channel) BIT(0 + (channel))596#define PTP_IO_PIN_CFG (0x0ADC)597#define PTP_IO_PIN_CFG_OBUF_TYPE_(channel) BIT(0 + (channel))598#define PTP_LTC_RD_SEC_HI (0x0AF0)599#define PTP_LTC_RD_SEC_HI_SEC_47_32_MASK_ GENMASK(15, 0)600#define PTP_LTC_RD_SEC_LO (0x0AF4)601#define PTP_LTC_RD_NS (0x0AF8)602#define PTP_LTC_RD_NS_29_0_MASK_ GENMASK(29, 0)603#define PTP_LTC_RD_SUBNS (0x0AFC)604#define PTP_RX_USER_MAC_HI (0x0B00)605#define PTP_RX_USER_MAC_HI_47_32_MASK_ GENMASK(15, 0)606#define PTP_RX_USER_MAC_LO (0x0B04)607#define PTP_RX_USER_IP_ADDR_0 (0x0B20)608#define PTP_RX_USER_IP_ADDR_1 (0x0B24)609#define PTP_RX_USER_IP_ADDR_2 (0x0B28)610#define PTP_RX_USER_IP_ADDR_3 (0x0B2C)611#define PTP_RX_USER_IP_MASK_0 (0x0B30)612#define PTP_RX_USER_IP_MASK_1 (0x0B34)613#define PTP_RX_USER_IP_MASK_2 (0x0B38)614#define PTP_RX_USER_IP_MASK_3 (0x0B3C)615#define PTP_TX_USER_MAC_HI (0x0B40)616#define PTP_TX_USER_MAC_HI_47_32_MASK_ GENMASK(15, 0)617#define PTP_TX_USER_MAC_LO (0x0B44)618#define PTP_TX_USER_IP_ADDR_0 (0x0B60)619#define PTP_TX_USER_IP_ADDR_1 (0x0B64)620#define PTP_TX_USER_IP_ADDR_2 (0x0B68)621#define PTP_TX_USER_IP_ADDR_3 (0x0B6C)622#define PTP_TX_USER_IP_MASK_0 (0x0B70)623#define PTP_TX_USER_IP_MASK_1 (0x0B74)624#define PTP_TX_USER_IP_MASK_2 (0x0B78)625#define PTP_TX_USER_IP_MASK_3 (0x0B7C)626 627#define DMAC_CFG (0xC00)628#define DMAC_CFG_COAL_EN_ BIT(16)629#define DMAC_CFG_CH_ARB_SEL_RX_HIGH_ (0x00000000)630#define DMAC_CFG_MAX_READ_REQ_MASK_ (0x00000070)631#define DMAC_CFG_MAX_READ_REQ_SET_(val) \632 ((((u32)(val)) << 4) & DMAC_CFG_MAX_READ_REQ_MASK_)633#define DMAC_CFG_MAX_DSPACE_16_ (0x00000000)634#define DMAC_CFG_MAX_DSPACE_32_ (0x00000001)635#define DMAC_CFG_MAX_DSPACE_64_ BIT(1)636#define DMAC_CFG_MAX_DSPACE_128_ (0x00000003)637 638#define DMAC_COAL_CFG (0xC04)639#define DMAC_COAL_CFG_TIMER_LIMIT_MASK_ (0xFFF00000)640#define DMAC_COAL_CFG_TIMER_LIMIT_SET_(val) \641 ((((u32)(val)) << 20) & DMAC_COAL_CFG_TIMER_LIMIT_MASK_)642#define DMAC_COAL_CFG_TIMER_TX_START_ BIT(19)643#define DMAC_COAL_CFG_FLUSH_INTS_ BIT(18)644#define DMAC_COAL_CFG_INT_EXIT_COAL_ BIT(17)645#define DMAC_COAL_CFG_CSR_EXIT_COAL_ BIT(16)646#define DMAC_COAL_CFG_TX_THRES_MASK_ (0x0000FF00)647#define DMAC_COAL_CFG_TX_THRES_SET_(val) \648 ((((u32)(val)) << 8) & DMAC_COAL_CFG_TX_THRES_MASK_)649#define DMAC_COAL_CFG_RX_THRES_MASK_ (0x000000FF)650#define DMAC_COAL_CFG_RX_THRES_SET_(val) \651 (((u32)(val)) & DMAC_COAL_CFG_RX_THRES_MASK_)652 653#define DMAC_OBFF_CFG (0xC08)654#define DMAC_OBFF_TX_THRES_MASK_ (0x0000FF00)655#define DMAC_OBFF_TX_THRES_SET_(val) \656 ((((u32)(val)) << 8) & DMAC_OBFF_TX_THRES_MASK_)657#define DMAC_OBFF_RX_THRES_MASK_ (0x000000FF)658#define DMAC_OBFF_RX_THRES_SET_(val) \659 (((u32)(val)) & DMAC_OBFF_RX_THRES_MASK_)660 661#define DMAC_CMD (0xC0C)662#define DMAC_CMD_SWR_ BIT(31)663#define DMAC_CMD_TX_SWR_(channel) BIT(24 + (channel))664#define DMAC_CMD_START_T_(channel) BIT(20 + (channel))665#define DMAC_CMD_STOP_T_(channel) BIT(16 + (channel))666#define DMAC_CMD_RX_SWR_(channel) BIT(8 + (channel))667#define DMAC_CMD_START_R_(channel) BIT(4 + (channel))668#define DMAC_CMD_STOP_R_(channel) BIT(0 + (channel))669 670#define DMAC_INT_STS (0xC10)671#define DMAC_INT_EN_SET (0xC14)672#define DMAC_INT_EN_CLR (0xC18)673#define DMAC_INT_BIT_RXFRM_(channel) BIT(16 + (channel))674#define DMAC_INT_BIT_TX_IOC_(channel) BIT(0 + (channel))675 676#define RX_CFG_A(channel) (0xC40 + ((channel) << 6))677#define RX_CFG_A_RX_WB_ON_INT_TMR_ BIT(30)678#define RX_CFG_A_RX_WB_THRES_MASK_ (0x1F000000)679#define RX_CFG_A_RX_WB_THRES_SET_(val) \680 ((((u32)(val)) << 24) & RX_CFG_A_RX_WB_THRES_MASK_)681#define RX_CFG_A_RX_PF_THRES_MASK_ (0x001F0000)682#define RX_CFG_A_RX_PF_THRES_SET_(val) \683 ((((u32)(val)) << 16) & RX_CFG_A_RX_PF_THRES_MASK_)684#define RX_CFG_A_RX_PF_PRI_THRES_MASK_ (0x00001F00)685#define RX_CFG_A_RX_PF_PRI_THRES_SET_(val) \686 ((((u32)(val)) << 8) & RX_CFG_A_RX_PF_PRI_THRES_MASK_)687#define RX_CFG_A_RX_HP_WB_EN_ BIT(5)688 689#define RX_CFG_B(channel) (0xC44 + ((channel) << 6))690#define RX_CFG_B_TS_ALL_RX_ BIT(29)691#define RX_CFG_B_TS_DESCR_EN_ BIT(28)692#define RX_CFG_B_TS_NONE_ 0693#define RX_CFG_B_TS_MASK_ (0xCFFFFFFF)694#define RX_CFG_B_RX_PAD_MASK_ (0x03000000)695#define RX_CFG_B_RX_PAD_0_ (0x00000000)696#define RX_CFG_B_RX_PAD_2_ (0x02000000)697#define RX_CFG_B_RDMABL_512_ (0x00040000)698#define RX_CFG_B_RX_RING_LEN_MASK_ (0x0000FFFF)699 700#define RX_BASE_ADDRH(channel) (0xC48 + ((channel) << 6))701 702#define RX_BASE_ADDRL(channel) (0xC4C + ((channel) << 6))703 704#define RX_HEAD_WRITEBACK_ADDRH(channel) (0xC50 + ((channel) << 6))705 706#define RX_HEAD_WRITEBACK_ADDRL(channel) (0xC54 + ((channel) << 6))707 708#define RX_HEAD(channel) (0xC58 + ((channel) << 6))709 710#define RX_TAIL(channel) (0xC5C + ((channel) << 6))711#define RX_TAIL_SET_TOP_INT_EN_ BIT(30)712#define RX_TAIL_SET_TOP_INT_VEC_EN_ BIT(29)713 714#define RX_CFG_C(channel) (0xC64 + ((channel) << 6))715#define RX_CFG_C_RX_TOP_INT_EN_AUTO_CLR_ BIT(6)716#define RX_CFG_C_RX_INT_EN_R2C_ BIT(4)717#define RX_CFG_C_RX_DMA_INT_STS_AUTO_CLR_ BIT(3)718#define RX_CFG_C_RX_INT_STS_R2C_MODE_MASK_ (0x00000007)719 720#define TX_CFG_A(channel) (0xD40 + ((channel) << 6))721#define TX_CFG_A_TX_HP_WB_ON_INT_TMR_ BIT(30)722#define TX_CFG_A_TX_TMR_HPWB_SEL_IOC_ (0x10000000)723#define TX_CFG_A_TX_PF_THRES_MASK_ (0x001F0000)724#define TX_CFG_A_TX_PF_THRES_SET_(value) \725 ((((u32)(value)) << 16) & TX_CFG_A_TX_PF_THRES_MASK_)726#define TX_CFG_A_TX_PF_PRI_THRES_MASK_ (0x00001F00)727#define TX_CFG_A_TX_PF_PRI_THRES_SET_(value) \728 ((((u32)(value)) << 8) & TX_CFG_A_TX_PF_PRI_THRES_MASK_)729#define TX_CFG_A_TX_HP_WB_EN_ BIT(5)730#define TX_CFG_A_TX_HP_WB_THRES_MASK_ (0x0000000F)731#define TX_CFG_A_TX_HP_WB_THRES_SET_(value) \732 (((u32)(value)) & TX_CFG_A_TX_HP_WB_THRES_MASK_)733 734#define TX_CFG_B(channel) (0xD44 + ((channel) << 6))735#define TX_CFG_B_TDMABL_512_ (0x00040000)736#define TX_CFG_B_TX_RING_LEN_MASK_ (0x0000FFFF)737 738#define TX_BASE_ADDRH(channel) (0xD48 + ((channel) << 6))739 740#define TX_BASE_ADDRL(channel) (0xD4C + ((channel) << 6))741 742#define TX_HEAD_WRITEBACK_ADDRH(channel) (0xD50 + ((channel) << 6))743 744#define TX_HEAD_WRITEBACK_ADDRL(channel) (0xD54 + ((channel) << 6))745 746#define TX_HEAD(channel) (0xD58 + ((channel) << 6))747 748#define TX_TAIL(channel) (0xD5C + ((channel) << 6))749#define TX_TAIL_SET_DMAC_INT_EN_ BIT(31)750#define TX_TAIL_SET_TOP_INT_EN_ BIT(30)751#define TX_TAIL_SET_TOP_INT_VEC_EN_ BIT(29)752 753#define TX_CFG_C(channel) (0xD64 + ((channel) << 6))754#define TX_CFG_C_TX_TOP_INT_EN_AUTO_CLR_ BIT(6)755#define TX_CFG_C_TX_DMA_INT_EN_AUTO_CLR_ BIT(5)756#define TX_CFG_C_TX_INT_EN_R2C_ BIT(4)757#define TX_CFG_C_TX_DMA_INT_STS_AUTO_CLR_ BIT(3)758#define TX_CFG_C_TX_INT_STS_R2C_MODE_MASK_ (0x00000007)759 760#define OTP_PWR_DN (0x1000)761#define OTP_PWR_DN_PWRDN_N_ BIT(0)762 763#define OTP_ADDR_HIGH (0x1004)764#define OTP_ADDR_LOW (0x1008)765 766#define OTP_PRGM_DATA (0x1010)767 768#define OTP_PRGM_MODE (0x1014)769#define OTP_PRGM_MODE_BYTE_ BIT(0)770 771#define OTP_READ_DATA (0x1018)772 773#define OTP_FUNC_CMD (0x1020)774#define OTP_FUNC_CMD_READ_ BIT(0)775 776#define OTP_TST_CMD (0x1024)777#define OTP_TST_CMD_PRGVRFY_ BIT(3)778 779#define OTP_CMD_GO (0x1028)780#define OTP_CMD_GO_GO_ BIT(0)781 782#define OTP_STATUS (0x1030)783#define OTP_STATUS_BUSY_ BIT(0)784 785/* Hearthstone OTP block registers */786#define HS_OTP_BLOCK_BASE (ETH_SYS_REG_ADDR_BASE + \787 ETH_OTP_REG_ADDR_BASE)788#define HS_OTP_PWR_DN (HS_OTP_BLOCK_BASE + 0x0)789#define HS_OTP_ADDR_HIGH (HS_OTP_BLOCK_BASE + 0x4)790#define HS_OTP_ADDR_LOW (HS_OTP_BLOCK_BASE + 0x8)791#define HS_OTP_PRGM_DATA (HS_OTP_BLOCK_BASE + 0x10)792#define HS_OTP_PRGM_MODE (HS_OTP_BLOCK_BASE + 0x14)793#define HS_OTP_READ_DATA (HS_OTP_BLOCK_BASE + 0x18)794#define HS_OTP_FUNC_CMD (HS_OTP_BLOCK_BASE + 0x20)795#define HS_OTP_TST_CMD (HS_OTP_BLOCK_BASE + 0x24)796#define HS_OTP_CMD_GO (HS_OTP_BLOCK_BASE + 0x28)797#define HS_OTP_STATUS (HS_OTP_BLOCK_BASE + 0x30)798 799/* MAC statistics registers */800#define STAT_RX_FCS_ERRORS (0x1200)801#define STAT_RX_ALIGNMENT_ERRORS (0x1204)802#define STAT_RX_FRAGMENT_ERRORS (0x1208)803#define STAT_RX_JABBER_ERRORS (0x120C)804#define STAT_RX_UNDERSIZE_FRAME_ERRORS (0x1210)805#define STAT_RX_OVERSIZE_FRAME_ERRORS (0x1214)806#define STAT_RX_DROPPED_FRAMES (0x1218)807#define STAT_RX_UNICAST_BYTE_COUNT (0x121C)808#define STAT_RX_BROADCAST_BYTE_COUNT (0x1220)809#define STAT_RX_MULTICAST_BYTE_COUNT (0x1224)810#define STAT_RX_UNICAST_FRAMES (0x1228)811#define STAT_RX_BROADCAST_FRAMES (0x122C)812#define STAT_RX_MULTICAST_FRAMES (0x1230)813#define STAT_RX_PAUSE_FRAMES (0x1234)814#define STAT_RX_64_BYTE_FRAMES (0x1238)815#define STAT_RX_65_127_BYTE_FRAMES (0x123C)816#define STAT_RX_128_255_BYTE_FRAMES (0x1240)817#define STAT_RX_256_511_BYTES_FRAMES (0x1244)818#define STAT_RX_512_1023_BYTE_FRAMES (0x1248)819#define STAT_RX_1024_1518_BYTE_FRAMES (0x124C)820#define STAT_RX_GREATER_1518_BYTE_FRAMES (0x1250)821#define STAT_RX_TOTAL_FRAMES (0x1254)822#define STAT_EEE_RX_LPI_TRANSITIONS (0x1258)823#define STAT_EEE_RX_LPI_TIME (0x125C)824#define STAT_RX_COUNTER_ROLLOVER_STATUS (0x127C)825 826#define STAT_TX_FCS_ERRORS (0x1280)827#define STAT_TX_EXCESS_DEFERRAL_ERRORS (0x1284)828#define STAT_TX_CARRIER_ERRORS (0x1288)829#define STAT_TX_BAD_BYTE_COUNT (0x128C)830#define STAT_TX_SINGLE_COLLISIONS (0x1290)831#define STAT_TX_MULTIPLE_COLLISIONS (0x1294)832#define STAT_TX_EXCESSIVE_COLLISION (0x1298)833#define STAT_TX_LATE_COLLISIONS (0x129C)834#define STAT_TX_UNICAST_BYTE_COUNT (0x12A0)835#define STAT_TX_BROADCAST_BYTE_COUNT (0x12A4)836#define STAT_TX_MULTICAST_BYTE_COUNT (0x12A8)837#define STAT_TX_UNICAST_FRAMES (0x12AC)838#define STAT_TX_BROADCAST_FRAMES (0x12B0)839#define STAT_TX_MULTICAST_FRAMES (0x12B4)840#define STAT_TX_PAUSE_FRAMES (0x12B8)841#define STAT_TX_64_BYTE_FRAMES (0x12BC)842#define STAT_TX_65_127_BYTE_FRAMES (0x12C0)843#define STAT_TX_128_255_BYTE_FRAMES (0x12C4)844#define STAT_TX_256_511_BYTES_FRAMES (0x12C8)845#define STAT_TX_512_1023_BYTE_FRAMES (0x12CC)846#define STAT_TX_1024_1518_BYTE_FRAMES (0x12D0)847#define STAT_TX_GREATER_1518_BYTE_FRAMES (0x12D4)848#define STAT_TX_TOTAL_FRAMES (0x12D8)849#define STAT_EEE_TX_LPI_TRANSITIONS (0x12DC)850#define STAT_EEE_TX_LPI_TIME (0x12E0)851#define STAT_TX_COUNTER_ROLLOVER_STATUS (0x12FC)852 853/* End of Register definitions */854 855#define LAN743X_MAX_RX_CHANNELS (4)856#define LAN743X_MAX_TX_CHANNELS (1)857#define PCI11X1X_MAX_TX_CHANNELS (4)858struct lan743x_adapter;859 860#define LAN743X_USED_RX_CHANNELS (4)861#define LAN743X_USED_TX_CHANNELS (1)862#define PCI11X1X_USED_TX_CHANNELS (4)863#define LAN743X_INT_MOD (400)864 865#if (LAN743X_USED_RX_CHANNELS > LAN743X_MAX_RX_CHANNELS)866#error Invalid LAN743X_USED_RX_CHANNELS867#endif868#if (LAN743X_USED_TX_CHANNELS > LAN743X_MAX_TX_CHANNELS)869#error Invalid LAN743X_USED_TX_CHANNELS870#endif871#if (PCI11X1X_USED_TX_CHANNELS > PCI11X1X_MAX_TX_CHANNELS)872#error Invalid PCI11X1X_USED_TX_CHANNELS873#endif874 875/* PCI */876/* SMSC acquired EFAR late 1990's, MCHP acquired SMSC 2012 */877#define PCI_VENDOR_ID_SMSC PCI_VENDOR_ID_EFAR878#define PCI_DEVICE_ID_SMSC_LAN7430 (0x7430)879#define PCI_DEVICE_ID_SMSC_LAN7431 (0x7431)880#define PCI_DEVICE_ID_SMSC_A011 (0xA011)881#define PCI_DEVICE_ID_SMSC_A041 (0xA041)882 883#define PCI_CONFIG_LENGTH (0x1000)884 885/* CSR */886#define CSR_LENGTH (0x2000)887 888#define LAN743X_CSR_FLAG_IS_A0 BIT(0)889#define LAN743X_CSR_FLAG_IS_B0 BIT(1)890#define LAN743X_CSR_FLAG_SUPPORTS_INTR_AUTO_SET_CLR BIT(8)891 892struct lan743x_csr {893 u32 flags;894 u8 __iomem *csr_address;895 u32 id_rev;896 u32 fpga_rev;897};898 899/* INTERRUPTS */900typedef void(*lan743x_vector_handler)(void *context, u32 int_sts, u32 flags);901 902#define LAN743X_VECTOR_FLAG_IRQ_SHARED BIT(0)903#define LAN743X_VECTOR_FLAG_SOURCE_STATUS_READ BIT(1)904#define LAN743X_VECTOR_FLAG_SOURCE_STATUS_R2C BIT(2)905#define LAN743X_VECTOR_FLAG_SOURCE_STATUS_W2C BIT(3)906#define LAN743X_VECTOR_FLAG_SOURCE_ENABLE_CHECK BIT(4)907#define LAN743X_VECTOR_FLAG_SOURCE_ENABLE_CLEAR BIT(5)908#define LAN743X_VECTOR_FLAG_SOURCE_ENABLE_R2C BIT(6)909#define LAN743X_VECTOR_FLAG_MASTER_ENABLE_CLEAR BIT(7)910#define LAN743X_VECTOR_FLAG_MASTER_ENABLE_SET BIT(8)911#define LAN743X_VECTOR_FLAG_VECTOR_ENABLE_ISR_CLEAR BIT(9)912#define LAN743X_VECTOR_FLAG_VECTOR_ENABLE_ISR_SET BIT(10)913#define LAN743X_VECTOR_FLAG_VECTOR_ENABLE_AUTO_CLEAR BIT(11)914#define LAN743X_VECTOR_FLAG_VECTOR_ENABLE_AUTO_SET BIT(12)915#define LAN743X_VECTOR_FLAG_SOURCE_ENABLE_AUTO_CLEAR BIT(13)916#define LAN743X_VECTOR_FLAG_SOURCE_ENABLE_AUTO_SET BIT(14)917#define LAN743X_VECTOR_FLAG_SOURCE_STATUS_AUTO_CLEAR BIT(15)918 919struct lan743x_vector {920 int irq;921 u32 flags;922 struct lan743x_adapter *adapter;923 int vector_index;924 u32 int_mask;925 lan743x_vector_handler handler;926 void *context;927};928 929#define LAN743X_MAX_VECTOR_COUNT (8)930#define PCI11X1X_MAX_VECTOR_COUNT (16)931 932struct lan743x_intr {933 int flags;934 935 unsigned int irq;936 937 struct lan743x_vector vector_list[PCI11X1X_MAX_VECTOR_COUNT];938 int number_of_vectors;939 bool using_vectors;940 941 bool software_isr_flag;942 wait_queue_head_t software_isr_wq;943};944 945#define LAN743X_MAX_FRAME_SIZE (9 * 1024)946 947/* PHY */948struct lan743x_phy {949 bool fc_autoneg;950 u8 fc_request_control;951};952 953/* TX */954struct lan743x_tx_descriptor;955struct lan743x_tx_buffer_info;956 957#define GPIO_QUEUE_STARTED (0)958#define GPIO_TX_FUNCTION (1)959#define GPIO_TX_COMPLETION (2)960#define GPIO_TX_FRAGMENT (3)961 962#define TX_FRAME_FLAG_IN_PROGRESS BIT(0)963 964#define TX_TS_FLAG_TIMESTAMPING_ENABLED BIT(0)965#define TX_TS_FLAG_ONE_STEP_SYNC BIT(1)966 967struct lan743x_tx {968 struct lan743x_adapter *adapter;969 u32 ts_flags;970 u32 vector_flags;971 int channel_number;972 973 int ring_size;974 size_t ring_allocation_size;975 struct lan743x_tx_descriptor *ring_cpu_ptr;976 dma_addr_t ring_dma_ptr;977 /* ring_lock: used to prevent concurrent access to tx ring */978 spinlock_t ring_lock;979 u32 frame_flags;980 u32 frame_first;981 u32 frame_data0;982 u32 frame_tail;983 984 struct lan743x_tx_buffer_info *buffer_info;985 986 __le32 *head_cpu_ptr;987 dma_addr_t head_dma_ptr;988 int last_head;989 int last_tail;990 991 struct napi_struct napi;992 u32 frame_count;993 u32 rqd_descriptors;994};995 996void lan743x_tx_set_timestamping_mode(struct lan743x_tx *tx,997 bool enable_timestamping,998 bool enable_onestep_sync);999 1000/* RX */1001struct lan743x_rx_descriptor;1002struct lan743x_rx_buffer_info;1003 1004struct lan743x_rx {1005 struct lan743x_adapter *adapter;1006 u32 vector_flags;1007 int channel_number;1008 1009 int ring_size;1010 size_t ring_allocation_size;1011 struct lan743x_rx_descriptor *ring_cpu_ptr;1012 dma_addr_t ring_dma_ptr;1013 1014 struct lan743x_rx_buffer_info *buffer_info;1015 1016 __le32 *head_cpu_ptr;1017 dma_addr_t head_dma_ptr;1018 u32 last_head;1019 u32 last_tail;1020 1021 struct napi_struct napi;1022 1023 u32 frame_count;1024 1025 struct sk_buff *skb_head, *skb_tail;1026};1027 1028int lan743x_rx_set_tstamp_mode(struct lan743x_adapter *adapter,1029 int rx_filter);1030 1031/* SGMII Link Speed Duplex status */1032enum lan743x_sgmii_lsd {1033 POWER_DOWN = 0,1034 LINK_DOWN,1035 ANEG_BUSY,1036 LINK_10HD,1037 LINK_10FD,1038 LINK_100HD,1039 LINK_100FD,1040 LINK_1000_MASTER,1041 LINK_1000_SLAVE,1042 LINK_2500_MASTER,1043 LINK_2500_SLAVE1044};1045 1046#define MAC_SUPPORTED_WAKES (WAKE_BCAST | WAKE_UCAST | WAKE_MCAST | \1047 WAKE_MAGIC | WAKE_ARP)1048struct lan743x_adapter {1049 struct net_device *netdev;1050 struct mii_bus *mdiobus;1051 int msg_enable;1052#ifdef CONFIG_PM1053 u32 wolopts;1054 u8 sopass[SOPASS_MAX];1055 u32 phy_wolopts;1056 u32 phy_wol_supported;1057#endif1058 struct pci_dev *pdev;1059 struct lan743x_csr csr;1060 struct lan743x_intr intr;1061 1062 struct lan743x_gpio gpio;1063 struct lan743x_ptp ptp;1064 1065 u8 mac_address[ETH_ALEN];1066 1067 struct lan743x_phy phy;1068 struct lan743x_tx tx[PCI11X1X_USED_TX_CHANNELS];1069 struct lan743x_rx rx[LAN743X_USED_RX_CHANNELS];1070 bool is_pci11x1x;1071 bool is_sgmii_en;1072 /* protect ethernet syslock */1073 spinlock_t eth_syslock_spinlock;1074 bool eth_syslock_en;1075 u32 eth_syslock_acquire_cnt;1076 struct mutex sgmii_rw_lock;1077 /* SGMII Link Speed & Duplex status */1078 enum lan743x_sgmii_lsd sgmii_lsd;1079 u8 max_tx_channels;1080 u8 used_tx_channels;1081 u8 max_vector_count;1082 1083#define LAN743X_ADAPTER_FLAG_OTP BIT(0)1084 u32 flags;1085 u32 hw_cfg;1086 phy_interface_t phy_interface;1087 struct phylink *phylink;1088 struct phylink_config phylink_config;1089};1090 1091#define LAN743X_COMPONENT_FLAG_RX(channel) BIT(20 + (channel))1092 1093#define INTR_FLAG_IRQ_REQUESTED(vector_index) BIT(0 + vector_index)1094#define INTR_FLAG_MSI_ENABLED BIT(8)1095#define INTR_FLAG_MSIX_ENABLED BIT(9)1096 1097#define MAC_MII_READ 11098#define MAC_MII_WRITE 01099 1100#define PHY_FLAG_OPENED BIT(0)1101#define PHY_FLAG_ATTACHED BIT(1)1102 1103#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT1104#define DMA_ADDR_HIGH32(dma_addr) ((u32)(((dma_addr) >> 32) & 0xFFFFFFFF))1105#else1106#define DMA_ADDR_HIGH32(dma_addr) ((u32)(0))1107#endif1108#define DMA_ADDR_LOW32(dma_addr) ((u32)((dma_addr) & 0xFFFFFFFF))1109#define DMA_DESCRIPTOR_SPACING_16 (16)1110#define DMA_DESCRIPTOR_SPACING_32 (32)1111#define DMA_DESCRIPTOR_SPACING_64 (64)1112#define DMA_DESCRIPTOR_SPACING_128 (128)1113#define DEFAULT_DMA_DESCRIPTOR_SPACING (DMA_DESCRIPTOR_SPACING_16)1114 1115#define DMAC_CHANNEL_STATE_SET(start_bit, stop_bit) \1116 (((start_bit) ? 2 : 0) | ((stop_bit) ? 1 : 0))1117#define DMAC_CHANNEL_STATE_INITIAL DMAC_CHANNEL_STATE_SET(0, 0)1118#define DMAC_CHANNEL_STATE_STARTED DMAC_CHANNEL_STATE_SET(1, 0)1119#define DMAC_CHANNEL_STATE_STOP_PENDING DMAC_CHANNEL_STATE_SET(1, 1)1120#define DMAC_CHANNEL_STATE_STOPPED DMAC_CHANNEL_STATE_SET(0, 1)1121 1122/* TX Descriptor bits */1123#define TX_DESC_DATA0_DTYPE_MASK_ (0xC0000000)1124#define TX_DESC_DATA0_DTYPE_DATA_ (0x00000000)1125#define TX_DESC_DATA0_DTYPE_EXT_ (0x40000000)1126#define TX_DESC_DATA0_FS_ (0x20000000)1127#define TX_DESC_DATA0_LS_ (0x10000000)1128#define TX_DESC_DATA0_EXT_ (0x08000000)1129#define TX_DESC_DATA0_IOC_ (0x04000000)1130#define TX_DESC_DATA0_ICE_ (0x00400000)1131#define TX_DESC_DATA0_IPE_ (0x00200000)1132#define TX_DESC_DATA0_TPE_ (0x00100000)1133#define TX_DESC_DATA0_FCS_ (0x00020000)1134#define TX_DESC_DATA0_TSE_ (0x00010000)1135#define TX_DESC_DATA0_BUF_LENGTH_MASK_ (0x0000FFFF)1136#define TX_DESC_DATA0_EXT_LSO_ (0x00200000)1137#define TX_DESC_DATA0_EXT_PAY_LENGTH_MASK_ (0x000FFFFF)1138#define TX_DESC_DATA3_FRAME_LENGTH_MSS_MASK_ (0x3FFF0000)1139 1140struct lan743x_tx_descriptor {1141 __le32 data0;1142 __le32 data1;1143 __le32 data2;1144 __le32 data3;1145} __aligned(DEFAULT_DMA_DESCRIPTOR_SPACING);1146 1147#define TX_BUFFER_INFO_FLAG_ACTIVE BIT(0)1148#define TX_BUFFER_INFO_FLAG_TIMESTAMP_REQUESTED BIT(1)1149#define TX_BUFFER_INFO_FLAG_IGNORE_SYNC BIT(2)1150#define TX_BUFFER_INFO_FLAG_SKB_FRAGMENT BIT(3)1151struct lan743x_tx_buffer_info {1152 int flags;1153 struct sk_buff *skb;1154 dma_addr_t dma_ptr;1155 unsigned int buffer_length;1156};1157 1158#define LAN743X_TX_RING_SIZE (128)1159 1160/* OWN bit is set. ie, Descs are owned by RX DMAC */1161#define RX_DESC_DATA0_OWN_ (0x00008000)1162/* OWN bit is clear. ie, Descs are owned by host */1163#define RX_DESC_DATA0_FS_ (0x80000000)1164#define RX_DESC_DATA0_LS_ (0x40000000)1165#define RX_DESC_DATA0_FRAME_LENGTH_MASK_ (0x3FFF0000)1166#define RX_DESC_DATA0_FRAME_LENGTH_GET_(data0) \1167 (((data0) & RX_DESC_DATA0_FRAME_LENGTH_MASK_) >> 16)1168#define RX_DESC_DATA0_EXT_ (0x00004000)1169#define RX_DESC_DATA0_BUF_LENGTH_MASK_ (0x00003FFF)1170#define RX_DESC_DATA1_STATUS_ICE_ (0x00020000)1171#define RX_DESC_DATA1_STATUS_TCE_ (0x00010000)1172#define RX_DESC_DATA1_STATUS_ICSM_ (0x00000001)1173#define RX_DESC_DATA2_TS_NS_MASK_ (0x3FFFFFFF)1174 1175#if ((NET_IP_ALIGN != 0) && (NET_IP_ALIGN != 2))1176#error NET_IP_ALIGN must be 0 or 21177#endif1178 1179#define RX_HEAD_PADDING NET_IP_ALIGN1180 1181struct lan743x_rx_descriptor {1182 __le32 data0;1183 __le32 data1;1184 __le32 data2;1185 __le32 data3;1186} __aligned(DEFAULT_DMA_DESCRIPTOR_SPACING);1187 1188#define RX_BUFFER_INFO_FLAG_ACTIVE BIT(0)1189struct lan743x_rx_buffer_info {1190 int flags;1191 struct sk_buff *skb;1192 1193 dma_addr_t dma_ptr;1194 unsigned int buffer_length;1195};1196 1197#define LAN743X_RX_RING_SIZE (128)1198 1199#define RX_PROCESS_RESULT_NOTHING_TO_DO (0)1200#define RX_PROCESS_RESULT_BUFFER_RECEIVED (1)1201 1202u32 lan743x_csr_read(struct lan743x_adapter *adapter, int offset);1203void lan743x_csr_write(struct lan743x_adapter *adapter, int offset, u32 data);1204int lan743x_hs_syslock_acquire(struct lan743x_adapter *adapter, u16 timeout);1205void lan743x_hs_syslock_release(struct lan743x_adapter *adapter);1206void lan743x_mac_flow_ctrl_set_enables(struct lan743x_adapter *adapter,1207 bool tx_enable, bool rx_enable);1208int lan743x_sgmii_read(struct lan743x_adapter *adapter, u8 mmd, u16 addr);1209void lan743x_mac_eee_enable(struct lan743x_adapter *adapter, bool enable);1210 1211#endif /* _LAN743X_H */1212