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1// SPDX-License-Identifier: (GPL-2.0 OR MIT)2 3#include <linux/types.h>4#include <linux/kernel.h>5 6#include "lan966x_vcap_ag_api.h"7 8/* keyfields */9static const struct vcap_field is1_normal_keyfield[] = {10 [VCAP_KF_TYPE] = {11 .type = VCAP_FIELD_BIT,12 .offset = 0,13 .width = 1,14 },15 [VCAP_KF_LOOKUP_INDEX] = {16 .type = VCAP_FIELD_U32,17 .offset = 1,18 .width = 2,19 },20 [VCAP_KF_IF_IGR_PORT_MASK] = {21 .type = VCAP_FIELD_U32,22 .offset = 3,23 .width = 9,24 },25 [VCAP_KF_L2_MC_IS] = {26 .type = VCAP_FIELD_BIT,27 .offset = 12,28 .width = 1,29 },30 [VCAP_KF_L2_BC_IS] = {31 .type = VCAP_FIELD_BIT,32 .offset = 13,33 .width = 1,34 },35 [VCAP_KF_IP_MC_IS] = {36 .type = VCAP_FIELD_BIT,37 .offset = 14,38 .width = 1,39 },40 [VCAP_KF_8021CB_R_TAGGED_IS] = {41 .type = VCAP_FIELD_BIT,42 .offset = 15,43 .width = 1,44 },45 [VCAP_KF_8021Q_VLAN_TAGGED_IS] = {46 .type = VCAP_FIELD_BIT,47 .offset = 16,48 .width = 1,49 },50 [VCAP_KF_8021Q_VLAN_DBL_TAGGED_IS] = {51 .type = VCAP_FIELD_BIT,52 .offset = 17,53 .width = 1,54 },55 [VCAP_KF_8021Q_TPID0] = {56 .type = VCAP_FIELD_BIT,57 .offset = 18,58 .width = 1,59 },60 [VCAP_KF_8021Q_VID0] = {61 .type = VCAP_FIELD_U32,62 .offset = 19,63 .width = 12,64 },65 [VCAP_KF_8021Q_DEI0] = {66 .type = VCAP_FIELD_BIT,67 .offset = 31,68 .width = 1,69 },70 [VCAP_KF_8021Q_PCP0] = {71 .type = VCAP_FIELD_U32,72 .offset = 32,73 .width = 3,74 },75 [VCAP_KF_L2_SMAC] = {76 .type = VCAP_FIELD_U48,77 .offset = 35,78 .width = 48,79 },80 [VCAP_KF_ETYPE_LEN_IS] = {81 .type = VCAP_FIELD_BIT,82 .offset = 83,83 .width = 1,84 },85 [VCAP_KF_ETYPE] = {86 .type = VCAP_FIELD_U32,87 .offset = 84,88 .width = 16,89 },90 [VCAP_KF_IP_SNAP_IS] = {91 .type = VCAP_FIELD_BIT,92 .offset = 100,93 .width = 1,94 },95 [VCAP_KF_IP4_IS] = {96 .type = VCAP_FIELD_BIT,97 .offset = 101,98 .width = 1,99 },100 [VCAP_KF_L3_FRAGMENT] = {101 .type = VCAP_FIELD_BIT,102 .offset = 102,103 .width = 1,104 },105 [VCAP_KF_L3_FRAG_OFS_GT0] = {106 .type = VCAP_FIELD_BIT,107 .offset = 103,108 .width = 1,109 },110 [VCAP_KF_L3_OPTIONS_IS] = {111 .type = VCAP_FIELD_BIT,112 .offset = 104,113 .width = 1,114 },115 [VCAP_KF_L3_DSCP] = {116 .type = VCAP_FIELD_U32,117 .offset = 105,118 .width = 6,119 },120 [VCAP_KF_L3_IP4_SIP] = {121 .type = VCAP_FIELD_U32,122 .offset = 111,123 .width = 32,124 },125 [VCAP_KF_TCP_UDP_IS] = {126 .type = VCAP_FIELD_BIT,127 .offset = 143,128 .width = 1,129 },130 [VCAP_KF_TCP_IS] = {131 .type = VCAP_FIELD_BIT,132 .offset = 144,133 .width = 1,134 },135 [VCAP_KF_L4_SPORT] = {136 .type = VCAP_FIELD_U32,137 .offset = 145,138 .width = 16,139 },140 [VCAP_KF_L4_RNG] = {141 .type = VCAP_FIELD_U32,142 .offset = 161,143 .width = 8,144 },145};146 147static const struct vcap_field is1_5tuple_ip4_keyfield[] = {148 [VCAP_KF_TYPE] = {149 .type = VCAP_FIELD_BIT,150 .offset = 0,151 .width = 1,152 },153 [VCAP_KF_LOOKUP_INDEX] = {154 .type = VCAP_FIELD_U32,155 .offset = 1,156 .width = 2,157 },158 [VCAP_KF_IF_IGR_PORT_MASK] = {159 .type = VCAP_FIELD_U32,160 .offset = 3,161 .width = 9,162 },163 [VCAP_KF_L2_MC_IS] = {164 .type = VCAP_FIELD_BIT,165 .offset = 12,166 .width = 1,167 },168 [VCAP_KF_L2_BC_IS] = {169 .type = VCAP_FIELD_BIT,170 .offset = 13,171 .width = 1,172 },173 [VCAP_KF_IP_MC_IS] = {174 .type = VCAP_FIELD_BIT,175 .offset = 14,176 .width = 1,177 },178 [VCAP_KF_8021CB_R_TAGGED_IS] = {179 .type = VCAP_FIELD_BIT,180 .offset = 15,181 .width = 1,182 },183 [VCAP_KF_8021Q_VLAN_TAGGED_IS] = {184 .type = VCAP_FIELD_BIT,185 .offset = 16,186 .width = 1,187 },188 [VCAP_KF_8021Q_VLAN_DBL_TAGGED_IS] = {189 .type = VCAP_FIELD_BIT,190 .offset = 17,191 .width = 1,192 },193 [VCAP_KF_8021Q_TPID0] = {194 .type = VCAP_FIELD_BIT,195 .offset = 18,196 .width = 1,197 },198 [VCAP_KF_8021Q_VID0] = {199 .type = VCAP_FIELD_U32,200 .offset = 19,201 .width = 12,202 },203 [VCAP_KF_8021Q_DEI0] = {204 .type = VCAP_FIELD_BIT,205 .offset = 31,206 .width = 1,207 },208 [VCAP_KF_8021Q_PCP0] = {209 .type = VCAP_FIELD_U32,210 .offset = 32,211 .width = 3,212 },213 [VCAP_KF_8021Q_TPID1] = {214 .type = VCAP_FIELD_BIT,215 .offset = 35,216 .width = 1,217 },218 [VCAP_KF_8021Q_VID1] = {219 .type = VCAP_FIELD_U32,220 .offset = 36,221 .width = 12,222 },223 [VCAP_KF_8021Q_DEI1] = {224 .type = VCAP_FIELD_BIT,225 .offset = 48,226 .width = 1,227 },228 [VCAP_KF_8021Q_PCP1] = {229 .type = VCAP_FIELD_U32,230 .offset = 49,231 .width = 3,232 },233 [VCAP_KF_IP4_IS] = {234 .type = VCAP_FIELD_BIT,235 .offset = 52,236 .width = 1,237 },238 [VCAP_KF_L3_FRAGMENT] = {239 .type = VCAP_FIELD_BIT,240 .offset = 53,241 .width = 1,242 },243 [VCAP_KF_L3_FRAG_OFS_GT0] = {244 .type = VCAP_FIELD_BIT,245 .offset = 54,246 .width = 1,247 },248 [VCAP_KF_L3_OPTIONS_IS] = {249 .type = VCAP_FIELD_BIT,250 .offset = 55,251 .width = 1,252 },253 [VCAP_KF_L3_DSCP] = {254 .type = VCAP_FIELD_U32,255 .offset = 56,256 .width = 6,257 },258 [VCAP_KF_L3_IP4_DIP] = {259 .type = VCAP_FIELD_U32,260 .offset = 62,261 .width = 32,262 },263 [VCAP_KF_L3_IP4_SIP] = {264 .type = VCAP_FIELD_U32,265 .offset = 94,266 .width = 32,267 },268 [VCAP_KF_L3_IP_PROTO] = {269 .type = VCAP_FIELD_U32,270 .offset = 126,271 .width = 8,272 },273 [VCAP_KF_TCP_UDP_IS] = {274 .type = VCAP_FIELD_BIT,275 .offset = 134,276 .width = 1,277 },278 [VCAP_KF_TCP_IS] = {279 .type = VCAP_FIELD_BIT,280 .offset = 135,281 .width = 1,282 },283 [VCAP_KF_L4_RNG] = {284 .type = VCAP_FIELD_U32,285 .offset = 136,286 .width = 8,287 },288 [VCAP_KF_IP_PAYLOAD_5TUPLE] = {289 .type = VCAP_FIELD_U32,290 .offset = 144,291 .width = 32,292 },293};294 295static const struct vcap_field is1_normal_ip6_keyfield[] = {296 [VCAP_KF_TYPE] = {297 .type = VCAP_FIELD_U32,298 .offset = 0,299 .width = 2,300 },301 [VCAP_KF_LOOKUP_INDEX] = {302 .type = VCAP_FIELD_U32,303 .offset = 2,304 .width = 2,305 },306 [VCAP_KF_IF_IGR_PORT_MASK] = {307 .type = VCAP_FIELD_U32,308 .offset = 4,309 .width = 9,310 },311 [VCAP_KF_L2_MC_IS] = {312 .type = VCAP_FIELD_BIT,313 .offset = 13,314 .width = 1,315 },316 [VCAP_KF_L2_BC_IS] = {317 .type = VCAP_FIELD_BIT,318 .offset = 14,319 .width = 1,320 },321 [VCAP_KF_IP_MC_IS] = {322 .type = VCAP_FIELD_BIT,323 .offset = 15,324 .width = 1,325 },326 [VCAP_KF_8021CB_R_TAGGED_IS] = {327 .type = VCAP_FIELD_BIT,328 .offset = 16,329 .width = 1,330 },331 [VCAP_KF_8021Q_VLAN_TAGGED_IS] = {332 .type = VCAP_FIELD_BIT,333 .offset = 17,334 .width = 1,335 },336 [VCAP_KF_8021Q_VLAN_DBL_TAGGED_IS] = {337 .type = VCAP_FIELD_BIT,338 .offset = 18,339 .width = 1,340 },341 [VCAP_KF_8021Q_TPID0] = {342 .type = VCAP_FIELD_BIT,343 .offset = 19,344 .width = 1,345 },346 [VCAP_KF_8021Q_VID0] = {347 .type = VCAP_FIELD_U32,348 .offset = 20,349 .width = 12,350 },351 [VCAP_KF_8021Q_DEI0] = {352 .type = VCAP_FIELD_BIT,353 .offset = 32,354 .width = 1,355 },356 [VCAP_KF_8021Q_PCP0] = {357 .type = VCAP_FIELD_U32,358 .offset = 33,359 .width = 3,360 },361 [VCAP_KF_8021Q_TPID1] = {362 .type = VCAP_FIELD_BIT,363 .offset = 36,364 .width = 1,365 },366 [VCAP_KF_8021Q_VID1] = {367 .type = VCAP_FIELD_U32,368 .offset = 37,369 .width = 12,370 },371 [VCAP_KF_8021Q_DEI1] = {372 .type = VCAP_FIELD_BIT,373 .offset = 49,374 .width = 1,375 },376 [VCAP_KF_8021Q_PCP1] = {377 .type = VCAP_FIELD_U32,378 .offset = 50,379 .width = 3,380 },381 [VCAP_KF_L2_SMAC] = {382 .type = VCAP_FIELD_U48,383 .offset = 53,384 .width = 48,385 },386 [VCAP_KF_L3_DSCP] = {387 .type = VCAP_FIELD_U32,388 .offset = 101,389 .width = 6,390 },391 [VCAP_KF_L3_IP6_SIP] = {392 .type = VCAP_FIELD_U128,393 .offset = 107,394 .width = 128,395 },396 [VCAP_KF_L3_IP_PROTO] = {397 .type = VCAP_FIELD_U32,398 .offset = 235,399 .width = 8,400 },401 [VCAP_KF_TCP_UDP_IS] = {402 .type = VCAP_FIELD_BIT,403 .offset = 243,404 .width = 1,405 },406 [VCAP_KF_L4_RNG] = {407 .type = VCAP_FIELD_U32,408 .offset = 244,409 .width = 8,410 },411 [VCAP_KF_IP_PAYLOAD_S1_IP6] = {412 .type = VCAP_FIELD_U112,413 .offset = 252,414 .width = 112,415 },416};417 418static const struct vcap_field is1_7tuple_keyfield[] = {419 [VCAP_KF_TYPE] = {420 .type = VCAP_FIELD_U32,421 .offset = 0,422 .width = 2,423 },424 [VCAP_KF_LOOKUP_INDEX] = {425 .type = VCAP_FIELD_U32,426 .offset = 2,427 .width = 2,428 },429 [VCAP_KF_IF_IGR_PORT_MASK] = {430 .type = VCAP_FIELD_U32,431 .offset = 4,432 .width = 9,433 },434 [VCAP_KF_L2_MC_IS] = {435 .type = VCAP_FIELD_BIT,436 .offset = 13,437 .width = 1,438 },439 [VCAP_KF_L2_BC_IS] = {440 .type = VCAP_FIELD_BIT,441 .offset = 14,442 .width = 1,443 },444 [VCAP_KF_IP_MC_IS] = {445 .type = VCAP_FIELD_BIT,446 .offset = 15,447 .width = 1,448 },449 [VCAP_KF_8021CB_R_TAGGED_IS] = {450 .type = VCAP_FIELD_BIT,451 .offset = 16,452 .width = 1,453 },454 [VCAP_KF_8021Q_VLAN_TAGGED_IS] = {455 .type = VCAP_FIELD_BIT,456 .offset = 17,457 .width = 1,458 },459 [VCAP_KF_8021Q_VLAN_DBL_TAGGED_IS] = {460 .type = VCAP_FIELD_BIT,461 .offset = 18,462 .width = 1,463 },464 [VCAP_KF_8021Q_TPID0] = {465 .type = VCAP_FIELD_BIT,466 .offset = 19,467 .width = 1,468 },469 [VCAP_KF_8021Q_VID0] = {470 .type = VCAP_FIELD_U32,471 .offset = 20,472 .width = 12,473 },474 [VCAP_KF_8021Q_DEI0] = {475 .type = VCAP_FIELD_BIT,476 .offset = 32,477 .width = 1,478 },479 [VCAP_KF_8021Q_PCP0] = {480 .type = VCAP_FIELD_U32,481 .offset = 33,482 .width = 3,483 },484 [VCAP_KF_8021Q_TPID1] = {485 .type = VCAP_FIELD_BIT,486 .offset = 36,487 .width = 1,488 },489 [VCAP_KF_8021Q_VID1] = {490 .type = VCAP_FIELD_U32,491 .offset = 37,492 .width = 12,493 },494 [VCAP_KF_8021Q_DEI1] = {495 .type = VCAP_FIELD_BIT,496 .offset = 49,497 .width = 1,498 },499 [VCAP_KF_8021Q_PCP1] = {500 .type = VCAP_FIELD_U32,501 .offset = 50,502 .width = 3,503 },504 [VCAP_KF_L2_DMAC] = {505 .type = VCAP_FIELD_U48,506 .offset = 53,507 .width = 48,508 },509 [VCAP_KF_L2_SMAC] = {510 .type = VCAP_FIELD_U48,511 .offset = 101,512 .width = 48,513 },514 [VCAP_KF_ETYPE_LEN_IS] = {515 .type = VCAP_FIELD_BIT,516 .offset = 149,517 .width = 1,518 },519 [VCAP_KF_ETYPE] = {520 .type = VCAP_FIELD_U32,521 .offset = 150,522 .width = 16,523 },524 [VCAP_KF_IP_SNAP_IS] = {525 .type = VCAP_FIELD_BIT,526 .offset = 166,527 .width = 1,528 },529 [VCAP_KF_IP4_IS] = {530 .type = VCAP_FIELD_BIT,531 .offset = 167,532 .width = 1,533 },534 [VCAP_KF_L3_FRAGMENT] = {535 .type = VCAP_FIELD_BIT,536 .offset = 168,537 .width = 1,538 },539 [VCAP_KF_L3_FRAG_OFS_GT0] = {540 .type = VCAP_FIELD_BIT,541 .offset = 169,542 .width = 1,543 },544 [VCAP_KF_L3_OPTIONS_IS] = {545 .type = VCAP_FIELD_BIT,546 .offset = 170,547 .width = 1,548 },549 [VCAP_KF_L3_DSCP] = {550 .type = VCAP_FIELD_U32,551 .offset = 171,552 .width = 6,553 },554 [VCAP_KF_L3_IP6_DIP_MSB] = {555 .type = VCAP_FIELD_U32,556 .offset = 177,557 .width = 16,558 },559 [VCAP_KF_L3_IP6_DIP] = {560 .type = VCAP_FIELD_U64,561 .offset = 193,562 .width = 64,563 },564 [VCAP_KF_L3_IP6_SIP_MSB] = {565 .type = VCAP_FIELD_U32,566 .offset = 257,567 .width = 16,568 },569 [VCAP_KF_L3_IP6_SIP] = {570 .type = VCAP_FIELD_U64,571 .offset = 273,572 .width = 64,573 },574 [VCAP_KF_TCP_UDP_IS] = {575 .type = VCAP_FIELD_BIT,576 .offset = 337,577 .width = 1,578 },579 [VCAP_KF_TCP_IS] = {580 .type = VCAP_FIELD_BIT,581 .offset = 338,582 .width = 1,583 },584 [VCAP_KF_L4_SPORT] = {585 .type = VCAP_FIELD_U32,586 .offset = 339,587 .width = 16,588 },589 [VCAP_KF_L4_RNG] = {590 .type = VCAP_FIELD_U32,591 .offset = 355,592 .width = 8,593 },594};595 596static const struct vcap_field is1_5tuple_ip6_keyfield[] = {597 [VCAP_KF_TYPE] = {598 .type = VCAP_FIELD_U32,599 .offset = 0,600 .width = 2,601 },602 [VCAP_KF_LOOKUP_INDEX] = {603 .type = VCAP_FIELD_U32,604 .offset = 2,605 .width = 2,606 },607 [VCAP_KF_IF_IGR_PORT_MASK] = {608 .type = VCAP_FIELD_U32,609 .offset = 4,610 .width = 9,611 },612 [VCAP_KF_L2_MC_IS] = {613 .type = VCAP_FIELD_BIT,614 .offset = 13,615 .width = 1,616 },617 [VCAP_KF_L2_BC_IS] = {618 .type = VCAP_FIELD_BIT,619 .offset = 14,620 .width = 1,621 },622 [VCAP_KF_IP_MC_IS] = {623 .type = VCAP_FIELD_BIT,624 .offset = 15,625 .width = 1,626 },627 [VCAP_KF_8021CB_R_TAGGED_IS] = {628 .type = VCAP_FIELD_BIT,629 .offset = 16,630 .width = 1,631 },632 [VCAP_KF_8021Q_VLAN_TAGGED_IS] = {633 .type = VCAP_FIELD_BIT,634 .offset = 17,635 .width = 1,636 },637 [VCAP_KF_8021Q_VLAN_DBL_TAGGED_IS] = {638 .type = VCAP_FIELD_BIT,639 .offset = 18,640 .width = 1,641 },642 [VCAP_KF_8021Q_TPID0] = {643 .type = VCAP_FIELD_BIT,644 .offset = 19,645 .width = 1,646 },647 [VCAP_KF_8021Q_VID0] = {648 .type = VCAP_FIELD_U32,649 .offset = 20,650 .width = 12,651 },652 [VCAP_KF_8021Q_DEI0] = {653 .type = VCAP_FIELD_BIT,654 .offset = 32,655 .width = 1,656 },657 [VCAP_KF_8021Q_PCP0] = {658 .type = VCAP_FIELD_U32,659 .offset = 33,660 .width = 3,661 },662 [VCAP_KF_8021Q_TPID1] = {663 .type = VCAP_FIELD_BIT,664 .offset = 36,665 .width = 1,666 },667 [VCAP_KF_8021Q_VID1] = {668 .type = VCAP_FIELD_U32,669 .offset = 37,670 .width = 12,671 },672 [VCAP_KF_8021Q_DEI1] = {673 .type = VCAP_FIELD_BIT,674 .offset = 49,675 .width = 1,676 },677 [VCAP_KF_8021Q_PCP1] = {678 .type = VCAP_FIELD_U32,679 .offset = 50,680 .width = 3,681 },682 [VCAP_KF_L3_DSCP] = {683 .type = VCAP_FIELD_U32,684 .offset = 53,685 .width = 6,686 },687 [VCAP_KF_L3_IP6_DIP] = {688 .type = VCAP_FIELD_U128,689 .offset = 59,690 .width = 128,691 },692 [VCAP_KF_L3_IP6_SIP] = {693 .type = VCAP_FIELD_U128,694 .offset = 187,695 .width = 128,696 },697 [VCAP_KF_L3_IP_PROTO] = {698 .type = VCAP_FIELD_U32,699 .offset = 315,700 .width = 8,701 },702 [VCAP_KF_TCP_UDP_IS] = {703 .type = VCAP_FIELD_BIT,704 .offset = 323,705 .width = 1,706 },707 [VCAP_KF_L4_RNG] = {708 .type = VCAP_FIELD_U32,709 .offset = 324,710 .width = 8,711 },712 [VCAP_KF_IP_PAYLOAD_5TUPLE] = {713 .type = VCAP_FIELD_U32,714 .offset = 332,715 .width = 32,716 },717};718 719static const struct vcap_field is1_dbl_vid_keyfield[] = {720 [VCAP_KF_TYPE] = {721 .type = VCAP_FIELD_U32,722 .offset = 0,723 .width = 2,724 },725 [VCAP_KF_LOOKUP_INDEX] = {726 .type = VCAP_FIELD_U32,727 .offset = 2,728 .width = 2,729 },730 [VCAP_KF_IF_IGR_PORT_MASK] = {731 .type = VCAP_FIELD_U32,732 .offset = 4,733 .width = 9,734 },735 [VCAP_KF_L2_MC_IS] = {736 .type = VCAP_FIELD_BIT,737 .offset = 13,738 .width = 1,739 },740 [VCAP_KF_L2_BC_IS] = {741 .type = VCAP_FIELD_BIT,742 .offset = 14,743 .width = 1,744 },745 [VCAP_KF_IP_MC_IS] = {746 .type = VCAP_FIELD_BIT,747 .offset = 15,748 .width = 1,749 },750 [VCAP_KF_8021CB_R_TAGGED_IS] = {751 .type = VCAP_FIELD_BIT,752 .offset = 16,753 .width = 1,754 },755 [VCAP_KF_8021Q_VLAN_TAGGED_IS] = {756 .type = VCAP_FIELD_BIT,757 .offset = 17,758 .width = 1,759 },760 [VCAP_KF_8021Q_VLAN_DBL_TAGGED_IS] = {761 .type = VCAP_FIELD_BIT,762 .offset = 18,763 .width = 1,764 },765 [VCAP_KF_8021Q_TPID0] = {766 .type = VCAP_FIELD_BIT,767 .offset = 19,768 .width = 1,769 },770 [VCAP_KF_8021Q_VID0] = {771 .type = VCAP_FIELD_U32,772 .offset = 20,773 .width = 12,774 },775 [VCAP_KF_8021Q_DEI0] = {776 .type = VCAP_FIELD_BIT,777 .offset = 32,778 .width = 1,779 },780 [VCAP_KF_8021Q_PCP0] = {781 .type = VCAP_FIELD_U32,782 .offset = 33,783 .width = 3,784 },785 [VCAP_KF_8021Q_TPID1] = {786 .type = VCAP_FIELD_BIT,787 .offset = 36,788 .width = 1,789 },790 [VCAP_KF_8021Q_VID1] = {791 .type = VCAP_FIELD_U32,792 .offset = 37,793 .width = 12,794 },795 [VCAP_KF_8021Q_DEI1] = {796 .type = VCAP_FIELD_BIT,797 .offset = 49,798 .width = 1,799 },800 [VCAP_KF_8021Q_PCP1] = {801 .type = VCAP_FIELD_U32,802 .offset = 50,803 .width = 3,804 },805 [VCAP_KF_ETYPE_LEN_IS] = {806 .type = VCAP_FIELD_BIT,807 .offset = 53,808 .width = 1,809 },810 [VCAP_KF_ETYPE] = {811 .type = VCAP_FIELD_U32,812 .offset = 54,813 .width = 16,814 },815 [VCAP_KF_IP_SNAP_IS] = {816 .type = VCAP_FIELD_BIT,817 .offset = 70,818 .width = 1,819 },820 [VCAP_KF_IP4_IS] = {821 .type = VCAP_FIELD_BIT,822 .offset = 71,823 .width = 1,824 },825 [VCAP_KF_L3_FRAGMENT] = {826 .type = VCAP_FIELD_BIT,827 .offset = 72,828 .width = 1,829 },830 [VCAP_KF_L3_FRAG_OFS_GT0] = {831 .type = VCAP_FIELD_BIT,832 .offset = 73,833 .width = 1,834 },835 [VCAP_KF_L3_OPTIONS_IS] = {836 .type = VCAP_FIELD_BIT,837 .offset = 74,838 .width = 1,839 },840 [VCAP_KF_L3_DSCP] = {841 .type = VCAP_FIELD_U32,842 .offset = 75,843 .width = 6,844 },845 [VCAP_KF_TCP_UDP_IS] = {846 .type = VCAP_FIELD_BIT,847 .offset = 81,848 .width = 1,849 },850 [VCAP_KF_TCP_IS] = {851 .type = VCAP_FIELD_BIT,852 .offset = 82,853 .width = 1,854 },855};856 857static const struct vcap_field is1_rt_keyfield[] = {858 [VCAP_KF_TYPE] = {859 .type = VCAP_FIELD_U32,860 .offset = 0,861 .width = 2,862 },863 [VCAP_KF_LOOKUP_FIRST_IS] = {864 .type = VCAP_FIELD_BIT,865 .offset = 2,866 .width = 1,867 },868 [VCAP_KF_IF_IGR_PORT] = {869 .type = VCAP_FIELD_U32,870 .offset = 3,871 .width = 3,872 },873 [VCAP_KF_8021CB_R_TAGGED_IS] = {874 .type = VCAP_FIELD_BIT,875 .offset = 6,876 .width = 1,877 },878 [VCAP_KF_8021Q_VLAN_TAGGED_IS] = {879 .type = VCAP_FIELD_BIT,880 .offset = 7,881 .width = 1,882 },883 [VCAP_KF_8021Q_VLAN_DBL_TAGGED_IS] = {884 .type = VCAP_FIELD_BIT,885 .offset = 8,886 .width = 1,887 },888 [VCAP_KF_L2_MAC] = {889 .type = VCAP_FIELD_U48,890 .offset = 9,891 .width = 48,892 },893 [VCAP_KF_RT_VLAN_IDX] = {894 .type = VCAP_FIELD_U32,895 .offset = 57,896 .width = 3,897 },898 [VCAP_KF_RT_TYPE] = {899 .type = VCAP_FIELD_U32,900 .offset = 60,901 .width = 2,902 },903 [VCAP_KF_RT_FRMID] = {904 .type = VCAP_FIELD_U32,905 .offset = 62,906 .width = 32,907 },908};909 910static const struct vcap_field is1_dmac_vid_keyfield[] = {911 [VCAP_KF_TYPE] = {912 .type = VCAP_FIELD_U32,913 .offset = 0,914 .width = 2,915 },916 [VCAP_KF_LOOKUP_INDEX] = {917 .type = VCAP_FIELD_U32,918 .offset = 2,919 .width = 2,920 },921 [VCAP_KF_IF_IGR_PORT_MASK] = {922 .type = VCAP_FIELD_U32,923 .offset = 4,924 .width = 9,925 },926 [VCAP_KF_8021CB_R_TAGGED_IS] = {927 .type = VCAP_FIELD_BIT,928 .offset = 13,929 .width = 1,930 },931 [VCAP_KF_8021Q_VLAN_TAGGED_IS] = {932 .type = VCAP_FIELD_BIT,933 .offset = 14,934 .width = 1,935 },936 [VCAP_KF_8021Q_VLAN_DBL_TAGGED_IS] = {937 .type = VCAP_FIELD_BIT,938 .offset = 15,939 .width = 1,940 },941 [VCAP_KF_8021Q_TPID0] = {942 .type = VCAP_FIELD_BIT,943 .offset = 16,944 .width = 1,945 },946 [VCAP_KF_8021Q_VID0] = {947 .type = VCAP_FIELD_U32,948 .offset = 17,949 .width = 12,950 },951 [VCAP_KF_8021Q_DEI0] = {952 .type = VCAP_FIELD_BIT,953 .offset = 29,954 .width = 1,955 },956 [VCAP_KF_8021Q_PCP0] = {957 .type = VCAP_FIELD_U32,958 .offset = 30,959 .width = 3,960 },961 [VCAP_KF_L2_DMAC] = {962 .type = VCAP_FIELD_U48,963 .offset = 33,964 .width = 48,965 },966};967 968static const struct vcap_field is2_mac_etype_keyfield[] = {969 [VCAP_KF_TYPE] = {970 .type = VCAP_FIELD_U32,971 .offset = 0,972 .width = 4,973 },974 [VCAP_KF_LOOKUP_FIRST_IS] = {975 .type = VCAP_FIELD_BIT,976 .offset = 4,977 .width = 1,978 },979 [VCAP_KF_LOOKUP_PAG] = {980 .type = VCAP_FIELD_U32,981 .offset = 5,982 .width = 8,983 },984 [VCAP_KF_IF_IGR_PORT_MASK] = {985 .type = VCAP_FIELD_U32,986 .offset = 13,987 .width = 9,988 },989 [VCAP_KF_ISDX_GT0_IS] = {990 .type = VCAP_FIELD_BIT,991 .offset = 22,992 .width = 1,993 },994 [VCAP_KF_HOST_MATCH] = {995 .type = VCAP_FIELD_BIT,996 .offset = 23,997 .width = 1,998 },999 [VCAP_KF_L2_MC_IS] = {1000 .type = VCAP_FIELD_BIT,1001 .offset = 24,1002 .width = 1,1003 },1004 [VCAP_KF_L2_BC_IS] = {1005 .type = VCAP_FIELD_BIT,1006 .offset = 25,1007 .width = 1,1008 },1009 [VCAP_KF_8021Q_VLAN_TAGGED_IS] = {1010 .type = VCAP_FIELD_BIT,1011 .offset = 26,1012 .width = 1,1013 },1014 [VCAP_KF_8021Q_VID_CLS] = {1015 .type = VCAP_FIELD_U32,1016 .offset = 27,1017 .width = 12,1018 },1019 [VCAP_KF_8021Q_DEI_CLS] = {1020 .type = VCAP_FIELD_BIT,1021 .offset = 39,1022 .width = 1,1023 },1024 [VCAP_KF_8021Q_PCP_CLS] = {1025 .type = VCAP_FIELD_U32,1026 .offset = 40,1027 .width = 3,1028 },1029 [VCAP_KF_L2_DMAC] = {1030 .type = VCAP_FIELD_U48,1031 .offset = 43,1032 .width = 48,1033 },1034 [VCAP_KF_L2_SMAC] = {1035 .type = VCAP_FIELD_U48,1036 .offset = 91,1037 .width = 48,1038 },1039 [VCAP_KF_ETYPE] = {1040 .type = VCAP_FIELD_U32,1041 .offset = 139,1042 .width = 16,1043 },1044 [VCAP_KF_L2_FRM_TYPE] = {1045 .type = VCAP_FIELD_U32,1046 .offset = 155,1047 .width = 4,1048 },1049 [VCAP_KF_L2_PAYLOAD0] = {1050 .type = VCAP_FIELD_U32,1051 .offset = 159,1052 .width = 16,1053 },1054 [VCAP_KF_L2_PAYLOAD1] = {1055 .type = VCAP_FIELD_U32,1056 .offset = 175,1057 .width = 8,1058 },1059 [VCAP_KF_L2_PAYLOAD2] = {1060 .type = VCAP_FIELD_U32,1061 .offset = 183,1062 .width = 3,1063 },1064};1065 1066static const struct vcap_field is2_mac_llc_keyfield[] = {1067 [VCAP_KF_TYPE] = {1068 .type = VCAP_FIELD_U32,1069 .offset = 0,1070 .width = 4,1071 },1072 [VCAP_KF_LOOKUP_FIRST_IS] = {1073 .type = VCAP_FIELD_BIT,1074 .offset = 4,1075 .width = 1,1076 },1077 [VCAP_KF_LOOKUP_PAG] = {1078 .type = VCAP_FIELD_U32,1079 .offset = 5,1080 .width = 8,1081 },1082 [VCAP_KF_IF_IGR_PORT_MASK] = {1083 .type = VCAP_FIELD_U32,1084 .offset = 13,1085 .width = 9,1086 },1087 [VCAP_KF_ISDX_GT0_IS] = {1088 .type = VCAP_FIELD_BIT,1089 .offset = 22,1090 .width = 1,1091 },1092 [VCAP_KF_HOST_MATCH] = {1093 .type = VCAP_FIELD_BIT,1094 .offset = 23,1095 .width = 1,1096 },1097 [VCAP_KF_L2_MC_IS] = {1098 .type = VCAP_FIELD_BIT,1099 .offset = 24,1100 .width = 1,1101 },1102 [VCAP_KF_L2_BC_IS] = {1103 .type = VCAP_FIELD_BIT,1104 .offset = 25,1105 .width = 1,1106 },1107 [VCAP_KF_8021Q_VLAN_TAGGED_IS] = {1108 .type = VCAP_FIELD_BIT,1109 .offset = 26,1110 .width = 1,1111 },1112 [VCAP_KF_8021Q_VID_CLS] = {1113 .type = VCAP_FIELD_U32,1114 .offset = 27,1115 .width = 12,1116 },1117 [VCAP_KF_8021Q_DEI_CLS] = {1118 .type = VCAP_FIELD_BIT,1119 .offset = 39,1120 .width = 1,1121 },1122 [VCAP_KF_8021Q_PCP_CLS] = {1123 .type = VCAP_FIELD_U32,1124 .offset = 40,1125 .width = 3,1126 },1127 [VCAP_KF_L2_DMAC] = {1128 .type = VCAP_FIELD_U48,1129 .offset = 43,1130 .width = 48,1131 },1132 [VCAP_KF_L2_SMAC] = {1133 .type = VCAP_FIELD_U48,1134 .offset = 91,1135 .width = 48,1136 },1137 [VCAP_KF_L2_LLC] = {1138 .type = VCAP_FIELD_U48,1139 .offset = 139,1140 .width = 40,1141 },1142};1143 1144static const struct vcap_field is2_mac_snap_keyfield[] = {1145 [VCAP_KF_TYPE] = {1146 .type = VCAP_FIELD_U32,1147 .offset = 0,1148 .width = 4,1149 },1150 [VCAP_KF_LOOKUP_FIRST_IS] = {1151 .type = VCAP_FIELD_BIT,1152 .offset = 4,1153 .width = 1,1154 },1155 [VCAP_KF_LOOKUP_PAG] = {1156 .type = VCAP_FIELD_U32,1157 .offset = 5,1158 .width = 8,1159 },1160 [VCAP_KF_IF_IGR_PORT_MASK] = {1161 .type = VCAP_FIELD_U32,1162 .offset = 13,1163 .width = 9,1164 },1165 [VCAP_KF_ISDX_GT0_IS] = {1166 .type = VCAP_FIELD_BIT,1167 .offset = 22,1168 .width = 1,1169 },1170 [VCAP_KF_HOST_MATCH] = {1171 .type = VCAP_FIELD_BIT,1172 .offset = 23,1173 .width = 1,1174 },1175 [VCAP_KF_L2_MC_IS] = {1176 .type = VCAP_FIELD_BIT,1177 .offset = 24,1178 .width = 1,1179 },1180 [VCAP_KF_L2_BC_IS] = {1181 .type = VCAP_FIELD_BIT,1182 .offset = 25,1183 .width = 1,1184 },1185 [VCAP_KF_8021Q_VLAN_TAGGED_IS] = {1186 .type = VCAP_FIELD_BIT,1187 .offset = 26,1188 .width = 1,1189 },1190 [VCAP_KF_8021Q_VID_CLS] = {1191 .type = VCAP_FIELD_U32,1192 .offset = 27,1193 .width = 12,1194 },1195 [VCAP_KF_8021Q_DEI_CLS] = {1196 .type = VCAP_FIELD_BIT,1197 .offset = 39,1198 .width = 1,1199 },1200 [VCAP_KF_8021Q_PCP_CLS] = {1201 .type = VCAP_FIELD_U32,1202 .offset = 40,1203 .width = 3,1204 },1205 [VCAP_KF_L2_DMAC] = {1206 .type = VCAP_FIELD_U48,1207 .offset = 43,1208 .width = 48,1209 },1210 [VCAP_KF_L2_SMAC] = {1211 .type = VCAP_FIELD_U48,1212 .offset = 91,1213 .width = 48,1214 },1215 [VCAP_KF_L2_SNAP] = {1216 .type = VCAP_FIELD_U48,1217 .offset = 139,1218 .width = 40,1219 },1220};1221 1222static const struct vcap_field is2_arp_keyfield[] = {1223 [VCAP_KF_TYPE] = {1224 .type = VCAP_FIELD_U32,1225 .offset = 0,1226 .width = 4,1227 },1228 [VCAP_KF_LOOKUP_FIRST_IS] = {1229 .type = VCAP_FIELD_BIT,1230 .offset = 4,1231 .width = 1,1232 },1233 [VCAP_KF_LOOKUP_PAG] = {1234 .type = VCAP_FIELD_U32,1235 .offset = 5,1236 .width = 8,1237 },1238 [VCAP_KF_IF_IGR_PORT_MASK] = {1239 .type = VCAP_FIELD_U32,1240 .offset = 13,1241 .width = 9,1242 },1243 [VCAP_KF_ISDX_GT0_IS] = {1244 .type = VCAP_FIELD_BIT,1245 .offset = 22,1246 .width = 1,1247 },1248 [VCAP_KF_HOST_MATCH] = {1249 .type = VCAP_FIELD_BIT,1250 .offset = 23,1251 .width = 1,1252 },1253 [VCAP_KF_L2_MC_IS] = {1254 .type = VCAP_FIELD_BIT,1255 .offset = 24,1256 .width = 1,1257 },1258 [VCAP_KF_L2_BC_IS] = {1259 .type = VCAP_FIELD_BIT,1260 .offset = 25,1261 .width = 1,1262 },1263 [VCAP_KF_8021Q_VLAN_TAGGED_IS] = {1264 .type = VCAP_FIELD_BIT,1265 .offset = 26,1266 .width = 1,1267 },1268 [VCAP_KF_8021Q_VID_CLS] = {1269 .type = VCAP_FIELD_U32,1270 .offset = 27,1271 .width = 12,1272 },1273 [VCAP_KF_8021Q_DEI_CLS] = {1274 .type = VCAP_FIELD_BIT,1275 .offset = 39,1276 .width = 1,1277 },1278 [VCAP_KF_8021Q_PCP_CLS] = {1279 .type = VCAP_FIELD_U32,1280 .offset = 40,1281 .width = 3,1282 },1283 [VCAP_KF_L2_SMAC] = {1284 .type = VCAP_FIELD_U48,1285 .offset = 43,1286 .width = 48,1287 },1288 [VCAP_KF_ARP_ADDR_SPACE_OK_IS] = {1289 .type = VCAP_FIELD_BIT,1290 .offset = 91,1291 .width = 1,1292 },1293 [VCAP_KF_ARP_PROTO_SPACE_OK_IS] = {1294 .type = VCAP_FIELD_BIT,1295 .offset = 92,1296 .width = 1,1297 },1298 [VCAP_KF_ARP_LEN_OK_IS] = {1299 .type = VCAP_FIELD_BIT,1300 .offset = 93,1301 .width = 1,1302 },1303 [VCAP_KF_ARP_TGT_MATCH_IS] = {1304 .type = VCAP_FIELD_BIT,1305 .offset = 94,1306 .width = 1,1307 },1308 [VCAP_KF_ARP_SENDER_MATCH_IS] = {1309 .type = VCAP_FIELD_BIT,1310 .offset = 95,1311 .width = 1,1312 },1313 [VCAP_KF_ARP_OPCODE_UNKNOWN_IS] = {1314 .type = VCAP_FIELD_BIT,1315 .offset = 96,1316 .width = 1,1317 },1318 [VCAP_KF_ARP_OPCODE] = {1319 .type = VCAP_FIELD_U32,1320 .offset = 97,1321 .width = 2,1322 },1323 [VCAP_KF_L3_IP4_DIP] = {1324 .type = VCAP_FIELD_U32,1325 .offset = 99,1326 .width = 32,1327 },1328 [VCAP_KF_L3_IP4_SIP] = {1329 .type = VCAP_FIELD_U32,1330 .offset = 131,1331 .width = 32,1332 },1333 [VCAP_KF_L3_DIP_EQ_SIP_IS] = {1334 .type = VCAP_FIELD_BIT,1335 .offset = 163,1336 .width = 1,1337 },1338};1339 1340static const struct vcap_field is2_ip4_tcp_udp_keyfield[] = {1341 [VCAP_KF_TYPE] = {1342 .type = VCAP_FIELD_U32,1343 .offset = 0,1344 .width = 4,1345 },1346 [VCAP_KF_LOOKUP_FIRST_IS] = {1347 .type = VCAP_FIELD_BIT,1348 .offset = 4,1349 .width = 1,1350 },1351 [VCAP_KF_LOOKUP_PAG] = {1352 .type = VCAP_FIELD_U32,1353 .offset = 5,1354 .width = 8,1355 },1356 [VCAP_KF_IF_IGR_PORT_MASK] = {1357 .type = VCAP_FIELD_U32,1358 .offset = 13,1359 .width = 9,1360 },1361 [VCAP_KF_ISDX_GT0_IS] = {1362 .type = VCAP_FIELD_BIT,1363 .offset = 22,1364 .width = 1,1365 },1366 [VCAP_KF_HOST_MATCH] = {1367 .type = VCAP_FIELD_BIT,1368 .offset = 23,1369 .width = 1,1370 },1371 [VCAP_KF_L2_MC_IS] = {1372 .type = VCAP_FIELD_BIT,1373 .offset = 24,1374 .width = 1,1375 },1376 [VCAP_KF_L2_BC_IS] = {1377 .type = VCAP_FIELD_BIT,1378 .offset = 25,1379 .width = 1,1380 },1381 [VCAP_KF_8021Q_VLAN_TAGGED_IS] = {1382 .type = VCAP_FIELD_BIT,1383 .offset = 26,1384 .width = 1,1385 },1386 [VCAP_KF_8021Q_VID_CLS] = {1387 .type = VCAP_FIELD_U32,1388 .offset = 27,1389 .width = 12,1390 },1391 [VCAP_KF_8021Q_DEI_CLS] = {1392 .type = VCAP_FIELD_BIT,1393 .offset = 39,1394 .width = 1,1395 },1396 [VCAP_KF_8021Q_PCP_CLS] = {1397 .type = VCAP_FIELD_U32,1398 .offset = 40,1399 .width = 3,1400 },1401 [VCAP_KF_IP4_IS] = {1402 .type = VCAP_FIELD_BIT,1403 .offset = 43,1404 .width = 1,1405 },1406 [VCAP_KF_L3_FRAGMENT] = {1407 .type = VCAP_FIELD_BIT,1408 .offset = 44,1409 .width = 1,1410 },1411 [VCAP_KF_L3_FRAG_OFS_GT0] = {1412 .type = VCAP_FIELD_BIT,1413 .offset = 45,1414 .width = 1,1415 },1416 [VCAP_KF_L3_OPTIONS_IS] = {1417 .type = VCAP_FIELD_BIT,1418 .offset = 46,1419 .width = 1,1420 },1421 [VCAP_KF_L3_TTL_GT0] = {1422 .type = VCAP_FIELD_BIT,1423 .offset = 47,1424 .width = 1,1425 },1426 [VCAP_KF_L3_TOS] = {1427 .type = VCAP_FIELD_U32,1428 .offset = 48,1429 .width = 8,1430 },1431 [VCAP_KF_L3_IP4_DIP] = {1432 .type = VCAP_FIELD_U32,1433 .offset = 56,1434 .width = 32,1435 },1436 [VCAP_KF_L3_IP4_SIP] = {1437 .type = VCAP_FIELD_U32,1438 .offset = 88,1439 .width = 32,1440 },1441 [VCAP_KF_L3_DIP_EQ_SIP_IS] = {1442 .type = VCAP_FIELD_BIT,1443 .offset = 120,1444 .width = 1,1445 },1446 [VCAP_KF_TCP_IS] = {1447 .type = VCAP_FIELD_BIT,1448 .offset = 121,1449 .width = 1,1450 },1451 [VCAP_KF_L4_DPORT] = {1452 .type = VCAP_FIELD_U32,1453 .offset = 122,1454 .width = 16,1455 },1456 [VCAP_KF_L4_SPORT] = {1457 .type = VCAP_FIELD_U32,1458 .offset = 138,1459 .width = 16,1460 },1461 [VCAP_KF_L4_RNG] = {1462 .type = VCAP_FIELD_U32,1463 .offset = 154,1464 .width = 8,1465 },1466 [VCAP_KF_L4_SPORT_EQ_DPORT_IS] = {1467 .type = VCAP_FIELD_BIT,1468 .offset = 162,1469 .width = 1,1470 },1471 [VCAP_KF_L4_SEQUENCE_EQ0_IS] = {1472 .type = VCAP_FIELD_BIT,1473 .offset = 163,1474 .width = 1,1475 },1476 [VCAP_KF_L4_FIN] = {1477 .type = VCAP_FIELD_BIT,1478 .offset = 164,1479 .width = 1,1480 },1481 [VCAP_KF_L4_SYN] = {1482 .type = VCAP_FIELD_BIT,1483 .offset = 165,1484 .width = 1,1485 },1486 [VCAP_KF_L4_RST] = {1487 .type = VCAP_FIELD_BIT,1488 .offset = 166,1489 .width = 1,1490 },1491 [VCAP_KF_L4_PSH] = {1492 .type = VCAP_FIELD_BIT,1493 .offset = 167,1494 .width = 1,1495 },1496 [VCAP_KF_L4_ACK] = {1497 .type = VCAP_FIELD_BIT,1498 .offset = 168,1499 .width = 1,1500 },1501 [VCAP_KF_L4_URG] = {1502 .type = VCAP_FIELD_BIT,1503 .offset = 169,1504 .width = 1,1505 },1506 [VCAP_KF_L4_1588_DOM] = {1507 .type = VCAP_FIELD_U32,1508 .offset = 170,1509 .width = 8,1510 },1511 [VCAP_KF_L4_1588_VER] = {1512 .type = VCAP_FIELD_U32,1513 .offset = 178,1514 .width = 4,1515 },1516};1517 1518static const struct vcap_field is2_ip4_other_keyfield[] = {1519 [VCAP_KF_TYPE] = {1520 .type = VCAP_FIELD_U32,1521 .offset = 0,1522 .width = 4,1523 },1524 [VCAP_KF_LOOKUP_FIRST_IS] = {1525 .type = VCAP_FIELD_BIT,1526 .offset = 4,1527 .width = 1,1528 },1529 [VCAP_KF_LOOKUP_PAG] = {1530 .type = VCAP_FIELD_U32,1531 .offset = 5,1532 .width = 8,1533 },1534 [VCAP_KF_IF_IGR_PORT_MASK] = {1535 .type = VCAP_FIELD_U32,1536 .offset = 13,1537 .width = 9,1538 },1539 [VCAP_KF_ISDX_GT0_IS] = {1540 .type = VCAP_FIELD_BIT,1541 .offset = 22,1542 .width = 1,1543 },1544 [VCAP_KF_HOST_MATCH] = {1545 .type = VCAP_FIELD_BIT,1546 .offset = 23,1547 .width = 1,1548 },1549 [VCAP_KF_L2_MC_IS] = {1550 .type = VCAP_FIELD_BIT,1551 .offset = 24,1552 .width = 1,1553 },1554 [VCAP_KF_L2_BC_IS] = {1555 .type = VCAP_FIELD_BIT,1556 .offset = 25,1557 .width = 1,1558 },1559 [VCAP_KF_8021Q_VLAN_TAGGED_IS] = {1560 .type = VCAP_FIELD_BIT,1561 .offset = 26,1562 .width = 1,1563 },1564 [VCAP_KF_8021Q_VID_CLS] = {1565 .type = VCAP_FIELD_U32,1566 .offset = 27,1567 .width = 12,1568 },1569 [VCAP_KF_8021Q_DEI_CLS] = {1570 .type = VCAP_FIELD_BIT,1571 .offset = 39,1572 .width = 1,1573 },1574 [VCAP_KF_8021Q_PCP_CLS] = {1575 .type = VCAP_FIELD_U32,1576 .offset = 40,1577 .width = 3,1578 },1579 [VCAP_KF_IP4_IS] = {1580 .type = VCAP_FIELD_BIT,1581 .offset = 43,1582 .width = 1,1583 },1584 [VCAP_KF_L3_FRAGMENT] = {1585 .type = VCAP_FIELD_BIT,1586 .offset = 44,1587 .width = 1,1588 },1589 [VCAP_KF_L3_FRAG_OFS_GT0] = {1590 .type = VCAP_FIELD_BIT,1591 .offset = 45,1592 .width = 1,1593 },1594 [VCAP_KF_L3_OPTIONS_IS] = {1595 .type = VCAP_FIELD_BIT,1596 .offset = 46,1597 .width = 1,1598 },1599 [VCAP_KF_L3_TTL_GT0] = {1600 .type = VCAP_FIELD_BIT,1601 .offset = 47,1602 .width = 1,1603 },1604 [VCAP_KF_L3_TOS] = {1605 .type = VCAP_FIELD_U32,1606 .offset = 48,1607 .width = 8,1608 },1609 [VCAP_KF_L3_IP4_DIP] = {1610 .type = VCAP_FIELD_U32,1611 .offset = 56,1612 .width = 32,1613 },1614 [VCAP_KF_L3_IP4_SIP] = {1615 .type = VCAP_FIELD_U32,1616 .offset = 88,1617 .width = 32,1618 },1619 [VCAP_KF_L3_DIP_EQ_SIP_IS] = {1620 .type = VCAP_FIELD_BIT,1621 .offset = 120,1622 .width = 1,1623 },1624 [VCAP_KF_L3_IP_PROTO] = {1625 .type = VCAP_FIELD_U32,1626 .offset = 121,1627 .width = 8,1628 },1629 [VCAP_KF_L3_PAYLOAD] = {1630 .type = VCAP_FIELD_U56,1631 .offset = 129,1632 .width = 56,1633 },1634};1635 1636static const struct vcap_field is2_ip6_std_keyfield[] = {1637 [VCAP_KF_TYPE] = {1638 .type = VCAP_FIELD_U32,1639 .offset = 0,1640 .width = 4,1641 },1642 [VCAP_KF_LOOKUP_FIRST_IS] = {1643 .type = VCAP_FIELD_BIT,1644 .offset = 4,1645 .width = 1,1646 },1647 [VCAP_KF_LOOKUP_PAG] = {1648 .type = VCAP_FIELD_U32,1649 .offset = 5,1650 .width = 8,1651 },1652 [VCAP_KF_IF_IGR_PORT_MASK] = {1653 .type = VCAP_FIELD_U32,1654 .offset = 13,1655 .width = 9,1656 },1657 [VCAP_KF_ISDX_GT0_IS] = {1658 .type = VCAP_FIELD_BIT,1659 .offset = 22,1660 .width = 1,1661 },1662 [VCAP_KF_HOST_MATCH] = {1663 .type = VCAP_FIELD_BIT,1664 .offset = 23,1665 .width = 1,1666 },1667 [VCAP_KF_L2_MC_IS] = {1668 .type = VCAP_FIELD_BIT,1669 .offset = 24,1670 .width = 1,1671 },1672 [VCAP_KF_L2_BC_IS] = {1673 .type = VCAP_FIELD_BIT,1674 .offset = 25,1675 .width = 1,1676 },1677 [VCAP_KF_8021Q_VLAN_TAGGED_IS] = {1678 .type = VCAP_FIELD_BIT,1679 .offset = 26,1680 .width = 1,1681 },1682 [VCAP_KF_8021Q_VID_CLS] = {1683 .type = VCAP_FIELD_U32,1684 .offset = 27,1685 .width = 12,1686 },1687 [VCAP_KF_8021Q_DEI_CLS] = {1688 .type = VCAP_FIELD_BIT,1689 .offset = 39,1690 .width = 1,1691 },1692 [VCAP_KF_8021Q_PCP_CLS] = {1693 .type = VCAP_FIELD_U32,1694 .offset = 40,1695 .width = 3,1696 },1697 [VCAP_KF_L3_TTL_GT0] = {1698 .type = VCAP_FIELD_BIT,1699 .offset = 43,1700 .width = 1,1701 },1702 [VCAP_KF_L3_IP6_SIP] = {1703 .type = VCAP_FIELD_U128,1704 .offset = 44,1705 .width = 128,1706 },1707 [VCAP_KF_L3_IP_PROTO] = {1708 .type = VCAP_FIELD_U32,1709 .offset = 172,1710 .width = 8,1711 },1712};1713 1714static const struct vcap_field is2_oam_keyfield[] = {1715 [VCAP_KF_TYPE] = {1716 .type = VCAP_FIELD_U32,1717 .offset = 0,1718 .width = 4,1719 },1720 [VCAP_KF_LOOKUP_FIRST_IS] = {1721 .type = VCAP_FIELD_BIT,1722 .offset = 4,1723 .width = 1,1724 },1725 [VCAP_KF_LOOKUP_PAG] = {1726 .type = VCAP_FIELD_U32,1727 .offset = 5,1728 .width = 8,1729 },1730 [VCAP_KF_IF_IGR_PORT_MASK] = {1731 .type = VCAP_FIELD_U32,1732 .offset = 13,1733 .width = 9,1734 },1735 [VCAP_KF_ISDX_GT0_IS] = {1736 .type = VCAP_FIELD_BIT,1737 .offset = 22,1738 .width = 1,1739 },1740 [VCAP_KF_HOST_MATCH] = {1741 .type = VCAP_FIELD_BIT,1742 .offset = 23,1743 .width = 1,1744 },1745 [VCAP_KF_L2_MC_IS] = {1746 .type = VCAP_FIELD_BIT,1747 .offset = 24,1748 .width = 1,1749 },1750 [VCAP_KF_L2_BC_IS] = {1751 .type = VCAP_FIELD_BIT,1752 .offset = 25,1753 .width = 1,1754 },1755 [VCAP_KF_8021Q_VLAN_TAGGED_IS] = {1756 .type = VCAP_FIELD_BIT,1757 .offset = 26,1758 .width = 1,1759 },1760 [VCAP_KF_8021Q_VID_CLS] = {1761 .type = VCAP_FIELD_U32,1762 .offset = 27,1763 .width = 12,1764 },1765 [VCAP_KF_8021Q_DEI_CLS] = {1766 .type = VCAP_FIELD_BIT,1767 .offset = 39,1768 .width = 1,1769 },1770 [VCAP_KF_8021Q_PCP_CLS] = {1771 .type = VCAP_FIELD_U32,1772 .offset = 40,1773 .width = 3,1774 },1775 [VCAP_KF_L2_DMAC] = {1776 .type = VCAP_FIELD_U48,1777 .offset = 43,1778 .width = 48,1779 },1780 [VCAP_KF_L2_SMAC] = {1781 .type = VCAP_FIELD_U48,1782 .offset = 91,1783 .width = 48,1784 },1785 [VCAP_KF_OAM_MEL_FLAGS] = {1786 .type = VCAP_FIELD_U32,1787 .offset = 139,1788 .width = 7,1789 },1790 [VCAP_KF_OAM_VER] = {1791 .type = VCAP_FIELD_U32,1792 .offset = 146,1793 .width = 5,1794 },1795 [VCAP_KF_OAM_OPCODE] = {1796 .type = VCAP_FIELD_U32,1797 .offset = 151,1798 .width = 8,1799 },1800 [VCAP_KF_OAM_FLAGS] = {1801 .type = VCAP_FIELD_U32,1802 .offset = 159,1803 .width = 8,1804 },1805 [VCAP_KF_OAM_MEPID] = {1806 .type = VCAP_FIELD_U32,1807 .offset = 167,1808 .width = 16,1809 },1810 [VCAP_KF_OAM_CCM_CNTS_EQ0] = {1811 .type = VCAP_FIELD_BIT,1812 .offset = 183,1813 .width = 1,1814 },1815 [VCAP_KF_OAM_Y1731_IS] = {1816 .type = VCAP_FIELD_BIT,1817 .offset = 184,1818 .width = 1,1819 },1820 [VCAP_KF_OAM_DETECTED] = {1821 .type = VCAP_FIELD_BIT,1822 .offset = 185,1823 .width = 1,1824 },1825};1826 1827static const struct vcap_field is2_ip6_tcp_udp_keyfield[] = {1828 [VCAP_KF_TYPE] = {1829 .type = VCAP_FIELD_U32,1830 .offset = 0,1831 .width = 2,1832 },1833 [VCAP_KF_LOOKUP_FIRST_IS] = {1834 .type = VCAP_FIELD_BIT,1835 .offset = 2,1836 .width = 1,1837 },1838 [VCAP_KF_LOOKUP_PAG] = {1839 .type = VCAP_FIELD_U32,1840 .offset = 3,1841 .width = 8,1842 },1843 [VCAP_KF_IF_IGR_PORT_MASK] = {1844 .type = VCAP_FIELD_U32,1845 .offset = 11,1846 .width = 9,1847 },1848 [VCAP_KF_ISDX_GT0_IS] = {1849 .type = VCAP_FIELD_BIT,1850 .offset = 20,1851 .width = 1,1852 },1853 [VCAP_KF_HOST_MATCH] = {1854 .type = VCAP_FIELD_BIT,1855 .offset = 21,1856 .width = 1,1857 },1858 [VCAP_KF_L2_MC_IS] = {1859 .type = VCAP_FIELD_BIT,1860 .offset = 22,1861 .width = 1,1862 },1863 [VCAP_KF_L2_BC_IS] = {1864 .type = VCAP_FIELD_BIT,1865 .offset = 23,1866 .width = 1,1867 },1868 [VCAP_KF_8021Q_VLAN_TAGGED_IS] = {1869 .type = VCAP_FIELD_BIT,1870 .offset = 24,1871 .width = 1,1872 },1873 [VCAP_KF_8021Q_VID_CLS] = {1874 .type = VCAP_FIELD_U32,1875 .offset = 25,1876 .width = 12,1877 },1878 [VCAP_KF_8021Q_DEI_CLS] = {1879 .type = VCAP_FIELD_BIT,1880 .offset = 37,1881 .width = 1,1882 },1883 [VCAP_KF_8021Q_PCP_CLS] = {1884 .type = VCAP_FIELD_U32,1885 .offset = 38,1886 .width = 3,1887 },1888 [VCAP_KF_L3_TTL_GT0] = {1889 .type = VCAP_FIELD_BIT,1890 .offset = 41,1891 .width = 1,1892 },1893 [VCAP_KF_L3_TOS] = {1894 .type = VCAP_FIELD_U32,1895 .offset = 42,1896 .width = 8,1897 },1898 [VCAP_KF_L3_IP6_DIP] = {1899 .type = VCAP_FIELD_U128,1900 .offset = 50,1901 .width = 128,1902 },1903 [VCAP_KF_L3_IP6_SIP] = {1904 .type = VCAP_FIELD_U128,1905 .offset = 178,1906 .width = 128,1907 },1908 [VCAP_KF_L3_DIP_EQ_SIP_IS] = {1909 .type = VCAP_FIELD_BIT,1910 .offset = 306,1911 .width = 1,1912 },1913 [VCAP_KF_TCP_IS] = {1914 .type = VCAP_FIELD_BIT,1915 .offset = 307,1916 .width = 1,1917 },1918 [VCAP_KF_L4_DPORT] = {1919 .type = VCAP_FIELD_U32,1920 .offset = 308,1921 .width = 16,1922 },1923 [VCAP_KF_L4_SPORT] = {1924 .type = VCAP_FIELD_U32,1925 .offset = 324,1926 .width = 16,1927 },1928 [VCAP_KF_L4_RNG] = {1929 .type = VCAP_FIELD_U32,1930 .offset = 340,1931 .width = 8,1932 },1933 [VCAP_KF_L4_SPORT_EQ_DPORT_IS] = {1934 .type = VCAP_FIELD_BIT,1935 .offset = 348,1936 .width = 1,1937 },1938 [VCAP_KF_L4_SEQUENCE_EQ0_IS] = {1939 .type = VCAP_FIELD_BIT,1940 .offset = 349,1941 .width = 1,1942 },1943 [VCAP_KF_L4_FIN] = {1944 .type = VCAP_FIELD_BIT,1945 .offset = 350,1946 .width = 1,1947 },1948 [VCAP_KF_L4_SYN] = {1949 .type = VCAP_FIELD_BIT,1950 .offset = 351,1951 .width = 1,1952 },1953 [VCAP_KF_L4_RST] = {1954 .type = VCAP_FIELD_BIT,1955 .offset = 352,1956 .width = 1,1957 },1958 [VCAP_KF_L4_PSH] = {1959 .type = VCAP_FIELD_BIT,1960 .offset = 353,1961 .width = 1,1962 },1963 [VCAP_KF_L4_ACK] = {1964 .type = VCAP_FIELD_BIT,1965 .offset = 354,1966 .width = 1,1967 },1968 [VCAP_KF_L4_URG] = {1969 .type = VCAP_FIELD_BIT,1970 .offset = 355,1971 .width = 1,1972 },1973 [VCAP_KF_L4_1588_DOM] = {1974 .type = VCAP_FIELD_U32,1975 .offset = 356,1976 .width = 8,1977 },1978 [VCAP_KF_L4_1588_VER] = {1979 .type = VCAP_FIELD_U32,1980 .offset = 364,1981 .width = 4,1982 },1983};1984 1985static const struct vcap_field is2_ip6_other_keyfield[] = {1986 [VCAP_KF_TYPE] = {1987 .type = VCAP_FIELD_U32,1988 .offset = 0,1989 .width = 2,1990 },1991 [VCAP_KF_LOOKUP_FIRST_IS] = {1992 .type = VCAP_FIELD_BIT,1993 .offset = 2,1994 .width = 1,1995 },1996 [VCAP_KF_LOOKUP_PAG] = {1997 .type = VCAP_FIELD_U32,1998 .offset = 3,1999 .width = 8,2000 },2001 [VCAP_KF_IF_IGR_PORT_MASK] = {2002 .type = VCAP_FIELD_U32,2003 .offset = 11,2004 .width = 9,2005 },2006 [VCAP_KF_ISDX_GT0_IS] = {2007 .type = VCAP_FIELD_BIT,2008 .offset = 20,2009 .width = 1,2010 },2011 [VCAP_KF_HOST_MATCH] = {2012 .type = VCAP_FIELD_BIT,2013 .offset = 21,2014 .width = 1,2015 },2016 [VCAP_KF_L2_MC_IS] = {2017 .type = VCAP_FIELD_BIT,2018 .offset = 22,2019 .width = 1,2020 },2021 [VCAP_KF_L2_BC_IS] = {2022 .type = VCAP_FIELD_BIT,2023 .offset = 23,2024 .width = 1,2025 },2026 [VCAP_KF_8021Q_VLAN_TAGGED_IS] = {2027 .type = VCAP_FIELD_BIT,2028 .offset = 24,2029 .width = 1,2030 },2031 [VCAP_KF_8021Q_VID_CLS] = {2032 .type = VCAP_FIELD_U32,2033 .offset = 25,2034 .width = 12,2035 },2036 [VCAP_KF_8021Q_DEI_CLS] = {2037 .type = VCAP_FIELD_BIT,2038 .offset = 37,2039 .width = 1,2040 },2041 [VCAP_KF_8021Q_PCP_CLS] = {2042 .type = VCAP_FIELD_U32,2043 .offset = 38,2044 .width = 3,2045 },2046 [VCAP_KF_L3_TTL_GT0] = {2047 .type = VCAP_FIELD_BIT,2048 .offset = 41,2049 .width = 1,2050 },2051 [VCAP_KF_L3_TOS] = {2052 .type = VCAP_FIELD_U32,2053 .offset = 42,2054 .width = 8,2055 },2056 [VCAP_KF_L3_IP6_DIP] = {2057 .type = VCAP_FIELD_U128,2058 .offset = 50,2059 .width = 128,2060 },2061 [VCAP_KF_L3_IP6_SIP] = {2062 .type = VCAP_FIELD_U128,2063 .offset = 178,2064 .width = 128,2065 },2066 [VCAP_KF_L3_DIP_EQ_SIP_IS] = {2067 .type = VCAP_FIELD_BIT,2068 .offset = 306,2069 .width = 1,2070 },2071 [VCAP_KF_L3_IP_PROTO] = {2072 .type = VCAP_FIELD_U32,2073 .offset = 307,2074 .width = 8,2075 },2076 [VCAP_KF_L3_PAYLOAD] = {2077 .type = VCAP_FIELD_U56,2078 .offset = 315,2079 .width = 56,2080 },2081};2082 2083static const struct vcap_field is2_smac_sip4_keyfield[] = {2084 [VCAP_KF_IF_IGR_PORT] = {2085 .type = VCAP_FIELD_U32,2086 .offset = 0,2087 .width = 4,2088 },2089 [VCAP_KF_L2_SMAC] = {2090 .type = VCAP_FIELD_U48,2091 .offset = 4,2092 .width = 48,2093 },2094 [VCAP_KF_L3_IP4_SIP] = {2095 .type = VCAP_FIELD_U32,2096 .offset = 52,2097 .width = 32,2098 },2099};2100 2101static const struct vcap_field is2_smac_sip6_keyfield[] = {2102 [VCAP_KF_TYPE] = {2103 .type = VCAP_FIELD_U32,2104 .offset = 0,2105 .width = 4,2106 },2107 [VCAP_KF_IF_IGR_PORT] = {2108 .type = VCAP_FIELD_U32,2109 .offset = 4,2110 .width = 4,2111 },2112 [VCAP_KF_L2_SMAC] = {2113 .type = VCAP_FIELD_U48,2114 .offset = 8,2115 .width = 48,2116 },2117 [VCAP_KF_L3_IP6_SIP] = {2118 .type = VCAP_FIELD_U128,2119 .offset = 56,2120 .width = 128,2121 },2122};2123 2124static const struct vcap_field es0_vid_keyfield[] = {2125 [VCAP_KF_IF_EGR_PORT_NO] = {2126 .type = VCAP_FIELD_U32,2127 .offset = 0,2128 .width = 4,2129 },2130 [VCAP_KF_IF_IGR_PORT] = {2131 .type = VCAP_FIELD_U32,2132 .offset = 4,2133 .width = 4,2134 },2135 [VCAP_KF_ISDX_GT0_IS] = {2136 .type = VCAP_FIELD_BIT,2137 .offset = 8,2138 .width = 1,2139 },2140 [VCAP_KF_ISDX_CLS] = {2141 .type = VCAP_FIELD_U32,2142 .offset = 9,2143 .width = 8,2144 },2145 [VCAP_KF_L2_MC_IS] = {2146 .type = VCAP_FIELD_BIT,2147 .offset = 17,2148 .width = 1,2149 },2150 [VCAP_KF_L2_BC_IS] = {2151 .type = VCAP_FIELD_BIT,2152 .offset = 18,2153 .width = 1,2154 },2155 [VCAP_KF_8021Q_VID_CLS] = {2156 .type = VCAP_FIELD_U32,2157 .offset = 19,2158 .width = 12,2159 },2160 [VCAP_KF_8021Q_DEI_CLS] = {2161 .type = VCAP_FIELD_BIT,2162 .offset = 31,2163 .width = 1,2164 },2165 [VCAP_KF_8021Q_PCP_CLS] = {2166 .type = VCAP_FIELD_U32,2167 .offset = 32,2168 .width = 3,2169 },2170 [VCAP_KF_L3_DPL_CLS] = {2171 .type = VCAP_FIELD_BIT,2172 .offset = 35,2173 .width = 1,2174 },2175 [VCAP_KF_RTP_ID] = {2176 .type = VCAP_FIELD_U32,2177 .offset = 36,2178 .width = 10,2179 },2180 [VCAP_KF_PDU_TYPE] = {2181 .type = VCAP_FIELD_U32,2182 .offset = 46,2183 .width = 4,2184 },2185};2186 2187/* keyfield_set */2188static const struct vcap_set is1_keyfield_set[] = {2189 [VCAP_KFS_NORMAL] = {2190 .type_id = 0,2191 .sw_per_item = 2,2192 .sw_cnt = 2,2193 },2194 [VCAP_KFS_5TUPLE_IP4] = {2195 .type_id = 1,2196 .sw_per_item = 2,2197 .sw_cnt = 2,2198 },2199 [VCAP_KFS_NORMAL_IP6] = {2200 .type_id = 0,2201 .sw_per_item = 4,2202 .sw_cnt = 1,2203 },2204 [VCAP_KFS_7TUPLE] = {2205 .type_id = 1,2206 .sw_per_item = 4,2207 .sw_cnt = 1,2208 },2209 [VCAP_KFS_5TUPLE_IP6] = {2210 .type_id = 2,2211 .sw_per_item = 4,2212 .sw_cnt = 1,2213 },2214 [VCAP_KFS_DBL_VID] = {2215 .type_id = 0,2216 .sw_per_item = 1,2217 .sw_cnt = 4,2218 },2219 [VCAP_KFS_RT] = {2220 .type_id = 1,2221 .sw_per_item = 1,2222 .sw_cnt = 4,2223 },2224 [VCAP_KFS_DMAC_VID] = {2225 .type_id = 2,2226 .sw_per_item = 1,2227 .sw_cnt = 4,2228 },2229};2230 2231static const struct vcap_set is2_keyfield_set[] = {2232 [VCAP_KFS_MAC_ETYPE] = {2233 .type_id = 0,2234 .sw_per_item = 2,2235 .sw_cnt = 2,2236 },2237 [VCAP_KFS_MAC_LLC] = {2238 .type_id = 1,2239 .sw_per_item = 2,2240 .sw_cnt = 2,2241 },2242 [VCAP_KFS_MAC_SNAP] = {2243 .type_id = 2,2244 .sw_per_item = 2,2245 .sw_cnt = 2,2246 },2247 [VCAP_KFS_ARP] = {2248 .type_id = 3,2249 .sw_per_item = 2,2250 .sw_cnt = 2,2251 },2252 [VCAP_KFS_IP4_TCP_UDP] = {2253 .type_id = 4,2254 .sw_per_item = 2,2255 .sw_cnt = 2,2256 },2257 [VCAP_KFS_IP4_OTHER] = {2258 .type_id = 5,2259 .sw_per_item = 2,2260 .sw_cnt = 2,2261 },2262 [VCAP_KFS_IP6_STD] = {2263 .type_id = 6,2264 .sw_per_item = 2,2265 .sw_cnt = 2,2266 },2267 [VCAP_KFS_OAM] = {2268 .type_id = 7,2269 .sw_per_item = 2,2270 .sw_cnt = 2,2271 },2272 [VCAP_KFS_IP6_TCP_UDP] = {2273 .type_id = 0,2274 .sw_per_item = 4,2275 .sw_cnt = 1,2276 },2277 [VCAP_KFS_IP6_OTHER] = {2278 .type_id = 1,2279 .sw_per_item = 4,2280 .sw_cnt = 1,2281 },2282 [VCAP_KFS_SMAC_SIP4] = {2283 .type_id = -1,2284 .sw_per_item = 1,2285 .sw_cnt = 4,2286 },2287 [VCAP_KFS_SMAC_SIP6] = {2288 .type_id = 8,2289 .sw_per_item = 2,2290 .sw_cnt = 2,2291 },2292};2293 2294static const struct vcap_set es0_keyfield_set[] = {2295 [VCAP_KFS_VID] = {2296 .type_id = -1,2297 .sw_per_item = 1,2298 .sw_cnt = 1,2299 },2300};2301 2302/* keyfield_set map */2303static const struct vcap_field *is1_keyfield_set_map[] = {2304 [VCAP_KFS_NORMAL] = is1_normal_keyfield,2305 [VCAP_KFS_5TUPLE_IP4] = is1_5tuple_ip4_keyfield,2306 [VCAP_KFS_NORMAL_IP6] = is1_normal_ip6_keyfield,2307 [VCAP_KFS_7TUPLE] = is1_7tuple_keyfield,2308 [VCAP_KFS_5TUPLE_IP6] = is1_5tuple_ip6_keyfield,2309 [VCAP_KFS_DBL_VID] = is1_dbl_vid_keyfield,2310 [VCAP_KFS_RT] = is1_rt_keyfield,2311 [VCAP_KFS_DMAC_VID] = is1_dmac_vid_keyfield,2312};2313 2314static const struct vcap_field *is2_keyfield_set_map[] = {2315 [VCAP_KFS_MAC_ETYPE] = is2_mac_etype_keyfield,2316 [VCAP_KFS_MAC_LLC] = is2_mac_llc_keyfield,2317 [VCAP_KFS_MAC_SNAP] = is2_mac_snap_keyfield,2318 [VCAP_KFS_ARP] = is2_arp_keyfield,2319 [VCAP_KFS_IP4_TCP_UDP] = is2_ip4_tcp_udp_keyfield,2320 [VCAP_KFS_IP4_OTHER] = is2_ip4_other_keyfield,2321 [VCAP_KFS_IP6_STD] = is2_ip6_std_keyfield,2322 [VCAP_KFS_OAM] = is2_oam_keyfield,2323 [VCAP_KFS_IP6_TCP_UDP] = is2_ip6_tcp_udp_keyfield,2324 [VCAP_KFS_IP6_OTHER] = is2_ip6_other_keyfield,2325 [VCAP_KFS_SMAC_SIP4] = is2_smac_sip4_keyfield,2326 [VCAP_KFS_SMAC_SIP6] = is2_smac_sip6_keyfield,2327};2328 2329static const struct vcap_field *es0_keyfield_set_map[] = {2330 [VCAP_KFS_VID] = es0_vid_keyfield,2331};2332 2333/* keyfield_set map sizes */2334static int is1_keyfield_set_map_size[] = {2335 [VCAP_KFS_NORMAL] = ARRAY_SIZE(is1_normal_keyfield),2336 [VCAP_KFS_5TUPLE_IP4] = ARRAY_SIZE(is1_5tuple_ip4_keyfield),2337 [VCAP_KFS_NORMAL_IP6] = ARRAY_SIZE(is1_normal_ip6_keyfield),2338 [VCAP_KFS_7TUPLE] = ARRAY_SIZE(is1_7tuple_keyfield),2339 [VCAP_KFS_5TUPLE_IP6] = ARRAY_SIZE(is1_5tuple_ip6_keyfield),2340 [VCAP_KFS_DBL_VID] = ARRAY_SIZE(is1_dbl_vid_keyfield),2341 [VCAP_KFS_RT] = ARRAY_SIZE(is1_rt_keyfield),2342 [VCAP_KFS_DMAC_VID] = ARRAY_SIZE(is1_dmac_vid_keyfield),2343};2344 2345static int is2_keyfield_set_map_size[] = {2346 [VCAP_KFS_MAC_ETYPE] = ARRAY_SIZE(is2_mac_etype_keyfield),2347 [VCAP_KFS_MAC_LLC] = ARRAY_SIZE(is2_mac_llc_keyfield),2348 [VCAP_KFS_MAC_SNAP] = ARRAY_SIZE(is2_mac_snap_keyfield),2349 [VCAP_KFS_ARP] = ARRAY_SIZE(is2_arp_keyfield),2350 [VCAP_KFS_IP4_TCP_UDP] = ARRAY_SIZE(is2_ip4_tcp_udp_keyfield),2351 [VCAP_KFS_IP4_OTHER] = ARRAY_SIZE(is2_ip4_other_keyfield),2352 [VCAP_KFS_IP6_STD] = ARRAY_SIZE(is2_ip6_std_keyfield),2353 [VCAP_KFS_OAM] = ARRAY_SIZE(is2_oam_keyfield),2354 [VCAP_KFS_IP6_TCP_UDP] = ARRAY_SIZE(is2_ip6_tcp_udp_keyfield),2355 [VCAP_KFS_IP6_OTHER] = ARRAY_SIZE(is2_ip6_other_keyfield),2356 [VCAP_KFS_SMAC_SIP4] = ARRAY_SIZE(is2_smac_sip4_keyfield),2357 [VCAP_KFS_SMAC_SIP6] = ARRAY_SIZE(is2_smac_sip6_keyfield),2358};2359 2360static int es0_keyfield_set_map_size[] = {2361 [VCAP_KFS_VID] = ARRAY_SIZE(es0_vid_keyfield),2362};2363 2364/* actionfields */2365static const struct vcap_field is1_s1_actionfield[] = {2366 [VCAP_AF_TYPE] = {2367 .type = VCAP_FIELD_BIT,2368 .offset = 0,2369 .width = 1,2370 },2371 [VCAP_AF_DSCP_ENA] = {2372 .type = VCAP_FIELD_BIT,2373 .offset = 1,2374 .width = 1,2375 },2376 [VCAP_AF_DSCP_VAL] = {2377 .type = VCAP_FIELD_U32,2378 .offset = 2,2379 .width = 6,2380 },2381 [VCAP_AF_QOS_ENA] = {2382 .type = VCAP_FIELD_BIT,2383 .offset = 8,2384 .width = 1,2385 },2386 [VCAP_AF_QOS_VAL] = {2387 .type = VCAP_FIELD_U32,2388 .offset = 9,2389 .width = 3,2390 },2391 [VCAP_AF_DP_ENA] = {2392 .type = VCAP_FIELD_BIT,2393 .offset = 12,2394 .width = 1,2395 },2396 [VCAP_AF_DP_VAL] = {2397 .type = VCAP_FIELD_BIT,2398 .offset = 13,2399 .width = 1,2400 },2401 [VCAP_AF_PAG_OVERRIDE_MASK] = {2402 .type = VCAP_FIELD_U32,2403 .offset = 14,2404 .width = 8,2405 },2406 [VCAP_AF_PAG_VAL] = {2407 .type = VCAP_FIELD_U32,2408 .offset = 22,2409 .width = 8,2410 },2411 [VCAP_AF_ISDX_REPLACE_ENA] = {2412 .type = VCAP_FIELD_BIT,2413 .offset = 30,2414 .width = 1,2415 },2416 [VCAP_AF_ISDX_ADD_VAL] = {2417 .type = VCAP_FIELD_U32,2418 .offset = 31,2419 .width = 8,2420 },2421 [VCAP_AF_VID_REPLACE_ENA] = {2422 .type = VCAP_FIELD_BIT,2423 .offset = 39,2424 .width = 1,2425 },2426 [VCAP_AF_VID_VAL] = {2427 .type = VCAP_FIELD_U32,2428 .offset = 40,2429 .width = 12,2430 },2431 [VCAP_AF_PCP_ENA] = {2432 .type = VCAP_FIELD_BIT,2433 .offset = 67,2434 .width = 1,2435 },2436 [VCAP_AF_PCP_VAL] = {2437 .type = VCAP_FIELD_U32,2438 .offset = 68,2439 .width = 3,2440 },2441 [VCAP_AF_DEI_ENA] = {2442 .type = VCAP_FIELD_BIT,2443 .offset = 71,2444 .width = 1,2445 },2446 [VCAP_AF_DEI_VAL] = {2447 .type = VCAP_FIELD_BIT,2448 .offset = 72,2449 .width = 1,2450 },2451 [VCAP_AF_VLAN_POP_CNT_ENA] = {2452 .type = VCAP_FIELD_BIT,2453 .offset = 73,2454 .width = 1,2455 },2456 [VCAP_AF_VLAN_POP_CNT] = {2457 .type = VCAP_FIELD_U32,2458 .offset = 74,2459 .width = 2,2460 },2461 [VCAP_AF_CUSTOM_ACE_TYPE_ENA] = {2462 .type = VCAP_FIELD_U32,2463 .offset = 76,2464 .width = 4,2465 },2466 [VCAP_AF_SFID_ENA] = {2467 .type = VCAP_FIELD_BIT,2468 .offset = 80,2469 .width = 1,2470 },2471 [VCAP_AF_SFID_VAL] = {2472 .type = VCAP_FIELD_U32,2473 .offset = 81,2474 .width = 8,2475 },2476 [VCAP_AF_SGID_ENA] = {2477 .type = VCAP_FIELD_BIT,2478 .offset = 89,2479 .width = 1,2480 },2481 [VCAP_AF_SGID_VAL] = {2482 .type = VCAP_FIELD_U32,2483 .offset = 90,2484 .width = 8,2485 },2486 [VCAP_AF_POLICE_ENA] = {2487 .type = VCAP_FIELD_BIT,2488 .offset = 98,2489 .width = 1,2490 },2491 [VCAP_AF_POLICE_IDX] = {2492 .type = VCAP_FIELD_U32,2493 .offset = 99,2494 .width = 9,2495 },2496 [VCAP_AF_OAM_SEL] = {2497 .type = VCAP_FIELD_U32,2498 .offset = 108,2499 .width = 3,2500 },2501 [VCAP_AF_MRP_SEL] = {2502 .type = VCAP_FIELD_U32,2503 .offset = 111,2504 .width = 2,2505 },2506 [VCAP_AF_DLR_SEL] = {2507 .type = VCAP_FIELD_U32,2508 .offset = 113,2509 .width = 2,2510 },2511};2512 2513static const struct vcap_field is2_base_type_actionfield[] = {2514 [VCAP_AF_HIT_ME_ONCE] = {2515 .type = VCAP_FIELD_BIT,2516 .offset = 0,2517 .width = 1,2518 },2519 [VCAP_AF_CPU_COPY_ENA] = {2520 .type = VCAP_FIELD_BIT,2521 .offset = 1,2522 .width = 1,2523 },2524 [VCAP_AF_CPU_QUEUE_NUM] = {2525 .type = VCAP_FIELD_U32,2526 .offset = 2,2527 .width = 3,2528 },2529 [VCAP_AF_MASK_MODE] = {2530 .type = VCAP_FIELD_U32,2531 .offset = 5,2532 .width = 2,2533 },2534 [VCAP_AF_MIRROR_ENA] = {2535 .type = VCAP_FIELD_BIT,2536 .offset = 7,2537 .width = 1,2538 },2539 [VCAP_AF_LRN_DIS] = {2540 .type = VCAP_FIELD_BIT,2541 .offset = 8,2542 .width = 1,2543 },2544 [VCAP_AF_POLICE_ENA] = {2545 .type = VCAP_FIELD_BIT,2546 .offset = 9,2547 .width = 1,2548 },2549 [VCAP_AF_POLICE_IDX] = {2550 .type = VCAP_FIELD_U32,2551 .offset = 10,2552 .width = 9,2553 },2554 [VCAP_AF_POLICE_VCAP_ONLY] = {2555 .type = VCAP_FIELD_BIT,2556 .offset = 19,2557 .width = 1,2558 },2559 [VCAP_AF_PORT_MASK] = {2560 .type = VCAP_FIELD_U32,2561 .offset = 20,2562 .width = 8,2563 },2564 [VCAP_AF_REW_OP] = {2565 .type = VCAP_FIELD_U32,2566 .offset = 28,2567 .width = 16,2568 },2569 [VCAP_AF_ISDX_ENA] = {2570 .type = VCAP_FIELD_BIT,2571 .offset = 44,2572 .width = 1,2573 },2574 [VCAP_AF_ACL_ID] = {2575 .type = VCAP_FIELD_U32,2576 .offset = 45,2577 .width = 6,2578 },2579};2580 2581static const struct vcap_field is2_smac_sip_actionfield[] = {2582 [VCAP_AF_CPU_COPY_ENA] = {2583 .type = VCAP_FIELD_BIT,2584 .offset = 0,2585 .width = 1,2586 },2587 [VCAP_AF_CPU_QUEUE_NUM] = {2588 .type = VCAP_FIELD_U32,2589 .offset = 1,2590 .width = 3,2591 },2592 [VCAP_AF_FWD_KILL_ENA] = {2593 .type = VCAP_FIELD_BIT,2594 .offset = 4,2595 .width = 1,2596 },2597 [VCAP_AF_HOST_MATCH] = {2598 .type = VCAP_FIELD_BIT,2599 .offset = 5,2600 .width = 1,2601 },2602};2603 2604static const struct vcap_field es0_vid_actionfield[] = {2605 [VCAP_AF_PUSH_OUTER_TAG] = {2606 .type = VCAP_FIELD_U32,2607 .offset = 0,2608 .width = 2,2609 },2610 [VCAP_AF_PUSH_INNER_TAG] = {2611 .type = VCAP_FIELD_BIT,2612 .offset = 2,2613 .width = 1,2614 },2615 [VCAP_AF_TAG_A_TPID_SEL] = {2616 .type = VCAP_FIELD_U32,2617 .offset = 3,2618 .width = 2,2619 },2620 [VCAP_AF_TAG_A_VID_SEL] = {2621 .type = VCAP_FIELD_BIT,2622 .offset = 5,2623 .width = 1,2624 },2625 [VCAP_AF_TAG_A_PCP_SEL] = {2626 .type = VCAP_FIELD_U32,2627 .offset = 6,2628 .width = 2,2629 },2630 [VCAP_AF_TAG_A_DEI_SEL] = {2631 .type = VCAP_FIELD_U32,2632 .offset = 8,2633 .width = 2,2634 },2635 [VCAP_AF_TAG_B_TPID_SEL] = {2636 .type = VCAP_FIELD_U32,2637 .offset = 10,2638 .width = 2,2639 },2640 [VCAP_AF_TAG_B_VID_SEL] = {2641 .type = VCAP_FIELD_BIT,2642 .offset = 12,2643 .width = 1,2644 },2645 [VCAP_AF_TAG_B_PCP_SEL] = {2646 .type = VCAP_FIELD_U32,2647 .offset = 13,2648 .width = 2,2649 },2650 [VCAP_AF_TAG_B_DEI_SEL] = {2651 .type = VCAP_FIELD_U32,2652 .offset = 15,2653 .width = 2,2654 },2655 [VCAP_AF_VID_A_VAL] = {2656 .type = VCAP_FIELD_U32,2657 .offset = 17,2658 .width = 12,2659 },2660 [VCAP_AF_PCP_A_VAL] = {2661 .type = VCAP_FIELD_U32,2662 .offset = 29,2663 .width = 3,2664 },2665 [VCAP_AF_DEI_A_VAL] = {2666 .type = VCAP_FIELD_BIT,2667 .offset = 32,2668 .width = 1,2669 },2670 [VCAP_AF_VID_B_VAL] = {2671 .type = VCAP_FIELD_U32,2672 .offset = 33,2673 .width = 12,2674 },2675 [VCAP_AF_PCP_B_VAL] = {2676 .type = VCAP_FIELD_U32,2677 .offset = 45,2678 .width = 3,2679 },2680 [VCAP_AF_DEI_B_VAL] = {2681 .type = VCAP_FIELD_BIT,2682 .offset = 48,2683 .width = 1,2684 },2685 [VCAP_AF_ESDX] = {2686 .type = VCAP_FIELD_U32,2687 .offset = 49,2688 .width = 8,2689 },2690};2691 2692/* actionfield_set */2693static const struct vcap_set is1_actionfield_set[] = {2694 [VCAP_AFS_S1] = {2695 .type_id = 0,2696 .sw_per_item = 1,2697 .sw_cnt = 4,2698 },2699};2700 2701static const struct vcap_set is2_actionfield_set[] = {2702 [VCAP_AFS_BASE_TYPE] = {2703 .type_id = -1,2704 .sw_per_item = 2,2705 .sw_cnt = 2,2706 },2707 [VCAP_AFS_SMAC_SIP] = {2708 .type_id = -1,2709 .sw_per_item = 1,2710 .sw_cnt = 4,2711 },2712};2713 2714static const struct vcap_set es0_actionfield_set[] = {2715 [VCAP_AFS_VID] = {2716 .type_id = -1,2717 .sw_per_item = 1,2718 .sw_cnt = 1,2719 },2720};2721 2722/* actionfield_set map */2723static const struct vcap_field *is1_actionfield_set_map[] = {2724 [VCAP_AFS_S1] = is1_s1_actionfield,2725};2726 2727static const struct vcap_field *is2_actionfield_set_map[] = {2728 [VCAP_AFS_BASE_TYPE] = is2_base_type_actionfield,2729 [VCAP_AFS_SMAC_SIP] = is2_smac_sip_actionfield,2730};2731 2732static const struct vcap_field *es0_actionfield_set_map[] = {2733 [VCAP_AFS_VID] = es0_vid_actionfield,2734};2735 2736/* actionfield_set map size */2737static int is1_actionfield_set_map_size[] = {2738 [VCAP_AFS_S1] = ARRAY_SIZE(is1_s1_actionfield),2739};2740 2741static int is2_actionfield_set_map_size[] = {2742 [VCAP_AFS_BASE_TYPE] = ARRAY_SIZE(is2_base_type_actionfield),2743 [VCAP_AFS_SMAC_SIP] = ARRAY_SIZE(is2_smac_sip_actionfield),2744};2745 2746static int es0_actionfield_set_map_size[] = {2747 [VCAP_AFS_VID] = ARRAY_SIZE(es0_vid_actionfield),2748};2749 2750/* Type Groups */2751static const struct vcap_typegroup is1_x4_keyfield_set_typegroups[] = {2752 {2753 .offset = 0,2754 .width = 3,2755 .value = 4,2756 },2757 {2758 .offset = 96,2759 .width = 1,2760 .value = 0,2761 },2762 {2763 .offset = 192,2764 .width = 2,2765 .value = 0,2766 },2767 {2768 .offset = 288,2769 .width = 1,2770 .value = 0,2771 },2772 {}2773};2774 2775static const struct vcap_typegroup is1_x2_keyfield_set_typegroups[] = {2776 {2777 .offset = 0,2778 .width = 2,2779 .value = 2,2780 },2781 {2782 .offset = 96,2783 .width = 1,2784 .value = 0,2785 },2786 {}2787};2788 2789static const struct vcap_typegroup is1_x1_keyfield_set_typegroups[] = {2790 {2791 .offset = 0,2792 .width = 1,2793 .value = 1,2794 },2795 {}2796};2797 2798static const struct vcap_typegroup is2_x4_keyfield_set_typegroups[] = {2799 {2800 .offset = 0,2801 .width = 3,2802 .value = 4,2803 },2804 {2805 .offset = 96,2806 .width = 1,2807 .value = 0,2808 },2809 {2810 .offset = 192,2811 .width = 2,2812 .value = 0,2813 },2814 {2815 .offset = 288,2816 .width = 1,2817 .value = 0,2818 },2819 {}2820};2821 2822static const struct vcap_typegroup is2_x2_keyfield_set_typegroups[] = {2823 {2824 .offset = 0,2825 .width = 2,2826 .value = 2,2827 },2828 {2829 .offset = 96,2830 .width = 1,2831 .value = 0,2832 },2833 {}2834};2835 2836static const struct vcap_typegroup is2_x1_keyfield_set_typegroups[] = {2837 {2838 .offset = 0,2839 .width = 1,2840 .value = 1,2841 },2842 {}2843};2844 2845static const struct vcap_typegroup es0_x1_keyfield_set_typegroups[] = {2846 {}2847};2848 2849static const struct vcap_typegroup *is1_keyfield_set_typegroups[] = {2850 [4] = is1_x4_keyfield_set_typegroups,2851 [2] = is1_x2_keyfield_set_typegroups,2852 [1] = is1_x1_keyfield_set_typegroups,2853 [5] = NULL,2854};2855 2856static const struct vcap_typegroup *is2_keyfield_set_typegroups[] = {2857 [4] = is2_x4_keyfield_set_typegroups,2858 [2] = is2_x2_keyfield_set_typegroups,2859 [1] = is2_x1_keyfield_set_typegroups,2860 [5] = NULL,2861};2862 2863static const struct vcap_typegroup *es0_keyfield_set_typegroups[] = {2864 [1] = es0_x1_keyfield_set_typegroups,2865 [2] = NULL,2866};2867 2868static const struct vcap_typegroup is1_x1_actionfield_set_typegroups[] = {2869 {}2870};2871 2872static const struct vcap_typegroup is2_x2_actionfield_set_typegroups[] = {2873 {2874 .offset = 0,2875 .width = 2,2876 .value = 2,2877 },2878 {2879 .offset = 31,2880 .width = 1,2881 .value = 0,2882 },2883 {}2884};2885 2886static const struct vcap_typegroup is2_x1_actionfield_set_typegroups[] = {2887 {2888 .offset = 0,2889 .width = 1,2890 .value = 1,2891 },2892 {}2893};2894 2895static const struct vcap_typegroup es0_x1_actionfield_set_typegroups[] = {2896 {}2897};2898 2899static const struct vcap_typegroup *is1_actionfield_set_typegroups[] = {2900 [1] = is1_x1_actionfield_set_typegroups,2901 [5] = NULL,2902};2903 2904static const struct vcap_typegroup *is2_actionfield_set_typegroups[] = {2905 [2] = is2_x2_actionfield_set_typegroups,2906 [1] = is2_x1_actionfield_set_typegroups,2907 [5] = NULL,2908};2909 2910static const struct vcap_typegroup *es0_actionfield_set_typegroups[] = {2911 [1] = es0_x1_actionfield_set_typegroups,2912 [2] = NULL,2913};2914 2915/* Keyfieldset names */2916static const char * const vcap_keyfield_set_names[] = {2917 [VCAP_KFS_NO_VALUE] = "(None)",2918 [VCAP_KFS_5TUPLE_IP4] = "VCAP_KFS_5TUPLE_IP4",2919 [VCAP_KFS_5TUPLE_IP6] = "VCAP_KFS_5TUPLE_IP6",2920 [VCAP_KFS_7TUPLE] = "VCAP_KFS_7TUPLE",2921 [VCAP_KFS_ARP] = "VCAP_KFS_ARP",2922 [VCAP_KFS_DBL_VID] = "VCAP_KFS_DBL_VID",2923 [VCAP_KFS_DMAC_VID] = "VCAP_KFS_DMAC_VID",2924 [VCAP_KFS_ETAG] = "VCAP_KFS_ETAG",2925 [VCAP_KFS_IP4_OTHER] = "VCAP_KFS_IP4_OTHER",2926 [VCAP_KFS_IP4_TCP_UDP] = "VCAP_KFS_IP4_TCP_UDP",2927 [VCAP_KFS_IP4_VID] = "VCAP_KFS_IP4_VID",2928 [VCAP_KFS_IP6_OTHER] = "VCAP_KFS_IP6_OTHER",2929 [VCAP_KFS_IP6_STD] = "VCAP_KFS_IP6_STD",2930 [VCAP_KFS_IP6_TCP_UDP] = "VCAP_KFS_IP6_TCP_UDP",2931 [VCAP_KFS_IP6_VID] = "VCAP_KFS_IP6_VID",2932 [VCAP_KFS_IP_7TUPLE] = "VCAP_KFS_IP_7TUPLE",2933 [VCAP_KFS_ISDX] = "VCAP_KFS_ISDX",2934 [VCAP_KFS_LL_FULL] = "VCAP_KFS_LL_FULL",2935 [VCAP_KFS_MAC_ETYPE] = "VCAP_KFS_MAC_ETYPE",2936 [VCAP_KFS_MAC_LLC] = "VCAP_KFS_MAC_LLC",2937 [VCAP_KFS_MAC_SNAP] = "VCAP_KFS_MAC_SNAP",2938 [VCAP_KFS_NORMAL] = "VCAP_KFS_NORMAL",2939 [VCAP_KFS_NORMAL_5TUPLE_IP4] = "VCAP_KFS_NORMAL_5TUPLE_IP4",2940 [VCAP_KFS_NORMAL_7TUPLE] = "VCAP_KFS_NORMAL_7TUPLE",2941 [VCAP_KFS_NORMAL_IP6] = "VCAP_KFS_NORMAL_IP6",2942 [VCAP_KFS_OAM] = "VCAP_KFS_OAM",2943 [VCAP_KFS_PURE_5TUPLE_IP4] = "VCAP_KFS_PURE_5TUPLE_IP4",2944 [VCAP_KFS_RT] = "VCAP_KFS_RT",2945 [VCAP_KFS_SMAC_SIP4] = "VCAP_KFS_SMAC_SIP4",2946 [VCAP_KFS_SMAC_SIP6] = "VCAP_KFS_SMAC_SIP6",2947 [VCAP_KFS_VID] = "VCAP_KFS_VID",2948};2949 2950/* Actionfieldset names */2951static const char * const vcap_actionfield_set_names[] = {2952 [VCAP_AFS_NO_VALUE] = "(None)",2953 [VCAP_AFS_BASE_TYPE] = "VCAP_AFS_BASE_TYPE",2954 [VCAP_AFS_CLASSIFICATION] = "VCAP_AFS_CLASSIFICATION",2955 [VCAP_AFS_CLASS_REDUCED] = "VCAP_AFS_CLASS_REDUCED",2956 [VCAP_AFS_ES0] = "VCAP_AFS_ES0",2957 [VCAP_AFS_FULL] = "VCAP_AFS_FULL",2958 [VCAP_AFS_S1] = "VCAP_AFS_S1",2959 [VCAP_AFS_SMAC_SIP] = "VCAP_AFS_SMAC_SIP",2960 [VCAP_AFS_VID] = "VCAP_AFS_VID",2961};2962 2963/* Keyfield names */2964static const char * const vcap_keyfield_names[] = {2965 [VCAP_KF_NO_VALUE] = "(None)",2966 [VCAP_KF_8021BR_ECID_BASE] = "8021BR_ECID_BASE",2967 [VCAP_KF_8021BR_ECID_EXT] = "8021BR_ECID_EXT",2968 [VCAP_KF_8021BR_E_TAGGED] = "8021BR_E_TAGGED",2969 [VCAP_KF_8021BR_GRP] = "8021BR_GRP",2970 [VCAP_KF_8021BR_IGR_ECID_BASE] = "8021BR_IGR_ECID_BASE",2971 [VCAP_KF_8021BR_IGR_ECID_EXT] = "8021BR_IGR_ECID_EXT",2972 [VCAP_KF_8021CB_R_TAGGED_IS] = "8021CB_R_TAGGED_IS",2973 [VCAP_KF_8021Q_DEI0] = "8021Q_DEI0",2974 [VCAP_KF_8021Q_DEI1] = "8021Q_DEI1",2975 [VCAP_KF_8021Q_DEI2] = "8021Q_DEI2",2976 [VCAP_KF_8021Q_DEI_CLS] = "8021Q_DEI_CLS",2977 [VCAP_KF_8021Q_PCP0] = "8021Q_PCP0",2978 [VCAP_KF_8021Q_PCP1] = "8021Q_PCP1",2979 [VCAP_KF_8021Q_PCP2] = "8021Q_PCP2",2980 [VCAP_KF_8021Q_PCP_CLS] = "8021Q_PCP_CLS",2981 [VCAP_KF_8021Q_TPID] = "8021Q_TPID",2982 [VCAP_KF_8021Q_TPID0] = "8021Q_TPID0",2983 [VCAP_KF_8021Q_TPID1] = "8021Q_TPID1",2984 [VCAP_KF_8021Q_TPID2] = "8021Q_TPID2",2985 [VCAP_KF_8021Q_VID0] = "8021Q_VID0",2986 [VCAP_KF_8021Q_VID1] = "8021Q_VID1",2987 [VCAP_KF_8021Q_VID2] = "8021Q_VID2",2988 [VCAP_KF_8021Q_VID_CLS] = "8021Q_VID_CLS",2989 [VCAP_KF_8021Q_VLAN_DBL_TAGGED_IS] = "8021Q_VLAN_DBL_TAGGED_IS",2990 [VCAP_KF_8021Q_VLAN_TAGGED_IS] = "8021Q_VLAN_TAGGED_IS",2991 [VCAP_KF_8021Q_VLAN_TAGS] = "8021Q_VLAN_TAGS",2992 [VCAP_KF_ACL_GRP_ID] = "ACL_GRP_ID",2993 [VCAP_KF_ARP_ADDR_SPACE_OK_IS] = "ARP_ADDR_SPACE_OK_IS",2994 [VCAP_KF_ARP_LEN_OK_IS] = "ARP_LEN_OK_IS",2995 [VCAP_KF_ARP_OPCODE] = "ARP_OPCODE",2996 [VCAP_KF_ARP_OPCODE_UNKNOWN_IS] = "ARP_OPCODE_UNKNOWN_IS",2997 [VCAP_KF_ARP_PROTO_SPACE_OK_IS] = "ARP_PROTO_SPACE_OK_IS",2998 [VCAP_KF_ARP_SENDER_MATCH_IS] = "ARP_SENDER_MATCH_IS",2999 [VCAP_KF_ARP_TGT_MATCH_IS] = "ARP_TGT_MATCH_IS",3000 [VCAP_KF_COSID_CLS] = "COSID_CLS",3001 [VCAP_KF_ES0_ISDX_KEY_ENA] = "ES0_ISDX_KEY_ENA",3002 [VCAP_KF_ETYPE] = "ETYPE",3003 [VCAP_KF_ETYPE_LEN_IS] = "ETYPE_LEN_IS",3004 [VCAP_KF_HOST_MATCH] = "HOST_MATCH",3005 [VCAP_KF_IF_EGR_PORT_MASK] = "IF_EGR_PORT_MASK",3006 [VCAP_KF_IF_EGR_PORT_MASK_RNG] = "IF_EGR_PORT_MASK_RNG",3007 [VCAP_KF_IF_EGR_PORT_NO] = "IF_EGR_PORT_NO",3008 [VCAP_KF_IF_IGR_PORT] = "IF_IGR_PORT",3009 [VCAP_KF_IF_IGR_PORT_MASK] = "IF_IGR_PORT_MASK",3010 [VCAP_KF_IF_IGR_PORT_MASK_L3] = "IF_IGR_PORT_MASK_L3",3011 [VCAP_KF_IF_IGR_PORT_MASK_RNG] = "IF_IGR_PORT_MASK_RNG",3012 [VCAP_KF_IF_IGR_PORT_MASK_SEL] = "IF_IGR_PORT_MASK_SEL",3013 [VCAP_KF_IF_IGR_PORT_SEL] = "IF_IGR_PORT_SEL",3014 [VCAP_KF_IP4_IS] = "IP4_IS",3015 [VCAP_KF_IP_MC_IS] = "IP_MC_IS",3016 [VCAP_KF_IP_PAYLOAD_5TUPLE] = "IP_PAYLOAD_5TUPLE",3017 [VCAP_KF_IP_PAYLOAD_S1_IP6] = "IP_PAYLOAD_S1_IP6",3018 [VCAP_KF_IP_SNAP_IS] = "IP_SNAP_IS",3019 [VCAP_KF_ISDX_CLS] = "ISDX_CLS",3020 [VCAP_KF_ISDX_GT0_IS] = "ISDX_GT0_IS",3021 [VCAP_KF_L2_BC_IS] = "L2_BC_IS",3022 [VCAP_KF_L2_DMAC] = "L2_DMAC",3023 [VCAP_KF_L2_FRM_TYPE] = "L2_FRM_TYPE",3024 [VCAP_KF_L2_FWD_IS] = "L2_FWD_IS",3025 [VCAP_KF_L2_LLC] = "L2_LLC",3026 [VCAP_KF_L2_MAC] = "L2_MAC",3027 [VCAP_KF_L2_MC_IS] = "L2_MC_IS",3028 [VCAP_KF_L2_PAYLOAD0] = "L2_PAYLOAD0",3029 [VCAP_KF_L2_PAYLOAD1] = "L2_PAYLOAD1",3030 [VCAP_KF_L2_PAYLOAD2] = "L2_PAYLOAD2",3031 [VCAP_KF_L2_PAYLOAD_ETYPE] = "L2_PAYLOAD_ETYPE",3032 [VCAP_KF_L2_SMAC] = "L2_SMAC",3033 [VCAP_KF_L2_SNAP] = "L2_SNAP",3034 [VCAP_KF_L3_DIP_EQ_SIP_IS] = "L3_DIP_EQ_SIP_IS",3035 [VCAP_KF_L3_DPL_CLS] = "L3_DPL_CLS",3036 [VCAP_KF_L3_DSCP] = "L3_DSCP",3037 [VCAP_KF_L3_DST_IS] = "L3_DST_IS",3038 [VCAP_KF_L3_FRAGMENT] = "L3_FRAGMENT",3039 [VCAP_KF_L3_FRAGMENT_TYPE] = "L3_FRAGMENT_TYPE",3040 [VCAP_KF_L3_FRAG_INVLD_L4_LEN] = "L3_FRAG_INVLD_L4_LEN",3041 [VCAP_KF_L3_FRAG_OFS_GT0] = "L3_FRAG_OFS_GT0",3042 [VCAP_KF_L3_IP4_DIP] = "L3_IP4_DIP",3043 [VCAP_KF_L3_IP4_SIP] = "L3_IP4_SIP",3044 [VCAP_KF_L3_IP6_DIP] = "L3_IP6_DIP",3045 [VCAP_KF_L3_IP6_DIP_MSB] = "L3_IP6_DIP_MSB",3046 [VCAP_KF_L3_IP6_SIP] = "L3_IP6_SIP",3047 [VCAP_KF_L3_IP6_SIP_MSB] = "L3_IP6_SIP_MSB",3048 [VCAP_KF_L3_IP_PROTO] = "L3_IP_PROTO",3049 [VCAP_KF_L3_OPTIONS_IS] = "L3_OPTIONS_IS",3050 [VCAP_KF_L3_PAYLOAD] = "L3_PAYLOAD",3051 [VCAP_KF_L3_RT_IS] = "L3_RT_IS",3052 [VCAP_KF_L3_TOS] = "L3_TOS",3053 [VCAP_KF_L3_TTL_GT0] = "L3_TTL_GT0",3054 [VCAP_KF_L4_1588_DOM] = "L4_1588_DOM",3055 [VCAP_KF_L4_1588_VER] = "L4_1588_VER",3056 [VCAP_KF_L4_ACK] = "L4_ACK",3057 [VCAP_KF_L4_DPORT] = "L4_DPORT",3058 [VCAP_KF_L4_FIN] = "L4_FIN",3059 [VCAP_KF_L4_PAYLOAD] = "L4_PAYLOAD",3060 [VCAP_KF_L4_PSH] = "L4_PSH",3061 [VCAP_KF_L4_RNG] = "L4_RNG",3062 [VCAP_KF_L4_RST] = "L4_RST",3063 [VCAP_KF_L4_SEQUENCE_EQ0_IS] = "L4_SEQUENCE_EQ0_IS",3064 [VCAP_KF_L4_SPORT] = "L4_SPORT",3065 [VCAP_KF_L4_SPORT_EQ_DPORT_IS] = "L4_SPORT_EQ_DPORT_IS",3066 [VCAP_KF_L4_SYN] = "L4_SYN",3067 [VCAP_KF_L4_URG] = "L4_URG",3068 [VCAP_KF_LOOKUP_FIRST_IS] = "LOOKUP_FIRST_IS",3069 [VCAP_KF_LOOKUP_GEN_IDX] = "LOOKUP_GEN_IDX",3070 [VCAP_KF_LOOKUP_GEN_IDX_SEL] = "LOOKUP_GEN_IDX_SEL",3071 [VCAP_KF_LOOKUP_INDEX] = "LOOKUP_INDEX",3072 [VCAP_KF_LOOKUP_PAG] = "LOOKUP_PAG",3073 [VCAP_KF_MIRROR_PROBE] = "MIRROR_PROBE",3074 [VCAP_KF_OAM_CCM_CNTS_EQ0] = "OAM_CCM_CNTS_EQ0",3075 [VCAP_KF_OAM_DETECTED] = "OAM_DETECTED",3076 [VCAP_KF_OAM_FLAGS] = "OAM_FLAGS",3077 [VCAP_KF_OAM_MEL_FLAGS] = "OAM_MEL_FLAGS",3078 [VCAP_KF_OAM_MEPID] = "OAM_MEPID",3079 [VCAP_KF_OAM_OPCODE] = "OAM_OPCODE",3080 [VCAP_KF_OAM_VER] = "OAM_VER",3081 [VCAP_KF_OAM_Y1731_IS] = "OAM_Y1731_IS",3082 [VCAP_KF_PDU_TYPE] = "PDU_TYPE",3083 [VCAP_KF_PROT_ACTIVE] = "PROT_ACTIVE",3084 [VCAP_KF_RTP_ID] = "RTP_ID",3085 [VCAP_KF_RT_FRMID] = "RT_FRMID",3086 [VCAP_KF_RT_TYPE] = "RT_TYPE",3087 [VCAP_KF_RT_VLAN_IDX] = "RT_VLAN_IDX",3088 [VCAP_KF_TCP_IS] = "TCP_IS",3089 [VCAP_KF_TCP_UDP_IS] = "TCP_UDP_IS",3090 [VCAP_KF_TYPE] = "TYPE",3091};3092 3093/* Actionfield names */3094static const char * const vcap_actionfield_names[] = {3095 [VCAP_AF_NO_VALUE] = "(None)",3096 [VCAP_AF_ACL_ID] = "ACL_ID",3097 [VCAP_AF_CLS_VID_SEL] = "CLS_VID_SEL",3098 [VCAP_AF_CNT_ID] = "CNT_ID",3099 [VCAP_AF_COPY_PORT_NUM] = "COPY_PORT_NUM",3100 [VCAP_AF_COPY_QUEUE_NUM] = "COPY_QUEUE_NUM",3101 [VCAP_AF_CPU_COPY_ENA] = "CPU_COPY_ENA",3102 [VCAP_AF_CPU_QU] = "CPU_QU",3103 [VCAP_AF_CPU_QUEUE_NUM] = "CPU_QUEUE_NUM",3104 [VCAP_AF_CUSTOM_ACE_TYPE_ENA] = "CUSTOM_ACE_TYPE_ENA",3105 [VCAP_AF_DEI_A_VAL] = "DEI_A_VAL",3106 [VCAP_AF_DEI_B_VAL] = "DEI_B_VAL",3107 [VCAP_AF_DEI_C_VAL] = "DEI_C_VAL",3108 [VCAP_AF_DEI_ENA] = "DEI_ENA",3109 [VCAP_AF_DEI_VAL] = "DEI_VAL",3110 [VCAP_AF_DLR_SEL] = "DLR_SEL",3111 [VCAP_AF_DP_ENA] = "DP_ENA",3112 [VCAP_AF_DP_VAL] = "DP_VAL",3113 [VCAP_AF_DSCP_ENA] = "DSCP_ENA",3114 [VCAP_AF_DSCP_SEL] = "DSCP_SEL",3115 [VCAP_AF_DSCP_VAL] = "DSCP_VAL",3116 [VCAP_AF_ES2_REW_CMD] = "ES2_REW_CMD",3117 [VCAP_AF_ESDX] = "ESDX",3118 [VCAP_AF_FWD_KILL_ENA] = "FWD_KILL_ENA",3119 [VCAP_AF_FWD_MODE] = "FWD_MODE",3120 [VCAP_AF_FWD_SEL] = "FWD_SEL",3121 [VCAP_AF_HIT_ME_ONCE] = "HIT_ME_ONCE",3122 [VCAP_AF_HOST_MATCH] = "HOST_MATCH",3123 [VCAP_AF_IGNORE_PIPELINE_CTRL] = "IGNORE_PIPELINE_CTRL",3124 [VCAP_AF_INTR_ENA] = "INTR_ENA",3125 [VCAP_AF_ISDX_ADD_REPLACE_SEL] = "ISDX_ADD_REPLACE_SEL",3126 [VCAP_AF_ISDX_ADD_VAL] = "ISDX_ADD_VAL",3127 [VCAP_AF_ISDX_ENA] = "ISDX_ENA",3128 [VCAP_AF_ISDX_REPLACE_ENA] = "ISDX_REPLACE_ENA",3129 [VCAP_AF_ISDX_VAL] = "ISDX_VAL",3130 [VCAP_AF_LOOP_ENA] = "LOOP_ENA",3131 [VCAP_AF_LRN_DIS] = "LRN_DIS",3132 [VCAP_AF_MAP_IDX] = "MAP_IDX",3133 [VCAP_AF_MAP_KEY] = "MAP_KEY",3134 [VCAP_AF_MAP_LOOKUP_SEL] = "MAP_LOOKUP_SEL",3135 [VCAP_AF_MASK_MODE] = "MASK_MODE",3136 [VCAP_AF_MATCH_ID] = "MATCH_ID",3137 [VCAP_AF_MATCH_ID_MASK] = "MATCH_ID_MASK",3138 [VCAP_AF_MIRROR_ENA] = "MIRROR_ENA",3139 [VCAP_AF_MIRROR_PROBE] = "MIRROR_PROBE",3140 [VCAP_AF_MIRROR_PROBE_ID] = "MIRROR_PROBE_ID",3141 [VCAP_AF_MRP_SEL] = "MRP_SEL",3142 [VCAP_AF_NXT_IDX] = "NXT_IDX",3143 [VCAP_AF_NXT_IDX_CTRL] = "NXT_IDX_CTRL",3144 [VCAP_AF_OAM_SEL] = "OAM_SEL",3145 [VCAP_AF_PAG_OVERRIDE_MASK] = "PAG_OVERRIDE_MASK",3146 [VCAP_AF_PAG_VAL] = "PAG_VAL",3147 [VCAP_AF_PCP_A_VAL] = "PCP_A_VAL",3148 [VCAP_AF_PCP_B_VAL] = "PCP_B_VAL",3149 [VCAP_AF_PCP_C_VAL] = "PCP_C_VAL",3150 [VCAP_AF_PCP_ENA] = "PCP_ENA",3151 [VCAP_AF_PCP_VAL] = "PCP_VAL",3152 [VCAP_AF_PIPELINE_ACT] = "PIPELINE_ACT",3153 [VCAP_AF_PIPELINE_FORCE_ENA] = "PIPELINE_FORCE_ENA",3154 [VCAP_AF_PIPELINE_PT] = "PIPELINE_PT",3155 [VCAP_AF_POLICE_ENA] = "POLICE_ENA",3156 [VCAP_AF_POLICE_IDX] = "POLICE_IDX",3157 [VCAP_AF_POLICE_REMARK] = "POLICE_REMARK",3158 [VCAP_AF_POLICE_VCAP_ONLY] = "POLICE_VCAP_ONLY",3159 [VCAP_AF_POP_VAL] = "POP_VAL",3160 [VCAP_AF_PORT_MASK] = "PORT_MASK",3161 [VCAP_AF_PUSH_CUSTOMER_TAG] = "PUSH_CUSTOMER_TAG",3162 [VCAP_AF_PUSH_INNER_TAG] = "PUSH_INNER_TAG",3163 [VCAP_AF_PUSH_OUTER_TAG] = "PUSH_OUTER_TAG",3164 [VCAP_AF_QOS_ENA] = "QOS_ENA",3165 [VCAP_AF_QOS_VAL] = "QOS_VAL",3166 [VCAP_AF_REW_OP] = "REW_OP",3167 [VCAP_AF_RT_DIS] = "RT_DIS",3168 [VCAP_AF_SFID_ENA] = "SFID_ENA",3169 [VCAP_AF_SFID_VAL] = "SFID_VAL",3170 [VCAP_AF_SGID_ENA] = "SGID_ENA",3171 [VCAP_AF_SGID_VAL] = "SGID_VAL",3172 [VCAP_AF_SWAP_MACS_ENA] = "SWAP_MACS_ENA",3173 [VCAP_AF_TAG_A_DEI_SEL] = "TAG_A_DEI_SEL",3174 [VCAP_AF_TAG_A_PCP_SEL] = "TAG_A_PCP_SEL",3175 [VCAP_AF_TAG_A_TPID_SEL] = "TAG_A_TPID_SEL",3176 [VCAP_AF_TAG_A_VID_SEL] = "TAG_A_VID_SEL",3177 [VCAP_AF_TAG_B_DEI_SEL] = "TAG_B_DEI_SEL",3178 [VCAP_AF_TAG_B_PCP_SEL] = "TAG_B_PCP_SEL",3179 [VCAP_AF_TAG_B_TPID_SEL] = "TAG_B_TPID_SEL",3180 [VCAP_AF_TAG_B_VID_SEL] = "TAG_B_VID_SEL",3181 [VCAP_AF_TAG_C_DEI_SEL] = "TAG_C_DEI_SEL",3182 [VCAP_AF_TAG_C_PCP_SEL] = "TAG_C_PCP_SEL",3183 [VCAP_AF_TAG_C_TPID_SEL] = "TAG_C_TPID_SEL",3184 [VCAP_AF_TAG_C_VID_SEL] = "TAG_C_VID_SEL",3185 [VCAP_AF_TYPE] = "TYPE",3186 [VCAP_AF_UNTAG_VID_ENA] = "UNTAG_VID_ENA",3187 [VCAP_AF_VID_A_VAL] = "VID_A_VAL",3188 [VCAP_AF_VID_B_VAL] = "VID_B_VAL",3189 [VCAP_AF_VID_C_VAL] = "VID_C_VAL",3190 [VCAP_AF_VID_REPLACE_ENA] = "VID_REPLACE_ENA",3191 [VCAP_AF_VID_VAL] = "VID_VAL",3192 [VCAP_AF_VLAN_POP_CNT] = "VLAN_POP_CNT",3193 [VCAP_AF_VLAN_POP_CNT_ENA] = "VLAN_POP_CNT_ENA",3194};3195 3196/* VCAPs */3197const struct vcap_info lan966x_vcaps[] = {3198 [VCAP_TYPE_IS1] = {3199 .name = "is1",3200 .rows = 192,3201 .sw_count = 4,3202 .sw_width = 96,3203 .sticky_width = 32,3204 .act_width = 123,3205 .default_cnt = 0,3206 .require_cnt_dis = 1,3207 .version = 1,3208 .keyfield_set = is1_keyfield_set,3209 .keyfield_set_size = ARRAY_SIZE(is1_keyfield_set),3210 .actionfield_set = is1_actionfield_set,3211 .actionfield_set_size = ARRAY_SIZE(is1_actionfield_set),3212 .keyfield_set_map = is1_keyfield_set_map,3213 .keyfield_set_map_size = is1_keyfield_set_map_size,3214 .actionfield_set_map = is1_actionfield_set_map,3215 .actionfield_set_map_size = is1_actionfield_set_map_size,3216 .keyfield_set_typegroups = is1_keyfield_set_typegroups,3217 .actionfield_set_typegroups = is1_actionfield_set_typegroups,3218 },3219 [VCAP_TYPE_IS2] = {3220 .name = "is2",3221 .rows = 64,3222 .sw_count = 4,3223 .sw_width = 96,3224 .sticky_width = 32,3225 .act_width = 31,3226 .default_cnt = 11,3227 .require_cnt_dis = 1,3228 .version = 1,3229 .keyfield_set = is2_keyfield_set,3230 .keyfield_set_size = ARRAY_SIZE(is2_keyfield_set),3231 .actionfield_set = is2_actionfield_set,3232 .actionfield_set_size = ARRAY_SIZE(is2_actionfield_set),3233 .keyfield_set_map = is2_keyfield_set_map,3234 .keyfield_set_map_size = is2_keyfield_set_map_size,3235 .actionfield_set_map = is2_actionfield_set_map,3236 .actionfield_set_map_size = is2_actionfield_set_map_size,3237 .keyfield_set_typegroups = is2_keyfield_set_typegroups,3238 .actionfield_set_typegroups = is2_actionfield_set_typegroups,3239 },3240 [VCAP_TYPE_ES0] = {3241 .name = "es0",3242 .rows = 256,3243 .sw_count = 1,3244 .sw_width = 96,3245 .sticky_width = 1,3246 .act_width = 65,3247 .default_cnt = 8,3248 .require_cnt_dis = 0,3249 .version = 1,3250 .keyfield_set = es0_keyfield_set,3251 .keyfield_set_size = ARRAY_SIZE(es0_keyfield_set),3252 .actionfield_set = es0_actionfield_set,3253 .actionfield_set_size = ARRAY_SIZE(es0_actionfield_set),3254 .keyfield_set_map = es0_keyfield_set_map,3255 .keyfield_set_map_size = es0_keyfield_set_map_size,3256 .actionfield_set_map = es0_actionfield_set_map,3257 .actionfield_set_map_size = es0_actionfield_set_map_size,3258 .keyfield_set_typegroups = es0_keyfield_set_typegroups,3259 .actionfield_set_typegroups = es0_actionfield_set_typegroups,3260 },3261};3262 3263const struct vcap_statistics lan966x_vcap_stats = {3264 .name = "lan966x",3265 .count = 3,3266 .keyfield_set_names = vcap_keyfield_set_names,3267 .actionfield_set_names = vcap_actionfield_set_names,3268 .keyfield_names = vcap_keyfield_names,3269 .actionfield_names = vcap_actionfield_names,3270};3271