brintos / linux-shallow public Read only

1// SPDX-License-Identifier: BSD-3-Clause2/* Copyright (C) 2023 Microchip Technology Inc. and its subsidiaries.3 * Microchip VCAP API4 */5 6/* This file is autogenerated by cml-utils 2023-02-10 11:15:56 +0100.7 * Commit ID: c30fb4bf0281cd4a7133bdab6682f9e43c872ada8 */9 10#include <linux/types.h>11#include <linux/kernel.h>12 13#include "vcap_api.h"14#include "sparx5_vcap_ag_api.h"15 16/* keyfields */17static const struct vcap_field is0_normal_7tuple_keyfield[] = {18	[VCAP_KF_TYPE] = {19		.type = VCAP_FIELD_BIT,20		.offset = 0,21		.width = 1,22	},23	[VCAP_KF_LOOKUP_FIRST_IS] = {24		.type = VCAP_FIELD_BIT,25		.offset = 1,26		.width = 1,27	},28	[VCAP_KF_LOOKUP_GEN_IDX_SEL] = {29		.type = VCAP_FIELD_U32,30		.offset = 2,31		.width = 2,32	},33	[VCAP_KF_LOOKUP_GEN_IDX] = {34		.type = VCAP_FIELD_U32,35		.offset = 4,36		.width = 12,37	},38	[VCAP_KF_IF_IGR_PORT_MASK_SEL] = {39		.type = VCAP_FIELD_U32,40		.offset = 16,41		.width = 2,42	},43	[VCAP_KF_IF_IGR_PORT_MASK] = {44		.type = VCAP_FIELD_U72,45		.offset = 18,46		.width = 65,47	},48	[VCAP_KF_L2_MC_IS] = {49		.type = VCAP_FIELD_BIT,50		.offset = 83,51		.width = 1,52	},53	[VCAP_KF_L2_BC_IS] = {54		.type = VCAP_FIELD_BIT,55		.offset = 84,56		.width = 1,57	},58	[VCAP_KF_8021Q_VLAN_TAGS] = {59		.type = VCAP_FIELD_U32,60		.offset = 85,61		.width = 3,62	},63	[VCAP_KF_8021Q_TPID0] = {64		.type = VCAP_FIELD_U32,65		.offset = 88,66		.width = 3,67	},68	[VCAP_KF_8021Q_PCP0] = {69		.type = VCAP_FIELD_U32,70		.offset = 91,71		.width = 3,72	},73	[VCAP_KF_8021Q_DEI0] = {74		.type = VCAP_FIELD_BIT,75		.offset = 94,76		.width = 1,77	},78	[VCAP_KF_8021Q_VID0] = {79		.type = VCAP_FIELD_U32,80		.offset = 95,81		.width = 12,82	},83	[VCAP_KF_8021Q_TPID1] = {84		.type = VCAP_FIELD_U32,85		.offset = 107,86		.width = 3,87	},88	[VCAP_KF_8021Q_PCP1] = {89		.type = VCAP_FIELD_U32,90		.offset = 110,91		.width = 3,92	},93	[VCAP_KF_8021Q_DEI1] = {94		.type = VCAP_FIELD_BIT,95		.offset = 113,96		.width = 1,97	},98	[VCAP_KF_8021Q_VID1] = {99		.type = VCAP_FIELD_U32,100		.offset = 114,101		.width = 12,102	},103	[VCAP_KF_8021Q_TPID2] = {104		.type = VCAP_FIELD_U32,105		.offset = 126,106		.width = 3,107	},108	[VCAP_KF_8021Q_PCP2] = {109		.type = VCAP_FIELD_U32,110		.offset = 129,111		.width = 3,112	},113	[VCAP_KF_8021Q_DEI2] = {114		.type = VCAP_FIELD_BIT,115		.offset = 132,116		.width = 1,117	},118	[VCAP_KF_8021Q_VID2] = {119		.type = VCAP_FIELD_U32,120		.offset = 133,121		.width = 12,122	},123	[VCAP_KF_L2_DMAC] = {124		.type = VCAP_FIELD_U48,125		.offset = 145,126		.width = 48,127	},128	[VCAP_KF_L2_SMAC] = {129		.type = VCAP_FIELD_U48,130		.offset = 193,131		.width = 48,132	},133	[VCAP_KF_IP_MC_IS] = {134		.type = VCAP_FIELD_BIT,135		.offset = 241,136		.width = 1,137	},138	[VCAP_KF_ETYPE_LEN_IS] = {139		.type = VCAP_FIELD_BIT,140		.offset = 242,141		.width = 1,142	},143	[VCAP_KF_ETYPE] = {144		.type = VCAP_FIELD_U32,145		.offset = 243,146		.width = 16,147	},148	[VCAP_KF_IP_SNAP_IS] = {149		.type = VCAP_FIELD_BIT,150		.offset = 259,151		.width = 1,152	},153	[VCAP_KF_IP4_IS] = {154		.type = VCAP_FIELD_BIT,155		.offset = 260,156		.width = 1,157	},158	[VCAP_KF_L3_FRAGMENT_TYPE] = {159		.type = VCAP_FIELD_U32,160		.offset = 261,161		.width = 2,162	},163	[VCAP_KF_L3_FRAG_INVLD_L4_LEN] = {164		.type = VCAP_FIELD_BIT,165		.offset = 263,166		.width = 1,167	},168	[VCAP_KF_L3_OPTIONS_IS] = {169		.type = VCAP_FIELD_BIT,170		.offset = 264,171		.width = 1,172	},173	[VCAP_KF_L3_DSCP] = {174		.type = VCAP_FIELD_U32,175		.offset = 265,176		.width = 6,177	},178	[VCAP_KF_L3_IP6_DIP] = {179		.type = VCAP_FIELD_U128,180		.offset = 271,181		.width = 128,182	},183	[VCAP_KF_L3_IP6_SIP] = {184		.type = VCAP_FIELD_U128,185		.offset = 399,186		.width = 128,187	},188	[VCAP_KF_TCP_UDP_IS] = {189		.type = VCAP_FIELD_BIT,190		.offset = 527,191		.width = 1,192	},193	[VCAP_KF_TCP_IS] = {194		.type = VCAP_FIELD_BIT,195		.offset = 528,196		.width = 1,197	},198	[VCAP_KF_L4_SPORT] = {199		.type = VCAP_FIELD_U32,200		.offset = 529,201		.width = 16,202	},203	[VCAP_KF_L4_RNG] = {204		.type = VCAP_FIELD_U32,205		.offset = 545,206		.width = 8,207	},208};209 210static const struct vcap_field is0_normal_5tuple_ip4_keyfield[] = {211	[VCAP_KF_TYPE] = {212		.type = VCAP_FIELD_U32,213		.offset = 0,214		.width = 2,215	},216	[VCAP_KF_LOOKUP_FIRST_IS] = {217		.type = VCAP_FIELD_BIT,218		.offset = 2,219		.width = 1,220	},221	[VCAP_KF_LOOKUP_GEN_IDX_SEL] = {222		.type = VCAP_FIELD_U32,223		.offset = 3,224		.width = 2,225	},226	[VCAP_KF_LOOKUP_GEN_IDX] = {227		.type = VCAP_FIELD_U32,228		.offset = 5,229		.width = 12,230	},231	[VCAP_KF_IF_IGR_PORT_MASK_SEL] = {232		.type = VCAP_FIELD_U32,233		.offset = 17,234		.width = 2,235	},236	[VCAP_KF_IF_IGR_PORT_MASK] = {237		.type = VCAP_FIELD_U72,238		.offset = 19,239		.width = 65,240	},241	[VCAP_KF_L2_MC_IS] = {242		.type = VCAP_FIELD_BIT,243		.offset = 84,244		.width = 1,245	},246	[VCAP_KF_L2_BC_IS] = {247		.type = VCAP_FIELD_BIT,248		.offset = 85,249		.width = 1,250	},251	[VCAP_KF_8021Q_VLAN_TAGS] = {252		.type = VCAP_FIELD_U32,253		.offset = 86,254		.width = 3,255	},256	[VCAP_KF_8021Q_TPID0] = {257		.type = VCAP_FIELD_U32,258		.offset = 89,259		.width = 3,260	},261	[VCAP_KF_8021Q_PCP0] = {262		.type = VCAP_FIELD_U32,263		.offset = 92,264		.width = 3,265	},266	[VCAP_KF_8021Q_DEI0] = {267		.type = VCAP_FIELD_BIT,268		.offset = 95,269		.width = 1,270	},271	[VCAP_KF_8021Q_VID0] = {272		.type = VCAP_FIELD_U32,273		.offset = 96,274		.width = 12,275	},276	[VCAP_KF_8021Q_TPID1] = {277		.type = VCAP_FIELD_U32,278		.offset = 108,279		.width = 3,280	},281	[VCAP_KF_8021Q_PCP1] = {282		.type = VCAP_FIELD_U32,283		.offset = 111,284		.width = 3,285	},286	[VCAP_KF_8021Q_DEI1] = {287		.type = VCAP_FIELD_BIT,288		.offset = 114,289		.width = 1,290	},291	[VCAP_KF_8021Q_VID1] = {292		.type = VCAP_FIELD_U32,293		.offset = 115,294		.width = 12,295	},296	[VCAP_KF_8021Q_TPID2] = {297		.type = VCAP_FIELD_U32,298		.offset = 127,299		.width = 3,300	},301	[VCAP_KF_8021Q_PCP2] = {302		.type = VCAP_FIELD_U32,303		.offset = 130,304		.width = 3,305	},306	[VCAP_KF_8021Q_DEI2] = {307		.type = VCAP_FIELD_BIT,308		.offset = 133,309		.width = 1,310	},311	[VCAP_KF_8021Q_VID2] = {312		.type = VCAP_FIELD_U32,313		.offset = 134,314		.width = 12,315	},316	[VCAP_KF_IP_MC_IS] = {317		.type = VCAP_FIELD_BIT,318		.offset = 146,319		.width = 1,320	},321	[VCAP_KF_IP4_IS] = {322		.type = VCAP_FIELD_BIT,323		.offset = 147,324		.width = 1,325	},326	[VCAP_KF_L3_FRAGMENT_TYPE] = {327		.type = VCAP_FIELD_U32,328		.offset = 148,329		.width = 2,330	},331	[VCAP_KF_L3_FRAG_INVLD_L4_LEN] = {332		.type = VCAP_FIELD_BIT,333		.offset = 150,334		.width = 1,335	},336	[VCAP_KF_L3_OPTIONS_IS] = {337		.type = VCAP_FIELD_BIT,338		.offset = 151,339		.width = 1,340	},341	[VCAP_KF_L3_DSCP] = {342		.type = VCAP_FIELD_U32,343		.offset = 152,344		.width = 6,345	},346	[VCAP_KF_L3_IP4_DIP] = {347		.type = VCAP_FIELD_U32,348		.offset = 158,349		.width = 32,350	},351	[VCAP_KF_L3_IP4_SIP] = {352		.type = VCAP_FIELD_U32,353		.offset = 190,354		.width = 32,355	},356	[VCAP_KF_L3_IP_PROTO] = {357		.type = VCAP_FIELD_U32,358		.offset = 222,359		.width = 8,360	},361	[VCAP_KF_TCP_UDP_IS] = {362		.type = VCAP_FIELD_BIT,363		.offset = 230,364		.width = 1,365	},366	[VCAP_KF_TCP_IS] = {367		.type = VCAP_FIELD_BIT,368		.offset = 231,369		.width = 1,370	},371	[VCAP_KF_L4_RNG] = {372		.type = VCAP_FIELD_U32,373		.offset = 232,374		.width = 8,375	},376	[VCAP_KF_IP_PAYLOAD_5TUPLE] = {377		.type = VCAP_FIELD_U32,378		.offset = 240,379		.width = 32,380	},381};382 383static const struct vcap_field is2_mac_etype_keyfield[] = {384	[VCAP_KF_TYPE] = {385		.type = VCAP_FIELD_U32,386		.offset = 0,387		.width = 4,388	},389	[VCAP_KF_LOOKUP_FIRST_IS] = {390		.type = VCAP_FIELD_BIT,391		.offset = 4,392		.width = 1,393	},394	[VCAP_KF_LOOKUP_PAG] = {395		.type = VCAP_FIELD_U32,396		.offset = 5,397		.width = 8,398	},399	[VCAP_KF_IF_IGR_PORT_MASK_L3] = {400		.type = VCAP_FIELD_BIT,401		.offset = 13,402		.width = 1,403	},404	[VCAP_KF_IF_IGR_PORT_MASK_RNG] = {405		.type = VCAP_FIELD_U32,406		.offset = 14,407		.width = 4,408	},409	[VCAP_KF_IF_IGR_PORT_MASK_SEL] = {410		.type = VCAP_FIELD_U32,411		.offset = 18,412		.width = 2,413	},414	[VCAP_KF_IF_IGR_PORT_MASK] = {415		.type = VCAP_FIELD_U32,416		.offset = 20,417		.width = 32,418	},419	[VCAP_KF_L2_MC_IS] = {420		.type = VCAP_FIELD_BIT,421		.offset = 52,422		.width = 1,423	},424	[VCAP_KF_L2_BC_IS] = {425		.type = VCAP_FIELD_BIT,426		.offset = 53,427		.width = 1,428	},429	[VCAP_KF_8021Q_VLAN_TAGGED_IS] = {430		.type = VCAP_FIELD_BIT,431		.offset = 54,432		.width = 1,433	},434	[VCAP_KF_ISDX_GT0_IS] = {435		.type = VCAP_FIELD_BIT,436		.offset = 55,437		.width = 1,438	},439	[VCAP_KF_ISDX_CLS] = {440		.type = VCAP_FIELD_U32,441		.offset = 56,442		.width = 12,443	},444	[VCAP_KF_8021Q_VID_CLS] = {445		.type = VCAP_FIELD_U32,446		.offset = 68,447		.width = 13,448	},449	[VCAP_KF_8021Q_DEI_CLS] = {450		.type = VCAP_FIELD_BIT,451		.offset = 81,452		.width = 1,453	},454	[VCAP_KF_8021Q_PCP_CLS] = {455		.type = VCAP_FIELD_U32,456		.offset = 82,457		.width = 3,458	},459	[VCAP_KF_L2_FWD_IS] = {460		.type = VCAP_FIELD_BIT,461		.offset = 85,462		.width = 1,463	},464	[VCAP_KF_L3_RT_IS] = {465		.type = VCAP_FIELD_BIT,466		.offset = 88,467		.width = 1,468	},469	[VCAP_KF_L3_DST_IS] = {470		.type = VCAP_FIELD_BIT,471		.offset = 89,472		.width = 1,473	},474	[VCAP_KF_L2_DMAC] = {475		.type = VCAP_FIELD_U48,476		.offset = 90,477		.width = 48,478	},479	[VCAP_KF_L2_SMAC] = {480		.type = VCAP_FIELD_U48,481		.offset = 138,482		.width = 48,483	},484	[VCAP_KF_ETYPE_LEN_IS] = {485		.type = VCAP_FIELD_BIT,486		.offset = 186,487		.width = 1,488	},489	[VCAP_KF_ETYPE] = {490		.type = VCAP_FIELD_U32,491		.offset = 187,492		.width = 16,493	},494	[VCAP_KF_L2_PAYLOAD_ETYPE] = {495		.type = VCAP_FIELD_U64,496		.offset = 203,497		.width = 64,498	},499	[VCAP_KF_L4_RNG] = {500		.type = VCAP_FIELD_U32,501		.offset = 267,502		.width = 16,503	},504	[VCAP_KF_OAM_CCM_CNTS_EQ0] = {505		.type = VCAP_FIELD_BIT,506		.offset = 283,507		.width = 1,508	},509	[VCAP_KF_OAM_Y1731_IS] = {510		.type = VCAP_FIELD_BIT,511		.offset = 284,512		.width = 1,513	},514};515 516static const struct vcap_field is2_arp_keyfield[] = {517	[VCAP_KF_TYPE] = {518		.type = VCAP_FIELD_U32,519		.offset = 0,520		.width = 4,521	},522	[VCAP_KF_LOOKUP_FIRST_IS] = {523		.type = VCAP_FIELD_BIT,524		.offset = 4,525		.width = 1,526	},527	[VCAP_KF_LOOKUP_PAG] = {528		.type = VCAP_FIELD_U32,529		.offset = 5,530		.width = 8,531	},532	[VCAP_KF_IF_IGR_PORT_MASK_L3] = {533		.type = VCAP_FIELD_BIT,534		.offset = 13,535		.width = 1,536	},537	[VCAP_KF_IF_IGR_PORT_MASK_RNG] = {538		.type = VCAP_FIELD_U32,539		.offset = 14,540		.width = 4,541	},542	[VCAP_KF_IF_IGR_PORT_MASK_SEL] = {543		.type = VCAP_FIELD_U32,544		.offset = 18,545		.width = 2,546	},547	[VCAP_KF_IF_IGR_PORT_MASK] = {548		.type = VCAP_FIELD_U32,549		.offset = 20,550		.width = 32,551	},552	[VCAP_KF_L2_MC_IS] = {553		.type = VCAP_FIELD_BIT,554		.offset = 52,555		.width = 1,556	},557	[VCAP_KF_L2_BC_IS] = {558		.type = VCAP_FIELD_BIT,559		.offset = 53,560		.width = 1,561	},562	[VCAP_KF_8021Q_VLAN_TAGGED_IS] = {563		.type = VCAP_FIELD_BIT,564		.offset = 54,565		.width = 1,566	},567	[VCAP_KF_ISDX_GT0_IS] = {568		.type = VCAP_FIELD_BIT,569		.offset = 55,570		.width = 1,571	},572	[VCAP_KF_ISDX_CLS] = {573		.type = VCAP_FIELD_U32,574		.offset = 56,575		.width = 12,576	},577	[VCAP_KF_8021Q_VID_CLS] = {578		.type = VCAP_FIELD_U32,579		.offset = 68,580		.width = 13,581	},582	[VCAP_KF_8021Q_DEI_CLS] = {583		.type = VCAP_FIELD_BIT,584		.offset = 81,585		.width = 1,586	},587	[VCAP_KF_8021Q_PCP_CLS] = {588		.type = VCAP_FIELD_U32,589		.offset = 82,590		.width = 3,591	},592	[VCAP_KF_L2_FWD_IS] = {593		.type = VCAP_FIELD_BIT,594		.offset = 85,595		.width = 1,596	},597	[VCAP_KF_L2_SMAC] = {598		.type = VCAP_FIELD_U48,599		.offset = 86,600		.width = 48,601	},602	[VCAP_KF_ARP_ADDR_SPACE_OK_IS] = {603		.type = VCAP_FIELD_BIT,604		.offset = 134,605		.width = 1,606	},607	[VCAP_KF_ARP_PROTO_SPACE_OK_IS] = {608		.type = VCAP_FIELD_BIT,609		.offset = 135,610		.width = 1,611	},612	[VCAP_KF_ARP_LEN_OK_IS] = {613		.type = VCAP_FIELD_BIT,614		.offset = 136,615		.width = 1,616	},617	[VCAP_KF_ARP_TGT_MATCH_IS] = {618		.type = VCAP_FIELD_BIT,619		.offset = 137,620		.width = 1,621	},622	[VCAP_KF_ARP_SENDER_MATCH_IS] = {623		.type = VCAP_FIELD_BIT,624		.offset = 138,625		.width = 1,626	},627	[VCAP_KF_ARP_OPCODE_UNKNOWN_IS] = {628		.type = VCAP_FIELD_BIT,629		.offset = 139,630		.width = 1,631	},632	[VCAP_KF_ARP_OPCODE] = {633		.type = VCAP_FIELD_U32,634		.offset = 140,635		.width = 2,636	},637	[VCAP_KF_L3_IP4_DIP] = {638		.type = VCAP_FIELD_U32,639		.offset = 142,640		.width = 32,641	},642	[VCAP_KF_L3_IP4_SIP] = {643		.type = VCAP_FIELD_U32,644		.offset = 174,645		.width = 32,646	},647	[VCAP_KF_L3_DIP_EQ_SIP_IS] = {648		.type = VCAP_FIELD_BIT,649		.offset = 206,650		.width = 1,651	},652	[VCAP_KF_L4_RNG] = {653		.type = VCAP_FIELD_U32,654		.offset = 207,655		.width = 16,656	},657};658 659static const struct vcap_field is2_ip4_tcp_udp_keyfield[] = {660	[VCAP_KF_TYPE] = {661		.type = VCAP_FIELD_U32,662		.offset = 0,663		.width = 4,664	},665	[VCAP_KF_LOOKUP_FIRST_IS] = {666		.type = VCAP_FIELD_BIT,667		.offset = 4,668		.width = 1,669	},670	[VCAP_KF_LOOKUP_PAG] = {671		.type = VCAP_FIELD_U32,672		.offset = 5,673		.width = 8,674	},675	[VCAP_KF_IF_IGR_PORT_MASK_L3] = {676		.type = VCAP_FIELD_BIT,677		.offset = 13,678		.width = 1,679	},680	[VCAP_KF_IF_IGR_PORT_MASK_RNG] = {681		.type = VCAP_FIELD_U32,682		.offset = 14,683		.width = 4,684	},685	[VCAP_KF_IF_IGR_PORT_MASK_SEL] = {686		.type = VCAP_FIELD_U32,687		.offset = 18,688		.width = 2,689	},690	[VCAP_KF_IF_IGR_PORT_MASK] = {691		.type = VCAP_FIELD_U32,692		.offset = 20,693		.width = 32,694	},695	[VCAP_KF_L2_MC_IS] = {696		.type = VCAP_FIELD_BIT,697		.offset = 52,698		.width = 1,699	},700	[VCAP_KF_L2_BC_IS] = {701		.type = VCAP_FIELD_BIT,702		.offset = 53,703		.width = 1,704	},705	[VCAP_KF_8021Q_VLAN_TAGGED_IS] = {706		.type = VCAP_FIELD_BIT,707		.offset = 54,708		.width = 1,709	},710	[VCAP_KF_ISDX_GT0_IS] = {711		.type = VCAP_FIELD_BIT,712		.offset = 55,713		.width = 1,714	},715	[VCAP_KF_ISDX_CLS] = {716		.type = VCAP_FIELD_U32,717		.offset = 56,718		.width = 12,719	},720	[VCAP_KF_8021Q_VID_CLS] = {721		.type = VCAP_FIELD_U32,722		.offset = 68,723		.width = 13,724	},725	[VCAP_KF_8021Q_DEI_CLS] = {726		.type = VCAP_FIELD_BIT,727		.offset = 81,728		.width = 1,729	},730	[VCAP_KF_8021Q_PCP_CLS] = {731		.type = VCAP_FIELD_U32,732		.offset = 82,733		.width = 3,734	},735	[VCAP_KF_L2_FWD_IS] = {736		.type = VCAP_FIELD_BIT,737		.offset = 85,738		.width = 1,739	},740	[VCAP_KF_L3_RT_IS] = {741		.type = VCAP_FIELD_BIT,742		.offset = 88,743		.width = 1,744	},745	[VCAP_KF_L3_DST_IS] = {746		.type = VCAP_FIELD_BIT,747		.offset = 89,748		.width = 1,749	},750	[VCAP_KF_IP4_IS] = {751		.type = VCAP_FIELD_BIT,752		.offset = 90,753		.width = 1,754	},755	[VCAP_KF_L3_FRAGMENT_TYPE] = {756		.type = VCAP_FIELD_U32,757		.offset = 91,758		.width = 2,759	},760	[VCAP_KF_L3_FRAG_INVLD_L4_LEN] = {761		.type = VCAP_FIELD_BIT,762		.offset = 93,763		.width = 1,764	},765	[VCAP_KF_L3_OPTIONS_IS] = {766		.type = VCAP_FIELD_BIT,767		.offset = 94,768		.width = 1,769	},770	[VCAP_KF_L3_TTL_GT0] = {771		.type = VCAP_FIELD_BIT,772		.offset = 95,773		.width = 1,774	},775	[VCAP_KF_L3_TOS] = {776		.type = VCAP_FIELD_U32,777		.offset = 96,778		.width = 8,779	},780	[VCAP_KF_L3_IP4_DIP] = {781		.type = VCAP_FIELD_U32,782		.offset = 104,783		.width = 32,784	},785	[VCAP_KF_L3_IP4_SIP] = {786		.type = VCAP_FIELD_U32,787		.offset = 136,788		.width = 32,789	},790	[VCAP_KF_L3_DIP_EQ_SIP_IS] = {791		.type = VCAP_FIELD_BIT,792		.offset = 168,793		.width = 1,794	},795	[VCAP_KF_TCP_IS] = {796		.type = VCAP_FIELD_BIT,797		.offset = 169,798		.width = 1,799	},800	[VCAP_KF_L4_DPORT] = {801		.type = VCAP_FIELD_U32,802		.offset = 170,803		.width = 16,804	},805	[VCAP_KF_L4_SPORT] = {806		.type = VCAP_FIELD_U32,807		.offset = 186,808		.width = 16,809	},810	[VCAP_KF_L4_RNG] = {811		.type = VCAP_FIELD_U32,812		.offset = 202,813		.width = 16,814	},815	[VCAP_KF_L4_SPORT_EQ_DPORT_IS] = {816		.type = VCAP_FIELD_BIT,817		.offset = 218,818		.width = 1,819	},820	[VCAP_KF_L4_SEQUENCE_EQ0_IS] = {821		.type = VCAP_FIELD_BIT,822		.offset = 219,823		.width = 1,824	},825	[VCAP_KF_L4_FIN] = {826		.type = VCAP_FIELD_BIT,827		.offset = 220,828		.width = 1,829	},830	[VCAP_KF_L4_SYN] = {831		.type = VCAP_FIELD_BIT,832		.offset = 221,833		.width = 1,834	},835	[VCAP_KF_L4_RST] = {836		.type = VCAP_FIELD_BIT,837		.offset = 222,838		.width = 1,839	},840	[VCAP_KF_L4_PSH] = {841		.type = VCAP_FIELD_BIT,842		.offset = 223,843		.width = 1,844	},845	[VCAP_KF_L4_ACK] = {846		.type = VCAP_FIELD_BIT,847		.offset = 224,848		.width = 1,849	},850	[VCAP_KF_L4_URG] = {851		.type = VCAP_FIELD_BIT,852		.offset = 225,853		.width = 1,854	},855	[VCAP_KF_L4_PAYLOAD] = {856		.type = VCAP_FIELD_U64,857		.offset = 226,858		.width = 64,859	},860};861 862static const struct vcap_field is2_ip4_other_keyfield[] = {863	[VCAP_KF_TYPE] = {864		.type = VCAP_FIELD_U32,865		.offset = 0,866		.width = 4,867	},868	[VCAP_KF_LOOKUP_FIRST_IS] = {869		.type = VCAP_FIELD_BIT,870		.offset = 4,871		.width = 1,872	},873	[VCAP_KF_LOOKUP_PAG] = {874		.type = VCAP_FIELD_U32,875		.offset = 5,876		.width = 8,877	},878	[VCAP_KF_IF_IGR_PORT_MASK_L3] = {879		.type = VCAP_FIELD_BIT,880		.offset = 13,881		.width = 1,882	},883	[VCAP_KF_IF_IGR_PORT_MASK_RNG] = {884		.type = VCAP_FIELD_U32,885		.offset = 14,886		.width = 4,887	},888	[VCAP_KF_IF_IGR_PORT_MASK_SEL] = {889		.type = VCAP_FIELD_U32,890		.offset = 18,891		.width = 2,892	},893	[VCAP_KF_IF_IGR_PORT_MASK] = {894		.type = VCAP_FIELD_U32,895		.offset = 20,896		.width = 32,897	},898	[VCAP_KF_L2_MC_IS] = {899		.type = VCAP_FIELD_BIT,900		.offset = 52,901		.width = 1,902	},903	[VCAP_KF_L2_BC_IS] = {904		.type = VCAP_FIELD_BIT,905		.offset = 53,906		.width = 1,907	},908	[VCAP_KF_8021Q_VLAN_TAGGED_IS] = {909		.type = VCAP_FIELD_BIT,910		.offset = 54,911		.width = 1,912	},913	[VCAP_KF_ISDX_GT0_IS] = {914		.type = VCAP_FIELD_BIT,915		.offset = 55,916		.width = 1,917	},918	[VCAP_KF_ISDX_CLS] = {919		.type = VCAP_FIELD_U32,920		.offset = 56,921		.width = 12,922	},923	[VCAP_KF_8021Q_VID_CLS] = {924		.type = VCAP_FIELD_U32,925		.offset = 68,926		.width = 13,927	},928	[VCAP_KF_8021Q_DEI_CLS] = {929		.type = VCAP_FIELD_BIT,930		.offset = 81,931		.width = 1,932	},933	[VCAP_KF_8021Q_PCP_CLS] = {934		.type = VCAP_FIELD_U32,935		.offset = 82,936		.width = 3,937	},938	[VCAP_KF_L2_FWD_IS] = {939		.type = VCAP_FIELD_BIT,940		.offset = 85,941		.width = 1,942	},943	[VCAP_KF_L3_RT_IS] = {944		.type = VCAP_FIELD_BIT,945		.offset = 88,946		.width = 1,947	},948	[VCAP_KF_L3_DST_IS] = {949		.type = VCAP_FIELD_BIT,950		.offset = 89,951		.width = 1,952	},953	[VCAP_KF_IP4_IS] = {954		.type = VCAP_FIELD_BIT,955		.offset = 90,956		.width = 1,957	},958	[VCAP_KF_L3_FRAGMENT_TYPE] = {959		.type = VCAP_FIELD_U32,960		.offset = 91,961		.width = 2,962	},963	[VCAP_KF_L3_FRAG_INVLD_L4_LEN] = {964		.type = VCAP_FIELD_BIT,965		.offset = 93,966		.width = 1,967	},968	[VCAP_KF_L3_OPTIONS_IS] = {969		.type = VCAP_FIELD_BIT,970		.offset = 94,971		.width = 1,972	},973	[VCAP_KF_L3_TTL_GT0] = {974		.type = VCAP_FIELD_BIT,975		.offset = 95,976		.width = 1,977	},978	[VCAP_KF_L3_TOS] = {979		.type = VCAP_FIELD_U32,980		.offset = 96,981		.width = 8,982	},983	[VCAP_KF_L3_IP4_DIP] = {984		.type = VCAP_FIELD_U32,985		.offset = 104,986		.width = 32,987	},988	[VCAP_KF_L3_IP4_SIP] = {989		.type = VCAP_FIELD_U32,990		.offset = 136,991		.width = 32,992	},993	[VCAP_KF_L3_DIP_EQ_SIP_IS] = {994		.type = VCAP_FIELD_BIT,995		.offset = 168,996		.width = 1,997	},998	[VCAP_KF_L3_IP_PROTO] = {999		.type = VCAP_FIELD_U32,1000		.offset = 169,1001		.width = 8,1002	},1003	[VCAP_KF_L4_RNG] = {1004		.type = VCAP_FIELD_U32,1005		.offset = 177,1006		.width = 16,1007	},1008	[VCAP_KF_L3_PAYLOAD] = {1009		.type = VCAP_FIELD_U112,1010		.offset = 193,1011		.width = 96,1012	},1013};1014 1015static const struct vcap_field is2_ip6_std_keyfield[] = {1016	[VCAP_KF_TYPE] = {1017		.type = VCAP_FIELD_U32,1018		.offset = 0,1019		.width = 4,1020	},1021	[VCAP_KF_LOOKUP_FIRST_IS] = {1022		.type = VCAP_FIELD_BIT,1023		.offset = 4,1024		.width = 1,1025	},1026	[VCAP_KF_LOOKUP_PAG] = {1027		.type = VCAP_FIELD_U32,1028		.offset = 5,1029		.width = 8,1030	},1031	[VCAP_KF_IF_IGR_PORT_MASK_L3] = {1032		.type = VCAP_FIELD_BIT,1033		.offset = 13,1034		.width = 1,1035	},1036	[VCAP_KF_IF_IGR_PORT_MASK_RNG] = {1037		.type = VCAP_FIELD_U32,1038		.offset = 14,1039		.width = 4,1040	},1041	[VCAP_KF_IF_IGR_PORT_MASK_SEL] = {1042		.type = VCAP_FIELD_U32,1043		.offset = 18,1044		.width = 2,1045	},1046	[VCAP_KF_IF_IGR_PORT_MASK] = {1047		.type = VCAP_FIELD_U32,1048		.offset = 20,1049		.width = 32,1050	},1051	[VCAP_KF_L2_MC_IS] = {1052		.type = VCAP_FIELD_BIT,1053		.offset = 52,1054		.width = 1,1055	},1056	[VCAP_KF_L2_BC_IS] = {1057		.type = VCAP_FIELD_BIT,1058		.offset = 53,1059		.width = 1,1060	},1061	[VCAP_KF_8021Q_VLAN_TAGGED_IS] = {1062		.type = VCAP_FIELD_BIT,1063		.offset = 54,1064		.width = 1,1065	},1066	[VCAP_KF_ISDX_GT0_IS] = {1067		.type = VCAP_FIELD_BIT,1068		.offset = 55,1069		.width = 1,1070	},1071	[VCAP_KF_ISDX_CLS] = {1072		.type = VCAP_FIELD_U32,1073		.offset = 56,1074		.width = 12,1075	},1076	[VCAP_KF_8021Q_VID_CLS] = {1077		.type = VCAP_FIELD_U32,1078		.offset = 68,1079		.width = 13,1080	},1081	[VCAP_KF_8021Q_DEI_CLS] = {1082		.type = VCAP_FIELD_BIT,1083		.offset = 81,1084		.width = 1,1085	},1086	[VCAP_KF_8021Q_PCP_CLS] = {1087		.type = VCAP_FIELD_U32,1088		.offset = 82,1089		.width = 3,1090	},1091	[VCAP_KF_L2_FWD_IS] = {1092		.type = VCAP_FIELD_BIT,1093		.offset = 85,1094		.width = 1,1095	},1096	[VCAP_KF_L3_RT_IS] = {1097		.type = VCAP_FIELD_BIT,1098		.offset = 88,1099		.width = 1,1100	},1101	[VCAP_KF_L3_TTL_GT0] = {1102		.type = VCAP_FIELD_BIT,1103		.offset = 90,1104		.width = 1,1105	},1106	[VCAP_KF_L3_IP6_SIP] = {1107		.type = VCAP_FIELD_U128,1108		.offset = 91,1109		.width = 128,1110	},1111	[VCAP_KF_L3_DIP_EQ_SIP_IS] = {1112		.type = VCAP_FIELD_BIT,1113		.offset = 219,1114		.width = 1,1115	},1116	[VCAP_KF_L3_IP_PROTO] = {1117		.type = VCAP_FIELD_U32,1118		.offset = 220,1119		.width = 8,1120	},1121	[VCAP_KF_L4_RNG] = {1122		.type = VCAP_FIELD_U32,1123		.offset = 228,1124		.width = 16,1125	},1126	[VCAP_KF_L3_PAYLOAD] = {1127		.type = VCAP_FIELD_U48,1128		.offset = 244,1129		.width = 40,1130	},1131};1132 1133static const struct vcap_field is2_ip_7tuple_keyfield[] = {1134	[VCAP_KF_TYPE] = {1135		.type = VCAP_FIELD_U32,1136		.offset = 0,1137		.width = 2,1138	},1139	[VCAP_KF_LOOKUP_FIRST_IS] = {1140		.type = VCAP_FIELD_BIT,1141		.offset = 2,1142		.width = 1,1143	},1144	[VCAP_KF_LOOKUP_PAG] = {1145		.type = VCAP_FIELD_U32,1146		.offset = 3,1147		.width = 8,1148	},1149	[VCAP_KF_IF_IGR_PORT_MASK_L3] = {1150		.type = VCAP_FIELD_BIT,1151		.offset = 11,1152		.width = 1,1153	},1154	[VCAP_KF_IF_IGR_PORT_MASK_RNG] = {1155		.type = VCAP_FIELD_U32,1156		.offset = 12,1157		.width = 4,1158	},1159	[VCAP_KF_IF_IGR_PORT_MASK_SEL] = {1160		.type = VCAP_FIELD_U32,1161		.offset = 16,1162		.width = 2,1163	},1164	[VCAP_KF_IF_IGR_PORT_MASK] = {1165		.type = VCAP_FIELD_U72,1166		.offset = 18,1167		.width = 65,1168	},1169	[VCAP_KF_L2_MC_IS] = {1170		.type = VCAP_FIELD_BIT,1171		.offset = 83,1172		.width = 1,1173	},1174	[VCAP_KF_L2_BC_IS] = {1175		.type = VCAP_FIELD_BIT,1176		.offset = 84,1177		.width = 1,1178	},1179	[VCAP_KF_8021Q_VLAN_TAGGED_IS] = {1180		.type = VCAP_FIELD_BIT,1181		.offset = 85,1182		.width = 1,1183	},1184	[VCAP_KF_ISDX_GT0_IS] = {1185		.type = VCAP_FIELD_BIT,1186		.offset = 86,1187		.width = 1,1188	},1189	[VCAP_KF_ISDX_CLS] = {1190		.type = VCAP_FIELD_U32,1191		.offset = 87,1192		.width = 12,1193	},1194	[VCAP_KF_8021Q_VID_CLS] = {1195		.type = VCAP_FIELD_U32,1196		.offset = 99,1197		.width = 13,1198	},1199	[VCAP_KF_8021Q_DEI_CLS] = {1200		.type = VCAP_FIELD_BIT,1201		.offset = 112,1202		.width = 1,1203	},1204	[VCAP_KF_8021Q_PCP_CLS] = {1205		.type = VCAP_FIELD_U32,1206		.offset = 113,1207		.width = 3,1208	},1209	[VCAP_KF_L2_FWD_IS] = {1210		.type = VCAP_FIELD_BIT,1211		.offset = 116,1212		.width = 1,1213	},1214	[VCAP_KF_L3_RT_IS] = {1215		.type = VCAP_FIELD_BIT,1216		.offset = 119,1217		.width = 1,1218	},1219	[VCAP_KF_L3_DST_IS] = {1220		.type = VCAP_FIELD_BIT,1221		.offset = 120,1222		.width = 1,1223	},1224	[VCAP_KF_L2_DMAC] = {1225		.type = VCAP_FIELD_U48,1226		.offset = 121,1227		.width = 48,1228	},1229	[VCAP_KF_L2_SMAC] = {1230		.type = VCAP_FIELD_U48,1231		.offset = 169,1232		.width = 48,1233	},1234	[VCAP_KF_IP4_IS] = {1235		.type = VCAP_FIELD_BIT,1236		.offset = 217,1237		.width = 1,1238	},1239	[VCAP_KF_L3_TTL_GT0] = {1240		.type = VCAP_FIELD_BIT,1241		.offset = 218,1242		.width = 1,1243	},1244	[VCAP_KF_L3_TOS] = {1245		.type = VCAP_FIELD_U32,1246		.offset = 219,1247		.width = 8,1248	},1249	[VCAP_KF_L3_IP6_DIP] = {1250		.type = VCAP_FIELD_U128,1251		.offset = 227,1252		.width = 128,1253	},1254	[VCAP_KF_L3_IP6_SIP] = {1255		.type = VCAP_FIELD_U128,1256		.offset = 355,1257		.width = 128,1258	},1259	[VCAP_KF_L3_DIP_EQ_SIP_IS] = {1260		.type = VCAP_FIELD_BIT,1261		.offset = 483,1262		.width = 1,1263	},1264	[VCAP_KF_TCP_UDP_IS] = {1265		.type = VCAP_FIELD_BIT,1266		.offset = 484,1267		.width = 1,1268	},1269	[VCAP_KF_TCP_IS] = {1270		.type = VCAP_FIELD_BIT,1271		.offset = 485,1272		.width = 1,1273	},1274	[VCAP_KF_L4_DPORT] = {1275		.type = VCAP_FIELD_U32,1276		.offset = 486,1277		.width = 16,1278	},1279	[VCAP_KF_L4_SPORT] = {1280		.type = VCAP_FIELD_U32,1281		.offset = 502,1282		.width = 16,1283	},1284	[VCAP_KF_L4_RNG] = {1285		.type = VCAP_FIELD_U32,1286		.offset = 518,1287		.width = 16,1288	},1289	[VCAP_KF_L4_SPORT_EQ_DPORT_IS] = {1290		.type = VCAP_FIELD_BIT,1291		.offset = 534,1292		.width = 1,1293	},1294	[VCAP_KF_L4_SEQUENCE_EQ0_IS] = {1295		.type = VCAP_FIELD_BIT,1296		.offset = 535,1297		.width = 1,1298	},1299	[VCAP_KF_L4_FIN] = {1300		.type = VCAP_FIELD_BIT,1301		.offset = 536,1302		.width = 1,1303	},1304	[VCAP_KF_L4_SYN] = {1305		.type = VCAP_FIELD_BIT,1306		.offset = 537,1307		.width = 1,1308	},1309	[VCAP_KF_L4_RST] = {1310		.type = VCAP_FIELD_BIT,1311		.offset = 538,1312		.width = 1,1313	},1314	[VCAP_KF_L4_PSH] = {1315		.type = VCAP_FIELD_BIT,1316		.offset = 539,1317		.width = 1,1318	},1319	[VCAP_KF_L4_ACK] = {1320		.type = VCAP_FIELD_BIT,1321		.offset = 540,1322		.width = 1,1323	},1324	[VCAP_KF_L4_URG] = {1325		.type = VCAP_FIELD_BIT,1326		.offset = 541,1327		.width = 1,1328	},1329	[VCAP_KF_L4_PAYLOAD] = {1330		.type = VCAP_FIELD_U64,1331		.offset = 542,1332		.width = 64,1333	},1334};1335 1336static const struct vcap_field es0_isdx_keyfield[] = {1337	[VCAP_KF_TYPE] = {1338		.type = VCAP_FIELD_BIT,1339		.offset = 0,1340		.width = 1,1341	},1342	[VCAP_KF_IF_EGR_PORT_NO] = {1343		.type = VCAP_FIELD_U32,1344		.offset = 1,1345		.width = 7,1346	},1347	[VCAP_KF_8021Q_VID_CLS] = {1348		.type = VCAP_FIELD_U32,1349		.offset = 8,1350		.width = 13,1351	},1352	[VCAP_KF_COSID_CLS] = {1353		.type = VCAP_FIELD_U32,1354		.offset = 21,1355		.width = 3,1356	},1357	[VCAP_KF_8021Q_TPID] = {1358		.type = VCAP_FIELD_U32,1359		.offset = 24,1360		.width = 3,1361	},1362	[VCAP_KF_L3_DPL_CLS] = {1363		.type = VCAP_FIELD_BIT,1364		.offset = 27,1365		.width = 1,1366	},1367	[VCAP_KF_ISDX_GT0_IS] = {1368		.type = VCAP_FIELD_BIT,1369		.offset = 28,1370		.width = 1,1371	},1372	[VCAP_KF_PROT_ACTIVE] = {1373		.type = VCAP_FIELD_BIT,1374		.offset = 29,1375		.width = 1,1376	},1377	[VCAP_KF_ISDX_CLS] = {1378		.type = VCAP_FIELD_U32,1379		.offset = 39,1380		.width = 12,1381	},1382};1383 1384static const struct vcap_field es2_mac_etype_keyfield[] = {1385	[VCAP_KF_TYPE] = {1386		.type = VCAP_FIELD_U32,1387		.offset = 0,1388		.width = 3,1389	},1390	[VCAP_KF_LOOKUP_FIRST_IS] = {1391		.type = VCAP_FIELD_BIT,1392		.offset = 3,1393		.width = 1,1394	},1395	[VCAP_KF_L2_MC_IS] = {1396		.type = VCAP_FIELD_BIT,1397		.offset = 13,1398		.width = 1,1399	},1400	[VCAP_KF_L2_BC_IS] = {1401		.type = VCAP_FIELD_BIT,1402		.offset = 14,1403		.width = 1,1404	},1405	[VCAP_KF_ISDX_GT0_IS] = {1406		.type = VCAP_FIELD_BIT,1407		.offset = 15,1408		.width = 1,1409	},1410	[VCAP_KF_ISDX_CLS] = {1411		.type = VCAP_FIELD_U32,1412		.offset = 16,1413		.width = 12,1414	},1415	[VCAP_KF_8021Q_VLAN_TAGGED_IS] = {1416		.type = VCAP_FIELD_BIT,1417		.offset = 28,1418		.width = 1,1419	},1420	[VCAP_KF_8021Q_VID_CLS] = {1421		.type = VCAP_FIELD_U32,1422		.offset = 29,1423		.width = 13,1424	},1425	[VCAP_KF_IF_EGR_PORT_MASK_RNG] = {1426		.type = VCAP_FIELD_U32,1427		.offset = 42,1428		.width = 3,1429	},1430	[VCAP_KF_IF_EGR_PORT_MASK] = {1431		.type = VCAP_FIELD_U32,1432		.offset = 45,1433		.width = 32,1434	},1435	[VCAP_KF_IF_IGR_PORT_SEL] = {1436		.type = VCAP_FIELD_BIT,1437		.offset = 77,1438		.width = 1,1439	},1440	[VCAP_KF_IF_IGR_PORT] = {1441		.type = VCAP_FIELD_U32,1442		.offset = 78,1443		.width = 9,1444	},1445	[VCAP_KF_8021Q_PCP_CLS] = {1446		.type = VCAP_FIELD_U32,1447		.offset = 87,1448		.width = 3,1449	},1450	[VCAP_KF_8021Q_DEI_CLS] = {1451		.type = VCAP_FIELD_BIT,1452		.offset = 90,1453		.width = 1,1454	},1455	[VCAP_KF_COSID_CLS] = {1456		.type = VCAP_FIELD_U32,1457		.offset = 91,1458		.width = 3,1459	},1460	[VCAP_KF_L3_DPL_CLS] = {1461		.type = VCAP_FIELD_BIT,1462		.offset = 94,1463		.width = 1,1464	},1465	[VCAP_KF_L3_RT_IS] = {1466		.type = VCAP_FIELD_BIT,1467		.offset = 95,1468		.width = 1,1469	},1470	[VCAP_KF_L2_DMAC] = {1471		.type = VCAP_FIELD_U48,1472		.offset = 99,1473		.width = 48,1474	},1475	[VCAP_KF_L2_SMAC] = {1476		.type = VCAP_FIELD_U48,1477		.offset = 147,1478		.width = 48,1479	},1480	[VCAP_KF_ETYPE_LEN_IS] = {1481		.type = VCAP_FIELD_BIT,1482		.offset = 195,1483		.width = 1,1484	},1485	[VCAP_KF_ETYPE] = {1486		.type = VCAP_FIELD_U32,1487		.offset = 196,1488		.width = 16,1489	},1490	[VCAP_KF_L2_PAYLOAD_ETYPE] = {1491		.type = VCAP_FIELD_U64,1492		.offset = 212,1493		.width = 64,1494	},1495	[VCAP_KF_OAM_CCM_CNTS_EQ0] = {1496		.type = VCAP_FIELD_BIT,1497		.offset = 276,1498		.width = 1,1499	},1500	[VCAP_KF_OAM_Y1731_IS] = {1501		.type = VCAP_FIELD_BIT,1502		.offset = 277,1503		.width = 1,1504	},1505};1506 1507static const struct vcap_field es2_arp_keyfield[] = {1508	[VCAP_KF_TYPE] = {1509		.type = VCAP_FIELD_U32,1510		.offset = 0,1511		.width = 3,1512	},1513	[VCAP_KF_LOOKUP_FIRST_IS] = {1514		.type = VCAP_FIELD_BIT,1515		.offset = 3,1516		.width = 1,1517	},1518	[VCAP_KF_L2_MC_IS] = {1519		.type = VCAP_FIELD_BIT,1520		.offset = 13,1521		.width = 1,1522	},1523	[VCAP_KF_L2_BC_IS] = {1524		.type = VCAP_FIELD_BIT,1525		.offset = 14,1526		.width = 1,1527	},1528	[VCAP_KF_ISDX_GT0_IS] = {1529		.type = VCAP_FIELD_BIT,1530		.offset = 15,1531		.width = 1,1532	},1533	[VCAP_KF_ISDX_CLS] = {1534		.type = VCAP_FIELD_U32,1535		.offset = 16,1536		.width = 12,1537	},1538	[VCAP_KF_8021Q_VLAN_TAGGED_IS] = {1539		.type = VCAP_FIELD_BIT,1540		.offset = 28,1541		.width = 1,1542	},1543	[VCAP_KF_8021Q_VID_CLS] = {1544		.type = VCAP_FIELD_U32,1545		.offset = 29,1546		.width = 13,1547	},1548	[VCAP_KF_IF_EGR_PORT_MASK_RNG] = {1549		.type = VCAP_FIELD_U32,1550		.offset = 42,1551		.width = 3,1552	},1553	[VCAP_KF_IF_EGR_PORT_MASK] = {1554		.type = VCAP_FIELD_U32,1555		.offset = 45,1556		.width = 32,1557	},1558	[VCAP_KF_IF_IGR_PORT_SEL] = {1559		.type = VCAP_FIELD_BIT,1560		.offset = 77,1561		.width = 1,1562	},1563	[VCAP_KF_IF_IGR_PORT] = {1564		.type = VCAP_FIELD_U32,1565		.offset = 78,1566		.width = 9,1567	},1568	[VCAP_KF_8021Q_PCP_CLS] = {1569		.type = VCAP_FIELD_U32,1570		.offset = 87,1571		.width = 3,1572	},1573	[VCAP_KF_8021Q_DEI_CLS] = {1574		.type = VCAP_FIELD_BIT,1575		.offset = 90,1576		.width = 1,1577	},1578	[VCAP_KF_COSID_CLS] = {1579		.type = VCAP_FIELD_U32,1580		.offset = 91,1581		.width = 3,1582	},1583	[VCAP_KF_L3_DPL_CLS] = {1584		.type = VCAP_FIELD_BIT,1585		.offset = 94,1586		.width = 1,1587	},1588	[VCAP_KF_L2_SMAC] = {1589		.type = VCAP_FIELD_U48,1590		.offset = 98,1591		.width = 48,1592	},1593	[VCAP_KF_ARP_ADDR_SPACE_OK_IS] = {1594		.type = VCAP_FIELD_BIT,1595		.offset = 146,1596		.width = 1,1597	},1598	[VCAP_KF_ARP_PROTO_SPACE_OK_IS] = {1599		.type = VCAP_FIELD_BIT,1600		.offset = 147,1601		.width = 1,1602	},1603	[VCAP_KF_ARP_LEN_OK_IS] = {1604		.type = VCAP_FIELD_BIT,1605		.offset = 148,1606		.width = 1,1607	},1608	[VCAP_KF_ARP_TGT_MATCH_IS] = {1609		.type = VCAP_FIELD_BIT,1610		.offset = 149,1611		.width = 1,1612	},1613	[VCAP_KF_ARP_SENDER_MATCH_IS] = {1614		.type = VCAP_FIELD_BIT,1615		.offset = 150,1616		.width = 1,1617	},1618	[VCAP_KF_ARP_OPCODE_UNKNOWN_IS] = {1619		.type = VCAP_FIELD_BIT,1620		.offset = 151,1621		.width = 1,1622	},1623	[VCAP_KF_ARP_OPCODE] = {1624		.type = VCAP_FIELD_U32,1625		.offset = 152,1626		.width = 2,1627	},1628	[VCAP_KF_L3_IP4_DIP] = {1629		.type = VCAP_FIELD_U32,1630		.offset = 154,1631		.width = 32,1632	},1633	[VCAP_KF_L3_IP4_SIP] = {1634		.type = VCAP_FIELD_U32,1635		.offset = 186,1636		.width = 32,1637	},1638	[VCAP_KF_L3_DIP_EQ_SIP_IS] = {1639		.type = VCAP_FIELD_BIT,1640		.offset = 218,1641		.width = 1,1642	},1643};1644 1645static const struct vcap_field es2_ip4_tcp_udp_keyfield[] = {1646	[VCAP_KF_TYPE] = {1647		.type = VCAP_FIELD_U32,1648		.offset = 0,1649		.width = 3,1650	},1651	[VCAP_KF_LOOKUP_FIRST_IS] = {1652		.type = VCAP_FIELD_BIT,1653		.offset = 3,1654		.width = 1,1655	},1656	[VCAP_KF_L2_MC_IS] = {1657		.type = VCAP_FIELD_BIT,1658		.offset = 13,1659		.width = 1,1660	},1661	[VCAP_KF_L2_BC_IS] = {1662		.type = VCAP_FIELD_BIT,1663		.offset = 14,1664		.width = 1,1665	},1666	[VCAP_KF_ISDX_GT0_IS] = {1667		.type = VCAP_FIELD_BIT,1668		.offset = 15,1669		.width = 1,1670	},1671	[VCAP_KF_ISDX_CLS] = {1672		.type = VCAP_FIELD_U32,1673		.offset = 16,1674		.width = 12,1675	},1676	[VCAP_KF_8021Q_VLAN_TAGGED_IS] = {1677		.type = VCAP_FIELD_BIT,1678		.offset = 28,1679		.width = 1,1680	},1681	[VCAP_KF_8021Q_VID_CLS] = {1682		.type = VCAP_FIELD_U32,1683		.offset = 29,1684		.width = 13,1685	},1686	[VCAP_KF_IF_EGR_PORT_MASK_RNG] = {1687		.type = VCAP_FIELD_U32,1688		.offset = 42,1689		.width = 3,1690	},1691	[VCAP_KF_IF_EGR_PORT_MASK] = {1692		.type = VCAP_FIELD_U32,1693		.offset = 45,1694		.width = 32,1695	},1696	[VCAP_KF_IF_IGR_PORT_SEL] = {1697		.type = VCAP_FIELD_BIT,1698		.offset = 77,1699		.width = 1,1700	},1701	[VCAP_KF_IF_IGR_PORT] = {1702		.type = VCAP_FIELD_U32,1703		.offset = 78,1704		.width = 9,1705	},1706	[VCAP_KF_8021Q_PCP_CLS] = {1707		.type = VCAP_FIELD_U32,1708		.offset = 87,1709		.width = 3,1710	},1711	[VCAP_KF_8021Q_DEI_CLS] = {1712		.type = VCAP_FIELD_BIT,1713		.offset = 90,1714		.width = 1,1715	},1716	[VCAP_KF_COSID_CLS] = {1717		.type = VCAP_FIELD_U32,1718		.offset = 91,1719		.width = 3,1720	},1721	[VCAP_KF_L3_DPL_CLS] = {1722		.type = VCAP_FIELD_BIT,1723		.offset = 94,1724		.width = 1,1725	},1726	[VCAP_KF_L3_RT_IS] = {1727		.type = VCAP_FIELD_BIT,1728		.offset = 95,1729		.width = 1,1730	},1731	[VCAP_KF_IP4_IS] = {1732		.type = VCAP_FIELD_BIT,1733		.offset = 99,1734		.width = 1,1735	},1736	[VCAP_KF_L3_FRAGMENT_TYPE] = {1737		.type = VCAP_FIELD_U32,1738		.offset = 100,1739		.width = 2,1740	},1741	[VCAP_KF_L3_OPTIONS_IS] = {1742		.type = VCAP_FIELD_BIT,1743		.offset = 102,1744		.width = 1,1745	},1746	[VCAP_KF_L3_TTL_GT0] = {1747		.type = VCAP_FIELD_BIT,1748		.offset = 103,1749		.width = 1,1750	},1751	[VCAP_KF_L3_TOS] = {1752		.type = VCAP_FIELD_U32,1753		.offset = 104,1754		.width = 8,1755	},1756	[VCAP_KF_L3_IP4_DIP] = {1757		.type = VCAP_FIELD_U32,1758		.offset = 112,1759		.width = 32,1760	},1761	[VCAP_KF_L3_IP4_SIP] = {1762		.type = VCAP_FIELD_U32,1763		.offset = 144,1764		.width = 32,1765	},1766	[VCAP_KF_L3_DIP_EQ_SIP_IS] = {1767		.type = VCAP_FIELD_BIT,1768		.offset = 176,1769		.width = 1,1770	},1771	[VCAP_KF_TCP_IS] = {1772		.type = VCAP_FIELD_BIT,1773		.offset = 177,1774		.width = 1,1775	},1776	[VCAP_KF_L4_DPORT] = {1777		.type = VCAP_FIELD_U32,1778		.offset = 178,1779		.width = 16,1780	},1781	[VCAP_KF_L4_SPORT] = {1782		.type = VCAP_FIELD_U32,1783		.offset = 194,1784		.width = 16,1785	},1786	[VCAP_KF_L4_RNG] = {1787		.type = VCAP_FIELD_U32,1788		.offset = 210,1789		.width = 16,1790	},1791	[VCAP_KF_L4_SPORT_EQ_DPORT_IS] = {1792		.type = VCAP_FIELD_BIT,1793		.offset = 226,1794		.width = 1,1795	},1796	[VCAP_KF_L4_SEQUENCE_EQ0_IS] = {1797		.type = VCAP_FIELD_BIT,1798		.offset = 227,1799		.width = 1,1800	},1801	[VCAP_KF_L4_FIN] = {1802		.type = VCAP_FIELD_BIT,1803		.offset = 228,1804		.width = 1,1805	},1806	[VCAP_KF_L4_SYN] = {1807		.type = VCAP_FIELD_BIT,1808		.offset = 229,1809		.width = 1,1810	},1811	[VCAP_KF_L4_RST] = {1812		.type = VCAP_FIELD_BIT,1813		.offset = 230,1814		.width = 1,1815	},1816	[VCAP_KF_L4_PSH] = {1817		.type = VCAP_FIELD_BIT,1818		.offset = 231,1819		.width = 1,1820	},1821	[VCAP_KF_L4_ACK] = {1822		.type = VCAP_FIELD_BIT,1823		.offset = 232,1824		.width = 1,1825	},1826	[VCAP_KF_L4_URG] = {1827		.type = VCAP_FIELD_BIT,1828		.offset = 233,1829		.width = 1,1830	},1831	[VCAP_KF_L4_PAYLOAD] = {1832		.type = VCAP_FIELD_U64,1833		.offset = 234,1834		.width = 64,1835	},1836};1837 1838static const struct vcap_field es2_ip4_other_keyfield[] = {1839	[VCAP_KF_TYPE] = {1840		.type = VCAP_FIELD_U32,1841		.offset = 0,1842		.width = 3,1843	},1844	[VCAP_KF_LOOKUP_FIRST_IS] = {1845		.type = VCAP_FIELD_BIT,1846		.offset = 3,1847		.width = 1,1848	},1849	[VCAP_KF_L2_MC_IS] = {1850		.type = VCAP_FIELD_BIT,1851		.offset = 13,1852		.width = 1,1853	},1854	[VCAP_KF_L2_BC_IS] = {1855		.type = VCAP_FIELD_BIT,1856		.offset = 14,1857		.width = 1,1858	},1859	[VCAP_KF_ISDX_GT0_IS] = {1860		.type = VCAP_FIELD_BIT,1861		.offset = 15,1862		.width = 1,1863	},1864	[VCAP_KF_ISDX_CLS] = {1865		.type = VCAP_FIELD_U32,1866		.offset = 16,1867		.width = 12,1868	},1869	[VCAP_KF_8021Q_VLAN_TAGGED_IS] = {1870		.type = VCAP_FIELD_BIT,1871		.offset = 28,1872		.width = 1,1873	},1874	[VCAP_KF_8021Q_VID_CLS] = {1875		.type = VCAP_FIELD_U32,1876		.offset = 29,1877		.width = 13,1878	},1879	[VCAP_KF_IF_EGR_PORT_MASK_RNG] = {1880		.type = VCAP_FIELD_U32,1881		.offset = 42,1882		.width = 3,1883	},1884	[VCAP_KF_IF_EGR_PORT_MASK] = {1885		.type = VCAP_FIELD_U32,1886		.offset = 45,1887		.width = 32,1888	},1889	[VCAP_KF_IF_IGR_PORT_SEL] = {1890		.type = VCAP_FIELD_BIT,1891		.offset = 77,1892		.width = 1,1893	},1894	[VCAP_KF_IF_IGR_PORT] = {1895		.type = VCAP_FIELD_U32,1896		.offset = 78,1897		.width = 9,1898	},1899	[VCAP_KF_8021Q_PCP_CLS] = {1900		.type = VCAP_FIELD_U32,1901		.offset = 87,1902		.width = 3,1903	},1904	[VCAP_KF_8021Q_DEI_CLS] = {1905		.type = VCAP_FIELD_BIT,1906		.offset = 90,1907		.width = 1,1908	},1909	[VCAP_KF_COSID_CLS] = {1910		.type = VCAP_FIELD_U32,1911		.offset = 91,1912		.width = 3,1913	},1914	[VCAP_KF_L3_DPL_CLS] = {1915		.type = VCAP_FIELD_BIT,1916		.offset = 94,1917		.width = 1,1918	},1919	[VCAP_KF_L3_RT_IS] = {1920		.type = VCAP_FIELD_BIT,1921		.offset = 95,1922		.width = 1,1923	},1924	[VCAP_KF_IP4_IS] = {1925		.type = VCAP_FIELD_BIT,1926		.offset = 99,1927		.width = 1,1928	},1929	[VCAP_KF_L3_FRAGMENT_TYPE] = {1930		.type = VCAP_FIELD_U32,1931		.offset = 100,1932		.width = 2,1933	},1934	[VCAP_KF_L3_OPTIONS_IS] = {1935		.type = VCAP_FIELD_BIT,1936		.offset = 102,1937		.width = 1,1938	},1939	[VCAP_KF_L3_TTL_GT0] = {1940		.type = VCAP_FIELD_BIT,1941		.offset = 103,1942		.width = 1,1943	},1944	[VCAP_KF_L3_TOS] = {1945		.type = VCAP_FIELD_U32,1946		.offset = 104,1947		.width = 8,1948	},1949	[VCAP_KF_L3_IP4_DIP] = {1950		.type = VCAP_FIELD_U32,1951		.offset = 112,1952		.width = 32,1953	},1954	[VCAP_KF_L3_IP4_SIP] = {1955		.type = VCAP_FIELD_U32,1956		.offset = 144,1957		.width = 32,1958	},1959	[VCAP_KF_L3_DIP_EQ_SIP_IS] = {1960		.type = VCAP_FIELD_BIT,1961		.offset = 176,1962		.width = 1,1963	},1964	[VCAP_KF_L3_IP_PROTO] = {1965		.type = VCAP_FIELD_U32,1966		.offset = 177,1967		.width = 8,1968	},1969	[VCAP_KF_L3_PAYLOAD] = {1970		.type = VCAP_FIELD_U112,1971		.offset = 185,1972		.width = 96,1973	},1974};1975 1976static const struct vcap_field es2_ip_7tuple_keyfield[] = {1977	[VCAP_KF_LOOKUP_FIRST_IS] = {1978		.type = VCAP_FIELD_BIT,1979		.offset = 0,1980		.width = 1,1981	},1982	[VCAP_KF_L2_MC_IS] = {1983		.type = VCAP_FIELD_BIT,1984		.offset = 10,1985		.width = 1,1986	},1987	[VCAP_KF_L2_BC_IS] = {1988		.type = VCAP_FIELD_BIT,1989		.offset = 11,1990		.width = 1,1991	},1992	[VCAP_KF_ISDX_GT0_IS] = {1993		.type = VCAP_FIELD_BIT,1994		.offset = 12,1995		.width = 1,1996	},1997	[VCAP_KF_ISDX_CLS] = {1998		.type = VCAP_FIELD_U32,1999		.offset = 13,2000		.width = 12,2001	},2002	[VCAP_KF_8021Q_VLAN_TAGGED_IS] = {2003		.type = VCAP_FIELD_BIT,2004		.offset = 25,2005		.width = 1,2006	},2007	[VCAP_KF_8021Q_VID_CLS] = {2008		.type = VCAP_FIELD_U32,2009		.offset = 26,2010		.width = 13,2011	},2012	[VCAP_KF_IF_EGR_PORT_MASK_RNG] = {2013		.type = VCAP_FIELD_U32,2014		.offset = 39,2015		.width = 3,2016	},2017	[VCAP_KF_IF_EGR_PORT_MASK] = {2018		.type = VCAP_FIELD_U32,2019		.offset = 42,2020		.width = 32,2021	},2022	[VCAP_KF_IF_IGR_PORT_SEL] = {2023		.type = VCAP_FIELD_BIT,2024		.offset = 74,2025		.width = 1,2026	},2027	[VCAP_KF_IF_IGR_PORT] = {2028		.type = VCAP_FIELD_U32,2029		.offset = 75,2030		.width = 9,2031	},2032	[VCAP_KF_8021Q_PCP_CLS] = {2033		.type = VCAP_FIELD_U32,2034		.offset = 84,2035		.width = 3,2036	},2037	[VCAP_KF_8021Q_DEI_CLS] = {2038		.type = VCAP_FIELD_BIT,2039		.offset = 87,2040		.width = 1,2041	},2042	[VCAP_KF_COSID_CLS] = {2043		.type = VCAP_FIELD_U32,2044		.offset = 88,2045		.width = 3,2046	},2047	[VCAP_KF_L3_DPL_CLS] = {2048		.type = VCAP_FIELD_BIT,2049		.offset = 91,2050		.width = 1,2051	},2052	[VCAP_KF_L3_RT_IS] = {2053		.type = VCAP_FIELD_BIT,2054		.offset = 92,2055		.width = 1,2056	},2057	[VCAP_KF_L2_DMAC] = {2058		.type = VCAP_FIELD_U48,2059		.offset = 96,2060		.width = 48,2061	},2062	[VCAP_KF_L2_SMAC] = {2063		.type = VCAP_FIELD_U48,2064		.offset = 144,2065		.width = 48,2066	},2067	[VCAP_KF_IP4_IS] = {2068		.type = VCAP_FIELD_BIT,2069		.offset = 192,2070		.width = 1,2071	},2072	[VCAP_KF_L3_TTL_GT0] = {2073		.type = VCAP_FIELD_BIT,2074		.offset = 193,2075		.width = 1,2076	},2077	[VCAP_KF_L3_TOS] = {2078		.type = VCAP_FIELD_U32,2079		.offset = 194,2080		.width = 8,2081	},2082	[VCAP_KF_L3_IP6_DIP] = {2083		.type = VCAP_FIELD_U128,2084		.offset = 202,2085		.width = 128,2086	},2087	[VCAP_KF_L3_IP6_SIP] = {2088		.type = VCAP_FIELD_U128,2089		.offset = 330,2090		.width = 128,2091	},2092	[VCAP_KF_L3_DIP_EQ_SIP_IS] = {2093		.type = VCAP_FIELD_BIT,2094		.offset = 458,2095		.width = 1,2096	},2097	[VCAP_KF_TCP_UDP_IS] = {2098		.type = VCAP_FIELD_BIT,2099		.offset = 459,2100		.width = 1,2101	},2102	[VCAP_KF_TCP_IS] = {2103		.type = VCAP_FIELD_BIT,2104		.offset = 460,2105		.width = 1,2106	},2107	[VCAP_KF_L4_DPORT] = {2108		.type = VCAP_FIELD_U32,2109		.offset = 461,2110		.width = 16,2111	},2112	[VCAP_KF_L4_SPORT] = {2113		.type = VCAP_FIELD_U32,2114		.offset = 477,2115		.width = 16,2116	},2117	[VCAP_KF_L4_RNG] = {2118		.type = VCAP_FIELD_U32,2119		.offset = 493,2120		.width = 16,2121	},2122	[VCAP_KF_L4_SPORT_EQ_DPORT_IS] = {2123		.type = VCAP_FIELD_BIT,2124		.offset = 509,2125		.width = 1,2126	},2127	[VCAP_KF_L4_SEQUENCE_EQ0_IS] = {2128		.type = VCAP_FIELD_BIT,2129		.offset = 510,2130		.width = 1,2131	},2132	[VCAP_KF_L4_FIN] = {2133		.type = VCAP_FIELD_BIT,2134		.offset = 511,2135		.width = 1,2136	},2137	[VCAP_KF_L4_SYN] = {2138		.type = VCAP_FIELD_BIT,2139		.offset = 512,2140		.width = 1,2141	},2142	[VCAP_KF_L4_RST] = {2143		.type = VCAP_FIELD_BIT,2144		.offset = 513,2145		.width = 1,2146	},2147	[VCAP_KF_L4_PSH] = {2148		.type = VCAP_FIELD_BIT,2149		.offset = 514,2150		.width = 1,2151	},2152	[VCAP_KF_L4_ACK] = {2153		.type = VCAP_FIELD_BIT,2154		.offset = 515,2155		.width = 1,2156	},2157	[VCAP_KF_L4_URG] = {2158		.type = VCAP_FIELD_BIT,2159		.offset = 516,2160		.width = 1,2161	},2162	[VCAP_KF_L4_PAYLOAD] = {2163		.type = VCAP_FIELD_U64,2164		.offset = 517,2165		.width = 64,2166	},2167};2168 2169static const struct vcap_field es2_ip6_std_keyfield[] = {2170	[VCAP_KF_TYPE] = {2171		.type = VCAP_FIELD_U32,2172		.offset = 0,2173		.width = 3,2174	},2175	[VCAP_KF_LOOKUP_FIRST_IS] = {2176		.type = VCAP_FIELD_BIT,2177		.offset = 3,2178		.width = 1,2179	},2180	[VCAP_KF_L2_MC_IS] = {2181		.type = VCAP_FIELD_BIT,2182		.offset = 13,2183		.width = 1,2184	},2185	[VCAP_KF_L2_BC_IS] = {2186		.type = VCAP_FIELD_BIT,2187		.offset = 14,2188		.width = 1,2189	},2190	[VCAP_KF_ISDX_GT0_IS] = {2191		.type = VCAP_FIELD_BIT,2192		.offset = 15,2193		.width = 1,2194	},2195	[VCAP_KF_ISDX_CLS] = {2196		.type = VCAP_FIELD_U32,2197		.offset = 16,2198		.width = 12,2199	},2200	[VCAP_KF_8021Q_VLAN_TAGGED_IS] = {2201		.type = VCAP_FIELD_BIT,2202		.offset = 28,2203		.width = 1,2204	},2205	[VCAP_KF_8021Q_VID_CLS] = {2206		.type = VCAP_FIELD_U32,2207		.offset = 29,2208		.width = 13,2209	},2210	[VCAP_KF_IF_EGR_PORT_MASK_RNG] = {2211		.type = VCAP_FIELD_U32,2212		.offset = 42,2213		.width = 3,2214	},2215	[VCAP_KF_IF_EGR_PORT_MASK] = {2216		.type = VCAP_FIELD_U32,2217		.offset = 45,2218		.width = 32,2219	},2220	[VCAP_KF_IF_IGR_PORT_SEL] = {2221		.type = VCAP_FIELD_BIT,2222		.offset = 77,2223		.width = 1,2224	},2225	[VCAP_KF_IF_IGR_PORT] = {2226		.type = VCAP_FIELD_U32,2227		.offset = 78,2228		.width = 9,2229	},2230	[VCAP_KF_8021Q_PCP_CLS] = {2231		.type = VCAP_FIELD_U32,2232		.offset = 87,2233		.width = 3,2234	},2235	[VCAP_KF_8021Q_DEI_CLS] = {2236		.type = VCAP_FIELD_BIT,2237		.offset = 90,2238		.width = 1,2239	},2240	[VCAP_KF_COSID_CLS] = {2241		.type = VCAP_FIELD_U32,2242		.offset = 91,2243		.width = 3,2244	},2245	[VCAP_KF_L3_DPL_CLS] = {2246		.type = VCAP_FIELD_BIT,2247		.offset = 94,2248		.width = 1,2249	},2250	[VCAP_KF_L3_RT_IS] = {2251		.type = VCAP_FIELD_BIT,2252		.offset = 95,2253		.width = 1,2254	},2255	[VCAP_KF_L3_TTL_GT0] = {2256		.type = VCAP_FIELD_BIT,2257		.offset = 99,2258		.width = 1,2259	},2260	[VCAP_KF_L3_IP6_SIP] = {2261		.type = VCAP_FIELD_U128,2262		.offset = 100,2263		.width = 128,2264	},2265	[VCAP_KF_L3_DIP_EQ_SIP_IS] = {2266		.type = VCAP_FIELD_BIT,2267		.offset = 228,2268		.width = 1,2269	},2270	[VCAP_KF_L3_IP_PROTO] = {2271		.type = VCAP_FIELD_U32,2272		.offset = 229,2273		.width = 8,2274	},2275	[VCAP_KF_L4_RNG] = {2276		.type = VCAP_FIELD_U32,2277		.offset = 237,2278		.width = 16,2279	},2280	[VCAP_KF_L3_PAYLOAD] = {2281		.type = VCAP_FIELD_U48,2282		.offset = 253,2283		.width = 40,2284	},2285};2286 2287/* keyfield_set */2288static const struct vcap_set is0_keyfield_set[] = {2289	[VCAP_KFS_NORMAL_7TUPLE] = {2290		.type_id = 0,2291		.sw_per_item = 12,2292		.sw_cnt = 1,2293	},2294	[VCAP_KFS_NORMAL_5TUPLE_IP4] = {2295		.type_id = 2,2296		.sw_per_item = 6,2297		.sw_cnt = 2,2298	},2299};2300 2301static const struct vcap_set is2_keyfield_set[] = {2302	[VCAP_KFS_MAC_ETYPE] = {2303		.type_id = 0,2304		.sw_per_item = 6,2305		.sw_cnt = 2,2306	},2307	[VCAP_KFS_ARP] = {2308		.type_id = 3,2309		.sw_per_item = 6,2310		.sw_cnt = 2,2311	},2312	[VCAP_KFS_IP4_TCP_UDP] = {2313		.type_id = 4,2314		.sw_per_item = 6,2315		.sw_cnt = 2,2316	},2317	[VCAP_KFS_IP4_OTHER] = {2318		.type_id = 5,2319		.sw_per_item = 6,2320		.sw_cnt = 2,2321	},2322	[VCAP_KFS_IP6_STD] = {2323		.type_id = 6,2324		.sw_per_item = 6,2325		.sw_cnt = 2,2326	},2327	[VCAP_KFS_IP_7TUPLE] = {2328		.type_id = 1,2329		.sw_per_item = 12,2330		.sw_cnt = 1,2331	},2332};2333 2334static const struct vcap_set es0_keyfield_set[] = {2335	[VCAP_KFS_ISDX] = {2336		.type_id = 0,2337		.sw_per_item = 1,2338		.sw_cnt = 1,2339	},2340};2341 2342static const struct vcap_set es2_keyfield_set[] = {2343	[VCAP_KFS_MAC_ETYPE] = {2344		.type_id = 0,2345		.sw_per_item = 6,2346		.sw_cnt = 2,2347	},2348	[VCAP_KFS_ARP] = {2349		.type_id = 1,2350		.sw_per_item = 6,2351		.sw_cnt = 2,2352	},2353	[VCAP_KFS_IP4_TCP_UDP] = {2354		.type_id = 2,2355		.sw_per_item = 6,2356		.sw_cnt = 2,2357	},2358	[VCAP_KFS_IP4_OTHER] = {2359		.type_id = 3,2360		.sw_per_item = 6,2361		.sw_cnt = 2,2362	},2363	[VCAP_KFS_IP_7TUPLE] = {2364		.type_id = -1,2365		.sw_per_item = 12,2366		.sw_cnt = 1,2367	},2368	[VCAP_KFS_IP6_STD] = {2369		.type_id = 4,2370		.sw_per_item = 6,2371		.sw_cnt = 2,2372	},2373};2374 2375/* keyfield_set map */2376static const struct vcap_field *is0_keyfield_set_map[] = {2377	[VCAP_KFS_NORMAL_7TUPLE] = is0_normal_7tuple_keyfield,2378	[VCAP_KFS_NORMAL_5TUPLE_IP4] = is0_normal_5tuple_ip4_keyfield,2379};2380 2381static const struct vcap_field *is2_keyfield_set_map[] = {2382	[VCAP_KFS_MAC_ETYPE] = is2_mac_etype_keyfield,2383	[VCAP_KFS_ARP] = is2_arp_keyfield,2384	[VCAP_KFS_IP4_TCP_UDP] = is2_ip4_tcp_udp_keyfield,2385	[VCAP_KFS_IP4_OTHER] = is2_ip4_other_keyfield,2386	[VCAP_KFS_IP6_STD] = is2_ip6_std_keyfield,2387	[VCAP_KFS_IP_7TUPLE] = is2_ip_7tuple_keyfield,2388};2389 2390static const struct vcap_field *es0_keyfield_set_map[] = {2391	[VCAP_KFS_ISDX] = es0_isdx_keyfield,2392};2393 2394static const struct vcap_field *es2_keyfield_set_map[] = {2395	[VCAP_KFS_MAC_ETYPE] = es2_mac_etype_keyfield,2396	[VCAP_KFS_ARP] = es2_arp_keyfield,2397	[VCAP_KFS_IP4_TCP_UDP] = es2_ip4_tcp_udp_keyfield,2398	[VCAP_KFS_IP4_OTHER] = es2_ip4_other_keyfield,2399	[VCAP_KFS_IP_7TUPLE] = es2_ip_7tuple_keyfield,2400	[VCAP_KFS_IP6_STD] = es2_ip6_std_keyfield,2401};2402 2403/* keyfield_set map sizes */2404static int is0_keyfield_set_map_size[] = {2405	[VCAP_KFS_NORMAL_7TUPLE] = ARRAY_SIZE(is0_normal_7tuple_keyfield),2406	[VCAP_KFS_NORMAL_5TUPLE_IP4] = ARRAY_SIZE(is0_normal_5tuple_ip4_keyfield),2407};2408 2409static int is2_keyfield_set_map_size[] = {2410	[VCAP_KFS_MAC_ETYPE] = ARRAY_SIZE(is2_mac_etype_keyfield),2411	[VCAP_KFS_ARP] = ARRAY_SIZE(is2_arp_keyfield),2412	[VCAP_KFS_IP4_TCP_UDP] = ARRAY_SIZE(is2_ip4_tcp_udp_keyfield),2413	[VCAP_KFS_IP4_OTHER] = ARRAY_SIZE(is2_ip4_other_keyfield),2414	[VCAP_KFS_IP6_STD] = ARRAY_SIZE(is2_ip6_std_keyfield),2415	[VCAP_KFS_IP_7TUPLE] = ARRAY_SIZE(is2_ip_7tuple_keyfield),2416};2417 2418static int es0_keyfield_set_map_size[] = {2419	[VCAP_KFS_ISDX] = ARRAY_SIZE(es0_isdx_keyfield),2420};2421 2422static int es2_keyfield_set_map_size[] = {2423	[VCAP_KFS_MAC_ETYPE] = ARRAY_SIZE(es2_mac_etype_keyfield),2424	[VCAP_KFS_ARP] = ARRAY_SIZE(es2_arp_keyfield),2425	[VCAP_KFS_IP4_TCP_UDP] = ARRAY_SIZE(es2_ip4_tcp_udp_keyfield),2426	[VCAP_KFS_IP4_OTHER] = ARRAY_SIZE(es2_ip4_other_keyfield),2427	[VCAP_KFS_IP_7TUPLE] = ARRAY_SIZE(es2_ip_7tuple_keyfield),2428	[VCAP_KFS_IP6_STD] = ARRAY_SIZE(es2_ip6_std_keyfield),2429};2430 2431/* actionfields */2432static const struct vcap_field is0_classification_actionfield[] = {2433	[VCAP_AF_TYPE] = {2434		.type = VCAP_FIELD_BIT,2435		.offset = 0,2436		.width = 1,2437	},2438	[VCAP_AF_DSCP_ENA] = {2439		.type = VCAP_FIELD_BIT,2440		.offset = 1,2441		.width = 1,2442	},2443	[VCAP_AF_DSCP_VAL] = {2444		.type = VCAP_FIELD_U32,2445		.offset = 2,2446		.width = 6,2447	},2448	[VCAP_AF_QOS_ENA] = {2449		.type = VCAP_FIELD_BIT,2450		.offset = 12,2451		.width = 1,2452	},2453	[VCAP_AF_QOS_VAL] = {2454		.type = VCAP_FIELD_U32,2455		.offset = 13,2456		.width = 3,2457	},2458	[VCAP_AF_DP_ENA] = {2459		.type = VCAP_FIELD_BIT,2460		.offset = 16,2461		.width = 1,2462	},2463	[VCAP_AF_DP_VAL] = {2464		.type = VCAP_FIELD_U32,2465		.offset = 17,2466		.width = 2,2467	},2468	[VCAP_AF_DEI_ENA] = {2469		.type = VCAP_FIELD_BIT,2470		.offset = 19,2471		.width = 1,2472	},2473	[VCAP_AF_DEI_VAL] = {2474		.type = VCAP_FIELD_BIT,2475		.offset = 20,2476		.width = 1,2477	},2478	[VCAP_AF_PCP_ENA] = {2479		.type = VCAP_FIELD_BIT,2480		.offset = 21,2481		.width = 1,2482	},2483	[VCAP_AF_PCP_VAL] = {2484		.type = VCAP_FIELD_U32,2485		.offset = 22,2486		.width = 3,2487	},2488	[VCAP_AF_MAP_LOOKUP_SEL] = {2489		.type = VCAP_FIELD_U32,2490		.offset = 25,2491		.width = 2,2492	},2493	[VCAP_AF_MAP_KEY] = {2494		.type = VCAP_FIELD_U32,2495		.offset = 27,2496		.width = 3,2497	},2498	[VCAP_AF_MAP_IDX] = {2499		.type = VCAP_FIELD_U32,2500		.offset = 30,2501		.width = 9,2502	},2503	[VCAP_AF_CLS_VID_SEL] = {2504		.type = VCAP_FIELD_U32,2505		.offset = 39,2506		.width = 3,2507	},2508	[VCAP_AF_VID_VAL] = {2509		.type = VCAP_FIELD_U32,2510		.offset = 45,2511		.width = 13,2512	},2513	[VCAP_AF_ISDX_ADD_REPLACE_SEL] = {2514		.type = VCAP_FIELD_BIT,2515		.offset = 68,2516		.width = 1,2517	},2518	[VCAP_AF_ISDX_VAL] = {2519		.type = VCAP_FIELD_U32,2520		.offset = 69,2521		.width = 12,2522	},2523	[VCAP_AF_PAG_OVERRIDE_MASK] = {2524		.type = VCAP_FIELD_U32,2525		.offset = 109,2526		.width = 8,2527	},2528	[VCAP_AF_PAG_VAL] = {2529		.type = VCAP_FIELD_U32,2530		.offset = 117,2531		.width = 8,2532	},2533	[VCAP_AF_NXT_IDX_CTRL] = {2534		.type = VCAP_FIELD_U32,2535		.offset = 171,2536		.width = 3,2537	},2538	[VCAP_AF_NXT_IDX] = {2539		.type = VCAP_FIELD_U32,2540		.offset = 174,2541		.width = 12,2542	},2543};2544 2545static const struct vcap_field is0_full_actionfield[] = {2546	[VCAP_AF_DSCP_ENA] = {2547		.type = VCAP_FIELD_BIT,2548		.offset = 0,2549		.width = 1,2550	},2551	[VCAP_AF_DSCP_VAL] = {2552		.type = VCAP_FIELD_U32,2553		.offset = 1,2554		.width = 6,2555	},2556	[VCAP_AF_QOS_ENA] = {2557		.type = VCAP_FIELD_BIT,2558		.offset = 11,2559		.width = 1,2560	},2561	[VCAP_AF_QOS_VAL] = {2562		.type = VCAP_FIELD_U32,2563		.offset = 12,2564		.width = 3,2565	},2566	[VCAP_AF_DP_ENA] = {2567		.type = VCAP_FIELD_BIT,2568		.offset = 15,2569		.width = 1,2570	},2571	[VCAP_AF_DP_VAL] = {2572		.type = VCAP_FIELD_U32,2573		.offset = 16,2574		.width = 2,2575	},2576	[VCAP_AF_DEI_ENA] = {2577		.type = VCAP_FIELD_BIT,2578		.offset = 18,2579		.width = 1,2580	},2581	[VCAP_AF_DEI_VAL] = {2582		.type = VCAP_FIELD_BIT,2583		.offset = 19,2584		.width = 1,2585	},2586	[VCAP_AF_PCP_ENA] = {2587		.type = VCAP_FIELD_BIT,2588		.offset = 20,2589		.width = 1,2590	},2591	[VCAP_AF_PCP_VAL] = {2592		.type = VCAP_FIELD_U32,2593		.offset = 21,2594		.width = 3,2595	},2596	[VCAP_AF_MAP_LOOKUP_SEL] = {2597		.type = VCAP_FIELD_U32,2598		.offset = 24,2599		.width = 2,2600	},2601	[VCAP_AF_MAP_KEY] = {2602		.type = VCAP_FIELD_U32,2603		.offset = 26,2604		.width = 3,2605	},2606	[VCAP_AF_MAP_IDX] = {2607		.type = VCAP_FIELD_U32,2608		.offset = 29,2609		.width = 9,2610	},2611	[VCAP_AF_CLS_VID_SEL] = {2612		.type = VCAP_FIELD_U32,2613		.offset = 38,2614		.width = 3,2615	},2616	[VCAP_AF_VID_VAL] = {2617		.type = VCAP_FIELD_U32,2618		.offset = 44,2619		.width = 13,2620	},2621	[VCAP_AF_ISDX_ADD_REPLACE_SEL] = {2622		.type = VCAP_FIELD_BIT,2623		.offset = 67,2624		.width = 1,2625	},2626	[VCAP_AF_ISDX_VAL] = {2627		.type = VCAP_FIELD_U32,2628		.offset = 68,2629		.width = 12,2630	},2631	[VCAP_AF_MASK_MODE] = {2632		.type = VCAP_FIELD_U32,2633		.offset = 80,2634		.width = 3,2635	},2636	[VCAP_AF_PORT_MASK] = {2637		.type = VCAP_FIELD_U72,2638		.offset = 83,2639		.width = 65,2640	},2641	[VCAP_AF_PAG_OVERRIDE_MASK] = {2642		.type = VCAP_FIELD_U32,2643		.offset = 204,2644		.width = 8,2645	},2646	[VCAP_AF_PAG_VAL] = {2647		.type = VCAP_FIELD_U32,2648		.offset = 212,2649		.width = 8,2650	},2651	[VCAP_AF_NXT_IDX_CTRL] = {2652		.type = VCAP_FIELD_U32,2653		.offset = 298,2654		.width = 3,2655	},2656	[VCAP_AF_NXT_IDX] = {2657		.type = VCAP_FIELD_U32,2658		.offset = 301,2659		.width = 12,2660	},2661};2662 2663static const struct vcap_field is0_class_reduced_actionfield[] = {2664	[VCAP_AF_TYPE] = {2665		.type = VCAP_FIELD_BIT,2666		.offset = 0,2667		.width = 1,2668	},2669	[VCAP_AF_QOS_ENA] = {2670		.type = VCAP_FIELD_BIT,2671		.offset = 5,2672		.width = 1,2673	},2674	[VCAP_AF_QOS_VAL] = {2675		.type = VCAP_FIELD_U32,2676		.offset = 6,2677		.width = 3,2678	},2679	[VCAP_AF_DP_ENA] = {2680		.type = VCAP_FIELD_BIT,2681		.offset = 9,2682		.width = 1,2683	},2684	[VCAP_AF_DP_VAL] = {2685		.type = VCAP_FIELD_U32,2686		.offset = 10,2687		.width = 2,2688	},2689	[VCAP_AF_MAP_LOOKUP_SEL] = {2690		.type = VCAP_FIELD_U32,2691		.offset = 12,2692		.width = 2,2693	},2694	[VCAP_AF_MAP_KEY] = {2695		.type = VCAP_FIELD_U32,2696		.offset = 14,2697		.width = 3,2698	},2699	[VCAP_AF_CLS_VID_SEL] = {2700		.type = VCAP_FIELD_U32,2701		.offset = 17,2702		.width = 3,2703	},2704	[VCAP_AF_VID_VAL] = {2705		.type = VCAP_FIELD_U32,2706		.offset = 23,2707		.width = 13,2708	},2709	[VCAP_AF_ISDX_ADD_REPLACE_SEL] = {2710		.type = VCAP_FIELD_BIT,2711		.offset = 46,2712		.width = 1,2713	},2714	[VCAP_AF_ISDX_VAL] = {2715		.type = VCAP_FIELD_U32,2716		.offset = 47,2717		.width = 12,2718	},2719	[VCAP_AF_NXT_IDX_CTRL] = {2720		.type = VCAP_FIELD_U32,2721		.offset = 90,2722		.width = 3,2723	},2724	[VCAP_AF_NXT_IDX] = {2725		.type = VCAP_FIELD_U32,2726		.offset = 93,2727		.width = 12,2728	},2729};2730 2731static const struct vcap_field is2_base_type_actionfield[] = {2732	[VCAP_AF_PIPELINE_FORCE_ENA] = {2733		.type = VCAP_FIELD_BIT,2734		.offset = 1,2735		.width = 1,2736	},2737	[VCAP_AF_PIPELINE_PT] = {2738		.type = VCAP_FIELD_U32,2739		.offset = 2,2740		.width = 5,2741	},2742	[VCAP_AF_HIT_ME_ONCE] = {2743		.type = VCAP_FIELD_BIT,2744		.offset = 7,2745		.width = 1,2746	},2747	[VCAP_AF_INTR_ENA] = {2748		.type = VCAP_FIELD_BIT,2749		.offset = 8,2750		.width = 1,2751	},2752	[VCAP_AF_CPU_COPY_ENA] = {2753		.type = VCAP_FIELD_BIT,2754		.offset = 9,2755		.width = 1,2756	},2757	[VCAP_AF_CPU_QUEUE_NUM] = {2758		.type = VCAP_FIELD_U32,2759		.offset = 10,2760		.width = 3,2761	},2762	[VCAP_AF_LRN_DIS] = {2763		.type = VCAP_FIELD_BIT,2764		.offset = 14,2765		.width = 1,2766	},2767	[VCAP_AF_RT_DIS] = {2768		.type = VCAP_FIELD_BIT,2769		.offset = 15,2770		.width = 1,2771	},2772	[VCAP_AF_POLICE_ENA] = {2773		.type = VCAP_FIELD_BIT,2774		.offset = 16,2775		.width = 1,2776	},2777	[VCAP_AF_POLICE_IDX] = {2778		.type = VCAP_FIELD_U32,2779		.offset = 17,2780		.width = 6,2781	},2782	[VCAP_AF_IGNORE_PIPELINE_CTRL] = {2783		.type = VCAP_FIELD_BIT,2784		.offset = 23,2785		.width = 1,2786	},2787	[VCAP_AF_MASK_MODE] = {2788		.type = VCAP_FIELD_U32,2789		.offset = 27,2790		.width = 3,2791	},2792	[VCAP_AF_PORT_MASK] = {2793		.type = VCAP_FIELD_U72,2794		.offset = 30,2795		.width = 68,2796	},2797	[VCAP_AF_MIRROR_PROBE] = {2798		.type = VCAP_FIELD_U32,2799		.offset = 111,2800		.width = 2,2801	},2802	[VCAP_AF_MATCH_ID] = {2803		.type = VCAP_FIELD_U32,2804		.offset = 159,2805		.width = 16,2806	},2807	[VCAP_AF_MATCH_ID_MASK] = {2808		.type = VCAP_FIELD_U32,2809		.offset = 175,2810		.width = 16,2811	},2812	[VCAP_AF_CNT_ID] = {2813		.type = VCAP_FIELD_U32,2814		.offset = 191,2815		.width = 12,2816	},2817};2818 2819static const struct vcap_field es0_es0_actionfield[] = {2820	[VCAP_AF_PUSH_OUTER_TAG] = {2821		.type = VCAP_FIELD_U32,2822		.offset = 0,2823		.width = 2,2824	},2825	[VCAP_AF_PUSH_INNER_TAG] = {2826		.type = VCAP_FIELD_BIT,2827		.offset = 2,2828		.width = 1,2829	},2830	[VCAP_AF_TAG_A_TPID_SEL] = {2831		.type = VCAP_FIELD_U32,2832		.offset = 3,2833		.width = 3,2834	},2835	[VCAP_AF_TAG_A_VID_SEL] = {2836		.type = VCAP_FIELD_U32,2837		.offset = 6,2838		.width = 2,2839	},2840	[VCAP_AF_TAG_A_PCP_SEL] = {2841		.type = VCAP_FIELD_U32,2842		.offset = 8,2843		.width = 3,2844	},2845	[VCAP_AF_TAG_A_DEI_SEL] = {2846		.type = VCAP_FIELD_U32,2847		.offset = 11,2848		.width = 3,2849	},2850	[VCAP_AF_TAG_B_TPID_SEL] = {2851		.type = VCAP_FIELD_U32,2852		.offset = 14,2853		.width = 3,2854	},2855	[VCAP_AF_TAG_B_VID_SEL] = {2856		.type = VCAP_FIELD_U32,2857		.offset = 17,2858		.width = 2,2859	},2860	[VCAP_AF_TAG_B_PCP_SEL] = {2861		.type = VCAP_FIELD_U32,2862		.offset = 19,2863		.width = 3,2864	},2865	[VCAP_AF_TAG_B_DEI_SEL] = {2866		.type = VCAP_FIELD_U32,2867		.offset = 22,2868		.width = 3,2869	},2870	[VCAP_AF_TAG_C_TPID_SEL] = {2871		.type = VCAP_FIELD_U32,2872		.offset = 25,2873		.width = 3,2874	},2875	[VCAP_AF_TAG_C_PCP_SEL] = {2876		.type = VCAP_FIELD_U32,2877		.offset = 28,2878		.width = 3,2879	},2880	[VCAP_AF_TAG_C_DEI_SEL] = {2881		.type = VCAP_FIELD_U32,2882		.offset = 31,2883		.width = 3,2884	},2885	[VCAP_AF_VID_A_VAL] = {2886		.type = VCAP_FIELD_U32,2887		.offset = 34,2888		.width = 12,2889	},2890	[VCAP_AF_PCP_A_VAL] = {2891		.type = VCAP_FIELD_U32,2892		.offset = 46,2893		.width = 3,2894	},2895	[VCAP_AF_DEI_A_VAL] = {2896		.type = VCAP_FIELD_BIT,2897		.offset = 49,2898		.width = 1,2899	},2900	[VCAP_AF_VID_B_VAL] = {2901		.type = VCAP_FIELD_U32,2902		.offset = 50,2903		.width = 12,2904	},2905	[VCAP_AF_PCP_B_VAL] = {2906		.type = VCAP_FIELD_U32,2907		.offset = 62,2908		.width = 3,2909	},2910	[VCAP_AF_DEI_B_VAL] = {2911		.type = VCAP_FIELD_BIT,2912		.offset = 65,2913		.width = 1,2914	},2915	[VCAP_AF_VID_C_VAL] = {2916		.type = VCAP_FIELD_U32,2917		.offset = 66,2918		.width = 12,2919	},2920	[VCAP_AF_PCP_C_VAL] = {2921		.type = VCAP_FIELD_U32,2922		.offset = 78,2923		.width = 3,2924	},2925	[VCAP_AF_DEI_C_VAL] = {2926		.type = VCAP_FIELD_BIT,2927		.offset = 81,2928		.width = 1,2929	},2930	[VCAP_AF_POP_VAL] = {2931		.type = VCAP_FIELD_U32,2932		.offset = 82,2933		.width = 2,2934	},2935	[VCAP_AF_UNTAG_VID_ENA] = {2936		.type = VCAP_FIELD_BIT,2937		.offset = 84,2938		.width = 1,2939	},2940	[VCAP_AF_PUSH_CUSTOMER_TAG] = {2941		.type = VCAP_FIELD_U32,2942		.offset = 85,2943		.width = 2,2944	},2945	[VCAP_AF_TAG_C_VID_SEL] = {2946		.type = VCAP_FIELD_U32,2947		.offset = 87,2948		.width = 2,2949	},2950	[VCAP_AF_DSCP_SEL] = {2951		.type = VCAP_FIELD_U32,2952		.offset = 127,2953		.width = 3,2954	},2955	[VCAP_AF_DSCP_VAL] = {2956		.type = VCAP_FIELD_U32,2957		.offset = 130,2958		.width = 6,2959	},2960	[VCAP_AF_ESDX] = {2961		.type = VCAP_FIELD_U32,2962		.offset = 323,2963		.width = 13,2964	},2965	[VCAP_AF_FWD_SEL] = {2966		.type = VCAP_FIELD_U32,2967		.offset = 459,2968		.width = 2,2969	},2970	[VCAP_AF_CPU_QU] = {2971		.type = VCAP_FIELD_U32,2972		.offset = 461,2973		.width = 3,2974	},2975	[VCAP_AF_PIPELINE_PT] = {2976		.type = VCAP_FIELD_U32,2977		.offset = 464,2978		.width = 2,2979	},2980	[VCAP_AF_PIPELINE_ACT] = {2981		.type = VCAP_FIELD_BIT,2982		.offset = 466,2983		.width = 1,2984	},2985	[VCAP_AF_SWAP_MACS_ENA] = {2986		.type = VCAP_FIELD_BIT,2987		.offset = 475,2988		.width = 1,2989	},2990	[VCAP_AF_LOOP_ENA] = {2991		.type = VCAP_FIELD_BIT,2992		.offset = 476,2993		.width = 1,2994	},2995};2996 2997static const struct vcap_field es2_base_type_actionfield[] = {2998	[VCAP_AF_HIT_ME_ONCE] = {2999		.type = VCAP_FIELD_BIT,3000		.offset = 0,3001		.width = 1,3002	},3003	[VCAP_AF_INTR_ENA] = {3004		.type = VCAP_FIELD_BIT,3005		.offset = 1,3006		.width = 1,3007	},3008	[VCAP_AF_FWD_MODE] = {3009		.type = VCAP_FIELD_U32,3010		.offset = 2,3011		.width = 2,3012	},3013	[VCAP_AF_COPY_QUEUE_NUM] = {3014		.type = VCAP_FIELD_U32,3015		.offset = 4,3016		.width = 16,3017	},3018	[VCAP_AF_COPY_PORT_NUM] = {3019		.type = VCAP_FIELD_U32,3020		.offset = 20,3021		.width = 7,3022	},3023	[VCAP_AF_MIRROR_PROBE_ID] = {3024		.type = VCAP_FIELD_U32,3025		.offset = 27,3026		.width = 2,3027	},3028	[VCAP_AF_CPU_COPY_ENA] = {3029		.type = VCAP_FIELD_BIT,3030		.offset = 29,3031		.width = 1,3032	},3033	[VCAP_AF_CPU_QUEUE_NUM] = {3034		.type = VCAP_FIELD_U32,3035		.offset = 30,3036		.width = 3,3037	},3038	[VCAP_AF_POLICE_ENA] = {3039		.type = VCAP_FIELD_BIT,3040		.offset = 33,3041		.width = 1,3042	},3043	[VCAP_AF_POLICE_REMARK] = {3044		.type = VCAP_FIELD_BIT,3045		.offset = 34,3046		.width = 1,3047	},3048	[VCAP_AF_POLICE_IDX] = {3049		.type = VCAP_FIELD_U32,3050		.offset = 35,3051		.width = 6,3052	},3053	[VCAP_AF_ES2_REW_CMD] = {3054		.type = VCAP_FIELD_U32,3055		.offset = 41,3056		.width = 3,3057	},3058	[VCAP_AF_CNT_ID] = {3059		.type = VCAP_FIELD_U32,3060		.offset = 44,3061		.width = 11,3062	},3063	[VCAP_AF_IGNORE_PIPELINE_CTRL] = {3064		.type = VCAP_FIELD_BIT,3065		.offset = 55,3066		.width = 1,3067	},3068};3069 3070/* actionfield_set */3071static const struct vcap_set is0_actionfield_set[] = {3072	[VCAP_AFS_CLASSIFICATION] = {3073		.type_id = 1,3074		.sw_per_item = 2,3075		.sw_cnt = 6,3076	},3077	[VCAP_AFS_FULL] = {3078		.type_id = -1,3079		.sw_per_item = 3,3080		.sw_cnt = 4,3081	},3082	[VCAP_AFS_CLASS_REDUCED] = {3083		.type_id = 1,3084		.sw_per_item = 1,3085		.sw_cnt = 12,3086	},3087};3088 3089static const struct vcap_set is2_actionfield_set[] = {3090	[VCAP_AFS_BASE_TYPE] = {3091		.type_id = -1,3092		.sw_per_item = 3,3093		.sw_cnt = 4,3094	},3095};3096 3097static const struct vcap_set es0_actionfield_set[] = {3098	[VCAP_AFS_ES0] = {3099		.type_id = -1,3100		.sw_per_item = 1,3101		.sw_cnt = 1,3102	},3103};3104 3105static const struct vcap_set es2_actionfield_set[] = {3106	[VCAP_AFS_BASE_TYPE] = {3107		.type_id = -1,3108		.sw_per_item = 3,3109		.sw_cnt = 4,3110	},3111};3112 3113/* actionfield_set map */3114static const struct vcap_field *is0_actionfield_set_map[] = {3115	[VCAP_AFS_CLASSIFICATION] = is0_classification_actionfield,3116	[VCAP_AFS_FULL] = is0_full_actionfield,3117	[VCAP_AFS_CLASS_REDUCED] = is0_class_reduced_actionfield,3118};3119 3120static const struct vcap_field *is2_actionfield_set_map[] = {3121	[VCAP_AFS_BASE_TYPE] = is2_base_type_actionfield,3122};3123 3124static const struct vcap_field *es0_actionfield_set_map[] = {3125	[VCAP_AFS_ES0] = es0_es0_actionfield,3126};3127 3128static const struct vcap_field *es2_actionfield_set_map[] = {3129	[VCAP_AFS_BASE_TYPE] = es2_base_type_actionfield,3130};3131 3132/* actionfield_set map size */3133static int is0_actionfield_set_map_size[] = {3134	[VCAP_AFS_CLASSIFICATION] = ARRAY_SIZE(is0_classification_actionfield),3135	[VCAP_AFS_FULL] = ARRAY_SIZE(is0_full_actionfield),3136	[VCAP_AFS_CLASS_REDUCED] = ARRAY_SIZE(is0_class_reduced_actionfield),3137};3138 3139static int is2_actionfield_set_map_size[] = {3140	[VCAP_AFS_BASE_TYPE] = ARRAY_SIZE(is2_base_type_actionfield),3141};3142 3143static int es0_actionfield_set_map_size[] = {3144	[VCAP_AFS_ES0] = ARRAY_SIZE(es0_es0_actionfield),3145};3146 3147static int es2_actionfield_set_map_size[] = {3148	[VCAP_AFS_BASE_TYPE] = ARRAY_SIZE(es2_base_type_actionfield),3149};3150 3151/* Type Groups */3152static const struct vcap_typegroup is0_x12_keyfield_set_typegroups[] = {3153	{3154		.offset = 0,3155		.width = 5,3156		.value = 16,3157	},3158	{3159		.offset = 52,3160		.width = 1,3161		.value = 0,3162	},3163	{3164		.offset = 104,3165		.width = 2,3166		.value = 0,3167	},3168	{3169		.offset = 156,3170		.width = 3,3171		.value = 0,3172	},3173	{3174		.offset = 208,3175		.width = 2,3176		.value = 0,3177	},3178	{3179		.offset = 260,3180		.width = 1,3181		.value = 0,3182	},3183	{3184		.offset = 312,3185		.width = 4,3186		.value = 0,3187	},3188	{3189		.offset = 364,3190		.width = 1,3191		.value = 0,3192	},3193	{3194		.offset = 416,3195		.width = 2,3196		.value = 0,3197	},3198	{3199		.offset = 468,3200		.width = 3,3201		.value = 0,3202	},3203	{3204		.offset = 520,3205		.width = 2,3206		.value = 0,3207	},3208	{3209		.offset = 572,3210		.width = 1,3211		.value = 0,3212	},3213	{}3214};3215 3216static const struct vcap_typegroup is0_x6_keyfield_set_typegroups[] = {3217	{3218		.offset = 0,3219		.width = 4,3220		.value = 8,3221	},3222	{3223		.offset = 52,3224		.width = 1,3225		.value = 0,3226	},3227	{3228		.offset = 104,3229		.width = 2,3230		.value = 0,3231	},3232	{3233		.offset = 156,3234		.width = 3,3235		.value = 0,3236	},3237	{3238		.offset = 208,3239		.width = 2,3240		.value = 0,3241	},3242	{3243		.offset = 260,3244		.width = 1,3245		.value = 0,3246	},3247	{}3248};3249 3250static const struct vcap_typegroup is0_x3_keyfield_set_typegroups[] = {3251	{3252		.offset = 0,3253		.width = 3,3254		.value = 4,3255	},3256	{3257		.offset = 52,3258		.width = 2,3259		.value = 0,3260	},3261	{3262		.offset = 104,3263		.width = 2,3264		.value = 0,3265	},3266	{}3267};3268 3269static const struct vcap_typegroup is0_x2_keyfield_set_typegroups[] = {3270	{3271		.offset = 0,3272		.width = 2,3273		.value = 2,3274	},3275	{3276		.offset = 52,3277		.width = 1,3278		.value = 0,3279	},3280	{}3281};3282 3283static const struct vcap_typegroup is0_x1_keyfield_set_typegroups[] = {3284	{}3285};3286 3287static const struct vcap_typegroup is2_x12_keyfield_set_typegroups[] = {3288	{3289		.offset = 0,3290		.width = 3,3291		.value = 4,3292	},3293	{3294		.offset = 156,3295		.width = 1,3296		.value = 0,3297	},3298	{3299		.offset = 312,3300		.width = 2,3301		.value = 0,3302	},3303	{3304		.offset = 468,3305		.width = 1,3306		.value = 0,3307	},3308	{}3309};3310 3311static const struct vcap_typegroup is2_x6_keyfield_set_typegroups[] = {3312	{3313		.offset = 0,3314		.width = 2,3315		.value = 2,3316	},3317	{3318		.offset = 156,3319		.width = 1,3320		.value = 0,3321	},3322	{}3323};3324 3325static const struct vcap_typegroup is2_x3_keyfield_set_typegroups[] = {3326	{}3327};3328 3329static const struct vcap_typegroup is2_x1_keyfield_set_typegroups[] = {3330	{}3331};3332 3333static const struct vcap_typegroup es0_x1_keyfield_set_typegroups[] = {3334	{}3335};3336 3337static const struct vcap_typegroup es2_x12_keyfield_set_typegroups[] = {3338	{3339		.offset = 0,3340		.width = 3,3341		.value = 4,3342	},3343	{3344		.offset = 156,3345		.width = 1,3346		.value = 0,3347	},3348	{3349		.offset = 312,3350		.width = 2,3351		.value = 0,3352	},3353	{3354		.offset = 468,3355		.width = 1,3356		.value = 0,3357	},3358	{}3359};3360 3361static const struct vcap_typegroup es2_x6_keyfield_set_typegroups[] = {3362	{3363		.offset = 0,3364		.width = 2,3365		.value = 2,3366	},3367	{3368		.offset = 156,3369		.width = 1,3370		.value = 0,3371	},3372	{}3373};3374 3375static const struct vcap_typegroup es2_x3_keyfield_set_typegroups[] = {3376	{3377		.offset = 0,3378		.width = 1,3379		.value = 1,3380	},3381	{}3382};3383 3384static const struct vcap_typegroup es2_x1_keyfield_set_typegroups[] = {3385	{}3386};3387 3388static const struct vcap_typegroup *is0_keyfield_set_typegroups[] = {3389	[12] = is0_x12_keyfield_set_typegroups,3390	[6] = is0_x6_keyfield_set_typegroups,3391	[3] = is0_x3_keyfield_set_typegroups,3392	[2] = is0_x2_keyfield_set_typegroups,3393	[1] = is0_x1_keyfield_set_typegroups,3394	[13] = NULL,3395};3396 3397static const struct vcap_typegroup *is2_keyfield_set_typegroups[] = {3398	[12] = is2_x12_keyfield_set_typegroups,3399	[6] = is2_x6_keyfield_set_typegroups,3400	[3] = is2_x3_keyfield_set_typegroups,3401	[1] = is2_x1_keyfield_set_typegroups,3402	[13] = NULL,3403};3404 3405static const struct vcap_typegroup *es0_keyfield_set_typegroups[] = {3406	[1] = es0_x1_keyfield_set_typegroups,3407	[2] = NULL,3408};3409 3410static const struct vcap_typegroup *es2_keyfield_set_typegroups[] = {3411	[12] = es2_x12_keyfield_set_typegroups,3412	[6] = es2_x6_keyfield_set_typegroups,3413	[3] = es2_x3_keyfield_set_typegroups,3414	[1] = es2_x1_keyfield_set_typegroups,3415	[13] = NULL,3416};3417 3418static const struct vcap_typegroup is0_x3_actionfield_set_typegroups[] = {3419	{3420		.offset = 0,3421		.width = 3,3422		.value = 4,3423	},3424	{3425		.offset = 110,3426		.width = 2,3427		.value = 0,3428	},3429	{3430		.offset = 220,3431		.width = 2,3432		.value = 0,3433	},3434	{}3435};3436 3437static const struct vcap_typegroup is0_x2_actionfield_set_typegroups[] = {3438	{3439		.offset = 0,3440		.width = 2,3441		.value = 2,3442	},3443	{3444		.offset = 110,3445		.width = 1,3446		.value = 0,3447	},3448	{}3449};3450 3451static const struct vcap_typegroup is0_x1_actionfield_set_typegroups[] = {3452	{3453		.offset = 0,3454		.width = 1,3455		.value = 1,3456	},3457	{}3458};3459 3460static const struct vcap_typegroup is2_x3_actionfield_set_typegroups[] = {3461	{3462		.offset = 0,3463		.width = 2,3464		.value = 2,3465	},3466	{3467		.offset = 110,3468		.width = 1,3469		.value = 0,3470	},3471	{3472		.offset = 220,3473		.width = 1,3474		.value = 0,3475	},3476	{}3477};3478 3479static const struct vcap_typegroup is2_x1_actionfield_set_typegroups[] = {3480	{}3481};3482 3483static const struct vcap_typegroup es0_x1_actionfield_set_typegroups[] = {3484	{}3485};3486 3487static const struct vcap_typegroup es2_x3_actionfield_set_typegroups[] = {3488	{3489		.offset = 0,3490		.width = 2,3491		.value = 2,3492	},3493	{3494		.offset = 21,3495		.width = 1,3496		.value = 0,3497	},3498	{3499		.offset = 42,3500		.width = 1,3501		.value = 0,3502	},3503	{}3504};3505 3506static const struct vcap_typegroup es2_x1_actionfield_set_typegroups[] = {3507	{}3508};3509 3510static const struct vcap_typegroup *is0_actionfield_set_typegroups[] = {3511	[3] = is0_x3_actionfield_set_typegroups,3512	[2] = is0_x2_actionfield_set_typegroups,3513	[1] = is0_x1_actionfield_set_typegroups,3514	[13] = NULL,3515};3516 3517static const struct vcap_typegroup *is2_actionfield_set_typegroups[] = {3518	[3] = is2_x3_actionfield_set_typegroups,3519	[1] = is2_x1_actionfield_set_typegroups,3520	[13] = NULL,3521};3522 3523static const struct vcap_typegroup *es0_actionfield_set_typegroups[] = {3524	[1] = es0_x1_actionfield_set_typegroups,3525	[2] = NULL,3526};3527 3528static const struct vcap_typegroup *es2_actionfield_set_typegroups[] = {3529	[3] = es2_x3_actionfield_set_typegroups,3530	[1] = es2_x1_actionfield_set_typegroups,3531	[13] = NULL,3532};3533 3534/* Keyfieldset names */3535static const char * const vcap_keyfield_set_names[] = {3536	[VCAP_KFS_NO_VALUE]                      =  "(None)",3537	[VCAP_KFS_ARP]                           =  "VCAP_KFS_ARP",3538	[VCAP_KFS_ETAG]                          =  "VCAP_KFS_ETAG",3539	[VCAP_KFS_IP4_OTHER]                     =  "VCAP_KFS_IP4_OTHER",3540	[VCAP_KFS_IP4_TCP_UDP]                   =  "VCAP_KFS_IP4_TCP_UDP",3541	[VCAP_KFS_IP4_VID]                       =  "VCAP_KFS_IP4_VID",3542	[VCAP_KFS_IP6_OTHER]                     =  "VCAP_KFS_IP6_OTHER",3543	[VCAP_KFS_IP6_STD]                       =  "VCAP_KFS_IP6_STD",3544	[VCAP_KFS_IP6_TCP_UDP]                   =  "VCAP_KFS_IP6_TCP_UDP",3545	[VCAP_KFS_IP6_VID]                       =  "VCAP_KFS_IP6_VID",3546	[VCAP_KFS_IP_7TUPLE]                     =  "VCAP_KFS_IP_7TUPLE",3547	[VCAP_KFS_ISDX]                          =  "VCAP_KFS_ISDX",3548	[VCAP_KFS_LL_FULL]                       =  "VCAP_KFS_LL_FULL",3549	[VCAP_KFS_MAC_ETYPE]                     =  "VCAP_KFS_MAC_ETYPE",3550	[VCAP_KFS_MAC_LLC]                       =  "VCAP_KFS_MAC_LLC",3551	[VCAP_KFS_MAC_SNAP]                      =  "VCAP_KFS_MAC_SNAP",3552	[VCAP_KFS_NORMAL_5TUPLE_IP4]             =  "VCAP_KFS_NORMAL_5TUPLE_IP4",3553	[VCAP_KFS_NORMAL_7TUPLE]                 =  "VCAP_KFS_NORMAL_7TUPLE",3554	[VCAP_KFS_OAM]                           =  "VCAP_KFS_OAM",3555	[VCAP_KFS_PURE_5TUPLE_IP4]               =  "VCAP_KFS_PURE_5TUPLE_IP4",3556	[VCAP_KFS_SMAC_SIP4]                     =  "VCAP_KFS_SMAC_SIP4",3557	[VCAP_KFS_SMAC_SIP6]                     =  "VCAP_KFS_SMAC_SIP6",3558};3559 3560/* Actionfieldset names */3561static const char * const vcap_actionfield_set_names[] = {3562	[VCAP_AFS_NO_VALUE]                      =  "(None)",3563	[VCAP_AFS_BASE_TYPE]                     =  "VCAP_AFS_BASE_TYPE",3564	[VCAP_AFS_CLASSIFICATION]                =  "VCAP_AFS_CLASSIFICATION",3565	[VCAP_AFS_CLASS_REDUCED]                 =  "VCAP_AFS_CLASS_REDUCED",3566	[VCAP_AFS_ES0]                           =  "VCAP_AFS_ES0",3567	[VCAP_AFS_FULL]                          =  "VCAP_AFS_FULL",3568	[VCAP_AFS_SMAC_SIP]                      =  "VCAP_AFS_SMAC_SIP",3569};3570 3571/* Keyfield names */3572static const char * const vcap_keyfield_names[] = {3573	[VCAP_KF_NO_VALUE]                       =  "(None)",3574	[VCAP_KF_8021BR_ECID_BASE]               =  "8021BR_ECID_BASE",3575	[VCAP_KF_8021BR_ECID_EXT]                =  "8021BR_ECID_EXT",3576	[VCAP_KF_8021BR_E_TAGGED]                =  "8021BR_E_TAGGED",3577	[VCAP_KF_8021BR_GRP]                     =  "8021BR_GRP",3578	[VCAP_KF_8021BR_IGR_ECID_BASE]           =  "8021BR_IGR_ECID_BASE",3579	[VCAP_KF_8021BR_IGR_ECID_EXT]            =  "8021BR_IGR_ECID_EXT",3580	[VCAP_KF_8021Q_DEI0]                     =  "8021Q_DEI0",3581	[VCAP_KF_8021Q_DEI1]                     =  "8021Q_DEI1",3582	[VCAP_KF_8021Q_DEI2]                     =  "8021Q_DEI2",3583	[VCAP_KF_8021Q_DEI_CLS]                  =  "8021Q_DEI_CLS",3584	[VCAP_KF_8021Q_PCP0]                     =  "8021Q_PCP0",3585	[VCAP_KF_8021Q_PCP1]                     =  "8021Q_PCP1",3586	[VCAP_KF_8021Q_PCP2]                     =  "8021Q_PCP2",3587	[VCAP_KF_8021Q_PCP_CLS]                  =  "8021Q_PCP_CLS",3588	[VCAP_KF_8021Q_TPID]                     =  "8021Q_TPID",3589	[VCAP_KF_8021Q_TPID0]                    =  "8021Q_TPID0",3590	[VCAP_KF_8021Q_TPID1]                    =  "8021Q_TPID1",3591	[VCAP_KF_8021Q_TPID2]                    =  "8021Q_TPID2",3592	[VCAP_KF_8021Q_VID0]                     =  "8021Q_VID0",3593	[VCAP_KF_8021Q_VID1]                     =  "8021Q_VID1",3594	[VCAP_KF_8021Q_VID2]                     =  "8021Q_VID2",3595	[VCAP_KF_8021Q_VID_CLS]                  =  "8021Q_VID_CLS",3596	[VCAP_KF_8021Q_VLAN_TAGGED_IS]           =  "8021Q_VLAN_TAGGED_IS",3597	[VCAP_KF_8021Q_VLAN_TAGS]                =  "8021Q_VLAN_TAGS",3598	[VCAP_KF_ACL_GRP_ID]                     =  "ACL_GRP_ID",3599	[VCAP_KF_ARP_ADDR_SPACE_OK_IS]           =  "ARP_ADDR_SPACE_OK_IS",3600	[VCAP_KF_ARP_LEN_OK_IS]                  =  "ARP_LEN_OK_IS",3601	[VCAP_KF_ARP_OPCODE]                     =  "ARP_OPCODE",3602	[VCAP_KF_ARP_OPCODE_UNKNOWN_IS]          =  "ARP_OPCODE_UNKNOWN_IS",3603	[VCAP_KF_ARP_PROTO_SPACE_OK_IS]          =  "ARP_PROTO_SPACE_OK_IS",3604	[VCAP_KF_ARP_SENDER_MATCH_IS]            =  "ARP_SENDER_MATCH_IS",3605	[VCAP_KF_ARP_TGT_MATCH_IS]               =  "ARP_TGT_MATCH_IS",3606	[VCAP_KF_COSID_CLS]                      =  "COSID_CLS",3607	[VCAP_KF_ES0_ISDX_KEY_ENA]               =  "ES0_ISDX_KEY_ENA",3608	[VCAP_KF_ETYPE]                          =  "ETYPE",3609	[VCAP_KF_ETYPE_LEN_IS]                   =  "ETYPE_LEN_IS",3610	[VCAP_KF_HOST_MATCH]                     =  "HOST_MATCH",3611	[VCAP_KF_IF_EGR_PORT_MASK]               =  "IF_EGR_PORT_MASK",3612	[VCAP_KF_IF_EGR_PORT_MASK_RNG]           =  "IF_EGR_PORT_MASK_RNG",3613	[VCAP_KF_IF_EGR_PORT_NO]                 =  "IF_EGR_PORT_NO",3614	[VCAP_KF_IF_IGR_PORT]                    =  "IF_IGR_PORT",3615	[VCAP_KF_IF_IGR_PORT_MASK]               =  "IF_IGR_PORT_MASK",3616	[VCAP_KF_IF_IGR_PORT_MASK_L3]            =  "IF_IGR_PORT_MASK_L3",3617	[VCAP_KF_IF_IGR_PORT_MASK_RNG]           =  "IF_IGR_PORT_MASK_RNG",3618	[VCAP_KF_IF_IGR_PORT_MASK_SEL]           =  "IF_IGR_PORT_MASK_SEL",3619	[VCAP_KF_IF_IGR_PORT_SEL]                =  "IF_IGR_PORT_SEL",3620	[VCAP_KF_IP4_IS]                         =  "IP4_IS",3621	[VCAP_KF_IP_MC_IS]                       =  "IP_MC_IS",3622	[VCAP_KF_IP_PAYLOAD_5TUPLE]              =  "IP_PAYLOAD_5TUPLE",3623	[VCAP_KF_IP_SNAP_IS]                     =  "IP_SNAP_IS",3624	[VCAP_KF_ISDX_CLS]                       =  "ISDX_CLS",3625	[VCAP_KF_ISDX_GT0_IS]                    =  "ISDX_GT0_IS",3626	[VCAP_KF_L2_BC_IS]                       =  "L2_BC_IS",3627	[VCAP_KF_L2_DMAC]                        =  "L2_DMAC",3628	[VCAP_KF_L2_FRM_TYPE]                    =  "L2_FRM_TYPE",3629	[VCAP_KF_L2_FWD_IS]                      =  "L2_FWD_IS",3630	[VCAP_KF_L2_LLC]                         =  "L2_LLC",3631	[VCAP_KF_L2_MC_IS]                       =  "L2_MC_IS",3632	[VCAP_KF_L2_PAYLOAD0]                    =  "L2_PAYLOAD0",3633	[VCAP_KF_L2_PAYLOAD1]                    =  "L2_PAYLOAD1",3634	[VCAP_KF_L2_PAYLOAD2]                    =  "L2_PAYLOAD2",3635	[VCAP_KF_L2_PAYLOAD_ETYPE]               =  "L2_PAYLOAD_ETYPE",3636	[VCAP_KF_L2_SMAC]                        =  "L2_SMAC",3637	[VCAP_KF_L2_SNAP]                        =  "L2_SNAP",3638	[VCAP_KF_L3_DIP_EQ_SIP_IS]               =  "L3_DIP_EQ_SIP_IS",3639	[VCAP_KF_L3_DPL_CLS]                     =  "L3_DPL_CLS",3640	[VCAP_KF_L3_DSCP]                        =  "L3_DSCP",3641	[VCAP_KF_L3_DST_IS]                      =  "L3_DST_IS",3642	[VCAP_KF_L3_FRAGMENT]                    =  "L3_FRAGMENT",3643	[VCAP_KF_L3_FRAGMENT_TYPE]               =  "L3_FRAGMENT_TYPE",3644	[VCAP_KF_L3_FRAG_INVLD_L4_LEN]           =  "L3_FRAG_INVLD_L4_LEN",3645	[VCAP_KF_L3_FRAG_OFS_GT0]                =  "L3_FRAG_OFS_GT0",3646	[VCAP_KF_L3_IP4_DIP]                     =  "L3_IP4_DIP",3647	[VCAP_KF_L3_IP4_SIP]                     =  "L3_IP4_SIP",3648	[VCAP_KF_L3_IP6_DIP]                     =  "L3_IP6_DIP",3649	[VCAP_KF_L3_IP6_SIP]                     =  "L3_IP6_SIP",3650	[VCAP_KF_L3_IP_PROTO]                    =  "L3_IP_PROTO",3651	[VCAP_KF_L3_OPTIONS_IS]                  =  "L3_OPTIONS_IS",3652	[VCAP_KF_L3_PAYLOAD]                     =  "L3_PAYLOAD",3653	[VCAP_KF_L3_RT_IS]                       =  "L3_RT_IS",3654	[VCAP_KF_L3_TOS]                         =  "L3_TOS",3655	[VCAP_KF_L3_TTL_GT0]                     =  "L3_TTL_GT0",3656	[VCAP_KF_L4_1588_DOM]                    =  "L4_1588_DOM",3657	[VCAP_KF_L4_1588_VER]                    =  "L4_1588_VER",3658	[VCAP_KF_L4_ACK]                         =  "L4_ACK",3659	[VCAP_KF_L4_DPORT]                       =  "L4_DPORT",3660	[VCAP_KF_L4_FIN]                         =  "L4_FIN",3661	[VCAP_KF_L4_PAYLOAD]                     =  "L4_PAYLOAD",3662	[VCAP_KF_L4_PSH]                         =  "L4_PSH",3663	[VCAP_KF_L4_RNG]                         =  "L4_RNG",3664	[VCAP_KF_L4_RST]                         =  "L4_RST",3665	[VCAP_KF_L4_SEQUENCE_EQ0_IS]             =  "L4_SEQUENCE_EQ0_IS",3666	[VCAP_KF_L4_SPORT]                       =  "L4_SPORT",3667	[VCAP_KF_L4_SPORT_EQ_DPORT_IS]           =  "L4_SPORT_EQ_DPORT_IS",3668	[VCAP_KF_L4_SYN]                         =  "L4_SYN",3669	[VCAP_KF_L4_URG]                         =  "L4_URG",3670	[VCAP_KF_LOOKUP_FIRST_IS]                =  "LOOKUP_FIRST_IS",3671	[VCAP_KF_LOOKUP_GEN_IDX]                 =  "LOOKUP_GEN_IDX",3672	[VCAP_KF_LOOKUP_GEN_IDX_SEL]             =  "LOOKUP_GEN_IDX_SEL",3673	[VCAP_KF_LOOKUP_PAG]                     =  "LOOKUP_PAG",3674	[VCAP_KF_MIRROR_PROBE]                   =  "MIRROR_PROBE",3675	[VCAP_KF_OAM_CCM_CNTS_EQ0]               =  "OAM_CCM_CNTS_EQ0",3676	[VCAP_KF_OAM_DETECTED]                   =  "OAM_DETECTED",3677	[VCAP_KF_OAM_FLAGS]                      =  "OAM_FLAGS",3678	[VCAP_KF_OAM_MEL_FLAGS]                  =  "OAM_MEL_FLAGS",3679	[VCAP_KF_OAM_MEPID]                      =  "OAM_MEPID",3680	[VCAP_KF_OAM_OPCODE]                     =  "OAM_OPCODE",3681	[VCAP_KF_OAM_VER]                        =  "OAM_VER",3682	[VCAP_KF_OAM_Y1731_IS]                   =  "OAM_Y1731_IS",3683	[VCAP_KF_PROT_ACTIVE]                    =  "PROT_ACTIVE",3684	[VCAP_KF_TCP_IS]                         =  "TCP_IS",3685	[VCAP_KF_TCP_UDP_IS]                     =  "TCP_UDP_IS",3686	[VCAP_KF_TYPE]                           =  "TYPE",3687};3688 3689/* Actionfield names */3690static const char * const vcap_actionfield_names[] = {3691	[VCAP_AF_NO_VALUE]                       =  "(None)",3692	[VCAP_AF_ACL_ID]                         =  "ACL_ID",3693	[VCAP_AF_CLS_VID_SEL]                    =  "CLS_VID_SEL",3694	[VCAP_AF_CNT_ID]                         =  "CNT_ID",3695	[VCAP_AF_COPY_PORT_NUM]                  =  "COPY_PORT_NUM",3696	[VCAP_AF_COPY_QUEUE_NUM]                 =  "COPY_QUEUE_NUM",3697	[VCAP_AF_CPU_COPY_ENA]                   =  "CPU_COPY_ENA",3698	[VCAP_AF_CPU_QU]                         =  "CPU_QU",3699	[VCAP_AF_CPU_QUEUE_NUM]                  =  "CPU_QUEUE_NUM",3700	[VCAP_AF_DEI_A_VAL]                      =  "DEI_A_VAL",3701	[VCAP_AF_DEI_B_VAL]                      =  "DEI_B_VAL",3702	[VCAP_AF_DEI_C_VAL]                      =  "DEI_C_VAL",3703	[VCAP_AF_DEI_ENA]                        =  "DEI_ENA",3704	[VCAP_AF_DEI_VAL]                        =  "DEI_VAL",3705	[VCAP_AF_DP_ENA]                         =  "DP_ENA",3706	[VCAP_AF_DP_VAL]                         =  "DP_VAL",3707	[VCAP_AF_DSCP_ENA]                       =  "DSCP_ENA",3708	[VCAP_AF_DSCP_SEL]                       =  "DSCP_SEL",3709	[VCAP_AF_DSCP_VAL]                       =  "DSCP_VAL",3710	[VCAP_AF_ES2_REW_CMD]                    =  "ES2_REW_CMD",3711	[VCAP_AF_ESDX]                           =  "ESDX",3712	[VCAP_AF_FWD_KILL_ENA]                   =  "FWD_KILL_ENA",3713	[VCAP_AF_FWD_MODE]                       =  "FWD_MODE",3714	[VCAP_AF_FWD_SEL]                        =  "FWD_SEL",3715	[VCAP_AF_HIT_ME_ONCE]                    =  "HIT_ME_ONCE",3716	[VCAP_AF_HOST_MATCH]                     =  "HOST_MATCH",3717	[VCAP_AF_IGNORE_PIPELINE_CTRL]           =  "IGNORE_PIPELINE_CTRL",3718	[VCAP_AF_INTR_ENA]                       =  "INTR_ENA",3719	[VCAP_AF_ISDX_ADD_REPLACE_SEL]           =  "ISDX_ADD_REPLACE_SEL",3720	[VCAP_AF_ISDX_ENA]                       =  "ISDX_ENA",3721	[VCAP_AF_ISDX_VAL]                       =  "ISDX_VAL",3722	[VCAP_AF_LOOP_ENA]                       =  "LOOP_ENA",3723	[VCAP_AF_LRN_DIS]                        =  "LRN_DIS",3724	[VCAP_AF_MAP_IDX]                        =  "MAP_IDX",3725	[VCAP_AF_MAP_KEY]                        =  "MAP_KEY",3726	[VCAP_AF_MAP_LOOKUP_SEL]                 =  "MAP_LOOKUP_SEL",3727	[VCAP_AF_MASK_MODE]                      =  "MASK_MODE",3728	[VCAP_AF_MATCH_ID]                       =  "MATCH_ID",3729	[VCAP_AF_MATCH_ID_MASK]                  =  "MATCH_ID_MASK",3730	[VCAP_AF_MIRROR_ENA]                     =  "MIRROR_ENA",3731	[VCAP_AF_MIRROR_PROBE]                   =  "MIRROR_PROBE",3732	[VCAP_AF_MIRROR_PROBE_ID]                =  "MIRROR_PROBE_ID",3733	[VCAP_AF_NXT_IDX]                        =  "NXT_IDX",3734	[VCAP_AF_NXT_IDX_CTRL]                   =  "NXT_IDX_CTRL",3735	[VCAP_AF_PAG_OVERRIDE_MASK]              =  "PAG_OVERRIDE_MASK",3736	[VCAP_AF_PAG_VAL]                        =  "PAG_VAL",3737	[VCAP_AF_PCP_A_VAL]                      =  "PCP_A_VAL",3738	[VCAP_AF_PCP_B_VAL]                      =  "PCP_B_VAL",3739	[VCAP_AF_PCP_C_VAL]                      =  "PCP_C_VAL",3740	[VCAP_AF_PCP_ENA]                        =  "PCP_ENA",3741	[VCAP_AF_PCP_VAL]                        =  "PCP_VAL",3742	[VCAP_AF_PIPELINE_ACT]                   =  "PIPELINE_ACT",3743	[VCAP_AF_PIPELINE_FORCE_ENA]             =  "PIPELINE_FORCE_ENA",3744	[VCAP_AF_PIPELINE_PT]                    =  "PIPELINE_PT",3745	[VCAP_AF_POLICE_ENA]                     =  "POLICE_ENA",3746	[VCAP_AF_POLICE_IDX]                     =  "POLICE_IDX",3747	[VCAP_AF_POLICE_REMARK]                  =  "POLICE_REMARK",3748	[VCAP_AF_POLICE_VCAP_ONLY]               =  "POLICE_VCAP_ONLY",3749	[VCAP_AF_POP_VAL]                        =  "POP_VAL",3750	[VCAP_AF_PORT_MASK]                      =  "PORT_MASK",3751	[VCAP_AF_PUSH_CUSTOMER_TAG]              =  "PUSH_CUSTOMER_TAG",3752	[VCAP_AF_PUSH_INNER_TAG]                 =  "PUSH_INNER_TAG",3753	[VCAP_AF_PUSH_OUTER_TAG]                 =  "PUSH_OUTER_TAG",3754	[VCAP_AF_QOS_ENA]                        =  "QOS_ENA",3755	[VCAP_AF_QOS_VAL]                        =  "QOS_VAL",3756	[VCAP_AF_REW_OP]                         =  "REW_OP",3757	[VCAP_AF_RT_DIS]                         =  "RT_DIS",3758	[VCAP_AF_SWAP_MACS_ENA]                  =  "SWAP_MACS_ENA",3759	[VCAP_AF_TAG_A_DEI_SEL]                  =  "TAG_A_DEI_SEL",3760	[VCAP_AF_TAG_A_PCP_SEL]                  =  "TAG_A_PCP_SEL",3761	[VCAP_AF_TAG_A_TPID_SEL]                 =  "TAG_A_TPID_SEL",3762	[VCAP_AF_TAG_A_VID_SEL]                  =  "TAG_A_VID_SEL",3763	[VCAP_AF_TAG_B_DEI_SEL]                  =  "TAG_B_DEI_SEL",3764	[VCAP_AF_TAG_B_PCP_SEL]                  =  "TAG_B_PCP_SEL",3765	[VCAP_AF_TAG_B_TPID_SEL]                 =  "TAG_B_TPID_SEL",3766	[VCAP_AF_TAG_B_VID_SEL]                  =  "TAG_B_VID_SEL",3767	[VCAP_AF_TAG_C_DEI_SEL]                  =  "TAG_C_DEI_SEL",3768	[VCAP_AF_TAG_C_PCP_SEL]                  =  "TAG_C_PCP_SEL",3769	[VCAP_AF_TAG_C_TPID_SEL]                 =  "TAG_C_TPID_SEL",3770	[VCAP_AF_TAG_C_VID_SEL]                  =  "TAG_C_VID_SEL",3771	[VCAP_AF_TYPE]                           =  "TYPE",3772	[VCAP_AF_UNTAG_VID_ENA]                  =  "UNTAG_VID_ENA",3773	[VCAP_AF_VID_A_VAL]                      =  "VID_A_VAL",3774	[VCAP_AF_VID_B_VAL]                      =  "VID_B_VAL",3775	[VCAP_AF_VID_C_VAL]                      =  "VID_C_VAL",3776	[VCAP_AF_VID_VAL]                        =  "VID_VAL",3777};3778 3779/* VCAPs */3780const struct vcap_info sparx5_vcaps[] = {3781	[VCAP_TYPE_IS0] = {3782		.name = "is0",3783		.rows = 1024,3784		.sw_count = 12,3785		.sw_width = 52,3786		.sticky_width = 1,3787		.act_width = 110,3788		.default_cnt = 140,3789		.require_cnt_dis = 0,3790		.version = 1,3791		.keyfield_set = is0_keyfield_set,3792		.keyfield_set_size = ARRAY_SIZE(is0_keyfield_set),3793		.actionfield_set = is0_actionfield_set,3794		.actionfield_set_size = ARRAY_SIZE(is0_actionfield_set),3795		.keyfield_set_map = is0_keyfield_set_map,3796		.keyfield_set_map_size = is0_keyfield_set_map_size,3797		.actionfield_set_map = is0_actionfield_set_map,3798		.actionfield_set_map_size = is0_actionfield_set_map_size,3799		.keyfield_set_typegroups = is0_keyfield_set_typegroups,3800		.actionfield_set_typegroups = is0_actionfield_set_typegroups,3801	},3802	[VCAP_TYPE_IS2] = {3803		.name = "is2",3804		.rows = 256,3805		.sw_count = 12,3806		.sw_width = 52,3807		.sticky_width = 1,3808		.act_width = 110,3809		.default_cnt = 73,3810		.require_cnt_dis = 0,3811		.version = 1,3812		.keyfield_set = is2_keyfield_set,3813		.keyfield_set_size = ARRAY_SIZE(is2_keyfield_set),3814		.actionfield_set = is2_actionfield_set,3815		.actionfield_set_size = ARRAY_SIZE(is2_actionfield_set),3816		.keyfield_set_map = is2_keyfield_set_map,3817		.keyfield_set_map_size = is2_keyfield_set_map_size,3818		.actionfield_set_map = is2_actionfield_set_map,3819		.actionfield_set_map_size = is2_actionfield_set_map_size,3820		.keyfield_set_typegroups = is2_keyfield_set_typegroups,3821		.actionfield_set_typegroups = is2_actionfield_set_typegroups,3822	},3823	[VCAP_TYPE_ES0] = {3824		.name = "es0",3825		.rows = 4096,3826		.sw_count = 1,3827		.sw_width = 52,3828		.sticky_width = 1,3829		.act_width = 489,3830		.default_cnt = 70,3831		.require_cnt_dis = 0,3832		.version = 1,3833		.keyfield_set = es0_keyfield_set,3834		.keyfield_set_size = ARRAY_SIZE(es0_keyfield_set),3835		.actionfield_set = es0_actionfield_set,3836		.actionfield_set_size = ARRAY_SIZE(es0_actionfield_set),3837		.keyfield_set_map = es0_keyfield_set_map,3838		.keyfield_set_map_size = es0_keyfield_set_map_size,3839		.actionfield_set_map = es0_actionfield_set_map,3840		.actionfield_set_map_size = es0_actionfield_set_map_size,3841		.keyfield_set_typegroups = es0_keyfield_set_typegroups,3842		.actionfield_set_typegroups = es0_actionfield_set_typegroups,3843	},3844	[VCAP_TYPE_ES2] = {3845		.name = "es2",3846		.rows = 1024,3847		.sw_count = 12,3848		.sw_width = 52,3849		.sticky_width = 1,3850		.act_width = 21,3851		.default_cnt = 74,3852		.require_cnt_dis = 0,3853		.version = 1,3854		.keyfield_set = es2_keyfield_set,3855		.keyfield_set_size = ARRAY_SIZE(es2_keyfield_set),3856		.actionfield_set = es2_actionfield_set,3857		.actionfield_set_size = ARRAY_SIZE(es2_actionfield_set),3858		.keyfield_set_map = es2_keyfield_set_map,3859		.keyfield_set_map_size = es2_keyfield_set_map_size,3860		.actionfield_set_map = es2_actionfield_set_map,3861		.actionfield_set_map_size = es2_actionfield_set_map_size,3862		.keyfield_set_typegroups = es2_keyfield_set_typegroups,3863		.actionfield_set_typegroups = es2_actionfield_set_typegroups,3864	},3865};3866 3867const struct vcap_statistics sparx5_vcap_stats = {3868	.name = "sparx5",3869	.count = 4,3870	.keyfield_set_names = vcap_keyfield_set_names,3871	.actionfield_set_names = vcap_actionfield_set_names,3872	.keyfield_names = vcap_keyfield_names,3873	.actionfield_names = vcap_actionfield_names,3874};3875