brintos / linux-shallow public Read only

1// SPDX-License-Identifier: BSD-3-Clause2/* Copyright (C) 2023 Microchip Technology Inc. and its subsidiaries.3 * Microchip VCAP test model interface for kunit testing4 */5 6/* This file is autogenerated by cml-utils 2023-02-10 11:16:00 +0100.7 * Commit ID: c30fb4bf0281cd4a7133bdab6682f9e43c872ada8 */9 10#include <linux/types.h>11#include <linux/kernel.h>12 13#include "vcap_api.h"14#include "vcap_model_kunit.h"15 16/* keyfields */17static const struct vcap_field is0_ll_full_keyfield[] = {18	[VCAP_KF_TYPE] = {19		.type = VCAP_FIELD_U32,20		.offset = 0,21		.width = 2,22	},23	[VCAP_KF_LOOKUP_FIRST_IS] = {24		.type = VCAP_FIELD_BIT,25		.offset = 2,26		.width = 1,27	},28	[VCAP_KF_IF_IGR_PORT] = {29		.type = VCAP_FIELD_U32,30		.offset = 3,31		.width = 7,32	},33	[VCAP_KF_8021Q_VLAN_TAGS] = {34		.type = VCAP_FIELD_U32,35		.offset = 10,36		.width = 3,37	},38	[VCAP_KF_8021Q_TPID0] = {39		.type = VCAP_FIELD_U32,40		.offset = 13,41		.width = 3,42	},43	[VCAP_KF_8021Q_PCP0] = {44		.type = VCAP_FIELD_U32,45		.offset = 16,46		.width = 3,47	},48	[VCAP_KF_8021Q_DEI0] = {49		.type = VCAP_FIELD_BIT,50		.offset = 19,51		.width = 1,52	},53	[VCAP_KF_8021Q_VID0] = {54		.type = VCAP_FIELD_U32,55		.offset = 20,56		.width = 12,57	},58	[VCAP_KF_8021Q_TPID1] = {59		.type = VCAP_FIELD_U32,60		.offset = 32,61		.width = 3,62	},63	[VCAP_KF_8021Q_PCP1] = {64		.type = VCAP_FIELD_U32,65		.offset = 35,66		.width = 3,67	},68	[VCAP_KF_8021Q_DEI1] = {69		.type = VCAP_FIELD_BIT,70		.offset = 38,71		.width = 1,72	},73	[VCAP_KF_8021Q_VID1] = {74		.type = VCAP_FIELD_U32,75		.offset = 39,76		.width = 12,77	},78	[VCAP_KF_8021Q_TPID2] = {79		.type = VCAP_FIELD_U32,80		.offset = 51,81		.width = 3,82	},83	[VCAP_KF_8021Q_PCP2] = {84		.type = VCAP_FIELD_U32,85		.offset = 54,86		.width = 3,87	},88	[VCAP_KF_8021Q_DEI2] = {89		.type = VCAP_FIELD_BIT,90		.offset = 57,91		.width = 1,92	},93	[VCAP_KF_8021Q_VID2] = {94		.type = VCAP_FIELD_U32,95		.offset = 58,96		.width = 12,97	},98	[VCAP_KF_L2_DMAC] = {99		.type = VCAP_FIELD_U48,100		.offset = 70,101		.width = 48,102	},103	[VCAP_KF_L2_SMAC] = {104		.type = VCAP_FIELD_U48,105		.offset = 118,106		.width = 48,107	},108	[VCAP_KF_ETYPE_LEN_IS] = {109		.type = VCAP_FIELD_BIT,110		.offset = 166,111		.width = 1,112	},113	[VCAP_KF_ETYPE] = {114		.type = VCAP_FIELD_U32,115		.offset = 167,116		.width = 16,117	},118	[VCAP_KF_IP_SNAP_IS] = {119		.type = VCAP_FIELD_BIT,120		.offset = 183,121		.width = 1,122	},123	[VCAP_KF_IP4_IS] = {124		.type = VCAP_FIELD_BIT,125		.offset = 184,126		.width = 1,127	},128	[VCAP_KF_L3_FRAGMENT_TYPE] = {129		.type = VCAP_FIELD_U32,130		.offset = 185,131		.width = 2,132	},133	[VCAP_KF_L3_FRAG_INVLD_L4_LEN] = {134		.type = VCAP_FIELD_BIT,135		.offset = 187,136		.width = 1,137	},138	[VCAP_KF_L3_OPTIONS_IS] = {139		.type = VCAP_FIELD_BIT,140		.offset = 188,141		.width = 1,142	},143	[VCAP_KF_L3_DSCP] = {144		.type = VCAP_FIELD_U32,145		.offset = 189,146		.width = 6,147	},148	[VCAP_KF_L3_IP4_DIP] = {149		.type = VCAP_FIELD_U32,150		.offset = 195,151		.width = 32,152	},153	[VCAP_KF_L3_IP4_SIP] = {154		.type = VCAP_FIELD_U32,155		.offset = 227,156		.width = 32,157	},158	[VCAP_KF_TCP_UDP_IS] = {159		.type = VCAP_FIELD_BIT,160		.offset = 259,161		.width = 1,162	},163	[VCAP_KF_TCP_IS] = {164		.type = VCAP_FIELD_BIT,165		.offset = 260,166		.width = 1,167	},168	[VCAP_KF_L4_SPORT] = {169		.type = VCAP_FIELD_U32,170		.offset = 261,171		.width = 16,172	},173	[VCAP_KF_L4_RNG] = {174		.type = VCAP_FIELD_U32,175		.offset = 277,176		.width = 8,177	},178};179 180static const struct vcap_field is0_normal_7tuple_keyfield[] = {181	[VCAP_KF_TYPE] = {182		.type = VCAP_FIELD_BIT,183		.offset = 0,184		.width = 1,185	},186	[VCAP_KF_LOOKUP_FIRST_IS] = {187		.type = VCAP_FIELD_BIT,188		.offset = 1,189		.width = 1,190	},191	[VCAP_KF_LOOKUP_GEN_IDX_SEL] = {192		.type = VCAP_FIELD_U32,193		.offset = 2,194		.width = 2,195	},196	[VCAP_KF_LOOKUP_GEN_IDX] = {197		.type = VCAP_FIELD_U32,198		.offset = 4,199		.width = 12,200	},201	[VCAP_KF_IF_IGR_PORT_MASK_SEL] = {202		.type = VCAP_FIELD_U32,203		.offset = 16,204		.width = 2,205	},206	[VCAP_KF_IF_IGR_PORT_MASK] = {207		.type = VCAP_FIELD_U72,208		.offset = 18,209		.width = 65,210	},211	[VCAP_KF_L2_MC_IS] = {212		.type = VCAP_FIELD_BIT,213		.offset = 83,214		.width = 1,215	},216	[VCAP_KF_L2_BC_IS] = {217		.type = VCAP_FIELD_BIT,218		.offset = 84,219		.width = 1,220	},221	[VCAP_KF_8021Q_VLAN_TAGS] = {222		.type = VCAP_FIELD_U32,223		.offset = 85,224		.width = 3,225	},226	[VCAP_KF_8021Q_TPID0] = {227		.type = VCAP_FIELD_U32,228		.offset = 88,229		.width = 3,230	},231	[VCAP_KF_8021Q_PCP0] = {232		.type = VCAP_FIELD_U32,233		.offset = 91,234		.width = 3,235	},236	[VCAP_KF_8021Q_DEI0] = {237		.type = VCAP_FIELD_BIT,238		.offset = 94,239		.width = 1,240	},241	[VCAP_KF_8021Q_VID0] = {242		.type = VCAP_FIELD_U32,243		.offset = 95,244		.width = 12,245	},246	[VCAP_KF_8021Q_TPID1] = {247		.type = VCAP_FIELD_U32,248		.offset = 107,249		.width = 3,250	},251	[VCAP_KF_8021Q_PCP1] = {252		.type = VCAP_FIELD_U32,253		.offset = 110,254		.width = 3,255	},256	[VCAP_KF_8021Q_DEI1] = {257		.type = VCAP_FIELD_BIT,258		.offset = 113,259		.width = 1,260	},261	[VCAP_KF_8021Q_VID1] = {262		.type = VCAP_FIELD_U32,263		.offset = 114,264		.width = 12,265	},266	[VCAP_KF_8021Q_TPID2] = {267		.type = VCAP_FIELD_U32,268		.offset = 126,269		.width = 3,270	},271	[VCAP_KF_8021Q_PCP2] = {272		.type = VCAP_FIELD_U32,273		.offset = 129,274		.width = 3,275	},276	[VCAP_KF_8021Q_DEI2] = {277		.type = VCAP_FIELD_BIT,278		.offset = 132,279		.width = 1,280	},281	[VCAP_KF_8021Q_VID2] = {282		.type = VCAP_FIELD_U32,283		.offset = 133,284		.width = 12,285	},286	[VCAP_KF_L2_DMAC] = {287		.type = VCAP_FIELD_U48,288		.offset = 145,289		.width = 48,290	},291	[VCAP_KF_L2_SMAC] = {292		.type = VCAP_FIELD_U48,293		.offset = 193,294		.width = 48,295	},296	[VCAP_KF_IP_MC_IS] = {297		.type = VCAP_FIELD_BIT,298		.offset = 241,299		.width = 1,300	},301	[VCAP_KF_ETYPE_LEN_IS] = {302		.type = VCAP_FIELD_BIT,303		.offset = 242,304		.width = 1,305	},306	[VCAP_KF_ETYPE] = {307		.type = VCAP_FIELD_U32,308		.offset = 243,309		.width = 16,310	},311	[VCAP_KF_IP_SNAP_IS] = {312		.type = VCAP_FIELD_BIT,313		.offset = 259,314		.width = 1,315	},316	[VCAP_KF_IP4_IS] = {317		.type = VCAP_FIELD_BIT,318		.offset = 260,319		.width = 1,320	},321	[VCAP_KF_L3_FRAGMENT_TYPE] = {322		.type = VCAP_FIELD_U32,323		.offset = 261,324		.width = 2,325	},326	[VCAP_KF_L3_FRAG_INVLD_L4_LEN] = {327		.type = VCAP_FIELD_BIT,328		.offset = 263,329		.width = 1,330	},331	[VCAP_KF_L3_OPTIONS_IS] = {332		.type = VCAP_FIELD_BIT,333		.offset = 264,334		.width = 1,335	},336	[VCAP_KF_L3_DSCP] = {337		.type = VCAP_FIELD_U32,338		.offset = 265,339		.width = 6,340	},341	[VCAP_KF_L3_IP6_DIP] = {342		.type = VCAP_FIELD_U128,343		.offset = 271,344		.width = 128,345	},346	[VCAP_KF_L3_IP6_SIP] = {347		.type = VCAP_FIELD_U128,348		.offset = 399,349		.width = 128,350	},351	[VCAP_KF_TCP_UDP_IS] = {352		.type = VCAP_FIELD_BIT,353		.offset = 527,354		.width = 1,355	},356	[VCAP_KF_TCP_IS] = {357		.type = VCAP_FIELD_BIT,358		.offset = 528,359		.width = 1,360	},361	[VCAP_KF_L4_SPORT] = {362		.type = VCAP_FIELD_U32,363		.offset = 529,364		.width = 16,365	},366	[VCAP_KF_L4_RNG] = {367		.type = VCAP_FIELD_U32,368		.offset = 545,369		.width = 8,370	},371};372 373static const struct vcap_field is0_normal_5tuple_ip4_keyfield[] = {374	[VCAP_KF_TYPE] = {375		.type = VCAP_FIELD_U32,376		.offset = 0,377		.width = 2,378	},379	[VCAP_KF_LOOKUP_FIRST_IS] = {380		.type = VCAP_FIELD_BIT,381		.offset = 2,382		.width = 1,383	},384	[VCAP_KF_LOOKUP_GEN_IDX_SEL] = {385		.type = VCAP_FIELD_U32,386		.offset = 3,387		.width = 2,388	},389	[VCAP_KF_LOOKUP_GEN_IDX] = {390		.type = VCAP_FIELD_U32,391		.offset = 5,392		.width = 12,393	},394	[VCAP_KF_IF_IGR_PORT_MASK_SEL] = {395		.type = VCAP_FIELD_U32,396		.offset = 17,397		.width = 2,398	},399	[VCAP_KF_IF_IGR_PORT_MASK] = {400		.type = VCAP_FIELD_U72,401		.offset = 19,402		.width = 65,403	},404	[VCAP_KF_L2_MC_IS] = {405		.type = VCAP_FIELD_BIT,406		.offset = 84,407		.width = 1,408	},409	[VCAP_KF_L2_BC_IS] = {410		.type = VCAP_FIELD_BIT,411		.offset = 85,412		.width = 1,413	},414	[VCAP_KF_8021Q_VLAN_TAGS] = {415		.type = VCAP_FIELD_U32,416		.offset = 86,417		.width = 3,418	},419	[VCAP_KF_8021Q_TPID0] = {420		.type = VCAP_FIELD_U32,421		.offset = 89,422		.width = 3,423	},424	[VCAP_KF_8021Q_PCP0] = {425		.type = VCAP_FIELD_U32,426		.offset = 92,427		.width = 3,428	},429	[VCAP_KF_8021Q_DEI0] = {430		.type = VCAP_FIELD_BIT,431		.offset = 95,432		.width = 1,433	},434	[VCAP_KF_8021Q_VID0] = {435		.type = VCAP_FIELD_U32,436		.offset = 96,437		.width = 12,438	},439	[VCAP_KF_8021Q_TPID1] = {440		.type = VCAP_FIELD_U32,441		.offset = 108,442		.width = 3,443	},444	[VCAP_KF_8021Q_PCP1] = {445		.type = VCAP_FIELD_U32,446		.offset = 111,447		.width = 3,448	},449	[VCAP_KF_8021Q_DEI1] = {450		.type = VCAP_FIELD_BIT,451		.offset = 114,452		.width = 1,453	},454	[VCAP_KF_8021Q_VID1] = {455		.type = VCAP_FIELD_U32,456		.offset = 115,457		.width = 12,458	},459	[VCAP_KF_8021Q_TPID2] = {460		.type = VCAP_FIELD_U32,461		.offset = 127,462		.width = 3,463	},464	[VCAP_KF_8021Q_PCP2] = {465		.type = VCAP_FIELD_U32,466		.offset = 130,467		.width = 3,468	},469	[VCAP_KF_8021Q_DEI2] = {470		.type = VCAP_FIELD_BIT,471		.offset = 133,472		.width = 1,473	},474	[VCAP_KF_8021Q_VID2] = {475		.type = VCAP_FIELD_U32,476		.offset = 134,477		.width = 12,478	},479	[VCAP_KF_IP_MC_IS] = {480		.type = VCAP_FIELD_BIT,481		.offset = 146,482		.width = 1,483	},484	[VCAP_KF_IP4_IS] = {485		.type = VCAP_FIELD_BIT,486		.offset = 147,487		.width = 1,488	},489	[VCAP_KF_L3_FRAGMENT_TYPE] = {490		.type = VCAP_FIELD_U32,491		.offset = 148,492		.width = 2,493	},494	[VCAP_KF_L3_FRAG_INVLD_L4_LEN] = {495		.type = VCAP_FIELD_BIT,496		.offset = 150,497		.width = 1,498	},499	[VCAP_KF_L3_OPTIONS_IS] = {500		.type = VCAP_FIELD_BIT,501		.offset = 151,502		.width = 1,503	},504	[VCAP_KF_L3_DSCP] = {505		.type = VCAP_FIELD_U32,506		.offset = 152,507		.width = 6,508	},509	[VCAP_KF_L3_IP4_DIP] = {510		.type = VCAP_FIELD_U32,511		.offset = 158,512		.width = 32,513	},514	[VCAP_KF_L3_IP4_SIP] = {515		.type = VCAP_FIELD_U32,516		.offset = 190,517		.width = 32,518	},519	[VCAP_KF_L3_IP_PROTO] = {520		.type = VCAP_FIELD_U32,521		.offset = 222,522		.width = 8,523	},524	[VCAP_KF_TCP_UDP_IS] = {525		.type = VCAP_FIELD_BIT,526		.offset = 230,527		.width = 1,528	},529	[VCAP_KF_TCP_IS] = {530		.type = VCAP_FIELD_BIT,531		.offset = 231,532		.width = 1,533	},534	[VCAP_KF_L4_RNG] = {535		.type = VCAP_FIELD_U32,536		.offset = 232,537		.width = 8,538	},539	[VCAP_KF_IP_PAYLOAD_5TUPLE] = {540		.type = VCAP_FIELD_U32,541		.offset = 240,542		.width = 32,543	},544};545 546static const struct vcap_field is0_pure_5tuple_ip4_keyfield[] = {547	[VCAP_KF_TYPE] = {548		.type = VCAP_FIELD_U32,549		.offset = 0,550		.width = 2,551	},552	[VCAP_KF_LOOKUP_FIRST_IS] = {553		.type = VCAP_FIELD_BIT,554		.offset = 2,555		.width = 1,556	},557	[VCAP_KF_LOOKUP_GEN_IDX_SEL] = {558		.type = VCAP_FIELD_U32,559		.offset = 3,560		.width = 2,561	},562	[VCAP_KF_LOOKUP_GEN_IDX] = {563		.type = VCAP_FIELD_U32,564		.offset = 5,565		.width = 12,566	},567	[VCAP_KF_L3_FRAGMENT_TYPE] = {568		.type = VCAP_FIELD_U32,569		.offset = 17,570		.width = 2,571	},572	[VCAP_KF_L3_FRAG_INVLD_L4_LEN] = {573		.type = VCAP_FIELD_BIT,574		.offset = 19,575		.width = 1,576	},577	[VCAP_KF_L3_OPTIONS_IS] = {578		.type = VCAP_FIELD_BIT,579		.offset = 20,580		.width = 1,581	},582	[VCAP_KF_L3_DSCP] = {583		.type = VCAP_FIELD_U32,584		.offset = 21,585		.width = 6,586	},587	[VCAP_KF_L3_IP4_DIP] = {588		.type = VCAP_FIELD_U32,589		.offset = 27,590		.width = 32,591	},592	[VCAP_KF_L3_IP4_SIP] = {593		.type = VCAP_FIELD_U32,594		.offset = 59,595		.width = 32,596	},597	[VCAP_KF_L3_IP_PROTO] = {598		.type = VCAP_FIELD_U32,599		.offset = 91,600		.width = 8,601	},602	[VCAP_KF_L4_RNG] = {603		.type = VCAP_FIELD_U32,604		.offset = 99,605		.width = 8,606	},607	[VCAP_KF_IP_PAYLOAD_5TUPLE] = {608		.type = VCAP_FIELD_U32,609		.offset = 107,610		.width = 32,611	},612};613 614static const struct vcap_field is0_etag_keyfield[] = {615	[VCAP_KF_TYPE] = {616		.type = VCAP_FIELD_U32,617		.offset = 0,618		.width = 2,619	},620	[VCAP_KF_LOOKUP_FIRST_IS] = {621		.type = VCAP_FIELD_BIT,622		.offset = 2,623		.width = 1,624	},625	[VCAP_KF_IF_IGR_PORT] = {626		.type = VCAP_FIELD_U32,627		.offset = 3,628		.width = 7,629	},630	[VCAP_KF_8021BR_E_TAGGED] = {631		.type = VCAP_FIELD_BIT,632		.offset = 10,633		.width = 1,634	},635	[VCAP_KF_8021BR_GRP] = {636		.type = VCAP_FIELD_U32,637		.offset = 11,638		.width = 2,639	},640	[VCAP_KF_8021BR_ECID_EXT] = {641		.type = VCAP_FIELD_U32,642		.offset = 13,643		.width = 8,644	},645	[VCAP_KF_8021BR_ECID_BASE] = {646		.type = VCAP_FIELD_U32,647		.offset = 21,648		.width = 12,649	},650	[VCAP_KF_8021BR_IGR_ECID_EXT] = {651		.type = VCAP_FIELD_U32,652		.offset = 33,653		.width = 8,654	},655	[VCAP_KF_8021BR_IGR_ECID_BASE] = {656		.type = VCAP_FIELD_U32,657		.offset = 41,658		.width = 12,659	},660};661 662static const struct vcap_field is2_mac_etype_keyfield[] = {663	[VCAP_KF_TYPE] = {664		.type = VCAP_FIELD_U32,665		.offset = 0,666		.width = 4,667	},668	[VCAP_KF_LOOKUP_FIRST_IS] = {669		.type = VCAP_FIELD_BIT,670		.offset = 4,671		.width = 1,672	},673	[VCAP_KF_LOOKUP_PAG] = {674		.type = VCAP_FIELD_U32,675		.offset = 5,676		.width = 8,677	},678	[VCAP_KF_IF_IGR_PORT_MASK_L3] = {679		.type = VCAP_FIELD_BIT,680		.offset = 13,681		.width = 1,682	},683	[VCAP_KF_IF_IGR_PORT_MASK_RNG] = {684		.type = VCAP_FIELD_U32,685		.offset = 14,686		.width = 4,687	},688	[VCAP_KF_IF_IGR_PORT_MASK_SEL] = {689		.type = VCAP_FIELD_U32,690		.offset = 18,691		.width = 2,692	},693	[VCAP_KF_IF_IGR_PORT_MASK] = {694		.type = VCAP_FIELD_U32,695		.offset = 20,696		.width = 32,697	},698	[VCAP_KF_L2_MC_IS] = {699		.type = VCAP_FIELD_BIT,700		.offset = 52,701		.width = 1,702	},703	[VCAP_KF_L2_BC_IS] = {704		.type = VCAP_FIELD_BIT,705		.offset = 53,706		.width = 1,707	},708	[VCAP_KF_8021Q_VLAN_TAGGED_IS] = {709		.type = VCAP_FIELD_BIT,710		.offset = 54,711		.width = 1,712	},713	[VCAP_KF_ISDX_GT0_IS] = {714		.type = VCAP_FIELD_BIT,715		.offset = 55,716		.width = 1,717	},718	[VCAP_KF_ISDX_CLS] = {719		.type = VCAP_FIELD_U32,720		.offset = 56,721		.width = 12,722	},723	[VCAP_KF_8021Q_VID_CLS] = {724		.type = VCAP_FIELD_U32,725		.offset = 68,726		.width = 13,727	},728	[VCAP_KF_8021Q_DEI_CLS] = {729		.type = VCAP_FIELD_BIT,730		.offset = 81,731		.width = 1,732	},733	[VCAP_KF_8021Q_PCP_CLS] = {734		.type = VCAP_FIELD_U32,735		.offset = 82,736		.width = 3,737	},738	[VCAP_KF_L2_FWD_IS] = {739		.type = VCAP_FIELD_BIT,740		.offset = 85,741		.width = 1,742	},743	[VCAP_KF_L3_RT_IS] = {744		.type = VCAP_FIELD_BIT,745		.offset = 88,746		.width = 1,747	},748	[VCAP_KF_L3_DST_IS] = {749		.type = VCAP_FIELD_BIT,750		.offset = 89,751		.width = 1,752	},753	[VCAP_KF_L2_DMAC] = {754		.type = VCAP_FIELD_U48,755		.offset = 90,756		.width = 48,757	},758	[VCAP_KF_L2_SMAC] = {759		.type = VCAP_FIELD_U48,760		.offset = 138,761		.width = 48,762	},763	[VCAP_KF_ETYPE_LEN_IS] = {764		.type = VCAP_FIELD_BIT,765		.offset = 186,766		.width = 1,767	},768	[VCAP_KF_ETYPE] = {769		.type = VCAP_FIELD_U32,770		.offset = 187,771		.width = 16,772	},773	[VCAP_KF_L2_PAYLOAD_ETYPE] = {774		.type = VCAP_FIELD_U64,775		.offset = 203,776		.width = 64,777	},778	[VCAP_KF_L4_RNG] = {779		.type = VCAP_FIELD_U32,780		.offset = 267,781		.width = 16,782	},783	[VCAP_KF_OAM_CCM_CNTS_EQ0] = {784		.type = VCAP_FIELD_BIT,785		.offset = 283,786		.width = 1,787	},788	[VCAP_KF_OAM_Y1731_IS] = {789		.type = VCAP_FIELD_BIT,790		.offset = 284,791		.width = 1,792	},793};794 795static const struct vcap_field is2_arp_keyfield[] = {796	[VCAP_KF_TYPE] = {797		.type = VCAP_FIELD_U32,798		.offset = 0,799		.width = 4,800	},801	[VCAP_KF_LOOKUP_FIRST_IS] = {802		.type = VCAP_FIELD_BIT,803		.offset = 4,804		.width = 1,805	},806	[VCAP_KF_LOOKUP_PAG] = {807		.type = VCAP_FIELD_U32,808		.offset = 5,809		.width = 8,810	},811	[VCAP_KF_IF_IGR_PORT_MASK_L3] = {812		.type = VCAP_FIELD_BIT,813		.offset = 13,814		.width = 1,815	},816	[VCAP_KF_IF_IGR_PORT_MASK_RNG] = {817		.type = VCAP_FIELD_U32,818		.offset = 14,819		.width = 4,820	},821	[VCAP_KF_IF_IGR_PORT_MASK_SEL] = {822		.type = VCAP_FIELD_U32,823		.offset = 18,824		.width = 2,825	},826	[VCAP_KF_IF_IGR_PORT_MASK] = {827		.type = VCAP_FIELD_U32,828		.offset = 20,829		.width = 32,830	},831	[VCAP_KF_L2_MC_IS] = {832		.type = VCAP_FIELD_BIT,833		.offset = 52,834		.width = 1,835	},836	[VCAP_KF_L2_BC_IS] = {837		.type = VCAP_FIELD_BIT,838		.offset = 53,839		.width = 1,840	},841	[VCAP_KF_8021Q_VLAN_TAGGED_IS] = {842		.type = VCAP_FIELD_BIT,843		.offset = 54,844		.width = 1,845	},846	[VCAP_KF_ISDX_GT0_IS] = {847		.type = VCAP_FIELD_BIT,848		.offset = 55,849		.width = 1,850	},851	[VCAP_KF_ISDX_CLS] = {852		.type = VCAP_FIELD_U32,853		.offset = 56,854		.width = 12,855	},856	[VCAP_KF_8021Q_VID_CLS] = {857		.type = VCAP_FIELD_U32,858		.offset = 68,859		.width = 13,860	},861	[VCAP_KF_8021Q_DEI_CLS] = {862		.type = VCAP_FIELD_BIT,863		.offset = 81,864		.width = 1,865	},866	[VCAP_KF_8021Q_PCP_CLS] = {867		.type = VCAP_FIELD_U32,868		.offset = 82,869		.width = 3,870	},871	[VCAP_KF_L2_FWD_IS] = {872		.type = VCAP_FIELD_BIT,873		.offset = 85,874		.width = 1,875	},876	[VCAP_KF_L2_SMAC] = {877		.type = VCAP_FIELD_U48,878		.offset = 86,879		.width = 48,880	},881	[VCAP_KF_ARP_ADDR_SPACE_OK_IS] = {882		.type = VCAP_FIELD_BIT,883		.offset = 134,884		.width = 1,885	},886	[VCAP_KF_ARP_PROTO_SPACE_OK_IS] = {887		.type = VCAP_FIELD_BIT,888		.offset = 135,889		.width = 1,890	},891	[VCAP_KF_ARP_LEN_OK_IS] = {892		.type = VCAP_FIELD_BIT,893		.offset = 136,894		.width = 1,895	},896	[VCAP_KF_ARP_TGT_MATCH_IS] = {897		.type = VCAP_FIELD_BIT,898		.offset = 137,899		.width = 1,900	},901	[VCAP_KF_ARP_SENDER_MATCH_IS] = {902		.type = VCAP_FIELD_BIT,903		.offset = 138,904		.width = 1,905	},906	[VCAP_KF_ARP_OPCODE_UNKNOWN_IS] = {907		.type = VCAP_FIELD_BIT,908		.offset = 139,909		.width = 1,910	},911	[VCAP_KF_ARP_OPCODE] = {912		.type = VCAP_FIELD_U32,913		.offset = 140,914		.width = 2,915	},916	[VCAP_KF_L3_IP4_DIP] = {917		.type = VCAP_FIELD_U32,918		.offset = 142,919		.width = 32,920	},921	[VCAP_KF_L3_IP4_SIP] = {922		.type = VCAP_FIELD_U32,923		.offset = 174,924		.width = 32,925	},926	[VCAP_KF_L3_DIP_EQ_SIP_IS] = {927		.type = VCAP_FIELD_BIT,928		.offset = 206,929		.width = 1,930	},931	[VCAP_KF_L4_RNG] = {932		.type = VCAP_FIELD_U32,933		.offset = 207,934		.width = 16,935	},936};937 938static const struct vcap_field is2_ip4_tcp_udp_keyfield[] = {939	[VCAP_KF_TYPE] = {940		.type = VCAP_FIELD_U32,941		.offset = 0,942		.width = 4,943	},944	[VCAP_KF_LOOKUP_FIRST_IS] = {945		.type = VCAP_FIELD_BIT,946		.offset = 4,947		.width = 1,948	},949	[VCAP_KF_LOOKUP_PAG] = {950		.type = VCAP_FIELD_U32,951		.offset = 5,952		.width = 8,953	},954	[VCAP_KF_IF_IGR_PORT_MASK_L3] = {955		.type = VCAP_FIELD_BIT,956		.offset = 13,957		.width = 1,958	},959	[VCAP_KF_IF_IGR_PORT_MASK_RNG] = {960		.type = VCAP_FIELD_U32,961		.offset = 14,962		.width = 4,963	},964	[VCAP_KF_IF_IGR_PORT_MASK_SEL] = {965		.type = VCAP_FIELD_U32,966		.offset = 18,967		.width = 2,968	},969	[VCAP_KF_IF_IGR_PORT_MASK] = {970		.type = VCAP_FIELD_U32,971		.offset = 20,972		.width = 32,973	},974	[VCAP_KF_L2_MC_IS] = {975		.type = VCAP_FIELD_BIT,976		.offset = 52,977		.width = 1,978	},979	[VCAP_KF_L2_BC_IS] = {980		.type = VCAP_FIELD_BIT,981		.offset = 53,982		.width = 1,983	},984	[VCAP_KF_8021Q_VLAN_TAGGED_IS] = {985		.type = VCAP_FIELD_BIT,986		.offset = 54,987		.width = 1,988	},989	[VCAP_KF_ISDX_GT0_IS] = {990		.type = VCAP_FIELD_BIT,991		.offset = 55,992		.width = 1,993	},994	[VCAP_KF_ISDX_CLS] = {995		.type = VCAP_FIELD_U32,996		.offset = 56,997		.width = 12,998	},999	[VCAP_KF_8021Q_VID_CLS] = {1000		.type = VCAP_FIELD_U32,1001		.offset = 68,1002		.width = 13,1003	},1004	[VCAP_KF_8021Q_DEI_CLS] = {1005		.type = VCAP_FIELD_BIT,1006		.offset = 81,1007		.width = 1,1008	},1009	[VCAP_KF_8021Q_PCP_CLS] = {1010		.type = VCAP_FIELD_U32,1011		.offset = 82,1012		.width = 3,1013	},1014	[VCAP_KF_L2_FWD_IS] = {1015		.type = VCAP_FIELD_BIT,1016		.offset = 85,1017		.width = 1,1018	},1019	[VCAP_KF_L3_RT_IS] = {1020		.type = VCAP_FIELD_BIT,1021		.offset = 88,1022		.width = 1,1023	},1024	[VCAP_KF_L3_DST_IS] = {1025		.type = VCAP_FIELD_BIT,1026		.offset = 89,1027		.width = 1,1028	},1029	[VCAP_KF_IP4_IS] = {1030		.type = VCAP_FIELD_BIT,1031		.offset = 90,1032		.width = 1,1033	},1034	[VCAP_KF_L3_FRAGMENT_TYPE] = {1035		.type = VCAP_FIELD_U32,1036		.offset = 91,1037		.width = 2,1038	},1039	[VCAP_KF_L3_FRAG_INVLD_L4_LEN] = {1040		.type = VCAP_FIELD_BIT,1041		.offset = 93,1042		.width = 1,1043	},1044	[VCAP_KF_L3_OPTIONS_IS] = {1045		.type = VCAP_FIELD_BIT,1046		.offset = 94,1047		.width = 1,1048	},1049	[VCAP_KF_L3_TTL_GT0] = {1050		.type = VCAP_FIELD_BIT,1051		.offset = 95,1052		.width = 1,1053	},1054	[VCAP_KF_L3_TOS] = {1055		.type = VCAP_FIELD_U32,1056		.offset = 96,1057		.width = 8,1058	},1059	[VCAP_KF_L3_IP4_DIP] = {1060		.type = VCAP_FIELD_U32,1061		.offset = 104,1062		.width = 32,1063	},1064	[VCAP_KF_L3_IP4_SIP] = {1065		.type = VCAP_FIELD_U32,1066		.offset = 136,1067		.width = 32,1068	},1069	[VCAP_KF_L3_DIP_EQ_SIP_IS] = {1070		.type = VCAP_FIELD_BIT,1071		.offset = 168,1072		.width = 1,1073	},1074	[VCAP_KF_TCP_IS] = {1075		.type = VCAP_FIELD_BIT,1076		.offset = 169,1077		.width = 1,1078	},1079	[VCAP_KF_L4_DPORT] = {1080		.type = VCAP_FIELD_U32,1081		.offset = 170,1082		.width = 16,1083	},1084	[VCAP_KF_L4_SPORT] = {1085		.type = VCAP_FIELD_U32,1086		.offset = 186,1087		.width = 16,1088	},1089	[VCAP_KF_L4_RNG] = {1090		.type = VCAP_FIELD_U32,1091		.offset = 202,1092		.width = 16,1093	},1094	[VCAP_KF_L4_SPORT_EQ_DPORT_IS] = {1095		.type = VCAP_FIELD_BIT,1096		.offset = 218,1097		.width = 1,1098	},1099	[VCAP_KF_L4_SEQUENCE_EQ0_IS] = {1100		.type = VCAP_FIELD_BIT,1101		.offset = 219,1102		.width = 1,1103	},1104	[VCAP_KF_L4_FIN] = {1105		.type = VCAP_FIELD_BIT,1106		.offset = 220,1107		.width = 1,1108	},1109	[VCAP_KF_L4_SYN] = {1110		.type = VCAP_FIELD_BIT,1111		.offset = 221,1112		.width = 1,1113	},1114	[VCAP_KF_L4_RST] = {1115		.type = VCAP_FIELD_BIT,1116		.offset = 222,1117		.width = 1,1118	},1119	[VCAP_KF_L4_PSH] = {1120		.type = VCAP_FIELD_BIT,1121		.offset = 223,1122		.width = 1,1123	},1124	[VCAP_KF_L4_ACK] = {1125		.type = VCAP_FIELD_BIT,1126		.offset = 224,1127		.width = 1,1128	},1129	[VCAP_KF_L4_URG] = {1130		.type = VCAP_FIELD_BIT,1131		.offset = 225,1132		.width = 1,1133	},1134	[VCAP_KF_L4_PAYLOAD] = {1135		.type = VCAP_FIELD_U64,1136		.offset = 226,1137		.width = 64,1138	},1139};1140 1141static const struct vcap_field is2_ip4_other_keyfield[] = {1142	[VCAP_KF_TYPE] = {1143		.type = VCAP_FIELD_U32,1144		.offset = 0,1145		.width = 4,1146	},1147	[VCAP_KF_LOOKUP_FIRST_IS] = {1148		.type = VCAP_FIELD_BIT,1149		.offset = 4,1150		.width = 1,1151	},1152	[VCAP_KF_LOOKUP_PAG] = {1153		.type = VCAP_FIELD_U32,1154		.offset = 5,1155		.width = 8,1156	},1157	[VCAP_KF_IF_IGR_PORT_MASK_L3] = {1158		.type = VCAP_FIELD_BIT,1159		.offset = 13,1160		.width = 1,1161	},1162	[VCAP_KF_IF_IGR_PORT_MASK_RNG] = {1163		.type = VCAP_FIELD_U32,1164		.offset = 14,1165		.width = 4,1166	},1167	[VCAP_KF_IF_IGR_PORT_MASK_SEL] = {1168		.type = VCAP_FIELD_U32,1169		.offset = 18,1170		.width = 2,1171	},1172	[VCAP_KF_IF_IGR_PORT_MASK] = {1173		.type = VCAP_FIELD_U32,1174		.offset = 20,1175		.width = 32,1176	},1177	[VCAP_KF_L2_MC_IS] = {1178		.type = VCAP_FIELD_BIT,1179		.offset = 52,1180		.width = 1,1181	},1182	[VCAP_KF_L2_BC_IS] = {1183		.type = VCAP_FIELD_BIT,1184		.offset = 53,1185		.width = 1,1186	},1187	[VCAP_KF_8021Q_VLAN_TAGGED_IS] = {1188		.type = VCAP_FIELD_BIT,1189		.offset = 54,1190		.width = 1,1191	},1192	[VCAP_KF_ISDX_GT0_IS] = {1193		.type = VCAP_FIELD_BIT,1194		.offset = 55,1195		.width = 1,1196	},1197	[VCAP_KF_ISDX_CLS] = {1198		.type = VCAP_FIELD_U32,1199		.offset = 56,1200		.width = 12,1201	},1202	[VCAP_KF_8021Q_VID_CLS] = {1203		.type = VCAP_FIELD_U32,1204		.offset = 68,1205		.width = 13,1206	},1207	[VCAP_KF_8021Q_DEI_CLS] = {1208		.type = VCAP_FIELD_BIT,1209		.offset = 81,1210		.width = 1,1211	},1212	[VCAP_KF_8021Q_PCP_CLS] = {1213		.type = VCAP_FIELD_U32,1214		.offset = 82,1215		.width = 3,1216	},1217	[VCAP_KF_L2_FWD_IS] = {1218		.type = VCAP_FIELD_BIT,1219		.offset = 85,1220		.width = 1,1221	},1222	[VCAP_KF_L3_RT_IS] = {1223		.type = VCAP_FIELD_BIT,1224		.offset = 88,1225		.width = 1,1226	},1227	[VCAP_KF_L3_DST_IS] = {1228		.type = VCAP_FIELD_BIT,1229		.offset = 89,1230		.width = 1,1231	},1232	[VCAP_KF_IP4_IS] = {1233		.type = VCAP_FIELD_BIT,1234		.offset = 90,1235		.width = 1,1236	},1237	[VCAP_KF_L3_FRAGMENT_TYPE] = {1238		.type = VCAP_FIELD_U32,1239		.offset = 91,1240		.width = 2,1241	},1242	[VCAP_KF_L3_FRAG_INVLD_L4_LEN] = {1243		.type = VCAP_FIELD_BIT,1244		.offset = 93,1245		.width = 1,1246	},1247	[VCAP_KF_L3_OPTIONS_IS] = {1248		.type = VCAP_FIELD_BIT,1249		.offset = 94,1250		.width = 1,1251	},1252	[VCAP_KF_L3_TTL_GT0] = {1253		.type = VCAP_FIELD_BIT,1254		.offset = 95,1255		.width = 1,1256	},1257	[VCAP_KF_L3_TOS] = {1258		.type = VCAP_FIELD_U32,1259		.offset = 96,1260		.width = 8,1261	},1262	[VCAP_KF_L3_IP4_DIP] = {1263		.type = VCAP_FIELD_U32,1264		.offset = 104,1265		.width = 32,1266	},1267	[VCAP_KF_L3_IP4_SIP] = {1268		.type = VCAP_FIELD_U32,1269		.offset = 136,1270		.width = 32,1271	},1272	[VCAP_KF_L3_DIP_EQ_SIP_IS] = {1273		.type = VCAP_FIELD_BIT,1274		.offset = 168,1275		.width = 1,1276	},1277	[VCAP_KF_L3_IP_PROTO] = {1278		.type = VCAP_FIELD_U32,1279		.offset = 169,1280		.width = 8,1281	},1282	[VCAP_KF_L4_RNG] = {1283		.type = VCAP_FIELD_U32,1284		.offset = 177,1285		.width = 16,1286	},1287	[VCAP_KF_L3_PAYLOAD] = {1288		.type = VCAP_FIELD_U112,1289		.offset = 193,1290		.width = 96,1291	},1292};1293 1294static const struct vcap_field is2_ip6_std_keyfield[] = {1295	[VCAP_KF_TYPE] = {1296		.type = VCAP_FIELD_U32,1297		.offset = 0,1298		.width = 4,1299	},1300	[VCAP_KF_LOOKUP_FIRST_IS] = {1301		.type = VCAP_FIELD_BIT,1302		.offset = 4,1303		.width = 1,1304	},1305	[VCAP_KF_LOOKUP_PAG] = {1306		.type = VCAP_FIELD_U32,1307		.offset = 5,1308		.width = 8,1309	},1310	[VCAP_KF_IF_IGR_PORT_MASK_L3] = {1311		.type = VCAP_FIELD_BIT,1312		.offset = 13,1313		.width = 1,1314	},1315	[VCAP_KF_IF_IGR_PORT_MASK_RNG] = {1316		.type = VCAP_FIELD_U32,1317		.offset = 14,1318		.width = 4,1319	},1320	[VCAP_KF_IF_IGR_PORT_MASK_SEL] = {1321		.type = VCAP_FIELD_U32,1322		.offset = 18,1323		.width = 2,1324	},1325	[VCAP_KF_IF_IGR_PORT_MASK] = {1326		.type = VCAP_FIELD_U32,1327		.offset = 20,1328		.width = 32,1329	},1330	[VCAP_KF_L2_MC_IS] = {1331		.type = VCAP_FIELD_BIT,1332		.offset = 52,1333		.width = 1,1334	},1335	[VCAP_KF_L2_BC_IS] = {1336		.type = VCAP_FIELD_BIT,1337		.offset = 53,1338		.width = 1,1339	},1340	[VCAP_KF_8021Q_VLAN_TAGGED_IS] = {1341		.type = VCAP_FIELD_BIT,1342		.offset = 54,1343		.width = 1,1344	},1345	[VCAP_KF_ISDX_GT0_IS] = {1346		.type = VCAP_FIELD_BIT,1347		.offset = 55,1348		.width = 1,1349	},1350	[VCAP_KF_ISDX_CLS] = {1351		.type = VCAP_FIELD_U32,1352		.offset = 56,1353		.width = 12,1354	},1355	[VCAP_KF_8021Q_VID_CLS] = {1356		.type = VCAP_FIELD_U32,1357		.offset = 68,1358		.width = 13,1359	},1360	[VCAP_KF_8021Q_DEI_CLS] = {1361		.type = VCAP_FIELD_BIT,1362		.offset = 81,1363		.width = 1,1364	},1365	[VCAP_KF_8021Q_PCP_CLS] = {1366		.type = VCAP_FIELD_U32,1367		.offset = 82,1368		.width = 3,1369	},1370	[VCAP_KF_L2_FWD_IS] = {1371		.type = VCAP_FIELD_BIT,1372		.offset = 85,1373		.width = 1,1374	},1375	[VCAP_KF_L3_RT_IS] = {1376		.type = VCAP_FIELD_BIT,1377		.offset = 88,1378		.width = 1,1379	},1380	[VCAP_KF_L3_TTL_GT0] = {1381		.type = VCAP_FIELD_BIT,1382		.offset = 90,1383		.width = 1,1384	},1385	[VCAP_KF_L3_IP6_SIP] = {1386		.type = VCAP_FIELD_U128,1387		.offset = 91,1388		.width = 128,1389	},1390	[VCAP_KF_L3_DIP_EQ_SIP_IS] = {1391		.type = VCAP_FIELD_BIT,1392		.offset = 219,1393		.width = 1,1394	},1395	[VCAP_KF_L3_IP_PROTO] = {1396		.type = VCAP_FIELD_U32,1397		.offset = 220,1398		.width = 8,1399	},1400	[VCAP_KF_L4_RNG] = {1401		.type = VCAP_FIELD_U32,1402		.offset = 228,1403		.width = 16,1404	},1405	[VCAP_KF_L3_PAYLOAD] = {1406		.type = VCAP_FIELD_U48,1407		.offset = 244,1408		.width = 40,1409	},1410};1411 1412static const struct vcap_field is2_ip_7tuple_keyfield[] = {1413	[VCAP_KF_TYPE] = {1414		.type = VCAP_FIELD_U32,1415		.offset = 0,1416		.width = 2,1417	},1418	[VCAP_KF_LOOKUP_FIRST_IS] = {1419		.type = VCAP_FIELD_BIT,1420		.offset = 2,1421		.width = 1,1422	},1423	[VCAP_KF_LOOKUP_PAG] = {1424		.type = VCAP_FIELD_U32,1425		.offset = 3,1426		.width = 8,1427	},1428	[VCAP_KF_IF_IGR_PORT_MASK_L3] = {1429		.type = VCAP_FIELD_BIT,1430		.offset = 11,1431		.width = 1,1432	},1433	[VCAP_KF_IF_IGR_PORT_MASK_RNG] = {1434		.type = VCAP_FIELD_U32,1435		.offset = 12,1436		.width = 4,1437	},1438	[VCAP_KF_IF_IGR_PORT_MASK_SEL] = {1439		.type = VCAP_FIELD_U32,1440		.offset = 16,1441		.width = 2,1442	},1443	[VCAP_KF_IF_IGR_PORT_MASK] = {1444		.type = VCAP_FIELD_U72,1445		.offset = 18,1446		.width = 65,1447	},1448	[VCAP_KF_L2_MC_IS] = {1449		.type = VCAP_FIELD_BIT,1450		.offset = 83,1451		.width = 1,1452	},1453	[VCAP_KF_L2_BC_IS] = {1454		.type = VCAP_FIELD_BIT,1455		.offset = 84,1456		.width = 1,1457	},1458	[VCAP_KF_8021Q_VLAN_TAGGED_IS] = {1459		.type = VCAP_FIELD_BIT,1460		.offset = 85,1461		.width = 1,1462	},1463	[VCAP_KF_ISDX_GT0_IS] = {1464		.type = VCAP_FIELD_BIT,1465		.offset = 86,1466		.width = 1,1467	},1468	[VCAP_KF_ISDX_CLS] = {1469		.type = VCAP_FIELD_U32,1470		.offset = 87,1471		.width = 12,1472	},1473	[VCAP_KF_8021Q_VID_CLS] = {1474		.type = VCAP_FIELD_U32,1475		.offset = 99,1476		.width = 13,1477	},1478	[VCAP_KF_8021Q_DEI_CLS] = {1479		.type = VCAP_FIELD_BIT,1480		.offset = 112,1481		.width = 1,1482	},1483	[VCAP_KF_8021Q_PCP_CLS] = {1484		.type = VCAP_FIELD_U32,1485		.offset = 113,1486		.width = 3,1487	},1488	[VCAP_KF_L2_FWD_IS] = {1489		.type = VCAP_FIELD_BIT,1490		.offset = 116,1491		.width = 1,1492	},1493	[VCAP_KF_L3_RT_IS] = {1494		.type = VCAP_FIELD_BIT,1495		.offset = 119,1496		.width = 1,1497	},1498	[VCAP_KF_L3_DST_IS] = {1499		.type = VCAP_FIELD_BIT,1500		.offset = 120,1501		.width = 1,1502	},1503	[VCAP_KF_L2_DMAC] = {1504		.type = VCAP_FIELD_U48,1505		.offset = 121,1506		.width = 48,1507	},1508	[VCAP_KF_L2_SMAC] = {1509		.type = VCAP_FIELD_U48,1510		.offset = 169,1511		.width = 48,1512	},1513	[VCAP_KF_IP4_IS] = {1514		.type = VCAP_FIELD_BIT,1515		.offset = 217,1516		.width = 1,1517	},1518	[VCAP_KF_L3_TTL_GT0] = {1519		.type = VCAP_FIELD_BIT,1520		.offset = 218,1521		.width = 1,1522	},1523	[VCAP_KF_L3_TOS] = {1524		.type = VCAP_FIELD_U32,1525		.offset = 219,1526		.width = 8,1527	},1528	[VCAP_KF_L3_IP6_DIP] = {1529		.type = VCAP_FIELD_U128,1530		.offset = 227,1531		.width = 128,1532	},1533	[VCAP_KF_L3_IP6_SIP] = {1534		.type = VCAP_FIELD_U128,1535		.offset = 355,1536		.width = 128,1537	},1538	[VCAP_KF_L3_DIP_EQ_SIP_IS] = {1539		.type = VCAP_FIELD_BIT,1540		.offset = 483,1541		.width = 1,1542	},1543	[VCAP_KF_TCP_UDP_IS] = {1544		.type = VCAP_FIELD_BIT,1545		.offset = 484,1546		.width = 1,1547	},1548	[VCAP_KF_TCP_IS] = {1549		.type = VCAP_FIELD_BIT,1550		.offset = 485,1551		.width = 1,1552	},1553	[VCAP_KF_L4_DPORT] = {1554		.type = VCAP_FIELD_U32,1555		.offset = 486,1556		.width = 16,1557	},1558	[VCAP_KF_L4_SPORT] = {1559		.type = VCAP_FIELD_U32,1560		.offset = 502,1561		.width = 16,1562	},1563	[VCAP_KF_L4_RNG] = {1564		.type = VCAP_FIELD_U32,1565		.offset = 518,1566		.width = 16,1567	},1568	[VCAP_KF_L4_SPORT_EQ_DPORT_IS] = {1569		.type = VCAP_FIELD_BIT,1570		.offset = 534,1571		.width = 1,1572	},1573	[VCAP_KF_L4_SEQUENCE_EQ0_IS] = {1574		.type = VCAP_FIELD_BIT,1575		.offset = 535,1576		.width = 1,1577	},1578	[VCAP_KF_L4_FIN] = {1579		.type = VCAP_FIELD_BIT,1580		.offset = 536,1581		.width = 1,1582	},1583	[VCAP_KF_L4_SYN] = {1584		.type = VCAP_FIELD_BIT,1585		.offset = 537,1586		.width = 1,1587	},1588	[VCAP_KF_L4_RST] = {1589		.type = VCAP_FIELD_BIT,1590		.offset = 538,1591		.width = 1,1592	},1593	[VCAP_KF_L4_PSH] = {1594		.type = VCAP_FIELD_BIT,1595		.offset = 539,1596		.width = 1,1597	},1598	[VCAP_KF_L4_ACK] = {1599		.type = VCAP_FIELD_BIT,1600		.offset = 540,1601		.width = 1,1602	},1603	[VCAP_KF_L4_URG] = {1604		.type = VCAP_FIELD_BIT,1605		.offset = 541,1606		.width = 1,1607	},1608	[VCAP_KF_L4_PAYLOAD] = {1609		.type = VCAP_FIELD_U64,1610		.offset = 542,1611		.width = 64,1612	},1613};1614 1615static const struct vcap_field es2_mac_etype_keyfield[] = {1616	[VCAP_KF_TYPE] = {1617		.type = VCAP_FIELD_U32,1618		.offset = 0,1619		.width = 3,1620	},1621	[VCAP_KF_LOOKUP_FIRST_IS] = {1622		.type = VCAP_FIELD_BIT,1623		.offset = 3,1624		.width = 1,1625	},1626	[VCAP_KF_L2_MC_IS] = {1627		.type = VCAP_FIELD_BIT,1628		.offset = 13,1629		.width = 1,1630	},1631	[VCAP_KF_L2_BC_IS] = {1632		.type = VCAP_FIELD_BIT,1633		.offset = 14,1634		.width = 1,1635	},1636	[VCAP_KF_ISDX_GT0_IS] = {1637		.type = VCAP_FIELD_BIT,1638		.offset = 15,1639		.width = 1,1640	},1641	[VCAP_KF_ISDX_CLS] = {1642		.type = VCAP_FIELD_U32,1643		.offset = 16,1644		.width = 12,1645	},1646	[VCAP_KF_8021Q_VLAN_TAGGED_IS] = {1647		.type = VCAP_FIELD_BIT,1648		.offset = 28,1649		.width = 1,1650	},1651	[VCAP_KF_8021Q_VID_CLS] = {1652		.type = VCAP_FIELD_U32,1653		.offset = 29,1654		.width = 13,1655	},1656	[VCAP_KF_IF_EGR_PORT_MASK_RNG] = {1657		.type = VCAP_FIELD_U32,1658		.offset = 42,1659		.width = 3,1660	},1661	[VCAP_KF_IF_EGR_PORT_MASK] = {1662		.type = VCAP_FIELD_U32,1663		.offset = 45,1664		.width = 32,1665	},1666	[VCAP_KF_IF_IGR_PORT_SEL] = {1667		.type = VCAP_FIELD_BIT,1668		.offset = 77,1669		.width = 1,1670	},1671	[VCAP_KF_IF_IGR_PORT] = {1672		.type = VCAP_FIELD_U32,1673		.offset = 78,1674		.width = 9,1675	},1676	[VCAP_KF_8021Q_PCP_CLS] = {1677		.type = VCAP_FIELD_U32,1678		.offset = 87,1679		.width = 3,1680	},1681	[VCAP_KF_8021Q_DEI_CLS] = {1682		.type = VCAP_FIELD_BIT,1683		.offset = 90,1684		.width = 1,1685	},1686	[VCAP_KF_COSID_CLS] = {1687		.type = VCAP_FIELD_U32,1688		.offset = 91,1689		.width = 3,1690	},1691	[VCAP_KF_L3_DPL_CLS] = {1692		.type = VCAP_FIELD_BIT,1693		.offset = 94,1694		.width = 1,1695	},1696	[VCAP_KF_L3_RT_IS] = {1697		.type = VCAP_FIELD_BIT,1698		.offset = 95,1699		.width = 1,1700	},1701	[VCAP_KF_L2_DMAC] = {1702		.type = VCAP_FIELD_U48,1703		.offset = 99,1704		.width = 48,1705	},1706	[VCAP_KF_L2_SMAC] = {1707		.type = VCAP_FIELD_U48,1708		.offset = 147,1709		.width = 48,1710	},1711	[VCAP_KF_ETYPE_LEN_IS] = {1712		.type = VCAP_FIELD_BIT,1713		.offset = 195,1714		.width = 1,1715	},1716	[VCAP_KF_ETYPE] = {1717		.type = VCAP_FIELD_U32,1718		.offset = 196,1719		.width = 16,1720	},1721	[VCAP_KF_L2_PAYLOAD_ETYPE] = {1722		.type = VCAP_FIELD_U64,1723		.offset = 212,1724		.width = 64,1725	},1726	[VCAP_KF_OAM_CCM_CNTS_EQ0] = {1727		.type = VCAP_FIELD_BIT,1728		.offset = 276,1729		.width = 1,1730	},1731	[VCAP_KF_OAM_Y1731_IS] = {1732		.type = VCAP_FIELD_BIT,1733		.offset = 277,1734		.width = 1,1735	},1736};1737 1738static const struct vcap_field es2_arp_keyfield[] = {1739	[VCAP_KF_TYPE] = {1740		.type = VCAP_FIELD_U32,1741		.offset = 0,1742		.width = 3,1743	},1744	[VCAP_KF_LOOKUP_FIRST_IS] = {1745		.type = VCAP_FIELD_BIT,1746		.offset = 3,1747		.width = 1,1748	},1749	[VCAP_KF_L2_MC_IS] = {1750		.type = VCAP_FIELD_BIT,1751		.offset = 13,1752		.width = 1,1753	},1754	[VCAP_KF_L2_BC_IS] = {1755		.type = VCAP_FIELD_BIT,1756		.offset = 14,1757		.width = 1,1758	},1759	[VCAP_KF_ISDX_GT0_IS] = {1760		.type = VCAP_FIELD_BIT,1761		.offset = 15,1762		.width = 1,1763	},1764	[VCAP_KF_ISDX_CLS] = {1765		.type = VCAP_FIELD_U32,1766		.offset = 16,1767		.width = 12,1768	},1769	[VCAP_KF_8021Q_VLAN_TAGGED_IS] = {1770		.type = VCAP_FIELD_BIT,1771		.offset = 28,1772		.width = 1,1773	},1774	[VCAP_KF_8021Q_VID_CLS] = {1775		.type = VCAP_FIELD_U32,1776		.offset = 29,1777		.width = 13,1778	},1779	[VCAP_KF_IF_EGR_PORT_MASK_RNG] = {1780		.type = VCAP_FIELD_U32,1781		.offset = 42,1782		.width = 3,1783	},1784	[VCAP_KF_IF_EGR_PORT_MASK] = {1785		.type = VCAP_FIELD_U32,1786		.offset = 45,1787		.width = 32,1788	},1789	[VCAP_KF_IF_IGR_PORT_SEL] = {1790		.type = VCAP_FIELD_BIT,1791		.offset = 77,1792		.width = 1,1793	},1794	[VCAP_KF_IF_IGR_PORT] = {1795		.type = VCAP_FIELD_U32,1796		.offset = 78,1797		.width = 9,1798	},1799	[VCAP_KF_8021Q_PCP_CLS] = {1800		.type = VCAP_FIELD_U32,1801		.offset = 87,1802		.width = 3,1803	},1804	[VCAP_KF_8021Q_DEI_CLS] = {1805		.type = VCAP_FIELD_BIT,1806		.offset = 90,1807		.width = 1,1808	},1809	[VCAP_KF_COSID_CLS] = {1810		.type = VCAP_FIELD_U32,1811		.offset = 91,1812		.width = 3,1813	},1814	[VCAP_KF_L3_DPL_CLS] = {1815		.type = VCAP_FIELD_BIT,1816		.offset = 94,1817		.width = 1,1818	},1819	[VCAP_KF_L2_SMAC] = {1820		.type = VCAP_FIELD_U48,1821		.offset = 98,1822		.width = 48,1823	},1824	[VCAP_KF_ARP_ADDR_SPACE_OK_IS] = {1825		.type = VCAP_FIELD_BIT,1826		.offset = 146,1827		.width = 1,1828	},1829	[VCAP_KF_ARP_PROTO_SPACE_OK_IS] = {1830		.type = VCAP_FIELD_BIT,1831		.offset = 147,1832		.width = 1,1833	},1834	[VCAP_KF_ARP_LEN_OK_IS] = {1835		.type = VCAP_FIELD_BIT,1836		.offset = 148,1837		.width = 1,1838	},1839	[VCAP_KF_ARP_TGT_MATCH_IS] = {1840		.type = VCAP_FIELD_BIT,1841		.offset = 149,1842		.width = 1,1843	},1844	[VCAP_KF_ARP_SENDER_MATCH_IS] = {1845		.type = VCAP_FIELD_BIT,1846		.offset = 150,1847		.width = 1,1848	},1849	[VCAP_KF_ARP_OPCODE_UNKNOWN_IS] = {1850		.type = VCAP_FIELD_BIT,1851		.offset = 151,1852		.width = 1,1853	},1854	[VCAP_KF_ARP_OPCODE] = {1855		.type = VCAP_FIELD_U32,1856		.offset = 152,1857		.width = 2,1858	},1859	[VCAP_KF_L3_IP4_DIP] = {1860		.type = VCAP_FIELD_U32,1861		.offset = 154,1862		.width = 32,1863	},1864	[VCAP_KF_L3_IP4_SIP] = {1865		.type = VCAP_FIELD_U32,1866		.offset = 186,1867		.width = 32,1868	},1869	[VCAP_KF_L3_DIP_EQ_SIP_IS] = {1870		.type = VCAP_FIELD_BIT,1871		.offset = 218,1872		.width = 1,1873	},1874};1875 1876static const struct vcap_field es2_ip4_tcp_udp_keyfield[] = {1877	[VCAP_KF_TYPE] = {1878		.type = VCAP_FIELD_U32,1879		.offset = 0,1880		.width = 3,1881	},1882	[VCAP_KF_LOOKUP_FIRST_IS] = {1883		.type = VCAP_FIELD_BIT,1884		.offset = 3,1885		.width = 1,1886	},1887	[VCAP_KF_L2_MC_IS] = {1888		.type = VCAP_FIELD_BIT,1889		.offset = 13,1890		.width = 1,1891	},1892	[VCAP_KF_L2_BC_IS] = {1893		.type = VCAP_FIELD_BIT,1894		.offset = 14,1895		.width = 1,1896	},1897	[VCAP_KF_ISDX_GT0_IS] = {1898		.type = VCAP_FIELD_BIT,1899		.offset = 15,1900		.width = 1,1901	},1902	[VCAP_KF_ISDX_CLS] = {1903		.type = VCAP_FIELD_U32,1904		.offset = 16,1905		.width = 12,1906	},1907	[VCAP_KF_8021Q_VLAN_TAGGED_IS] = {1908		.type = VCAP_FIELD_BIT,1909		.offset = 28,1910		.width = 1,1911	},1912	[VCAP_KF_8021Q_VID_CLS] = {1913		.type = VCAP_FIELD_U32,1914		.offset = 29,1915		.width = 13,1916	},1917	[VCAP_KF_IF_EGR_PORT_MASK_RNG] = {1918		.type = VCAP_FIELD_U32,1919		.offset = 42,1920		.width = 3,1921	},1922	[VCAP_KF_IF_EGR_PORT_MASK] = {1923		.type = VCAP_FIELD_U32,1924		.offset = 45,1925		.width = 32,1926	},1927	[VCAP_KF_IF_IGR_PORT_SEL] = {1928		.type = VCAP_FIELD_BIT,1929		.offset = 77,1930		.width = 1,1931	},1932	[VCAP_KF_IF_IGR_PORT] = {1933		.type = VCAP_FIELD_U32,1934		.offset = 78,1935		.width = 9,1936	},1937	[VCAP_KF_8021Q_PCP_CLS] = {1938		.type = VCAP_FIELD_U32,1939		.offset = 87,1940		.width = 3,1941	},1942	[VCAP_KF_8021Q_DEI_CLS] = {1943		.type = VCAP_FIELD_BIT,1944		.offset = 90,1945		.width = 1,1946	},1947	[VCAP_KF_COSID_CLS] = {1948		.type = VCAP_FIELD_U32,1949		.offset = 91,1950		.width = 3,1951	},1952	[VCAP_KF_L3_DPL_CLS] = {1953		.type = VCAP_FIELD_BIT,1954		.offset = 94,1955		.width = 1,1956	},1957	[VCAP_KF_L3_RT_IS] = {1958		.type = VCAP_FIELD_BIT,1959		.offset = 95,1960		.width = 1,1961	},1962	[VCAP_KF_IP4_IS] = {1963		.type = VCAP_FIELD_BIT,1964		.offset = 99,1965		.width = 1,1966	},1967	[VCAP_KF_L3_FRAGMENT_TYPE] = {1968		.type = VCAP_FIELD_U32,1969		.offset = 100,1970		.width = 2,1971	},1972	[VCAP_KF_L3_OPTIONS_IS] = {1973		.type = VCAP_FIELD_BIT,1974		.offset = 102,1975		.width = 1,1976	},1977	[VCAP_KF_L3_TTL_GT0] = {1978		.type = VCAP_FIELD_BIT,1979		.offset = 103,1980		.width = 1,1981	},1982	[VCAP_KF_L3_TOS] = {1983		.type = VCAP_FIELD_U32,1984		.offset = 104,1985		.width = 8,1986	},1987	[VCAP_KF_L3_IP4_DIP] = {1988		.type = VCAP_FIELD_U32,1989		.offset = 112,1990		.width = 32,1991	},1992	[VCAP_KF_L3_IP4_SIP] = {1993		.type = VCAP_FIELD_U32,1994		.offset = 144,1995		.width = 32,1996	},1997	[VCAP_KF_L3_DIP_EQ_SIP_IS] = {1998		.type = VCAP_FIELD_BIT,1999		.offset = 176,2000		.width = 1,2001	},2002	[VCAP_KF_TCP_IS] = {2003		.type = VCAP_FIELD_BIT,2004		.offset = 177,2005		.width = 1,2006	},2007	[VCAP_KF_L4_DPORT] = {2008		.type = VCAP_FIELD_U32,2009		.offset = 178,2010		.width = 16,2011	},2012	[VCAP_KF_L4_SPORT] = {2013		.type = VCAP_FIELD_U32,2014		.offset = 194,2015		.width = 16,2016	},2017	[VCAP_KF_L4_RNG] = {2018		.type = VCAP_FIELD_U32,2019		.offset = 210,2020		.width = 16,2021	},2022	[VCAP_KF_L4_SPORT_EQ_DPORT_IS] = {2023		.type = VCAP_FIELD_BIT,2024		.offset = 226,2025		.width = 1,2026	},2027	[VCAP_KF_L4_SEQUENCE_EQ0_IS] = {2028		.type = VCAP_FIELD_BIT,2029		.offset = 227,2030		.width = 1,2031	},2032	[VCAP_KF_L4_FIN] = {2033		.type = VCAP_FIELD_BIT,2034		.offset = 228,2035		.width = 1,2036	},2037	[VCAP_KF_L4_SYN] = {2038		.type = VCAP_FIELD_BIT,2039		.offset = 229,2040		.width = 1,2041	},2042	[VCAP_KF_L4_RST] = {2043		.type = VCAP_FIELD_BIT,2044		.offset = 230,2045		.width = 1,2046	},2047	[VCAP_KF_L4_PSH] = {2048		.type = VCAP_FIELD_BIT,2049		.offset = 231,2050		.width = 1,2051	},2052	[VCAP_KF_L4_ACK] = {2053		.type = VCAP_FIELD_BIT,2054		.offset = 232,2055		.width = 1,2056	},2057	[VCAP_KF_L4_URG] = {2058		.type = VCAP_FIELD_BIT,2059		.offset = 233,2060		.width = 1,2061	},2062	[VCAP_KF_L4_PAYLOAD] = {2063		.type = VCAP_FIELD_U64,2064		.offset = 234,2065		.width = 64,2066	},2067};2068 2069static const struct vcap_field es2_ip4_other_keyfield[] = {2070	[VCAP_KF_TYPE] = {2071		.type = VCAP_FIELD_U32,2072		.offset = 0,2073		.width = 3,2074	},2075	[VCAP_KF_LOOKUP_FIRST_IS] = {2076		.type = VCAP_FIELD_BIT,2077		.offset = 3,2078		.width = 1,2079	},2080	[VCAP_KF_L2_MC_IS] = {2081		.type = VCAP_FIELD_BIT,2082		.offset = 13,2083		.width = 1,2084	},2085	[VCAP_KF_L2_BC_IS] = {2086		.type = VCAP_FIELD_BIT,2087		.offset = 14,2088		.width = 1,2089	},2090	[VCAP_KF_ISDX_GT0_IS] = {2091		.type = VCAP_FIELD_BIT,2092		.offset = 15,2093		.width = 1,2094	},2095	[VCAP_KF_ISDX_CLS] = {2096		.type = VCAP_FIELD_U32,2097		.offset = 16,2098		.width = 12,2099	},2100	[VCAP_KF_8021Q_VLAN_TAGGED_IS] = {2101		.type = VCAP_FIELD_BIT,2102		.offset = 28,2103		.width = 1,2104	},2105	[VCAP_KF_8021Q_VID_CLS] = {2106		.type = VCAP_FIELD_U32,2107		.offset = 29,2108		.width = 13,2109	},2110	[VCAP_KF_IF_EGR_PORT_MASK_RNG] = {2111		.type = VCAP_FIELD_U32,2112		.offset = 42,2113		.width = 3,2114	},2115	[VCAP_KF_IF_EGR_PORT_MASK] = {2116		.type = VCAP_FIELD_U32,2117		.offset = 45,2118		.width = 32,2119	},2120	[VCAP_KF_IF_IGR_PORT_SEL] = {2121		.type = VCAP_FIELD_BIT,2122		.offset = 77,2123		.width = 1,2124	},2125	[VCAP_KF_IF_IGR_PORT] = {2126		.type = VCAP_FIELD_U32,2127		.offset = 78,2128		.width = 9,2129	},2130	[VCAP_KF_8021Q_PCP_CLS] = {2131		.type = VCAP_FIELD_U32,2132		.offset = 87,2133		.width = 3,2134	},2135	[VCAP_KF_8021Q_DEI_CLS] = {2136		.type = VCAP_FIELD_BIT,2137		.offset = 90,2138		.width = 1,2139	},2140	[VCAP_KF_COSID_CLS] = {2141		.type = VCAP_FIELD_U32,2142		.offset = 91,2143		.width = 3,2144	},2145	[VCAP_KF_L3_DPL_CLS] = {2146		.type = VCAP_FIELD_BIT,2147		.offset = 94,2148		.width = 1,2149	},2150	[VCAP_KF_L3_RT_IS] = {2151		.type = VCAP_FIELD_BIT,2152		.offset = 95,2153		.width = 1,2154	},2155	[VCAP_KF_IP4_IS] = {2156		.type = VCAP_FIELD_BIT,2157		.offset = 99,2158		.width = 1,2159	},2160	[VCAP_KF_L3_FRAGMENT_TYPE] = {2161		.type = VCAP_FIELD_U32,2162		.offset = 100,2163		.width = 2,2164	},2165	[VCAP_KF_L3_OPTIONS_IS] = {2166		.type = VCAP_FIELD_BIT,2167		.offset = 102,2168		.width = 1,2169	},2170	[VCAP_KF_L3_TTL_GT0] = {2171		.type = VCAP_FIELD_BIT,2172		.offset = 103,2173		.width = 1,2174	},2175	[VCAP_KF_L3_TOS] = {2176		.type = VCAP_FIELD_U32,2177		.offset = 104,2178		.width = 8,2179	},2180	[VCAP_KF_L3_IP4_DIP] = {2181		.type = VCAP_FIELD_U32,2182		.offset = 112,2183		.width = 32,2184	},2185	[VCAP_KF_L3_IP4_SIP] = {2186		.type = VCAP_FIELD_U32,2187		.offset = 144,2188		.width = 32,2189	},2190	[VCAP_KF_L3_DIP_EQ_SIP_IS] = {2191		.type = VCAP_FIELD_BIT,2192		.offset = 176,2193		.width = 1,2194	},2195	[VCAP_KF_L3_IP_PROTO] = {2196		.type = VCAP_FIELD_U32,2197		.offset = 177,2198		.width = 8,2199	},2200	[VCAP_KF_L3_PAYLOAD] = {2201		.type = VCAP_FIELD_U112,2202		.offset = 185,2203		.width = 96,2204	},2205};2206 2207static const struct vcap_field es2_ip_7tuple_keyfield[] = {2208	[VCAP_KF_LOOKUP_FIRST_IS] = {2209		.type = VCAP_FIELD_BIT,2210		.offset = 0,2211		.width = 1,2212	},2213	[VCAP_KF_L2_MC_IS] = {2214		.type = VCAP_FIELD_BIT,2215		.offset = 10,2216		.width = 1,2217	},2218	[VCAP_KF_L2_BC_IS] = {2219		.type = VCAP_FIELD_BIT,2220		.offset = 11,2221		.width = 1,2222	},2223	[VCAP_KF_ISDX_GT0_IS] = {2224		.type = VCAP_FIELD_BIT,2225		.offset = 12,2226		.width = 1,2227	},2228	[VCAP_KF_ISDX_CLS] = {2229		.type = VCAP_FIELD_U32,2230		.offset = 13,2231		.width = 12,2232	},2233	[VCAP_KF_8021Q_VLAN_TAGGED_IS] = {2234		.type = VCAP_FIELD_BIT,2235		.offset = 25,2236		.width = 1,2237	},2238	[VCAP_KF_8021Q_VID_CLS] = {2239		.type = VCAP_FIELD_U32,2240		.offset = 26,2241		.width = 13,2242	},2243	[VCAP_KF_IF_EGR_PORT_MASK_RNG] = {2244		.type = VCAP_FIELD_U32,2245		.offset = 39,2246		.width = 3,2247	},2248	[VCAP_KF_IF_EGR_PORT_MASK] = {2249		.type = VCAP_FIELD_U32,2250		.offset = 42,2251		.width = 32,2252	},2253	[VCAP_KF_IF_IGR_PORT_SEL] = {2254		.type = VCAP_FIELD_BIT,2255		.offset = 74,2256		.width = 1,2257	},2258	[VCAP_KF_IF_IGR_PORT] = {2259		.type = VCAP_FIELD_U32,2260		.offset = 75,2261		.width = 9,2262	},2263	[VCAP_KF_8021Q_PCP_CLS] = {2264		.type = VCAP_FIELD_U32,2265		.offset = 84,2266		.width = 3,2267	},2268	[VCAP_KF_8021Q_DEI_CLS] = {2269		.type = VCAP_FIELD_BIT,2270		.offset = 87,2271		.width = 1,2272	},2273	[VCAP_KF_COSID_CLS] = {2274		.type = VCAP_FIELD_U32,2275		.offset = 88,2276		.width = 3,2277	},2278	[VCAP_KF_L3_DPL_CLS] = {2279		.type = VCAP_FIELD_BIT,2280		.offset = 91,2281		.width = 1,2282	},2283	[VCAP_KF_L3_RT_IS] = {2284		.type = VCAP_FIELD_BIT,2285		.offset = 92,2286		.width = 1,2287	},2288	[VCAP_KF_L2_DMAC] = {2289		.type = VCAP_FIELD_U48,2290		.offset = 96,2291		.width = 48,2292	},2293	[VCAP_KF_L2_SMAC] = {2294		.type = VCAP_FIELD_U48,2295		.offset = 144,2296		.width = 48,2297	},2298	[VCAP_KF_IP4_IS] = {2299		.type = VCAP_FIELD_BIT,2300		.offset = 192,2301		.width = 1,2302	},2303	[VCAP_KF_L3_TTL_GT0] = {2304		.type = VCAP_FIELD_BIT,2305		.offset = 193,2306		.width = 1,2307	},2308	[VCAP_KF_L3_TOS] = {2309		.type = VCAP_FIELD_U32,2310		.offset = 194,2311		.width = 8,2312	},2313	[VCAP_KF_L3_IP6_DIP] = {2314		.type = VCAP_FIELD_U128,2315		.offset = 202,2316		.width = 128,2317	},2318	[VCAP_KF_L3_IP6_SIP] = {2319		.type = VCAP_FIELD_U128,2320		.offset = 330,2321		.width = 128,2322	},2323	[VCAP_KF_L3_DIP_EQ_SIP_IS] = {2324		.type = VCAP_FIELD_BIT,2325		.offset = 458,2326		.width = 1,2327	},2328	[VCAP_KF_TCP_UDP_IS] = {2329		.type = VCAP_FIELD_BIT,2330		.offset = 459,2331		.width = 1,2332	},2333	[VCAP_KF_TCP_IS] = {2334		.type = VCAP_FIELD_BIT,2335		.offset = 460,2336		.width = 1,2337	},2338	[VCAP_KF_L4_DPORT] = {2339		.type = VCAP_FIELD_U32,2340		.offset = 461,2341		.width = 16,2342	},2343	[VCAP_KF_L4_SPORT] = {2344		.type = VCAP_FIELD_U32,2345		.offset = 477,2346		.width = 16,2347	},2348	[VCAP_KF_L4_RNG] = {2349		.type = VCAP_FIELD_U32,2350		.offset = 493,2351		.width = 16,2352	},2353	[VCAP_KF_L4_SPORT_EQ_DPORT_IS] = {2354		.type = VCAP_FIELD_BIT,2355		.offset = 509,2356		.width = 1,2357	},2358	[VCAP_KF_L4_SEQUENCE_EQ0_IS] = {2359		.type = VCAP_FIELD_BIT,2360		.offset = 510,2361		.width = 1,2362	},2363	[VCAP_KF_L4_FIN] = {2364		.type = VCAP_FIELD_BIT,2365		.offset = 511,2366		.width = 1,2367	},2368	[VCAP_KF_L4_SYN] = {2369		.type = VCAP_FIELD_BIT,2370		.offset = 512,2371		.width = 1,2372	},2373	[VCAP_KF_L4_RST] = {2374		.type = VCAP_FIELD_BIT,2375		.offset = 513,2376		.width = 1,2377	},2378	[VCAP_KF_L4_PSH] = {2379		.type = VCAP_FIELD_BIT,2380		.offset = 514,2381		.width = 1,2382	},2383	[VCAP_KF_L4_ACK] = {2384		.type = VCAP_FIELD_BIT,2385		.offset = 515,2386		.width = 1,2387	},2388	[VCAP_KF_L4_URG] = {2389		.type = VCAP_FIELD_BIT,2390		.offset = 516,2391		.width = 1,2392	},2393	[VCAP_KF_L4_PAYLOAD] = {2394		.type = VCAP_FIELD_U64,2395		.offset = 517,2396		.width = 64,2397	},2398};2399 2400static const struct vcap_field es2_ip6_std_keyfield[] = {2401	[VCAP_KF_TYPE] = {2402		.type = VCAP_FIELD_U32,2403		.offset = 0,2404		.width = 3,2405	},2406	[VCAP_KF_LOOKUP_FIRST_IS] = {2407		.type = VCAP_FIELD_BIT,2408		.offset = 3,2409		.width = 1,2410	},2411	[VCAP_KF_L2_MC_IS] = {2412		.type = VCAP_FIELD_BIT,2413		.offset = 13,2414		.width = 1,2415	},2416	[VCAP_KF_L2_BC_IS] = {2417		.type = VCAP_FIELD_BIT,2418		.offset = 14,2419		.width = 1,2420	},2421	[VCAP_KF_ISDX_GT0_IS] = {2422		.type = VCAP_FIELD_BIT,2423		.offset = 15,2424		.width = 1,2425	},2426	[VCAP_KF_ISDX_CLS] = {2427		.type = VCAP_FIELD_U32,2428		.offset = 16,2429		.width = 12,2430	},2431	[VCAP_KF_8021Q_VLAN_TAGGED_IS] = {2432		.type = VCAP_FIELD_BIT,2433		.offset = 28,2434		.width = 1,2435	},2436	[VCAP_KF_8021Q_VID_CLS] = {2437		.type = VCAP_FIELD_U32,2438		.offset = 29,2439		.width = 13,2440	},2441	[VCAP_KF_IF_EGR_PORT_MASK_RNG] = {2442		.type = VCAP_FIELD_U32,2443		.offset = 42,2444		.width = 3,2445	},2446	[VCAP_KF_IF_EGR_PORT_MASK] = {2447		.type = VCAP_FIELD_U32,2448		.offset = 45,2449		.width = 32,2450	},2451	[VCAP_KF_IF_IGR_PORT_SEL] = {2452		.type = VCAP_FIELD_BIT,2453		.offset = 77,2454		.width = 1,2455	},2456	[VCAP_KF_IF_IGR_PORT] = {2457		.type = VCAP_FIELD_U32,2458		.offset = 78,2459		.width = 9,2460	},2461	[VCAP_KF_8021Q_PCP_CLS] = {2462		.type = VCAP_FIELD_U32,2463		.offset = 87,2464		.width = 3,2465	},2466	[VCAP_KF_8021Q_DEI_CLS] = {2467		.type = VCAP_FIELD_BIT,2468		.offset = 90,2469		.width = 1,2470	},2471	[VCAP_KF_COSID_CLS] = {2472		.type = VCAP_FIELD_U32,2473		.offset = 91,2474		.width = 3,2475	},2476	[VCAP_KF_L3_DPL_CLS] = {2477		.type = VCAP_FIELD_BIT,2478		.offset = 94,2479		.width = 1,2480	},2481	[VCAP_KF_L3_RT_IS] = {2482		.type = VCAP_FIELD_BIT,2483		.offset = 95,2484		.width = 1,2485	},2486	[VCAP_KF_L3_TTL_GT0] = {2487		.type = VCAP_FIELD_BIT,2488		.offset = 99,2489		.width = 1,2490	},2491	[VCAP_KF_L3_IP6_SIP] = {2492		.type = VCAP_FIELD_U128,2493		.offset = 100,2494		.width = 128,2495	},2496	[VCAP_KF_L3_DIP_EQ_SIP_IS] = {2497		.type = VCAP_FIELD_BIT,2498		.offset = 228,2499		.width = 1,2500	},2501	[VCAP_KF_L3_IP_PROTO] = {2502		.type = VCAP_FIELD_U32,2503		.offset = 229,2504		.width = 8,2505	},2506	[VCAP_KF_L4_RNG] = {2507		.type = VCAP_FIELD_U32,2508		.offset = 237,2509		.width = 16,2510	},2511	[VCAP_KF_L3_PAYLOAD] = {2512		.type = VCAP_FIELD_U48,2513		.offset = 253,2514		.width = 40,2515	},2516};2517 2518static const struct vcap_field es2_ip4_vid_keyfield[] = {2519	[VCAP_KF_LOOKUP_FIRST_IS] = {2520		.type = VCAP_FIELD_BIT,2521		.offset = 0,2522		.width = 1,2523	},2524	[VCAP_KF_ACL_GRP_ID] = {2525		.type = VCAP_FIELD_U32,2526		.offset = 1,2527		.width = 8,2528	},2529	[VCAP_KF_PROT_ACTIVE] = {2530		.type = VCAP_FIELD_BIT,2531		.offset = 9,2532		.width = 1,2533	},2534	[VCAP_KF_L2_MC_IS] = {2535		.type = VCAP_FIELD_BIT,2536		.offset = 10,2537		.width = 1,2538	},2539	[VCAP_KF_L2_BC_IS] = {2540		.type = VCAP_FIELD_BIT,2541		.offset = 11,2542		.width = 1,2543	},2544	[VCAP_KF_ISDX_GT0_IS] = {2545		.type = VCAP_FIELD_BIT,2546		.offset = 12,2547		.width = 1,2548	},2549	[VCAP_KF_ISDX_CLS] = {2550		.type = VCAP_FIELD_U32,2551		.offset = 13,2552		.width = 12,2553	},2554	[VCAP_KF_8021Q_VLAN_TAGGED_IS] = {2555		.type = VCAP_FIELD_BIT,2556		.offset = 25,2557		.width = 1,2558	},2559	[VCAP_KF_8021Q_VID_CLS] = {2560		.type = VCAP_FIELD_U32,2561		.offset = 26,2562		.width = 13,2563	},2564	[VCAP_KF_8021Q_PCP_CLS] = {2565		.type = VCAP_FIELD_U32,2566		.offset = 39,2567		.width = 3,2568	},2569	[VCAP_KF_8021Q_DEI_CLS] = {2570		.type = VCAP_FIELD_BIT,2571		.offset = 42,2572		.width = 1,2573	},2574	[VCAP_KF_COSID_CLS] = {2575		.type = VCAP_FIELD_U32,2576		.offset = 43,2577		.width = 3,2578	},2579	[VCAP_KF_L3_DPL_CLS] = {2580		.type = VCAP_FIELD_BIT,2581		.offset = 46,2582		.width = 1,2583	},2584	[VCAP_KF_L3_RT_IS] = {2585		.type = VCAP_FIELD_BIT,2586		.offset = 47,2587		.width = 1,2588	},2589	[VCAP_KF_ES0_ISDX_KEY_ENA] = {2590		.type = VCAP_FIELD_BIT,2591		.offset = 48,2592		.width = 1,2593	},2594	[VCAP_KF_MIRROR_PROBE] = {2595		.type = VCAP_FIELD_U32,2596		.offset = 49,2597		.width = 2,2598	},2599	[VCAP_KF_IP4_IS] = {2600		.type = VCAP_FIELD_BIT,2601		.offset = 51,2602		.width = 1,2603	},2604	[VCAP_KF_L3_IP4_DIP] = {2605		.type = VCAP_FIELD_U32,2606		.offset = 52,2607		.width = 32,2608	},2609	[VCAP_KF_L3_IP4_SIP] = {2610		.type = VCAP_FIELD_U32,2611		.offset = 84,2612		.width = 32,2613	},2614	[VCAP_KF_L4_RNG] = {2615		.type = VCAP_FIELD_U32,2616		.offset = 116,2617		.width = 16,2618	},2619};2620 2621static const struct vcap_field es2_ip6_vid_keyfield[] = {2622	[VCAP_KF_TYPE] = {2623		.type = VCAP_FIELD_U32,2624		.offset = 0,2625		.width = 3,2626	},2627	[VCAP_KF_LOOKUP_FIRST_IS] = {2628		.type = VCAP_FIELD_BIT,2629		.offset = 3,2630		.width = 1,2631	},2632	[VCAP_KF_ACL_GRP_ID] = {2633		.type = VCAP_FIELD_U32,2634		.offset = 4,2635		.width = 8,2636	},2637	[VCAP_KF_PROT_ACTIVE] = {2638		.type = VCAP_FIELD_BIT,2639		.offset = 12,2640		.width = 1,2641	},2642	[VCAP_KF_L2_MC_IS] = {2643		.type = VCAP_FIELD_BIT,2644		.offset = 13,2645		.width = 1,2646	},2647	[VCAP_KF_L2_BC_IS] = {2648		.type = VCAP_FIELD_BIT,2649		.offset = 14,2650		.width = 1,2651	},2652	[VCAP_KF_ISDX_GT0_IS] = {2653		.type = VCAP_FIELD_BIT,2654		.offset = 15,2655		.width = 1,2656	},2657	[VCAP_KF_ISDX_CLS] = {2658		.type = VCAP_FIELD_U32,2659		.offset = 16,2660		.width = 12,2661	},2662	[VCAP_KF_8021Q_VLAN_TAGGED_IS] = {2663		.type = VCAP_FIELD_BIT,2664		.offset = 28,2665		.width = 1,2666	},2667	[VCAP_KF_8021Q_VID_CLS] = {2668		.type = VCAP_FIELD_U32,2669		.offset = 29,2670		.width = 13,2671	},2672	[VCAP_KF_L3_RT_IS] = {2673		.type = VCAP_FIELD_BIT,2674		.offset = 42,2675		.width = 1,2676	},2677	[VCAP_KF_L3_IP6_DIP] = {2678		.type = VCAP_FIELD_U128,2679		.offset = 43,2680		.width = 128,2681	},2682	[VCAP_KF_L3_IP6_SIP] = {2683		.type = VCAP_FIELD_U128,2684		.offset = 171,2685		.width = 128,2686	},2687};2688 2689/* keyfield_set */2690static const struct vcap_set is0_keyfield_set[] = {2691	[VCAP_KFS_LL_FULL] = {2692		.type_id = 0,2693		.sw_per_item = 6,2694		.sw_cnt = 2,2695	},2696	[VCAP_KFS_NORMAL_7TUPLE] = {2697		.type_id = 0,2698		.sw_per_item = 12,2699		.sw_cnt = 1,2700	},2701	[VCAP_KFS_NORMAL_5TUPLE_IP4] = {2702		.type_id = 2,2703		.sw_per_item = 6,2704		.sw_cnt = 2,2705	},2706	[VCAP_KFS_PURE_5TUPLE_IP4] = {2707		.type_id = 2,2708		.sw_per_item = 3,2709		.sw_cnt = 4,2710	},2711	[VCAP_KFS_ETAG] = {2712		.type_id = 3,2713		.sw_per_item = 2,2714		.sw_cnt = 6,2715	},2716};2717 2718static const struct vcap_set is2_keyfield_set[] = {2719	[VCAP_KFS_MAC_ETYPE] = {2720		.type_id = 0,2721		.sw_per_item = 6,2722		.sw_cnt = 2,2723	},2724	[VCAP_KFS_ARP] = {2725		.type_id = 3,2726		.sw_per_item = 6,2727		.sw_cnt = 2,2728	},2729	[VCAP_KFS_IP4_TCP_UDP] = {2730		.type_id = 4,2731		.sw_per_item = 6,2732		.sw_cnt = 2,2733	},2734	[VCAP_KFS_IP4_OTHER] = {2735		.type_id = 5,2736		.sw_per_item = 6,2737		.sw_cnt = 2,2738	},2739	[VCAP_KFS_IP6_STD] = {2740		.type_id = 6,2741		.sw_per_item = 6,2742		.sw_cnt = 2,2743	},2744	[VCAP_KFS_IP_7TUPLE] = {2745		.type_id = 1,2746		.sw_per_item = 12,2747		.sw_cnt = 1,2748	},2749};2750 2751static const struct vcap_set es2_keyfield_set[] = {2752	[VCAP_KFS_MAC_ETYPE] = {2753		.type_id = 0,2754		.sw_per_item = 6,2755		.sw_cnt = 2,2756	},2757	[VCAP_KFS_ARP] = {2758		.type_id = 1,2759		.sw_per_item = 6,2760		.sw_cnt = 2,2761	},2762	[VCAP_KFS_IP4_TCP_UDP] = {2763		.type_id = 2,2764		.sw_per_item = 6,2765		.sw_cnt = 2,2766	},2767	[VCAP_KFS_IP4_OTHER] = {2768		.type_id = 3,2769		.sw_per_item = 6,2770		.sw_cnt = 2,2771	},2772	[VCAP_KFS_IP_7TUPLE] = {2773		.type_id = -1,2774		.sw_per_item = 12,2775		.sw_cnt = 1,2776	},2777	[VCAP_KFS_IP6_STD] = {2778		.type_id = 4,2779		.sw_per_item = 6,2780		.sw_cnt = 2,2781	},2782	[VCAP_KFS_IP4_VID] = {2783		.type_id = -1,2784		.sw_per_item = 3,2785		.sw_cnt = 4,2786	},2787	[VCAP_KFS_IP6_VID] = {2788		.type_id = 5,2789		.sw_per_item = 6,2790		.sw_cnt = 2,2791	},2792};2793 2794/* keyfield_set map */2795static const struct vcap_field *is0_keyfield_set_map[] = {2796	[VCAP_KFS_LL_FULL] = is0_ll_full_keyfield,2797	[VCAP_KFS_NORMAL_7TUPLE] = is0_normal_7tuple_keyfield,2798	[VCAP_KFS_NORMAL_5TUPLE_IP4] = is0_normal_5tuple_ip4_keyfield,2799	[VCAP_KFS_PURE_5TUPLE_IP4] = is0_pure_5tuple_ip4_keyfield,2800	[VCAP_KFS_ETAG] = is0_etag_keyfield,2801};2802 2803static const struct vcap_field *is2_keyfield_set_map[] = {2804	[VCAP_KFS_MAC_ETYPE] = is2_mac_etype_keyfield,2805	[VCAP_KFS_ARP] = is2_arp_keyfield,2806	[VCAP_KFS_IP4_TCP_UDP] = is2_ip4_tcp_udp_keyfield,2807	[VCAP_KFS_IP4_OTHER] = is2_ip4_other_keyfield,2808	[VCAP_KFS_IP6_STD] = is2_ip6_std_keyfield,2809	[VCAP_KFS_IP_7TUPLE] = is2_ip_7tuple_keyfield,2810};2811 2812static const struct vcap_field *es2_keyfield_set_map[] = {2813	[VCAP_KFS_MAC_ETYPE] = es2_mac_etype_keyfield,2814	[VCAP_KFS_ARP] = es2_arp_keyfield,2815	[VCAP_KFS_IP4_TCP_UDP] = es2_ip4_tcp_udp_keyfield,2816	[VCAP_KFS_IP4_OTHER] = es2_ip4_other_keyfield,2817	[VCAP_KFS_IP_7TUPLE] = es2_ip_7tuple_keyfield,2818	[VCAP_KFS_IP6_STD] = es2_ip6_std_keyfield,2819	[VCAP_KFS_IP4_VID] = es2_ip4_vid_keyfield,2820	[VCAP_KFS_IP6_VID] = es2_ip6_vid_keyfield,2821};2822 2823/* keyfield_set map sizes */2824static int is0_keyfield_set_map_size[] = {2825	[VCAP_KFS_LL_FULL] = ARRAY_SIZE(is0_ll_full_keyfield),2826	[VCAP_KFS_NORMAL_7TUPLE] = ARRAY_SIZE(is0_normal_7tuple_keyfield),2827	[VCAP_KFS_NORMAL_5TUPLE_IP4] = ARRAY_SIZE(is0_normal_5tuple_ip4_keyfield),2828	[VCAP_KFS_PURE_5TUPLE_IP4] = ARRAY_SIZE(is0_pure_5tuple_ip4_keyfield),2829	[VCAP_KFS_ETAG] = ARRAY_SIZE(is0_etag_keyfield),2830};2831 2832static int is2_keyfield_set_map_size[] = {2833	[VCAP_KFS_MAC_ETYPE] = ARRAY_SIZE(is2_mac_etype_keyfield),2834	[VCAP_KFS_ARP] = ARRAY_SIZE(is2_arp_keyfield),2835	[VCAP_KFS_IP4_TCP_UDP] = ARRAY_SIZE(is2_ip4_tcp_udp_keyfield),2836	[VCAP_KFS_IP4_OTHER] = ARRAY_SIZE(is2_ip4_other_keyfield),2837	[VCAP_KFS_IP6_STD] = ARRAY_SIZE(is2_ip6_std_keyfield),2838	[VCAP_KFS_IP_7TUPLE] = ARRAY_SIZE(is2_ip_7tuple_keyfield),2839};2840 2841static int es2_keyfield_set_map_size[] = {2842	[VCAP_KFS_MAC_ETYPE] = ARRAY_SIZE(es2_mac_etype_keyfield),2843	[VCAP_KFS_ARP] = ARRAY_SIZE(es2_arp_keyfield),2844	[VCAP_KFS_IP4_TCP_UDP] = ARRAY_SIZE(es2_ip4_tcp_udp_keyfield),2845	[VCAP_KFS_IP4_OTHER] = ARRAY_SIZE(es2_ip4_other_keyfield),2846	[VCAP_KFS_IP_7TUPLE] = ARRAY_SIZE(es2_ip_7tuple_keyfield),2847	[VCAP_KFS_IP6_STD] = ARRAY_SIZE(es2_ip6_std_keyfield),2848	[VCAP_KFS_IP4_VID] = ARRAY_SIZE(es2_ip4_vid_keyfield),2849	[VCAP_KFS_IP6_VID] = ARRAY_SIZE(es2_ip6_vid_keyfield),2850};2851 2852/* actionfields */2853static const struct vcap_field is0_classification_actionfield[] = {2854	[VCAP_AF_TYPE] = {2855		.type = VCAP_FIELD_BIT,2856		.offset = 0,2857		.width = 1,2858	},2859	[VCAP_AF_DSCP_ENA] = {2860		.type = VCAP_FIELD_BIT,2861		.offset = 1,2862		.width = 1,2863	},2864	[VCAP_AF_DSCP_VAL] = {2865		.type = VCAP_FIELD_U32,2866		.offset = 2,2867		.width = 6,2868	},2869	[VCAP_AF_QOS_ENA] = {2870		.type = VCAP_FIELD_BIT,2871		.offset = 12,2872		.width = 1,2873	},2874	[VCAP_AF_QOS_VAL] = {2875		.type = VCAP_FIELD_U32,2876		.offset = 13,2877		.width = 3,2878	},2879	[VCAP_AF_DP_ENA] = {2880		.type = VCAP_FIELD_BIT,2881		.offset = 16,2882		.width = 1,2883	},2884	[VCAP_AF_DP_VAL] = {2885		.type = VCAP_FIELD_U32,2886		.offset = 17,2887		.width = 2,2888	},2889	[VCAP_AF_DEI_ENA] = {2890		.type = VCAP_FIELD_BIT,2891		.offset = 19,2892		.width = 1,2893	},2894	[VCAP_AF_DEI_VAL] = {2895		.type = VCAP_FIELD_BIT,2896		.offset = 20,2897		.width = 1,2898	},2899	[VCAP_AF_PCP_ENA] = {2900		.type = VCAP_FIELD_BIT,2901		.offset = 21,2902		.width = 1,2903	},2904	[VCAP_AF_PCP_VAL] = {2905		.type = VCAP_FIELD_U32,2906		.offset = 22,2907		.width = 3,2908	},2909	[VCAP_AF_MAP_LOOKUP_SEL] = {2910		.type = VCAP_FIELD_U32,2911		.offset = 25,2912		.width = 2,2913	},2914	[VCAP_AF_MAP_KEY] = {2915		.type = VCAP_FIELD_U32,2916		.offset = 27,2917		.width = 3,2918	},2919	[VCAP_AF_MAP_IDX] = {2920		.type = VCAP_FIELD_U32,2921		.offset = 30,2922		.width = 9,2923	},2924	[VCAP_AF_CLS_VID_SEL] = {2925		.type = VCAP_FIELD_U32,2926		.offset = 39,2927		.width = 3,2928	},2929	[VCAP_AF_VID_VAL] = {2930		.type = VCAP_FIELD_U32,2931		.offset = 45,2932		.width = 13,2933	},2934	[VCAP_AF_ISDX_ADD_REPLACE_SEL] = {2935		.type = VCAP_FIELD_BIT,2936		.offset = 68,2937		.width = 1,2938	},2939	[VCAP_AF_ISDX_VAL] = {2940		.type = VCAP_FIELD_U32,2941		.offset = 69,2942		.width = 12,2943	},2944	[VCAP_AF_PAG_OVERRIDE_MASK] = {2945		.type = VCAP_FIELD_U32,2946		.offset = 109,2947		.width = 8,2948	},2949	[VCAP_AF_PAG_VAL] = {2950		.type = VCAP_FIELD_U32,2951		.offset = 117,2952		.width = 8,2953	},2954	[VCAP_AF_NXT_IDX_CTRL] = {2955		.type = VCAP_FIELD_U32,2956		.offset = 171,2957		.width = 3,2958	},2959	[VCAP_AF_NXT_IDX] = {2960		.type = VCAP_FIELD_U32,2961		.offset = 174,2962		.width = 12,2963	},2964};2965 2966static const struct vcap_field is0_full_actionfield[] = {2967	[VCAP_AF_DSCP_ENA] = {2968		.type = VCAP_FIELD_BIT,2969		.offset = 0,2970		.width = 1,2971	},2972	[VCAP_AF_DSCP_VAL] = {2973		.type = VCAP_FIELD_U32,2974		.offset = 1,2975		.width = 6,2976	},2977	[VCAP_AF_QOS_ENA] = {2978		.type = VCAP_FIELD_BIT,2979		.offset = 11,2980		.width = 1,2981	},2982	[VCAP_AF_QOS_VAL] = {2983		.type = VCAP_FIELD_U32,2984		.offset = 12,2985		.width = 3,2986	},2987	[VCAP_AF_DP_ENA] = {2988		.type = VCAP_FIELD_BIT,2989		.offset = 15,2990		.width = 1,2991	},2992	[VCAP_AF_DP_VAL] = {2993		.type = VCAP_FIELD_U32,2994		.offset = 16,2995		.width = 2,2996	},2997	[VCAP_AF_DEI_ENA] = {2998		.type = VCAP_FIELD_BIT,2999		.offset = 18,3000		.width = 1,3001	},3002	[VCAP_AF_DEI_VAL] = {3003		.type = VCAP_FIELD_BIT,3004		.offset = 19,3005		.width = 1,3006	},3007	[VCAP_AF_PCP_ENA] = {3008		.type = VCAP_FIELD_BIT,3009		.offset = 20,3010		.width = 1,3011	},3012	[VCAP_AF_PCP_VAL] = {3013		.type = VCAP_FIELD_U32,3014		.offset = 21,3015		.width = 3,3016	},3017	[VCAP_AF_MAP_LOOKUP_SEL] = {3018		.type = VCAP_FIELD_U32,3019		.offset = 24,3020		.width = 2,3021	},3022	[VCAP_AF_MAP_KEY] = {3023		.type = VCAP_FIELD_U32,3024		.offset = 26,3025		.width = 3,3026	},3027	[VCAP_AF_MAP_IDX] = {3028		.type = VCAP_FIELD_U32,3029		.offset = 29,3030		.width = 9,3031	},3032	[VCAP_AF_CLS_VID_SEL] = {3033		.type = VCAP_FIELD_U32,3034		.offset = 38,3035		.width = 3,3036	},3037	[VCAP_AF_VID_VAL] = {3038		.type = VCAP_FIELD_U32,3039		.offset = 44,3040		.width = 13,3041	},3042	[VCAP_AF_ISDX_ADD_REPLACE_SEL] = {3043		.type = VCAP_FIELD_BIT,3044		.offset = 67,3045		.width = 1,3046	},3047	[VCAP_AF_ISDX_VAL] = {3048		.type = VCAP_FIELD_U32,3049		.offset = 68,3050		.width = 12,3051	},3052	[VCAP_AF_MASK_MODE] = {3053		.type = VCAP_FIELD_U32,3054		.offset = 80,3055		.width = 3,3056	},3057	[VCAP_AF_PORT_MASK] = {3058		.type = VCAP_FIELD_U72,3059		.offset = 83,3060		.width = 65,3061	},3062	[VCAP_AF_PAG_OVERRIDE_MASK] = {3063		.type = VCAP_FIELD_U32,3064		.offset = 204,3065		.width = 8,3066	},3067	[VCAP_AF_PAG_VAL] = {3068		.type = VCAP_FIELD_U32,3069		.offset = 212,3070		.width = 8,3071	},3072	[VCAP_AF_NXT_IDX_CTRL] = {3073		.type = VCAP_FIELD_U32,3074		.offset = 298,3075		.width = 3,3076	},3077	[VCAP_AF_NXT_IDX] = {3078		.type = VCAP_FIELD_U32,3079		.offset = 301,3080		.width = 12,3081	},3082};3083 3084static const struct vcap_field is0_class_reduced_actionfield[] = {3085	[VCAP_AF_TYPE] = {3086		.type = VCAP_FIELD_BIT,3087		.offset = 0,3088		.width = 1,3089	},3090	[VCAP_AF_QOS_ENA] = {3091		.type = VCAP_FIELD_BIT,3092		.offset = 5,3093		.width = 1,3094	},3095	[VCAP_AF_QOS_VAL] = {3096		.type = VCAP_FIELD_U32,3097		.offset = 6,3098		.width = 3,3099	},3100	[VCAP_AF_DP_ENA] = {3101		.type = VCAP_FIELD_BIT,3102		.offset = 9,3103		.width = 1,3104	},3105	[VCAP_AF_DP_VAL] = {3106		.type = VCAP_FIELD_U32,3107		.offset = 10,3108		.width = 2,3109	},3110	[VCAP_AF_MAP_LOOKUP_SEL] = {3111		.type = VCAP_FIELD_U32,3112		.offset = 12,3113		.width = 2,3114	},3115	[VCAP_AF_MAP_KEY] = {3116		.type = VCAP_FIELD_U32,3117		.offset = 14,3118		.width = 3,3119	},3120	[VCAP_AF_CLS_VID_SEL] = {3121		.type = VCAP_FIELD_U32,3122		.offset = 17,3123		.width = 3,3124	},3125	[VCAP_AF_VID_VAL] = {3126		.type = VCAP_FIELD_U32,3127		.offset = 23,3128		.width = 13,3129	},3130	[VCAP_AF_ISDX_ADD_REPLACE_SEL] = {3131		.type = VCAP_FIELD_BIT,3132		.offset = 46,3133		.width = 1,3134	},3135	[VCAP_AF_ISDX_VAL] = {3136		.type = VCAP_FIELD_U32,3137		.offset = 47,3138		.width = 12,3139	},3140	[VCAP_AF_NXT_IDX_CTRL] = {3141		.type = VCAP_FIELD_U32,3142		.offset = 90,3143		.width = 3,3144	},3145	[VCAP_AF_NXT_IDX] = {3146		.type = VCAP_FIELD_U32,3147		.offset = 93,3148		.width = 12,3149	},3150};3151 3152static const struct vcap_field is2_base_type_actionfield[] = {3153	[VCAP_AF_PIPELINE_FORCE_ENA] = {3154		.type = VCAP_FIELD_BIT,3155		.offset = 1,3156		.width = 1,3157	},3158	[VCAP_AF_PIPELINE_PT] = {3159		.type = VCAP_FIELD_U32,3160		.offset = 2,3161		.width = 5,3162	},3163	[VCAP_AF_HIT_ME_ONCE] = {3164		.type = VCAP_FIELD_BIT,3165		.offset = 7,3166		.width = 1,3167	},3168	[VCAP_AF_INTR_ENA] = {3169		.type = VCAP_FIELD_BIT,3170		.offset = 8,3171		.width = 1,3172	},3173	[VCAP_AF_CPU_COPY_ENA] = {3174		.type = VCAP_FIELD_BIT,3175		.offset = 9,3176		.width = 1,3177	},3178	[VCAP_AF_CPU_QUEUE_NUM] = {3179		.type = VCAP_FIELD_U32,3180		.offset = 10,3181		.width = 3,3182	},3183	[VCAP_AF_LRN_DIS] = {3184		.type = VCAP_FIELD_BIT,3185		.offset = 14,3186		.width = 1,3187	},3188	[VCAP_AF_RT_DIS] = {3189		.type = VCAP_FIELD_BIT,3190		.offset = 15,3191		.width = 1,3192	},3193	[VCAP_AF_POLICE_ENA] = {3194		.type = VCAP_FIELD_BIT,3195		.offset = 16,3196		.width = 1,3197	},3198	[VCAP_AF_POLICE_IDX] = {3199		.type = VCAP_FIELD_U32,3200		.offset = 17,3201		.width = 6,3202	},3203	[VCAP_AF_IGNORE_PIPELINE_CTRL] = {3204		.type = VCAP_FIELD_BIT,3205		.offset = 23,3206		.width = 1,3207	},3208	[VCAP_AF_MASK_MODE] = {3209		.type = VCAP_FIELD_U32,3210		.offset = 27,3211		.width = 3,3212	},3213	[VCAP_AF_PORT_MASK] = {3214		.type = VCAP_FIELD_U72,3215		.offset = 30,3216		.width = 68,3217	},3218	[VCAP_AF_MIRROR_PROBE] = {3219		.type = VCAP_FIELD_U32,3220		.offset = 111,3221		.width = 2,3222	},3223	[VCAP_AF_MATCH_ID] = {3224		.type = VCAP_FIELD_U32,3225		.offset = 159,3226		.width = 16,3227	},3228	[VCAP_AF_MATCH_ID_MASK] = {3229		.type = VCAP_FIELD_U32,3230		.offset = 175,3231		.width = 16,3232	},3233	[VCAP_AF_CNT_ID] = {3234		.type = VCAP_FIELD_U32,3235		.offset = 191,3236		.width = 12,3237	},3238};3239 3240static const struct vcap_field es2_base_type_actionfield[] = {3241	[VCAP_AF_HIT_ME_ONCE] = {3242		.type = VCAP_FIELD_BIT,3243		.offset = 0,3244		.width = 1,3245	},3246	[VCAP_AF_INTR_ENA] = {3247		.type = VCAP_FIELD_BIT,3248		.offset = 1,3249		.width = 1,3250	},3251	[VCAP_AF_FWD_MODE] = {3252		.type = VCAP_FIELD_U32,3253		.offset = 2,3254		.width = 2,3255	},3256	[VCAP_AF_COPY_QUEUE_NUM] = {3257		.type = VCAP_FIELD_U32,3258		.offset = 4,3259		.width = 16,3260	},3261	[VCAP_AF_COPY_PORT_NUM] = {3262		.type = VCAP_FIELD_U32,3263		.offset = 20,3264		.width = 7,3265	},3266	[VCAP_AF_MIRROR_PROBE_ID] = {3267		.type = VCAP_FIELD_U32,3268		.offset = 27,3269		.width = 2,3270	},3271	[VCAP_AF_CPU_COPY_ENA] = {3272		.type = VCAP_FIELD_BIT,3273		.offset = 29,3274		.width = 1,3275	},3276	[VCAP_AF_CPU_QUEUE_NUM] = {3277		.type = VCAP_FIELD_U32,3278		.offset = 30,3279		.width = 3,3280	},3281	[VCAP_AF_POLICE_ENA] = {3282		.type = VCAP_FIELD_BIT,3283		.offset = 33,3284		.width = 1,3285	},3286	[VCAP_AF_POLICE_REMARK] = {3287		.type = VCAP_FIELD_BIT,3288		.offset = 34,3289		.width = 1,3290	},3291	[VCAP_AF_POLICE_IDX] = {3292		.type = VCAP_FIELD_U32,3293		.offset = 35,3294		.width = 6,3295	},3296	[VCAP_AF_ES2_REW_CMD] = {3297		.type = VCAP_FIELD_U32,3298		.offset = 41,3299		.width = 3,3300	},3301	[VCAP_AF_CNT_ID] = {3302		.type = VCAP_FIELD_U32,3303		.offset = 44,3304		.width = 11,3305	},3306	[VCAP_AF_IGNORE_PIPELINE_CTRL] = {3307		.type = VCAP_FIELD_BIT,3308		.offset = 55,3309		.width = 1,3310	},3311};3312 3313/* actionfield_set */3314static const struct vcap_set is0_actionfield_set[] = {3315	[VCAP_AFS_CLASSIFICATION] = {3316		.type_id = 1,3317		.sw_per_item = 2,3318		.sw_cnt = 6,3319	},3320	[VCAP_AFS_FULL] = {3321		.type_id = -1,3322		.sw_per_item = 3,3323		.sw_cnt = 4,3324	},3325	[VCAP_AFS_CLASS_REDUCED] = {3326		.type_id = 1,3327		.sw_per_item = 1,3328		.sw_cnt = 12,3329	},3330};3331 3332static const struct vcap_set is2_actionfield_set[] = {3333	[VCAP_AFS_BASE_TYPE] = {3334		.type_id = -1,3335		.sw_per_item = 3,3336		.sw_cnt = 4,3337	},3338};3339 3340static const struct vcap_set es2_actionfield_set[] = {3341	[VCAP_AFS_BASE_TYPE] = {3342		.type_id = -1,3343		.sw_per_item = 3,3344		.sw_cnt = 4,3345	},3346};3347 3348/* actionfield_set map */3349static const struct vcap_field *is0_actionfield_set_map[] = {3350	[VCAP_AFS_CLASSIFICATION] = is0_classification_actionfield,3351	[VCAP_AFS_FULL] = is0_full_actionfield,3352	[VCAP_AFS_CLASS_REDUCED] = is0_class_reduced_actionfield,3353};3354 3355static const struct vcap_field *is2_actionfield_set_map[] = {3356	[VCAP_AFS_BASE_TYPE] = is2_base_type_actionfield,3357};3358 3359static const struct vcap_field *es2_actionfield_set_map[] = {3360	[VCAP_AFS_BASE_TYPE] = es2_base_type_actionfield,3361};3362 3363/* actionfield_set map size */3364static int is0_actionfield_set_map_size[] = {3365	[VCAP_AFS_CLASSIFICATION] = ARRAY_SIZE(is0_classification_actionfield),3366	[VCAP_AFS_FULL] = ARRAY_SIZE(is0_full_actionfield),3367	[VCAP_AFS_CLASS_REDUCED] = ARRAY_SIZE(is0_class_reduced_actionfield),3368};3369 3370static int is2_actionfield_set_map_size[] = {3371	[VCAP_AFS_BASE_TYPE] = ARRAY_SIZE(is2_base_type_actionfield),3372};3373 3374static int es2_actionfield_set_map_size[] = {3375	[VCAP_AFS_BASE_TYPE] = ARRAY_SIZE(es2_base_type_actionfield),3376};3377 3378/* Type Groups */3379static const struct vcap_typegroup is0_x12_keyfield_set_typegroups[] = {3380	{3381		.offset = 0,3382		.width = 5,3383		.value = 16,3384	},3385	{3386		.offset = 52,3387		.width = 1,3388		.value = 0,3389	},3390	{3391		.offset = 104,3392		.width = 2,3393		.value = 0,3394	},3395	{3396		.offset = 156,3397		.width = 3,3398		.value = 0,3399	},3400	{3401		.offset = 208,3402		.width = 2,3403		.value = 0,3404	},3405	{3406		.offset = 260,3407		.width = 1,3408		.value = 0,3409	},3410	{3411		.offset = 312,3412		.width = 4,3413		.value = 0,3414	},3415	{3416		.offset = 364,3417		.width = 1,3418		.value = 0,3419	},3420	{3421		.offset = 416,3422		.width = 2,3423		.value = 0,3424	},3425	{3426		.offset = 468,3427		.width = 3,3428		.value = 0,3429	},3430	{3431		.offset = 520,3432		.width = 2,3433		.value = 0,3434	},3435	{3436		.offset = 572,3437		.width = 1,3438		.value = 0,3439	},3440	{}3441};3442 3443static const struct vcap_typegroup is0_x6_keyfield_set_typegroups[] = {3444	{3445		.offset = 0,3446		.width = 4,3447		.value = 8,3448	},3449	{3450		.offset = 52,3451		.width = 1,3452		.value = 0,3453	},3454	{3455		.offset = 104,3456		.width = 2,3457		.value = 0,3458	},3459	{3460		.offset = 156,3461		.width = 3,3462		.value = 0,3463	},3464	{3465		.offset = 208,3466		.width = 2,3467		.value = 0,3468	},3469	{3470		.offset = 260,3471		.width = 1,3472		.value = 0,3473	},3474	{}3475};3476 3477static const struct vcap_typegroup is0_x3_keyfield_set_typegroups[] = {3478	{3479		.offset = 0,3480		.width = 3,3481		.value = 4,3482	},3483	{3484		.offset = 52,3485		.width = 2,3486		.value = 0,3487	},3488	{3489		.offset = 104,3490		.width = 2,3491		.value = 0,3492	},3493	{}3494};3495 3496static const struct vcap_typegroup is0_x2_keyfield_set_typegroups[] = {3497	{3498		.offset = 0,3499		.width = 2,3500		.value = 2,3501	},3502	{3503		.offset = 52,3504		.width = 1,3505		.value = 0,3506	},3507	{}3508};3509 3510static const struct vcap_typegroup is0_x1_keyfield_set_typegroups[] = {3511	{}3512};3513 3514static const struct vcap_typegroup is2_x12_keyfield_set_typegroups[] = {3515	{3516		.offset = 0,3517		.width = 3,3518		.value = 4,3519	},3520	{3521		.offset = 156,3522		.width = 1,3523		.value = 0,3524	},3525	{3526		.offset = 312,3527		.width = 2,3528		.value = 0,3529	},3530	{3531		.offset = 468,3532		.width = 1,3533		.value = 0,3534	},3535	{}3536};3537 3538static const struct vcap_typegroup is2_x6_keyfield_set_typegroups[] = {3539	{3540		.offset = 0,3541		.width = 2,3542		.value = 2,3543	},3544	{3545		.offset = 156,3546		.width = 1,3547		.value = 0,3548	},3549	{}3550};3551 3552static const struct vcap_typegroup is2_x3_keyfield_set_typegroups[] = {3553	{}3554};3555 3556static const struct vcap_typegroup is2_x1_keyfield_set_typegroups[] = {3557	{}3558};3559 3560static const struct vcap_typegroup es2_x12_keyfield_set_typegroups[] = {3561	{3562		.offset = 0,3563		.width = 3,3564		.value = 4,3565	},3566	{3567		.offset = 156,3568		.width = 1,3569		.value = 0,3570	},3571	{3572		.offset = 312,3573		.width = 2,3574		.value = 0,3575	},3576	{3577		.offset = 468,3578		.width = 1,3579		.value = 0,3580	},3581	{}3582};3583 3584static const struct vcap_typegroup es2_x6_keyfield_set_typegroups[] = {3585	{3586		.offset = 0,3587		.width = 2,3588		.value = 2,3589	},3590	{3591		.offset = 156,3592		.width = 1,3593		.value = 0,3594	},3595	{}3596};3597 3598static const struct vcap_typegroup es2_x3_keyfield_set_typegroups[] = {3599	{3600		.offset = 0,3601		.width = 1,3602		.value = 1,3603	},3604	{}3605};3606 3607static const struct vcap_typegroup es2_x1_keyfield_set_typegroups[] = {3608	{}3609};3610 3611static const struct vcap_typegroup *is0_keyfield_set_typegroups[] = {3612	[12] = is0_x12_keyfield_set_typegroups,3613	[6] = is0_x6_keyfield_set_typegroups,3614	[3] = is0_x3_keyfield_set_typegroups,3615	[2] = is0_x2_keyfield_set_typegroups,3616	[1] = is0_x1_keyfield_set_typegroups,3617	[13] = NULL,3618};3619 3620static const struct vcap_typegroup *is2_keyfield_set_typegroups[] = {3621	[12] = is2_x12_keyfield_set_typegroups,3622	[6] = is2_x6_keyfield_set_typegroups,3623	[3] = is2_x3_keyfield_set_typegroups,3624	[1] = is2_x1_keyfield_set_typegroups,3625	[13] = NULL,3626};3627 3628static const struct vcap_typegroup *es2_keyfield_set_typegroups[] = {3629	[12] = es2_x12_keyfield_set_typegroups,3630	[6] = es2_x6_keyfield_set_typegroups,3631	[3] = es2_x3_keyfield_set_typegroups,3632	[1] = es2_x1_keyfield_set_typegroups,3633	[13] = NULL,3634};3635 3636static const struct vcap_typegroup is0_x3_actionfield_set_typegroups[] = {3637	{3638		.offset = 0,3639		.width = 3,3640		.value = 4,3641	},3642	{3643		.offset = 110,3644		.width = 2,3645		.value = 0,3646	},3647	{3648		.offset = 220,3649		.width = 2,3650		.value = 0,3651	},3652	{}3653};3654 3655static const struct vcap_typegroup is0_x2_actionfield_set_typegroups[] = {3656	{3657		.offset = 0,3658		.width = 2,3659		.value = 2,3660	},3661	{3662		.offset = 110,3663		.width = 1,3664		.value = 0,3665	},3666	{}3667};3668 3669static const struct vcap_typegroup is0_x1_actionfield_set_typegroups[] = {3670	{3671		.offset = 0,3672		.width = 1,3673		.value = 1,3674	},3675	{}3676};3677 3678static const struct vcap_typegroup is2_x3_actionfield_set_typegroups[] = {3679	{3680		.offset = 0,3681		.width = 2,3682		.value = 2,3683	},3684	{3685		.offset = 110,3686		.width = 1,3687		.value = 0,3688	},3689	{3690		.offset = 220,3691		.width = 1,3692		.value = 0,3693	},3694	{}3695};3696 3697static const struct vcap_typegroup is2_x1_actionfield_set_typegroups[] = {3698	{}3699};3700 3701static const struct vcap_typegroup es2_x3_actionfield_set_typegroups[] = {3702	{3703		.offset = 0,3704		.width = 2,3705		.value = 2,3706	},3707	{3708		.offset = 21,3709		.width = 1,3710		.value = 0,3711	},3712	{3713		.offset = 42,3714		.width = 1,3715		.value = 0,3716	},3717	{}3718};3719 3720static const struct vcap_typegroup es2_x1_actionfield_set_typegroups[] = {3721	{}3722};3723 3724static const struct vcap_typegroup *is0_actionfield_set_typegroups[] = {3725	[3] = is0_x3_actionfield_set_typegroups,3726	[2] = is0_x2_actionfield_set_typegroups,3727	[1] = is0_x1_actionfield_set_typegroups,3728	[13] = NULL,3729};3730 3731static const struct vcap_typegroup *is2_actionfield_set_typegroups[] = {3732	[3] = is2_x3_actionfield_set_typegroups,3733	[1] = is2_x1_actionfield_set_typegroups,3734	[13] = NULL,3735};3736 3737static const struct vcap_typegroup *es2_actionfield_set_typegroups[] = {3738	[3] = es2_x3_actionfield_set_typegroups,3739	[1] = es2_x1_actionfield_set_typegroups,3740	[13] = NULL,3741};3742 3743/* Keyfieldset names */3744static const char * const vcap_keyfield_set_names[] = {3745	[VCAP_KFS_NO_VALUE]                      =  "(None)",3746	[VCAP_KFS_ARP]                           =  "VCAP_KFS_ARP",3747	[VCAP_KFS_ETAG]                          =  "VCAP_KFS_ETAG",3748	[VCAP_KFS_IP4_OTHER]                     =  "VCAP_KFS_IP4_OTHER",3749	[VCAP_KFS_IP4_TCP_UDP]                   =  "VCAP_KFS_IP4_TCP_UDP",3750	[VCAP_KFS_IP4_VID]                       =  "VCAP_KFS_IP4_VID",3751	[VCAP_KFS_IP6_OTHER]                     =  "VCAP_KFS_IP6_OTHER",3752	[VCAP_KFS_IP6_STD]                       =  "VCAP_KFS_IP6_STD",3753	[VCAP_KFS_IP6_TCP_UDP]                   =  "VCAP_KFS_IP6_TCP_UDP",3754	[VCAP_KFS_IP6_VID]                       =  "VCAP_KFS_IP6_VID",3755	[VCAP_KFS_IP_7TUPLE]                     =  "VCAP_KFS_IP_7TUPLE",3756	[VCAP_KFS_ISDX]                          =  "VCAP_KFS_ISDX",3757	[VCAP_KFS_LL_FULL]                       =  "VCAP_KFS_LL_FULL",3758	[VCAP_KFS_MAC_ETYPE]                     =  "VCAP_KFS_MAC_ETYPE",3759	[VCAP_KFS_MAC_LLC]                       =  "VCAP_KFS_MAC_LLC",3760	[VCAP_KFS_MAC_SNAP]                      =  "VCAP_KFS_MAC_SNAP",3761	[VCAP_KFS_NORMAL_5TUPLE_IP4]             =  "VCAP_KFS_NORMAL_5TUPLE_IP4",3762	[VCAP_KFS_NORMAL_7TUPLE]                 =  "VCAP_KFS_NORMAL_7TUPLE",3763	[VCAP_KFS_OAM]                           =  "VCAP_KFS_OAM",3764	[VCAP_KFS_PURE_5TUPLE_IP4]               =  "VCAP_KFS_PURE_5TUPLE_IP4",3765	[VCAP_KFS_SMAC_SIP4]                     =  "VCAP_KFS_SMAC_SIP4",3766	[VCAP_KFS_SMAC_SIP6]                     =  "VCAP_KFS_SMAC_SIP6",3767};3768 3769/* Actionfieldset names */3770static const char * const vcap_actionfield_set_names[] = {3771	[VCAP_AFS_NO_VALUE]                      =  "(None)",3772	[VCAP_AFS_BASE_TYPE]                     =  "VCAP_AFS_BASE_TYPE",3773	[VCAP_AFS_CLASSIFICATION]                =  "VCAP_AFS_CLASSIFICATION",3774	[VCAP_AFS_CLASS_REDUCED]                 =  "VCAP_AFS_CLASS_REDUCED",3775	[VCAP_AFS_ES0]                           =  "VCAP_AFS_ES0",3776	[VCAP_AFS_FULL]                          =  "VCAP_AFS_FULL",3777	[VCAP_AFS_SMAC_SIP]                      =  "VCAP_AFS_SMAC_SIP",3778};3779 3780/* Keyfield names */3781static const char * const vcap_keyfield_names[] = {3782	[VCAP_KF_NO_VALUE]                       =  "(None)",3783	[VCAP_KF_8021BR_ECID_BASE]               =  "8021BR_ECID_BASE",3784	[VCAP_KF_8021BR_ECID_EXT]                =  "8021BR_ECID_EXT",3785	[VCAP_KF_8021BR_E_TAGGED]                =  "8021BR_E_TAGGED",3786	[VCAP_KF_8021BR_GRP]                     =  "8021BR_GRP",3787	[VCAP_KF_8021BR_IGR_ECID_BASE]           =  "8021BR_IGR_ECID_BASE",3788	[VCAP_KF_8021BR_IGR_ECID_EXT]            =  "8021BR_IGR_ECID_EXT",3789	[VCAP_KF_8021Q_DEI0]                     =  "8021Q_DEI0",3790	[VCAP_KF_8021Q_DEI1]                     =  "8021Q_DEI1",3791	[VCAP_KF_8021Q_DEI2]                     =  "8021Q_DEI2",3792	[VCAP_KF_8021Q_DEI_CLS]                  =  "8021Q_DEI_CLS",3793	[VCAP_KF_8021Q_PCP0]                     =  "8021Q_PCP0",3794	[VCAP_KF_8021Q_PCP1]                     =  "8021Q_PCP1",3795	[VCAP_KF_8021Q_PCP2]                     =  "8021Q_PCP2",3796	[VCAP_KF_8021Q_PCP_CLS]                  =  "8021Q_PCP_CLS",3797	[VCAP_KF_8021Q_TPID]                     =  "8021Q_TPID",3798	[VCAP_KF_8021Q_TPID0]                    =  "8021Q_TPID0",3799	[VCAP_KF_8021Q_TPID1]                    =  "8021Q_TPID1",3800	[VCAP_KF_8021Q_TPID2]                    =  "8021Q_TPID2",3801	[VCAP_KF_8021Q_VID0]                     =  "8021Q_VID0",3802	[VCAP_KF_8021Q_VID1]                     =  "8021Q_VID1",3803	[VCAP_KF_8021Q_VID2]                     =  "8021Q_VID2",3804	[VCAP_KF_8021Q_VID_CLS]                  =  "8021Q_VID_CLS",3805	[VCAP_KF_8021Q_VLAN_TAGGED_IS]           =  "8021Q_VLAN_TAGGED_IS",3806	[VCAP_KF_8021Q_VLAN_TAGS]                =  "8021Q_VLAN_TAGS",3807	[VCAP_KF_ACL_GRP_ID]                     =  "ACL_GRP_ID",3808	[VCAP_KF_ARP_ADDR_SPACE_OK_IS]           =  "ARP_ADDR_SPACE_OK_IS",3809	[VCAP_KF_ARP_LEN_OK_IS]                  =  "ARP_LEN_OK_IS",3810	[VCAP_KF_ARP_OPCODE]                     =  "ARP_OPCODE",3811	[VCAP_KF_ARP_OPCODE_UNKNOWN_IS]          =  "ARP_OPCODE_UNKNOWN_IS",3812	[VCAP_KF_ARP_PROTO_SPACE_OK_IS]          =  "ARP_PROTO_SPACE_OK_IS",3813	[VCAP_KF_ARP_SENDER_MATCH_IS]            =  "ARP_SENDER_MATCH_IS",3814	[VCAP_KF_ARP_TGT_MATCH_IS]               =  "ARP_TGT_MATCH_IS",3815	[VCAP_KF_COSID_CLS]                      =  "COSID_CLS",3816	[VCAP_KF_ES0_ISDX_KEY_ENA]               =  "ES0_ISDX_KEY_ENA",3817	[VCAP_KF_ETYPE]                          =  "ETYPE",3818	[VCAP_KF_ETYPE_LEN_IS]                   =  "ETYPE_LEN_IS",3819	[VCAP_KF_HOST_MATCH]                     =  "HOST_MATCH",3820	[VCAP_KF_IF_EGR_PORT_MASK]               =  "IF_EGR_PORT_MASK",3821	[VCAP_KF_IF_EGR_PORT_MASK_RNG]           =  "IF_EGR_PORT_MASK_RNG",3822	[VCAP_KF_IF_EGR_PORT_NO]                 =  "IF_EGR_PORT_NO",3823	[VCAP_KF_IF_IGR_PORT]                    =  "IF_IGR_PORT",3824	[VCAP_KF_IF_IGR_PORT_MASK]               =  "IF_IGR_PORT_MASK",3825	[VCAP_KF_IF_IGR_PORT_MASK_L3]            =  "IF_IGR_PORT_MASK_L3",3826	[VCAP_KF_IF_IGR_PORT_MASK_RNG]           =  "IF_IGR_PORT_MASK_RNG",3827	[VCAP_KF_IF_IGR_PORT_MASK_SEL]           =  "IF_IGR_PORT_MASK_SEL",3828	[VCAP_KF_IF_IGR_PORT_SEL]                =  "IF_IGR_PORT_SEL",3829	[VCAP_KF_IP4_IS]                         =  "IP4_IS",3830	[VCAP_KF_IP_MC_IS]                       =  "IP_MC_IS",3831	[VCAP_KF_IP_PAYLOAD_5TUPLE]              =  "IP_PAYLOAD_5TUPLE",3832	[VCAP_KF_IP_SNAP_IS]                     =  "IP_SNAP_IS",3833	[VCAP_KF_ISDX_CLS]                       =  "ISDX_CLS",3834	[VCAP_KF_ISDX_GT0_IS]                    =  "ISDX_GT0_IS",3835	[VCAP_KF_L2_BC_IS]                       =  "L2_BC_IS",3836	[VCAP_KF_L2_DMAC]                        =  "L2_DMAC",3837	[VCAP_KF_L2_FRM_TYPE]                    =  "L2_FRM_TYPE",3838	[VCAP_KF_L2_FWD_IS]                      =  "L2_FWD_IS",3839	[VCAP_KF_L2_LLC]                         =  "L2_LLC",3840	[VCAP_KF_L2_MC_IS]                       =  "L2_MC_IS",3841	[VCAP_KF_L2_PAYLOAD0]                    =  "L2_PAYLOAD0",3842	[VCAP_KF_L2_PAYLOAD1]                    =  "L2_PAYLOAD1",3843	[VCAP_KF_L2_PAYLOAD2]                    =  "L2_PAYLOAD2",3844	[VCAP_KF_L2_PAYLOAD_ETYPE]               =  "L2_PAYLOAD_ETYPE",3845	[VCAP_KF_L2_SMAC]                        =  "L2_SMAC",3846	[VCAP_KF_L2_SNAP]                        =  "L2_SNAP",3847	[VCAP_KF_L3_DIP_EQ_SIP_IS]               =  "L3_DIP_EQ_SIP_IS",3848	[VCAP_KF_L3_DPL_CLS]                     =  "L3_DPL_CLS",3849	[VCAP_KF_L3_DSCP]                        =  "L3_DSCP",3850	[VCAP_KF_L3_DST_IS]                      =  "L3_DST_IS",3851	[VCAP_KF_L3_FRAGMENT]                    =  "L3_FRAGMENT",3852	[VCAP_KF_L3_FRAGMENT_TYPE]               =  "L3_FRAGMENT_TYPE",3853	[VCAP_KF_L3_FRAG_INVLD_L4_LEN]           =  "L3_FRAG_INVLD_L4_LEN",3854	[VCAP_KF_L3_FRAG_OFS_GT0]                =  "L3_FRAG_OFS_GT0",3855	[VCAP_KF_L3_IP4_DIP]                     =  "L3_IP4_DIP",3856	[VCAP_KF_L3_IP4_SIP]                     =  "L3_IP4_SIP",3857	[VCAP_KF_L3_IP6_DIP]                     =  "L3_IP6_DIP",3858	[VCAP_KF_L3_IP6_SIP]                     =  "L3_IP6_SIP",3859	[VCAP_KF_L3_IP_PROTO]                    =  "L3_IP_PROTO",3860	[VCAP_KF_L3_OPTIONS_IS]                  =  "L3_OPTIONS_IS",3861	[VCAP_KF_L3_PAYLOAD]                     =  "L3_PAYLOAD",3862	[VCAP_KF_L3_RT_IS]                       =  "L3_RT_IS",3863	[VCAP_KF_L3_TOS]                         =  "L3_TOS",3864	[VCAP_KF_L3_TTL_GT0]                     =  "L3_TTL_GT0",3865	[VCAP_KF_L4_1588_DOM]                    =  "L4_1588_DOM",3866	[VCAP_KF_L4_1588_VER]                    =  "L4_1588_VER",3867	[VCAP_KF_L4_ACK]                         =  "L4_ACK",3868	[VCAP_KF_L4_DPORT]                       =  "L4_DPORT",3869	[VCAP_KF_L4_FIN]                         =  "L4_FIN",3870	[VCAP_KF_L4_PAYLOAD]                     =  "L4_PAYLOAD",3871	[VCAP_KF_L4_PSH]                         =  "L4_PSH",3872	[VCAP_KF_L4_RNG]                         =  "L4_RNG",3873	[VCAP_KF_L4_RST]                         =  "L4_RST",3874	[VCAP_KF_L4_SEQUENCE_EQ0_IS]             =  "L4_SEQUENCE_EQ0_IS",3875	[VCAP_KF_L4_SPORT]                       =  "L4_SPORT",3876	[VCAP_KF_L4_SPORT_EQ_DPORT_IS]           =  "L4_SPORT_EQ_DPORT_IS",3877	[VCAP_KF_L4_SYN]                         =  "L4_SYN",3878	[VCAP_KF_L4_URG]                         =  "L4_URG",3879	[VCAP_KF_LOOKUP_FIRST_IS]                =  "LOOKUP_FIRST_IS",3880	[VCAP_KF_LOOKUP_GEN_IDX]                 =  "LOOKUP_GEN_IDX",3881	[VCAP_KF_LOOKUP_GEN_IDX_SEL]             =  "LOOKUP_GEN_IDX_SEL",3882	[VCAP_KF_LOOKUP_PAG]                     =  "LOOKUP_PAG",3883	[VCAP_KF_MIRROR_PROBE]                   =  "MIRROR_PROBE",3884	[VCAP_KF_OAM_CCM_CNTS_EQ0]               =  "OAM_CCM_CNTS_EQ0",3885	[VCAP_KF_OAM_DETECTED]                   =  "OAM_DETECTED",3886	[VCAP_KF_OAM_FLAGS]                      =  "OAM_FLAGS",3887	[VCAP_KF_OAM_MEL_FLAGS]                  =  "OAM_MEL_FLAGS",3888	[VCAP_KF_OAM_MEPID]                      =  "OAM_MEPID",3889	[VCAP_KF_OAM_OPCODE]                     =  "OAM_OPCODE",3890	[VCAP_KF_OAM_VER]                        =  "OAM_VER",3891	[VCAP_KF_OAM_Y1731_IS]                   =  "OAM_Y1731_IS",3892	[VCAP_KF_PROT_ACTIVE]                    =  "PROT_ACTIVE",3893	[VCAP_KF_TCP_IS]                         =  "TCP_IS",3894	[VCAP_KF_TCP_UDP_IS]                     =  "TCP_UDP_IS",3895	[VCAP_KF_TYPE]                           =  "TYPE",3896};3897 3898/* Actionfield names */3899static const char * const vcap_actionfield_names[] = {3900	[VCAP_AF_NO_VALUE]                       =  "(None)",3901	[VCAP_AF_ACL_ID]                         =  "ACL_ID",3902	[VCAP_AF_CLS_VID_SEL]                    =  "CLS_VID_SEL",3903	[VCAP_AF_CNT_ID]                         =  "CNT_ID",3904	[VCAP_AF_COPY_PORT_NUM]                  =  "COPY_PORT_NUM",3905	[VCAP_AF_COPY_QUEUE_NUM]                 =  "COPY_QUEUE_NUM",3906	[VCAP_AF_CPU_COPY_ENA]                   =  "CPU_COPY_ENA",3907	[VCAP_AF_CPU_QU]                         =  "CPU_QU",3908	[VCAP_AF_CPU_QUEUE_NUM]                  =  "CPU_QUEUE_NUM",3909	[VCAP_AF_DEI_A_VAL]                      =  "DEI_A_VAL",3910	[VCAP_AF_DEI_B_VAL]                      =  "DEI_B_VAL",3911	[VCAP_AF_DEI_C_VAL]                      =  "DEI_C_VAL",3912	[VCAP_AF_DEI_ENA]                        =  "DEI_ENA",3913	[VCAP_AF_DEI_VAL]                        =  "DEI_VAL",3914	[VCAP_AF_DP_ENA]                         =  "DP_ENA",3915	[VCAP_AF_DP_VAL]                         =  "DP_VAL",3916	[VCAP_AF_DSCP_ENA]                       =  "DSCP_ENA",3917	[VCAP_AF_DSCP_SEL]                       =  "DSCP_SEL",3918	[VCAP_AF_DSCP_VAL]                       =  "DSCP_VAL",3919	[VCAP_AF_ES2_REW_CMD]                    =  "ES2_REW_CMD",3920	[VCAP_AF_ESDX]                           =  "ESDX",3921	[VCAP_AF_FWD_KILL_ENA]                   =  "FWD_KILL_ENA",3922	[VCAP_AF_FWD_MODE]                       =  "FWD_MODE",3923	[VCAP_AF_FWD_SEL]                        =  "FWD_SEL",3924	[VCAP_AF_HIT_ME_ONCE]                    =  "HIT_ME_ONCE",3925	[VCAP_AF_HOST_MATCH]                     =  "HOST_MATCH",3926	[VCAP_AF_IGNORE_PIPELINE_CTRL]           =  "IGNORE_PIPELINE_CTRL",3927	[VCAP_AF_INTR_ENA]                       =  "INTR_ENA",3928	[VCAP_AF_ISDX_ADD_REPLACE_SEL]           =  "ISDX_ADD_REPLACE_SEL",3929	[VCAP_AF_ISDX_ENA]                       =  "ISDX_ENA",3930	[VCAP_AF_ISDX_VAL]                       =  "ISDX_VAL",3931	[VCAP_AF_LOOP_ENA]                       =  "LOOP_ENA",3932	[VCAP_AF_LRN_DIS]                        =  "LRN_DIS",3933	[VCAP_AF_MAP_IDX]                        =  "MAP_IDX",3934	[VCAP_AF_MAP_KEY]                        =  "MAP_KEY",3935	[VCAP_AF_MAP_LOOKUP_SEL]                 =  "MAP_LOOKUP_SEL",3936	[VCAP_AF_MASK_MODE]                      =  "MASK_MODE",3937	[VCAP_AF_MATCH_ID]                       =  "MATCH_ID",3938	[VCAP_AF_MATCH_ID_MASK]                  =  "MATCH_ID_MASK",3939	[VCAP_AF_MIRROR_ENA]                     =  "MIRROR_ENA",3940	[VCAP_AF_MIRROR_PROBE]                   =  "MIRROR_PROBE",3941	[VCAP_AF_MIRROR_PROBE_ID]                =  "MIRROR_PROBE_ID",3942	[VCAP_AF_NXT_IDX]                        =  "NXT_IDX",3943	[VCAP_AF_NXT_IDX_CTRL]                   =  "NXT_IDX_CTRL",3944	[VCAP_AF_PAG_OVERRIDE_MASK]              =  "PAG_OVERRIDE_MASK",3945	[VCAP_AF_PAG_VAL]                        =  "PAG_VAL",3946	[VCAP_AF_PCP_A_VAL]                      =  "PCP_A_VAL",3947	[VCAP_AF_PCP_B_VAL]                      =  "PCP_B_VAL",3948	[VCAP_AF_PCP_C_VAL]                      =  "PCP_C_VAL",3949	[VCAP_AF_PCP_ENA]                        =  "PCP_ENA",3950	[VCAP_AF_PCP_VAL]                        =  "PCP_VAL",3951	[VCAP_AF_PIPELINE_ACT]                   =  "PIPELINE_ACT",3952	[VCAP_AF_PIPELINE_FORCE_ENA]             =  "PIPELINE_FORCE_ENA",3953	[VCAP_AF_PIPELINE_PT]                    =  "PIPELINE_PT",3954	[VCAP_AF_POLICE_ENA]                     =  "POLICE_ENA",3955	[VCAP_AF_POLICE_IDX]                     =  "POLICE_IDX",3956	[VCAP_AF_POLICE_REMARK]                  =  "POLICE_REMARK",3957	[VCAP_AF_POLICE_VCAP_ONLY]               =  "POLICE_VCAP_ONLY",3958	[VCAP_AF_POP_VAL]                        =  "POP_VAL",3959	[VCAP_AF_PORT_MASK]                      =  "PORT_MASK",3960	[VCAP_AF_PUSH_CUSTOMER_TAG]              =  "PUSH_CUSTOMER_TAG",3961	[VCAP_AF_PUSH_INNER_TAG]                 =  "PUSH_INNER_TAG",3962	[VCAP_AF_PUSH_OUTER_TAG]                 =  "PUSH_OUTER_TAG",3963	[VCAP_AF_QOS_ENA]                        =  "QOS_ENA",3964	[VCAP_AF_QOS_VAL]                        =  "QOS_VAL",3965	[VCAP_AF_REW_OP]                         =  "REW_OP",3966	[VCAP_AF_RT_DIS]                         =  "RT_DIS",3967	[VCAP_AF_SWAP_MACS_ENA]                  =  "SWAP_MACS_ENA",3968	[VCAP_AF_TAG_A_DEI_SEL]                  =  "TAG_A_DEI_SEL",3969	[VCAP_AF_TAG_A_PCP_SEL]                  =  "TAG_A_PCP_SEL",3970	[VCAP_AF_TAG_A_TPID_SEL]                 =  "TAG_A_TPID_SEL",3971	[VCAP_AF_TAG_A_VID_SEL]                  =  "TAG_A_VID_SEL",3972	[VCAP_AF_TAG_B_DEI_SEL]                  =  "TAG_B_DEI_SEL",3973	[VCAP_AF_TAG_B_PCP_SEL]                  =  "TAG_B_PCP_SEL",3974	[VCAP_AF_TAG_B_TPID_SEL]                 =  "TAG_B_TPID_SEL",3975	[VCAP_AF_TAG_B_VID_SEL]                  =  "TAG_B_VID_SEL",3976	[VCAP_AF_TAG_C_DEI_SEL]                  =  "TAG_C_DEI_SEL",3977	[VCAP_AF_TAG_C_PCP_SEL]                  =  "TAG_C_PCP_SEL",3978	[VCAP_AF_TAG_C_TPID_SEL]                 =  "TAG_C_TPID_SEL",3979	[VCAP_AF_TAG_C_VID_SEL]                  =  "TAG_C_VID_SEL",3980	[VCAP_AF_TYPE]                           =  "TYPE",3981	[VCAP_AF_UNTAG_VID_ENA]                  =  "UNTAG_VID_ENA",3982	[VCAP_AF_VID_A_VAL]                      =  "VID_A_VAL",3983	[VCAP_AF_VID_B_VAL]                      =  "VID_B_VAL",3984	[VCAP_AF_VID_C_VAL]                      =  "VID_C_VAL",3985	[VCAP_AF_VID_VAL]                        =  "VID_VAL",3986};3987 3988/* VCAPs */3989const struct vcap_info kunit_test_vcaps[] = {3990	[VCAP_TYPE_IS0] = {3991		.name = "is0",3992		.rows = 1024,3993		.sw_count = 12,3994		.sw_width = 52,3995		.sticky_width = 1,3996		.act_width = 110,3997		.default_cnt = 140,3998		.require_cnt_dis = 0,3999		.version = 1,4000		.keyfield_set = is0_keyfield_set,4001		.keyfield_set_size = ARRAY_SIZE(is0_keyfield_set),4002		.actionfield_set = is0_actionfield_set,4003		.actionfield_set_size = ARRAY_SIZE(is0_actionfield_set),4004		.keyfield_set_map = is0_keyfield_set_map,4005		.keyfield_set_map_size = is0_keyfield_set_map_size,4006		.actionfield_set_map = is0_actionfield_set_map,4007		.actionfield_set_map_size = is0_actionfield_set_map_size,4008		.keyfield_set_typegroups = is0_keyfield_set_typegroups,4009		.actionfield_set_typegroups = is0_actionfield_set_typegroups,4010	},4011	[VCAP_TYPE_IS2] = {4012		.name = "is2",4013		.rows = 256,4014		.sw_count = 12,4015		.sw_width = 52,4016		.sticky_width = 1,4017		.act_width = 110,4018		.default_cnt = 73,4019		.require_cnt_dis = 0,4020		.version = 1,4021		.keyfield_set = is2_keyfield_set,4022		.keyfield_set_size = ARRAY_SIZE(is2_keyfield_set),4023		.actionfield_set = is2_actionfield_set,4024		.actionfield_set_size = ARRAY_SIZE(is2_actionfield_set),4025		.keyfield_set_map = is2_keyfield_set_map,4026		.keyfield_set_map_size = is2_keyfield_set_map_size,4027		.actionfield_set_map = is2_actionfield_set_map,4028		.actionfield_set_map_size = is2_actionfield_set_map_size,4029		.keyfield_set_typegroups = is2_keyfield_set_typegroups,4030		.actionfield_set_typegroups = is2_actionfield_set_typegroups,4031	},4032	[VCAP_TYPE_ES2] = {4033		.name = "es2",4034		.rows = 1024,4035		.sw_count = 12,4036		.sw_width = 52,4037		.sticky_width = 1,4038		.act_width = 21,4039		.default_cnt = 74,4040		.require_cnt_dis = 0,4041		.version = 1,4042		.keyfield_set = es2_keyfield_set,4043		.keyfield_set_size = ARRAY_SIZE(es2_keyfield_set),4044		.actionfield_set = es2_actionfield_set,4045		.actionfield_set_size = ARRAY_SIZE(es2_actionfield_set),4046		.keyfield_set_map = es2_keyfield_set_map,4047		.keyfield_set_map_size = es2_keyfield_set_map_size,4048		.actionfield_set_map = es2_actionfield_set_map,4049		.actionfield_set_map_size = es2_actionfield_set_map_size,4050		.keyfield_set_typegroups = es2_keyfield_set_typegroups,4051		.actionfield_set_typegroups = es2_actionfield_set_typegroups,4052	},4053};4054 4055const struct vcap_statistics kunit_test_vcap_stats = {4056	.name = "kunit_test",4057	.count = 3,4058	.keyfield_set_names = vcap_keyfield_set_names,4059	.actionfield_set_names = vcap_actionfield_set_names,4060	.keyfield_names = vcap_keyfield_names,4061	.actionfield_names = vcap_actionfield_names,4062};4063