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1// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause2/* Copyright (c) 2021, Microsoft Corporation. */3 4#include <linux/module.h>5#include <linux/pci.h>6#include <linux/utsname.h>7#include <linux/version.h>8 9#include <net/mana/mana.h>10 11static u32 mana_gd_r32(struct gdma_context *g, u64 offset)12{13 return readl(g->bar0_va + offset);14}15 16static u64 mana_gd_r64(struct gdma_context *g, u64 offset)17{18 return readq(g->bar0_va + offset);19}20 21static void mana_gd_init_pf_regs(struct pci_dev *pdev)22{23 struct gdma_context *gc = pci_get_drvdata(pdev);24 void __iomem *sriov_base_va;25 u64 sriov_base_off;26 27 gc->db_page_size = mana_gd_r32(gc, GDMA_PF_REG_DB_PAGE_SIZE) & 0xFFFF;28 gc->db_page_base = gc->bar0_va +29 mana_gd_r64(gc, GDMA_PF_REG_DB_PAGE_OFF);30 31 sriov_base_off = mana_gd_r64(gc, GDMA_SRIOV_REG_CFG_BASE_OFF);32 33 sriov_base_va = gc->bar0_va + sriov_base_off;34 gc->shm_base = sriov_base_va +35 mana_gd_r64(gc, sriov_base_off + GDMA_PF_REG_SHM_OFF);36}37 38static void mana_gd_init_vf_regs(struct pci_dev *pdev)39{40 struct gdma_context *gc = pci_get_drvdata(pdev);41 42 gc->db_page_size = mana_gd_r32(gc, GDMA_REG_DB_PAGE_SIZE) & 0xFFFF;43 44 gc->db_page_base = gc->bar0_va +45 mana_gd_r64(gc, GDMA_REG_DB_PAGE_OFFSET);46 47 gc->phys_db_page_base = gc->bar0_pa +48 mana_gd_r64(gc, GDMA_REG_DB_PAGE_OFFSET);49 50 gc->shm_base = gc->bar0_va + mana_gd_r64(gc, GDMA_REG_SHM_OFFSET);51}52 53static void mana_gd_init_registers(struct pci_dev *pdev)54{55 struct gdma_context *gc = pci_get_drvdata(pdev);56 57 if (gc->is_pf)58 mana_gd_init_pf_regs(pdev);59 else60 mana_gd_init_vf_regs(pdev);61}62 63static int mana_gd_query_max_resources(struct pci_dev *pdev)64{65 struct gdma_context *gc = pci_get_drvdata(pdev);66 struct gdma_query_max_resources_resp resp = {};67 struct gdma_general_req req = {};68 int err;69 70 mana_gd_init_req_hdr(&req.hdr, GDMA_QUERY_MAX_RESOURCES,71 sizeof(req), sizeof(resp));72 73 err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp);74 if (err || resp.hdr.status) {75 dev_err(gc->dev, "Failed to query resource info: %d, 0x%x\n",76 err, resp.hdr.status);77 return err ? err : -EPROTO;78 }79 80 if (gc->num_msix_usable > resp.max_msix)81 gc->num_msix_usable = resp.max_msix;82 83 if (gc->num_msix_usable <= 1)84 return -ENOSPC;85 86 gc->max_num_queues = num_online_cpus();87 if (gc->max_num_queues > MANA_MAX_NUM_QUEUES)88 gc->max_num_queues = MANA_MAX_NUM_QUEUES;89 90 if (gc->max_num_queues > resp.max_eq)91 gc->max_num_queues = resp.max_eq;92 93 if (gc->max_num_queues > resp.max_cq)94 gc->max_num_queues = resp.max_cq;95 96 if (gc->max_num_queues > resp.max_sq)97 gc->max_num_queues = resp.max_sq;98 99 if (gc->max_num_queues > resp.max_rq)100 gc->max_num_queues = resp.max_rq;101 102 /* The Hardware Channel (HWC) used 1 MSI-X */103 if (gc->max_num_queues > gc->num_msix_usable - 1)104 gc->max_num_queues = gc->num_msix_usable - 1;105 106 return 0;107}108 109static int mana_gd_query_hwc_timeout(struct pci_dev *pdev, u32 *timeout_val)110{111 struct gdma_context *gc = pci_get_drvdata(pdev);112 struct gdma_query_hwc_timeout_resp resp = {};113 struct gdma_query_hwc_timeout_req req = {};114 int err;115 116 mana_gd_init_req_hdr(&req.hdr, GDMA_QUERY_HWC_TIMEOUT,117 sizeof(req), sizeof(resp));118 req.timeout_ms = *timeout_val;119 err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp);120 if (err || resp.hdr.status)121 return err ? err : -EPROTO;122 123 *timeout_val = resp.timeout_ms;124 125 return 0;126}127 128static int mana_gd_detect_devices(struct pci_dev *pdev)129{130 struct gdma_context *gc = pci_get_drvdata(pdev);131 struct gdma_list_devices_resp resp = {};132 struct gdma_general_req req = {};133 struct gdma_dev_id dev;134 u32 i, max_num_devs;135 u16 dev_type;136 int err;137 138 mana_gd_init_req_hdr(&req.hdr, GDMA_LIST_DEVICES, sizeof(req),139 sizeof(resp));140 141 err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp);142 if (err || resp.hdr.status) {143 dev_err(gc->dev, "Failed to detect devices: %d, 0x%x\n", err,144 resp.hdr.status);145 return err ? err : -EPROTO;146 }147 148 max_num_devs = min_t(u32, MAX_NUM_GDMA_DEVICES, resp.num_of_devs);149 150 for (i = 0; i < max_num_devs; i++) {151 dev = resp.devs[i];152 dev_type = dev.type;153 154 /* HWC is already detected in mana_hwc_create_channel(). */155 if (dev_type == GDMA_DEVICE_HWC)156 continue;157 158 if (dev_type == GDMA_DEVICE_MANA) {159 gc->mana.gdma_context = gc;160 gc->mana.dev_id = dev;161 } else if (dev_type == GDMA_DEVICE_MANA_IB) {162 gc->mana_ib.dev_id = dev;163 gc->mana_ib.gdma_context = gc;164 }165 }166 167 return gc->mana.dev_id.type == 0 ? -ENODEV : 0;168}169 170int mana_gd_send_request(struct gdma_context *gc, u32 req_len, const void *req,171 u32 resp_len, void *resp)172{173 struct hw_channel_context *hwc = gc->hwc.driver_data;174 175 return mana_hwc_send_request(hwc, req_len, req, resp_len, resp);176}177EXPORT_SYMBOL_NS(mana_gd_send_request, NET_MANA);178 179int mana_gd_alloc_memory(struct gdma_context *gc, unsigned int length,180 struct gdma_mem_info *gmi)181{182 dma_addr_t dma_handle;183 void *buf;184 185 if (length < MANA_PAGE_SIZE || !is_power_of_2(length))186 return -EINVAL;187 188 gmi->dev = gc->dev;189 buf = dma_alloc_coherent(gmi->dev, length, &dma_handle, GFP_KERNEL);190 if (!buf)191 return -ENOMEM;192 193 gmi->dma_handle = dma_handle;194 gmi->virt_addr = buf;195 gmi->length = length;196 197 return 0;198}199 200void mana_gd_free_memory(struct gdma_mem_info *gmi)201{202 dma_free_coherent(gmi->dev, gmi->length, gmi->virt_addr,203 gmi->dma_handle);204}205 206static int mana_gd_create_hw_eq(struct gdma_context *gc,207 struct gdma_queue *queue)208{209 struct gdma_create_queue_resp resp = {};210 struct gdma_create_queue_req req = {};211 int err;212 213 if (queue->type != GDMA_EQ)214 return -EINVAL;215 216 mana_gd_init_req_hdr(&req.hdr, GDMA_CREATE_QUEUE,217 sizeof(req), sizeof(resp));218 219 req.hdr.dev_id = queue->gdma_dev->dev_id;220 req.type = queue->type;221 req.pdid = queue->gdma_dev->pdid;222 req.doolbell_id = queue->gdma_dev->doorbell;223 req.gdma_region = queue->mem_info.dma_region_handle;224 req.queue_size = queue->queue_size;225 req.log2_throttle_limit = queue->eq.log2_throttle_limit;226 req.eq_pci_msix_index = queue->eq.msix_index;227 228 err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp);229 if (err || resp.hdr.status) {230 dev_err(gc->dev, "Failed to create queue: %d, 0x%x\n", err,231 resp.hdr.status);232 return err ? err : -EPROTO;233 }234 235 queue->id = resp.queue_index;236 queue->eq.disable_needed = true;237 queue->mem_info.dma_region_handle = GDMA_INVALID_DMA_REGION;238 return 0;239}240 241static int mana_gd_disable_queue(struct gdma_queue *queue)242{243 struct gdma_context *gc = queue->gdma_dev->gdma_context;244 struct gdma_disable_queue_req req = {};245 struct gdma_general_resp resp = {};246 int err;247 248 WARN_ON(queue->type != GDMA_EQ);249 250 mana_gd_init_req_hdr(&req.hdr, GDMA_DISABLE_QUEUE,251 sizeof(req), sizeof(resp));252 253 req.hdr.dev_id = queue->gdma_dev->dev_id;254 req.type = queue->type;255 req.queue_index = queue->id;256 req.alloc_res_id_on_creation = 1;257 258 err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp);259 if (err || resp.hdr.status) {260 dev_err(gc->dev, "Failed to disable queue: %d, 0x%x\n", err,261 resp.hdr.status);262 return err ? err : -EPROTO;263 }264 265 return 0;266}267 268#define DOORBELL_OFFSET_SQ 0x0269#define DOORBELL_OFFSET_RQ 0x400270#define DOORBELL_OFFSET_CQ 0x800271#define DOORBELL_OFFSET_EQ 0xFF8272 273static void mana_gd_ring_doorbell(struct gdma_context *gc, u32 db_index,274 enum gdma_queue_type q_type, u32 qid,275 u32 tail_ptr, u8 num_req)276{277 void __iomem *addr = gc->db_page_base + gc->db_page_size * db_index;278 union gdma_doorbell_entry e = {};279 280 switch (q_type) {281 case GDMA_EQ:282 e.eq.id = qid;283 e.eq.tail_ptr = tail_ptr;284 e.eq.arm = num_req;285 286 addr += DOORBELL_OFFSET_EQ;287 break;288 289 case GDMA_CQ:290 e.cq.id = qid;291 e.cq.tail_ptr = tail_ptr;292 e.cq.arm = num_req;293 294 addr += DOORBELL_OFFSET_CQ;295 break;296 297 case GDMA_RQ:298 e.rq.id = qid;299 e.rq.tail_ptr = tail_ptr;300 e.rq.wqe_cnt = num_req;301 302 addr += DOORBELL_OFFSET_RQ;303 break;304 305 case GDMA_SQ:306 e.sq.id = qid;307 e.sq.tail_ptr = tail_ptr;308 309 addr += DOORBELL_OFFSET_SQ;310 break;311 312 default:313 WARN_ON(1);314 return;315 }316 317 /* Ensure all writes are done before ring doorbell */318 wmb();319 320 writeq(e.as_uint64, addr);321}322 323void mana_gd_wq_ring_doorbell(struct gdma_context *gc, struct gdma_queue *queue)324{325 /* Hardware Spec specifies that software client should set 0 for326 * wqe_cnt for Receive Queues. This value is not used in Send Queues.327 */328 mana_gd_ring_doorbell(gc, queue->gdma_dev->doorbell, queue->type,329 queue->id, queue->head * GDMA_WQE_BU_SIZE, 0);330}331 332void mana_gd_ring_cq(struct gdma_queue *cq, u8 arm_bit)333{334 struct gdma_context *gc = cq->gdma_dev->gdma_context;335 336 u32 num_cqe = cq->queue_size / GDMA_CQE_SIZE;337 338 u32 head = cq->head % (num_cqe << GDMA_CQE_OWNER_BITS);339 340 mana_gd_ring_doorbell(gc, cq->gdma_dev->doorbell, cq->type, cq->id,341 head, arm_bit);342}343 344static void mana_gd_process_eqe(struct gdma_queue *eq)345{346 u32 head = eq->head % (eq->queue_size / GDMA_EQE_SIZE);347 struct gdma_context *gc = eq->gdma_dev->gdma_context;348 struct gdma_eqe *eq_eqe_ptr = eq->queue_mem_ptr;349 union gdma_eqe_info eqe_info;350 enum gdma_eqe_type type;351 struct gdma_event event;352 struct gdma_queue *cq;353 struct gdma_eqe *eqe;354 u32 cq_id;355 356 eqe = &eq_eqe_ptr[head];357 eqe_info.as_uint32 = eqe->eqe_info;358 type = eqe_info.type;359 360 switch (type) {361 case GDMA_EQE_COMPLETION:362 cq_id = eqe->details[0] & 0xFFFFFF;363 if (WARN_ON_ONCE(cq_id >= gc->max_num_cqs))364 break;365 366 cq = gc->cq_table[cq_id];367 if (WARN_ON_ONCE(!cq || cq->type != GDMA_CQ || cq->id != cq_id))368 break;369 370 if (cq->cq.callback)371 cq->cq.callback(cq->cq.context, cq);372 373 break;374 375 case GDMA_EQE_TEST_EVENT:376 gc->test_event_eq_id = eq->id;377 complete(&gc->eq_test_event);378 break;379 380 case GDMA_EQE_HWC_INIT_EQ_ID_DB:381 case GDMA_EQE_HWC_INIT_DATA:382 case GDMA_EQE_HWC_INIT_DONE:383 case GDMA_EQE_RNIC_QP_FATAL:384 if (!eq->eq.callback)385 break;386 387 event.type = type;388 memcpy(&event.details, &eqe->details, GDMA_EVENT_DATA_SIZE);389 eq->eq.callback(eq->eq.context, eq, &event);390 break;391 392 default:393 break;394 }395}396 397static void mana_gd_process_eq_events(void *arg)398{399 u32 owner_bits, new_bits, old_bits;400 union gdma_eqe_info eqe_info;401 struct gdma_eqe *eq_eqe_ptr;402 struct gdma_queue *eq = arg;403 struct gdma_context *gc;404 struct gdma_eqe *eqe;405 u32 head, num_eqe;406 int i;407 408 gc = eq->gdma_dev->gdma_context;409 410 num_eqe = eq->queue_size / GDMA_EQE_SIZE;411 eq_eqe_ptr = eq->queue_mem_ptr;412 413 /* Process up to 5 EQEs at a time, and update the HW head. */414 for (i = 0; i < 5; i++) {415 eqe = &eq_eqe_ptr[eq->head % num_eqe];416 eqe_info.as_uint32 = eqe->eqe_info;417 owner_bits = eqe_info.owner_bits;418 419 old_bits = (eq->head / num_eqe - 1) & GDMA_EQE_OWNER_MASK;420 /* No more entries */421 if (owner_bits == old_bits) {422 /* return here without ringing the doorbell */423 if (i == 0)424 return;425 break;426 }427 428 new_bits = (eq->head / num_eqe) & GDMA_EQE_OWNER_MASK;429 if (owner_bits != new_bits) {430 dev_err(gc->dev, "EQ %d: overflow detected\n", eq->id);431 break;432 }433 434 /* Per GDMA spec, rmb is necessary after checking owner_bits, before435 * reading eqe.436 */437 rmb();438 439 mana_gd_process_eqe(eq);440 441 eq->head++;442 }443 444 head = eq->head % (num_eqe << GDMA_EQE_OWNER_BITS);445 446 mana_gd_ring_doorbell(gc, eq->gdma_dev->doorbell, eq->type, eq->id,447 head, SET_ARM_BIT);448}449 450static int mana_gd_register_irq(struct gdma_queue *queue,451 const struct gdma_queue_spec *spec)452{453 struct gdma_dev *gd = queue->gdma_dev;454 struct gdma_irq_context *gic;455 struct gdma_context *gc;456 unsigned int msi_index;457 unsigned long flags;458 struct device *dev;459 int err = 0;460 461 gc = gd->gdma_context;462 dev = gc->dev;463 msi_index = spec->eq.msix_index;464 465 if (msi_index >= gc->num_msix_usable) {466 err = -ENOSPC;467 dev_err(dev, "Register IRQ err:%d, msi:%u nMSI:%u",468 err, msi_index, gc->num_msix_usable);469 470 return err;471 }472 473 queue->eq.msix_index = msi_index;474 gic = &gc->irq_contexts[msi_index];475 476 spin_lock_irqsave(&gic->lock, flags);477 list_add_rcu(&queue->entry, &gic->eq_list);478 spin_unlock_irqrestore(&gic->lock, flags);479 480 return 0;481}482 483static void mana_gd_deregiser_irq(struct gdma_queue *queue)484{485 struct gdma_dev *gd = queue->gdma_dev;486 struct gdma_irq_context *gic;487 struct gdma_context *gc;488 unsigned int msix_index;489 unsigned long flags;490 struct gdma_queue *eq;491 492 gc = gd->gdma_context;493 494 /* At most num_online_cpus() + 1 interrupts are used. */495 msix_index = queue->eq.msix_index;496 if (WARN_ON(msix_index >= gc->num_msix_usable))497 return;498 499 gic = &gc->irq_contexts[msix_index];500 spin_lock_irqsave(&gic->lock, flags);501 list_for_each_entry_rcu(eq, &gic->eq_list, entry) {502 if (queue == eq) {503 list_del_rcu(&eq->entry);504 break;505 }506 }507 spin_unlock_irqrestore(&gic->lock, flags);508 509 queue->eq.msix_index = INVALID_PCI_MSIX_INDEX;510 synchronize_rcu();511}512 513int mana_gd_test_eq(struct gdma_context *gc, struct gdma_queue *eq)514{515 struct gdma_generate_test_event_req req = {};516 struct gdma_general_resp resp = {};517 struct device *dev = gc->dev;518 int err;519 520 mutex_lock(&gc->eq_test_event_mutex);521 522 init_completion(&gc->eq_test_event);523 gc->test_event_eq_id = INVALID_QUEUE_ID;524 525 mana_gd_init_req_hdr(&req.hdr, GDMA_GENERATE_TEST_EQE,526 sizeof(req), sizeof(resp));527 528 req.hdr.dev_id = eq->gdma_dev->dev_id;529 req.queue_index = eq->id;530 531 err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp);532 if (err) {533 dev_err(dev, "test_eq failed: %d\n", err);534 goto out;535 }536 537 err = -EPROTO;538 539 if (resp.hdr.status) {540 dev_err(dev, "test_eq failed: 0x%x\n", resp.hdr.status);541 goto out;542 }543 544 if (!wait_for_completion_timeout(&gc->eq_test_event, 30 * HZ)) {545 dev_err(dev, "test_eq timed out on queue %d\n", eq->id);546 goto out;547 }548 549 if (eq->id != gc->test_event_eq_id) {550 dev_err(dev, "test_eq got an event on wrong queue %d (%d)\n",551 gc->test_event_eq_id, eq->id);552 goto out;553 }554 555 err = 0;556out:557 mutex_unlock(&gc->eq_test_event_mutex);558 return err;559}560 561static void mana_gd_destroy_eq(struct gdma_context *gc, bool flush_evenets,562 struct gdma_queue *queue)563{564 int err;565 566 if (flush_evenets) {567 err = mana_gd_test_eq(gc, queue);568 if (err)569 dev_warn(gc->dev, "Failed to flush EQ: %d\n", err);570 }571 572 mana_gd_deregiser_irq(queue);573 574 if (queue->eq.disable_needed)575 mana_gd_disable_queue(queue);576}577 578static int mana_gd_create_eq(struct gdma_dev *gd,579 const struct gdma_queue_spec *spec,580 bool create_hwq, struct gdma_queue *queue)581{582 struct gdma_context *gc = gd->gdma_context;583 struct device *dev = gc->dev;584 u32 log2_num_entries;585 int err;586 587 queue->eq.msix_index = INVALID_PCI_MSIX_INDEX;588 queue->id = INVALID_QUEUE_ID;589 590 log2_num_entries = ilog2(queue->queue_size / GDMA_EQE_SIZE);591 592 if (spec->eq.log2_throttle_limit > log2_num_entries) {593 dev_err(dev, "EQ throttling limit (%lu) > maximum EQE (%u)\n",594 spec->eq.log2_throttle_limit, log2_num_entries);595 return -EINVAL;596 }597 598 err = mana_gd_register_irq(queue, spec);599 if (err) {600 dev_err(dev, "Failed to register irq: %d\n", err);601 return err;602 }603 604 queue->eq.callback = spec->eq.callback;605 queue->eq.context = spec->eq.context;606 queue->head |= INITIALIZED_OWNER_BIT(log2_num_entries);607 queue->eq.log2_throttle_limit = spec->eq.log2_throttle_limit ?: 1;608 609 if (create_hwq) {610 err = mana_gd_create_hw_eq(gc, queue);611 if (err)612 goto out;613 614 err = mana_gd_test_eq(gc, queue);615 if (err)616 goto out;617 }618 619 return 0;620out:621 dev_err(dev, "Failed to create EQ: %d\n", err);622 mana_gd_destroy_eq(gc, false, queue);623 return err;624}625 626static void mana_gd_create_cq(const struct gdma_queue_spec *spec,627 struct gdma_queue *queue)628{629 u32 log2_num_entries = ilog2(spec->queue_size / GDMA_CQE_SIZE);630 631 queue->head |= INITIALIZED_OWNER_BIT(log2_num_entries);632 queue->cq.parent = spec->cq.parent_eq;633 queue->cq.context = spec->cq.context;634 queue->cq.callback = spec->cq.callback;635}636 637static void mana_gd_destroy_cq(struct gdma_context *gc,638 struct gdma_queue *queue)639{640 u32 id = queue->id;641 642 if (id >= gc->max_num_cqs)643 return;644 645 if (!gc->cq_table[id])646 return;647 648 gc->cq_table[id] = NULL;649}650 651int mana_gd_create_hwc_queue(struct gdma_dev *gd,652 const struct gdma_queue_spec *spec,653 struct gdma_queue **queue_ptr)654{655 struct gdma_context *gc = gd->gdma_context;656 struct gdma_mem_info *gmi;657 struct gdma_queue *queue;658 int err;659 660 queue = kzalloc(sizeof(*queue), GFP_KERNEL);661 if (!queue)662 return -ENOMEM;663 664 gmi = &queue->mem_info;665 err = mana_gd_alloc_memory(gc, spec->queue_size, gmi);666 if (err)667 goto free_q;668 669 queue->head = 0;670 queue->tail = 0;671 queue->queue_mem_ptr = gmi->virt_addr;672 queue->queue_size = spec->queue_size;673 queue->monitor_avl_buf = spec->monitor_avl_buf;674 queue->type = spec->type;675 queue->gdma_dev = gd;676 677 if (spec->type == GDMA_EQ)678 err = mana_gd_create_eq(gd, spec, false, queue);679 else if (spec->type == GDMA_CQ)680 mana_gd_create_cq(spec, queue);681 682 if (err)683 goto out;684 685 *queue_ptr = queue;686 return 0;687out:688 mana_gd_free_memory(gmi);689free_q:690 kfree(queue);691 return err;692}693 694int mana_gd_destroy_dma_region(struct gdma_context *gc, u64 dma_region_handle)695{696 struct gdma_destroy_dma_region_req req = {};697 struct gdma_general_resp resp = {};698 int err;699 700 if (dma_region_handle == GDMA_INVALID_DMA_REGION)701 return 0;702 703 mana_gd_init_req_hdr(&req.hdr, GDMA_DESTROY_DMA_REGION, sizeof(req),704 sizeof(resp));705 req.dma_region_handle = dma_region_handle;706 707 err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp);708 if (err || resp.hdr.status) {709 dev_err(gc->dev, "Failed to destroy DMA region: %d, 0x%x\n",710 err, resp.hdr.status);711 return -EPROTO;712 }713 714 return 0;715}716EXPORT_SYMBOL_NS(mana_gd_destroy_dma_region, NET_MANA);717 718static int mana_gd_create_dma_region(struct gdma_dev *gd,719 struct gdma_mem_info *gmi)720{721 unsigned int num_page = gmi->length / MANA_PAGE_SIZE;722 struct gdma_create_dma_region_req *req = NULL;723 struct gdma_create_dma_region_resp resp = {};724 struct gdma_context *gc = gd->gdma_context;725 struct hw_channel_context *hwc;726 u32 length = gmi->length;727 size_t req_msg_size;728 int err;729 int i;730 731 if (length < MANA_PAGE_SIZE || !is_power_of_2(length))732 return -EINVAL;733 734 if (!MANA_PAGE_ALIGNED(gmi->virt_addr))735 return -EINVAL;736 737 hwc = gc->hwc.driver_data;738 req_msg_size = struct_size(req, page_addr_list, num_page);739 if (req_msg_size > hwc->max_req_msg_size)740 return -EINVAL;741 742 req = kzalloc(req_msg_size, GFP_KERNEL);743 if (!req)744 return -ENOMEM;745 746 mana_gd_init_req_hdr(&req->hdr, GDMA_CREATE_DMA_REGION,747 req_msg_size, sizeof(resp));748 req->length = length;749 req->offset_in_page = 0;750 req->gdma_page_type = GDMA_PAGE_TYPE_4K;751 req->page_count = num_page;752 req->page_addr_list_len = num_page;753 754 for (i = 0; i < num_page; i++)755 req->page_addr_list[i] = gmi->dma_handle + i * MANA_PAGE_SIZE;756 757 err = mana_gd_send_request(gc, req_msg_size, req, sizeof(resp), &resp);758 if (err)759 goto out;760 761 if (resp.hdr.status ||762 resp.dma_region_handle == GDMA_INVALID_DMA_REGION) {763 dev_err(gc->dev, "Failed to create DMA region: 0x%x\n",764 resp.hdr.status);765 err = -EPROTO;766 goto out;767 }768 769 gmi->dma_region_handle = resp.dma_region_handle;770out:771 kfree(req);772 return err;773}774 775int mana_gd_create_mana_eq(struct gdma_dev *gd,776 const struct gdma_queue_spec *spec,777 struct gdma_queue **queue_ptr)778{779 struct gdma_context *gc = gd->gdma_context;780 struct gdma_mem_info *gmi;781 struct gdma_queue *queue;782 int err;783 784 if (spec->type != GDMA_EQ)785 return -EINVAL;786 787 queue = kzalloc(sizeof(*queue), GFP_KERNEL);788 if (!queue)789 return -ENOMEM;790 791 gmi = &queue->mem_info;792 err = mana_gd_alloc_memory(gc, spec->queue_size, gmi);793 if (err)794 goto free_q;795 796 err = mana_gd_create_dma_region(gd, gmi);797 if (err)798 goto out;799 800 queue->head = 0;801 queue->tail = 0;802 queue->queue_mem_ptr = gmi->virt_addr;803 queue->queue_size = spec->queue_size;804 queue->monitor_avl_buf = spec->monitor_avl_buf;805 queue->type = spec->type;806 queue->gdma_dev = gd;807 808 err = mana_gd_create_eq(gd, spec, true, queue);809 if (err)810 goto out;811 812 *queue_ptr = queue;813 return 0;814out:815 mana_gd_free_memory(gmi);816free_q:817 kfree(queue);818 return err;819}820EXPORT_SYMBOL_NS(mana_gd_create_mana_eq, NET_MANA);821 822int mana_gd_create_mana_wq_cq(struct gdma_dev *gd,823 const struct gdma_queue_spec *spec,824 struct gdma_queue **queue_ptr)825{826 struct gdma_context *gc = gd->gdma_context;827 struct gdma_mem_info *gmi;828 struct gdma_queue *queue;829 int err;830 831 if (spec->type != GDMA_CQ && spec->type != GDMA_SQ &&832 spec->type != GDMA_RQ)833 return -EINVAL;834 835 queue = kzalloc(sizeof(*queue), GFP_KERNEL);836 if (!queue)837 return -ENOMEM;838 839 gmi = &queue->mem_info;840 err = mana_gd_alloc_memory(gc, spec->queue_size, gmi);841 if (err)842 goto free_q;843 844 err = mana_gd_create_dma_region(gd, gmi);845 if (err)846 goto out;847 848 queue->head = 0;849 queue->tail = 0;850 queue->queue_mem_ptr = gmi->virt_addr;851 queue->queue_size = spec->queue_size;852 queue->monitor_avl_buf = spec->monitor_avl_buf;853 queue->type = spec->type;854 queue->gdma_dev = gd;855 856 if (spec->type == GDMA_CQ)857 mana_gd_create_cq(spec, queue);858 859 *queue_ptr = queue;860 return 0;861out:862 mana_gd_free_memory(gmi);863free_q:864 kfree(queue);865 return err;866}867 868void mana_gd_destroy_queue(struct gdma_context *gc, struct gdma_queue *queue)869{870 struct gdma_mem_info *gmi = &queue->mem_info;871 872 switch (queue->type) {873 case GDMA_EQ:874 mana_gd_destroy_eq(gc, queue->eq.disable_needed, queue);875 break;876 877 case GDMA_CQ:878 mana_gd_destroy_cq(gc, queue);879 break;880 881 case GDMA_RQ:882 break;883 884 case GDMA_SQ:885 break;886 887 default:888 dev_err(gc->dev, "Can't destroy unknown queue: type=%d\n",889 queue->type);890 return;891 }892 893 mana_gd_destroy_dma_region(gc, gmi->dma_region_handle);894 mana_gd_free_memory(gmi);895 kfree(queue);896}897EXPORT_SYMBOL_NS(mana_gd_destroy_queue, NET_MANA);898 899int mana_gd_verify_vf_version(struct pci_dev *pdev)900{901 struct gdma_context *gc = pci_get_drvdata(pdev);902 struct gdma_verify_ver_resp resp = {};903 struct gdma_verify_ver_req req = {};904 struct hw_channel_context *hwc;905 int err;906 907 hwc = gc->hwc.driver_data;908 mana_gd_init_req_hdr(&req.hdr, GDMA_VERIFY_VF_DRIVER_VERSION,909 sizeof(req), sizeof(resp));910 911 req.protocol_ver_min = GDMA_PROTOCOL_FIRST;912 req.protocol_ver_max = GDMA_PROTOCOL_LAST;913 914 req.gd_drv_cap_flags1 = GDMA_DRV_CAP_FLAGS1;915 req.gd_drv_cap_flags2 = GDMA_DRV_CAP_FLAGS2;916 req.gd_drv_cap_flags3 = GDMA_DRV_CAP_FLAGS3;917 req.gd_drv_cap_flags4 = GDMA_DRV_CAP_FLAGS4;918 919 req.drv_ver = 0; /* Unused*/920 req.os_type = 0x10; /* Linux */921 req.os_ver_major = LINUX_VERSION_MAJOR;922 req.os_ver_minor = LINUX_VERSION_PATCHLEVEL;923 req.os_ver_build = LINUX_VERSION_SUBLEVEL;924 strscpy(req.os_ver_str1, utsname()->sysname, sizeof(req.os_ver_str1));925 strscpy(req.os_ver_str2, utsname()->release, sizeof(req.os_ver_str2));926 strscpy(req.os_ver_str3, utsname()->version, sizeof(req.os_ver_str3));927 928 err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp);929 if (err || resp.hdr.status) {930 dev_err(gc->dev, "VfVerifyVersionOutput: %d, status=0x%x\n",931 err, resp.hdr.status);932 return err ? err : -EPROTO;933 }934 if (resp.pf_cap_flags1 & GDMA_DRV_CAP_FLAG_1_HWC_TIMEOUT_RECONFIG) {935 err = mana_gd_query_hwc_timeout(pdev, &hwc->hwc_timeout);936 if (err) {937 dev_err(gc->dev, "Failed to set the hwc timeout %d\n", err);938 return err;939 }940 dev_dbg(gc->dev, "set the hwc timeout to %u\n", hwc->hwc_timeout);941 }942 return 0;943}944 945int mana_gd_register_device(struct gdma_dev *gd)946{947 struct gdma_context *gc = gd->gdma_context;948 struct gdma_register_device_resp resp = {};949 struct gdma_general_req req = {};950 int err;951 952 gd->pdid = INVALID_PDID;953 gd->doorbell = INVALID_DOORBELL;954 gd->gpa_mkey = INVALID_MEM_KEY;955 956 mana_gd_init_req_hdr(&req.hdr, GDMA_REGISTER_DEVICE, sizeof(req),957 sizeof(resp));958 959 req.hdr.dev_id = gd->dev_id;960 961 err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp);962 if (err || resp.hdr.status) {963 dev_err(gc->dev, "gdma_register_device_resp failed: %d, 0x%x\n",964 err, resp.hdr.status);965 return err ? err : -EPROTO;966 }967 968 gd->pdid = resp.pdid;969 gd->gpa_mkey = resp.gpa_mkey;970 gd->doorbell = resp.db_id;971 972 return 0;973}974EXPORT_SYMBOL_NS(mana_gd_register_device, NET_MANA);975 976int mana_gd_deregister_device(struct gdma_dev *gd)977{978 struct gdma_context *gc = gd->gdma_context;979 struct gdma_general_resp resp = {};980 struct gdma_general_req req = {};981 int err;982 983 if (gd->pdid == INVALID_PDID)984 return -EINVAL;985 986 mana_gd_init_req_hdr(&req.hdr, GDMA_DEREGISTER_DEVICE, sizeof(req),987 sizeof(resp));988 989 req.hdr.dev_id = gd->dev_id;990 991 err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp);992 if (err || resp.hdr.status) {993 dev_err(gc->dev, "Failed to deregister device: %d, 0x%x\n",994 err, resp.hdr.status);995 if (!err)996 err = -EPROTO;997 }998 999 gd->pdid = INVALID_PDID;1000 gd->doorbell = INVALID_DOORBELL;1001 gd->gpa_mkey = INVALID_MEM_KEY;1002 1003 return err;1004}1005EXPORT_SYMBOL_NS(mana_gd_deregister_device, NET_MANA);1006 1007u32 mana_gd_wq_avail_space(struct gdma_queue *wq)1008{1009 u32 used_space = (wq->head - wq->tail) * GDMA_WQE_BU_SIZE;1010 u32 wq_size = wq->queue_size;1011 1012 WARN_ON_ONCE(used_space > wq_size);1013 1014 return wq_size - used_space;1015}1016 1017u8 *mana_gd_get_wqe_ptr(const struct gdma_queue *wq, u32 wqe_offset)1018{1019 u32 offset = (wqe_offset * GDMA_WQE_BU_SIZE) & (wq->queue_size - 1);1020 1021 WARN_ON_ONCE((offset + GDMA_WQE_BU_SIZE) > wq->queue_size);1022 1023 return wq->queue_mem_ptr + offset;1024}1025 1026static u32 mana_gd_write_client_oob(const struct gdma_wqe_request *wqe_req,1027 enum gdma_queue_type q_type,1028 u32 client_oob_size, u32 sgl_data_size,1029 u8 *wqe_ptr)1030{1031 bool oob_in_sgl = !!(wqe_req->flags & GDMA_WR_OOB_IN_SGL);1032 bool pad_data = !!(wqe_req->flags & GDMA_WR_PAD_BY_SGE0);1033 struct gdma_wqe *header = (struct gdma_wqe *)wqe_ptr;1034 u8 *ptr;1035 1036 memset(header, 0, sizeof(struct gdma_wqe));1037 header->num_sge = wqe_req->num_sge;1038 header->inline_oob_size_div4 = client_oob_size / sizeof(u32);1039 1040 if (oob_in_sgl) {1041 WARN_ON_ONCE(!pad_data || wqe_req->num_sge < 2);1042 1043 header->client_oob_in_sgl = 1;1044 1045 if (pad_data)1046 header->last_vbytes = wqe_req->sgl[0].size;1047 }1048 1049 if (q_type == GDMA_SQ)1050 header->client_data_unit = wqe_req->client_data_unit;1051 1052 /* The size of gdma_wqe + client_oob_size must be less than or equal1053 * to one Basic Unit (i.e. 32 bytes), so the pointer can't go beyond1054 * the queue memory buffer boundary.1055 */1056 ptr = wqe_ptr + sizeof(header);1057 1058 if (wqe_req->inline_oob_data && wqe_req->inline_oob_size > 0) {1059 memcpy(ptr, wqe_req->inline_oob_data, wqe_req->inline_oob_size);1060 1061 if (client_oob_size > wqe_req->inline_oob_size)1062 memset(ptr + wqe_req->inline_oob_size, 0,1063 client_oob_size - wqe_req->inline_oob_size);1064 }1065 1066 return sizeof(header) + client_oob_size;1067}1068 1069static void mana_gd_write_sgl(struct gdma_queue *wq, u8 *wqe_ptr,1070 const struct gdma_wqe_request *wqe_req)1071{1072 u32 sgl_size = sizeof(struct gdma_sge) * wqe_req->num_sge;1073 const u8 *address = (u8 *)wqe_req->sgl;1074 u8 *base_ptr, *end_ptr;1075 u32 size_to_end;1076 1077 base_ptr = wq->queue_mem_ptr;1078 end_ptr = base_ptr + wq->queue_size;1079 size_to_end = (u32)(end_ptr - wqe_ptr);1080 1081 if (size_to_end < sgl_size) {1082 memcpy(wqe_ptr, address, size_to_end);1083 1084 wqe_ptr = base_ptr;1085 address += size_to_end;1086 sgl_size -= size_to_end;1087 }1088 1089 memcpy(wqe_ptr, address, sgl_size);1090}1091 1092int mana_gd_post_work_request(struct gdma_queue *wq,1093 const struct gdma_wqe_request *wqe_req,1094 struct gdma_posted_wqe_info *wqe_info)1095{1096 u32 client_oob_size = wqe_req->inline_oob_size;1097 struct gdma_context *gc;1098 u32 sgl_data_size;1099 u32 max_wqe_size;1100 u32 wqe_size;1101 u8 *wqe_ptr;1102 1103 if (wqe_req->num_sge == 0)1104 return -EINVAL;1105 1106 if (wq->type == GDMA_RQ) {1107 if (client_oob_size != 0)1108 return -EINVAL;1109 1110 client_oob_size = INLINE_OOB_SMALL_SIZE;1111 1112 max_wqe_size = GDMA_MAX_RQE_SIZE;1113 } else {1114 if (client_oob_size != INLINE_OOB_SMALL_SIZE &&1115 client_oob_size != INLINE_OOB_LARGE_SIZE)1116 return -EINVAL;1117 1118 max_wqe_size = GDMA_MAX_SQE_SIZE;1119 }1120 1121 sgl_data_size = sizeof(struct gdma_sge) * wqe_req->num_sge;1122 wqe_size = ALIGN(sizeof(struct gdma_wqe) + client_oob_size +1123 sgl_data_size, GDMA_WQE_BU_SIZE);1124 if (wqe_size > max_wqe_size)1125 return -EINVAL;1126 1127 if (wq->monitor_avl_buf && wqe_size > mana_gd_wq_avail_space(wq)) {1128 gc = wq->gdma_dev->gdma_context;1129 dev_err(gc->dev, "unsuccessful flow control!\n");1130 return -ENOSPC;1131 }1132 1133 if (wqe_info)1134 wqe_info->wqe_size_in_bu = wqe_size / GDMA_WQE_BU_SIZE;1135 1136 wqe_ptr = mana_gd_get_wqe_ptr(wq, wq->head);1137 wqe_ptr += mana_gd_write_client_oob(wqe_req, wq->type, client_oob_size,1138 sgl_data_size, wqe_ptr);1139 if (wqe_ptr >= (u8 *)wq->queue_mem_ptr + wq->queue_size)1140 wqe_ptr -= wq->queue_size;1141 1142 mana_gd_write_sgl(wq, wqe_ptr, wqe_req);1143 1144 wq->head += wqe_size / GDMA_WQE_BU_SIZE;1145 1146 return 0;1147}1148 1149int mana_gd_post_and_ring(struct gdma_queue *queue,1150 const struct gdma_wqe_request *wqe_req,1151 struct gdma_posted_wqe_info *wqe_info)1152{1153 struct gdma_context *gc = queue->gdma_dev->gdma_context;1154 int err;1155 1156 err = mana_gd_post_work_request(queue, wqe_req, wqe_info);1157 if (err)1158 return err;1159 1160 mana_gd_wq_ring_doorbell(gc, queue);1161 1162 return 0;1163}1164 1165static int mana_gd_read_cqe(struct gdma_queue *cq, struct gdma_comp *comp)1166{1167 unsigned int num_cqe = cq->queue_size / sizeof(struct gdma_cqe);1168 struct gdma_cqe *cq_cqe = cq->queue_mem_ptr;1169 u32 owner_bits, new_bits, old_bits;1170 struct gdma_cqe *cqe;1171 1172 cqe = &cq_cqe[cq->head % num_cqe];1173 owner_bits = cqe->cqe_info.owner_bits;1174 1175 old_bits = (cq->head / num_cqe - 1) & GDMA_CQE_OWNER_MASK;1176 /* Return 0 if no more entries. */1177 if (owner_bits == old_bits)1178 return 0;1179 1180 new_bits = (cq->head / num_cqe) & GDMA_CQE_OWNER_MASK;1181 /* Return -1 if overflow detected. */1182 if (WARN_ON_ONCE(owner_bits != new_bits))1183 return -1;1184 1185 /* Per GDMA spec, rmb is necessary after checking owner_bits, before1186 * reading completion info1187 */1188 rmb();1189 1190 comp->wq_num = cqe->cqe_info.wq_num;1191 comp->is_sq = cqe->cqe_info.is_sq;1192 memcpy(comp->cqe_data, cqe->cqe_data, GDMA_COMP_DATA_SIZE);1193 1194 return 1;1195}1196 1197int mana_gd_poll_cq(struct gdma_queue *cq, struct gdma_comp *comp, int num_cqe)1198{1199 int cqe_idx;1200 int ret;1201 1202 for (cqe_idx = 0; cqe_idx < num_cqe; cqe_idx++) {1203 ret = mana_gd_read_cqe(cq, &comp[cqe_idx]);1204 1205 if (ret < 0) {1206 cq->head -= cqe_idx;1207 return ret;1208 }1209 1210 if (ret == 0)1211 break;1212 1213 cq->head++;1214 }1215 1216 return cqe_idx;1217}1218 1219static irqreturn_t mana_gd_intr(int irq, void *arg)1220{1221 struct gdma_irq_context *gic = arg;1222 struct list_head *eq_list = &gic->eq_list;1223 struct gdma_queue *eq;1224 1225 rcu_read_lock();1226 list_for_each_entry_rcu(eq, eq_list, entry) {1227 gic->handler(eq);1228 }1229 rcu_read_unlock();1230 1231 return IRQ_HANDLED;1232}1233 1234int mana_gd_alloc_res_map(u32 res_avail, struct gdma_resource *r)1235{1236 r->map = bitmap_zalloc(res_avail, GFP_KERNEL);1237 if (!r->map)1238 return -ENOMEM;1239 1240 r->size = res_avail;1241 spin_lock_init(&r->lock);1242 1243 return 0;1244}1245 1246void mana_gd_free_res_map(struct gdma_resource *r)1247{1248 bitmap_free(r->map);1249 r->map = NULL;1250 r->size = 0;1251}1252 1253static int irq_setup(unsigned int *irqs, unsigned int len, int node)1254{1255 const struct cpumask *next, *prev = cpu_none_mask;1256 cpumask_var_t cpus __free(free_cpumask_var);1257 int cpu, weight;1258 1259 if (!alloc_cpumask_var(&cpus, GFP_KERNEL))1260 return -ENOMEM;1261 1262 rcu_read_lock();1263 for_each_numa_hop_mask(next, node) {1264 weight = cpumask_weight_andnot(next, prev);1265 while (weight > 0) {1266 cpumask_andnot(cpus, next, prev);1267 for_each_cpu(cpu, cpus) {1268 if (len-- == 0)1269 goto done;1270 irq_set_affinity_and_hint(*irqs++, topology_sibling_cpumask(cpu));1271 cpumask_andnot(cpus, cpus, topology_sibling_cpumask(cpu));1272 --weight;1273 }1274 }1275 prev = next;1276 }1277done:1278 rcu_read_unlock();1279 return 0;1280}1281 1282static int mana_gd_setup_irqs(struct pci_dev *pdev)1283{1284 struct gdma_context *gc = pci_get_drvdata(pdev);1285 unsigned int max_queues_per_port;1286 struct gdma_irq_context *gic;1287 unsigned int max_irqs, cpu;1288 int start_irq_index = 1;1289 int nvec, *irqs, irq;1290 int err, i = 0, j;1291 1292 cpus_read_lock();1293 max_queues_per_port = num_online_cpus();1294 if (max_queues_per_port > MANA_MAX_NUM_QUEUES)1295 max_queues_per_port = MANA_MAX_NUM_QUEUES;1296 1297 /* Need 1 interrupt for the Hardware communication Channel (HWC) */1298 max_irqs = max_queues_per_port + 1;1299 1300 nvec = pci_alloc_irq_vectors(pdev, 2, max_irqs, PCI_IRQ_MSIX);1301 if (nvec < 0) {1302 cpus_read_unlock();1303 return nvec;1304 }1305 if (nvec <= num_online_cpus())1306 start_irq_index = 0;1307 1308 irqs = kmalloc_array((nvec - start_irq_index), sizeof(int), GFP_KERNEL);1309 if (!irqs) {1310 err = -ENOMEM;1311 goto free_irq_vector;1312 }1313 1314 gc->irq_contexts = kcalloc(nvec, sizeof(struct gdma_irq_context),1315 GFP_KERNEL);1316 if (!gc->irq_contexts) {1317 err = -ENOMEM;1318 goto free_irq_vector;1319 }1320 1321 for (i = 0; i < nvec; i++) {1322 gic = &gc->irq_contexts[i];1323 gic->handler = mana_gd_process_eq_events;1324 INIT_LIST_HEAD(&gic->eq_list);1325 spin_lock_init(&gic->lock);1326 1327 if (!i)1328 snprintf(gic->name, MANA_IRQ_NAME_SZ, "mana_hwc@pci:%s",1329 pci_name(pdev));1330 else1331 snprintf(gic->name, MANA_IRQ_NAME_SZ, "mana_q%d@pci:%s",1332 i - 1, pci_name(pdev));1333 1334 irq = pci_irq_vector(pdev, i);1335 if (irq < 0) {1336 err = irq;1337 goto free_irq;1338 }1339 1340 if (!i) {1341 err = request_irq(irq, mana_gd_intr, 0, gic->name, gic);1342 if (err)1343 goto free_irq;1344 1345 /* If number of IRQ is one extra than number of online CPUs,1346 * then we need to assign IRQ0 (hwc irq) and IRQ1 to1347 * same CPU.1348 * Else we will use different CPUs for IRQ0 and IRQ1.1349 * Also we are using cpumask_local_spread instead of1350 * cpumask_first for the node, because the node can be1351 * mem only.1352 */1353 if (start_irq_index) {1354 cpu = cpumask_local_spread(i, gc->numa_node);1355 irq_set_affinity_and_hint(irq, cpumask_of(cpu));1356 } else {1357 irqs[start_irq_index] = irq;1358 }1359 } else {1360 irqs[i - start_irq_index] = irq;1361 err = request_irq(irqs[i - start_irq_index], mana_gd_intr, 0,1362 gic->name, gic);1363 if (err)1364 goto free_irq;1365 }1366 }1367 1368 err = irq_setup(irqs, (nvec - start_irq_index), gc->numa_node);1369 if (err)1370 goto free_irq;1371 1372 gc->max_num_msix = nvec;1373 gc->num_msix_usable = nvec;1374 cpus_read_unlock();1375 return 0;1376 1377free_irq:1378 for (j = i - 1; j >= 0; j--) {1379 irq = pci_irq_vector(pdev, j);1380 gic = &gc->irq_contexts[j];1381 1382 irq_update_affinity_hint(irq, NULL);1383 free_irq(irq, gic);1384 }1385 1386 kfree(gc->irq_contexts);1387 kfree(irqs);1388 gc->irq_contexts = NULL;1389free_irq_vector:1390 cpus_read_unlock();1391 pci_free_irq_vectors(pdev);1392 return err;1393}1394 1395static void mana_gd_remove_irqs(struct pci_dev *pdev)1396{1397 struct gdma_context *gc = pci_get_drvdata(pdev);1398 struct gdma_irq_context *gic;1399 int irq, i;1400 1401 if (gc->max_num_msix < 1)1402 return;1403 1404 for (i = 0; i < gc->max_num_msix; i++) {1405 irq = pci_irq_vector(pdev, i);1406 if (irq < 0)1407 continue;1408 1409 gic = &gc->irq_contexts[i];1410 1411 /* Need to clear the hint before free_irq */1412 irq_update_affinity_hint(irq, NULL);1413 free_irq(irq, gic);1414 }1415 1416 pci_free_irq_vectors(pdev);1417 1418 gc->max_num_msix = 0;1419 gc->num_msix_usable = 0;1420 kfree(gc->irq_contexts);1421 gc->irq_contexts = NULL;1422}1423 1424static int mana_gd_setup(struct pci_dev *pdev)1425{1426 struct gdma_context *gc = pci_get_drvdata(pdev);1427 int err;1428 1429 mana_gd_init_registers(pdev);1430 mana_smc_init(&gc->shm_channel, gc->dev, gc->shm_base);1431 1432 err = mana_gd_setup_irqs(pdev);1433 if (err)1434 return err;1435 1436 err = mana_hwc_create_channel(gc);1437 if (err)1438 goto remove_irq;1439 1440 err = mana_gd_verify_vf_version(pdev);1441 if (err)1442 goto destroy_hwc;1443 1444 err = mana_gd_query_max_resources(pdev);1445 if (err)1446 goto destroy_hwc;1447 1448 err = mana_gd_detect_devices(pdev);1449 if (err)1450 goto destroy_hwc;1451 1452 return 0;1453 1454destroy_hwc:1455 mana_hwc_destroy_channel(gc);1456remove_irq:1457 mana_gd_remove_irqs(pdev);1458 return err;1459}1460 1461static void mana_gd_cleanup(struct pci_dev *pdev)1462{1463 struct gdma_context *gc = pci_get_drvdata(pdev);1464 1465 mana_hwc_destroy_channel(gc);1466 1467 mana_gd_remove_irqs(pdev);1468}1469 1470static bool mana_is_pf(unsigned short dev_id)1471{1472 return dev_id == MANA_PF_DEVICE_ID;1473}1474 1475static int mana_gd_probe(struct pci_dev *pdev, const struct pci_device_id *ent)1476{1477 struct gdma_context *gc;1478 void __iomem *bar0_va;1479 int bar = 0;1480 int err;1481 1482 /* Each port has 2 CQs, each CQ has at most 1 EQE at a time */1483 BUILD_BUG_ON(2 * MAX_PORTS_IN_MANA_DEV * GDMA_EQE_SIZE > EQ_SIZE);1484 1485 err = pci_enable_device(pdev);1486 if (err)1487 return -ENXIO;1488 1489 pci_set_master(pdev);1490 1491 err = pci_request_regions(pdev, "mana");1492 if (err)1493 goto disable_dev;1494 1495 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));1496 if (err)1497 goto release_region;1498 1499 dma_set_max_seg_size(&pdev->dev, UINT_MAX);1500 1501 err = -ENOMEM;1502 gc = vzalloc(sizeof(*gc));1503 if (!gc)1504 goto release_region;1505 1506 mutex_init(&gc->eq_test_event_mutex);1507 pci_set_drvdata(pdev, gc);1508 gc->bar0_pa = pci_resource_start(pdev, 0);1509 1510 bar0_va = pci_iomap(pdev, bar, 0);1511 if (!bar0_va)1512 goto free_gc;1513 1514 gc->numa_node = dev_to_node(&pdev->dev);1515 gc->is_pf = mana_is_pf(pdev->device);1516 gc->bar0_va = bar0_va;1517 gc->dev = &pdev->dev;1518 1519 err = mana_gd_setup(pdev);1520 if (err)1521 goto unmap_bar;1522 1523 err = mana_probe(&gc->mana, false);1524 if (err)1525 goto cleanup_gd;1526 1527 return 0;1528 1529cleanup_gd:1530 mana_gd_cleanup(pdev);1531unmap_bar:1532 pci_iounmap(pdev, bar0_va);1533free_gc:1534 pci_set_drvdata(pdev, NULL);1535 vfree(gc);1536release_region:1537 pci_release_regions(pdev);1538disable_dev:1539 pci_disable_device(pdev);1540 dev_err(&pdev->dev, "gdma probe failed: err = %d\n", err);1541 return err;1542}1543 1544static void mana_gd_remove(struct pci_dev *pdev)1545{1546 struct gdma_context *gc = pci_get_drvdata(pdev);1547 1548 mana_remove(&gc->mana, false);1549 1550 mana_gd_cleanup(pdev);1551 1552 pci_iounmap(pdev, gc->bar0_va);1553 1554 vfree(gc);1555 1556 pci_release_regions(pdev);1557 pci_disable_device(pdev);1558}1559 1560/* The 'state' parameter is not used. */1561static int mana_gd_suspend(struct pci_dev *pdev, pm_message_t state)1562{1563 struct gdma_context *gc = pci_get_drvdata(pdev);1564 1565 mana_remove(&gc->mana, true);1566 1567 mana_gd_cleanup(pdev);1568 1569 return 0;1570}1571 1572/* In case the NIC hardware stops working, the suspend and resume callbacks will1573 * fail -- if this happens, it's safer to just report an error than try to undo1574 * what has been done.1575 */1576static int mana_gd_resume(struct pci_dev *pdev)1577{1578 struct gdma_context *gc = pci_get_drvdata(pdev);1579 int err;1580 1581 err = mana_gd_setup(pdev);1582 if (err)1583 return err;1584 1585 err = mana_probe(&gc->mana, true);1586 if (err)1587 return err;1588 1589 return 0;1590}1591 1592/* Quiesce the device for kexec. This is also called upon reboot/shutdown. */1593static void mana_gd_shutdown(struct pci_dev *pdev)1594{1595 struct gdma_context *gc = pci_get_drvdata(pdev);1596 1597 dev_info(&pdev->dev, "Shutdown was called\n");1598 1599 mana_remove(&gc->mana, true);1600 1601 mana_gd_cleanup(pdev);1602 1603 pci_disable_device(pdev);1604}1605 1606static const struct pci_device_id mana_id_table[] = {1607 { PCI_DEVICE(PCI_VENDOR_ID_MICROSOFT, MANA_PF_DEVICE_ID) },1608 { PCI_DEVICE(PCI_VENDOR_ID_MICROSOFT, MANA_VF_DEVICE_ID) },1609 { }1610};1611 1612static struct pci_driver mana_driver = {1613 .name = "mana",1614 .id_table = mana_id_table,1615 .probe = mana_gd_probe,1616 .remove = mana_gd_remove,1617 .suspend = mana_gd_suspend,1618 .resume = mana_gd_resume,1619 .shutdown = mana_gd_shutdown,1620};1621 1622module_pci_driver(mana_driver);1623 1624MODULE_DEVICE_TABLE(pci, mana_id_table);1625 1626MODULE_LICENSE("Dual BSD/GPL");1627MODULE_DESCRIPTION("Microsoft Azure Network Adapter driver");1628