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1// SPDX-License-Identifier: (GPL-2.0 OR MIT)2/* Microsemi Ocelot Switch driver3 * Copyright (c) 2019 Microsemi Corporation4 */5 6#include <linux/iopoll.h>7#include <linux/proc_fs.h>8 9#include <soc/mscc/ocelot_vcap.h>10#include "ocelot_police.h"11#include "ocelot_vcap.h"12 13#define ENTRY_WIDTH 3214 15enum vcap_sel {16 VCAP_SEL_ENTRY = 0x1,17 VCAP_SEL_ACTION = 0x2,18 VCAP_SEL_COUNTER = 0x4,19 VCAP_SEL_ALL = 0x7,20};21 22enum vcap_cmd {23 VCAP_CMD_WRITE = 0, /* Copy from Cache to TCAM */24 VCAP_CMD_READ = 1, /* Copy from TCAM to Cache */25 VCAP_CMD_MOVE_UP = 2, /* Move <count> up */26 VCAP_CMD_MOVE_DOWN = 3, /* Move <count> down */27 VCAP_CMD_INITIALIZE = 4, /* Write all (from cache) */28};29 30#define VCAP_ENTRY_WIDTH 12 /* Max entry width (32bit words) */31#define VCAP_COUNTER_WIDTH 4 /* Max counter width (32bit words) */32 33struct vcap_data {34 u32 entry[VCAP_ENTRY_WIDTH]; /* ENTRY_DAT */35 u32 mask[VCAP_ENTRY_WIDTH]; /* MASK_DAT */36 u32 action[VCAP_ENTRY_WIDTH]; /* ACTION_DAT */37 u32 counter[VCAP_COUNTER_WIDTH]; /* CNT_DAT */38 u32 tg; /* TG_DAT */39 u32 type; /* Action type */40 u32 tg_sw; /* Current type-group */41 u32 cnt; /* Current counter */42 u32 key_offset; /* Current entry offset */43 u32 action_offset; /* Current action offset */44 u32 counter_offset; /* Current counter offset */45 u32 tg_value; /* Current type-group value */46 u32 tg_mask; /* Current type-group mask */47};48 49static u32 vcap_read_update_ctrl(struct ocelot *ocelot,50 const struct vcap_props *vcap)51{52 return ocelot_target_read(ocelot, vcap->target, VCAP_CORE_UPDATE_CTRL);53}54 55static void vcap_cmd(struct ocelot *ocelot, const struct vcap_props *vcap,56 u16 ix, int cmd, int sel)57{58 u32 value = (VCAP_CORE_UPDATE_CTRL_UPDATE_CMD(cmd) |59 VCAP_CORE_UPDATE_CTRL_UPDATE_ADDR(ix) |60 VCAP_CORE_UPDATE_CTRL_UPDATE_SHOT);61 62 if ((sel & VCAP_SEL_ENTRY) && ix >= vcap->entry_count)63 return;64 65 if (!(sel & VCAP_SEL_ENTRY))66 value |= VCAP_CORE_UPDATE_CTRL_UPDATE_ENTRY_DIS;67 68 if (!(sel & VCAP_SEL_ACTION))69 value |= VCAP_CORE_UPDATE_CTRL_UPDATE_ACTION_DIS;70 71 if (!(sel & VCAP_SEL_COUNTER))72 value |= VCAP_CORE_UPDATE_CTRL_UPDATE_CNT_DIS;73 74 ocelot_target_write(ocelot, vcap->target, value, VCAP_CORE_UPDATE_CTRL);75 76 read_poll_timeout(vcap_read_update_ctrl, value,77 (value & VCAP_CORE_UPDATE_CTRL_UPDATE_SHOT) == 0,78 10, 100000, false, ocelot, vcap);79}80 81/* Convert from 0-based row to VCAP entry row and run command */82static void vcap_row_cmd(struct ocelot *ocelot, const struct vcap_props *vcap,83 u32 row, int cmd, int sel)84{85 vcap_cmd(ocelot, vcap, vcap->entry_count - row - 1, cmd, sel);86}87 88static void vcap_entry2cache(struct ocelot *ocelot,89 const struct vcap_props *vcap,90 struct vcap_data *data)91{92 u32 entry_words, i;93 94 entry_words = DIV_ROUND_UP(vcap->entry_width, ENTRY_WIDTH);95 96 for (i = 0; i < entry_words; i++) {97 ocelot_target_write_rix(ocelot, vcap->target, data->entry[i],98 VCAP_CACHE_ENTRY_DAT, i);99 ocelot_target_write_rix(ocelot, vcap->target, ~data->mask[i],100 VCAP_CACHE_MASK_DAT, i);101 }102 ocelot_target_write(ocelot, vcap->target, data->tg, VCAP_CACHE_TG_DAT);103}104 105static void vcap_cache2entry(struct ocelot *ocelot,106 const struct vcap_props *vcap,107 struct vcap_data *data)108{109 u32 entry_words, i;110 111 entry_words = DIV_ROUND_UP(vcap->entry_width, ENTRY_WIDTH);112 113 for (i = 0; i < entry_words; i++) {114 data->entry[i] = ocelot_target_read_rix(ocelot, vcap->target,115 VCAP_CACHE_ENTRY_DAT, i);116 // Invert mask117 data->mask[i] = ~ocelot_target_read_rix(ocelot, vcap->target,118 VCAP_CACHE_MASK_DAT, i);119 }120 data->tg = ocelot_target_read(ocelot, vcap->target, VCAP_CACHE_TG_DAT);121}122 123static void vcap_action2cache(struct ocelot *ocelot,124 const struct vcap_props *vcap,125 struct vcap_data *data)126{127 u32 action_words, mask;128 int i, width;129 130 /* Encode action type */131 width = vcap->action_type_width;132 if (width) {133 mask = GENMASK(width, 0);134 data->action[0] = ((data->action[0] & ~mask) | data->type);135 }136 137 action_words = DIV_ROUND_UP(vcap->action_width, ENTRY_WIDTH);138 139 for (i = 0; i < action_words; i++)140 ocelot_target_write_rix(ocelot, vcap->target, data->action[i],141 VCAP_CACHE_ACTION_DAT, i);142 143 for (i = 0; i < vcap->counter_words; i++)144 ocelot_target_write_rix(ocelot, vcap->target, data->counter[i],145 VCAP_CACHE_CNT_DAT, i);146}147 148static void vcap_cache2action(struct ocelot *ocelot,149 const struct vcap_props *vcap,150 struct vcap_data *data)151{152 u32 action_words;153 int i, width;154 155 action_words = DIV_ROUND_UP(vcap->action_width, ENTRY_WIDTH);156 157 for (i = 0; i < action_words; i++)158 data->action[i] = ocelot_target_read_rix(ocelot, vcap->target,159 VCAP_CACHE_ACTION_DAT,160 i);161 162 for (i = 0; i < vcap->counter_words; i++)163 data->counter[i] = ocelot_target_read_rix(ocelot, vcap->target,164 VCAP_CACHE_CNT_DAT,165 i);166 167 /* Extract action type */168 width = vcap->action_type_width;169 data->type = (width ? (data->action[0] & GENMASK(width, 0)) : 0);170}171 172/* Calculate offsets for entry */173static void vcap_data_offset_get(const struct vcap_props *vcap,174 struct vcap_data *data, int ix)175{176 int num_subwords_per_entry, num_subwords_per_action;177 int i, col, offset, num_entries_per_row, base;178 u32 width = vcap->tg_width;179 180 switch (data->tg_sw) {181 case VCAP_TG_FULL:182 num_entries_per_row = 1;183 break;184 case VCAP_TG_HALF:185 num_entries_per_row = 2;186 break;187 case VCAP_TG_QUARTER:188 num_entries_per_row = 4;189 break;190 default:191 return;192 }193 194 col = (ix % num_entries_per_row);195 num_subwords_per_entry = (vcap->sw_count / num_entries_per_row);196 base = (vcap->sw_count - col * num_subwords_per_entry -197 num_subwords_per_entry);198 data->tg_value = 0;199 data->tg_mask = 0;200 for (i = 0; i < num_subwords_per_entry; i++) {201 offset = ((base + i) * width);202 data->tg_value |= (data->tg_sw << offset);203 data->tg_mask |= GENMASK(offset + width - 1, offset);204 }205 206 /* Calculate key/action/counter offsets */207 col = (num_entries_per_row - col - 1);208 data->key_offset = (base * vcap->entry_width) / vcap->sw_count;209 data->counter_offset = (num_subwords_per_entry * col *210 vcap->counter_width);211 i = data->type;212 width = vcap->action_table[i].width;213 num_subwords_per_action = vcap->action_table[i].count;214 data->action_offset = ((num_subwords_per_action * col * width) /215 num_entries_per_row);216 data->action_offset += vcap->action_type_width;217}218 219static void vcap_data_set(u32 *data, u32 offset, u32 len, u32 value)220{221 u32 i, v, m;222 223 for (i = 0; i < len; i++, offset++) {224 v = data[offset / ENTRY_WIDTH];225 m = (1 << (offset % ENTRY_WIDTH));226 if (value & (1 << i))227 v |= m;228 else229 v &= ~m;230 data[offset / ENTRY_WIDTH] = v;231 }232}233 234static u32 vcap_data_get(u32 *data, u32 offset, u32 len)235{236 u32 i, v, m, value = 0;237 238 for (i = 0; i < len; i++, offset++) {239 v = data[offset / ENTRY_WIDTH];240 m = (1 << (offset % ENTRY_WIDTH));241 if (v & m)242 value |= (1 << i);243 }244 return value;245}246 247static void vcap_key_field_set(struct vcap_data *data, u32 offset, u32 width,248 u32 value, u32 mask)249{250 vcap_data_set(data->entry, offset + data->key_offset, width, value);251 vcap_data_set(data->mask, offset + data->key_offset, width, mask);252}253 254static void vcap_key_set(const struct vcap_props *vcap, struct vcap_data *data,255 int field, u32 value, u32 mask)256{257 u32 offset = vcap->keys[field].offset;258 u32 length = vcap->keys[field].length;259 260 vcap_key_field_set(data, offset, length, value, mask);261}262 263static void vcap_key_bytes_set(const struct vcap_props *vcap,264 struct vcap_data *data, int field,265 u8 *val, u8 *msk)266{267 u32 offset = vcap->keys[field].offset;268 u32 count = vcap->keys[field].length;269 u32 i, j, n = 0, value = 0, mask = 0;270 271 WARN_ON(count % 8);272 273 /* Data wider than 32 bits are split up in chunks of maximum 32 bits.274 * The 32 LSB of the data are written to the 32 MSB of the TCAM.275 */276 offset += count;277 count /= 8;278 279 for (i = 0; i < count; i++) {280 j = (count - i - 1);281 value += (val[j] << n);282 mask += (msk[j] << n);283 n += 8;284 if (n == ENTRY_WIDTH || (i + 1) == count) {285 offset -= n;286 vcap_key_field_set(data, offset, n, value, mask);287 n = 0;288 value = 0;289 mask = 0;290 }291 }292}293 294static void vcap_key_l4_port_set(const struct vcap_props *vcap,295 struct vcap_data *data, int field,296 struct ocelot_vcap_udp_tcp *port)297{298 u32 offset = vcap->keys[field].offset;299 u32 length = vcap->keys[field].length;300 301 WARN_ON(length != 16);302 303 vcap_key_field_set(data, offset, length, port->value, port->mask);304}305 306static void vcap_key_bit_set(const struct vcap_props *vcap,307 struct vcap_data *data, int field,308 enum ocelot_vcap_bit val)309{310 u32 value = (val == OCELOT_VCAP_BIT_1 ? 1 : 0);311 u32 msk = (val == OCELOT_VCAP_BIT_ANY ? 0 : 1);312 u32 offset = vcap->keys[field].offset;313 u32 length = vcap->keys[field].length;314 315 WARN_ON(length != 1);316 317 vcap_key_field_set(data, offset, length, value, msk);318}319 320static void vcap_action_set(const struct vcap_props *vcap,321 struct vcap_data *data, int field, u32 value)322{323 int offset = vcap->actions[field].offset;324 int length = vcap->actions[field].length;325 326 vcap_data_set(data->action, offset + data->action_offset, length,327 value);328}329 330static void is2_action_set(struct ocelot *ocelot, struct vcap_data *data,331 struct ocelot_vcap_filter *filter)332{333 const struct vcap_props *vcap = &ocelot->vcap[VCAP_IS2];334 struct ocelot_vcap_action *a = &filter->action;335 336 vcap_action_set(vcap, data, VCAP_IS2_ACT_MASK_MODE, a->mask_mode);337 vcap_action_set(vcap, data, VCAP_IS2_ACT_PORT_MASK, a->port_mask);338 vcap_action_set(vcap, data, VCAP_IS2_ACT_MIRROR_ENA, a->mirror_ena);339 vcap_action_set(vcap, data, VCAP_IS2_ACT_POLICE_ENA, a->police_ena);340 vcap_action_set(vcap, data, VCAP_IS2_ACT_POLICE_IDX, a->pol_ix);341 vcap_action_set(vcap, data, VCAP_IS2_ACT_CPU_QU_NUM, a->cpu_qu_num);342 vcap_action_set(vcap, data, VCAP_IS2_ACT_CPU_COPY_ENA, a->cpu_copy_ena);343}344 345static void is2_entry_set(struct ocelot *ocelot, int ix,346 struct ocelot_vcap_filter *filter)347{348 const struct vcap_props *vcap = &ocelot->vcap[VCAP_IS2];349 struct ocelot_vcap_key_vlan *tag = &filter->vlan;350 u32 val, msk, type, type_mask = 0xf, i, count;351 struct ocelot_vcap_u64 payload;352 struct vcap_data data;353 int row = (ix / 2);354 355 memset(&payload, 0, sizeof(payload));356 memset(&data, 0, sizeof(data));357 358 /* Read row */359 vcap_row_cmd(ocelot, vcap, row, VCAP_CMD_READ, VCAP_SEL_ALL);360 vcap_cache2entry(ocelot, vcap, &data);361 vcap_cache2action(ocelot, vcap, &data);362 363 data.tg_sw = VCAP_TG_HALF;364 vcap_data_offset_get(vcap, &data, ix);365 data.tg = (data.tg & ~data.tg_mask);366 if (filter->prio != 0)367 data.tg |= data.tg_value;368 369 data.type = IS2_ACTION_TYPE_NORMAL;370 371 vcap_key_set(vcap, &data, VCAP_IS2_HK_PAG, filter->pag, 0xff);372 vcap_key_bit_set(vcap, &data, VCAP_IS2_HK_FIRST,373 (filter->lookup == 0) ? OCELOT_VCAP_BIT_1 :374 OCELOT_VCAP_BIT_0);375 vcap_key_set(vcap, &data, VCAP_IS2_HK_IGR_PORT_MASK, 0,376 ~filter->ingress_port_mask);377 vcap_key_bit_set(vcap, &data, VCAP_IS2_HK_HOST_MATCH,378 OCELOT_VCAP_BIT_ANY);379 vcap_key_bit_set(vcap, &data, VCAP_IS2_HK_L2_MC, filter->dmac_mc);380 vcap_key_bit_set(vcap, &data, VCAP_IS2_HK_L2_BC, filter->dmac_bc);381 vcap_key_bit_set(vcap, &data, VCAP_IS2_HK_VLAN_TAGGED, tag->tagged);382 vcap_key_set(vcap, &data, VCAP_IS2_HK_VID,383 tag->vid.value, tag->vid.mask);384 vcap_key_set(vcap, &data, VCAP_IS2_HK_PCP,385 tag->pcp.value[0], tag->pcp.mask[0]);386 vcap_key_bit_set(vcap, &data, VCAP_IS2_HK_DEI, tag->dei);387 388 switch (filter->key_type) {389 case OCELOT_VCAP_KEY_ETYPE: {390 struct ocelot_vcap_key_etype *etype = &filter->key.etype;391 392 type = IS2_TYPE_ETYPE;393 vcap_key_bytes_set(vcap, &data, VCAP_IS2_HK_L2_DMAC,394 etype->dmac.value, etype->dmac.mask);395 vcap_key_bytes_set(vcap, &data, VCAP_IS2_HK_L2_SMAC,396 etype->smac.value, etype->smac.mask);397 vcap_key_bytes_set(vcap, &data, VCAP_IS2_HK_MAC_ETYPE_ETYPE,398 etype->etype.value, etype->etype.mask);399 /* Clear unused bits */400 vcap_key_set(vcap, &data, VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD0,401 0, 0);402 vcap_key_set(vcap, &data, VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD1,403 0, 0);404 vcap_key_set(vcap, &data, VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD2,405 0, 0);406 vcap_key_bytes_set(vcap, &data,407 VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD0,408 etype->data.value, etype->data.mask);409 break;410 }411 case OCELOT_VCAP_KEY_LLC: {412 struct ocelot_vcap_key_llc *llc = &filter->key.llc;413 414 type = IS2_TYPE_LLC;415 vcap_key_bytes_set(vcap, &data, VCAP_IS2_HK_L2_DMAC,416 llc->dmac.value, llc->dmac.mask);417 vcap_key_bytes_set(vcap, &data, VCAP_IS2_HK_L2_SMAC,418 llc->smac.value, llc->smac.mask);419 for (i = 0; i < 4; i++) {420 payload.value[i] = llc->llc.value[i];421 payload.mask[i] = llc->llc.mask[i];422 }423 vcap_key_bytes_set(vcap, &data, VCAP_IS2_HK_MAC_LLC_L2_LLC,424 payload.value, payload.mask);425 break;426 }427 case OCELOT_VCAP_KEY_SNAP: {428 struct ocelot_vcap_key_snap *snap = &filter->key.snap;429 430 type = IS2_TYPE_SNAP;431 vcap_key_bytes_set(vcap, &data, VCAP_IS2_HK_L2_DMAC,432 snap->dmac.value, snap->dmac.mask);433 vcap_key_bytes_set(vcap, &data, VCAP_IS2_HK_L2_SMAC,434 snap->smac.value, snap->smac.mask);435 vcap_key_bytes_set(vcap, &data, VCAP_IS2_HK_MAC_SNAP_L2_SNAP,436 filter->key.snap.snap.value,437 filter->key.snap.snap.mask);438 break;439 }440 case OCELOT_VCAP_KEY_ARP: {441 struct ocelot_vcap_key_arp *arp = &filter->key.arp;442 443 type = IS2_TYPE_ARP;444 vcap_key_bytes_set(vcap, &data, VCAP_IS2_HK_MAC_ARP_SMAC,445 arp->smac.value, arp->smac.mask);446 vcap_key_bit_set(vcap, &data,447 VCAP_IS2_HK_MAC_ARP_ADDR_SPACE_OK,448 arp->ethernet);449 vcap_key_bit_set(vcap, &data,450 VCAP_IS2_HK_MAC_ARP_PROTO_SPACE_OK,451 arp->ip);452 vcap_key_bit_set(vcap, &data,453 VCAP_IS2_HK_MAC_ARP_LEN_OK,454 arp->length);455 vcap_key_bit_set(vcap, &data,456 VCAP_IS2_HK_MAC_ARP_TARGET_MATCH,457 arp->dmac_match);458 vcap_key_bit_set(vcap, &data,459 VCAP_IS2_HK_MAC_ARP_SENDER_MATCH,460 arp->smac_match);461 vcap_key_bit_set(vcap, &data,462 VCAP_IS2_HK_MAC_ARP_OPCODE_UNKNOWN,463 arp->unknown);464 465 /* OPCODE is inverse, bit 0 is reply flag, bit 1 is RARP flag */466 val = ((arp->req == OCELOT_VCAP_BIT_0 ? 1 : 0) |467 (arp->arp == OCELOT_VCAP_BIT_0 ? 2 : 0));468 msk = ((arp->req == OCELOT_VCAP_BIT_ANY ? 0 : 1) |469 (arp->arp == OCELOT_VCAP_BIT_ANY ? 0 : 2));470 vcap_key_set(vcap, &data, VCAP_IS2_HK_MAC_ARP_OPCODE,471 val, msk);472 vcap_key_bytes_set(vcap, &data,473 VCAP_IS2_HK_MAC_ARP_L3_IP4_DIP,474 arp->dip.value.addr, arp->dip.mask.addr);475 vcap_key_bytes_set(vcap, &data,476 VCAP_IS2_HK_MAC_ARP_L3_IP4_SIP,477 arp->sip.value.addr, arp->sip.mask.addr);478 vcap_key_set(vcap, &data, VCAP_IS2_HK_MAC_ARP_DIP_EQ_SIP,479 0, 0);480 break;481 }482 case OCELOT_VCAP_KEY_IPV4:483 case OCELOT_VCAP_KEY_IPV6: {484 enum ocelot_vcap_bit sip_eq_dip, sport_eq_dport, seq_zero, tcp;485 enum ocelot_vcap_bit ttl, fragment, options, tcp_ack, tcp_urg;486 enum ocelot_vcap_bit tcp_fin, tcp_syn, tcp_rst, tcp_psh;487 struct ocelot_vcap_key_ipv4 *ipv4 = NULL;488 struct ocelot_vcap_key_ipv6 *ipv6 = NULL;489 struct ocelot_vcap_udp_tcp *sport, *dport;490 struct ocelot_vcap_ipv4 sip, dip;491 struct ocelot_vcap_u8 proto, ds;492 struct ocelot_vcap_u48 *ip_data;493 494 if (filter->key_type == OCELOT_VCAP_KEY_IPV4) {495 ipv4 = &filter->key.ipv4;496 ttl = ipv4->ttl;497 fragment = ipv4->fragment;498 options = ipv4->options;499 proto = ipv4->proto;500 ds = ipv4->ds;501 ip_data = &ipv4->data;502 sip = ipv4->sip;503 dip = ipv4->dip;504 sport = &ipv4->sport;505 dport = &ipv4->dport;506 tcp_fin = ipv4->tcp_fin;507 tcp_syn = ipv4->tcp_syn;508 tcp_rst = ipv4->tcp_rst;509 tcp_psh = ipv4->tcp_psh;510 tcp_ack = ipv4->tcp_ack;511 tcp_urg = ipv4->tcp_urg;512 sip_eq_dip = ipv4->sip_eq_dip;513 sport_eq_dport = ipv4->sport_eq_dport;514 seq_zero = ipv4->seq_zero;515 } else {516 ipv6 = &filter->key.ipv6;517 ttl = ipv6->ttl;518 fragment = OCELOT_VCAP_BIT_ANY;519 options = OCELOT_VCAP_BIT_ANY;520 proto = ipv6->proto;521 ds = ipv6->ds;522 ip_data = &ipv6->data;523 for (i = 0; i < 8; i++) {524 val = ipv6->sip.value[i + 8];525 msk = ipv6->sip.mask[i + 8];526 if (i < 4) {527 dip.value.addr[i] = val;528 dip.mask.addr[i] = msk;529 } else {530 sip.value.addr[i - 4] = val;531 sip.mask.addr[i - 4] = msk;532 }533 }534 sport = &ipv6->sport;535 dport = &ipv6->dport;536 tcp_fin = ipv6->tcp_fin;537 tcp_syn = ipv6->tcp_syn;538 tcp_rst = ipv6->tcp_rst;539 tcp_psh = ipv6->tcp_psh;540 tcp_ack = ipv6->tcp_ack;541 tcp_urg = ipv6->tcp_urg;542 sip_eq_dip = ipv6->sip_eq_dip;543 sport_eq_dport = ipv6->sport_eq_dport;544 seq_zero = ipv6->seq_zero;545 }546 547 vcap_key_bit_set(vcap, &data, VCAP_IS2_HK_IP4,548 ipv4 ? OCELOT_VCAP_BIT_1 : OCELOT_VCAP_BIT_0);549 vcap_key_bit_set(vcap, &data, VCAP_IS2_HK_L3_FRAGMENT,550 fragment);551 vcap_key_set(vcap, &data, VCAP_IS2_HK_L3_FRAG_OFS_GT0, 0, 0);552 vcap_key_bit_set(vcap, &data, VCAP_IS2_HK_L3_OPTIONS,553 options);554 vcap_key_bit_set(vcap, &data, VCAP_IS2_HK_IP4_L3_TTL_GT0,555 ttl);556 vcap_key_bytes_set(vcap, &data, VCAP_IS2_HK_L3_TOS,557 ds.value, ds.mask);558 vcap_key_bytes_set(vcap, &data, VCAP_IS2_HK_L3_IP4_DIP,559 dip.value.addr, dip.mask.addr);560 vcap_key_bytes_set(vcap, &data, VCAP_IS2_HK_L3_IP4_SIP,561 sip.value.addr, sip.mask.addr);562 vcap_key_bit_set(vcap, &data, VCAP_IS2_HK_DIP_EQ_SIP,563 sip_eq_dip);564 val = proto.value[0];565 msk = proto.mask[0];566 type = IS2_TYPE_IP_UDP_TCP;567 if (msk == 0xff && (val == IPPROTO_TCP || val == IPPROTO_UDP)) {568 /* UDP/TCP protocol match */569 tcp = (val == IPPROTO_TCP ?570 OCELOT_VCAP_BIT_1 : OCELOT_VCAP_BIT_0);571 vcap_key_bit_set(vcap, &data, VCAP_IS2_HK_TCP, tcp);572 vcap_key_l4_port_set(vcap, &data,573 VCAP_IS2_HK_L4_DPORT, dport);574 vcap_key_l4_port_set(vcap, &data,575 VCAP_IS2_HK_L4_SPORT, sport);576 vcap_key_set(vcap, &data, VCAP_IS2_HK_L4_RNG, 0, 0);577 vcap_key_bit_set(vcap, &data,578 VCAP_IS2_HK_L4_SPORT_EQ_DPORT,579 sport_eq_dport);580 vcap_key_bit_set(vcap, &data,581 VCAP_IS2_HK_L4_SEQUENCE_EQ0,582 seq_zero);583 vcap_key_bit_set(vcap, &data, VCAP_IS2_HK_L4_FIN,584 tcp_fin);585 vcap_key_bit_set(vcap, &data, VCAP_IS2_HK_L4_SYN,586 tcp_syn);587 vcap_key_bit_set(vcap, &data, VCAP_IS2_HK_L4_RST,588 tcp_rst);589 vcap_key_bit_set(vcap, &data, VCAP_IS2_HK_L4_PSH,590 tcp_psh);591 vcap_key_bit_set(vcap, &data, VCAP_IS2_HK_L4_ACK,592 tcp_ack);593 vcap_key_bit_set(vcap, &data, VCAP_IS2_HK_L4_URG,594 tcp_urg);595 vcap_key_set(vcap, &data, VCAP_IS2_HK_L4_1588_DOM,596 0, 0);597 vcap_key_set(vcap, &data, VCAP_IS2_HK_L4_1588_VER,598 0, 0);599 } else {600 if (msk == 0) {601 /* Any IP protocol match */602 type_mask = IS2_TYPE_MASK_IP_ANY;603 } else {604 /* Non-UDP/TCP protocol match */605 type = IS2_TYPE_IP_OTHER;606 for (i = 0; i < 6; i++) {607 payload.value[i] = ip_data->value[i];608 payload.mask[i] = ip_data->mask[i];609 }610 }611 vcap_key_bytes_set(vcap, &data,612 VCAP_IS2_HK_IP4_L3_PROTO,613 proto.value, proto.mask);614 vcap_key_bytes_set(vcap, &data,615 VCAP_IS2_HK_L3_PAYLOAD,616 payload.value, payload.mask);617 }618 break;619 }620 case OCELOT_VCAP_KEY_ANY:621 default:622 type = 0;623 type_mask = 0;624 count = vcap->entry_width / 2;625 /* Iterate over the non-common part of the key and626 * clear entry data627 */628 for (i = vcap->keys[VCAP_IS2_HK_L2_DMAC].offset;629 i < count; i += ENTRY_WIDTH) {630 vcap_key_field_set(&data, i, min(32u, count - i), 0, 0);631 }632 break;633 }634 635 vcap_key_set(vcap, &data, VCAP_IS2_TYPE, type, type_mask);636 is2_action_set(ocelot, &data, filter);637 vcap_data_set(data.counter, data.counter_offset,638 vcap->counter_width, filter->stats.pkts);639 640 /* Write row */641 vcap_entry2cache(ocelot, vcap, &data);642 vcap_action2cache(ocelot, vcap, &data);643 vcap_row_cmd(ocelot, vcap, row, VCAP_CMD_WRITE, VCAP_SEL_ALL);644}645 646static void is1_action_set(struct ocelot *ocelot, struct vcap_data *data,647 const struct ocelot_vcap_filter *filter)648{649 const struct vcap_props *vcap = &ocelot->vcap[VCAP_IS1];650 const struct ocelot_vcap_action *a = &filter->action;651 652 vcap_action_set(vcap, data, VCAP_IS1_ACT_VID_REPLACE_ENA,653 a->vid_replace_ena);654 vcap_action_set(vcap, data, VCAP_IS1_ACT_VID_ADD_VAL, a->vid);655 vcap_action_set(vcap, data, VCAP_IS1_ACT_VLAN_POP_CNT_ENA,656 a->vlan_pop_cnt_ena);657 vcap_action_set(vcap, data, VCAP_IS1_ACT_VLAN_POP_CNT,658 a->vlan_pop_cnt);659 vcap_action_set(vcap, data, VCAP_IS1_ACT_PCP_DEI_ENA, a->pcp_dei_ena);660 vcap_action_set(vcap, data, VCAP_IS1_ACT_PCP_VAL, a->pcp);661 vcap_action_set(vcap, data, VCAP_IS1_ACT_DEI_VAL, a->dei);662 vcap_action_set(vcap, data, VCAP_IS1_ACT_QOS_ENA, a->qos_ena);663 vcap_action_set(vcap, data, VCAP_IS1_ACT_QOS_VAL, a->qos_val);664 vcap_action_set(vcap, data, VCAP_IS1_ACT_PAG_OVERRIDE_MASK,665 a->pag_override_mask);666 vcap_action_set(vcap, data, VCAP_IS1_ACT_PAG_VAL, a->pag_val);667}668 669static void is1_entry_set(struct ocelot *ocelot, int ix,670 struct ocelot_vcap_filter *filter)671{672 const struct vcap_props *vcap = &ocelot->vcap[VCAP_IS1];673 struct ocelot_vcap_key_vlan *tag = &filter->vlan;674 struct vcap_data data;675 int row = ix / 2;676 u32 type;677 678 memset(&data, 0, sizeof(data));679 680 /* Read row */681 vcap_row_cmd(ocelot, vcap, row, VCAP_CMD_READ, VCAP_SEL_ALL);682 vcap_cache2entry(ocelot, vcap, &data);683 vcap_cache2action(ocelot, vcap, &data);684 685 data.tg_sw = VCAP_TG_HALF;686 data.type = IS1_ACTION_TYPE_NORMAL;687 vcap_data_offset_get(vcap, &data, ix);688 data.tg = (data.tg & ~data.tg_mask);689 if (filter->prio != 0)690 data.tg |= data.tg_value;691 692 vcap_key_set(vcap, &data, VCAP_IS1_HK_LOOKUP, filter->lookup, 0x3);693 vcap_key_set(vcap, &data, VCAP_IS1_HK_IGR_PORT_MASK, 0,694 ~filter->ingress_port_mask);695 vcap_key_bit_set(vcap, &data, VCAP_IS1_HK_L2_MC, filter->dmac_mc);696 vcap_key_bit_set(vcap, &data, VCAP_IS1_HK_L2_BC, filter->dmac_bc);697 vcap_key_bit_set(vcap, &data, VCAP_IS1_HK_VLAN_TAGGED, tag->tagged);698 vcap_key_bit_set(vcap, &data, VCAP_IS1_HK_TPID, tag->tpid);699 vcap_key_set(vcap, &data, VCAP_IS1_HK_VID,700 tag->vid.value, tag->vid.mask);701 vcap_key_set(vcap, &data, VCAP_IS1_HK_PCP,702 tag->pcp.value[0], tag->pcp.mask[0]);703 type = IS1_TYPE_S1_NORMAL;704 705 switch (filter->key_type) {706 case OCELOT_VCAP_KEY_ETYPE: {707 struct ocelot_vcap_key_etype *etype = &filter->key.etype;708 709 vcap_key_bytes_set(vcap, &data, VCAP_IS1_HK_L2_SMAC,710 etype->smac.value, etype->smac.mask);711 vcap_key_bytes_set(vcap, &data, VCAP_IS1_HK_ETYPE,712 etype->etype.value, etype->etype.mask);713 break;714 }715 case OCELOT_VCAP_KEY_IPV4: {716 struct ocelot_vcap_key_ipv4 *ipv4 = &filter->key.ipv4;717 struct ocelot_vcap_udp_tcp *sport = &ipv4->sport;718 struct ocelot_vcap_udp_tcp *dport = &ipv4->dport;719 enum ocelot_vcap_bit tcp_udp = OCELOT_VCAP_BIT_0;720 struct ocelot_vcap_u8 proto = ipv4->proto;721 struct ocelot_vcap_ipv4 sip = ipv4->sip;722 u32 val, msk;723 724 vcap_key_bit_set(vcap, &data, VCAP_IS1_HK_IP_SNAP,725 OCELOT_VCAP_BIT_1);726 vcap_key_bit_set(vcap, &data, VCAP_IS1_HK_IP4,727 OCELOT_VCAP_BIT_1);728 vcap_key_bit_set(vcap, &data, VCAP_IS1_HK_ETYPE_LEN,729 OCELOT_VCAP_BIT_1);730 vcap_key_bytes_set(vcap, &data, VCAP_IS1_HK_L3_IP4_SIP,731 sip.value.addr, sip.mask.addr);732 733 val = proto.value[0];734 msk = proto.mask[0];735 736 if ((val == NEXTHDR_TCP || val == NEXTHDR_UDP) && msk == 0xff)737 tcp_udp = OCELOT_VCAP_BIT_1;738 vcap_key_bit_set(vcap, &data, VCAP_IS1_HK_TCP_UDP, tcp_udp);739 740 if (tcp_udp) {741 enum ocelot_vcap_bit tcp = OCELOT_VCAP_BIT_0;742 743 if (val == NEXTHDR_TCP)744 tcp = OCELOT_VCAP_BIT_1;745 746 vcap_key_bit_set(vcap, &data, VCAP_IS1_HK_TCP, tcp);747 vcap_key_l4_port_set(vcap, &data, VCAP_IS1_HK_L4_SPORT,748 sport);749 /* Overloaded field */750 vcap_key_l4_port_set(vcap, &data, VCAP_IS1_HK_ETYPE,751 dport);752 } else {753 /* IPv4 "other" frame */754 struct ocelot_vcap_u16 etype = {0};755 756 /* Overloaded field */757 etype.value[0] = proto.value[0];758 etype.mask[0] = proto.mask[0];759 760 vcap_key_bytes_set(vcap, &data, VCAP_IS1_HK_ETYPE,761 etype.value, etype.mask);762 }763 break;764 }765 default:766 break;767 }768 vcap_key_bit_set(vcap, &data, VCAP_IS1_HK_TYPE,769 type ? OCELOT_VCAP_BIT_1 : OCELOT_VCAP_BIT_0);770 771 is1_action_set(ocelot, &data, filter);772 vcap_data_set(data.counter, data.counter_offset,773 vcap->counter_width, filter->stats.pkts);774 775 /* Write row */776 vcap_entry2cache(ocelot, vcap, &data);777 vcap_action2cache(ocelot, vcap, &data);778 vcap_row_cmd(ocelot, vcap, row, VCAP_CMD_WRITE, VCAP_SEL_ALL);779}780 781static void es0_action_set(struct ocelot *ocelot, struct vcap_data *data,782 const struct ocelot_vcap_filter *filter)783{784 const struct vcap_props *vcap = &ocelot->vcap[VCAP_ES0];785 const struct ocelot_vcap_action *a = &filter->action;786 787 vcap_action_set(vcap, data, VCAP_ES0_ACT_PUSH_OUTER_TAG,788 a->push_outer_tag);789 vcap_action_set(vcap, data, VCAP_ES0_ACT_PUSH_INNER_TAG,790 a->push_inner_tag);791 vcap_action_set(vcap, data, VCAP_ES0_ACT_TAG_A_TPID_SEL,792 a->tag_a_tpid_sel);793 vcap_action_set(vcap, data, VCAP_ES0_ACT_TAG_A_VID_SEL,794 a->tag_a_vid_sel);795 vcap_action_set(vcap, data, VCAP_ES0_ACT_TAG_A_PCP_SEL,796 a->tag_a_pcp_sel);797 vcap_action_set(vcap, data, VCAP_ES0_ACT_VID_A_VAL, a->vid_a_val);798 vcap_action_set(vcap, data, VCAP_ES0_ACT_PCP_A_VAL, a->pcp_a_val);799 vcap_action_set(vcap, data, VCAP_ES0_ACT_TAG_B_TPID_SEL,800 a->tag_b_tpid_sel);801 vcap_action_set(vcap, data, VCAP_ES0_ACT_TAG_B_VID_SEL,802 a->tag_b_vid_sel);803 vcap_action_set(vcap, data, VCAP_ES0_ACT_TAG_B_PCP_SEL,804 a->tag_b_pcp_sel);805 vcap_action_set(vcap, data, VCAP_ES0_ACT_VID_B_VAL, a->vid_b_val);806 vcap_action_set(vcap, data, VCAP_ES0_ACT_PCP_B_VAL, a->pcp_b_val);807}808 809static void es0_entry_set(struct ocelot *ocelot, int ix,810 struct ocelot_vcap_filter *filter)811{812 const struct vcap_props *vcap = &ocelot->vcap[VCAP_ES0];813 struct ocelot_vcap_key_vlan *tag = &filter->vlan;814 struct vcap_data data;815 int row = ix;816 817 memset(&data, 0, sizeof(data));818 819 /* Read row */820 vcap_row_cmd(ocelot, vcap, row, VCAP_CMD_READ, VCAP_SEL_ALL);821 vcap_cache2entry(ocelot, vcap, &data);822 vcap_cache2action(ocelot, vcap, &data);823 824 data.tg_sw = VCAP_TG_FULL;825 data.type = ES0_ACTION_TYPE_NORMAL;826 vcap_data_offset_get(vcap, &data, ix);827 data.tg = (data.tg & ~data.tg_mask);828 if (filter->prio != 0)829 data.tg |= data.tg_value;830 831 vcap_key_set(vcap, &data, VCAP_ES0_IGR_PORT, filter->ingress_port.value,832 filter->ingress_port.mask);833 vcap_key_set(vcap, &data, VCAP_ES0_EGR_PORT, filter->egress_port.value,834 filter->egress_port.mask);835 vcap_key_bit_set(vcap, &data, VCAP_ES0_L2_MC, filter->dmac_mc);836 vcap_key_bit_set(vcap, &data, VCAP_ES0_L2_BC, filter->dmac_bc);837 vcap_key_set(vcap, &data, VCAP_ES0_VID,838 tag->vid.value, tag->vid.mask);839 vcap_key_set(vcap, &data, VCAP_ES0_PCP,840 tag->pcp.value[0], tag->pcp.mask[0]);841 842 es0_action_set(ocelot, &data, filter);843 vcap_data_set(data.counter, data.counter_offset,844 vcap->counter_width, filter->stats.pkts);845 846 /* Write row */847 vcap_entry2cache(ocelot, vcap, &data);848 vcap_action2cache(ocelot, vcap, &data);849 vcap_row_cmd(ocelot, vcap, row, VCAP_CMD_WRITE, VCAP_SEL_ALL);850}851 852static void vcap_entry_get(struct ocelot *ocelot, int ix,853 struct ocelot_vcap_filter *filter)854{855 const struct vcap_props *vcap = &ocelot->vcap[filter->block_id];856 struct vcap_data data;857 int row, count;858 u32 cnt;859 860 if (filter->block_id == VCAP_ES0)861 data.tg_sw = VCAP_TG_FULL;862 else863 data.tg_sw = VCAP_TG_HALF;864 865 count = (1 << (data.tg_sw - 1));866 row = (ix / count);867 vcap_row_cmd(ocelot, vcap, row, VCAP_CMD_READ, VCAP_SEL_COUNTER);868 vcap_cache2action(ocelot, vcap, &data);869 vcap_data_offset_get(vcap, &data, ix);870 cnt = vcap_data_get(data.counter, data.counter_offset,871 vcap->counter_width);872 873 filter->stats.pkts = cnt;874}875 876static void vcap_entry_set(struct ocelot *ocelot, int ix,877 struct ocelot_vcap_filter *filter)878{879 if (filter->block_id == VCAP_IS1)880 return is1_entry_set(ocelot, ix, filter);881 if (filter->block_id == VCAP_IS2)882 return is2_entry_set(ocelot, ix, filter);883 if (filter->block_id == VCAP_ES0)884 return es0_entry_set(ocelot, ix, filter);885}886 887struct vcap_policer_entry {888 struct list_head list;889 refcount_t refcount;890 u32 pol_ix;891};892 893int ocelot_vcap_policer_add(struct ocelot *ocelot, u32 pol_ix,894 struct ocelot_policer *pol)895{896 struct qos_policer_conf pp = { 0 };897 struct vcap_policer_entry *tmp;898 int ret;899 900 if (!pol)901 return -EINVAL;902 903 pp.mode = MSCC_QOS_RATE_MODE_DATA;904 pp.pir = pol->rate;905 pp.pbs = pol->burst;906 907 list_for_each_entry(tmp, &ocelot->vcap_pol.pol_list, list)908 if (tmp->pol_ix == pol_ix) {909 refcount_inc(&tmp->refcount);910 return 0;911 }912 913 tmp = kzalloc(sizeof(*tmp), GFP_KERNEL);914 if (!tmp)915 return -ENOMEM;916 917 ret = qos_policer_conf_set(ocelot, pol_ix, &pp);918 if (ret) {919 kfree(tmp);920 return ret;921 }922 923 tmp->pol_ix = pol_ix;924 refcount_set(&tmp->refcount, 1);925 list_add_tail(&tmp->list, &ocelot->vcap_pol.pol_list);926 927 return 0;928}929EXPORT_SYMBOL(ocelot_vcap_policer_add);930 931int ocelot_vcap_policer_del(struct ocelot *ocelot, u32 pol_ix)932{933 struct qos_policer_conf pp = {0};934 struct vcap_policer_entry *tmp, *n;935 u8 z = 0;936 937 list_for_each_entry_safe(tmp, n, &ocelot->vcap_pol.pol_list, list)938 if (tmp->pol_ix == pol_ix) {939 z = refcount_dec_and_test(&tmp->refcount);940 if (z) {941 list_del(&tmp->list);942 kfree(tmp);943 }944 }945 946 if (z) {947 pp.mode = MSCC_QOS_RATE_MODE_DISABLED;948 return qos_policer_conf_set(ocelot, pol_ix, &pp);949 }950 951 return 0;952}953EXPORT_SYMBOL(ocelot_vcap_policer_del);954 955static int956ocelot_vcap_filter_add_aux_resources(struct ocelot *ocelot,957 struct ocelot_vcap_filter *filter,958 struct netlink_ext_ack *extack)959{960 struct ocelot_mirror *m;961 int ret;962 963 if (filter->block_id == VCAP_IS2 && filter->action.mirror_ena) {964 m = ocelot_mirror_get(ocelot, filter->egress_port.value,965 extack);966 if (IS_ERR(m))967 return PTR_ERR(m);968 }969 970 if (filter->block_id == VCAP_IS2 && filter->action.police_ena) {971 ret = ocelot_vcap_policer_add(ocelot, filter->action.pol_ix,972 &filter->action.pol);973 if (ret)974 return ret;975 }976 977 return 0;978}979 980static void981ocelot_vcap_filter_del_aux_resources(struct ocelot *ocelot,982 struct ocelot_vcap_filter *filter)983{984 if (filter->block_id == VCAP_IS2 && filter->action.police_ena)985 ocelot_vcap_policer_del(ocelot, filter->action.pol_ix);986 987 if (filter->block_id == VCAP_IS2 && filter->action.mirror_ena)988 ocelot_mirror_put(ocelot);989}990 991static int ocelot_vcap_filter_add_to_block(struct ocelot *ocelot,992 struct ocelot_vcap_block *block,993 struct ocelot_vcap_filter *filter,994 struct netlink_ext_ack *extack)995{996 struct list_head *pos = &block->rules;997 struct ocelot_vcap_filter *tmp;998 int ret;999 1000 ret = ocelot_vcap_filter_add_aux_resources(ocelot, filter, extack);1001 if (ret)1002 return ret;1003 1004 block->count++;1005 1006 list_for_each_entry(tmp, &block->rules, list) {1007 if (filter->prio < tmp->prio) {1008 pos = &tmp->list;1009 break;1010 }1011 }1012 list_add_tail(&filter->list, pos);1013 1014 return 0;1015}1016 1017static bool ocelot_vcap_filter_equal(const struct ocelot_vcap_filter *a,1018 const struct ocelot_vcap_filter *b)1019{1020 return !memcmp(&a->id, &b->id, sizeof(struct ocelot_vcap_id));1021}1022 1023static int ocelot_vcap_block_get_filter_index(struct ocelot_vcap_block *block,1024 struct ocelot_vcap_filter *filter)1025{1026 struct ocelot_vcap_filter *tmp;1027 int index = 0;1028 1029 list_for_each_entry(tmp, &block->rules, list) {1030 if (ocelot_vcap_filter_equal(filter, tmp))1031 return index;1032 index++;1033 }1034 1035 return -ENOENT;1036}1037 1038static struct ocelot_vcap_filter*1039ocelot_vcap_block_find_filter_by_index(struct ocelot_vcap_block *block,1040 int index)1041{1042 struct ocelot_vcap_filter *tmp;1043 int i = 0;1044 1045 list_for_each_entry(tmp, &block->rules, list) {1046 if (i == index)1047 return tmp;1048 ++i;1049 }1050 1051 return NULL;1052}1053 1054struct ocelot_vcap_filter *1055ocelot_vcap_block_find_filter_by_id(struct ocelot_vcap_block *block,1056 unsigned long cookie, bool tc_offload)1057{1058 struct ocelot_vcap_filter *filter;1059 1060 list_for_each_entry(filter, &block->rules, list)1061 if (filter->id.tc_offload == tc_offload &&1062 filter->id.cookie == cookie)1063 return filter;1064 1065 return NULL;1066}1067EXPORT_SYMBOL(ocelot_vcap_block_find_filter_by_id);1068 1069/* If @on=false, then SNAP, ARP, IP and OAM frames will not match on keys based1070 * on destination and source MAC addresses, but only on higher-level protocol1071 * information. The only frame types to match on keys containing MAC addresses1072 * in this case are non-SNAP, non-ARP, non-IP and non-OAM frames.1073 *1074 * If @on=true, then the above frame types (SNAP, ARP, IP and OAM) will match1075 * on MAC_ETYPE keys such as destination and source MAC on this ingress port.1076 * However the setting has the side effect of making these frames not matching1077 * on any _other_ keys than MAC_ETYPE ones.1078 */1079static void ocelot_match_all_as_mac_etype(struct ocelot *ocelot, int port,1080 int lookup, bool on)1081{1082 u32 val = 0;1083 1084 if (on)1085 val = ANA_PORT_VCAP_S2_CFG_S2_SNAP_DIS(BIT(lookup)) |1086 ANA_PORT_VCAP_S2_CFG_S2_ARP_DIS(BIT(lookup)) |1087 ANA_PORT_VCAP_S2_CFG_S2_IP_TCPUDP_DIS(BIT(lookup)) |1088 ANA_PORT_VCAP_S2_CFG_S2_IP_OTHER_DIS(BIT(lookup)) |1089 ANA_PORT_VCAP_S2_CFG_S2_OAM_DIS(BIT(lookup));1090 1091 ocelot_rmw_gix(ocelot, val,1092 ANA_PORT_VCAP_S2_CFG_S2_SNAP_DIS(BIT(lookup)) |1093 ANA_PORT_VCAP_S2_CFG_S2_ARP_DIS(BIT(lookup)) |1094 ANA_PORT_VCAP_S2_CFG_S2_IP_TCPUDP_DIS(BIT(lookup)) |1095 ANA_PORT_VCAP_S2_CFG_S2_IP_OTHER_DIS(BIT(lookup)) |1096 ANA_PORT_VCAP_S2_CFG_S2_OAM_DIS(BIT(lookup)),1097 ANA_PORT_VCAP_S2_CFG, port);1098}1099 1100static bool1101ocelot_vcap_is_problematic_mac_etype(struct ocelot_vcap_filter *filter)1102{1103 u16 proto, mask;1104 1105 if (filter->key_type != OCELOT_VCAP_KEY_ETYPE)1106 return false;1107 1108 proto = ntohs(*(__be16 *)filter->key.etype.etype.value);1109 mask = ntohs(*(__be16 *)filter->key.etype.etype.mask);1110 1111 /* ETH_P_ALL match, so all protocols below are included */1112 if (mask == 0)1113 return true;1114 if (proto == ETH_P_ARP)1115 return true;1116 if (proto == ETH_P_IP)1117 return true;1118 if (proto == ETH_P_IPV6)1119 return true;1120 1121 return false;1122}1123 1124static bool1125ocelot_vcap_is_problematic_non_mac_etype(struct ocelot_vcap_filter *filter)1126{1127 if (filter->key_type == OCELOT_VCAP_KEY_SNAP)1128 return true;1129 if (filter->key_type == OCELOT_VCAP_KEY_ARP)1130 return true;1131 if (filter->key_type == OCELOT_VCAP_KEY_IPV4)1132 return true;1133 if (filter->key_type == OCELOT_VCAP_KEY_IPV6)1134 return true;1135 return false;1136}1137 1138static bool1139ocelot_exclusive_mac_etype_filter_rules(struct ocelot *ocelot,1140 struct ocelot_vcap_filter *filter)1141{1142 struct ocelot_vcap_block *block = &ocelot->block[filter->block_id];1143 struct ocelot_vcap_filter *tmp;1144 unsigned long port;1145 int i;1146 1147 /* We only have the S2_IP_TCPUDP_DIS set of knobs for VCAP IS2 */1148 if (filter->block_id != VCAP_IS2)1149 return true;1150 1151 if (ocelot_vcap_is_problematic_mac_etype(filter)) {1152 /* Search for any non-MAC_ETYPE rules on the port */1153 for (i = 0; i < block->count; i++) {1154 tmp = ocelot_vcap_block_find_filter_by_index(block, i);1155 if (tmp->ingress_port_mask & filter->ingress_port_mask &&1156 tmp->lookup == filter->lookup &&1157 ocelot_vcap_is_problematic_non_mac_etype(tmp))1158 return false;1159 }1160 1161 for_each_set_bit(port, &filter->ingress_port_mask,1162 ocelot->num_phys_ports)1163 ocelot_match_all_as_mac_etype(ocelot, port,1164 filter->lookup, true);1165 } else if (ocelot_vcap_is_problematic_non_mac_etype(filter)) {1166 /* Search for any MAC_ETYPE rules on the port */1167 for (i = 0; i < block->count; i++) {1168 tmp = ocelot_vcap_block_find_filter_by_index(block, i);1169 if (tmp->ingress_port_mask & filter->ingress_port_mask &&1170 tmp->lookup == filter->lookup &&1171 ocelot_vcap_is_problematic_mac_etype(tmp))1172 return false;1173 }1174 1175 for_each_set_bit(port, &filter->ingress_port_mask,1176 ocelot->num_phys_ports)1177 ocelot_match_all_as_mac_etype(ocelot, port,1178 filter->lookup, false);1179 }1180 1181 return true;1182}1183 1184int ocelot_vcap_filter_add(struct ocelot *ocelot,1185 struct ocelot_vcap_filter *filter,1186 struct netlink_ext_ack *extack)1187{1188 struct ocelot_vcap_block *block = &ocelot->block[filter->block_id];1189 int i, index, ret;1190 1191 if (!ocelot_exclusive_mac_etype_filter_rules(ocelot, filter)) {1192 NL_SET_ERR_MSG_MOD(extack,1193 "Cannot mix MAC_ETYPE with non-MAC_ETYPE rules, use the other IS2 lookup");1194 return -EBUSY;1195 }1196 1197 /* Add filter to the linked list */1198 ret = ocelot_vcap_filter_add_to_block(ocelot, block, filter, extack);1199 if (ret)1200 return ret;1201 1202 /* Get the index of the inserted filter */1203 index = ocelot_vcap_block_get_filter_index(block, filter);1204 if (index < 0)1205 return index;1206 1207 /* Move down the rules to make place for the new filter */1208 for (i = block->count - 1; i > index; i--) {1209 struct ocelot_vcap_filter *tmp;1210 1211 tmp = ocelot_vcap_block_find_filter_by_index(block, i);1212 /* Read back the filter's counters before moving it */1213 vcap_entry_get(ocelot, i - 1, tmp);1214 vcap_entry_set(ocelot, i, tmp);1215 }1216 1217 /* Now insert the new filter */1218 vcap_entry_set(ocelot, index, filter);1219 return 0;1220}1221EXPORT_SYMBOL(ocelot_vcap_filter_add);1222 1223static void ocelot_vcap_block_remove_filter(struct ocelot *ocelot,1224 struct ocelot_vcap_block *block,1225 struct ocelot_vcap_filter *filter)1226{1227 struct ocelot_vcap_filter *tmp, *n;1228 1229 list_for_each_entry_safe(tmp, n, &block->rules, list) {1230 if (ocelot_vcap_filter_equal(filter, tmp)) {1231 ocelot_vcap_filter_del_aux_resources(ocelot, tmp);1232 list_del(&tmp->list);1233 kfree(tmp);1234 }1235 }1236 1237 block->count--;1238}1239 1240int ocelot_vcap_filter_del(struct ocelot *ocelot,1241 struct ocelot_vcap_filter *filter)1242{1243 struct ocelot_vcap_block *block = &ocelot->block[filter->block_id];1244 struct ocelot_vcap_filter del_filter;1245 int i, index;1246 1247 /* Need to inherit the block_id so that vcap_entry_set()1248 * does not get confused and knows where to install it.1249 */1250 memset(&del_filter, 0, sizeof(del_filter));1251 del_filter.block_id = filter->block_id;1252 1253 /* Gets index of the filter */1254 index = ocelot_vcap_block_get_filter_index(block, filter);1255 if (index < 0)1256 return index;1257 1258 /* Delete filter */1259 ocelot_vcap_block_remove_filter(ocelot, block, filter);1260 1261 /* Move up all the blocks over the deleted filter */1262 for (i = index; i < block->count; i++) {1263 struct ocelot_vcap_filter *tmp;1264 1265 tmp = ocelot_vcap_block_find_filter_by_index(block, i);1266 /* Read back the filter's counters before moving it */1267 vcap_entry_get(ocelot, i + 1, tmp);1268 vcap_entry_set(ocelot, i, tmp);1269 }1270 1271 /* Now delete the last filter, because it is duplicated */1272 vcap_entry_set(ocelot, block->count, &del_filter);1273 1274 return 0;1275}1276EXPORT_SYMBOL(ocelot_vcap_filter_del);1277 1278int ocelot_vcap_filter_replace(struct ocelot *ocelot,1279 struct ocelot_vcap_filter *filter)1280{1281 struct ocelot_vcap_block *block = &ocelot->block[filter->block_id];1282 int index;1283 1284 index = ocelot_vcap_block_get_filter_index(block, filter);1285 if (index < 0)1286 return index;1287 1288 vcap_entry_set(ocelot, index, filter);1289 1290 return 0;1291}1292EXPORT_SYMBOL(ocelot_vcap_filter_replace);1293 1294int ocelot_vcap_filter_stats_update(struct ocelot *ocelot,1295 struct ocelot_vcap_filter *filter)1296{1297 struct ocelot_vcap_block *block = &ocelot->block[filter->block_id];1298 struct ocelot_vcap_filter tmp;1299 int index;1300 1301 index = ocelot_vcap_block_get_filter_index(block, filter);1302 if (index < 0)1303 return index;1304 1305 vcap_entry_get(ocelot, index, filter);1306 1307 /* After we get the result we need to clear the counters */1308 tmp = *filter;1309 tmp.stats.pkts = 0;1310 vcap_entry_set(ocelot, index, &tmp);1311 1312 return 0;1313}1314 1315static void ocelot_vcap_init_one(struct ocelot *ocelot,1316 const struct vcap_props *vcap)1317{1318 struct vcap_data data;1319 1320 memset(&data, 0, sizeof(data));1321 1322 vcap_entry2cache(ocelot, vcap, &data);1323 ocelot_target_write(ocelot, vcap->target, vcap->entry_count,1324 VCAP_CORE_MV_CFG);1325 vcap_cmd(ocelot, vcap, 0, VCAP_CMD_INITIALIZE, VCAP_SEL_ENTRY);1326 1327 vcap_action2cache(ocelot, vcap, &data);1328 ocelot_target_write(ocelot, vcap->target, vcap->action_count,1329 VCAP_CORE_MV_CFG);1330 vcap_cmd(ocelot, vcap, 0, VCAP_CMD_INITIALIZE,1331 VCAP_SEL_ACTION | VCAP_SEL_COUNTER);1332}1333 1334static void ocelot_vcap_detect_constants(struct ocelot *ocelot,1335 struct vcap_props *vcap)1336{1337 int counter_memory_width;1338 int num_default_actions;1339 int version;1340 1341 version = ocelot_target_read(ocelot, vcap->target,1342 VCAP_CONST_VCAP_VER);1343 /* Only version 0 VCAP supported for now */1344 if (WARN_ON(version != 0))1345 return;1346 1347 /* Width in bits of type-group field */1348 vcap->tg_width = ocelot_target_read(ocelot, vcap->target,1349 VCAP_CONST_ENTRY_TG_WIDTH);1350 /* Number of subwords per TCAM row */1351 vcap->sw_count = ocelot_target_read(ocelot, vcap->target,1352 VCAP_CONST_ENTRY_SWCNT);1353 /* Number of rows in TCAM. There can be this many full keys, or double1354 * this number half keys, or 4 times this number quarter keys.1355 */1356 vcap->entry_count = ocelot_target_read(ocelot, vcap->target,1357 VCAP_CONST_ENTRY_CNT);1358 /* Assuming there are 4 subwords per TCAM row, their layout in the1359 * actual TCAM (not in the cache) would be:1360 *1361 * | SW 3 | TG 3 | SW 2 | TG 2 | SW 1 | TG 1 | SW 0 | TG 0 |1362 *1363 * (where SW=subword and TG=Type-Group).1364 *1365 * What VCAP_CONST_ENTRY_CNT is giving us is the width of one full TCAM1366 * row. But when software accesses the TCAM through the cache1367 * registers, the Type-Group values are written through another set of1368 * registers VCAP_TG_DAT, and therefore, it appears as though the 41369 * subwords are contiguous in the cache memory.1370 * Important mention: regardless of the number of key entries per row1371 * (and therefore of key size: 1 full key or 2 half keys or 4 quarter1372 * keys), software always has to configure 4 Type-Group values. For1373 * example, in the case of 1 full key, the driver needs to set all 41374 * Type-Group to be full key.1375 *1376 * For this reason, we need to fix up the value that the hardware is1377 * giving us. We don't actually care about the width of the entry in1378 * the TCAM. What we care about is the width of the entry in the cache1379 * registers, which is how we get to interact with it. And since the1380 * VCAP_ENTRY_DAT cache registers access only the subwords and not the1381 * Type-Groups, this means we need to subtract the width of the1382 * Type-Groups when packing and unpacking key entry data in a TCAM row.1383 */1384 vcap->entry_width = ocelot_target_read(ocelot, vcap->target,1385 VCAP_CONST_ENTRY_WIDTH);1386 vcap->entry_width -= vcap->tg_width * vcap->sw_count;1387 num_default_actions = ocelot_target_read(ocelot, vcap->target,1388 VCAP_CONST_ACTION_DEF_CNT);1389 vcap->action_count = vcap->entry_count + num_default_actions;1390 vcap->action_width = ocelot_target_read(ocelot, vcap->target,1391 VCAP_CONST_ACTION_WIDTH);1392 /* The width of the counter memory, this is the complete width of all1393 * counter-fields associated with one full-word entry. There is one1394 * counter per entry sub-word (see CAP_CORE::ENTRY_SWCNT for number of1395 * subwords.)1396 */1397 vcap->counter_words = vcap->sw_count;1398 counter_memory_width = ocelot_target_read(ocelot, vcap->target,1399 VCAP_CONST_CNT_WIDTH);1400 vcap->counter_width = counter_memory_width / vcap->counter_words;1401}1402 1403int ocelot_vcap_init(struct ocelot *ocelot)1404{1405 struct qos_policer_conf cpu_drop = {1406 .mode = MSCC_QOS_RATE_MODE_DATA,1407 };1408 int ret, i;1409 1410 /* Create a policer that will drop the frames for the cpu.1411 * This policer will be used as action in the acl rules to drop1412 * frames.1413 */1414 ret = qos_policer_conf_set(ocelot, OCELOT_POLICER_DISCARD, &cpu_drop);1415 if (ret)1416 return ret;1417 1418 for (i = 0; i < OCELOT_NUM_VCAP_BLOCKS; i++) {1419 struct ocelot_vcap_block *block = &ocelot->block[i];1420 struct vcap_props *vcap = &ocelot->vcap[i];1421 1422 INIT_LIST_HEAD(&block->rules);1423 1424 ocelot_vcap_detect_constants(ocelot, vcap);1425 ocelot_vcap_init_one(ocelot, vcap);1426 }1427 1428 INIT_LIST_HEAD(&ocelot->dummy_rules);1429 INIT_LIST_HEAD(&ocelot->traps);1430 INIT_LIST_HEAD(&ocelot->vcap_pol.pol_list);1431 1432 return 0;1433}1434