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1// SPDX-License-Identifier: GPL-2.0-or-later2/*3 * drivers/net/ethernet/nxp/lpc_eth.c4 *5 * Author: Kevin Wells <kevin.wells@nxp.com>6 *7 * Copyright (C) 2010 NXP Semiconductors8 * Copyright (C) 2012 Roland Stigge <stigge@antcom.de>9 */10 11#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt12 13#include <linux/clk.h>14#include <linux/crc32.h>15#include <linux/etherdevice.h>16#include <linux/module.h>17#include <linux/of.h>18#include <linux/of_mdio.h>19#include <linux/of_net.h>20#include <linux/phy.h>21#include <linux/platform_device.h>22#include <linux/spinlock.h>23#include <linux/soc/nxp/lpc32xx-misc.h>24 25#define MODNAME "lpc-eth"26#define DRV_VERSION "1.00"27 28#define ENET_MAXF_SIZE 153629#define ENET_RX_DESC 4830#define ENET_TX_DESC 1631 32#define NAPI_WEIGHT 1633 34/*35 * Ethernet MAC controller Register offsets36 */37#define LPC_ENET_MAC1(x) (x + 0x000)38#define LPC_ENET_MAC2(x) (x + 0x004)39#define LPC_ENET_IPGT(x) (x + 0x008)40#define LPC_ENET_IPGR(x) (x + 0x00C)41#define LPC_ENET_CLRT(x) (x + 0x010)42#define LPC_ENET_MAXF(x) (x + 0x014)43#define LPC_ENET_SUPP(x) (x + 0x018)44#define LPC_ENET_TEST(x) (x + 0x01C)45#define LPC_ENET_MCFG(x) (x + 0x020)46#define LPC_ENET_MCMD(x) (x + 0x024)47#define LPC_ENET_MADR(x) (x + 0x028)48#define LPC_ENET_MWTD(x) (x + 0x02C)49#define LPC_ENET_MRDD(x) (x + 0x030)50#define LPC_ENET_MIND(x) (x + 0x034)51#define LPC_ENET_SA0(x) (x + 0x040)52#define LPC_ENET_SA1(x) (x + 0x044)53#define LPC_ENET_SA2(x) (x + 0x048)54#define LPC_ENET_COMMAND(x) (x + 0x100)55#define LPC_ENET_STATUS(x) (x + 0x104)56#define LPC_ENET_RXDESCRIPTOR(x) (x + 0x108)57#define LPC_ENET_RXSTATUS(x) (x + 0x10C)58#define LPC_ENET_RXDESCRIPTORNUMBER(x) (x + 0x110)59#define LPC_ENET_RXPRODUCEINDEX(x) (x + 0x114)60#define LPC_ENET_RXCONSUMEINDEX(x) (x + 0x118)61#define LPC_ENET_TXDESCRIPTOR(x) (x + 0x11C)62#define LPC_ENET_TXSTATUS(x) (x + 0x120)63#define LPC_ENET_TXDESCRIPTORNUMBER(x) (x + 0x124)64#define LPC_ENET_TXPRODUCEINDEX(x) (x + 0x128)65#define LPC_ENET_TXCONSUMEINDEX(x) (x + 0x12C)66#define LPC_ENET_TSV0(x) (x + 0x158)67#define LPC_ENET_TSV1(x) (x + 0x15C)68#define LPC_ENET_RSV(x) (x + 0x160)69#define LPC_ENET_FLOWCONTROLCOUNTER(x) (x + 0x170)70#define LPC_ENET_FLOWCONTROLSTATUS(x) (x + 0x174)71#define LPC_ENET_RXFILTER_CTRL(x) (x + 0x200)72#define LPC_ENET_RXFILTERWOLSTATUS(x) (x + 0x204)73#define LPC_ENET_RXFILTERWOLCLEAR(x) (x + 0x208)74#define LPC_ENET_HASHFILTERL(x) (x + 0x210)75#define LPC_ENET_HASHFILTERH(x) (x + 0x214)76#define LPC_ENET_INTSTATUS(x) (x + 0xFE0)77#define LPC_ENET_INTENABLE(x) (x + 0xFE4)78#define LPC_ENET_INTCLEAR(x) (x + 0xFE8)79#define LPC_ENET_INTSET(x) (x + 0xFEC)80#define LPC_ENET_POWERDOWN(x) (x + 0xFF4)81 82/*83 * mac1 register definitions84 */85#define LPC_MAC1_RECV_ENABLE (1 << 0)86#define LPC_MAC1_PASS_ALL_RX_FRAMES (1 << 1)87#define LPC_MAC1_RX_FLOW_CONTROL (1 << 2)88#define LPC_MAC1_TX_FLOW_CONTROL (1 << 3)89#define LPC_MAC1_LOOPBACK (1 << 4)90#define LPC_MAC1_RESET_TX (1 << 8)91#define LPC_MAC1_RESET_MCS_TX (1 << 9)92#define LPC_MAC1_RESET_RX (1 << 10)93#define LPC_MAC1_RESET_MCS_RX (1 << 11)94#define LPC_MAC1_SIMULATION_RESET (1 << 14)95#define LPC_MAC1_SOFT_RESET (1 << 15)96 97/*98 * mac2 register definitions99 */100#define LPC_MAC2_FULL_DUPLEX (1 << 0)101#define LPC_MAC2_FRAME_LENGTH_CHECKING (1 << 1)102#define LPC_MAC2_HUGH_LENGTH_CHECKING (1 << 2)103#define LPC_MAC2_DELAYED_CRC (1 << 3)104#define LPC_MAC2_CRC_ENABLE (1 << 4)105#define LPC_MAC2_PAD_CRC_ENABLE (1 << 5)106#define LPC_MAC2_VLAN_PAD_ENABLE (1 << 6)107#define LPC_MAC2_AUTO_DETECT_PAD_ENABLE (1 << 7)108#define LPC_MAC2_PURE_PREAMBLE_ENFORCEMENT (1 << 8)109#define LPC_MAC2_LONG_PREAMBLE_ENFORCEMENT (1 << 9)110#define LPC_MAC2_NO_BACKOFF (1 << 12)111#define LPC_MAC2_BACK_PRESSURE (1 << 13)112#define LPC_MAC2_EXCESS_DEFER (1 << 14)113 114/*115 * ipgt register definitions116 */117#define LPC_IPGT_LOAD(n) ((n) & 0x7F)118 119/*120 * ipgr register definitions121 */122#define LPC_IPGR_LOAD_PART2(n) ((n) & 0x7F)123#define LPC_IPGR_LOAD_PART1(n) (((n) & 0x7F) << 8)124 125/*126 * clrt register definitions127 */128#define LPC_CLRT_LOAD_RETRY_MAX(n) ((n) & 0xF)129#define LPC_CLRT_LOAD_COLLISION_WINDOW(n) (((n) & 0x3F) << 8)130 131/*132 * maxf register definitions133 */134#define LPC_MAXF_LOAD_MAX_FRAME_LEN(n) ((n) & 0xFFFF)135 136/*137 * supp register definitions138 */139#define LPC_SUPP_SPEED (1 << 8)140#define LPC_SUPP_RESET_RMII (1 << 11)141 142/*143 * test register definitions144 */145#define LPC_TEST_SHORTCUT_PAUSE_QUANTA (1 << 0)146#define LPC_TEST_PAUSE (1 << 1)147#define LPC_TEST_BACKPRESSURE (1 << 2)148 149/*150 * mcfg register definitions151 */152#define LPC_MCFG_SCAN_INCREMENT (1 << 0)153#define LPC_MCFG_SUPPRESS_PREAMBLE (1 << 1)154#define LPC_MCFG_CLOCK_SELECT(n) (((n) & 0x7) << 2)155#define LPC_MCFG_CLOCK_HOST_DIV_4 0156#define LPC_MCFG_CLOCK_HOST_DIV_6 2157#define LPC_MCFG_CLOCK_HOST_DIV_8 3158#define LPC_MCFG_CLOCK_HOST_DIV_10 4159#define LPC_MCFG_CLOCK_HOST_DIV_14 5160#define LPC_MCFG_CLOCK_HOST_DIV_20 6161#define LPC_MCFG_CLOCK_HOST_DIV_28 7162#define LPC_MCFG_RESET_MII_MGMT (1 << 15)163 164/*165 * mcmd register definitions166 */167#define LPC_MCMD_READ (1 << 0)168#define LPC_MCMD_SCAN (1 << 1)169 170/*171 * madr register definitions172 */173#define LPC_MADR_REGISTER_ADDRESS(n) ((n) & 0x1F)174#define LPC_MADR_PHY_0ADDRESS(n) (((n) & 0x1F) << 8)175 176/*177 * mwtd register definitions178 */179#define LPC_MWDT_WRITE(n) ((n) & 0xFFFF)180 181/*182 * mrdd register definitions183 */184#define LPC_MRDD_READ_MASK 0xFFFF185 186/*187 * mind register definitions188 */189#define LPC_MIND_BUSY (1 << 0)190#define LPC_MIND_SCANNING (1 << 1)191#define LPC_MIND_NOT_VALID (1 << 2)192#define LPC_MIND_MII_LINK_FAIL (1 << 3)193 194/*195 * command register definitions196 */197#define LPC_COMMAND_RXENABLE (1 << 0)198#define LPC_COMMAND_TXENABLE (1 << 1)199#define LPC_COMMAND_REG_RESET (1 << 3)200#define LPC_COMMAND_TXRESET (1 << 4)201#define LPC_COMMAND_RXRESET (1 << 5)202#define LPC_COMMAND_PASSRUNTFRAME (1 << 6)203#define LPC_COMMAND_PASSRXFILTER (1 << 7)204#define LPC_COMMAND_TXFLOWCONTROL (1 << 8)205#define LPC_COMMAND_RMII (1 << 9)206#define LPC_COMMAND_FULLDUPLEX (1 << 10)207 208/*209 * status register definitions210 */211#define LPC_STATUS_RXACTIVE (1 << 0)212#define LPC_STATUS_TXACTIVE (1 << 1)213 214/*215 * tsv0 register definitions216 */217#define LPC_TSV0_CRC_ERROR (1 << 0)218#define LPC_TSV0_LENGTH_CHECK_ERROR (1 << 1)219#define LPC_TSV0_LENGTH_OUT_OF_RANGE (1 << 2)220#define LPC_TSV0_DONE (1 << 3)221#define LPC_TSV0_MULTICAST (1 << 4)222#define LPC_TSV0_BROADCAST (1 << 5)223#define LPC_TSV0_PACKET_DEFER (1 << 6)224#define LPC_TSV0_ESCESSIVE_DEFER (1 << 7)225#define LPC_TSV0_ESCESSIVE_COLLISION (1 << 8)226#define LPC_TSV0_LATE_COLLISION (1 << 9)227#define LPC_TSV0_GIANT (1 << 10)228#define LPC_TSV0_UNDERRUN (1 << 11)229#define LPC_TSV0_TOTAL_BYTES(n) (((n) >> 12) & 0xFFFF)230#define LPC_TSV0_CONTROL_FRAME (1 << 28)231#define LPC_TSV0_PAUSE (1 << 29)232#define LPC_TSV0_BACKPRESSURE (1 << 30)233#define LPC_TSV0_VLAN (1 << 31)234 235/*236 * tsv1 register definitions237 */238#define LPC_TSV1_TRANSMIT_BYTE_COUNT(n) ((n) & 0xFFFF)239#define LPC_TSV1_COLLISION_COUNT(n) (((n) >> 16) & 0xF)240 241/*242 * rsv register definitions243 */244#define LPC_RSV_RECEIVED_BYTE_COUNT(n) ((n) & 0xFFFF)245#define LPC_RSV_RXDV_EVENT_IGNORED (1 << 16)246#define LPC_RSV_RXDV_EVENT_PREVIOUSLY_SEEN (1 << 17)247#define LPC_RSV_CARRIER_EVNT_PREVIOUS_SEEN (1 << 18)248#define LPC_RSV_RECEIVE_CODE_VIOLATION (1 << 19)249#define LPC_RSV_CRC_ERROR (1 << 20)250#define LPC_RSV_LENGTH_CHECK_ERROR (1 << 21)251#define LPC_RSV_LENGTH_OUT_OF_RANGE (1 << 22)252#define LPC_RSV_RECEIVE_OK (1 << 23)253#define LPC_RSV_MULTICAST (1 << 24)254#define LPC_RSV_BROADCAST (1 << 25)255#define LPC_RSV_DRIBBLE_NIBBLE (1 << 26)256#define LPC_RSV_CONTROL_FRAME (1 << 27)257#define LPC_RSV_PAUSE (1 << 28)258#define LPC_RSV_UNSUPPORTED_OPCODE (1 << 29)259#define LPC_RSV_VLAN (1 << 30)260 261/*262 * flowcontrolcounter register definitions263 */264#define LPC_FCCR_MIRRORCOUNTER(n) ((n) & 0xFFFF)265#define LPC_FCCR_PAUSETIMER(n) (((n) >> 16) & 0xFFFF)266 267/*268 * flowcontrolstatus register definitions269 */270#define LPC_FCCR_MIRRORCOUNTERCURRENT(n) ((n) & 0xFFFF)271 272/*273 * rxfilterctrl, rxfilterwolstatus, and rxfilterwolclear shared274 * register definitions275 */276#define LPC_RXFLTRW_ACCEPTUNICAST (1 << 0)277#define LPC_RXFLTRW_ACCEPTUBROADCAST (1 << 1)278#define LPC_RXFLTRW_ACCEPTUMULTICAST (1 << 2)279#define LPC_RXFLTRW_ACCEPTUNICASTHASH (1 << 3)280#define LPC_RXFLTRW_ACCEPTUMULTICASTHASH (1 << 4)281#define LPC_RXFLTRW_ACCEPTPERFECT (1 << 5)282 283/*284 * rxfilterctrl register definitions285 */286#define LPC_RXFLTRWSTS_MAGICPACKETENWOL (1 << 12)287#define LPC_RXFLTRWSTS_RXFILTERENWOL (1 << 13)288 289/*290 * rxfilterwolstatus/rxfilterwolclear register definitions291 */292#define LPC_RXFLTRWSTS_RXFILTERWOL (1 << 7)293#define LPC_RXFLTRWSTS_MAGICPACKETWOL (1 << 8)294 295/*296 * intstatus, intenable, intclear, and Intset shared register297 * definitions298 */299#define LPC_MACINT_RXOVERRUNINTEN (1 << 0)300#define LPC_MACINT_RXERRORONINT (1 << 1)301#define LPC_MACINT_RXFINISHEDINTEN (1 << 2)302#define LPC_MACINT_RXDONEINTEN (1 << 3)303#define LPC_MACINT_TXUNDERRUNINTEN (1 << 4)304#define LPC_MACINT_TXERRORINTEN (1 << 5)305#define LPC_MACINT_TXFINISHEDINTEN (1 << 6)306#define LPC_MACINT_TXDONEINTEN (1 << 7)307#define LPC_MACINT_SOFTINTEN (1 << 12)308#define LPC_MACINT_WAKEUPINTEN (1 << 13)309 310/*311 * powerdown register definitions312 */313#define LPC_POWERDOWN_MACAHB (1 << 31)314 315static phy_interface_t lpc_phy_interface_mode(struct device *dev)316{317 if (dev && dev->of_node) {318 const char *mode = of_get_property(dev->of_node,319 "phy-mode", NULL);320 if (mode && !strcmp(mode, "mii"))321 return PHY_INTERFACE_MODE_MII;322 }323 return PHY_INTERFACE_MODE_RMII;324}325 326static bool use_iram_for_net(struct device *dev)327{328 if (dev && dev->of_node)329 return of_property_read_bool(dev->of_node, "use-iram");330 return false;331}332 333/* Receive Status information word */334#define RXSTATUS_SIZE 0x000007FF335#define RXSTATUS_CONTROL (1 << 18)336#define RXSTATUS_VLAN (1 << 19)337#define RXSTATUS_FILTER (1 << 20)338#define RXSTATUS_MULTICAST (1 << 21)339#define RXSTATUS_BROADCAST (1 << 22)340#define RXSTATUS_CRC (1 << 23)341#define RXSTATUS_SYMBOL (1 << 24)342#define RXSTATUS_LENGTH (1 << 25)343#define RXSTATUS_RANGE (1 << 26)344#define RXSTATUS_ALIGN (1 << 27)345#define RXSTATUS_OVERRUN (1 << 28)346#define RXSTATUS_NODESC (1 << 29)347#define RXSTATUS_LAST (1 << 30)348#define RXSTATUS_ERROR (1 << 31)349 350#define RXSTATUS_STATUS_ERROR \351 (RXSTATUS_NODESC | RXSTATUS_OVERRUN | RXSTATUS_ALIGN | \352 RXSTATUS_RANGE | RXSTATUS_LENGTH | RXSTATUS_SYMBOL | RXSTATUS_CRC)353 354/* Receive Descriptor control word */355#define RXDESC_CONTROL_SIZE 0x000007FF356#define RXDESC_CONTROL_INT (1 << 31)357 358/* Transmit Status information word */359#define TXSTATUS_COLLISIONS_GET(x) (((x) >> 21) & 0xF)360#define TXSTATUS_DEFER (1 << 25)361#define TXSTATUS_EXCESSDEFER (1 << 26)362#define TXSTATUS_EXCESSCOLL (1 << 27)363#define TXSTATUS_LATECOLL (1 << 28)364#define TXSTATUS_UNDERRUN (1 << 29)365#define TXSTATUS_NODESC (1 << 30)366#define TXSTATUS_ERROR (1 << 31)367 368/* Transmit Descriptor control word */369#define TXDESC_CONTROL_SIZE 0x000007FF370#define TXDESC_CONTROL_OVERRIDE (1 << 26)371#define TXDESC_CONTROL_HUGE (1 << 27)372#define TXDESC_CONTROL_PAD (1 << 28)373#define TXDESC_CONTROL_CRC (1 << 29)374#define TXDESC_CONTROL_LAST (1 << 30)375#define TXDESC_CONTROL_INT (1 << 31)376 377/*378 * Structure of a TX/RX descriptors and RX status379 */380struct txrx_desc_t {381 __le32 packet;382 __le32 control;383};384struct rx_status_t {385 __le32 statusinfo;386 __le32 statushashcrc;387};388 389/*390 * Device driver data structure391 */392struct netdata_local {393 struct platform_device *pdev;394 struct net_device *ndev;395 struct device_node *phy_node;396 spinlock_t lock;397 void __iomem *net_base;398 u32 msg_enable;399 unsigned int skblen[ENET_TX_DESC];400 unsigned int last_tx_idx;401 unsigned int num_used_tx_buffs;402 struct mii_bus *mii_bus;403 struct clk *clk;404 dma_addr_t dma_buff_base_p;405 void *dma_buff_base_v;406 size_t dma_buff_size;407 struct txrx_desc_t *tx_desc_v;408 u32 *tx_stat_v;409 void *tx_buff_v;410 struct txrx_desc_t *rx_desc_v;411 struct rx_status_t *rx_stat_v;412 void *rx_buff_v;413 int link;414 int speed;415 int duplex;416 struct napi_struct napi;417};418 419/*420 * MAC support functions421 */422static void __lpc_set_mac(struct netdata_local *pldat, const u8 *mac)423{424 u32 tmp;425 426 /* Set station address */427 tmp = mac[0] | ((u32)mac[1] << 8);428 writel(tmp, LPC_ENET_SA2(pldat->net_base));429 tmp = mac[2] | ((u32)mac[3] << 8);430 writel(tmp, LPC_ENET_SA1(pldat->net_base));431 tmp = mac[4] | ((u32)mac[5] << 8);432 writel(tmp, LPC_ENET_SA0(pldat->net_base));433 434 netdev_dbg(pldat->ndev, "Ethernet MAC address %pM\n", mac);435}436 437static void __lpc_get_mac(struct netdata_local *pldat, u8 *mac)438{439 u32 tmp;440 441 /* Get station address */442 tmp = readl(LPC_ENET_SA2(pldat->net_base));443 mac[0] = tmp & 0xFF;444 mac[1] = tmp >> 8;445 tmp = readl(LPC_ENET_SA1(pldat->net_base));446 mac[2] = tmp & 0xFF;447 mac[3] = tmp >> 8;448 tmp = readl(LPC_ENET_SA0(pldat->net_base));449 mac[4] = tmp & 0xFF;450 mac[5] = tmp >> 8;451}452 453static void __lpc_params_setup(struct netdata_local *pldat)454{455 u32 tmp;456 457 if (pldat->duplex == DUPLEX_FULL) {458 tmp = readl(LPC_ENET_MAC2(pldat->net_base));459 tmp |= LPC_MAC2_FULL_DUPLEX;460 writel(tmp, LPC_ENET_MAC2(pldat->net_base));461 tmp = readl(LPC_ENET_COMMAND(pldat->net_base));462 tmp |= LPC_COMMAND_FULLDUPLEX;463 writel(tmp, LPC_ENET_COMMAND(pldat->net_base));464 writel(LPC_IPGT_LOAD(0x15), LPC_ENET_IPGT(pldat->net_base));465 } else {466 tmp = readl(LPC_ENET_MAC2(pldat->net_base));467 tmp &= ~LPC_MAC2_FULL_DUPLEX;468 writel(tmp, LPC_ENET_MAC2(pldat->net_base));469 tmp = readl(LPC_ENET_COMMAND(pldat->net_base));470 tmp &= ~LPC_COMMAND_FULLDUPLEX;471 writel(tmp, LPC_ENET_COMMAND(pldat->net_base));472 writel(LPC_IPGT_LOAD(0x12), LPC_ENET_IPGT(pldat->net_base));473 }474 475 if (pldat->speed == SPEED_100)476 writel(LPC_SUPP_SPEED, LPC_ENET_SUPP(pldat->net_base));477 else478 writel(0, LPC_ENET_SUPP(pldat->net_base));479}480 481static void __lpc_eth_reset(struct netdata_local *pldat)482{483 /* Reset all MAC logic */484 writel((LPC_MAC1_RESET_TX | LPC_MAC1_RESET_MCS_TX | LPC_MAC1_RESET_RX |485 LPC_MAC1_RESET_MCS_RX | LPC_MAC1_SIMULATION_RESET |486 LPC_MAC1_SOFT_RESET), LPC_ENET_MAC1(pldat->net_base));487 writel((LPC_COMMAND_REG_RESET | LPC_COMMAND_TXRESET |488 LPC_COMMAND_RXRESET), LPC_ENET_COMMAND(pldat->net_base));489}490 491static int __lpc_mii_mngt_reset(struct netdata_local *pldat)492{493 /* Reset MII management hardware */494 writel(LPC_MCFG_RESET_MII_MGMT, LPC_ENET_MCFG(pldat->net_base));495 496 /* Setup MII clock to slowest rate with a /28 divider */497 writel(LPC_MCFG_CLOCK_SELECT(LPC_MCFG_CLOCK_HOST_DIV_28),498 LPC_ENET_MCFG(pldat->net_base));499 500 return 0;501}502 503static inline phys_addr_t __va_to_pa(void *addr, struct netdata_local *pldat)504{505 phys_addr_t phaddr;506 507 phaddr = addr - pldat->dma_buff_base_v;508 phaddr += pldat->dma_buff_base_p;509 510 return phaddr;511}512 513static void lpc_eth_enable_int(void __iomem *regbase)514{515 writel((LPC_MACINT_RXDONEINTEN | LPC_MACINT_TXDONEINTEN),516 LPC_ENET_INTENABLE(regbase));517}518 519static void lpc_eth_disable_int(void __iomem *regbase)520{521 writel(0, LPC_ENET_INTENABLE(regbase));522}523 524/* Setup TX/RX descriptors */525static void __lpc_txrx_desc_setup(struct netdata_local *pldat)526{527 u32 *ptxstat;528 void *tbuff;529 int i;530 struct txrx_desc_t *ptxrxdesc;531 struct rx_status_t *prxstat;532 533 tbuff = PTR_ALIGN(pldat->dma_buff_base_v, 16);534 535 /* Setup TX descriptors, status, and buffers */536 pldat->tx_desc_v = tbuff;537 tbuff += sizeof(struct txrx_desc_t) * ENET_TX_DESC;538 539 pldat->tx_stat_v = tbuff;540 tbuff += sizeof(u32) * ENET_TX_DESC;541 542 tbuff = PTR_ALIGN(tbuff, 16);543 pldat->tx_buff_v = tbuff;544 tbuff += ENET_MAXF_SIZE * ENET_TX_DESC;545 546 /* Setup RX descriptors, status, and buffers */547 pldat->rx_desc_v = tbuff;548 tbuff += sizeof(struct txrx_desc_t) * ENET_RX_DESC;549 550 tbuff = PTR_ALIGN(tbuff, 16);551 pldat->rx_stat_v = tbuff;552 tbuff += sizeof(struct rx_status_t) * ENET_RX_DESC;553 554 tbuff = PTR_ALIGN(tbuff, 16);555 pldat->rx_buff_v = tbuff;556 tbuff += ENET_MAXF_SIZE * ENET_RX_DESC;557 558 /* Map the TX descriptors to the TX buffers in hardware */559 for (i = 0; i < ENET_TX_DESC; i++) {560 ptxstat = &pldat->tx_stat_v[i];561 ptxrxdesc = &pldat->tx_desc_v[i];562 563 ptxrxdesc->packet = __va_to_pa(564 pldat->tx_buff_v + i * ENET_MAXF_SIZE, pldat);565 ptxrxdesc->control = 0;566 *ptxstat = 0;567 }568 569 /* Map the RX descriptors to the RX buffers in hardware */570 for (i = 0; i < ENET_RX_DESC; i++) {571 prxstat = &pldat->rx_stat_v[i];572 ptxrxdesc = &pldat->rx_desc_v[i];573 574 ptxrxdesc->packet = __va_to_pa(575 pldat->rx_buff_v + i * ENET_MAXF_SIZE, pldat);576 ptxrxdesc->control = RXDESC_CONTROL_INT | (ENET_MAXF_SIZE - 1);577 prxstat->statusinfo = 0;578 prxstat->statushashcrc = 0;579 }580 581 /* Setup base addresses in hardware to point to buffers and582 * descriptors583 */584 writel((ENET_TX_DESC - 1),585 LPC_ENET_TXDESCRIPTORNUMBER(pldat->net_base));586 writel(__va_to_pa(pldat->tx_desc_v, pldat),587 LPC_ENET_TXDESCRIPTOR(pldat->net_base));588 writel(__va_to_pa(pldat->tx_stat_v, pldat),589 LPC_ENET_TXSTATUS(pldat->net_base));590 writel((ENET_RX_DESC - 1),591 LPC_ENET_RXDESCRIPTORNUMBER(pldat->net_base));592 writel(__va_to_pa(pldat->rx_desc_v, pldat),593 LPC_ENET_RXDESCRIPTOR(pldat->net_base));594 writel(__va_to_pa(pldat->rx_stat_v, pldat),595 LPC_ENET_RXSTATUS(pldat->net_base));596}597 598static void __lpc_eth_init(struct netdata_local *pldat)599{600 u32 tmp;601 602 /* Disable controller and reset */603 tmp = readl(LPC_ENET_COMMAND(pldat->net_base));604 tmp &= ~LPC_COMMAND_RXENABLE | LPC_COMMAND_TXENABLE;605 writel(tmp, LPC_ENET_COMMAND(pldat->net_base));606 tmp = readl(LPC_ENET_MAC1(pldat->net_base));607 tmp &= ~LPC_MAC1_RECV_ENABLE;608 writel(tmp, LPC_ENET_MAC1(pldat->net_base));609 610 /* Initial MAC setup */611 writel(LPC_MAC1_PASS_ALL_RX_FRAMES, LPC_ENET_MAC1(pldat->net_base));612 writel((LPC_MAC2_PAD_CRC_ENABLE | LPC_MAC2_CRC_ENABLE),613 LPC_ENET_MAC2(pldat->net_base));614 writel(ENET_MAXF_SIZE, LPC_ENET_MAXF(pldat->net_base));615 616 /* Collision window, gap */617 writel((LPC_CLRT_LOAD_RETRY_MAX(0xF) |618 LPC_CLRT_LOAD_COLLISION_WINDOW(0x37)),619 LPC_ENET_CLRT(pldat->net_base));620 writel(LPC_IPGR_LOAD_PART2(0x12), LPC_ENET_IPGR(pldat->net_base));621 622 if (lpc_phy_interface_mode(&pldat->pdev->dev) == PHY_INTERFACE_MODE_MII)623 writel(LPC_COMMAND_PASSRUNTFRAME,624 LPC_ENET_COMMAND(pldat->net_base));625 else {626 writel((LPC_COMMAND_PASSRUNTFRAME | LPC_COMMAND_RMII),627 LPC_ENET_COMMAND(pldat->net_base));628 writel(LPC_SUPP_RESET_RMII, LPC_ENET_SUPP(pldat->net_base));629 }630 631 __lpc_params_setup(pldat);632 633 /* Setup TX and RX descriptors */634 __lpc_txrx_desc_setup(pldat);635 636 /* Setup packet filtering */637 writel((LPC_RXFLTRW_ACCEPTUBROADCAST | LPC_RXFLTRW_ACCEPTPERFECT),638 LPC_ENET_RXFILTER_CTRL(pldat->net_base));639 640 /* Get the next TX buffer output index */641 pldat->num_used_tx_buffs = 0;642 pldat->last_tx_idx =643 readl(LPC_ENET_TXCONSUMEINDEX(pldat->net_base));644 645 /* Clear and enable interrupts */646 writel(0xFFFF, LPC_ENET_INTCLEAR(pldat->net_base));647 smp_wmb();648 lpc_eth_enable_int(pldat->net_base);649 650 /* Enable controller */651 tmp = readl(LPC_ENET_COMMAND(pldat->net_base));652 tmp |= LPC_COMMAND_RXENABLE | LPC_COMMAND_TXENABLE;653 writel(tmp, LPC_ENET_COMMAND(pldat->net_base));654 tmp = readl(LPC_ENET_MAC1(pldat->net_base));655 tmp |= LPC_MAC1_RECV_ENABLE;656 writel(tmp, LPC_ENET_MAC1(pldat->net_base));657}658 659static void __lpc_eth_shutdown(struct netdata_local *pldat)660{661 /* Reset ethernet and power down PHY */662 __lpc_eth_reset(pldat);663 writel(0, LPC_ENET_MAC1(pldat->net_base));664 writel(0, LPC_ENET_MAC2(pldat->net_base));665}666 667/*668 * MAC<--->PHY support functions669 */670static int lpc_mdio_read(struct mii_bus *bus, int phy_id, int phyreg)671{672 struct netdata_local *pldat = bus->priv;673 unsigned long timeout = jiffies + msecs_to_jiffies(100);674 int lps;675 676 writel(((phy_id << 8) | phyreg), LPC_ENET_MADR(pldat->net_base));677 writel(LPC_MCMD_READ, LPC_ENET_MCMD(pldat->net_base));678 679 /* Wait for unbusy status */680 while (readl(LPC_ENET_MIND(pldat->net_base)) & LPC_MIND_BUSY) {681 if (time_after(jiffies, timeout))682 return -EIO;683 cpu_relax();684 }685 686 lps = readl(LPC_ENET_MRDD(pldat->net_base));687 writel(0, LPC_ENET_MCMD(pldat->net_base));688 689 return lps;690}691 692static int lpc_mdio_write(struct mii_bus *bus, int phy_id, int phyreg,693 u16 phydata)694{695 struct netdata_local *pldat = bus->priv;696 unsigned long timeout = jiffies + msecs_to_jiffies(100);697 698 writel(((phy_id << 8) | phyreg), LPC_ENET_MADR(pldat->net_base));699 writel(phydata, LPC_ENET_MWTD(pldat->net_base));700 701 /* Wait for completion */702 while (readl(LPC_ENET_MIND(pldat->net_base)) & LPC_MIND_BUSY) {703 if (time_after(jiffies, timeout))704 return -EIO;705 cpu_relax();706 }707 708 return 0;709}710 711static int lpc_mdio_reset(struct mii_bus *bus)712{713 return __lpc_mii_mngt_reset((struct netdata_local *)bus->priv);714}715 716static void lpc_handle_link_change(struct net_device *ndev)717{718 struct netdata_local *pldat = netdev_priv(ndev);719 struct phy_device *phydev = ndev->phydev;720 unsigned long flags;721 722 bool status_change = false;723 724 spin_lock_irqsave(&pldat->lock, flags);725 726 if (phydev->link) {727 if ((pldat->speed != phydev->speed) ||728 (pldat->duplex != phydev->duplex)) {729 pldat->speed = phydev->speed;730 pldat->duplex = phydev->duplex;731 status_change = true;732 }733 }734 735 if (phydev->link != pldat->link) {736 if (!phydev->link) {737 pldat->speed = 0;738 pldat->duplex = -1;739 }740 pldat->link = phydev->link;741 742 status_change = true;743 }744 745 spin_unlock_irqrestore(&pldat->lock, flags);746 747 if (status_change)748 __lpc_params_setup(pldat);749}750 751static int lpc_mii_probe(struct net_device *ndev)752{753 struct netdata_local *pldat = netdev_priv(ndev);754 struct phy_device *phydev;755 756 /* Attach to the PHY */757 if (lpc_phy_interface_mode(&pldat->pdev->dev) == PHY_INTERFACE_MODE_MII)758 netdev_info(ndev, "using MII interface\n");759 else760 netdev_info(ndev, "using RMII interface\n");761 762 if (pldat->phy_node)763 phydev = of_phy_find_device(pldat->phy_node);764 else765 phydev = phy_find_first(pldat->mii_bus);766 if (!phydev) {767 netdev_err(ndev, "no PHY found\n");768 return -ENODEV;769 }770 771 phydev = phy_connect(ndev, phydev_name(phydev),772 &lpc_handle_link_change,773 lpc_phy_interface_mode(&pldat->pdev->dev));774 if (IS_ERR(phydev)) {775 netdev_err(ndev, "Could not attach to PHY\n");776 return PTR_ERR(phydev);777 }778 779 phy_set_max_speed(phydev, SPEED_100);780 781 pldat->link = 0;782 pldat->speed = 0;783 pldat->duplex = -1;784 785 phy_attached_info(phydev);786 787 return 0;788}789 790static int lpc_mii_init(struct netdata_local *pldat)791{792 struct device_node *node;793 int err = -ENXIO;794 795 pldat->mii_bus = mdiobus_alloc();796 if (!pldat->mii_bus) {797 err = -ENOMEM;798 goto err_out;799 }800 801 /* Setup MII mode */802 if (lpc_phy_interface_mode(&pldat->pdev->dev) == PHY_INTERFACE_MODE_MII)803 writel(LPC_COMMAND_PASSRUNTFRAME,804 LPC_ENET_COMMAND(pldat->net_base));805 else {806 writel((LPC_COMMAND_PASSRUNTFRAME | LPC_COMMAND_RMII),807 LPC_ENET_COMMAND(pldat->net_base));808 writel(LPC_SUPP_RESET_RMII, LPC_ENET_SUPP(pldat->net_base));809 }810 811 pldat->mii_bus->name = "lpc_mii_bus";812 pldat->mii_bus->read = &lpc_mdio_read;813 pldat->mii_bus->write = &lpc_mdio_write;814 pldat->mii_bus->reset = &lpc_mdio_reset;815 snprintf(pldat->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",816 pldat->pdev->name, pldat->pdev->id);817 pldat->mii_bus->priv = pldat;818 pldat->mii_bus->parent = &pldat->pdev->dev;819 820 node = of_get_child_by_name(pldat->pdev->dev.of_node, "mdio");821 err = of_mdiobus_register(pldat->mii_bus, node);822 of_node_put(node);823 if (err)824 goto err_out_unregister_bus;825 826 err = lpc_mii_probe(pldat->ndev);827 if (err)828 goto err_out_unregister_bus;829 830 return 0;831 832err_out_unregister_bus:833 mdiobus_unregister(pldat->mii_bus);834 mdiobus_free(pldat->mii_bus);835err_out:836 return err;837}838 839static void __lpc_handle_xmit(struct net_device *ndev)840{841 struct netdata_local *pldat = netdev_priv(ndev);842 u32 txcidx, *ptxstat, txstat;843 844 txcidx = readl(LPC_ENET_TXCONSUMEINDEX(pldat->net_base));845 while (pldat->last_tx_idx != txcidx) {846 unsigned int skblen = pldat->skblen[pldat->last_tx_idx];847 848 /* A buffer is available, get buffer status */849 ptxstat = &pldat->tx_stat_v[pldat->last_tx_idx];850 txstat = *ptxstat;851 852 /* Next buffer and decrement used buffer counter */853 pldat->num_used_tx_buffs--;854 pldat->last_tx_idx++;855 if (pldat->last_tx_idx >= ENET_TX_DESC)856 pldat->last_tx_idx = 0;857 858 /* Update collision counter */859 ndev->stats.collisions += TXSTATUS_COLLISIONS_GET(txstat);860 861 /* Any errors occurred? */862 if (txstat & TXSTATUS_ERROR) {863 if (txstat & TXSTATUS_UNDERRUN) {864 /* FIFO underrun */865 ndev->stats.tx_fifo_errors++;866 }867 if (txstat & TXSTATUS_LATECOLL) {868 /* Late collision */869 ndev->stats.tx_aborted_errors++;870 }871 if (txstat & TXSTATUS_EXCESSCOLL) {872 /* Excessive collision */873 ndev->stats.tx_aborted_errors++;874 }875 if (txstat & TXSTATUS_EXCESSDEFER) {876 /* Defer limit */877 ndev->stats.tx_aborted_errors++;878 }879 ndev->stats.tx_errors++;880 } else {881 /* Update stats */882 ndev->stats.tx_packets++;883 ndev->stats.tx_bytes += skblen;884 }885 886 txcidx = readl(LPC_ENET_TXCONSUMEINDEX(pldat->net_base));887 }888 889 if (pldat->num_used_tx_buffs <= ENET_TX_DESC/2) {890 if (netif_queue_stopped(ndev))891 netif_wake_queue(ndev);892 }893}894 895static int __lpc_handle_recv(struct net_device *ndev, int budget)896{897 struct netdata_local *pldat = netdev_priv(ndev);898 struct sk_buff *skb;899 u32 rxconsidx, len, ethst;900 struct rx_status_t *prxstat;901 int rx_done = 0;902 903 /* Get the current RX buffer indexes */904 rxconsidx = readl(LPC_ENET_RXCONSUMEINDEX(pldat->net_base));905 while (rx_done < budget && rxconsidx !=906 readl(LPC_ENET_RXPRODUCEINDEX(pldat->net_base))) {907 /* Get pointer to receive status */908 prxstat = &pldat->rx_stat_v[rxconsidx];909 len = (prxstat->statusinfo & RXSTATUS_SIZE) + 1;910 911 /* Status error? */912 ethst = prxstat->statusinfo;913 if ((ethst & (RXSTATUS_ERROR | RXSTATUS_STATUS_ERROR)) ==914 (RXSTATUS_ERROR | RXSTATUS_RANGE))915 ethst &= ~RXSTATUS_ERROR;916 917 if (ethst & RXSTATUS_ERROR) {918 int si = prxstat->statusinfo;919 /* Check statuses */920 if (si & RXSTATUS_OVERRUN) {921 /* Overrun error */922 ndev->stats.rx_fifo_errors++;923 } else if (si & RXSTATUS_CRC) {924 /* CRC error */925 ndev->stats.rx_crc_errors++;926 } else if (si & RXSTATUS_LENGTH) {927 /* Length error */928 ndev->stats.rx_length_errors++;929 } else if (si & RXSTATUS_ERROR) {930 /* Other error */931 ndev->stats.rx_length_errors++;932 }933 ndev->stats.rx_errors++;934 } else {935 /* Packet is good */936 skb = dev_alloc_skb(len);937 if (!skb) {938 ndev->stats.rx_dropped++;939 } else {940 /* Copy packet from buffer */941 skb_put_data(skb,942 pldat->rx_buff_v + rxconsidx * ENET_MAXF_SIZE,943 len);944 945 /* Pass to upper layer */946 skb->protocol = eth_type_trans(skb, ndev);947 netif_receive_skb(skb);948 ndev->stats.rx_packets++;949 ndev->stats.rx_bytes += len;950 }951 }952 953 /* Increment consume index */954 rxconsidx = rxconsidx + 1;955 if (rxconsidx >= ENET_RX_DESC)956 rxconsidx = 0;957 writel(rxconsidx,958 LPC_ENET_RXCONSUMEINDEX(pldat->net_base));959 rx_done++;960 }961 962 return rx_done;963}964 965static int lpc_eth_poll(struct napi_struct *napi, int budget)966{967 struct netdata_local *pldat = container_of(napi,968 struct netdata_local, napi);969 struct net_device *ndev = pldat->ndev;970 int rx_done = 0;971 struct netdev_queue *txq = netdev_get_tx_queue(ndev, 0);972 973 __netif_tx_lock(txq, smp_processor_id());974 __lpc_handle_xmit(ndev);975 __netif_tx_unlock(txq);976 rx_done = __lpc_handle_recv(ndev, budget);977 978 if (rx_done < budget) {979 napi_complete_done(napi, rx_done);980 lpc_eth_enable_int(pldat->net_base);981 }982 983 return rx_done;984}985 986static irqreturn_t __lpc_eth_interrupt(int irq, void *dev_id)987{988 struct net_device *ndev = dev_id;989 struct netdata_local *pldat = netdev_priv(ndev);990 u32 tmp;991 992 spin_lock(&pldat->lock);993 994 tmp = readl(LPC_ENET_INTSTATUS(pldat->net_base));995 /* Clear interrupts */996 writel(tmp, LPC_ENET_INTCLEAR(pldat->net_base));997 998 lpc_eth_disable_int(pldat->net_base);999 if (likely(napi_schedule_prep(&pldat->napi)))1000 __napi_schedule(&pldat->napi);1001 1002 spin_unlock(&pldat->lock);1003 1004 return IRQ_HANDLED;1005}1006 1007static int lpc_eth_close(struct net_device *ndev)1008{1009 unsigned long flags;1010 struct netdata_local *pldat = netdev_priv(ndev);1011 1012 if (netif_msg_ifdown(pldat))1013 dev_dbg(&pldat->pdev->dev, "shutting down %s\n", ndev->name);1014 1015 napi_disable(&pldat->napi);1016 netif_stop_queue(ndev);1017 1018 spin_lock_irqsave(&pldat->lock, flags);1019 __lpc_eth_reset(pldat);1020 netif_carrier_off(ndev);1021 writel(0, LPC_ENET_MAC1(pldat->net_base));1022 writel(0, LPC_ENET_MAC2(pldat->net_base));1023 spin_unlock_irqrestore(&pldat->lock, flags);1024 1025 if (ndev->phydev)1026 phy_stop(ndev->phydev);1027 clk_disable_unprepare(pldat->clk);1028 1029 return 0;1030}1031 1032static netdev_tx_t lpc_eth_hard_start_xmit(struct sk_buff *skb,1033 struct net_device *ndev)1034{1035 struct netdata_local *pldat = netdev_priv(ndev);1036 u32 len, txidx;1037 u32 *ptxstat;1038 struct txrx_desc_t *ptxrxdesc;1039 1040 len = skb->len;1041 1042 spin_lock_irq(&pldat->lock);1043 1044 if (pldat->num_used_tx_buffs >= (ENET_TX_DESC - 1)) {1045 /* This function should never be called when there are no1046 * buffers1047 */1048 netif_stop_queue(ndev);1049 spin_unlock_irq(&pldat->lock);1050 WARN(1, "BUG! TX request when no free TX buffers!\n");1051 return NETDEV_TX_BUSY;1052 }1053 1054 /* Get the next TX descriptor index */1055 txidx = readl(LPC_ENET_TXPRODUCEINDEX(pldat->net_base));1056 1057 /* Setup control for the transfer */1058 ptxstat = &pldat->tx_stat_v[txidx];1059 *ptxstat = 0;1060 ptxrxdesc = &pldat->tx_desc_v[txidx];1061 ptxrxdesc->control =1062 (len - 1) | TXDESC_CONTROL_LAST | TXDESC_CONTROL_INT;1063 1064 /* Copy data to the DMA buffer */1065 memcpy(pldat->tx_buff_v + txidx * ENET_MAXF_SIZE, skb->data, len);1066 1067 /* Save the buffer and increment the buffer counter */1068 pldat->skblen[txidx] = len;1069 pldat->num_used_tx_buffs++;1070 1071 /* Start transmit */1072 txidx++;1073 if (txidx >= ENET_TX_DESC)1074 txidx = 0;1075 writel(txidx, LPC_ENET_TXPRODUCEINDEX(pldat->net_base));1076 1077 /* Stop queue if no more TX buffers */1078 if (pldat->num_used_tx_buffs >= (ENET_TX_DESC - 1))1079 netif_stop_queue(ndev);1080 1081 spin_unlock_irq(&pldat->lock);1082 1083 dev_kfree_skb(skb);1084 return NETDEV_TX_OK;1085}1086 1087static int lpc_set_mac_address(struct net_device *ndev, void *p)1088{1089 struct sockaddr *addr = p;1090 struct netdata_local *pldat = netdev_priv(ndev);1091 unsigned long flags;1092 1093 if (!is_valid_ether_addr(addr->sa_data))1094 return -EADDRNOTAVAIL;1095 eth_hw_addr_set(ndev, addr->sa_data);1096 1097 spin_lock_irqsave(&pldat->lock, flags);1098 1099 /* Set station address */1100 __lpc_set_mac(pldat, ndev->dev_addr);1101 1102 spin_unlock_irqrestore(&pldat->lock, flags);1103 1104 return 0;1105}1106 1107static void lpc_eth_set_multicast_list(struct net_device *ndev)1108{1109 struct netdata_local *pldat = netdev_priv(ndev);1110 struct netdev_hw_addr_list *mcptr = &ndev->mc;1111 struct netdev_hw_addr *ha;1112 u32 tmp32, hash_val, hashlo, hashhi;1113 unsigned long flags;1114 1115 spin_lock_irqsave(&pldat->lock, flags);1116 1117 /* Set station address */1118 __lpc_set_mac(pldat, ndev->dev_addr);1119 1120 tmp32 = LPC_RXFLTRW_ACCEPTUBROADCAST | LPC_RXFLTRW_ACCEPTPERFECT;1121 1122 if (ndev->flags & IFF_PROMISC)1123 tmp32 |= LPC_RXFLTRW_ACCEPTUNICAST |1124 LPC_RXFLTRW_ACCEPTUMULTICAST;1125 if (ndev->flags & IFF_ALLMULTI)1126 tmp32 |= LPC_RXFLTRW_ACCEPTUMULTICAST;1127 1128 if (netdev_hw_addr_list_count(mcptr))1129 tmp32 |= LPC_RXFLTRW_ACCEPTUMULTICASTHASH;1130 1131 writel(tmp32, LPC_ENET_RXFILTER_CTRL(pldat->net_base));1132 1133 1134 /* Set initial hash table */1135 hashlo = 0x0;1136 hashhi = 0x0;1137 1138 /* 64 bits : multicast address in hash table */1139 netdev_hw_addr_list_for_each(ha, mcptr) {1140 hash_val = (ether_crc(6, ha->addr) >> 23) & 0x3F;1141 1142 if (hash_val >= 32)1143 hashhi |= 1 << (hash_val - 32);1144 else1145 hashlo |= 1 << hash_val;1146 }1147 1148 writel(hashlo, LPC_ENET_HASHFILTERL(pldat->net_base));1149 writel(hashhi, LPC_ENET_HASHFILTERH(pldat->net_base));1150 1151 spin_unlock_irqrestore(&pldat->lock, flags);1152}1153 1154static int lpc_eth_open(struct net_device *ndev)1155{1156 struct netdata_local *pldat = netdev_priv(ndev);1157 int ret;1158 1159 if (netif_msg_ifup(pldat))1160 dev_dbg(&pldat->pdev->dev, "enabling %s\n", ndev->name);1161 1162 ret = clk_prepare_enable(pldat->clk);1163 if (ret)1164 return ret;1165 1166 /* Suspended PHY makes LPC ethernet core block, so resume now */1167 phy_resume(ndev->phydev);1168 1169 /* Reset and initialize */1170 __lpc_eth_reset(pldat);1171 __lpc_eth_init(pldat);1172 1173 /* schedule a link state check */1174 phy_start(ndev->phydev);1175 netif_start_queue(ndev);1176 napi_enable(&pldat->napi);1177 1178 return 0;1179}1180 1181/*1182 * Ethtool ops1183 */1184static void lpc_eth_ethtool_getdrvinfo(struct net_device *ndev,1185 struct ethtool_drvinfo *info)1186{1187 strscpy(info->driver, MODNAME, sizeof(info->driver));1188 strscpy(info->version, DRV_VERSION, sizeof(info->version));1189 strscpy(info->bus_info, dev_name(ndev->dev.parent),1190 sizeof(info->bus_info));1191}1192 1193static u32 lpc_eth_ethtool_getmsglevel(struct net_device *ndev)1194{1195 struct netdata_local *pldat = netdev_priv(ndev);1196 1197 return pldat->msg_enable;1198}1199 1200static void lpc_eth_ethtool_setmsglevel(struct net_device *ndev, u32 level)1201{1202 struct netdata_local *pldat = netdev_priv(ndev);1203 1204 pldat->msg_enable = level;1205}1206 1207static const struct ethtool_ops lpc_eth_ethtool_ops = {1208 .get_drvinfo = lpc_eth_ethtool_getdrvinfo,1209 .get_msglevel = lpc_eth_ethtool_getmsglevel,1210 .set_msglevel = lpc_eth_ethtool_setmsglevel,1211 .get_link = ethtool_op_get_link,1212 .get_link_ksettings = phy_ethtool_get_link_ksettings,1213 .set_link_ksettings = phy_ethtool_set_link_ksettings,1214};1215 1216static const struct net_device_ops lpc_netdev_ops = {1217 .ndo_open = lpc_eth_open,1218 .ndo_stop = lpc_eth_close,1219 .ndo_start_xmit = lpc_eth_hard_start_xmit,1220 .ndo_set_rx_mode = lpc_eth_set_multicast_list,1221 .ndo_eth_ioctl = phy_do_ioctl_running,1222 .ndo_set_mac_address = lpc_set_mac_address,1223 .ndo_validate_addr = eth_validate_addr,1224};1225 1226static int lpc_eth_drv_probe(struct platform_device *pdev)1227{1228 struct device *dev = &pdev->dev;1229 struct device_node *np = dev->of_node;1230 struct netdata_local *pldat;1231 struct net_device *ndev;1232 dma_addr_t dma_handle;1233 struct resource *res;1234 u8 addr[ETH_ALEN];1235 int irq, ret;1236 1237 /* Setup network interface for RMII or MII mode */1238 lpc32xx_set_phy_interface_mode(lpc_phy_interface_mode(dev));1239 1240 /* Get platform resources */1241 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);1242 irq = platform_get_irq(pdev, 0);1243 if (!res || irq < 0) {1244 dev_err(dev, "error getting resources.\n");1245 ret = -ENXIO;1246 goto err_exit;1247 }1248 1249 /* Allocate net driver data structure */1250 ndev = alloc_etherdev(sizeof(struct netdata_local));1251 if (!ndev) {1252 dev_err(dev, "could not allocate device.\n");1253 ret = -ENOMEM;1254 goto err_exit;1255 }1256 1257 SET_NETDEV_DEV(ndev, dev);1258 1259 pldat = netdev_priv(ndev);1260 pldat->pdev = pdev;1261 pldat->ndev = ndev;1262 1263 spin_lock_init(&pldat->lock);1264 1265 /* Save resources */1266 ndev->irq = irq;1267 1268 /* Get clock for the device */1269 pldat->clk = clk_get(dev, NULL);1270 if (IS_ERR(pldat->clk)) {1271 dev_err(dev, "error getting clock.\n");1272 ret = PTR_ERR(pldat->clk);1273 goto err_out_free_dev;1274 }1275 1276 /* Enable network clock */1277 ret = clk_prepare_enable(pldat->clk);1278 if (ret)1279 goto err_out_clk_put;1280 1281 /* Map IO space */1282 pldat->net_base = ioremap(res->start, resource_size(res));1283 if (!pldat->net_base) {1284 dev_err(dev, "failed to map registers\n");1285 ret = -ENOMEM;1286 goto err_out_disable_clocks;1287 }1288 ret = request_irq(ndev->irq, __lpc_eth_interrupt, 0,1289 ndev->name, ndev);1290 if (ret) {1291 dev_err(dev, "error requesting interrupt.\n");1292 goto err_out_iounmap;1293 }1294 1295 /* Setup driver functions */1296 ndev->netdev_ops = &lpc_netdev_ops;1297 ndev->ethtool_ops = &lpc_eth_ethtool_ops;1298 ndev->watchdog_timeo = msecs_to_jiffies(2500);1299 1300 /* Get size of DMA buffers/descriptors region */1301 pldat->dma_buff_size = (ENET_TX_DESC + ENET_RX_DESC) * (ENET_MAXF_SIZE +1302 sizeof(struct txrx_desc_t) + sizeof(struct rx_status_t));1303 1304 if (use_iram_for_net(dev)) {1305 if (pldat->dma_buff_size >1306 lpc32xx_return_iram(&pldat->dma_buff_base_v, &dma_handle)) {1307 pldat->dma_buff_base_v = NULL;1308 pldat->dma_buff_size = 0;1309 netdev_err(ndev,1310 "IRAM not big enough for net buffers, using SDRAM instead.\n");1311 }1312 }1313 1314 if (pldat->dma_buff_base_v == NULL) {1315 ret = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(32));1316 if (ret)1317 goto err_out_free_irq;1318 1319 pldat->dma_buff_size = PAGE_ALIGN(pldat->dma_buff_size);1320 1321 /* Allocate a chunk of memory for the DMA ethernet buffers1322 * and descriptors1323 */1324 pldat->dma_buff_base_v =1325 dma_alloc_coherent(dev,1326 pldat->dma_buff_size, &dma_handle,1327 GFP_KERNEL);1328 if (pldat->dma_buff_base_v == NULL) {1329 ret = -ENOMEM;1330 goto err_out_free_irq;1331 }1332 }1333 pldat->dma_buff_base_p = dma_handle;1334 1335 netdev_dbg(ndev, "IO address space :%pR\n", res);1336 netdev_dbg(ndev, "IO address size :%zd\n",1337 (size_t)resource_size(res));1338 netdev_dbg(ndev, "IO address (mapped) :0x%p\n",1339 pldat->net_base);1340 netdev_dbg(ndev, "IRQ number :%d\n", ndev->irq);1341 netdev_dbg(ndev, "DMA buffer size :%zd\n", pldat->dma_buff_size);1342 netdev_dbg(ndev, "DMA buffer P address :%pad\n",1343 &pldat->dma_buff_base_p);1344 netdev_dbg(ndev, "DMA buffer V address :0x%p\n",1345 pldat->dma_buff_base_v);1346 1347 pldat->phy_node = of_parse_phandle(np, "phy-handle", 0);1348 1349 /* Get MAC address from current HW setting (POR state is all zeros) */1350 __lpc_get_mac(pldat, addr);1351 eth_hw_addr_set(ndev, addr);1352 1353 if (!is_valid_ether_addr(ndev->dev_addr)) {1354 of_get_ethdev_address(np, ndev);1355 }1356 if (!is_valid_ether_addr(ndev->dev_addr))1357 eth_hw_addr_random(ndev);1358 1359 /* then shut everything down to save power */1360 __lpc_eth_shutdown(pldat);1361 1362 /* Set default parameters */1363 pldat->msg_enable = NETIF_MSG_LINK;1364 1365 /* Force an MII interface reset and clock setup */1366 __lpc_mii_mngt_reset(pldat);1367 1368 /* Force default PHY interface setup in chip, this will probably be1369 * changed by the PHY driver1370 */1371 pldat->link = 0;1372 pldat->speed = 100;1373 pldat->duplex = DUPLEX_FULL;1374 __lpc_params_setup(pldat);1375 1376 netif_napi_add_weight(ndev, &pldat->napi, lpc_eth_poll, NAPI_WEIGHT);1377 1378 ret = register_netdev(ndev);1379 if (ret) {1380 dev_err(dev, "Cannot register net device, aborting.\n");1381 goto err_out_dma_unmap;1382 }1383 platform_set_drvdata(pdev, ndev);1384 1385 ret = lpc_mii_init(pldat);1386 if (ret)1387 goto err_out_unregister_netdev;1388 1389 netdev_info(ndev, "LPC mac at 0x%08lx irq %d\n",1390 (unsigned long)res->start, ndev->irq);1391 1392 device_init_wakeup(dev, 1);1393 device_set_wakeup_enable(dev, 0);1394 1395 return 0;1396 1397err_out_unregister_netdev:1398 unregister_netdev(ndev);1399err_out_dma_unmap:1400 if (!use_iram_for_net(dev) ||1401 pldat->dma_buff_size > lpc32xx_return_iram(NULL, NULL))1402 dma_free_coherent(dev, pldat->dma_buff_size,1403 pldat->dma_buff_base_v,1404 pldat->dma_buff_base_p);1405err_out_free_irq:1406 free_irq(ndev->irq, ndev);1407err_out_iounmap:1408 iounmap(pldat->net_base);1409err_out_disable_clocks:1410 clk_disable_unprepare(pldat->clk);1411err_out_clk_put:1412 clk_put(pldat->clk);1413err_out_free_dev:1414 free_netdev(ndev);1415err_exit:1416 pr_err("%s: not found (%d).\n", MODNAME, ret);1417 return ret;1418}1419 1420static void lpc_eth_drv_remove(struct platform_device *pdev)1421{1422 struct net_device *ndev = platform_get_drvdata(pdev);1423 struct netdata_local *pldat = netdev_priv(ndev);1424 1425 unregister_netdev(ndev);1426 1427 if (!use_iram_for_net(&pldat->pdev->dev) ||1428 pldat->dma_buff_size > lpc32xx_return_iram(NULL, NULL))1429 dma_free_coherent(&pldat->pdev->dev, pldat->dma_buff_size,1430 pldat->dma_buff_base_v,1431 pldat->dma_buff_base_p);1432 free_irq(ndev->irq, ndev);1433 iounmap(pldat->net_base);1434 mdiobus_unregister(pldat->mii_bus);1435 mdiobus_free(pldat->mii_bus);1436 clk_disable_unprepare(pldat->clk);1437 clk_put(pldat->clk);1438 free_netdev(ndev);1439}1440 1441#ifdef CONFIG_PM1442static int lpc_eth_drv_suspend(struct platform_device *pdev,1443 pm_message_t state)1444{1445 struct net_device *ndev = platform_get_drvdata(pdev);1446 struct netdata_local *pldat = netdev_priv(ndev);1447 1448 if (device_may_wakeup(&pdev->dev))1449 enable_irq_wake(ndev->irq);1450 1451 if (ndev) {1452 if (netif_running(ndev)) {1453 netif_device_detach(ndev);1454 __lpc_eth_shutdown(pldat);1455 clk_disable_unprepare(pldat->clk);1456 1457 /*1458 * Reset again now clock is disable to be sure1459 * EMC_MDC is down1460 */1461 __lpc_eth_reset(pldat);1462 }1463 }1464 1465 return 0;1466}1467 1468static int lpc_eth_drv_resume(struct platform_device *pdev)1469{1470 struct net_device *ndev = platform_get_drvdata(pdev);1471 struct netdata_local *pldat;1472 int ret;1473 1474 if (device_may_wakeup(&pdev->dev))1475 disable_irq_wake(ndev->irq);1476 1477 if (ndev) {1478 if (netif_running(ndev)) {1479 pldat = netdev_priv(ndev);1480 1481 /* Enable interface clock */1482 ret = clk_enable(pldat->clk);1483 if (ret)1484 return ret;1485 1486 /* Reset and initialize */1487 __lpc_eth_reset(pldat);1488 __lpc_eth_init(pldat);1489 1490 netif_device_attach(ndev);1491 }1492 }1493 1494 return 0;1495}1496#endif1497 1498static const struct of_device_id lpc_eth_match[] = {1499 { .compatible = "nxp,lpc-eth" },1500 { }1501};1502MODULE_DEVICE_TABLE(of, lpc_eth_match);1503 1504static struct platform_driver lpc_eth_driver = {1505 .probe = lpc_eth_drv_probe,1506 .remove_new = lpc_eth_drv_remove,1507#ifdef CONFIG_PM1508 .suspend = lpc_eth_drv_suspend,1509 .resume = lpc_eth_drv_resume,1510#endif1511 .driver = {1512 .name = MODNAME,1513 .of_match_table = lpc_eth_match,1514 },1515};1516 1517module_platform_driver(lpc_eth_driver);1518 1519MODULE_AUTHOR("Kevin Wells <kevin.wells@nxp.com>");1520MODULE_AUTHOR("Roland Stigge <stigge@antcom.de>");1521MODULE_DESCRIPTION("LPC Ethernet Driver");1522MODULE_LICENSE("GPL");1523