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1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */2/* QLogic qed NIC Driver3 * Copyright (c) 2019-2021 Marvell International Ltd.4 */5 6#ifndef _QED_IRO_HSI_H7#define _QED_IRO_HSI_H8 9#include <linux/types.h>10 11enum {12 IRO_YSTORM_FLOW_CONTROL_MODE_GTT,13 IRO_PSTORM_PKT_DUPLICATION_CFG,14 IRO_TSTORM_PORT_STAT,15 IRO_TSTORM_LL2_PORT_STAT,16 IRO_TSTORM_PKT_DUPLICATION_CFG,17 IRO_USTORM_VF_PF_CHANNEL_READY_GTT,18 IRO_USTORM_FLR_FINAL_ACK_GTT,19 IRO_USTORM_EQE_CONS_GTT,20 IRO_USTORM_ETH_QUEUE_ZONE_GTT,21 IRO_USTORM_COMMON_QUEUE_CONS_GTT,22 IRO_XSTORM_PQ_INFO,23 IRO_XSTORM_INTEG_TEST_DATA,24 IRO_YSTORM_INTEG_TEST_DATA,25 IRO_PSTORM_INTEG_TEST_DATA,26 IRO_TSTORM_INTEG_TEST_DATA,27 IRO_MSTORM_INTEG_TEST_DATA,28 IRO_USTORM_INTEG_TEST_DATA,29 IRO_XSTORM_OVERLAY_BUF_ADDR,30 IRO_YSTORM_OVERLAY_BUF_ADDR,31 IRO_PSTORM_OVERLAY_BUF_ADDR,32 IRO_TSTORM_OVERLAY_BUF_ADDR,33 IRO_MSTORM_OVERLAY_BUF_ADDR,34 IRO_USTORM_OVERLAY_BUF_ADDR,35 IRO_TSTORM_LL2_RX_PRODS_GTT,36 IRO_CORE_LL2_TSTORM_PER_QUEUE_STAT,37 IRO_CORE_LL2_USTORM_PER_QUEUE_STAT,38 IRO_CORE_LL2_PSTORM_PER_QUEUE_STAT,39 IRO_MSTORM_QUEUE_STAT,40 IRO_MSTORM_TPA_TIMEOUT_US,41 IRO_MSTORM_ETH_VF_PRODS,42 IRO_MSTORM_ETH_PF_PRODS_GTT,43 IRO_MSTORM_ETH_PF_STAT,44 IRO_USTORM_QUEUE_STAT,45 IRO_USTORM_ETH_PF_STAT,46 IRO_PSTORM_QUEUE_STAT,47 IRO_PSTORM_ETH_PF_STAT,48 IRO_PSTORM_CTL_FRAME_ETHTYPE_GTT,49 IRO_TSTORM_ETH_PRS_INPUT,50 IRO_ETH_RX_RATE_LIMIT,51 IRO_TSTORM_ETH_RSS_UPDATE_GTT,52 IRO_XSTORM_ETH_QUEUE_ZONE_GTT,53 IRO_YSTORM_TOE_CQ_PROD,54 IRO_USTORM_TOE_CQ_PROD,55 IRO_USTORM_TOE_GRQ_PROD,56 IRO_TSTORM_SCSI_CMDQ_CONS_GTT,57 IRO_TSTORM_SCSI_BDQ_EXT_PROD_GTT,58 IRO_MSTORM_SCSI_BDQ_EXT_PROD_GTT,59 IRO_TSTORM_ISCSI_RX_STATS,60 IRO_MSTORM_ISCSI_RX_STATS,61 IRO_USTORM_ISCSI_RX_STATS,62 IRO_XSTORM_ISCSI_TX_STATS,63 IRO_YSTORM_ISCSI_TX_STATS,64 IRO_PSTORM_ISCSI_TX_STATS,65 IRO_TSTORM_FCOE_RX_STATS,66 IRO_PSTORM_FCOE_TX_STATS,67 IRO_PSTORM_RDMA_QUEUE_STAT,68 IRO_TSTORM_RDMA_QUEUE_STAT,69 IRO_XSTORM_RDMA_ASSERT_LEVEL,70 IRO_YSTORM_RDMA_ASSERT_LEVEL,71 IRO_PSTORM_RDMA_ASSERT_LEVEL,72 IRO_TSTORM_RDMA_ASSERT_LEVEL,73 IRO_MSTORM_RDMA_ASSERT_LEVEL,74 IRO_USTORM_RDMA_ASSERT_LEVEL,75 IRO_XSTORM_IWARP_RXMIT_STATS,76 IRO_TSTORM_ROCE_EVENTS_STAT,77 IRO_YSTORM_ROCE_DCQCN_RECEIVED_STATS,78 IRO_YSTORM_ROCE_ERROR_STATS,79 IRO_PSTORM_ROCE_DCQCN_SENT_STATS,80 IRO_USTORM_ROCE_CQE_STATS,81};82 83/* Pstorm LiteL2 queue statistics */84 85#define CORE_LL2_PSTORM_PER_QUEUE_STAT_OFFSET(core_tx_stats_id) \86 (IRO[IRO_CORE_LL2_PSTORM_PER_QUEUE_STAT].base \87 + ((core_tx_stats_id) * IRO[IRO_CORE_LL2_PSTORM_PER_QUEUE_STAT].m1))88#define CORE_LL2_PSTORM_PER_QUEUE_STAT_SIZE \89 (IRO[IRO_CORE_LL2_PSTORM_PER_QUEUE_STAT].size)90 91/* Tstorm LightL2 queue statistics */92#define CORE_LL2_TSTORM_PER_QUEUE_STAT_OFFSET(core_rx_queue_id) \93 (IRO[IRO_CORE_LL2_TSTORM_PER_QUEUE_STAT].base \94 + ((core_rx_queue_id) * IRO[IRO_CORE_LL2_TSTORM_PER_QUEUE_STAT].m1))95#define CORE_LL2_TSTORM_PER_QUEUE_STAT_SIZE \96 (IRO[IRO_CORE_LL2_TSTORM_PER_QUEUE_STAT].size)97 98/* Ustorm LiteL2 queue statistics */99#define CORE_LL2_USTORM_PER_QUEUE_STAT_OFFSET(core_rx_queue_id) \100 (IRO[IRO_CORE_LL2_USTORM_PER_QUEUE_STAT].base \101 + ((core_rx_queue_id) * IRO[IRO_CORE_LL2_USTORM_PER_QUEUE_STAT].m1))102#define CORE_LL2_USTORM_PER_QUEUE_STAT_SIZE \103 (IRO[IRO_CORE_LL2_USTORM_PER_QUEUE_STAT].size)104 105/* Tstorm Eth limit Rx rate */106#define ETH_RX_RATE_LIMIT_OFFSET(pf_id) \107 (IRO[IRO_ETH_RX_RATE_LIMIT].base \108 + ((pf_id) * IRO[IRO_ETH_RX_RATE_LIMIT].m1))109#define ETH_RX_RATE_LIMIT_SIZE (IRO[IRO_ETH_RX_RATE_LIMIT].size)110 111/* Mstorm ETH PF queues producers */112#define MSTORM_ETH_PF_PRODS_GTT_OFFSET(queue_id) \113 (IRO[IRO_MSTORM_ETH_PF_PRODS_GTT].base \114 + ((queue_id) * IRO[IRO_MSTORM_ETH_PF_PRODS_GTT].m1))115#define MSTORM_ETH_PF_PRODS_GTT_SIZE (IRO[IRO_MSTORM_ETH_PF_PRODS_GTT].size)116 117/* Mstorm pf statistics */118#define MSTORM_ETH_PF_STAT_OFFSET(pf_id) \119 (IRO[IRO_MSTORM_ETH_PF_STAT].base \120 + ((pf_id) * IRO[IRO_MSTORM_ETH_PF_STAT].m1))121#define MSTORM_ETH_PF_STAT_SIZE (IRO[IRO_MSTORM_ETH_PF_STAT].size)122 123/* Mstorm ETH VF queues producers offset in RAM. Used in default VF zone124 * size mode.125 */126#define MSTORM_ETH_VF_PRODS_OFFSET(vf_id, vf_queue_id) \127 (IRO[IRO_MSTORM_ETH_VF_PRODS].base \128 + ((vf_id) * IRO[IRO_MSTORM_ETH_VF_PRODS].m1) \129 + ((vf_queue_id) * IRO[IRO_MSTORM_ETH_VF_PRODS].m2))130#define MSTORM_ETH_VF_PRODS_SIZE (IRO[IRO_MSTORM_ETH_VF_PRODS].size)131 132/* Mstorm Integration Test Data */133#define MSTORM_INTEG_TEST_DATA_OFFSET (IRO[IRO_MSTORM_INTEG_TEST_DATA].base)134#define MSTORM_INTEG_TEST_DATA_SIZE (IRO[IRO_MSTORM_INTEG_TEST_DATA].size)135 136/* Mstorm iSCSI RX stats */137#define MSTORM_ISCSI_RX_STATS_OFFSET(storage_func_id) \138 (IRO[IRO_MSTORM_ISCSI_RX_STATS].base \139 + ((storage_func_id) * IRO[IRO_MSTORM_ISCSI_RX_STATS].m1))140#define MSTORM_ISCSI_RX_STATS_SIZE (IRO[IRO_MSTORM_ISCSI_RX_STATS].size)141 142/* Mstorm overlay buffer host address */143#define MSTORM_OVERLAY_BUF_ADDR_OFFSET (IRO[IRO_MSTORM_OVERLAY_BUF_ADDR].base)144#define MSTORM_OVERLAY_BUF_ADDR_SIZE (IRO[IRO_MSTORM_OVERLAY_BUF_ADDR].size)145 146/* Mstorm queue statistics */147#define MSTORM_QUEUE_STAT_OFFSET(stat_counter_id) \148 (IRO[IRO_MSTORM_QUEUE_STAT].base \149 + ((stat_counter_id) * IRO[IRO_MSTORM_QUEUE_STAT].m1))150#define MSTORM_QUEUE_STAT_SIZ (IRO[IRO_MSTORM_QUEUE_STAT].size)151 152/* Mstorm error level for assert */153#define MSTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id) \154 (IRO[IRO_MSTORM_RDMA_ASSERT_LEVEL].base \155 + ((pf_id) * IRO[IRO_MSTORM_RDMA_ASSERT_LEVEL].m1))156#define MSTORM_RDMA_ASSERT_LEVEL_SIZE (IRO[IRO_MSTORM_RDMA_ASSERT_LEVEL].size)157 158/* Mstorm bdq-external-producer of given BDQ resource ID, BDqueue-id */159#define MSTORM_SCSI_BDQ_EXT_PROD_GTT_OFFSET(storage_func_id, bdq_id) \160 (IRO[IRO_MSTORM_SCSI_BDQ_EXT_PROD_GTT].base \161 + ((storage_func_id) * IRO[IRO_MSTORM_SCSI_BDQ_EXT_PROD_GTT].m1) \162 + ((bdq_id) * IRO[IRO_MSTORM_SCSI_BDQ_EXT_PROD_GTT].m2))163#define MSTORM_SCSI_BDQ_EXT_PROD_GTT_SIZE \164 (IRO[IRO_MSTORM_SCSI_BDQ_EXT_PROD_GTT].size)165 166/* TPA agregation timeout in us resolution (on ASIC) */167#define MSTORM_TPA_TIMEOUT_US_OFFSET (IRO[IRO_MSTORM_TPA_TIMEOUT_US].base)168#define MSTORM_TPA_TIMEOUT_US_SIZE (IRO[IRO_MSTORM_TPA_TIMEOUT_US].size)169 170/* Control frame's EthType configuration for TX control frame security */171#define PSTORM_CTL_FRAME_ETHTYPE_GTT_OFFSET(ethtype_id) \172 (IRO[IRO_PSTORM_CTL_FRAME_ETHTYPE_GTT].base \173 + ((ethtype_id) * IRO[IRO_PSTORM_CTL_FRAME_ETHTYPE_GTT].m1))174#define PSTORM_CTL_FRAME_ETHTYPE_GTT_SIZE \175 (IRO[IRO_PSTORM_CTL_FRAME_ETHTYPE_GTT].size)176 177/* Pstorm pf statistics */178#define PSTORM_ETH_PF_STAT_OFFSET(pf_id) \179 (IRO[IRO_PSTORM_ETH_PF_STAT].base \180 + ((pf_id) * IRO[IRO_PSTORM_ETH_PF_STAT].m1))181#define PSTORM_ETH_PF_STAT_SIZE (IRO[IRO_PSTORM_ETH_PF_STAT].size)182 183/* Pstorm FCoE TX stats */184#define PSTORM_FCOE_TX_STATS_OFFSET(pf_id) \185 (IRO[IRO_PSTORM_FCOE_TX_STATS].base \186 + ((pf_id) * IRO[IRO_PSTORM_FCOE_TX_STATS].m1))187#define PSTORM_FCOE_TX_STATS_SIZE (IRO[IRO_PSTORM_FCOE_TX_STATS].size)188 189/* Pstorm Integration Test Data */190#define PSTORM_INTEG_TEST_DATA_OFFSET (IRO[IRO_PSTORM_INTEG_TEST_DATA].base)191#define PSTORM_INTEG_TEST_DATA_SIZE (IRO[IRO_PSTORM_INTEG_TEST_DATA].size)192 193/* Pstorm iSCSI TX stats */194#define PSTORM_ISCSI_TX_STATS_OFFSET(storage_func_id) \195 (IRO[IRO_PSTORM_ISCSI_TX_STATS].base \196 + ((storage_func_id) * IRO[IRO_PSTORM_ISCSI_TX_STATS].m1))197#define PSTORM_ISCSI_TX_STATS_SIZE (IRO[IRO_PSTORM_ISCSI_TX_STATS].size)198 199/* Pstorm overlay buffer host address */200#define PSTORM_OVERLAY_BUF_ADDR_OFFSET (IRO[IRO_PSTORM_OVERLAY_BUF_ADDR].base)201#define PSTORM_OVERLAY_BUF_ADDR_SIZE (IRO[IRO_PSTORM_OVERLAY_BUF_ADDR].size)202 203/* Pstorm LL2 packet duplication configuration. Use pstorm_pkt_dup_cfg204 * data type.205 */206#define PSTORM_PKT_DUPLICATION_CFG_OFFSET(pf_id) \207 (IRO[IRO_PSTORM_PKT_DUPLICATION_CFG].base \208 + ((pf_id) * IRO[IRO_PSTORM_PKT_DUPLICATION_CFG].m1))209#define PSTORM_PKT_DUPLICATION_CFG_SIZE \210 (IRO[IRO_PSTORM_PKT_DUPLICATION_CFG].size)211 212/* Pstorm queue statistics */213#define PSTORM_QUEUE_STAT_OFFSET(stat_counter_id) \214 (IRO[IRO_PSTORM_QUEUE_STAT].base \215 + ((stat_counter_id) * IRO[IRO_PSTORM_QUEUE_STAT].m1))216#define PSTORM_QUEUE_STAT_SIZE (IRO[IRO_PSTORM_QUEUE_STAT].size)217 218/* Pstorm error level for assert */219#define PSTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id) \220 (IRO[IRO_PSTORM_RDMA_ASSERT_LEVEL].base \221 + ((pf_id) * IRO[IRO_PSTORM_RDMA_ASSERT_LEVEL].m1))222#define PSTORM_RDMA_ASSERT_LEVEL_SIZE (IRO[IRO_PSTORM_RDMA_ASSERT_LEVEL].size)223 224/* Pstorm RDMA queue statistics */225#define PSTORM_RDMA_QUEUE_STAT_OFFSET(rdma_stat_counter_id) \226 (IRO[IRO_PSTORM_RDMA_QUEUE_STAT].base \227 + ((rdma_stat_counter_id) * IRO[IRO_PSTORM_RDMA_QUEUE_STAT].m1))228#define PSTORM_RDMA_QUEUE_STAT_SIZE (IRO[IRO_PSTORM_RDMA_QUEUE_STAT].size)229 230/* DCQCN Sent Statistics */231#define PSTORM_ROCE_DCQCN_SENT_STATS_OFFSET(roce_pf_id) \232 (IRO[IRO_PSTORM_ROCE_DCQCN_SENT_STATS].base \233 + ((roce_pf_id) * IRO[IRO_PSTORM_ROCE_DCQCN_SENT_STATS].m1))234#define PSTORM_ROCE_DCQCN_SENT_STATS_SIZE \235 (IRO[IRO_PSTORM_ROCE_DCQCN_SENT_STATS].size)236 237/* Tstorm last parser message */238#define TSTORM_ETH_PRS_INPUT_OFFSET (IRO[IRO_TSTORM_ETH_PRS_INPUT].base)239#define TSTORM_ETH_PRS_INPUT_SIZE (IRO[IRO_TSTORM_ETH_PRS_INPUT].size)240 241/* RSS indirection table entry update command per PF offset in TSTORM PF BAR0.242 * Use eth_tstorm_rss_update_data for update.243 */244#define TSTORM_ETH_RSS_UPDATE_GTT_OFFSET(pf_id) \245 (IRO[IRO_TSTORM_ETH_RSS_UPDATE_GTT].base \246 + ((pf_id) * IRO[IRO_TSTORM_ETH_RSS_UPDATE_GTT].m1))247#define TSTORM_ETH_RSS_UPDATE_GTT_SIZE\248 (IRO[IRO_TSTORM_ETH_RSS_UPDATE_GTT].size)249 250/* Tstorm FCoE RX stats */251#define TSTORM_FCOE_RX_STATS_OFFSET(pf_id) \252 (IRO[IRO_TSTORM_FCOE_RX_STATS].base \253 + ((pf_id) * IRO[IRO_TSTORM_FCOE_RX_STATS].m1))254#define TSTORM_FCOE_RX_STATS_SIZE (IRO[IRO_TSTORM_FCOE_RX_STATS].size)255 256/* Tstorm Integration Test Data */257#define TSTORM_INTEG_TEST_DATA_OFFSET (IRO[IRO_TSTORM_INTEG_TEST_DATA].base)258#define TSTORM_INTEG_TEST_DATA_SIZE (IRO[IRO_TSTORM_INTEG_TEST_DATA].size)259 260/* Tstorm iSCSI RX stats */261#define TSTORM_ISCSI_RX_STATS_OFFSET(storage_func_id) \262 (IRO[IRO_TSTORM_ISCSI_RX_STATS].base \263 + ((storage_func_id) * IRO[IRO_TSTORM_ISCSI_RX_STATS].m1))264#define TSTORM_ISCSI_RX_STATS_SIZE (IRO[IRO_TSTORM_ISCSI_RX_STATS].size)265 266/* Tstorm ll2 port statistics */267#define TSTORM_LL2_PORT_STAT_OFFSET(port_id) \268 (IRO[IRO_TSTORM_LL2_PORT_STAT].base \269 + ((port_id) * IRO[IRO_TSTORM_LL2_PORT_STAT].m1))270#define TSTORM_LL2_PORT_STAT_SIZE (IRO[IRO_TSTORM_LL2_PORT_STAT].size)271 272/* Tstorm producers */273#define TSTORM_LL2_RX_PRODS_GTT_OFFSET(core_rx_queue_id) \274 (IRO[IRO_TSTORM_LL2_RX_PRODS_GTT].base \275 + ((core_rx_queue_id) * IRO[IRO_TSTORM_LL2_RX_PRODS_GTT].m1))276#define TSTORM_LL2_RX_PRODS_GTT_SIZE (IRO[IRO_TSTORM_LL2_RX_PRODS_GTT].size)277 278/* Tstorm overlay buffer host address */279#define TSTORM_OVERLAY_BUF_ADDR_OFFSET (IRO[IRO_TSTORM_OVERLAY_BUF_ADDR].base)280 281#define TSTORM_OVERLAY_BUF_ADDR_SIZE (IRO[IRO_TSTORM_OVERLAY_BUF_ADDR].size)282 283/* Tstorm LL2 packet duplication configuration.284 * Use tstorm_pkt_dup_cfg data type.285 */286#define TSTORM_PKT_DUPLICATION_CFG_OFFSET(pf_id) \287 (IRO[IRO_TSTORM_PKT_DUPLICATION_CFG].base \288 + ((pf_id) * IRO[IRO_TSTORM_PKT_DUPLICATION_CFG].m1))289#define TSTORM_PKT_DUPLICATION_CFG_SIZE \290 (IRO[IRO_TSTORM_PKT_DUPLICATION_CFG].size)291 292/* Tstorm port statistics */293#define TSTORM_PORT_STAT_OFFSET(port_id) \294 (IRO[IRO_TSTORM_PORT_STAT].base \295 + ((port_id) * IRO[IRO_TSTORM_PORT_STAT].m1))296#define TSTORM_PORT_STAT_SIZE (IRO[IRO_TSTORM_PORT_STAT].size)297 298/* Tstorm error level for assert */299#define TSTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id) \300 (IRO[IRO_TSTORM_RDMA_ASSERT_LEVEL].base \301 + ((pf_id) * IRO[IRO_TSTORM_RDMA_ASSERT_LEVEL].m1))302#define TSTORM_RDMA_ASSERT_LEVEL_SIZE (IRO[IRO_TSTORM_RDMA_ASSERT_LEVEL].size)303 304/* Tstorm RDMA queue statistics */305#define TSTORM_RDMA_QUEUE_STAT_OFFSET(rdma_stat_counter_id) \306 (IRO[IRO_TSTORM_RDMA_QUEUE_STAT].base \307 + ((rdma_stat_counter_id) * IRO[IRO_TSTORM_RDMA_QUEUE_STAT].m1))308#define TSTORM_RDMA_QUEUE_STAT_SIZE (IRO[IRO_TSTORM_RDMA_QUEUE_STAT].size)309 310/* Tstorm RoCE Event Statistics */311#define TSTORM_ROCE_EVENTS_STAT_OFFSET(roce_pf_id) \312 (IRO[IRO_TSTORM_ROCE_EVENTS_STAT].base \313 + ((roce_pf_id) * IRO[IRO_TSTORM_ROCE_EVENTS_STAT].m1))314#define TSTORM_ROCE_EVENTS_STAT_SIZE (IRO[IRO_TSTORM_ROCE_EVENTS_STAT].size)315 316/* Tstorm (reflects M-Storm) bdq-external-producer of given function ID,317 * BDqueue-id.318 */319#define TSTORM_SCSI_BDQ_EXT_PROD_GTT_OFFSET(storage_func_id, bdq_id) \320 (IRO[IRO_TSTORM_SCSI_BDQ_EXT_PROD_GTT].base \321 + ((storage_func_id) * IRO[IRO_TSTORM_SCSI_BDQ_EXT_PROD_GTT].m1) \322 + ((bdq_id) * IRO[IRO_TSTORM_SCSI_BDQ_EXT_PROD_GTT].m2))323#define TSTORM_SCSI_BDQ_EXT_PROD_GTT_SIZE \324 (IRO[IRO_TSTORM_SCSI_BDQ_EXT_PROD_GTT].size)325 326/* Tstorm cmdq-cons of given command queue-id */327#define TSTORM_SCSI_CMDQ_CONS_GTT_OFFSET(cmdq_queue_id) \328 (IRO[IRO_TSTORM_SCSI_CMDQ_CONS_GTT].base \329 + ((cmdq_queue_id) * IRO[IRO_TSTORM_SCSI_CMDQ_CONS_GTT].m1))330#define TSTORM_SCSI_CMDQ_CONS_GTT_SIZE \331 (IRO[IRO_TSTORM_SCSI_CMDQ_CONS_GTT].size)332 333/* Ustorm Common Queue ring consumer */334#define USTORM_COMMON_QUEUE_CONS_GTT_OFFSET(queue_zone_id) \335 (IRO[IRO_USTORM_COMMON_QUEUE_CONS_GTT].base \336 + ((queue_zone_id) * IRO[IRO_USTORM_COMMON_QUEUE_CONS_GTT].m1))337#define USTORM_COMMON_QUEUE_CONS_GTT_SIZE \338 (IRO[IRO_USTORM_COMMON_QUEUE_CONS_GTT].size)339 340/* Ustorm Event ring consumer */341#define USTORM_EQE_CONS_GTT_OFFSET(pf_id) \342 (IRO[IRO_USTORM_EQE_CONS_GTT].base \343 + ((pf_id) * IRO[IRO_USTORM_EQE_CONS_GTT].m1))344#define USTORM_EQE_CONS_GTT_SIZE (IRO[IRO_USTORM_EQE_CONS_GTT].size)345 346/* Ustorm pf statistics */347#define USTORM_ETH_PF_STAT_OFFSET(pf_id) \348 (IRO[IRO_USTORM_ETH_PF_STAT].base \349 + ((pf_id) * IRO[IRO_USTORM_ETH_PF_STAT].m1))350#define USTORM_ETH_PF_STAT_SIZE (IRO[IRO_USTORM_ETH_PF_STAT].size)351 352/* Ustorm eth queue zone */353#define USTORM_ETH_QUEUE_ZONE_GTT_OFFSET(queue_zone_id) \354 (IRO[IRO_USTORM_ETH_QUEUE_ZONE_GTT].base \355 + ((queue_zone_id) * IRO[IRO_USTORM_ETH_QUEUE_ZONE_GTT].m1))356#define USTORM_ETH_QUEUE_ZONE_GTT_SIZE (IRO[IRO_USTORM_ETH_QUEUE_ZONE_GTT].size)357 358/* Ustorm Final flr cleanup ack */359#define USTORM_FLR_FINAL_ACK_GTT_OFFSET(pf_id) \360 (IRO[IRO_USTORM_FLR_FINAL_ACK_GTT].base \361 + ((pf_id) * IRO[IRO_USTORM_FLR_FINAL_ACK_GTT].m1))362#define USTORM_FLR_FINAL_ACK_GTT_SIZE (IRO[IRO_USTORM_FLR_FINAL_ACK_GTT].size)363 364/* Ustorm Integration Test Data */365#define USTORM_INTEG_TEST_DATA_OFFSET (IRO[IRO_USTORM_INTEG_TEST_DATA].base)366#define USTORM_INTEG_TEST_DATA_SIZE (IRO[IRO_USTORM_INTEG_TEST_DATA].size)367 368/* Ustorm iSCSI RX stats */369#define USTORM_ISCSI_RX_STATS_OFFSET(storage_func_id) \370 (IRO[IRO_USTORM_ISCSI_RX_STATS].base \371 + ((storage_func_id) * IRO[IRO_USTORM_ISCSI_RX_STATS].m1))372#define USTORM_ISCSI_RX_STATS_SIZE (IRO[IRO_USTORM_ISCSI_RX_STATS].size)373 374/* Ustorm overlay buffer host address */375#define USTORM_OVERLAY_BUF_ADDR_OFFSET (IRO[IRO_USTORM_OVERLAY_BUF_ADDR].base)376#define USTORM_OVERLAY_BUF_ADDR_SIZE (IRO[IRO_USTORM_OVERLAY_BUF_ADDR].size)377 378/* Ustorm queue statistics */379#define USTORM_QUEUE_STAT_OFFSET(stat_counter_id) \380 (IRO[IRO_USTORM_QUEUE_STAT].base \381 + ((stat_counter_id) * IRO[IRO_USTORM_QUEUE_STAT].m1))382#define USTORM_QUEUE_STAT_SIZE (IRO[IRO_USTORM_QUEUE_STAT].size)383 384/* Ustorm error level for assert */385#define USTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id) \386 (IRO[IRO_USTORM_RDMA_ASSERT_LEVEL].base \387 + ((pf_id) * IRO[IRO_USTORM_RDMA_ASSERT_LEVEL].m1))388#define USTORM_RDMA_ASSERT_LEVEL_SIZE (IRO[IRO_USTORM_RDMA_ASSERT_LEVEL].size)389 390/* RoCE CQEs Statistics */391#define USTORM_ROCE_CQE_STATS_OFFSET(roce_pf_id) \392 (IRO[IRO_USTORM_ROCE_CQE_STATS].base \393 + ((roce_pf_id) * IRO[IRO_USTORM_ROCE_CQE_STATS].m1))394#define USTORM_ROCE_CQE_STATS_SIZE (IRO[IRO_USTORM_ROCE_CQE_STATS].size)395 396/* Ustorm cqe producer */397#define USTORM_TOE_CQ_PROD_OFFSET(rss_id) \398 (IRO[IRO_USTORM_TOE_CQ_PROD].base \399 + ((rss_id) * IRO[IRO_USTORM_TOE_CQ_PROD].m1))400#define USTORM_TOE_CQ_PROD_SIZE (IRO[IRO_USTORM_TOE_CQ_PROD].size)401 402/* Ustorm grq producer */403#define USTORM_TOE_GRQ_PROD_OFFSET(pf_id) \404 (IRO[IRO_USTORM_TOE_GRQ_PROD].base \405 + ((pf_id) * IRO[IRO_USTORM_TOE_GRQ_PROD].m1))406#define USTORM_TOE_GRQ_PROD_SIZE (IRO[IRO_USTORM_TOE_GRQ_PROD].size)407 408/* Ustorm VF-PF Channel ready flag */409#define USTORM_VF_PF_CHANNEL_READY_GTT_OFFSET(vf_id) \410 (IRO[IRO_USTORM_VF_PF_CHANNEL_READY_GTT].base \411 + ((vf_id) * IRO[IRO_USTORM_VF_PF_CHANNEL_READY_GTT].m1))412#define USTORM_VF_PF_CHANNEL_READY_GTT_SIZE \413 (IRO[IRO_USTORM_VF_PF_CHANNEL_READY_GTT].size)414 415/* Xstorm queue zone */416#define XSTORM_ETH_QUEUE_ZONE_GTT_OFFSET(queue_id) \417 (IRO[IRO_XSTORM_ETH_QUEUE_ZONE_GTT].base \418 + ((queue_id) * IRO[IRO_XSTORM_ETH_QUEUE_ZONE_GTT].m1))419#define XSTORM_ETH_QUEUE_ZONE_GTT_SIZE (IRO[IRO_XSTORM_ETH_QUEUE_ZONE_GTT].size)420 421/* Xstorm Integration Test Data */422#define XSTORM_INTEG_TEST_DATA_OFFSET (IRO[IRO_XSTORM_INTEG_TEST_DATA].base)423#define XSTORM_INTEG_TEST_DATA_SIZE (IRO[IRO_XSTORM_INTEG_TEST_DATA].size)424 425/* Xstorm iSCSI TX stats */426#define XSTORM_ISCSI_TX_STATS_OFFSET(storage_func_id) \427 (IRO[IRO_XSTORM_ISCSI_TX_STATS].base \428 + ((storage_func_id) * IRO[IRO_XSTORM_ISCSI_TX_STATS].m1))429#define XSTORM_ISCSI_TX_STATS_SIZE (IRO[IRO_XSTORM_ISCSI_TX_STATS].size)430 431/* Xstorm iWARP rxmit stats */432#define XSTORM_IWARP_RXMIT_STATS_OFFSET(pf_id) \433 (IRO[IRO_XSTORM_IWARP_RXMIT_STATS].base \434 + ((pf_id) * IRO[IRO_XSTORM_IWARP_RXMIT_STATS].m1))435#define XSTORM_IWARP_RXMIT_STATS_SIZE (IRO[IRO_XSTORM_IWARP_RXMIT_STATS].size)436 437/* Xstorm overlay buffer host address */438#define XSTORM_OVERLAY_BUF_ADDR_OFFSET (IRO[IRO_XSTORM_OVERLAY_BUF_ADDR].base)439#define XSTORM_OVERLAY_BUF_ADDR_SIZE (IRO[IRO_XSTORM_OVERLAY_BUF_ADDR].size)440 441/* Xstorm common PQ info */442#define XSTORM_PQ_INFO_OFFSET(pq_id) \443 (IRO[IRO_XSTORM_PQ_INFO].base \444 + ((pq_id) * IRO[IRO_XSTORM_PQ_INFO].m1))445#define XSTORM_PQ_INFO_SIZE (IRO[IRO_XSTORM_PQ_INFO].size)446 447/* Xstorm error level for assert */448#define XSTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id) \449 (IRO[IRO_XSTORM_RDMA_ASSERT_LEVEL].base \450 + ((pf_id) * IRO[IRO_XSTORM_RDMA_ASSERT_LEVEL].m1))451#define XSTORM_RDMA_ASSERT_LEVEL_SIZE (IRO[IRO_XSTORM_RDMA_ASSERT_LEVEL].size)452 453/* Ystorm flow control mode. Use enum fw_flow_ctrl_mode */454#define YSTORM_FLOW_CONTROL_MODE_GTT_OFFSET \455 (IRO[IRO_YSTORM_FLOW_CONTROL_MODE_GTT].base)456#define YSTORM_FLOW_CONTROL_MODE_GTT_SIZE \457 (IRO[IRO_YSTORM_FLOW_CONTROL_MODE_GTT].size)458 459/* Ystorm Integration Test Data */460#define YSTORM_INTEG_TEST_DATA_OFFSET (IRO[IRO_YSTORM_INTEG_TEST_DATA].base)461#define YSTORM_INTEG_TEST_DATA_SIZE (IRO[IRO_YSTORM_INTEG_TEST_DATA].size)462 463/* Ystorm iSCSI TX stats */464#define YSTORM_ISCSI_TX_STATS_OFFSET(storage_func_id) \465 (IRO[IRO_YSTORM_ISCSI_TX_STATS].base \466 + ((storage_func_id) * IRO[IRO_YSTORM_ISCSI_TX_STATS].m1))467#define YSTORM_ISCSI_TX_STATS_SIZE (IRO[IRO_YSTORM_ISCSI_TX_STATS].size)468 469/* Ystorm overlay buffer host address */470#define YSTORM_OVERLAY_BUF_ADDR_OFFSET (IRO[IRO_YSTORM_OVERLAY_BUF_ADDR].base)471#define YSTORM_OVERLAY_BUF_ADDR_SIZE (IRO[IRO_YSTORM_OVERLAY_BUF_ADDR].size)472 473/* Ystorm error level for assert */474#define YSTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id) \475 (IRO[IRO_YSTORM_RDMA_ASSERT_LEVEL].base \476 + ((pf_id) * IRO[IRO_YSTORM_RDMA_ASSERT_LEVEL].m1))477#define YSTORM_RDMA_ASSERT_LEVEL_SIZE (IRO[IRO_YSTORM_RDMA_ASSERT_LEVEL].size)478 479/* DCQCN Received Statistics */480#define YSTORM_ROCE_DCQCN_RECEIVED_STATS_OFFSET(roce_pf_id) \481 (IRO[IRO_YSTORM_ROCE_DCQCN_RECEIVED_STATS].base \482 + ((roce_pf_id) * IRO[IRO_YSTORM_ROCE_DCQCN_RECEIVED_STATS].m1))483#define YSTORM_ROCE_DCQCN_RECEIVED_STATS_SIZE \484 (IRO[IRO_YSTORM_ROCE_DCQCN_RECEIVED_STATS].size)485 486/* RoCE Error Statistics */487#define YSTORM_ROCE_ERROR_STATS_OFFSET(roce_pf_id) \488 (IRO[IRO_YSTORM_ROCE_ERROR_STATS].base \489 + ((roce_pf_id) * IRO[IRO_YSTORM_ROCE_ERROR_STATS].m1))490#define YSTORM_ROCE_ERROR_STATS_SIZE (IRO[IRO_YSTORM_ROCE_ERROR_STATS].size)491 492/* Ystorm cqe producer */493#define YSTORM_TOE_CQ_PROD_OFFSET(rss_id) \494 (IRO[IRO_YSTORM_TOE_CQ_PROD].base \495 + ((rss_id) * IRO[IRO_YSTORM_TOE_CQ_PROD].m1))496#define YSTORM_TOE_CQ_PROD_SIZE (IRO[IRO_YSTORM_TOE_CQ_PROD].size)497 498/* Per-chip offsets in iro_arr in dwords */499#define E4_IRO_ARR_OFFSET 0500#endif501