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1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */2/* QLogic qed NIC Driver3 * Copyright (c) 2015-2017 QLogic Corporation4 * Copyright (c) 2019-2020 Marvell International Ltd.5 */6 7#ifndef REG_ADDR_H8#define REG_ADDR_H9 10#define CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE_SHIFT \11 012 13#define CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE ( \14 0xfff << 0)15 16#define CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE_SHIFT \17 1218 19#define CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE ( \20 0xfff << 12)21 22#define CDU_REG_CID_ADDR_PARAMS_NCIB_SHIFT \23 2424 25#define CDU_REG_CID_ADDR_PARAMS_NCIB ( \26 0xff << 24)27 28#define CDU_REG_SEGMENT0_PARAMS \29 0x580904UL30#define CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK \31 (0xfff << 0)32#define CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK_SHIFT \33 034#define CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE \35 (0xff << 16)36#define CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE_SHIFT \37 1638#define CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE \39 (0xff << 24)40#define CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE_SHIFT \41 2442#define CDU_REG_SEGMENT1_PARAMS \43 0x580908UL44#define CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK \45 (0xfff << 0)46#define CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK_SHIFT \47 048#define CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE \49 (0xff << 16)50#define CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE_SHIFT \51 1652#define CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE \53 (0xff << 24)54#define CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE_SHIFT \55 2456 57#define XSDM_REG_OPERATION_GEN \58 0xf80408UL59#define NIG_REG_RX_BRB_OUT_EN \60 0x500e18UL61#define NIG_REG_STORM_OUT_EN \62 0x500e08UL63#define PSWRQ2_REG_L2P_VALIDATE_VFID \64 0x240c50UL65#define PGLUE_B_REG_USE_CLIENTID_IN_TAG \66 0x2aae04UL67#define PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER \68 0x2aa16cUL69#define PGLUE_B_REG_WAS_ERROR_VF_31_0_CLR \70 0x2aa118UL71#define PSWHST_REG_ZONE_PERMISSION_TABLE \72 0x2a0800UL73#define BAR0_MAP_REG_MSDM_RAM \74 0x1d00000UL75#define BAR0_MAP_REG_USDM_RAM \76 0x1d80000UL77#define BAR0_MAP_REG_PSDM_RAM \78 0x1f00000UL79#define BAR0_MAP_REG_TSDM_RAM \80 0x1c80000UL81#define BAR0_MAP_REG_XSDM_RAM \82 0x1e00000UL83#define BAR0_MAP_REG_YSDM_RAM \84 0x1e80000UL85#define NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF \86 0x5011f4UL87#define PRS_REG_SEARCH_RESP_INITIATOR_TYPE \88 0x1f0164UL89#define PRS_REG_SEARCH_TCP \90 0x1f0400UL91#define PRS_REG_SEARCH_UDP \92 0x1f0404UL93#define PRS_REG_SEARCH_FCOE \94 0x1f0408UL95#define PRS_REG_SEARCH_ROCE \96 0x1f040cUL97#define PRS_REG_SEARCH_OPENFLOW \98 0x1f0434UL99#define PRS_REG_SEARCH_TAG1 \100 0x1f0444UL101#define PRS_REG_SEARCH_TENANT_ID \102 0x1f044cUL103#define PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST \104 0x1f0a0cUL105#define PRS_REG_SEARCH_TCP_FIRST_FRAG \106 0x1f0410UL107#define TM_REG_PF_ENABLE_CONN \108 0x2c043cUL109#define TM_REG_PF_ENABLE_TASK \110 0x2c0444UL111#define TM_REG_PF_SCAN_ACTIVE_CONN \112 0x2c04fcUL113#define TM_REG_PF_SCAN_ACTIVE_TASK \114 0x2c0500UL115#define IGU_REG_LEADING_EDGE_LATCH \116 0x18082cUL117#define IGU_REG_TRAILING_EDGE_LATCH \118 0x180830UL119#define QM_REG_USG_CNT_PF_TX \120 0x2f2eacUL121#define QM_REG_USG_CNT_PF_OTHER \122 0x2f2eb0UL123#define DORQ_REG_PF_DB_ENABLE \124 0x100508UL125#define DORQ_REG_VF_USAGE_CNT \126 0x1009c4UL127#define QM_REG_PF_EN \128 0x2f2ea4UL129#define QM_REG_RLGLBLUPPERBOUND \130 0x2f3c00UL131#define TCFC_REG_WEAK_ENABLE_VF \132 0x2d0704UL133#define TCFC_REG_STRONG_ENABLE_PF \134 0x2d0708UL135#define TCFC_REG_STRONG_ENABLE_VF \136 0x2d070cUL137#define CCFC_REG_WEAK_ENABLE_VF \138 0x2e0704UL139#define CCFC_REG_STRONG_ENABLE_PF \140 0x2e0708UL141#define PGLUE_B_REG_PGL_ADDR_88_F0_BB \142 0x2aa404UL143#define PGLUE_B_REG_PGL_ADDR_8C_F0_BB \144 0x2aa408UL145#define PGLUE_B_REG_PGL_ADDR_90_F0_BB \146 0x2aa40cUL147#define PGLUE_B_REG_PGL_ADDR_94_F0_BB \148 0x2aa410UL149#define PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR \150 0x2aa138UL151#define PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ \152 0x2aa174UL153#define MISC_REG_GEN_PURP_CR0 \154 0x008c80UL155#define MCP_REG_SCRATCH \156 0xe20000UL157#define MCP_REG_SCRATCH_SIZE \158 57344159#define CNIG_REG_NW_PORT_MODE_BB \160 0x218200UL161#define MISCS_REG_CHIP_NUM \162 0x00976cUL163#define MISCS_REG_CHIP_REV \164 0x009770UL165#define MISCS_REG_CMT_ENABLED_FOR_PAIR \166 0x00971cUL167#define MISCS_REG_CHIP_TEST_REG \168 0x009778UL169#define MISCS_REG_CHIP_METAL \170 0x009774UL171#define MISCS_REG_FUNCTION_HIDE \172 0x0096f0UL173#define BRB_REG_HEADER_SIZE \174 0x340804UL175#define BTB_REG_HEADER_SIZE \176 0xdb0804UL177#define CAU_REG_LONG_TIMEOUT_THRESHOLD \178 0x1c0708UL179#define CCFC_REG_ACTIVITY_COUNTER \180 0x2e8800UL181#define CCFC_REG_STRONG_ENABLE_VF \182 0x2e070cUL183#define CDU_REG_CCFC_CTX_VALID0 \184 0x580400UL185#define CDU_REG_CCFC_CTX_VALID1 \186 0x580404UL187#define CDU_REG_TCFC_CTX_VALID0 \188 0x580408UL189#define CDU_REG_CID_ADDR_PARAMS \190 0x580900UL191#define DBG_REG_CLIENT_ENABLE \192 0x010004UL193#define DBG_REG_TIMESTAMP_VALID_EN \194 0x010b58UL195#define DMAE_REG_INIT \196 0x00c000UL197#define DORQ_REG_IFEN \198 0x100040UL199#define DORQ_REG_TAG1_OVRD_MODE \200 0x1008b4UL201#define DORQ_REG_PF_PCP_BB_K2 \202 0x1008c4UL203#define DORQ_REG_PF_EXT_VID_BB_K2 \204 0x1008c8UL205#define DORQ_REG_DB_DROP_REASON \206 0x100a2cUL207#define DORQ_REG_DB_DROP_DETAILS \208 0x100a24UL209#define DORQ_REG_DB_DROP_DETAILS_ADDRESS \210 0x100a1cUL211#define GRC_REG_TIMEOUT_EN \212 0x050404UL213#define GRC_REG_TIMEOUT_ATTN_ACCESS_VALID \214 0x050054UL215#define GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_0 \216 0x05004cUL217#define GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_1 \218 0x050050UL219#define IGU_REG_BLOCK_CONFIGURATION \220 0x180040UL221#define MCM_REG_INIT \222 0x1200000UL223#define MCP2_REG_DBG_DWORD_ENABLE \224 0x052404UL225#define MISC_REG_PORT_MODE \226 0x008c00UL227#define MISCS_REG_CLK_100G_MODE \228 0x009070UL229#define MSDM_REG_ENABLE_IN1 \230 0xfc0004UL231#define MSEM_REG_ENABLE_IN \232 0x1800004UL233#define NIG_REG_CM_HDR \234 0x500840UL235#define NIG_REG_LLH_TAGMAC_DEF_PF_VECTOR \236 0x50196cUL237#define NIG_REG_LLH_PPFID2PFID_TBL_0 \238 0x501970UL239#define NIG_REG_LLH_ENG_CLS_ROCE_QP_SEL \240 0x50241#define NIG_REG_LLH_CLS_TYPE_DUALMODE \242 0x501964UL243#define NIG_REG_LLH_FUNC_TAG_EN 0x5019b0UL244#define NIG_REG_LLH_FUNC_TAG_VALUE 0x5019d0UL245#define NIG_REG_LLH_FUNC_FILTER_VALUE \246 0x501a00UL247#define NIG_REG_LLH_FUNC_FILTER_VALUE_SIZE \248 32249#define NIG_REG_LLH_FUNC_FILTER_EN \250 0x501a80UL251#define NIG_REG_LLH_FUNC_FILTER_EN_SIZE \252 16253#define NIG_REG_LLH_FUNC_FILTER_MODE \254 0x501ac0UL255#define NIG_REG_LLH_FUNC_FILTER_MODE_SIZE \256 16257#define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE \258 0x501b00UL259#define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_SIZE \260 16261#define NIG_REG_LLH_FUNC_FILTER_HDR_SEL \262 0x501b40UL263#define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_SIZE \264 16265#define NCSI_REG_CONFIG \266 0x040200UL267#define PBF_REG_INIT \268 0xd80000UL269#define PBF_REG_NUM_BLOCKS_ALLOCATED_PROD_VOQ0 \270 0xd806c8UL271#define PBF_REG_NUM_BLOCKS_ALLOCATED_CONS_VOQ0 \272 0xd806ccUL273#define PTU_REG_ATC_INIT_ARRAY \274 0x560000UL275#define PCM_REG_INIT \276 0x1100000UL277#define PGLUE_B_REG_ADMIN_PER_PF_REGION \278 0x2a9000UL279#define PGLUE_B_REG_TX_ERR_WR_DETAILS2 \280 0x2aa150UL281#define PGLUE_B_REG_TX_ERR_WR_ADD_31_0 \282 0x2aa144UL283#define PGLUE_B_REG_TX_ERR_WR_ADD_63_32 \284 0x2aa148UL285#define PGLUE_B_REG_TX_ERR_WR_DETAILS \286 0x2aa14cUL287#define PGLUE_B_REG_TX_ERR_RD_ADD_31_0 \288 0x2aa154UL289#define PGLUE_B_REG_TX_ERR_RD_ADD_63_32 \290 0x2aa158UL291#define PGLUE_B_REG_TX_ERR_RD_DETAILS \292 0x2aa15cUL293#define PGLUE_B_REG_TX_ERR_RD_DETAILS2 \294 0x2aa160UL295#define PGLUE_B_REG_TX_ERR_WR_DETAILS_ICPL \296 0x2aa164UL297#define PGLUE_B_REG_MASTER_ZLR_ERR_DETAILS \298 0x2aa54cUL299#define PGLUE_B_REG_MASTER_ZLR_ERR_ADD_31_0 \300 0x2aa544UL301#define PGLUE_B_REG_MASTER_ZLR_ERR_ADD_63_32 \302 0x2aa548UL303#define PGLUE_B_REG_VF_ILT_ERR_ADD_31_0 \304 0x2aae74UL305#define PGLUE_B_REG_VF_ILT_ERR_ADD_63_32 \306 0x2aae78UL307#define PGLUE_B_REG_VF_ILT_ERR_DETAILS \308 0x2aae7cUL309#define PGLUE_B_REG_VF_ILT_ERR_DETAILS2 \310 0x2aae80UL311#define PGLUE_B_REG_LATCHED_ERRORS_CLR \312 0x2aa3bcUL313#define PRM_REG_DISABLE_PRM \314 0x230000UL315#define PRS_REG_SOFT_RST \316 0x1f0000UL317#define PRS_REG_MSG_INFO \318 0x1f0a1cUL319#define PRS_REG_ROCE_DEST_QP_MAX_PF \320 0x1f0430UL321#define PRS_REG_USE_LIGHT_L2 \322 0x1f096cUL323#define PSDM_REG_ENABLE_IN1 \324 0xfa0004UL325#define PSEM_REG_ENABLE_IN \326 0x1600004UL327#define PSWRQ_REG_DBG_SELECT \328 0x280020UL329#define PSWRQ2_REG_CDUT_P_SIZE \330 0x24000cUL331#define PSWRQ2_REG_ILT_MEMORY \332 0x260000UL333#define PSWRQ2_REG_ILT_MEMORY_SIZE_BB \334 15200335#define PSWRQ2_REG_ILT_MEMORY_SIZE_K2 \336 22000337#define PSWHST_REG_DISCARD_INTERNAL_WRITES \338 0x2a0040UL339#define PSWHST2_REG_DBGSYN_ALMOST_FULL_THR \340 0x29e050UL341#define PSWHST_REG_INCORRECT_ACCESS_VALID \342 0x2a0070UL343#define PSWHST_REG_INCORRECT_ACCESS_ADDRESS \344 0x2a0074UL345#define PSWHST_REG_INCORRECT_ACCESS_DATA \346 0x2a0068UL347#define PSWHST_REG_INCORRECT_ACCESS_LENGTH \348 0x2a006cUL349#define PSWRD_REG_DBG_SELECT \350 0x29c040UL351#define PSWRD2_REG_CONF11 \352 0x29d064UL353#define PSWWR_REG_USDM_FULL_TH \354 0x29a040UL355#define PSWWR2_REG_CDU_FULL_TH2 \356 0x29b040UL357#define QM_REG_MAXPQSIZE_0 \358 0x2f0434UL359#define RSS_REG_RSS_INIT_EN \360 0x238804UL361#define RDIF_REG_STOP_ON_ERROR \362 0x300040UL363#define RDIF_REG_DEBUG_ERROR_INFO \364 0x300400UL365#define RDIF_REG_DEBUG_ERROR_INFO_SIZE \366 64367#define SRC_REG_SOFT_RST \368 0x23874cUL369#define TCFC_REG_ACTIVITY_COUNTER \370 0x2d8800UL371#define TCM_REG_INIT \372 0x1180000UL373#define TM_REG_PXP_READ_DATA_FIFO_INIT \374 0x2c0014UL375#define TSDM_REG_ENABLE_IN1 \376 0xfb0004UL377#define TSEM_REG_ENABLE_IN \378 0x1700004UL379#define TDIF_REG_STOP_ON_ERROR \380 0x310040UL381#define TDIF_REG_DEBUG_ERROR_INFO \382 0x310400UL383#define TDIF_REG_DEBUG_ERROR_INFO_SIZE \384 64385#define UCM_REG_INIT \386 0x1280000UL387#define UMAC_REG_IPG_HD_BKP_CNTL_BB_B0 \388 0x051004UL389#define USDM_REG_ENABLE_IN1 \390 0xfd0004UL391#define USEM_REG_ENABLE_IN \392 0x1900004UL393#define XCM_REG_INIT \394 0x1000000UL395#define XSDM_REG_ENABLE_IN1 \396 0xf80004UL397#define XSEM_REG_ENABLE_IN \398 0x1400004UL399#define YCM_REG_INIT \400 0x1080000UL401#define YSDM_REG_ENABLE_IN1 \402 0xf90004UL403#define YSEM_REG_ENABLE_IN \404 0x1500004UL405#define XYLD_REG_SCBD_STRICT_PRIO \406 0x4c0000UL407#define TMLD_REG_SCBD_STRICT_PRIO \408 0x4d0000UL409#define MULD_REG_SCBD_STRICT_PRIO \410 0x4e0000UL411#define YULD_REG_SCBD_STRICT_PRIO \412 0x4c8000UL413#define MISC_REG_SHARED_MEM_ADDR \414 0x008c20UL415#define DMAE_REG_GO_C0 \416 0x00c048UL417#define DMAE_REG_GO_C1 \418 0x00c04cUL419#define DMAE_REG_GO_C2 \420 0x00c050UL421#define DMAE_REG_GO_C3 \422 0x00c054UL423#define DMAE_REG_GO_C4 \424 0x00c058UL425#define DMAE_REG_GO_C5 \426 0x00c05cUL427#define DMAE_REG_GO_C6 \428 0x00c060UL429#define DMAE_REG_GO_C7 \430 0x00c064UL431#define DMAE_REG_GO_C8 \432 0x00c068UL433#define DMAE_REG_GO_C9 \434 0x00c06cUL435#define DMAE_REG_GO_C10 \436 0x00c070UL437#define DMAE_REG_GO_C11 \438 0x00c074UL439#define DMAE_REG_GO_C12 \440 0x00c078UL441#define DMAE_REG_GO_C13 \442 0x00c07cUL443#define DMAE_REG_GO_C14 \444 0x00c080UL445#define DMAE_REG_GO_C15 \446 0x00c084UL447#define DMAE_REG_GO_C16 \448 0x00c088UL449#define DMAE_REG_GO_C17 \450 0x00c08cUL451#define DMAE_REG_GO_C18 \452 0x00c090UL453#define DMAE_REG_GO_C19 \454 0x00c094UL455#define DMAE_REG_GO_C20 \456 0x00c098UL457#define DMAE_REG_GO_C21 \458 0x00c09cUL459#define DMAE_REG_GO_C22 \460 0x00c0a0UL461#define DMAE_REG_GO_C23 \462 0x00c0a4UL463#define DMAE_REG_GO_C24 \464 0x00c0a8UL465#define DMAE_REG_GO_C25 \466 0x00c0acUL467#define DMAE_REG_GO_C26 \468 0x00c0b0UL469#define DMAE_REG_GO_C27 \470 0x00c0b4UL471#define DMAE_REG_GO_C28 \472 0x00c0b8UL473#define DMAE_REG_GO_C29 \474 0x00c0bcUL475#define DMAE_REG_GO_C30 \476 0x00c0c0UL477#define DMAE_REG_GO_C31 \478 0x00c0c4UL479#define DMAE_REG_CMD_MEM \480 0x00c800UL481#define QM_REG_MAXPQSIZETXSEL_0 \482 0x2f0440UL483#define QM_REG_SDMCMDREADY \484 0x2f1e10UL485#define QM_REG_SDMCMDADDR \486 0x2f1e04UL487#define QM_REG_SDMCMDDATALSB \488 0x2f1e08UL489#define QM_REG_SDMCMDDATAMSB \490 0x2f1e0cUL491#define QM_REG_SDMCMDGO \492 0x2f1e14UL493#define QM_REG_RLPFCRD \494 0x2f4d80UL495#define QM_REG_RLPFINCVAL \496 0x2f4c80UL497#define QM_REG_RLGLBLCRD \498 0x2f4400UL499#define QM_REG_RLGLBLINCVAL \500 0x2f3400UL501#define IGU_REG_ATTENTION_ENABLE \502 0x18083cUL503#define IGU_REG_ATTN_MSG_ADDR_L \504 0x180820UL505#define IGU_REG_ATTN_MSG_ADDR_H \506 0x180824UL507#define MISC_REG_AEU_GENERAL_ATTN_0 \508 0x008400UL509#define MISC_REG_AEU_GENERAL_ATTN_32 \510 0x008480UL511#define MISC_REG_AEU_GENERAL_ATTN_35 \512 0x00848cUL513#define CAU_REG_SB_ADDR_MEMORY \514 0x1c8000UL515#define CAU_REG_SB_VAR_MEMORY \516 0x1c6000UL517#define CAU_REG_PI_MEMORY \518 0x1d0000UL519#define IGU_REG_PF_CONFIGURATION \520 0x180800UL521#define IGU_REG_VF_CONFIGURATION \522 0x180804UL523#define MISC_REG_AEU_ENABLE1_IGU_OUT_0 \524 0x00849cUL525#define MISC_REG_AEU_ENABLE4_IGU_OUT_0 \526 0x0084a8UL527#define MISC_REG_AEU_ENABLE4_IGU_OUT_0_GENERAL_ATTN32 \528 (0x1UL << 0)529#define MISC_REG_AEU_ENABLE4_IGU_OUT_0_GENERAL_ATTN32_SHIFT \530 0531#define MISC_REG_AEU_AFTER_INVERT_1_IGU \532 0x0087b4UL533#define MISC_REG_AEU_MASK_ATTN_IGU \534 0x008494UL535#define IGU_REG_CLEANUP_STATUS_0 \536 0x180980UL537#define IGU_REG_CLEANUP_STATUS_1 \538 0x180a00UL539#define IGU_REG_CLEANUP_STATUS_2 \540 0x180a80UL541#define IGU_REG_CLEANUP_STATUS_3 \542 0x180b00UL543#define IGU_REG_CLEANUP_STATUS_4 \544 0x180b80UL545#define IGU_REG_COMMAND_REG_32LSB_DATA \546 0x180840UL547#define IGU_REG_COMMAND_REG_CTRL \548 0x180848UL549#define IGU_REG_BLOCK_CONFIGURATION_VF_CLEANUP_EN ( \550 0x1 << 1)551#define IGU_REG_BLOCK_CONFIGURATION_PXP_TPH_INTERFACE_EN ( \552 0x1 << 0)553#define IGU_REG_PRODUCER_MEMORY 0x182000UL554#define IGU_REG_CONSUMER_MEM 0x183000UL555#define IGU_REG_MAPPING_MEMORY \556 0x184000UL557#define IGU_REG_STATISTIC_NUM_VF_MSG_SENT \558 0x180408UL559#define IGU_REG_WRITE_DONE_PENDING \560 0x180900UL561#define MISCS_REG_GENERIC_POR_0 \562 0x0096d4UL563#define MCP_REG_NVM_CFG4 \564 0xe0642cUL565#define MCP_REG_NVM_CFG4_FLASH_SIZE ( \566 0x7 << 0)567#define MCP_REG_NVM_CFG4_FLASH_SIZE_SHIFT \568 0569#define MCP_REG_CPU_STATE \570 0xe05004UL571#define MCP_REG_CPU_STATE_SOFT_HALTED (0x1UL << 10)572#define MCP_REG_CPU_EVENT_MASK \573 0xe05008UL574#define MCP_REG_CPU_PROGRAM_COUNTER 0xe0501cUL575#define PGLUE_B_REG_PF_BAR0_SIZE \576 0x2aae60UL577#define PGLUE_B_REG_PF_BAR1_SIZE \578 0x2aae64UL579#define PGLUE_B_REG_VF_BAR1_SIZE 0x2aae68UL580#define PRS_REG_ENCAPSULATION_TYPE_EN 0x1f0730UL581#define PRS_REG_GRE_PROTOCOL 0x1f0734UL582#define PRS_REG_VXLAN_PORT 0x1f0738UL583#define PRS_REG_OUTPUT_FORMAT_4_0 0x1f099cUL584#define NIG_REG_ENC_TYPE_ENABLE 0x501058UL585 586#define NIG_REG_ENC_TYPE_ENABLE_ETH_OVER_GRE_ENABLE (0x1 << 0)587#define NIG_REG_ENC_TYPE_ENABLE_ETH_OVER_GRE_ENABLE_SHIFT 0588#define NIG_REG_ENC_TYPE_ENABLE_IP_OVER_GRE_ENABLE (0x1 << 1)589#define NIG_REG_ENC_TYPE_ENABLE_IP_OVER_GRE_ENABLE_SHIFT 1590#define NIG_REG_ENC_TYPE_ENABLE_VXLAN_ENABLE (0x1 << 2)591#define NIG_REG_ENC_TYPE_ENABLE_VXLAN_ENABLE_SHIFT 2592 593#define NIG_REG_VXLAN_CTRL 0x50105cUL594#define PBF_REG_VXLAN_PORT 0xd80518UL595#define PBF_REG_NGE_PORT 0xd8051cUL596#define PRS_REG_NGE_PORT 0x1f086cUL597#define NIG_REG_NGE_PORT 0x508b38UL598 599#define DORQ_REG_L2_EDPM_TUNNEL_GRE_ETH_EN 0x10090cUL600#define DORQ_REG_L2_EDPM_TUNNEL_GRE_IP_EN 0x100910UL601#define DORQ_REG_L2_EDPM_TUNNEL_VXLAN_EN 0x100914UL602#define DORQ_REG_L2_EDPM_TUNNEL_NGE_IP_EN_K2 0x10092cUL603#define DORQ_REG_L2_EDPM_TUNNEL_NGE_ETH_EN_K2 0x100930UL604 605#define NIG_REG_NGE_IP_ENABLE 0x508b28UL606#define NIG_REG_NGE_ETH_ENABLE 0x508b2cUL607#define NIG_REG_NGE_COMP_VER 0x508b30UL608#define PBF_REG_NGE_COMP_VER 0xd80524UL609#define PRS_REG_NGE_COMP_VER 0x1f0878UL610 611#define QM_REG_WFQPFWEIGHT 0x2f4e80UL612#define QM_REG_WFQVPWEIGHT 0x2fa000UL613#define QM_REG_WFQVPUPPERBOUND \614 0x2fb000UL615#define QM_REG_WFQVPCRD \616 0x2fc000UL617#define PGLCS_REG_DBG_SELECT_K2_E5 \618 0x001d14UL619#define PGLCS_REG_DBG_DWORD_ENABLE_K2_E5 \620 0x001d18UL621#define PGLCS_REG_DBG_SHIFT_K2_E5 \622 0x001d1cUL623#define PGLCS_REG_DBG_FORCE_VALID_K2_E5 \624 0x001d20UL625#define PGLCS_REG_DBG_FORCE_FRAME_K2_E5 \626 0x001d24UL627#define MISC_REG_RESET_PL_PDA_VMAIN_1 \628 0x008070UL629#define MISC_REG_RESET_PL_PDA_VMAIN_2 \630 0x008080UL631#define MISC_REG_RESET_PL_PDA_VAUX \632 0x008090UL633#define MISCS_REG_RESET_PL_UA \634 0x009050UL635#define MISCS_REG_RESET_PL_HV \636 0x009060UL637#define MISCS_REG_RESET_PL_HV_2_K2_E5 \638 0x009150UL639#define DMAE_REG_DBG_SELECT \640 0x00c510UL641#define DMAE_REG_DBG_DWORD_ENABLE \642 0x00c514UL643#define DMAE_REG_DBG_SHIFT \644 0x00c518UL645#define DMAE_REG_DBG_FORCE_VALID \646 0x00c51cUL647#define DMAE_REG_DBG_FORCE_FRAME \648 0x00c520UL649#define NCSI_REG_DBG_SELECT \650 0x040474UL651#define NCSI_REG_DBG_DWORD_ENABLE \652 0x040478UL653#define NCSI_REG_DBG_SHIFT \654 0x04047cUL655#define NCSI_REG_DBG_FORCE_VALID \656 0x040480UL657#define NCSI_REG_DBG_FORCE_FRAME \658 0x040484UL659#define GRC_REG_DBG_SELECT \660 0x0500a4UL661#define GRC_REG_DBG_DWORD_ENABLE \662 0x0500a8UL663#define GRC_REG_DBG_SHIFT \664 0x0500acUL665#define GRC_REG_DBG_FORCE_VALID \666 0x0500b0UL667#define GRC_REG_DBG_FORCE_FRAME \668 0x0500b4UL669#define UMAC_REG_DBG_SELECT_K2_E5 \670 0x051094UL671#define UMAC_REG_DBG_DWORD_ENABLE_K2_E5 \672 0x051098UL673#define UMAC_REG_DBG_SHIFT_K2_E5 \674 0x05109cUL675#define UMAC_REG_DBG_FORCE_VALID_K2_E5 \676 0x0510a0UL677#define UMAC_REG_DBG_FORCE_FRAME_K2_E5 \678 0x0510a4UL679#define MCP2_REG_DBG_SELECT \680 0x052400UL681#define MCP2_REG_DBG_DWORD_ENABLE \682 0x052404UL683#define MCP2_REG_DBG_SHIFT \684 0x052408UL685#define MCP2_REG_DBG_FORCE_VALID \686 0x052440UL687#define MCP2_REG_DBG_FORCE_FRAME \688 0x052444UL689#define PCIE_REG_DBG_SELECT \690 0x0547e8UL691#define PCIE_REG_DBG_DWORD_ENABLE \692 0x0547ecUL693#define PCIE_REG_DBG_SHIFT \694 0x0547f0UL695#define PCIE_REG_DBG_FORCE_VALID \696 0x0547f4UL697#define PCIE_REG_DBG_FORCE_FRAME \698 0x0547f8UL699#define DORQ_REG_DBG_SELECT \700 0x100ad0UL701#define DORQ_REG_DBG_DWORD_ENABLE \702 0x100ad4UL703#define DORQ_REG_DBG_SHIFT \704 0x100ad8UL705#define DORQ_REG_DBG_FORCE_VALID \706 0x100adcUL707#define DORQ_REG_DBG_FORCE_FRAME \708 0x100ae0UL709#define IGU_REG_DBG_SELECT \710 0x181578UL711#define IGU_REG_DBG_DWORD_ENABLE \712 0x18157cUL713#define IGU_REG_DBG_SHIFT \714 0x181580UL715#define IGU_REG_DBG_FORCE_VALID \716 0x181584UL717#define IGU_REG_DBG_FORCE_FRAME \718 0x181588UL719#define CAU_REG_DBG_SELECT \720 0x1c0ea8UL721#define CAU_REG_DBG_DWORD_ENABLE \722 0x1c0eacUL723#define CAU_REG_DBG_SHIFT \724 0x1c0eb0UL725#define CAU_REG_DBG_FORCE_VALID \726 0x1c0eb4UL727#define CAU_REG_DBG_FORCE_FRAME \728 0x1c0eb8UL729#define PRS_REG_DBG_SELECT \730 0x1f0b6cUL731#define PRS_REG_DBG_DWORD_ENABLE \732 0x1f0b70UL733#define PRS_REG_DBG_SHIFT \734 0x1f0b74UL735#define PRS_REG_DBG_FORCE_VALID \736 0x1f0ba0UL737#define PRS_REG_DBG_FORCE_FRAME \738 0x1f0ba4UL739#define CNIG_REG_DBG_SELECT_K2_E5 \740 0x218254UL741#define CNIG_REG_DBG_DWORD_ENABLE_K2_E5 \742 0x218258UL743#define CNIG_REG_DBG_SHIFT_K2_E5 \744 0x21825cUL745#define CNIG_REG_DBG_FORCE_VALID_K2_E5 \746 0x218260UL747#define CNIG_REG_DBG_FORCE_FRAME_K2_E5 \748 0x218264UL749#define PRM_REG_DBG_SELECT \750 0x2306a8UL751#define PRM_REG_DBG_DWORD_ENABLE \752 0x2306acUL753#define PRM_REG_DBG_SHIFT \754 0x2306b0UL755#define PRM_REG_DBG_FORCE_VALID \756 0x2306b4UL757#define PRM_REG_DBG_FORCE_FRAME \758 0x2306b8UL759#define SRC_REG_DBG_SELECT \760 0x238700UL761#define SRC_REG_DBG_DWORD_ENABLE \762 0x238704UL763#define SRC_REG_DBG_SHIFT \764 0x238708UL765#define SRC_REG_DBG_FORCE_VALID \766 0x23870cUL767#define SRC_REG_DBG_FORCE_FRAME \768 0x238710UL769#define RSS_REG_DBG_SELECT \770 0x238c4cUL771#define RSS_REG_DBG_DWORD_ENABLE \772 0x238c50UL773#define RSS_REG_DBG_SHIFT \774 0x238c54UL775#define RSS_REG_DBG_FORCE_VALID \776 0x238c58UL777#define RSS_REG_DBG_FORCE_FRAME \778 0x238c5cUL779#define RPB_REG_DBG_SELECT \780 0x23c728UL781#define RPB_REG_DBG_DWORD_ENABLE \782 0x23c72cUL783#define RPB_REG_DBG_SHIFT \784 0x23c730UL785#define RPB_REG_DBG_FORCE_VALID \786 0x23c734UL787#define RPB_REG_DBG_FORCE_FRAME \788 0x23c738UL789#define PSWRQ2_REG_DBG_SELECT \790 0x240100UL791#define PSWRQ2_REG_DBG_DWORD_ENABLE \792 0x240104UL793#define PSWRQ2_REG_DBG_SHIFT \794 0x240108UL795#define PSWRQ2_REG_DBG_FORCE_VALID \796 0x24010cUL797#define PSWRQ2_REG_DBG_FORCE_FRAME \798 0x240110UL799#define PSWRQ_REG_DBG_SELECT \800 0x280020UL801#define PSWRQ_REG_DBG_DWORD_ENABLE \802 0x280024UL803#define PSWRQ_REG_DBG_SHIFT \804 0x280028UL805#define PSWRQ_REG_DBG_FORCE_VALID \806 0x28002cUL807#define PSWRQ_REG_DBG_FORCE_FRAME \808 0x280030UL809#define PSWWR_REG_DBG_SELECT \810 0x29a084UL811#define PSWWR_REG_DBG_DWORD_ENABLE \812 0x29a088UL813#define PSWWR_REG_DBG_SHIFT \814 0x29a08cUL815#define PSWWR_REG_DBG_FORCE_VALID \816 0x29a090UL817#define PSWWR_REG_DBG_FORCE_FRAME \818 0x29a094UL819#define PSWRD_REG_DBG_SELECT \820 0x29c040UL821#define PSWRD_REG_DBG_DWORD_ENABLE \822 0x29c044UL823#define PSWRD_REG_DBG_SHIFT \824 0x29c048UL825#define PSWRD_REG_DBG_FORCE_VALID \826 0x29c04cUL827#define PSWRD_REG_DBG_FORCE_FRAME \828 0x29c050UL829#define PSWRD2_REG_DBG_SELECT \830 0x29d400UL831#define PSWRD2_REG_DBG_DWORD_ENABLE \832 0x29d404UL833#define PSWRD2_REG_DBG_SHIFT \834 0x29d408UL835#define PSWRD2_REG_DBG_FORCE_VALID \836 0x29d40cUL837#define PSWRD2_REG_DBG_FORCE_FRAME \838 0x29d410UL839#define PSWHST2_REG_DBG_SELECT \840 0x29e058UL841#define PSWHST2_REG_DBG_DWORD_ENABLE \842 0x29e05cUL843#define PSWHST2_REG_DBG_SHIFT \844 0x29e060UL845#define PSWHST2_REG_DBG_FORCE_VALID \846 0x29e064UL847#define PSWHST2_REG_DBG_FORCE_FRAME \848 0x29e068UL849#define PSWHST_REG_DBG_SELECT \850 0x2a0100UL851#define PSWHST_REG_DBG_DWORD_ENABLE \852 0x2a0104UL853#define PSWHST_REG_DBG_SHIFT \854 0x2a0108UL855#define PSWHST_REG_DBG_FORCE_VALID \856 0x2a010cUL857#define PSWHST_REG_DBG_FORCE_FRAME \858 0x2a0110UL859#define PGLUE_B_REG_DBG_SELECT \860 0x2a8400UL861#define PGLUE_B_REG_DBG_DWORD_ENABLE \862 0x2a8404UL863#define PGLUE_B_REG_DBG_SHIFT \864 0x2a8408UL865#define PGLUE_B_REG_DBG_FORCE_VALID \866 0x2a840cUL867#define PGLUE_B_REG_DBG_FORCE_FRAME \868 0x2a8410UL869#define TM_REG_DBG_SELECT \870 0x2c07a8UL871#define TM_REG_DBG_DWORD_ENABLE \872 0x2c07acUL873#define TM_REG_DBG_SHIFT \874 0x2c07b0UL875#define TM_REG_DBG_FORCE_VALID \876 0x2c07b4UL877#define TM_REG_DBG_FORCE_FRAME \878 0x2c07b8UL879#define TCFC_REG_DBG_SELECT \880 0x2d0500UL881#define TCFC_REG_DBG_DWORD_ENABLE \882 0x2d0504UL883#define TCFC_REG_DBG_SHIFT \884 0x2d0508UL885#define TCFC_REG_DBG_FORCE_VALID \886 0x2d050cUL887#define TCFC_REG_DBG_FORCE_FRAME \888 0x2d0510UL889#define CCFC_REG_DBG_SELECT \890 0x2e0500UL891#define CCFC_REG_DBG_DWORD_ENABLE \892 0x2e0504UL893#define CCFC_REG_DBG_SHIFT \894 0x2e0508UL895#define CCFC_REG_DBG_FORCE_VALID \896 0x2e050cUL897#define CCFC_REG_DBG_FORCE_FRAME \898 0x2e0510UL899#define QM_REG_DBG_SELECT \900 0x2f2e74UL901#define QM_REG_DBG_DWORD_ENABLE \902 0x2f2e78UL903#define QM_REG_DBG_SHIFT \904 0x2f2e7cUL905#define QM_REG_DBG_FORCE_VALID \906 0x2f2e80UL907#define QM_REG_DBG_FORCE_FRAME \908 0x2f2e84UL909#define RDIF_REG_DBG_SELECT \910 0x300500UL911#define RDIF_REG_DBG_DWORD_ENABLE \912 0x300504UL913#define RDIF_REG_DBG_SHIFT \914 0x300508UL915#define RDIF_REG_DBG_FORCE_VALID \916 0x30050cUL917#define RDIF_REG_DBG_FORCE_FRAME \918 0x300510UL919#define TDIF_REG_DBG_SELECT \920 0x310500UL921#define TDIF_REG_DBG_DWORD_ENABLE \922 0x310504UL923#define TDIF_REG_DBG_SHIFT \924 0x310508UL925#define TDIF_REG_DBG_FORCE_VALID \926 0x31050cUL927#define TDIF_REG_DBG_FORCE_FRAME \928 0x310510UL929#define BRB_REG_DBG_SELECT \930 0x340ed0UL931#define BRB_REG_DBG_DWORD_ENABLE \932 0x340ed4UL933#define BRB_REG_DBG_SHIFT \934 0x340ed8UL935#define BRB_REG_DBG_FORCE_VALID \936 0x340edcUL937#define BRB_REG_DBG_FORCE_FRAME \938 0x340ee0UL939#define XYLD_REG_DBG_SELECT \940 0x4c1600UL941#define XYLD_REG_DBG_DWORD_ENABLE \942 0x4c1604UL943#define XYLD_REG_DBG_SHIFT \944 0x4c1608UL945#define XYLD_REG_DBG_FORCE_VALID \946 0x4c160cUL947#define XYLD_REG_DBG_FORCE_FRAME \948 0x4c1610UL949#define YULD_REG_DBG_SELECT_BB_K2 \950 0x4c9600UL951#define YULD_REG_DBG_DWORD_ENABLE_BB_K2 \952 0x4c9604UL953#define YULD_REG_DBG_SHIFT_BB_K2 \954 0x4c9608UL955#define YULD_REG_DBG_FORCE_VALID_BB_K2 \956 0x4c960cUL957#define YULD_REG_DBG_FORCE_FRAME_BB_K2 \958 0x4c9610UL959#define TMLD_REG_DBG_SELECT \960 0x4d1600UL961#define TMLD_REG_DBG_DWORD_ENABLE \962 0x4d1604UL963#define TMLD_REG_DBG_SHIFT \964 0x4d1608UL965#define TMLD_REG_DBG_FORCE_VALID \966 0x4d160cUL967#define TMLD_REG_DBG_FORCE_FRAME \968 0x4d1610UL969#define MULD_REG_DBG_SELECT \970 0x4e1600UL971#define MULD_REG_DBG_DWORD_ENABLE \972 0x4e1604UL973#define MULD_REG_DBG_SHIFT \974 0x4e1608UL975#define MULD_REG_DBG_FORCE_VALID \976 0x4e160cUL977#define MULD_REG_DBG_FORCE_FRAME \978 0x4e1610UL979#define NIG_REG_DBG_SELECT \980 0x502140UL981#define NIG_REG_DBG_DWORD_ENABLE \982 0x502144UL983#define NIG_REG_DBG_SHIFT \984 0x502148UL985#define NIG_REG_DBG_FORCE_VALID \986 0x50214cUL987#define NIG_REG_DBG_FORCE_FRAME \988 0x502150UL989#define BMB_REG_DBG_SELECT \990 0x540a7cUL991#define BMB_REG_DBG_DWORD_ENABLE \992 0x540a80UL993#define BMB_REG_DBG_SHIFT \994 0x540a84UL995#define BMB_REG_DBG_FORCE_VALID \996 0x540a88UL997#define BMB_REG_DBG_FORCE_FRAME \998 0x540a8cUL999#define PTU_REG_DBG_SELECT \1000 0x560100UL1001#define PTU_REG_DBG_DWORD_ENABLE \1002 0x560104UL1003#define PTU_REG_DBG_SHIFT \1004 0x560108UL1005#define PTU_REG_DBG_FORCE_VALID \1006 0x56010cUL1007#define PTU_REG_DBG_FORCE_FRAME \1008 0x560110UL1009#define CDU_REG_DBG_SELECT \1010 0x580704UL1011#define CDU_REG_DBG_DWORD_ENABLE \1012 0x580708UL1013#define CDU_REG_DBG_SHIFT \1014 0x58070cUL1015#define CDU_REG_DBG_FORCE_VALID \1016 0x580710UL1017#define CDU_REG_DBG_FORCE_FRAME \1018 0x580714UL1019#define WOL_REG_DBG_SELECT_K2_E5 \1020 0x600140UL1021#define WOL_REG_DBG_DWORD_ENABLE_K2_E5 \1022 0x600144UL1023#define WOL_REG_DBG_SHIFT_K2_E5 \1024 0x600148UL1025#define WOL_REG_DBG_FORCE_VALID_K2_E5 \1026 0x60014cUL1027#define WOL_REG_DBG_FORCE_FRAME_K2_E5 \1028 0x600150UL1029#define BMBN_REG_DBG_SELECT_K2_E5 \1030 0x610140UL1031#define BMBN_REG_DBG_DWORD_ENABLE_K2_E5 \1032 0x610144UL1033#define BMBN_REG_DBG_SHIFT_K2_E5 \1034 0x610148UL1035#define BMBN_REG_DBG_FORCE_VALID_K2_E5 \1036 0x61014cUL1037#define BMBN_REG_DBG_FORCE_FRAME_K2_E5 \1038 0x610150UL1039#define NWM_REG_DBG_SELECT_K2_E5 \1040 0x8000ecUL1041#define NWM_REG_DBG_DWORD_ENABLE_K2_E5 \1042 0x8000f0UL1043#define NWM_REG_DBG_SHIFT_K2_E5 \1044 0x8000f4UL1045#define NWM_REG_DBG_FORCE_VALID_K2_E5 \1046 0x8000f8UL1047#define NWM_REG_DBG_FORCE_FRAME_K2_E5 \1048 0x8000fcUL1049#define PBF_REG_DBG_SELECT \1050 0xd80060UL1051#define PBF_REG_DBG_DWORD_ENABLE \1052 0xd80064UL1053#define PBF_REG_DBG_SHIFT \1054 0xd80068UL1055#define PBF_REG_DBG_FORCE_VALID \1056 0xd8006cUL1057#define PBF_REG_DBG_FORCE_FRAME \1058 0xd80070UL1059#define PBF_PB1_REG_DBG_SELECT \1060 0xda0728UL1061#define PBF_PB1_REG_DBG_DWORD_ENABLE \1062 0xda072cUL1063#define PBF_PB1_REG_DBG_SHIFT \1064 0xda0730UL1065#define PBF_PB1_REG_DBG_FORCE_VALID \1066 0xda0734UL1067#define PBF_PB1_REG_DBG_FORCE_FRAME \1068 0xda0738UL1069#define PBF_PB2_REG_DBG_SELECT \1070 0xda4728UL1071#define PBF_PB2_REG_DBG_DWORD_ENABLE \1072 0xda472cUL1073#define PBF_PB2_REG_DBG_SHIFT \1074 0xda4730UL1075#define PBF_PB2_REG_DBG_FORCE_VALID \1076 0xda4734UL1077#define PBF_PB2_REG_DBG_FORCE_FRAME \1078 0xda4738UL1079#define BTB_REG_DBG_SELECT \1080 0xdb08c8UL1081#define BTB_REG_DBG_DWORD_ENABLE \1082 0xdb08ccUL1083#define BTB_REG_DBG_SHIFT \1084 0xdb08d0UL1085#define BTB_REG_DBG_FORCE_VALID \1086 0xdb08d4UL1087#define BTB_REG_DBG_FORCE_FRAME \1088 0xdb08d8UL1089#define XSDM_REG_DBG_SELECT \1090 0xf80e28UL1091#define XSDM_REG_DBG_DWORD_ENABLE \1092 0xf80e2cUL1093#define XSDM_REG_DBG_SHIFT \1094 0xf80e30UL1095#define XSDM_REG_DBG_FORCE_VALID \1096 0xf80e34UL1097#define XSDM_REG_DBG_FORCE_FRAME \1098 0xf80e38UL1099#define YSDM_REG_DBG_SELECT \1100 0xf90e28UL1101#define YSDM_REG_DBG_DWORD_ENABLE \1102 0xf90e2cUL1103#define YSDM_REG_DBG_SHIFT \1104 0xf90e30UL1105#define YSDM_REG_DBG_FORCE_VALID \1106 0xf90e34UL1107#define YSDM_REG_DBG_FORCE_FRAME \1108 0xf90e38UL1109#define PSDM_REG_DBG_SELECT \1110 0xfa0e28UL1111#define PSDM_REG_DBG_DWORD_ENABLE \1112 0xfa0e2cUL1113#define PSDM_REG_DBG_SHIFT \1114 0xfa0e30UL1115#define PSDM_REG_DBG_FORCE_VALID \1116 0xfa0e34UL1117#define PSDM_REG_DBG_FORCE_FRAME \1118 0xfa0e38UL1119#define TSDM_REG_DBG_SELECT \1120 0xfb0e28UL1121#define TSDM_REG_DBG_DWORD_ENABLE \1122 0xfb0e2cUL1123#define TSDM_REG_DBG_SHIFT \1124 0xfb0e30UL1125#define TSDM_REG_DBG_FORCE_VALID \1126 0xfb0e34UL1127#define TSDM_REG_DBG_FORCE_FRAME \1128 0xfb0e38UL1129#define MSDM_REG_DBG_SELECT \1130 0xfc0e28UL1131#define MSDM_REG_DBG_DWORD_ENABLE \1132 0xfc0e2cUL1133#define MSDM_REG_DBG_SHIFT \1134 0xfc0e30UL1135#define MSDM_REG_DBG_FORCE_VALID \1136 0xfc0e34UL1137#define MSDM_REG_DBG_FORCE_FRAME \1138 0xfc0e38UL1139#define USDM_REG_DBG_SELECT \1140 0xfd0e28UL1141#define USDM_REG_DBG_DWORD_ENABLE \1142 0xfd0e2cUL1143#define USDM_REG_DBG_SHIFT \1144 0xfd0e30UL1145#define USDM_REG_DBG_FORCE_VALID \1146 0xfd0e34UL1147#define USDM_REG_DBG_FORCE_FRAME \1148 0xfd0e38UL1149#define XCM_REG_DBG_SELECT \1150 0x1000040UL1151#define XCM_REG_DBG_DWORD_ENABLE \1152 0x1000044UL1153#define XCM_REG_DBG_SHIFT \1154 0x1000048UL1155#define XCM_REG_DBG_FORCE_VALID \1156 0x100004cUL1157#define XCM_REG_DBG_FORCE_FRAME \1158 0x1000050UL1159#define YCM_REG_DBG_SELECT \1160 0x1080040UL1161#define YCM_REG_DBG_DWORD_ENABLE \1162 0x1080044UL1163#define YCM_REG_DBG_SHIFT \1164 0x1080048UL1165#define YCM_REG_DBG_FORCE_VALID \1166 0x108004cUL1167#define YCM_REG_DBG_FORCE_FRAME \1168 0x1080050UL1169#define PCM_REG_DBG_SELECT \1170 0x1100040UL1171#define PCM_REG_DBG_DWORD_ENABLE \1172 0x1100044UL1173#define PCM_REG_DBG_SHIFT \1174 0x1100048UL1175#define PCM_REG_DBG_FORCE_VALID \1176 0x110004cUL1177#define PCM_REG_DBG_FORCE_FRAME \1178 0x1100050UL1179#define TCM_REG_DBG_SELECT \1180 0x1180040UL1181#define TCM_REG_DBG_DWORD_ENABLE \1182 0x1180044UL1183#define TCM_REG_DBG_SHIFT \1184 0x1180048UL1185#define TCM_REG_DBG_FORCE_VALID \1186 0x118004cUL1187#define TCM_REG_DBG_FORCE_FRAME \1188 0x1180050UL1189#define MCM_REG_DBG_SELECT \1190 0x1200040UL1191#define MCM_REG_DBG_DWORD_ENABLE \1192 0x1200044UL1193#define MCM_REG_DBG_SHIFT \1194 0x1200048UL1195#define MCM_REG_DBG_FORCE_VALID \1196 0x120004cUL1197#define MCM_REG_DBG_FORCE_FRAME \1198 0x1200050UL1199#define UCM_REG_DBG_SELECT \1200 0x1280050UL1201#define UCM_REG_DBG_DWORD_ENABLE \1202 0x1280054UL1203#define UCM_REG_DBG_SHIFT \1204 0x1280058UL1205#define UCM_REG_DBG_FORCE_VALID \1206 0x128005cUL1207#define UCM_REG_DBG_FORCE_FRAME \1208 0x1280060UL1209#define XSEM_REG_DBG_SELECT \1210 0x1401528UL1211#define XSEM_REG_DBG_DWORD_ENABLE \1212 0x140152cUL1213#define XSEM_REG_DBG_SHIFT \1214 0x1401530UL1215#define XSEM_REG_DBG_FORCE_VALID \1216 0x1401534UL1217#define XSEM_REG_DBG_FORCE_FRAME \1218 0x1401538UL1219#define YSEM_REG_DBG_SELECT \1220 0x1501528UL1221#define YSEM_REG_DBG_DWORD_ENABLE \1222 0x150152cUL1223#define YSEM_REG_DBG_SHIFT \1224 0x1501530UL1225#define YSEM_REG_DBG_FORCE_VALID \1226 0x1501534UL1227#define YSEM_REG_DBG_FORCE_FRAME \1228 0x1501538UL1229#define PSEM_REG_DBG_SELECT \1230 0x1601528UL1231#define PSEM_REG_DBG_DWORD_ENABLE \1232 0x160152cUL1233#define PSEM_REG_DBG_SHIFT \1234 0x1601530UL1235#define PSEM_REG_DBG_FORCE_VALID \1236 0x1601534UL1237#define PSEM_REG_DBG_FORCE_FRAME \1238 0x1601538UL1239#define TSEM_REG_DBG_SELECT \1240 0x1701528UL1241#define TSEM_REG_DBG_DWORD_ENABLE \1242 0x170152cUL1243#define TSEM_REG_DBG_SHIFT \1244 0x1701530UL1245#define TSEM_REG_DBG_FORCE_VALID \1246 0x1701534UL1247#define TSEM_REG_DBG_FORCE_FRAME \1248 0x1701538UL1249#define DORQ_REG_PF_USAGE_CNT \1250 0x1009c0UL1251#define DORQ_REG_PF_OVFL_STICKY \1252 0x1009d0UL1253#define DORQ_REG_DPM_FORCE_ABORT \1254 0x1009d8UL1255#define DORQ_REG_INT_STS \1256 0x100180UL1257#define DORQ_REG_INT_STS_ADDRESS_ERROR \1258 (0x1UL << 0)1259#define DORQ_REG_INT_STS_WR \1260 0x100188UL1261#define DORQ_REG_DB_DROP_DETAILS_REL \1262 0x100a28UL1263#define DORQ_REG_INT_STS_ADDRESS_ERROR_SHIFT \1264 01265#define DORQ_REG_INT_STS_DB_DROP \1266 (0x1UL << 1)1267#define DORQ_REG_INT_STS_DB_DROP_SHIFT \1268 11269#define DORQ_REG_INT_STS_DORQ_FIFO_OVFL_ERR \1270 (0x1UL << 2)1271#define DORQ_REG_INT_STS_DORQ_FIFO_OVFL_ERR_SHIFT \1272 21273#define DORQ_REG_INT_STS_DORQ_FIFO_AFULL\1274 (0x1UL << 3)1275#define DORQ_REG_INT_STS_DORQ_FIFO_AFULL_SHIFT \1276 31277#define DORQ_REG_INT_STS_CFC_BYP_VALIDATION_ERR \1278 (0x1UL << 4)1279#define DORQ_REG_INT_STS_CFC_BYP_VALIDATION_ERR_SHIFT \1280 41281#define DORQ_REG_INT_STS_CFC_LD_RESP_ERR \1282 (0x1UL << 5)1283#define DORQ_REG_INT_STS_CFC_LD_RESP_ERR_SHIFT \1284 51285#define DORQ_REG_INT_STS_XCM_DONE_CNT_ERR \1286 (0x1UL << 6)1287#define DORQ_REG_INT_STS_XCM_DONE_CNT_ERR_SHIFT \1288 61289#define DORQ_REG_INT_STS_CFC_LD_REQ_FIFO_OVFL_ERR \1290 (0x1UL << 7)1291#define DORQ_REG_INT_STS_CFC_LD_REQ_FIFO_OVFL_ERR_SHIFT \1292 71293#define DORQ_REG_INT_STS_CFC_LD_REQ_FIFO_UNDER_ERR \1294 (0x1UL << 8)1295#define DORQ_REG_INT_STS_CFC_LD_REQ_FIFO_UNDER_ERR_SHIFT \1296 81297#define DORQ_REG_DB_DROP_DETAILS_REASON \1298 0x100a20UL1299#define MSEM_REG_DBG_SELECT \1300 0x1801528UL1301#define MSEM_REG_DBG_DWORD_ENABLE \1302 0x180152cUL1303#define MSEM_REG_DBG_SHIFT \1304 0x1801530UL1305#define MSEM_REG_DBG_FORCE_VALID \1306 0x1801534UL1307#define MSEM_REG_DBG_FORCE_FRAME \1308 0x1801538UL1309#define USEM_REG_DBG_SELECT \1310 0x1901528UL1311#define USEM_REG_DBG_DWORD_ENABLE \1312 0x190152cUL1313#define USEM_REG_DBG_SHIFT \1314 0x1901530UL1315#define USEM_REG_DBG_FORCE_VALID \1316 0x1901534UL1317#define USEM_REG_DBG_FORCE_FRAME \1318 0x1901538UL1319#define NWS_REG_DBG_SELECT_K2_E5 \1320 0x700128UL1321#define NWS_REG_DBG_DWORD_ENABLE_K2_E5 \1322 0x70012cUL1323#define NWS_REG_DBG_SHIFT_K2_E5 \1324 0x700130UL1325#define NWS_REG_DBG_FORCE_VALID_K2_E5 \1326 0x700134UL1327#define NWS_REG_DBG_FORCE_FRAME_K2_E5 \1328 0x700138UL1329#define MS_REG_DBG_SELECT_K2_E5 \1330 0x6a0228UL1331#define MS_REG_DBG_DWORD_ENABLE_K2_E5 \1332 0x6a022cUL1333#define MS_REG_DBG_SHIFT_K2_E5 \1334 0x6a0230UL1335#define MS_REG_DBG_FORCE_VALID_K2_E5 \1336 0x6a0234UL1337#define MS_REG_DBG_FORCE_FRAME_K2_E5 \1338 0x6a0238UL1339#define PCIE_REG_DBG_COMMON_SELECT_K2_E5 \1340 0x054398UL1341#define PCIE_REG_DBG_COMMON_DWORD_ENABLE_K2_E5 \1342 0x05439cUL1343#define PCIE_REG_DBG_COMMON_SHIFT_K2_E5 \1344 0x0543a0UL1345#define PCIE_REG_DBG_COMMON_FORCE_VALID_K2_E5 \1346 0x0543a4UL1347#define PCIE_REG_DBG_COMMON_FORCE_FRAME_K2_E5 \1348 0x0543a8UL1349#define PTLD_REG_DBG_SELECT_E5 \1350 0x5a1600UL1351#define PTLD_REG_DBG_DWORD_ENABLE_E5 \1352 0x5a1604UL1353#define PTLD_REG_DBG_SHIFT_E5 \1354 0x5a1608UL1355#define PTLD_REG_DBG_FORCE_VALID_E5 \1356 0x5a160cUL1357#define PTLD_REG_DBG_FORCE_FRAME_E5 \1358 0x5a1610UL1359#define YPLD_REG_DBG_SELECT_E5 \1360 0x5c1600UL1361#define YPLD_REG_DBG_DWORD_ENABLE_E5 \1362 0x5c1604UL1363#define YPLD_REG_DBG_SHIFT_E5 \1364 0x5c1608UL1365#define YPLD_REG_DBG_FORCE_VALID_E5 \1366 0x5c160cUL1367#define YPLD_REG_DBG_FORCE_FRAME_E5 \1368 0x5c1610UL1369#define RGSRC_REG_DBG_SELECT_E5 \1370 0x320040UL1371#define RGSRC_REG_DBG_DWORD_ENABLE_E5 \1372 0x320044UL1373#define RGSRC_REG_DBG_SHIFT_E5 \1374 0x320048UL1375#define RGSRC_REG_DBG_FORCE_VALID_E5 \1376 0x32004cUL1377#define RGSRC_REG_DBG_FORCE_FRAME_E5 \1378 0x320050UL1379#define TGSRC_REG_DBG_SELECT_E5 \1380 0x322040UL1381#define TGSRC_REG_DBG_DWORD_ENABLE_E5 \1382 0x322044UL1383#define TGSRC_REG_DBG_SHIFT_E5 \1384 0x322048UL1385#define TGSRC_REG_DBG_FORCE_VALID_E5 \1386 0x32204cUL1387#define TGSRC_REG_DBG_FORCE_FRAME_E5 \1388 0x322050UL1389#define MISC_REG_RESET_PL_UA \1390 0x008050UL1391#define MISC_REG_RESET_PL_HV \1392 0x008060UL1393#define XCM_REG_CTX_RBC_ACCS \1394 0x1001800UL1395#define XCM_REG_AGG_CON_CTX \1396 0x1001804UL1397#define XCM_REG_SM_CON_CTX \1398 0x1001808UL1399#define YCM_REG_CTX_RBC_ACCS \1400 0x1081800UL1401#define YCM_REG_AGG_CON_CTX \1402 0x1081804UL1403#define YCM_REG_AGG_TASK_CTX \1404 0x1081808UL1405#define YCM_REG_SM_CON_CTX \1406 0x108180cUL1407#define YCM_REG_SM_TASK_CTX \1408 0x1081810UL1409#define PCM_REG_CTX_RBC_ACCS \1410 0x1101440UL1411#define PCM_REG_SM_CON_CTX \1412 0x1101444UL1413#define TCM_REG_CTX_RBC_ACCS \1414 0x11814c0UL1415#define TCM_REG_AGG_CON_CTX \1416 0x11814c4UL1417#define TCM_REG_AGG_TASK_CTX \1418 0x11814c8UL1419#define TCM_REG_SM_CON_CTX \1420 0x11814ccUL1421#define TCM_REG_SM_TASK_CTX \1422 0x11814d0UL1423#define MCM_REG_CTX_RBC_ACCS \1424 0x1201800UL1425#define MCM_REG_AGG_CON_CTX \1426 0x1201804UL1427#define MCM_REG_AGG_TASK_CTX \1428 0x1201808UL1429#define MCM_REG_SM_CON_CTX \1430 0x120180cUL1431#define MCM_REG_SM_TASK_CTX \1432 0x1201810UL1433#define UCM_REG_CTX_RBC_ACCS \1434 0x1281700UL1435#define UCM_REG_AGG_CON_CTX \1436 0x1281704UL1437#define UCM_REG_AGG_TASK_CTX \1438 0x1281708UL1439#define UCM_REG_SM_CON_CTX \1440 0x128170cUL1441#define UCM_REG_SM_TASK_CTX \1442 0x1281710UL1443#define XSEM_REG_SLOW_DBG_EMPTY_BB_K2 \1444 0x1401140UL1445#define XSEM_REG_SYNC_DBG_EMPTY \1446 0x1401160UL1447#define XSEM_REG_SLOW_DBG_ACTIVE \1448 0x1401400UL1449#define XSEM_REG_SLOW_DBG_MODE \1450 0x1401404UL1451#define XSEM_REG_DBG_FRAME_MODE \1452 0x1401408UL1453#define XSEM_REG_DBG_GPRE_VECT \1454 0x1401410UL1455#define XSEM_REG_DBG_MODE1_CFG \1456 0x1401420UL1457#define XSEM_REG_FAST_MEMORY \1458 0x1440000UL1459#define YSEM_REG_SYNC_DBG_EMPTY \1460 0x1501160UL1461#define YSEM_REG_SLOW_DBG_ACTIVE \1462 0x1501400UL1463#define YSEM_REG_SLOW_DBG_MODE \1464 0x1501404UL1465#define YSEM_REG_DBG_FRAME_MODE \1466 0x1501408UL1467#define YSEM_REG_DBG_GPRE_VECT \1468 0x1501410UL1469#define YSEM_REG_DBG_MODE1_CFG \1470 0x1501420UL1471#define YSEM_REG_FAST_MEMORY \1472 0x1540000UL1473#define PSEM_REG_SLOW_DBG_EMPTY_BB_K2 \1474 0x1601140UL1475#define PSEM_REG_SYNC_DBG_EMPTY \1476 0x1601160UL1477#define PSEM_REG_SLOW_DBG_ACTIVE \1478 0x1601400UL1479#define PSEM_REG_SLOW_DBG_MODE \1480 0x1601404UL1481#define PSEM_REG_DBG_FRAME_MODE \1482 0x1601408UL1483#define PSEM_REG_DBG_GPRE_VECT \1484 0x1601410UL1485#define PSEM_REG_DBG_MODE1_CFG \1486 0x1601420UL1487#define PSEM_REG_FAST_MEMORY \1488 0x1640000UL1489#define TSEM_REG_SLOW_DBG_EMPTY_BB_K2 \1490 0x1701140UL1491#define TSEM_REG_SYNC_DBG_EMPTY \1492 0x1701160UL1493#define TSEM_REG_SLOW_DBG_ACTIVE \1494 0x1701400UL1495#define TSEM_REG_SLOW_DBG_MODE \1496 0x1701404UL1497#define TSEM_REG_DBG_FRAME_MODE \1498 0x1701408UL1499#define TSEM_REG_DBG_GPRE_VECT \1500 0x1701410UL1501#define TSEM_REG_DBG_MODE1_CFG \1502 0x1701420UL1503#define TSEM_REG_FAST_MEMORY \1504 0x1740000UL1505#define MSEM_REG_SLOW_DBG_EMPTY_BB_K2 \1506 0x1801140UL1507#define MSEM_REG_SYNC_DBG_EMPTY \1508 0x1801160UL1509#define MSEM_REG_SLOW_DBG_ACTIVE \1510 0x1801400UL1511#define MSEM_REG_SLOW_DBG_MODE \1512 0x1801404UL1513#define MSEM_REG_DBG_FRAME_MODE \1514 0x1801408UL1515#define MSEM_REG_DBG_GPRE_VECT \1516 0x1801410UL1517#define MSEM_REG_DBG_MODE1_CFG \1518 0x1801420UL1519#define MSEM_REG_FAST_MEMORY \1520 0x1840000UL1521#define USEM_REG_SLOW_DBG_EMPTY_BB_K2 \1522 0x1901140UL1523#define SEM_FAST_REG_INT_RAM_SIZE \1524 204801525#define USEM_REG_SYNC_DBG_EMPTY \1526 0x1901160UL1527#define USEM_REG_SLOW_DBG_ACTIVE \1528 0x1901400UL1529#define USEM_REG_SLOW_DBG_MODE \1530 0x1901404UL1531#define USEM_REG_DBG_FRAME_MODE \1532 0x1901408UL1533#define USEM_REG_DBG_GPRE_VECT \1534 0x1901410UL1535#define USEM_REG_DBG_MODE1_CFG \1536 0x1901420UL1537#define USEM_REG_FAST_MEMORY \1538 0x1940000UL1539#define SEM_FAST_REG_DBG_MODE23_SRC_DISABLE \1540 0x000748UL1541#define SEM_FAST_REG_DBG_MODSRC_DISABLE \1542 0x00074cUL1543#define SEM_FAST_REG_DBG_MODE6_SRC_DISABLE \1544 0x000750UL1545#define SEM_FAST_REG_DEBUG_ACTIVE \1546 0x000740UL1547#define SEM_FAST_REG_INT_RAM \1548 0x020000UL1549#define SEM_FAST_REG_INT_RAM_SIZE_BB_K2 \1550 204801551#define SEM_FAST_REG_RECORD_FILTER_ENABLE \1552 0x000768UL1553#define GRC_REG_TRACE_FIFO_VALID_DATA \1554 0x050064UL1555#define GRC_REG_NUMBER_VALID_OVERRIDE_WINDOW \1556 0x05040cUL1557#define GRC_REG_PROTECTION_OVERRIDE_WINDOW \1558 0x050500UL1559#define IGU_REG_ERROR_HANDLING_MEMORY \1560 0x181520UL1561#define MCP_REG_CPU_MODE \1562 0xe05000UL1563#define MCP_REG_CPU_MODE_SOFT_HALT \1564 (0x1 << 10)1565#define BRB_REG_BIG_RAM_ADDRESS \1566 0x340800UL1567#define BRB_REG_BIG_RAM_DATA \1568 0x341500UL1569#define BRB_REG_BIG_RAM_DATA_SIZE \1570 641571#define SEM_FAST_REG_STALL_0 \1572 0x000488UL1573#define SEM_FAST_REG_STALLED \1574 0x000494UL1575#define BTB_REG_BIG_RAM_ADDRESS \1576 0xdb0800UL1577#define BTB_REG_BIG_RAM_DATA \1578 0xdb0c00UL1579#define BMB_REG_BIG_RAM_ADDRESS \1580 0x540800UL1581#define BMB_REG_BIG_RAM_DATA \1582 0x540f00UL1583#define SEM_FAST_REG_STORM_REG_FILE \1584 0x008000UL1585#define RSS_REG_RSS_RAM_ADDR \1586 0x238c30UL1587#define MISCS_REG_BLOCK_256B_EN \1588 0x009074UL1589#define MCP_REG_SCRATCH_SIZE_BB_K2 \1590 573441591#define MCP_REG_CPU_REG_FILE \1592 0xe05200UL1593#define MCP_REG_CPU_REG_FILE_SIZE \1594 321595#define DBG_REG_DEBUG_TARGET \1596 0x01005cUL1597#define DBG_REG_FULL_MODE \1598 0x010060UL1599#define DBG_REG_CALENDAR_OUT_DATA \1600 0x010480UL1601#define GRC_REG_TRACE_FIFO \1602 0x050068UL1603#define IGU_REG_ERROR_HANDLING_DATA_VALID \1604 0x181530UL1605#define DBG_REG_DBG_BLOCK_ON \1606 0x010454UL1607#define DBG_REG_FILTER_ENABLE \1608 0x0109d0UL1609#define DBG_REG_FRAMING_MODE \1610 0x010058UL1611#define DBG_REG_TRIGGER_ENABLE \1612 0x01054cUL1613#define SEM_FAST_REG_VFC_DATA_WR \1614 0x000b40UL1615#define SEM_FAST_REG_VFC_ADDR \1616 0x000b44UL1617#define SEM_FAST_REG_VFC_DATA_RD \1618 0x000b48UL1619#define SEM_FAST_REG_VFC_STATUS \1620 0x000b4cUL1621#define RSS_REG_RSS_RAM_DATA \1622 0x238c20UL1623#define RSS_REG_RSS_RAM_DATA_SIZE \1624 41625#define MISC_REG_BLOCK_256B_EN \1626 0x008c14UL1627#define NWS_REG_NWS_CMU_K2 \1628 0x720000UL1629#define PHY_NW_IP_REG_PHY0_TOP_TBUS_ADDR_7_0_K2 \1630 0x000680UL1631#define PHY_NW_IP_REG_PHY0_TOP_TBUS_ADDR_15_8_K2 \1632 0x000684UL1633#define PHY_NW_IP_REG_PHY0_TOP_TBUS_DATA_7_0_K2 \1634 0x0006c0UL1635#define PHY_NW_IP_REG_PHY0_TOP_TBUS_DATA_11_8_K2 \1636 0x0006c4UL1637#define MS_REG_MS_CMU_K2 \1638 0x6a4000UL1639#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X130_K2 \1640 0x000208UL1641#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X131_K2 \1642 0x00020cUL1643#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X132_K2 \1644 0x000210UL1645#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X133_K2 \1646 0x000214UL1647#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X130_K2 \1648 0x000208UL1649#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X131_K2 \1650 0x00020cUL1651#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X132_K2 \1652 0x000210UL1653#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X133_K2 \1654 0x000214UL1655#define PHY_PCIE_REG_PHY0_K2 \1656 0x620000UL1657#define PHY_PCIE_REG_PHY1_K2 \1658 0x624000UL1659#define NIG_REG_ROCE_DUPLICATE_TO_HOST 0x5088f0UL1660#define NIG_REG_PPF_TO_ENGINE_SEL 0x508900UL1661#define NIG_REG_PPF_TO_ENGINE_SEL_SIZE 81662#define PRS_REG_LIGHT_L2_ETHERTYPE_EN 0x1f0968UL1663#define NIG_REG_LLH_ENG_CLS_ENG_ID_TBL 0x501b90UL1664#define DORQ_REG_PF_DPM_ENABLE 0x100510UL1665#define DORQ_REG_PF_ICID_BIT_SHIFT_NORM 0x100448UL1666#define DORQ_REG_PF_MIN_ADDR_REG1 0x100400UL1667#define DORQ_REG_PF_DPI_BIT_SHIFT 0x100450UL1668#define NIG_REG_RX_PTP_EN 0x501900UL1669#define NIG_REG_TX_PTP_EN 0x501904UL1670#define NIG_REG_LLH_PTP_TO_HOST 0x501908UL1671#define NIG_REG_LLH_PTP_TO_MCP 0x50190cUL1672#define NIG_REG_PTP_SW_TXTSEN 0x501910UL1673#define NIG_REG_LLH_PTP_ETHERTYPE_1 0x501914UL1674#define NIG_REG_LLH_PTP_MAC_DA_2_LSB 0x501918UL1675#define NIG_REG_LLH_PTP_MAC_DA_2_MSB 0x50191cUL1676#define NIG_REG_LLH_PTP_PARAM_MASK 0x501920UL1677#define NIG_REG_LLH_PTP_RULE_MASK 0x501924UL1678#define NIG_REG_TX_LLH_PTP_PARAM_MASK 0x501928UL1679#define NIG_REG_TX_LLH_PTP_RULE_MASK 0x50192cUL1680#define NIG_REG_LLH_PTP_HOST_BUF_SEQID 0x501930UL1681#define NIG_REG_LLH_PTP_HOST_BUF_TS_LSB 0x501934UL1682#define NIG_REG_LLH_PTP_HOST_BUF_TS_MSB 0x501938UL1683#define NIG_REG_LLH_PTP_MCP_BUF_SEQID 0x50193cUL1684#define NIG_REG_LLH_PTP_MCP_BUF_TS_LSB 0x501940UL1685#define NIG_REG_LLH_PTP_MCP_BUF_TS_MSB 0x501944UL1686#define NIG_REG_TX_LLH_PTP_BUF_SEQID 0x501948UL1687#define NIG_REG_TX_LLH_PTP_BUF_TS_LSB 0x50194cUL1688#define NIG_REG_TX_LLH_PTP_BUF_TS_MSB 0x501950UL1689#define NIG_REG_RX_PTP_TS_MSB_ERR 0x501954UL1690#define NIG_REG_TX_PTP_TS_MSB_ERR 0x501958UL1691#define NIG_REG_TSGEN_SYNC_TIME_LSB 0x5088c0UL1692#define NIG_REG_TSGEN_SYNC_TIME_MSB 0x5088c4UL1693#define NIG_REG_TSGEN_RST_DRIFT_CNTR 0x5088d8UL1694#define NIG_REG_TSGEN_DRIFT_CNTR_CONF 0x5088dcUL1695#define NIG_REG_TS_OUTPUT_ENABLE_PDA 0x508870UL1696#define NIG_REG_TIMESYNC_GEN_REG_BB 0x500d00UL1697#define NIG_REG_TSGEN_FREE_CNT_VALUE_LSB 0x5088a8UL1698#define NIG_REG_TSGEN_FREE_CNT_VALUE_MSB 0x5088acUL1699#define NIG_REG_PTP_LATCH_OSTS_PKT_TIME 0x509040UL1700#define PSWRQ2_REG_WR_MBS0 0x240400UL1701 1702#define PGLUE_B_REG_PGL_ADDR_E8_F0_K2 0x2aaf98UL1703#define PGLUE_B_REG_PGL_ADDR_EC_F0_K2 0x2aaf9cUL1704#define PGLUE_B_REG_PGL_ADDR_F0_F0_K2 0x2aafa0UL1705#define PGLUE_B_REG_PGL_ADDR_F4_F0_K2 0x2aafa4UL1706#define PGLUE_B_REG_MASTER_WRITE_PAD_ENABLE 0x2aae30UL1707#define NIG_REG_TSGEN_FREECNT_UPDATE_K2 0x509008UL1708#define CNIG_REG_NIG_PORT0_CONF_K2 0x218200UL1709 1710#define NIG_REG_TX_EDPM_CTRL 0x501f0cUL1711#define NIG_REG_TX_EDPM_CTRL_TX_EDPM_EN (0x1 << 0)1712#define NIG_REG_TX_EDPM_CTRL_TX_EDPM_EN_SHIFT 01713#define NIG_REG_TX_EDPM_CTRL_TX_EDPM_TC_EN (0xff << 1)1714#define NIG_REG_TX_EDPM_CTRL_TX_EDPM_TC_EN_SHIFT 11715 1716#define PRS_REG_SEARCH_GFT 0x1f11bcUL1717#define PRS_REG_SEARCH_NON_IP_AS_GFT 0x1f11c0UL1718#define PRS_REG_CM_HDR_GFT 0x1f11c8UL1719#define PRS_REG_GFT_CAM 0x1f1100UL1720#define PRS_REG_GFT_PROFILE_MASK_RAM 0x1f1000UL1721#define PRS_REG_CM_HDR_GFT_EVENT_ID_SHIFT 01722#define PRS_REG_CM_HDR_GFT_CM_HDR_SHIFT 81723#define PRS_REG_LOAD_L2_FILTER 0x1f0198UL1724 1725#endif1726