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1/* SPDX-License-Identifier: GPL-2.0-only */2/* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.3 */4 5#ifndef _EMAC_H_6#define _EMAC_H_7 8#include <linux/irqreturn.h>9#include <linux/netdevice.h>10#include <linux/clk.h>11#include <linux/platform_device.h>12#include "emac-mac.h"13#include "emac-phy.h"14#include "emac-sgmii.h"15 16/* EMAC base register offsets */17#define EMAC_DMA_MAS_CTRL 0x140018#define EMAC_IRQ_MOD_TIM_INIT 0x140819#define EMAC_BLK_IDLE_STS 0x140c20#define EMAC_PHY_LINK_DELAY 0x141c21#define EMAC_SYS_ALIV_CTRL 0x143422#define EMAC_MAC_CTRL 0x148023#define EMAC_MAC_IPGIFG_CTRL 0x148424#define EMAC_MAC_STA_ADDR0 0x148825#define EMAC_MAC_STA_ADDR1 0x148c26#define EMAC_HASH_TAB_REG0 0x149027#define EMAC_HASH_TAB_REG1 0x149428#define EMAC_MAC_HALF_DPLX_CTRL 0x149829#define EMAC_MAX_FRAM_LEN_CTRL 0x149c30#define EMAC_WOL_CTRL0 0x14a031#define EMAC_RSS_KEY0 0x14b032#define EMAC_H1TPD_BASE_ADDR_LO 0x14e033#define EMAC_H2TPD_BASE_ADDR_LO 0x14e434#define EMAC_H3TPD_BASE_ADDR_LO 0x14e835#define EMAC_INTER_SRAM_PART9 0x153436#define EMAC_DESC_CTRL_0 0x154037#define EMAC_DESC_CTRL_1 0x154438#define EMAC_DESC_CTRL_2 0x155039#define EMAC_DESC_CTRL_10 0x155440#define EMAC_DESC_CTRL_12 0x155841#define EMAC_DESC_CTRL_13 0x155c42#define EMAC_DESC_CTRL_3 0x156043#define EMAC_DESC_CTRL_4 0x156444#define EMAC_DESC_CTRL_5 0x156845#define EMAC_DESC_CTRL_14 0x156c46#define EMAC_DESC_CTRL_15 0x157047#define EMAC_DESC_CTRL_16 0x157448#define EMAC_DESC_CTRL_6 0x157849#define EMAC_DESC_CTRL_8 0x158050#define EMAC_DESC_CTRL_9 0x158451#define EMAC_DESC_CTRL_11 0x158852#define EMAC_TXQ_CTRL_0 0x159053#define EMAC_TXQ_CTRL_1 0x159454#define EMAC_TXQ_CTRL_2 0x159855#define EMAC_RXQ_CTRL_0 0x15a056#define EMAC_RXQ_CTRL_1 0x15a457#define EMAC_RXQ_CTRL_2 0x15a858#define EMAC_RXQ_CTRL_3 0x15ac59#define EMAC_BASE_CPU_NUMBER 0x15b860#define EMAC_DMA_CTRL 0x15c061#define EMAC_MAILBOX_0 0x15e062#define EMAC_MAILBOX_5 0x15e463#define EMAC_MAILBOX_6 0x15e864#define EMAC_MAILBOX_13 0x15ec65#define EMAC_MAILBOX_2 0x15f466#define EMAC_MAILBOX_3 0x15f867#define EMAC_INT_STATUS 0x160068#define EMAC_INT_MASK 0x160469#define EMAC_MAILBOX_11 0x160c70#define EMAC_AXI_MAST_CTRL 0x161071#define EMAC_MAILBOX_12 0x161472#define EMAC_MAILBOX_9 0x161873#define EMAC_MAILBOX_10 0x161c74#define EMAC_ATHR_HEADER_CTRL 0x162075#define EMAC_RXMAC_STATC_REG0 0x170076#define EMAC_RXMAC_STATC_REG22 0x175877#define EMAC_TXMAC_STATC_REG0 0x176078#define EMAC_TXMAC_STATC_REG24 0x17c079#define EMAC_CLK_GATE_CTRL 0x181480#define EMAC_CORE_HW_VERSION 0x197481#define EMAC_MISC_CTRL 0x199082#define EMAC_MAILBOX_7 0x19e083#define EMAC_MAILBOX_8 0x19e484#define EMAC_IDT_TABLE0 0x1b0085#define EMAC_RXMAC_STATC_REG23 0x1bc886#define EMAC_RXMAC_STATC_REG24 0x1bcc87#define EMAC_TXMAC_STATC_REG25 0x1bd088#define EMAC_MAILBOX_15 0x1bd489#define EMAC_MAILBOX_16 0x1bd890#define EMAC_INT1_MASK 0x1bf091#define EMAC_INT1_STATUS 0x1bf492#define EMAC_INT2_MASK 0x1bf893#define EMAC_INT2_STATUS 0x1bfc94#define EMAC_INT3_MASK 0x1c0095#define EMAC_INT3_STATUS 0x1c0496 97/* EMAC_DMA_MAS_CTRL */98#define DEV_ID_NUM_BMSK 0x7f00000099#define DEV_ID_NUM_SHFT 24100#define DEV_REV_NUM_BMSK 0xff0000101#define DEV_REV_NUM_SHFT 16102#define INT_RD_CLR_EN 0x4000103#define IRQ_MODERATOR2_EN 0x800104#define IRQ_MODERATOR_EN 0x400105#define LPW_CLK_SEL 0x80106#define LPW_STATE 0x20107#define LPW_MODE 0x10108#define SOFT_RST 0x1109 110/* EMAC_IRQ_MOD_TIM_INIT */111#define IRQ_MODERATOR2_INIT_BMSK 0xffff0000112#define IRQ_MODERATOR2_INIT_SHFT 16113#define IRQ_MODERATOR_INIT_BMSK 0xffff114#define IRQ_MODERATOR_INIT_SHFT 0115 116/* EMAC_INT_STATUS */117#define DIS_INT BIT(31)118#define PTP_INT BIT(30)119#define RFD4_UR_INT BIT(29)120#define TX_PKT_INT3 BIT(26)121#define TX_PKT_INT2 BIT(25)122#define TX_PKT_INT1 BIT(24)123#define RX_PKT_INT3 BIT(19)124#define RX_PKT_INT2 BIT(18)125#define RX_PKT_INT1 BIT(17)126#define RX_PKT_INT0 BIT(16)127#define TX_PKT_INT BIT(15)128#define TXQ_TO_INT BIT(14)129#define GPHY_WAKEUP_INT BIT(13)130#define GPHY_LINK_DOWN_INT BIT(12)131#define GPHY_LINK_UP_INT BIT(11)132#define DMAW_TO_INT BIT(10)133#define DMAR_TO_INT BIT(9)134#define TXF_UR_INT BIT(8)135#define RFD3_UR_INT BIT(7)136#define RFD2_UR_INT BIT(6)137#define RFD1_UR_INT BIT(5)138#define RFD0_UR_INT BIT(4)139#define RXF_OF_INT BIT(3)140#define SW_MAN_INT BIT(2)141 142/* EMAC_MAILBOX_6 */143#define RFD2_PROC_IDX_BMSK 0xfff0000144#define RFD2_PROC_IDX_SHFT 16145#define RFD2_PROD_IDX_BMSK 0xfff146#define RFD2_PROD_IDX_SHFT 0147 148/* EMAC_CORE_HW_VERSION */149#define MAJOR_BMSK 0xf0000000150#define MAJOR_SHFT 28151#define MINOR_BMSK 0xfff0000152#define MINOR_SHFT 16153#define STEP_BMSK 0xffff154#define STEP_SHFT 0155 156/* EMAC_EMAC_WRAPPER_CSR1 */157#define TX_INDX_FIFO_SYNC_RST BIT(23)158#define TX_TS_FIFO_SYNC_RST BIT(22)159#define RX_TS_FIFO2_SYNC_RST BIT(21)160#define RX_TS_FIFO1_SYNC_RST BIT(20)161#define TX_TS_ENABLE BIT(16)162#define DIS_1588_CLKS BIT(11)163#define FREQ_MODE BIT(9)164#define ENABLE_RRD_TIMESTAMP BIT(3)165 166/* EMAC_EMAC_WRAPPER_CSR2 */167#define HDRIVE_BMSK 0x3000168#define HDRIVE_SHFT 12169#define SLB_EN BIT(9)170#define PLB_EN BIT(8)171#define WOL_EN BIT(3)172#define PHY_RESET BIT(0)173 174#define EMAC_DEV_ID 0x0040175 176/* SGMII v2 per lane registers */177#define SGMII_LN_RSM_START 0x029C178 179/* SGMII v2 PHY common registers */180#define SGMII_PHY_CMN_CTRL 0x0408181#define SGMII_PHY_CMN_RESET_CTRL 0x0410182 183/* SGMII v2 PHY registers per lane */184#define SGMII_PHY_LN_OFFSET 0x0400185#define SGMII_PHY_LN_LANE_STATUS 0x00DC186#define SGMII_PHY_LN_BIST_GEN0 0x008C187#define SGMII_PHY_LN_BIST_GEN1 0x0090188#define SGMII_PHY_LN_BIST_GEN2 0x0094189#define SGMII_PHY_LN_BIST_GEN3 0x0098190#define SGMII_PHY_LN_CDR_CTRL1 0x005C191 192enum emac_clk_id {193 EMAC_CLK_AXI,194 EMAC_CLK_CFG_AHB,195 EMAC_CLK_HIGH_SPEED,196 EMAC_CLK_MDIO,197 EMAC_CLK_TX,198 EMAC_CLK_RX,199 EMAC_CLK_SYS,200 EMAC_CLK_CNT201};202 203#define EMAC_LINK_SPEED_UNKNOWN 0x0204#define EMAC_LINK_SPEED_10_HALF BIT(0)205#define EMAC_LINK_SPEED_10_FULL BIT(1)206#define EMAC_LINK_SPEED_100_HALF BIT(2)207#define EMAC_LINK_SPEED_100_FULL BIT(3)208#define EMAC_LINK_SPEED_1GB_FULL BIT(5)209 210#define EMAC_MAX_SETUP_LNK_CYCLE 100211 212struct emac_stats {213 /* rx */214 u64 rx_ok; /* good packets */215 u64 rx_bcast; /* good broadcast packets */216 u64 rx_mcast; /* good multicast packets */217 u64 rx_pause; /* pause packet */218 u64 rx_ctrl; /* control packets other than pause frame. */219 u64 rx_fcs_err; /* packets with bad FCS. */220 u64 rx_len_err; /* packets with length mismatch */221 u64 rx_byte_cnt; /* good bytes count (without FCS) */222 u64 rx_runt; /* runt packets */223 u64 rx_frag; /* fragment count */224 u64 rx_sz_64; /* packets that are 64 bytes */225 u64 rx_sz_65_127; /* packets that are 65-127 bytes */226 u64 rx_sz_128_255; /* packets that are 128-255 bytes */227 u64 rx_sz_256_511; /* packets that are 256-511 bytes */228 u64 rx_sz_512_1023; /* packets that are 512-1023 bytes */229 u64 rx_sz_1024_1518; /* packets that are 1024-1518 bytes */230 u64 rx_sz_1519_max; /* packets that are 1519-MTU bytes*/231 u64 rx_sz_ov; /* packets that are >MTU bytes (truncated) */232 u64 rx_rxf_ov; /* packets dropped due to RX FIFO overflow */233 u64 rx_align_err; /* alignment errors */234 u64 rx_bcast_byte_cnt; /* broadcast packets byte count (without FCS) */235 u64 rx_mcast_byte_cnt; /* multicast packets byte count (without FCS) */236 u64 rx_err_addr; /* packets dropped due to address filtering */237 u64 rx_crc_align; /* CRC align errors */238 u64 rx_jabbers; /* jabbers */239 240 /* tx */241 u64 tx_ok; /* good packets */242 u64 tx_bcast; /* good broadcast packets */243 u64 tx_mcast; /* good multicast packets */244 u64 tx_pause; /* pause packets */245 u64 tx_exc_defer; /* packets with excessive deferral */246 u64 tx_ctrl; /* control packets other than pause frame */247 u64 tx_defer; /* packets that are deferred. */248 u64 tx_byte_cnt; /* good bytes count (without FCS) */249 u64 tx_sz_64; /* packets that are 64 bytes */250 u64 tx_sz_65_127; /* packets that are 65-127 bytes */251 u64 tx_sz_128_255; /* packets that are 128-255 bytes */252 u64 tx_sz_256_511; /* packets that are 256-511 bytes */253 u64 tx_sz_512_1023; /* packets that are 512-1023 bytes */254 u64 tx_sz_1024_1518; /* packets that are 1024-1518 bytes */255 u64 tx_sz_1519_max; /* packets that are 1519-MTU bytes */256 u64 tx_1_col; /* packets single prior collision */257 u64 tx_2_col; /* packets with multiple prior collisions */258 u64 tx_late_col; /* packets with late collisions */259 u64 tx_abort_col; /* packets aborted due to excess collisions */260 u64 tx_underrun; /* packets aborted due to FIFO underrun */261 u64 tx_rd_eop; /* count of reads beyond EOP */262 u64 tx_len_err; /* packets with length mismatch */263 u64 tx_trunc; /* packets truncated due to size >MTU */264 u64 tx_bcast_byte; /* broadcast packets byte count (without FCS) */265 u64 tx_mcast_byte; /* multicast packets byte count (without FCS) */266 u64 tx_col; /* collisions */267 268 spinlock_t lock; /* prevent multiple simultaneous readers */269};270 271/* RSS hstype Definitions */272#define EMAC_RSS_HSTYP_IPV4_EN 0x00000001273#define EMAC_RSS_HSTYP_TCP4_EN 0x00000002274#define EMAC_RSS_HSTYP_IPV6_EN 0x00000004275#define EMAC_RSS_HSTYP_TCP6_EN 0x00000008276#define EMAC_RSS_HSTYP_ALL_EN (\277 EMAC_RSS_HSTYP_IPV4_EN |\278 EMAC_RSS_HSTYP_TCP4_EN |\279 EMAC_RSS_HSTYP_IPV6_EN |\280 EMAC_RSS_HSTYP_TCP6_EN)281 282#define EMAC_VLAN_TO_TAG(_vlan, _tag) \283 (_tag = ((((_vlan) >> 8) & 0xFF) | (((_vlan) & 0xFF) << 8)))284 285#define EMAC_TAG_TO_VLAN(_tag, _vlan) \286 (_vlan = ((((_tag) >> 8) & 0xFF) | (((_tag) & 0xFF) << 8)))287 288#define EMAC_DEF_RX_BUF_SIZE 1536289#define EMAC_MAX_JUMBO_PKT_SIZE (9 * 1024)290#define EMAC_MAX_TX_OFFLOAD_THRESH (9 * 1024)291 292#define EMAC_MAX_ETH_FRAME_SIZE EMAC_MAX_JUMBO_PKT_SIZE293#define EMAC_MIN_ETH_FRAME_SIZE 68294 295#define EMAC_DEF_TX_QUEUES 1296#define EMAC_DEF_RX_QUEUES 1297 298#define EMAC_MIN_TX_DESCS 128299#define EMAC_MIN_RX_DESCS 128300 301#define EMAC_MAX_TX_DESCS 16383302#define EMAC_MAX_RX_DESCS 2047303 304#define EMAC_DEF_TX_DESCS 512305#define EMAC_DEF_RX_DESCS 256306 307#define EMAC_DEF_RX_IRQ_MOD 250308#define EMAC_DEF_TX_IRQ_MOD 250309 310#define EMAC_WATCHDOG_TIME (5 * HZ)311 312/* by default check link every 4 seconds */313#define EMAC_TRY_LINK_TIMEOUT (4 * HZ)314 315/* emac_irq per-device (per-adapter) irq properties.316 * @irq: irq number.317 * @mask mask to use over status register.318 */319struct emac_irq {320 unsigned int irq;321 u32 mask;322};323 324/* The device's main data structure */325struct emac_adapter {326 struct net_device *netdev;327 struct mii_bus *mii_bus;328 struct phy_device *phydev;329 330 void __iomem *base;331 void __iomem *csr;332 333 struct emac_sgmii phy;334 struct emac_stats stats;335 336 struct emac_irq irq;337 struct clk *clk[EMAC_CLK_CNT];338 339 /* All Descriptor memory */340 struct emac_ring_header ring_header;341 struct emac_tx_queue tx_q;342 struct emac_rx_queue rx_q;343 unsigned int tx_desc_cnt;344 unsigned int rx_desc_cnt;345 unsigned int rrd_size; /* in quad words */346 unsigned int rfd_size; /* in quad words */347 unsigned int tpd_size; /* in quad words */348 349 unsigned int rxbuf_size;350 351 /* Flow control / pause frames support. If automatic=True, do whatever352 * the PHY does. Otherwise, use tx_flow_control and rx_flow_control.353 */354 bool automatic;355 bool tx_flow_control;356 bool rx_flow_control;357 358 /* True == use single-pause-frame mode. */359 bool single_pause_mode;360 361 /* Ring parameter */362 u8 tpd_burst;363 u8 rfd_burst;364 unsigned int dmaw_dly_cnt;365 unsigned int dmar_dly_cnt;366 enum emac_dma_req_block dmar_block;367 enum emac_dma_req_block dmaw_block;368 enum emac_dma_order dma_order;369 370 u32 irq_mod;371 u32 preamble;372 373 struct work_struct work_thread;374 375 u16 msg_enable;376 377 struct mutex reset_lock;378};379 380int emac_reinit_locked(struct emac_adapter *adpt);381void emac_reg_update32(void __iomem *addr, u32 mask, u32 val);382 383void emac_set_ethtool_ops(struct net_device *netdev);384void emac_update_hw_stats(struct emac_adapter *adpt);385 386#endif /* _EMAC_H_ */387