175 lines · c
1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * linux/drivers/acorn/net/ether3.h4 *5 * Copyright (C) 1995-2000 Russell King6 *7 * network driver for Acorn/ANT Ether3 cards8 */9 10#ifndef _LINUX_ether3_H11#define _LINUX_ether3_H12 13/* use 0 for production, 1 for verification, >2 for debug. debug flags: */14#define DEBUG_TX 215#define DEBUG_RX 416#define DEBUG_INT 817#define DEBUG_IC 1618#ifndef NET_DEBUG19#define NET_DEBUG 020#endif21 22#define priv(dev) ((struct dev_priv *)netdev_priv(dev))23 24/* Command register definitions & bits */25#define REG_COMMAND (priv(dev)->seeq + 0x0000)26#define CMD_ENINTDMA 0x000127#define CMD_ENINTRX 0x000228#define CMD_ENINTTX 0x000429#define CMD_ENINTBUFWIN 0x000830#define CMD_ACKINTDMA 0x001031#define CMD_ACKINTRX 0x002032#define CMD_ACKINTTX 0x004033#define CMD_ACKINTBUFWIN 0x008034#define CMD_DMAON 0x010035#define CMD_RXON 0x020036#define CMD_TXON 0x040037#define CMD_DMAOFF 0x080038#define CMD_RXOFF 0x100039#define CMD_TXOFF 0x200040#define CMD_FIFOREAD 0x400041#define CMD_FIFOWRITE 0x800042 43/* status register */44#define REG_STATUS (priv(dev)->seeq + 0x0000)45#define STAT_ENINTSTAT 0x000146#define STAT_ENINTRX 0x000247#define STAT_ENINTTX 0x000448#define STAT_ENINTBUFWIN 0x000849#define STAT_INTDMA 0x001050#define STAT_INTRX 0x002051#define STAT_INTTX 0x004052#define STAT_INTBUFWIN 0x008053#define STAT_DMAON 0x010054#define STAT_RXON 0x020055#define STAT_TXON 0x040056#define STAT_FIFOFULL 0x200057#define STAT_FIFOEMPTY 0x400058#define STAT_FIFODIR 0x800059 60/* configuration register 1 */61#define REG_CONFIG1 (priv(dev)->seeq + 0x0040)62#define CFG1_BUFSELSTAT0 0x000063#define CFG1_BUFSELSTAT1 0x000164#define CFG1_BUFSELSTAT2 0x000265#define CFG1_BUFSELSTAT3 0x000366#define CFG1_BUFSELSTAT4 0x000467#define CFG1_BUFSELSTAT5 0x000568#define CFG1_ADDRPROM 0x000669#define CFG1_TRANSEND 0x000770#define CFG1_LOCBUFMEM 0x000871#define CFG1_INTVECTOR 0x000972#define CFG1_RECVSPECONLY 0x000073#define CFG1_RECVSPECBROAD 0x400074#define CFG1_RECVSPECBRMULTI 0x800075#define CFG1_RECVPROMISC 0xC00076 77/* The following aren't in 8004 */78#define CFG1_DMABURSTCONT 0x000079#define CFG1_DMABURST800NS 0x001080#define CFG1_DMABURST1600NS 0x002081#define CFG1_DMABURST3200NS 0x003082#define CFG1_DMABURST1 0x000083#define CFG1_DMABURST4 0x004084#define CFG1_DMABURST8 0x008085#define CFG1_DMABURST16 0x00C086#define CFG1_RECVCOMPSTAT0 0x010087#define CFG1_RECVCOMPSTAT1 0x020088#define CFG1_RECVCOMPSTAT2 0x040089#define CFG1_RECVCOMPSTAT3 0x080090#define CFG1_RECVCOMPSTAT4 0x100091#define CFG1_RECVCOMPSTAT5 0x200092 93/* configuration register 2 */94#define REG_CONFIG2 (priv(dev)->seeq + 0x0080)95#define CFG2_BYTESWAP 0x000196#define CFG2_ERRENCRC 0x000897#define CFG2_ERRENDRIBBLE 0x001098#define CFG2_ERRSHORTFRAME 0x002099#define CFG2_SLOTSELECT 0x0040100#define CFG2_PREAMSELECT 0x0080101#define CFG2_ADDRLENGTH 0x0100102#define CFG2_RECVCRC 0x0200103#define CFG2_XMITNOCRC 0x0400104#define CFG2_LOOPBACK 0x0800105#define CFG2_CTRLO 0x1000106#define CFG2_RESET 0x8000107 108#define REG_RECVEND (priv(dev)->seeq + 0x00c0)109 110#define REG_BUFWIN (priv(dev)->seeq + 0x0100)111 112#define REG_RECVPTR (priv(dev)->seeq + 0x0140)113 114#define REG_TRANSMITPTR (priv(dev)->seeq + 0x0180)115 116#define REG_DMAADDR (priv(dev)->seeq + 0x01c0)117 118/*119 * Cards transmit/receive headers120 */121#define TX_NEXT (0xffff)122#define TXHDR_ENBABBLEINT (1 << 16)123#define TXHDR_ENCOLLISIONINT (1 << 17)124#define TXHDR_EN16COLLISION (1 << 18)125#define TXHDR_ENSUCCESS (1 << 19)126#define TXHDR_DATAFOLLOWS (1 << 21)127#define TXHDR_CHAINCONTINUE (1 << 22)128#define TXHDR_TRANSMIT (1 << 23)129#define TXSTAT_BABBLED (1 << 24)130#define TXSTAT_COLLISION (1 << 25)131#define TXSTAT_16COLLISIONS (1 << 26)132#define TXSTAT_DONE (1 << 31)133 134#define RX_NEXT (0xffff)135#define RXHDR_CHAINCONTINUE (1 << 6)136#define RXHDR_RECEIVE (1 << 7)137#define RXSTAT_OVERSIZE (1 << 8)138#define RXSTAT_CRCERROR (1 << 9)139#define RXSTAT_DRIBBLEERROR (1 << 10)140#define RXSTAT_SHORTPACKET (1 << 11)141#define RXSTAT_DONE (1 << 15)142 143 144#define TX_START 0x0000145#define TX_END 0x6000146#define RX_START 0x6000147#define RX_LEN 0xA000148#define RX_END 0x10000149/* must be a power of 2 and greater than MAX_TX_BUFFERED */150#define MAX_TXED 16151#define MAX_TX_BUFFERED 10152 153struct dev_priv {154 void __iomem *base;155 void __iomem *seeq;156 struct {157 unsigned int command;158 unsigned int config1;159 unsigned int config2;160 } regs;161 unsigned char tx_head; /* buffer nr to insert next packet */162 unsigned char tx_tail; /* buffer nr of transmitting packet */163 unsigned int rx_head; /* address to fetch next packet from */164 struct timer_list timer;165 struct net_device *dev;166 int broken; /* 0 = ok, 1 = something went wrong */167};168 169struct ether3_data {170 const char name[8];171 unsigned long base_offset;172};173 174#endif175