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1/* SPDX-License-Identifier: GPL-2.0-only */2/****************************************************************************3 * Driver for Solarflare network controllers and boards4 * Copyright 2018 Solarflare Communications Inc.5 * Copyright 2019-2022 Xilinx Inc.6 *7 * This program is free software; you can redistribute it and/or modify it8 * under the terms of the GNU General Public License version 2 as published9 * by the Free Software Foundation, incorporated herein by reference.10 */11 12#ifndef EFX_EF100_REGS_H13#define EFX_EF100_REGS_H14 15/* EF100 hardware architecture definitions have a name prefix following16 * the format:17 *18 * E<type>_<min-rev><max-rev>_19 *20 * The following <type> strings are used:21 *22 * MMIO register Host memory structure23 * -------------------------------------------------------------24 * Address R25 * Bitfield RF SF26 * Enumerator FE SE27 *28 * <min-rev> is the first revision to which the definition applies:29 *30 * G: Riverhead31 *32 * If the definition has been changed or removed in later revisions33 * then <max-rev> is the last revision to which the definition applies;34 * otherwise it is "Z".35 */36 37/**************************************************************************38 *39 * EF100 registers and descriptors40 *41 **************************************************************************42 */43 44/* HW_REV_ID_REG: Hardware revision info register */45#define ER_GZ_HW_REV_ID 0x0000000046 47/* NIC_REV_ID: SoftNIC revision info register */48#define ER_GZ_NIC_REV_ID 0x0000000449 50/* NIC_MAGIC: Signature register that should contain a well-known value */51#define ER_GZ_NIC_MAGIC 0x0000000852#define ERF_GZ_NIC_MAGIC_LBN 053#define ERF_GZ_NIC_MAGIC_WIDTH 3254#define EFE_GZ_NIC_MAGIC_EXPECTED 0xEF100FCB55 56/* MC_SFT_STATUS: MC soft status */57#define ER_GZ_MC_SFT_STATUS 0x0000001058#define ER_GZ_MC_SFT_STATUS_STEP 459#define ER_GZ_MC_SFT_STATUS_ROWS 260 61/* MC_DB_LWRD_REG: MC doorbell register, low word */62#define ER_GZ_MC_DB_LWRD 0x0000002063 64/* MC_DB_HWRD_REG: MC doorbell register, high word */65#define ER_GZ_MC_DB_HWRD 0x0000002466 67/* EVQ_INT_PRIME: Prime EVQ */68#define ER_GZ_EVQ_INT_PRIME 0x0000004069#define ERF_GZ_IDX_LBN 1670#define ERF_GZ_IDX_WIDTH 1671#define ERF_GZ_EVQ_ID_LBN 072#define ERF_GZ_EVQ_ID_WIDTH 1673 74/* INT_AGG_RING_PRIME: Prime interrupt aggregation ring. */75#define ER_GZ_INT_AGG_RING_PRIME 0x0000004876/* defined as ERF_GZ_IDX_LBN 16; access=WO reset=0x0 */77/* defined as ERF_GZ_IDX_WIDTH 16 */78#define ERF_GZ_RING_ID_LBN 079#define ERF_GZ_RING_ID_WIDTH 1680 81/* EVQ_TMR: EVQ timer control */82#define ER_GZ_EVQ_TMR 0x0000010483#define ER_GZ_EVQ_TMR_STEP 6553684#define ER_GZ_EVQ_TMR_ROWS 102485 86/* EVQ_UNSOL_CREDIT_GRANT_SEQ: Grant credits for unsolicited events. */87#define ER_GZ_EVQ_UNSOL_CREDIT_GRANT_SEQ 0x0000010888#define ER_GZ_EVQ_UNSOL_CREDIT_GRANT_SEQ_STEP 6553689#define ER_GZ_EVQ_UNSOL_CREDIT_GRANT_SEQ_ROWS 102490 91/* EVQ_DESC_CREDIT_GRANT_SEQ: Grant credits for descriptor proxy events. */92#define ER_GZ_EVQ_DESC_CREDIT_GRANT_SEQ 0x0000011093#define ER_GZ_EVQ_DESC_CREDIT_GRANT_SEQ_STEP 6553694#define ER_GZ_EVQ_DESC_CREDIT_GRANT_SEQ_ROWS 102495 96/* RX_RING_DOORBELL: Ring Rx doorbell. */97#define ER_GZ_RX_RING_DOORBELL 0x0000018098#define ER_GZ_RX_RING_DOORBELL_STEP 6553699#define ER_GZ_RX_RING_DOORBELL_ROWS 1024100#define ERF_GZ_RX_RING_PIDX_LBN 16101#define ERF_GZ_RX_RING_PIDX_WIDTH 16102 103/* TX_RING_DOORBELL: Ring Tx doorbell. */104#define ER_GZ_TX_RING_DOORBELL 0x00000200105#define ER_GZ_TX_RING_DOORBELL_STEP 65536106#define ER_GZ_TX_RING_DOORBELL_ROWS 1024107#define ERF_GZ_TX_RING_PIDX_LBN 16108#define ERF_GZ_TX_RING_PIDX_WIDTH 16109 110/* TX_DESC_PUSH: Tx ring descriptor push. Reserved for future use. */111#define ER_GZ_TX_DESC_PUSH 0x00000210112#define ER_GZ_TX_DESC_PUSH_STEP 65536113#define ER_GZ_TX_DESC_PUSH_ROWS 1024114 115/* THE_TIME: NIC hardware time */116#define ER_GZ_THE_TIME 0x00000280117#define ER_GZ_THE_TIME_STEP 65536118#define ER_GZ_THE_TIME_ROWS 1024119#define ERF_GZ_THE_TIME_SECS_LBN 32120#define ERF_GZ_THE_TIME_SECS_WIDTH 32121#define ERF_GZ_THE_TIME_NANOS_LBN 2122#define ERF_GZ_THE_TIME_NANOS_WIDTH 30123#define ERF_GZ_THE_TIME_CLOCK_IN_SYNC_LBN 1124#define ERF_GZ_THE_TIME_CLOCK_IN_SYNC_WIDTH 1125#define ERF_GZ_THE_TIME_CLOCK_IS_SET_LBN 0126#define ERF_GZ_THE_TIME_CLOCK_IS_SET_WIDTH 1127 128/* PARAMS_TLV_LEN: Size of design parameters area in bytes */129#define ER_GZ_PARAMS_TLV_LEN 0x00000c00130#define ER_GZ_PARAMS_TLV_LEN_STEP 65536131#define ER_GZ_PARAMS_TLV_LEN_ROWS 1024132 133/* PARAMS_TLV: Design parameters */134#define ER_GZ_PARAMS_TLV 0x00000c04135#define ER_GZ_PARAMS_TLV_STEP 65536136#define ER_GZ_PARAMS_TLV_ROWS 1024137 138/* EW_EMBEDDED_EVENT */139#define ESF_GZ_EV_256_EVENT_LBN 0140#define ESF_GZ_EV_256_EVENT_WIDTH 64141#define ESE_GZ_EW_EMBEDDED_EVENT_STRUCT_SIZE 64142 143/* NMMU_PAGESZ_2M_ADDR */144#define ESF_GZ_NMMU_2M_PAGE_SIZE_ID_LBN 59145#define ESF_GZ_NMMU_2M_PAGE_SIZE_ID_WIDTH 5146#define ESE_GZ_NMMU_PAGE_SIZE_2M 9147#define ESF_GZ_NMMU_2M_PAGE_ID_LBN 21148#define ESF_GZ_NMMU_2M_PAGE_ID_WIDTH 38149#define ESF_GZ_NMMU_2M_PAGE_OFFSET_LBN 0150#define ESF_GZ_NMMU_2M_PAGE_OFFSET_WIDTH 21151#define ESE_GZ_NMMU_PAGESZ_2M_ADDR_STRUCT_SIZE 64152 153/* PARAM_TLV */154#define ESF_GZ_TLV_VALUE_LBN 16155#define ESF_GZ_TLV_VALUE_WIDTH 8156#define ESE_GZ_TLV_VALUE_LENMIN 8157#define ESE_GZ_TLV_VALUE_LENMAX 2040158#define ESF_GZ_TLV_LEN_LBN 8159#define ESF_GZ_TLV_LEN_WIDTH 8160#define ESF_GZ_TLV_TYPE_LBN 0161#define ESF_GZ_TLV_TYPE_WIDTH 8162#define ESE_GZ_DP_NMMU_GROUP_SIZE 5163#define ESE_GZ_DP_EVQ_UNSOL_CREDIT_SEQ_BITS 4164#define ESE_GZ_DP_TX_EV_NUM_DESCS_BITS 3165#define ESE_GZ_DP_RX_EV_NUM_PACKETS_BITS 2166#define ESE_GZ_DP_PARTIAL_TSTAMP_SUB_NANO_BITS 1167#define ESE_GZ_DP_PAD 0168#define ESE_GZ_PARAM_TLV_STRUCT_SIZE 24169 170/* PCI_EXPRESS_XCAP_HDR */171#define ESF_GZ_PCI_EXPRESS_XCAP_NEXT_LBN 20172#define ESF_GZ_PCI_EXPRESS_XCAP_NEXT_WIDTH 12173#define ESF_GZ_PCI_EXPRESS_XCAP_VER_LBN 16174#define ESF_GZ_PCI_EXPRESS_XCAP_VER_WIDTH 4175#define ESE_GZ_PCI_EXPRESS_XCAP_VER_VSEC 1176#define ESF_GZ_PCI_EXPRESS_XCAP_ID_LBN 0177#define ESF_GZ_PCI_EXPRESS_XCAP_ID_WIDTH 16178#define ESE_GZ_PCI_EXPRESS_XCAP_ID_VNDR 0xb179#define ESE_GZ_PCI_EXPRESS_XCAP_HDR_STRUCT_SIZE 32180 181/* RHEAD_BASE_EVENT */182#define ESF_GZ_E_TYPE_LBN 60183#define ESF_GZ_E_TYPE_WIDTH 4184#define ESF_GZ_EV_EVQ_PHASE_LBN 59185#define ESF_GZ_EV_EVQ_PHASE_WIDTH 1186#define ESE_GZ_RHEAD_BASE_EVENT_STRUCT_SIZE 64187 188/* RHEAD_EW_EVENT */189#define ESF_GZ_EV_256_EV32_PHASE_LBN 255190#define ESF_GZ_EV_256_EV32_PHASE_WIDTH 1191#define ESF_GZ_EV_256_EV32_TYPE_LBN 251192#define ESF_GZ_EV_256_EV32_TYPE_WIDTH 4193#define ESE_GZ_EF100_EVEW_VIRTQ_DESC 2194#define ESE_GZ_EF100_EVEW_TXQ_DESC 1195#define ESE_GZ_EF100_EVEW_64BIT 0196#define ESE_GZ_RHEAD_EW_EVENT_STRUCT_SIZE 256197 198/* RX_DESC */199#define ESF_GZ_RX_BUF_ADDR_LBN 0200#define ESF_GZ_RX_BUF_ADDR_WIDTH 64201#define ESE_GZ_RX_DESC_STRUCT_SIZE 64202 203/* TXQ_DESC_PROXY_EVENT */204#define ESF_GZ_EV_TXQ_DP_VI_ID_LBN 128205#define ESF_GZ_EV_TXQ_DP_VI_ID_WIDTH 16206#define ESF_GZ_EV_TXQ_DP_TXQ_DESC_LBN 0207#define ESF_GZ_EV_TXQ_DP_TXQ_DESC_WIDTH 128208#define ESE_GZ_TXQ_DESC_PROXY_EVENT_STRUCT_SIZE 144209 210/* TX_DESC_TYPE */211#define ESF_GZ_TX_DESC_TYPE_LBN 124212#define ESF_GZ_TX_DESC_TYPE_WIDTH 4213#define ESE_GZ_TX_DESC_TYPE_DESC2CMPT 7214#define ESE_GZ_TX_DESC_TYPE_MEM2MEM 4215#define ESE_GZ_TX_DESC_TYPE_SEG 3216#define ESE_GZ_TX_DESC_TYPE_TSO 2217#define ESE_GZ_TX_DESC_TYPE_PREFIX 1218#define ESE_GZ_TX_DESC_TYPE_SEND 0219#define ESE_GZ_TX_DESC_TYPE_STRUCT_SIZE 128220 221/* VIRTQ_DESC_PROXY_EVENT */222#define ESF_GZ_EV_VQ_DP_AVAIL_ENTRY_LBN 144223#define ESF_GZ_EV_VQ_DP_AVAIL_ENTRY_WIDTH 16224#define ESF_GZ_EV_VQ_DP_VI_ID_LBN 128225#define ESF_GZ_EV_VQ_DP_VI_ID_WIDTH 16226#define ESF_GZ_EV_VQ_DP_VIRTQ_DESC_LBN 0227#define ESF_GZ_EV_VQ_DP_VIRTQ_DESC_WIDTH 128228#define ESE_GZ_VIRTQ_DESC_PROXY_EVENT_STRUCT_SIZE 160229 230/* XIL_CFGBAR_TBL_ENTRY */231#define ESF_GZ_CFGBAR_CONT_CAP_OFF_HI_LBN 96232#define ESF_GZ_CFGBAR_CONT_CAP_OFF_HI_WIDTH 32233#define ESF_GZ_CFGBAR_CONT_CAP_OFFSET_LBN 68234#define ESF_GZ_CFGBAR_CONT_CAP_OFFSET_WIDTH 60235#define ESE_GZ_CONT_CAP_OFFSET_BYTES_SHIFT 4236#define ESF_GZ_CFGBAR_EF100_FUNC_CTL_WIN_OFF_LBN 67237#define ESF_GZ_CFGBAR_EF100_FUNC_CTL_WIN_OFF_WIDTH 29238#define ESE_GZ_EF100_FUNC_CTL_WIN_OFF_SHIFT 4239#define ESF_GZ_CFGBAR_CONT_CAP_OFF_LO_LBN 68240#define ESF_GZ_CFGBAR_CONT_CAP_OFF_LO_WIDTH 28241#define ESF_GZ_CFGBAR_CONT_CAP_RSV_LBN 67242#define ESF_GZ_CFGBAR_CONT_CAP_RSV_WIDTH 1243#define ESF_GZ_CFGBAR_EF100_BAR_LBN 64244#define ESF_GZ_CFGBAR_EF100_BAR_WIDTH 3245#define ESE_GZ_CFGBAR_EF100_BAR_NUM_INVALID 7246#define ESE_GZ_CFGBAR_EF100_BAR_NUM_EXPANSION_ROM 6247#define ESF_GZ_CFGBAR_CONT_CAP_BAR_LBN 64248#define ESF_GZ_CFGBAR_CONT_CAP_BAR_WIDTH 3249#define ESE_GZ_CFGBAR_CONT_CAP_BAR_NUM_INVALID 7250#define ESE_GZ_CFGBAR_CONT_CAP_BAR_NUM_EXPANSION_ROM 6251#define ESF_GZ_CFGBAR_ENTRY_SIZE_LBN 32252#define ESF_GZ_CFGBAR_ENTRY_SIZE_WIDTH 32253#define ESE_GZ_CFGBAR_ENTRY_SIZE_EF100 12254#define ESE_GZ_CFGBAR_ENTRY_HEADER_SIZE 8255#define ESF_GZ_CFGBAR_ENTRY_LAST_LBN 28256#define ESF_GZ_CFGBAR_ENTRY_LAST_WIDTH 1257#define ESF_GZ_CFGBAR_ENTRY_REV_LBN 20258#define ESF_GZ_CFGBAR_ENTRY_REV_WIDTH 8259#define ESE_GZ_CFGBAR_ENTRY_REV_EF100 0260#define ESF_GZ_CFGBAR_ENTRY_FORMAT_LBN 0261#define ESF_GZ_CFGBAR_ENTRY_FORMAT_WIDTH 20262#define ESE_GZ_CFGBAR_ENTRY_LAST 0xfffff263#define ESE_GZ_CFGBAR_ENTRY_CONT_CAP_ADDR 0xffffe264#define ESE_GZ_CFGBAR_ENTRY_EF100 0xef100265#define ESE_GZ_XIL_CFGBAR_TBL_ENTRY_STRUCT_SIZE 128266 267/* XIL_CFGBAR_VSEC */268#define ESF_GZ_VSEC_TBL_OFF_HI_LBN 64269#define ESF_GZ_VSEC_TBL_OFF_HI_WIDTH 32270#define ESE_GZ_VSEC_TBL_OFF_HI_BYTES_SHIFT 32271#define ESF_GZ_VSEC_TBL_OFF_LO_LBN 36272#define ESF_GZ_VSEC_TBL_OFF_LO_WIDTH 28273#define ESE_GZ_VSEC_TBL_OFF_LO_BYTES_SHIFT 4274#define ESF_GZ_VSEC_TBL_BAR_LBN 32275#define ESF_GZ_VSEC_TBL_BAR_WIDTH 4276#define ESE_GZ_VSEC_BAR_NUM_INVALID 7277#define ESE_GZ_VSEC_BAR_NUM_EXPANSION_ROM 6278#define ESF_GZ_VSEC_LEN_LBN 20279#define ESF_GZ_VSEC_LEN_WIDTH 12280#define ESE_GZ_VSEC_LEN_HIGH_OFFT 16281#define ESE_GZ_VSEC_LEN_MIN 12282#define ESF_GZ_VSEC_VER_LBN 16283#define ESF_GZ_VSEC_VER_WIDTH 4284#define ESE_GZ_VSEC_VER_XIL_CFGBAR 0285#define ESF_GZ_VSEC_ID_LBN 0286#define ESF_GZ_VSEC_ID_WIDTH 16287#define ESE_GZ_XILINX_VSEC_ID 0x20288#define ESE_GZ_XIL_CFGBAR_VSEC_STRUCT_SIZE 96289 290/* rh_egres_hclass */291#define ESF_GZ_RX_PREFIX_HCLASS_TUN_OUTER_L4_CSUM_LBN 15292#define ESF_GZ_RX_PREFIX_HCLASS_TUN_OUTER_L4_CSUM_WIDTH 1293#define ESF_GZ_RX_PREFIX_HCLASS_TUN_OUTER_L3_CLASS_LBN 13294#define ESF_GZ_RX_PREFIX_HCLASS_TUN_OUTER_L3_CLASS_WIDTH 2295#define ESF_GZ_RX_PREFIX_HCLASS_NT_OR_INNER_L4_CSUM_LBN 12296#define ESF_GZ_RX_PREFIX_HCLASS_NT_OR_INNER_L4_CSUM_WIDTH 1297#define ESF_GZ_RX_PREFIX_HCLASS_NT_OR_INNER_L4_CLASS_LBN 10298#define ESF_GZ_RX_PREFIX_HCLASS_NT_OR_INNER_L4_CLASS_WIDTH 2299#define ESF_GZ_RX_PREFIX_HCLASS_NT_OR_INNER_L3_CLASS_LBN 8300#define ESF_GZ_RX_PREFIX_HCLASS_NT_OR_INNER_L3_CLASS_WIDTH 2301#define ESF_GZ_RX_PREFIX_HCLASS_TUNNEL_CLASS_LBN 5302#define ESF_GZ_RX_PREFIX_HCLASS_TUNNEL_CLASS_WIDTH 3303#define ESF_GZ_RX_PREFIX_HCLASS_L2_N_VLAN_LBN 3304#define ESF_GZ_RX_PREFIX_HCLASS_L2_N_VLAN_WIDTH 2305#define ESF_GZ_RX_PREFIX_HCLASS_L2_CLASS_LBN 2306#define ESF_GZ_RX_PREFIX_HCLASS_L2_CLASS_WIDTH 1307#define ESF_GZ_RX_PREFIX_HCLASS_L2_STATUS_LBN 0308#define ESF_GZ_RX_PREFIX_HCLASS_L2_STATUS_WIDTH 2309#define ESE_GZ_RH_EGRES_HCLASS_STRUCT_SIZE 16310 311/* sf_driver */312#define ESF_GZ_DRIVER_E_TYPE_LBN 60313#define ESF_GZ_DRIVER_E_TYPE_WIDTH 4314#define ESF_GZ_DRIVER_PHASE_LBN 59315#define ESF_GZ_DRIVER_PHASE_WIDTH 1316#define ESF_GZ_DRIVER_DATA_LBN 0317#define ESF_GZ_DRIVER_DATA_WIDTH 59318#define ESE_GZ_SF_DRIVER_STRUCT_SIZE 64319 320/* sf_ev_rsvd */321#define ESF_GZ_EV_RSVD_TBD_NEXT_LBN 34322#define ESF_GZ_EV_RSVD_TBD_NEXT_WIDTH 3323#define ESF_GZ_EV_RSVD_EVENT_GEN_FLAGS_LBN 30324#define ESF_GZ_EV_RSVD_EVENT_GEN_FLAGS_WIDTH 4325#define ESF_GZ_EV_RSVD_SRC_QID_LBN 18326#define ESF_GZ_EV_RSVD_SRC_QID_WIDTH 12327#define ESF_GZ_EV_RSVD_SEQ_NUM_LBN 2328#define ESF_GZ_EV_RSVD_SEQ_NUM_WIDTH 16329#define ESF_GZ_EV_RSVD_TBD_LBN 0330#define ESF_GZ_EV_RSVD_TBD_WIDTH 2331#define ESE_GZ_SF_EV_RSVD_STRUCT_SIZE 37332 333/* sf_flush_evnt */334#define ESF_GZ_EV_FLSH_E_TYPE_LBN 60335#define ESF_GZ_EV_FLSH_E_TYPE_WIDTH 4336#define ESF_GZ_EV_FLSH_PHASE_LBN 59337#define ESF_GZ_EV_FLSH_PHASE_WIDTH 1338#define ESF_GZ_EV_FLSH_SUB_TYPE_LBN 53339#define ESF_GZ_EV_FLSH_SUB_TYPE_WIDTH 6340#define ESF_GZ_EV_FLSH_RSVD_LBN 10341#define ESF_GZ_EV_FLSH_RSVD_WIDTH 43342#define ESF_GZ_EV_FLSH_LABEL_LBN 4343#define ESF_GZ_EV_FLSH_LABEL_WIDTH 6344#define ESF_GZ_EV_FLSH_FLUSH_TYPE_LBN 0345#define ESF_GZ_EV_FLSH_FLUSH_TYPE_WIDTH 4346#define ESE_GZ_SF_FLUSH_EVNT_STRUCT_SIZE 64347 348/* sf_rx_pkts */349#define ESF_GZ_EV_RXPKTS_E_TYPE_LBN 60350#define ESF_GZ_EV_RXPKTS_E_TYPE_WIDTH 4351#define ESF_GZ_EV_RXPKTS_PHASE_LBN 59352#define ESF_GZ_EV_RXPKTS_PHASE_WIDTH 1353#define ESF_GZ_EV_RXPKTS_RSVD_LBN 22354#define ESF_GZ_EV_RXPKTS_RSVD_WIDTH 37355#define ESF_GZ_EV_RXPKTS_Q_LABEL_LBN 16356#define ESF_GZ_EV_RXPKTS_Q_LABEL_WIDTH 6357#define ESF_GZ_EV_RXPKTS_NUM_PKT_LBN 0358#define ESF_GZ_EV_RXPKTS_NUM_PKT_WIDTH 16359#define ESE_GZ_SF_RX_PKTS_STRUCT_SIZE 64360 361/* sf_rx_prefix */362#define ESF_GZ_RX_PREFIX_VLAN_STRIP_TCI_LBN 160363#define ESF_GZ_RX_PREFIX_VLAN_STRIP_TCI_WIDTH 16364#define ESF_GZ_RX_PREFIX_CSUM_FRAME_LBN 144365#define ESF_GZ_RX_PREFIX_CSUM_FRAME_WIDTH 16366#define ESF_GZ_RX_PREFIX_INGRESS_MPORT_LBN 128367#define ESF_GZ_RX_PREFIX_INGRESS_MPORT_WIDTH 16368#define ESF_GZ_RX_PREFIX_USER_MARK_LBN 96369#define ESF_GZ_RX_PREFIX_USER_MARK_WIDTH 32370#define ESF_GZ_RX_PREFIX_RSS_HASH_LBN 64371#define ESF_GZ_RX_PREFIX_RSS_HASH_WIDTH 32372#define ESF_GZ_RX_PREFIX_PARTIAL_TSTAMP_LBN 34373#define ESF_GZ_RX_PREFIX_PARTIAL_TSTAMP_WIDTH 30374#define ESF_GZ_RX_PREFIX_VSWITCH_STATUS_LBN 33375#define ESF_GZ_RX_PREFIX_VSWITCH_STATUS_WIDTH 1376#define ESF_GZ_RX_PREFIX_VLAN_STRIPPED_LBN 32377#define ESF_GZ_RX_PREFIX_VLAN_STRIPPED_WIDTH 1378#define ESF_GZ_RX_PREFIX_CLASS_LBN 16379#define ESF_GZ_RX_PREFIX_CLASS_WIDTH 16380#define ESF_GZ_RX_PREFIX_USER_FLAG_LBN 15381#define ESF_GZ_RX_PREFIX_USER_FLAG_WIDTH 1382#define ESF_GZ_RX_PREFIX_RSS_HASH_VALID_LBN 14383#define ESF_GZ_RX_PREFIX_RSS_HASH_VALID_WIDTH 1384#define ESF_GZ_RX_PREFIX_LENGTH_LBN 0385#define ESF_GZ_RX_PREFIX_LENGTH_WIDTH 14386#define ESE_GZ_SF_RX_PREFIX_STRUCT_SIZE 176387 388/* sf_rxtx_generic */389#define ESF_GZ_EV_BARRIER_LBN 167390#define ESF_GZ_EV_BARRIER_WIDTH 1391#define ESF_GZ_EV_RSVD_LBN 130392#define ESF_GZ_EV_RSVD_WIDTH 37393#define ESF_GZ_EV_DPRXY_LBN 129394#define ESF_GZ_EV_DPRXY_WIDTH 1395#define ESF_GZ_EV_VIRTIO_LBN 128396#define ESF_GZ_EV_VIRTIO_WIDTH 1397#define ESF_GZ_EV_COUNT_LBN 0398#define ESF_GZ_EV_COUNT_WIDTH 128399#define ESE_GZ_SF_RXTX_GENERIC_STRUCT_SIZE 168400 401/* sf_ts_stamp */402#define ESF_GZ_EV_TS_E_TYPE_LBN 60403#define ESF_GZ_EV_TS_E_TYPE_WIDTH 4404#define ESF_GZ_EV_TS_PHASE_LBN 59405#define ESF_GZ_EV_TS_PHASE_WIDTH 1406#define ESF_GZ_EV_TS_RSVD_LBN 56407#define ESF_GZ_EV_TS_RSVD_WIDTH 3408#define ESF_GZ_EV_TS_STATUS_LBN 54409#define ESF_GZ_EV_TS_STATUS_WIDTH 2410#define ESF_GZ_EV_TS_Q_LABEL_LBN 48411#define ESF_GZ_EV_TS_Q_LABEL_WIDTH 6412#define ESF_GZ_EV_TS_DESC_ID_LBN 32413#define ESF_GZ_EV_TS_DESC_ID_WIDTH 16414#define ESF_GZ_EV_TS_PARTIAL_STAMP_LBN 0415#define ESF_GZ_EV_TS_PARTIAL_STAMP_WIDTH 32416#define ESE_GZ_SF_TS_STAMP_STRUCT_SIZE 64417 418/* sf_tx_cmplt */419#define ESF_GZ_EV_TXCMPL_E_TYPE_LBN 60420#define ESF_GZ_EV_TXCMPL_E_TYPE_WIDTH 4421#define ESF_GZ_EV_TXCMPL_PHASE_LBN 59422#define ESF_GZ_EV_TXCMPL_PHASE_WIDTH 1423#define ESF_GZ_EV_TXCMPL_RSVD_LBN 22424#define ESF_GZ_EV_TXCMPL_RSVD_WIDTH 37425#define ESF_GZ_EV_TXCMPL_Q_LABEL_LBN 16426#define ESF_GZ_EV_TXCMPL_Q_LABEL_WIDTH 6427#define ESF_GZ_EV_TXCMPL_NUM_DESC_LBN 0428#define ESF_GZ_EV_TXCMPL_NUM_DESC_WIDTH 16429#define ESE_GZ_SF_TX_CMPLT_STRUCT_SIZE 64430 431/* sf_tx_desc2cmpt_dsc_fmt */432#define ESF_GZ_D2C_TGT_VI_ID_LBN 108433#define ESF_GZ_D2C_TGT_VI_ID_WIDTH 16434#define ESF_GZ_D2C_CMPT2_LBN 107435#define ESF_GZ_D2C_CMPT2_WIDTH 1436#define ESF_GZ_D2C_ABS_VI_ID_LBN 106437#define ESF_GZ_D2C_ABS_VI_ID_WIDTH 1438#define ESF_GZ_D2C_ORDERED_LBN 105439#define ESF_GZ_D2C_ORDERED_WIDTH 1440#define ESF_GZ_D2C_SKIP_N_LBN 97441#define ESF_GZ_D2C_SKIP_N_WIDTH 8442#define ESF_GZ_D2C_RSVD_LBN 64443#define ESF_GZ_D2C_RSVD_WIDTH 33444#define ESF_GZ_D2C_COMPLETION_LBN 0445#define ESF_GZ_D2C_COMPLETION_WIDTH 64446#define ESE_GZ_SF_TX_DESC2CMPT_DSC_FMT_STRUCT_SIZE 124447 448/* sf_tx_mem2mem_dsc_fmt */449#define ESF_GZ_M2M_ADDR_SPC_EN_LBN 123450#define ESF_GZ_M2M_ADDR_SPC_EN_WIDTH 1451#define ESF_GZ_M2M_TRANSLATE_ADDR_LBN 122452#define ESF_GZ_M2M_TRANSLATE_ADDR_WIDTH 1453#define ESF_GZ_M2M_RSVD_LBN 120454#define ESF_GZ_M2M_RSVD_WIDTH 2455#define ESF_GZ_M2M_ADDR_SPC_ID_LBN 84456#define ESF_GZ_M2M_ADDR_SPC_ID_WIDTH 36457#define ESF_GZ_M2M_LEN_MINUS_1_LBN 64458#define ESF_GZ_M2M_LEN_MINUS_1_WIDTH 20459#define ESF_GZ_M2M_ADDR_LBN 0460#define ESF_GZ_M2M_ADDR_WIDTH 64461#define ESE_GZ_SF_TX_MEM2MEM_DSC_FMT_STRUCT_SIZE 124462 463/* sf_tx_ovr_dsc_fmt */464#define ESF_GZ_TX_PREFIX_MARK_EN_LBN 123465#define ESF_GZ_TX_PREFIX_MARK_EN_WIDTH 1466#define ESF_GZ_TX_PREFIX_INGRESS_MPORT_EN_LBN 122467#define ESF_GZ_TX_PREFIX_INGRESS_MPORT_EN_WIDTH 1468#define ESF_GZ_TX_PREFIX_INLINE_CAPSULE_META_LBN 121469#define ESF_GZ_TX_PREFIX_INLINE_CAPSULE_META_WIDTH 1470#define ESF_GZ_TX_PREFIX_EGRESS_MPORT_EN_LBN 120471#define ESF_GZ_TX_PREFIX_EGRESS_MPORT_EN_WIDTH 1472#define ESF_GZ_TX_PREFIX_RSRVD_LBN 64473#define ESF_GZ_TX_PREFIX_RSRVD_WIDTH 56474#define ESF_GZ_TX_PREFIX_EGRESS_MPORT_LBN 48475#define ESF_GZ_TX_PREFIX_EGRESS_MPORT_WIDTH 16476#define ESF_GZ_TX_PREFIX_INGRESS_MPORT_LBN 32477#define ESF_GZ_TX_PREFIX_INGRESS_MPORT_WIDTH 16478#define ESF_GZ_TX_PREFIX_MARK_LBN 0479#define ESF_GZ_TX_PREFIX_MARK_WIDTH 32480#define ESE_GZ_SF_TX_OVR_DSC_FMT_STRUCT_SIZE 124481 482/* sf_tx_seg_dsc_fmt */483#define ESF_GZ_TX_SEG_ADDR_SPC_EN_LBN 123484#define ESF_GZ_TX_SEG_ADDR_SPC_EN_WIDTH 1485#define ESF_GZ_TX_SEG_TRANSLATE_ADDR_LBN 122486#define ESF_GZ_TX_SEG_TRANSLATE_ADDR_WIDTH 1487#define ESF_GZ_TX_SEG_RSVD2_LBN 120488#define ESF_GZ_TX_SEG_RSVD2_WIDTH 2489#define ESF_GZ_TX_SEG_ADDR_SPC_ID_LBN 84490#define ESF_GZ_TX_SEG_ADDR_SPC_ID_WIDTH 36491#define ESF_GZ_TX_SEG_RSVD_LBN 80492#define ESF_GZ_TX_SEG_RSVD_WIDTH 4493#define ESF_GZ_TX_SEG_LEN_LBN 64494#define ESF_GZ_TX_SEG_LEN_WIDTH 16495#define ESF_GZ_TX_SEG_ADDR_LBN 0496#define ESF_GZ_TX_SEG_ADDR_WIDTH 64497#define ESE_GZ_SF_TX_SEG_DSC_FMT_STRUCT_SIZE 124498 499/* sf_tx_std_dsc_fmt */500#define ESF_GZ_TX_SEND_VLAN_INSERT_TCI_LBN 108501#define ESF_GZ_TX_SEND_VLAN_INSERT_TCI_WIDTH 16502#define ESF_GZ_TX_SEND_VLAN_INSERT_EN_LBN 107503#define ESF_GZ_TX_SEND_VLAN_INSERT_EN_WIDTH 1504#define ESF_GZ_TX_SEND_TSTAMP_REQ_LBN 106505#define ESF_GZ_TX_SEND_TSTAMP_REQ_WIDTH 1506#define ESF_GZ_TX_SEND_CSO_OUTER_L4_LBN 105507#define ESF_GZ_TX_SEND_CSO_OUTER_L4_WIDTH 1508#define ESF_GZ_TX_SEND_CSO_OUTER_L3_LBN 104509#define ESF_GZ_TX_SEND_CSO_OUTER_L3_WIDTH 1510#define ESF_GZ_TX_SEND_CSO_INNER_L3_LBN 101511#define ESF_GZ_TX_SEND_CSO_INNER_L3_WIDTH 3512#define ESF_GZ_TX_SEND_RSVD_LBN 99513#define ESF_GZ_TX_SEND_RSVD_WIDTH 2514#define ESF_GZ_TX_SEND_CSO_PARTIAL_EN_LBN 97515#define ESF_GZ_TX_SEND_CSO_PARTIAL_EN_WIDTH 2516#define ESF_GZ_TX_SEND_CSO_PARTIAL_CSUM_W_LBN 92517#define ESF_GZ_TX_SEND_CSO_PARTIAL_CSUM_W_WIDTH 5518#define ESF_GZ_TX_SEND_CSO_PARTIAL_START_W_LBN 83519#define ESF_GZ_TX_SEND_CSO_PARTIAL_START_W_WIDTH 9520#define ESF_GZ_TX_SEND_NUM_SEGS_LBN 78521#define ESF_GZ_TX_SEND_NUM_SEGS_WIDTH 5522#define ESF_GZ_TX_SEND_LEN_LBN 64523#define ESF_GZ_TX_SEND_LEN_WIDTH 14524#define ESF_GZ_TX_SEND_ADDR_LBN 0525#define ESF_GZ_TX_SEND_ADDR_WIDTH 64526#define ESE_GZ_SF_TX_STD_DSC_FMT_STRUCT_SIZE 124527 528/* sf_tx_tso_dsc_fmt */529#define ESF_GZ_TX_TSO_VLAN_INSERT_TCI_LBN 108530#define ESF_GZ_TX_TSO_VLAN_INSERT_TCI_WIDTH 16531#define ESF_GZ_TX_TSO_VLAN_INSERT_EN_LBN 107532#define ESF_GZ_TX_TSO_VLAN_INSERT_EN_WIDTH 1533#define ESF_GZ_TX_TSO_TSTAMP_REQ_LBN 106534#define ESF_GZ_TX_TSO_TSTAMP_REQ_WIDTH 1535#define ESF_GZ_TX_TSO_CSO_OUTER_L4_LBN 105536#define ESF_GZ_TX_TSO_CSO_OUTER_L4_WIDTH 1537#define ESF_GZ_TX_TSO_CSO_OUTER_L3_LBN 104538#define ESF_GZ_TX_TSO_CSO_OUTER_L3_WIDTH 1539#define ESF_GZ_TX_TSO_CSO_INNER_L3_LBN 101540#define ESF_GZ_TX_TSO_CSO_INNER_L3_WIDTH 3541#define ESF_GZ_TX_TSO_RSVD_LBN 94542#define ESF_GZ_TX_TSO_RSVD_WIDTH 7543#define ESF_GZ_TX_TSO_CSO_INNER_L4_LBN 93544#define ESF_GZ_TX_TSO_CSO_INNER_L4_WIDTH 1545#define ESF_GZ_TX_TSO_INNER_L4_OFF_W_LBN 85546#define ESF_GZ_TX_TSO_INNER_L4_OFF_W_WIDTH 8547#define ESF_GZ_TX_TSO_INNER_L3_OFF_W_LBN 77548#define ESF_GZ_TX_TSO_INNER_L3_OFF_W_WIDTH 8549#define ESF_GZ_TX_TSO_OUTER_L4_OFF_W_LBN 69550#define ESF_GZ_TX_TSO_OUTER_L4_OFF_W_WIDTH 8551#define ESF_GZ_TX_TSO_OUTER_L3_OFF_W_LBN 64552#define ESF_GZ_TX_TSO_OUTER_L3_OFF_W_WIDTH 5553#define ESF_GZ_TX_TSO_PAYLOAD_LEN_LBN 42554#define ESF_GZ_TX_TSO_PAYLOAD_LEN_WIDTH 22555#define ESF_GZ_TX_TSO_HDR_LEN_W_LBN 34556#define ESF_GZ_TX_TSO_HDR_LEN_W_WIDTH 8557#define ESF_GZ_TX_TSO_ED_OUTER_UDP_LEN_LBN 33558#define ESF_GZ_TX_TSO_ED_OUTER_UDP_LEN_WIDTH 1559#define ESF_GZ_TX_TSO_ED_INNER_IP_LEN_LBN 32560#define ESF_GZ_TX_TSO_ED_INNER_IP_LEN_WIDTH 1561#define ESF_GZ_TX_TSO_ED_OUTER_IP_LEN_LBN 31562#define ESF_GZ_TX_TSO_ED_OUTER_IP_LEN_WIDTH 1563#define ESF_GZ_TX_TSO_ED_INNER_IP4_ID_LBN 29564#define ESF_GZ_TX_TSO_ED_INNER_IP4_ID_WIDTH 2565#define ESF_GZ_TX_TSO_ED_OUTER_IP4_ID_LBN 27566#define ESF_GZ_TX_TSO_ED_OUTER_IP4_ID_WIDTH 2567#define ESF_GZ_TX_TSO_PAYLOAD_NUM_SEGS_LBN 17568#define ESF_GZ_TX_TSO_PAYLOAD_NUM_SEGS_WIDTH 10569#define ESF_GZ_TX_TSO_HDR_NUM_SEGS_LBN 14570#define ESF_GZ_TX_TSO_HDR_NUM_SEGS_WIDTH 3571#define ESF_GZ_TX_TSO_MSS_LBN 0572#define ESF_GZ_TX_TSO_MSS_WIDTH 14573#define ESE_GZ_SF_TX_TSO_DSC_FMT_STRUCT_SIZE 124574 575 576/* Enum D2VIO_MSG_OP */577#define ESE_GZ_QUE_JBDNE 3578#define ESE_GZ_QUE_EVICT 2579#define ESE_GZ_QUE_EMPTY 1580#define ESE_GZ_NOP 0581 582/* Enum DESIGN_PARAMS */583#define ESE_EF100_DP_GZ_RX_MAX_RUNT 17584#define ESE_EF100_DP_GZ_VI_STRIDES 16585#define ESE_EF100_DP_GZ_NMMU_PAGE_SIZES 15586#define ESE_EF100_DP_GZ_EVQ_TIMER_TICK_NANOS 14587#define ESE_EF100_DP_GZ_MEM2MEM_MAX_LEN 13588#define ESE_EF100_DP_GZ_COMPAT 12589#define ESE_EF100_DP_GZ_TSO_MAX_NUM_FRAMES 11590#define ESE_EF100_DP_GZ_TSO_MAX_PAYLOAD_NUM_SEGS 10591#define ESE_EF100_DP_GZ_TSO_MAX_PAYLOAD_LEN 9592#define ESE_EF100_DP_GZ_TXQ_SIZE_GRANULARITY 8593#define ESE_EF100_DP_GZ_RXQ_SIZE_GRANULARITY 7594#define ESE_EF100_DP_GZ_TSO_MAX_HDR_NUM_SEGS 6595#define ESE_EF100_DP_GZ_TSO_MAX_HDR_LEN 5596#define ESE_EF100_DP_GZ_RX_L4_CSUM_PROTOCOLS 4597#define ESE_EF100_DP_GZ_NMMU_GROUP_SIZE 3598#define ESE_EF100_DP_GZ_EVQ_UNSOL_CREDIT_SEQ_BITS 2599#define ESE_EF100_DP_GZ_PARTIAL_TSTAMP_SUB_NANO_BITS 1600#define ESE_EF100_DP_GZ_PAD 0601 602/* Enum DESIGN_PARAM_DEFAULTS */603#define ESE_EF100_DP_GZ_TSO_MAX_PAYLOAD_LEN_DEFAULT 0x3fffff604#define ESE_EF100_DP_GZ_TSO_MAX_NUM_FRAMES_DEFAULT 8192605#define ESE_EF100_DP_GZ_MEM2MEM_MAX_LEN_DEFAULT 8192606#define ESE_EF100_DP_GZ_RX_L4_CSUM_PROTOCOLS_DEFAULT 0x1106607#define ESE_EF100_DP_GZ_TSO_MAX_PAYLOAD_NUM_SEGS_DEFAULT 0x3ff608#define ESE_EF100_DP_GZ_RX_MAX_RUNT_DEFAULT 640609#define ESE_EF100_DP_GZ_EVQ_TIMER_TICK_NANOS_DEFAULT 512610#define ESE_EF100_DP_GZ_NMMU_PAGE_SIZES_DEFAULT 512611#define ESE_EF100_DP_GZ_TSO_MAX_HDR_LEN_DEFAULT 192612#define ESE_EF100_DP_GZ_RXQ_SIZE_GRANULARITY_DEFAULT 64613#define ESE_EF100_DP_GZ_TXQ_SIZE_GRANULARITY_DEFAULT 64614#define ESE_EF100_DP_GZ_NMMU_GROUP_SIZE_DEFAULT 32615#define ESE_EF100_DP_GZ_VI_STRIDES_DEFAULT 16616#define ESE_EF100_DP_GZ_EVQ_UNSOL_CREDIT_SEQ_BITS_DEFAULT 7617#define ESE_EF100_DP_GZ_TSO_MAX_HDR_NUM_SEGS_DEFAULT 4618#define ESE_EF100_DP_GZ_PARTIAL_TSTAMP_SUB_NANO_BITS_DEFAULT 2619#define ESE_EF100_DP_GZ_COMPAT_DEFAULT 0620 621/* Enum HOST_IF_CONSTANTS */622#define ESE_GZ_FCW_LEN 0x4C623#define ESE_GZ_RX_PKT_PREFIX_LEN 22624 625/* Enum PCI_CONSTANTS */626#define ESE_GZ_PCI_BASE_CONFIG_SPACE_SIZE 256627#define ESE_GZ_PCI_EXPRESS_XCAP_HDR_SIZE 4628 629/* Enum RH_DSC_TYPE */630#define ESE_GZ_TX_TOMB 0xF631#define ESE_GZ_TX_VIO 0xE632#define ESE_GZ_TX_TSO_OVRRD 0x8633#define ESE_GZ_TX_D2CMP 0x7634#define ESE_GZ_TX_DATA 0x6635#define ESE_GZ_TX_D2M 0x5636#define ESE_GZ_TX_M2M 0x4637#define ESE_GZ_TX_SEG 0x3638#define ESE_GZ_TX_TSO 0x2639#define ESE_GZ_TX_OVRRD 0x1640#define ESE_GZ_TX_SEND 0x0641 642/* Enum RH_HCLASS_L2_CLASS */643#define ESE_GZ_RH_HCLASS_L2_CLASS_E2_0123VLAN 1644#define ESE_GZ_RH_HCLASS_L2_CLASS_OTHER 0645 646/* Enum RH_HCLASS_L2_STATUS */647#define ESE_GZ_RH_HCLASS_L2_STATUS_RESERVED 3648#define ESE_GZ_RH_HCLASS_L2_STATUS_FCS_ERR 2649#define ESE_GZ_RH_HCLASS_L2_STATUS_LEN_ERR 1650#define ESE_GZ_RH_HCLASS_L2_STATUS_OK 0651 652/* Enum RH_HCLASS_L3_CLASS */653#define ESE_GZ_RH_HCLASS_L3_CLASS_OTHER 3654#define ESE_GZ_RH_HCLASS_L3_CLASS_IP6 2655#define ESE_GZ_RH_HCLASS_L3_CLASS_IP4BAD 1656#define ESE_GZ_RH_HCLASS_L3_CLASS_IP4GOOD 0657 658/* Enum RH_HCLASS_L4_CLASS */659#define ESE_GZ_RH_HCLASS_L4_CLASS_OTHER 3660#define ESE_GZ_RH_HCLASS_L4_CLASS_FRAG 2661#define ESE_GZ_RH_HCLASS_L4_CLASS_UDP 1662#define ESE_GZ_RH_HCLASS_L4_CLASS_TCP 0663 664/* Enum RH_HCLASS_L4_CSUM */665#define ESE_GZ_RH_HCLASS_L4_CSUM_GOOD 1666#define ESE_GZ_RH_HCLASS_L4_CSUM_BAD_OR_UNKNOWN 0667 668/* Enum RH_HCLASS_TUNNEL_CLASS */669#define ESE_GZ_RH_HCLASS_TUNNEL_CLASS_RESERVED_7 7670#define ESE_GZ_RH_HCLASS_TUNNEL_CLASS_RESERVED_6 6671#define ESE_GZ_RH_HCLASS_TUNNEL_CLASS_RESERVED_5 5672#define ESE_GZ_RH_HCLASS_TUNNEL_CLASS_RESERVED_4 4673#define ESE_GZ_RH_HCLASS_TUNNEL_CLASS_GENEVE 3674#define ESE_GZ_RH_HCLASS_TUNNEL_CLASS_NVGRE 2675#define ESE_GZ_RH_HCLASS_TUNNEL_CLASS_VXLAN 1676#define ESE_GZ_RH_HCLASS_TUNNEL_CLASS_NONE 0677 678/* Enum SF_CTL_EVENT_SUBTYPE */679#define ESE_GZ_EF100_CTL_EV_EVQ_TIMEOUT 0x3680#define ESE_GZ_EF100_CTL_EV_FLUSH 0x2681#define ESE_GZ_EF100_CTL_EV_TIME_SYNC 0x1682#define ESE_GZ_EF100_CTL_EV_UNSOL_OVERFLOW 0x0683 684/* Enum SF_EVENT_TYPE */685#define ESE_GZ_EF100_EV_DRIVER 0x5686#define ESE_GZ_EF100_EV_MCDI 0x4687#define ESE_GZ_EF100_EV_CONTROL 0x3688#define ESE_GZ_EF100_EV_TX_TIMESTAMP 0x2689#define ESE_GZ_EF100_EV_TX_COMPLETION 0x1690#define ESE_GZ_EF100_EV_RX_PKTS 0x0691 692/* Enum SF_EW_EVENT_TYPE */693#define ESE_GZ_EF100_EWEV_VIRTQ_DESC 0x2694#define ESE_GZ_EF100_EWEV_TXQ_DESC 0x1695#define ESE_GZ_EF100_EWEV_64BIT 0x0696 697/* Enum TX_DESC_CSO_PARTIAL_EN */698#define ESE_GZ_TX_DESC_CSO_PARTIAL_EN_TCP 2699#define ESE_GZ_TX_DESC_CSO_PARTIAL_EN_UDP 1700#define ESE_GZ_TX_DESC_CSO_PARTIAL_EN_OFF 0701 702/* Enum TX_DESC_CS_INNER_L3 */703#define ESE_GZ_TX_DESC_CS_INNER_L3_GENEVE 3704#define ESE_GZ_TX_DESC_CS_INNER_L3_NVGRE 2705#define ESE_GZ_TX_DESC_CS_INNER_L3_VXLAN 1706#define ESE_GZ_TX_DESC_CS_INNER_L3_OFF 0707 708/* Enum TX_DESC_IP4_ID */709#define ESE_GZ_TX_DESC_IP4_ID_INC_MOD16 2710#define ESE_GZ_TX_DESC_IP4_ID_INC_MOD15 1711#define ESE_GZ_TX_DESC_IP4_ID_NO_OP 0712 713/* Enum VIRTIO_NET_HDR_F */714#define ESE_GZ_NEEDS_CSUM 0x1715 716/* Enum VIRTIO_NET_HDR_GSO */717#define ESE_GZ_TCPV6 0x4718#define ESE_GZ_UDP 0x3719#define ESE_GZ_TCPV4 0x1720#define ESE_GZ_NONE 0x0721/**************************************************************************/722 723#define ESF_GZ_EV_DEBUG_EVENT_GEN_FLAGS_LBN 44724#define ESF_GZ_EV_DEBUG_EVENT_GEN_FLAGS_WIDTH 4725#define ESF_GZ_EV_DEBUG_SRC_QID_LBN 32726#define ESF_GZ_EV_DEBUG_SRC_QID_WIDTH 12727#define ESF_GZ_EV_DEBUG_SEQ_NUM_LBN 16728#define ESF_GZ_EV_DEBUG_SEQ_NUM_WIDTH 16729 730#endif /* EFX_EF100_REGS_H */731