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1/* SPDX-License-Identifier: GPL-2.0-only */2/****************************************************************************3 * Driver for Solarflare network controllers and boards4 * Copyright 2012-2017 Solarflare Communications Inc.5 */6 7#ifndef EFX_EF10_REGS_H8#define EFX_EF10_REGS_H9 10/* EF10 hardware architecture definitions have a name prefix following11 * the format:12 *13 * E<type>_<min-rev><max-rev>_14 *15 * The following <type> strings are used:16 *17 * MMIO register Host memory structure18 * -------------------------------------------------------------19 * Address R20 * Bitfield RF SF21 * Enumerator FE SE22 *23 * <min-rev> is the first revision to which the definition applies:24 *25 * D: Huntington A026 *27 * If the definition has been changed or removed in later revisions28 * then <max-rev> is the last revision to which the definition applies;29 * otherwise it is "Z".30 */31 32/**************************************************************************33 *34 * EF10 registers and descriptors35 *36 **************************************************************************37 */38 39/* BIU_HW_REV_ID_REG: */40#define ER_DZ_BIU_HW_REV_ID 0x0000000041#define ERF_DZ_HW_REV_ID_LBN 042#define ERF_DZ_HW_REV_ID_WIDTH 3243 44/* BIU_MC_SFT_STATUS_REG: */45#define ER_DZ_BIU_MC_SFT_STATUS 0x0000001046#define ER_DZ_BIU_MC_SFT_STATUS_STEP 447#define ER_DZ_BIU_MC_SFT_STATUS_ROWS 848#define ERF_DZ_MC_SFT_STATUS_LBN 049#define ERF_DZ_MC_SFT_STATUS_WIDTH 3250 51/* BIU_INT_ISR_REG: */52#define ER_DZ_BIU_INT_ISR 0x0000009053#define ERF_DZ_ISR_REG_LBN 054#define ERF_DZ_ISR_REG_WIDTH 3255 56/* MC_DB_LWRD_REG: */57#define ER_DZ_MC_DB_LWRD 0x0000020058#define ERF_DZ_MC_DOORBELL_L_LBN 059#define ERF_DZ_MC_DOORBELL_L_WIDTH 3260 61/* MC_DB_HWRD_REG: */62#define ER_DZ_MC_DB_HWRD 0x0000020463#define ERF_DZ_MC_DOORBELL_H_LBN 064#define ERF_DZ_MC_DOORBELL_H_WIDTH 3265 66/* EVQ_RPTR_REG: */67#define ER_DZ_EVQ_RPTR 0x0000040068#define ER_DZ_EVQ_RPTR_STEP 819269#define ER_DZ_EVQ_RPTR_ROWS 204870#define ERF_DZ_EVQ_RPTR_VLD_LBN 1571#define ERF_DZ_EVQ_RPTR_VLD_WIDTH 172#define ERF_DZ_EVQ_RPTR_LBN 073#define ERF_DZ_EVQ_RPTR_WIDTH 1574 75/* EVQ_TMR_REG: */76#define ER_DZ_EVQ_TMR 0x0000042077#define ER_DZ_EVQ_TMR_STEP 819278#define ER_DZ_EVQ_TMR_ROWS 204879#define ERF_FZ_TC_TMR_REL_VAL_LBN 1680#define ERF_FZ_TC_TMR_REL_VAL_WIDTH 1481#define ERF_DZ_TC_TIMER_MODE_LBN 1482#define ERF_DZ_TC_TIMER_MODE_WIDTH 283#define ERF_DZ_TC_TIMER_VAL_LBN 084#define ERF_DZ_TC_TIMER_VAL_WIDTH 1485 86/* RX_DESC_UPD_REG: */87#define ER_DZ_RX_DESC_UPD 0x0000083088#define ER_DZ_RX_DESC_UPD_STEP 819289#define ER_DZ_RX_DESC_UPD_ROWS 204890#define ERF_DZ_RX_DESC_WPTR_LBN 091#define ERF_DZ_RX_DESC_WPTR_WIDTH 1292 93/* TX_DESC_UPD_REG: */94#define ER_DZ_TX_DESC_UPD 0x00000a1095#define ER_DZ_TX_DESC_UPD_STEP 819296#define ER_DZ_TX_DESC_UPD_ROWS 204897#define ERF_DZ_RSVD_LBN 7698#define ERF_DZ_RSVD_WIDTH 2099#define ERF_DZ_TX_DESC_WPTR_LBN 64100#define ERF_DZ_TX_DESC_WPTR_WIDTH 12101#define ERF_DZ_TX_DESC_HWORD_LBN 32102#define ERF_DZ_TX_DESC_HWORD_WIDTH 32103#define ERF_DZ_TX_DESC_LWORD_LBN 0104#define ERF_DZ_TX_DESC_LWORD_WIDTH 32105 106/* DRIVER_EV */107#define ESF_DZ_DRV_CODE_LBN 60108#define ESF_DZ_DRV_CODE_WIDTH 4109#define ESF_DZ_DRV_SUB_CODE_LBN 56110#define ESF_DZ_DRV_SUB_CODE_WIDTH 4111#define ESE_DZ_DRV_TIMER_EV 3112#define ESE_DZ_DRV_START_UP_EV 2113#define ESE_DZ_DRV_WAKE_UP_EV 1114#define ESF_DZ_DRV_SUB_DATA_LBN 0115#define ESF_DZ_DRV_SUB_DATA_WIDTH 56116#define ESF_DZ_DRV_EVQ_ID_LBN 0117#define ESF_DZ_DRV_EVQ_ID_WIDTH 14118#define ESF_DZ_DRV_TMR_ID_LBN 0119#define ESF_DZ_DRV_TMR_ID_WIDTH 14120 121/* EVENT_ENTRY */122#define ESF_DZ_EV_CODE_LBN 60123#define ESF_DZ_EV_CODE_WIDTH 4124#define ESE_DZ_EV_CODE_MCDI_EV 12125#define ESE_DZ_EV_CODE_DRIVER_EV 5126#define ESE_DZ_EV_CODE_TX_EV 2127#define ESE_DZ_EV_CODE_RX_EV 0128#define ESE_DZ_OTHER other129#define ESF_DZ_EV_DATA_LBN 0130#define ESF_DZ_EV_DATA_WIDTH 60131 132/* MC_EVENT */133#define ESF_DZ_MC_CODE_LBN 60134#define ESF_DZ_MC_CODE_WIDTH 4135#define ESF_DZ_MC_OVERRIDE_HOLDOFF_LBN 59136#define ESF_DZ_MC_OVERRIDE_HOLDOFF_WIDTH 1137#define ESF_DZ_MC_DROP_EVENT_LBN 58138#define ESF_DZ_MC_DROP_EVENT_WIDTH 1139#define ESF_DZ_MC_SOFT_LBN 0140#define ESF_DZ_MC_SOFT_WIDTH 58141 142/* RX_EVENT */143#define ESF_DZ_RX_CODE_LBN 60144#define ESF_DZ_RX_CODE_WIDTH 4145#define ESF_DZ_RX_OVERRIDE_HOLDOFF_LBN 59146#define ESF_DZ_RX_OVERRIDE_HOLDOFF_WIDTH 1147#define ESF_DZ_RX_DROP_EVENT_LBN 58148#define ESF_DZ_RX_DROP_EVENT_WIDTH 1149#define ESF_DD_RX_EV_RSVD2_LBN 54150#define ESF_DD_RX_EV_RSVD2_WIDTH 4151#define ESF_EZ_RX_TCP_UDP_INNER_CHKSUM_ERR_LBN 57152#define ESF_EZ_RX_TCP_UDP_INNER_CHKSUM_ERR_WIDTH 1153#define ESF_EZ_RX_IP_INNER_CHKSUM_ERR_LBN 56154#define ESF_EZ_RX_IP_INNER_CHKSUM_ERR_WIDTH 1155#define ESF_EZ_RX_EV_RSVD2_LBN 54156#define ESF_EZ_RX_EV_RSVD2_WIDTH 2157#define ESF_DZ_RX_EV_SOFT2_LBN 52158#define ESF_DZ_RX_EV_SOFT2_WIDTH 2159#define ESF_DZ_RX_DSC_PTR_LBITS_LBN 48160#define ESF_DZ_RX_DSC_PTR_LBITS_WIDTH 4161#define ESF_DE_RX_L4_CLASS_LBN 45162#define ESF_DE_RX_L4_CLASS_WIDTH 3163#define ESE_DE_L4_CLASS_RSVD7 7164#define ESE_DE_L4_CLASS_RSVD6 6165#define ESE_DE_L4_CLASS_RSVD5 5166#define ESE_DE_L4_CLASS_RSVD4 4167#define ESE_DE_L4_CLASS_RSVD3 3168#define ESE_DE_L4_CLASS_UDP 2169#define ESE_DE_L4_CLASS_TCP 1170#define ESE_DE_L4_CLASS_UNKNOWN 0171#define ESF_FZ_RX_FASTPD_INDCTR_LBN 47172#define ESF_FZ_RX_FASTPD_INDCTR_WIDTH 1173#define ESF_FZ_RX_L4_CLASS_LBN 45174#define ESF_FZ_RX_L4_CLASS_WIDTH 2175#define ESE_FZ_L4_CLASS_RSVD3 3176#define ESE_FZ_L4_CLASS_UDP 2177#define ESE_FZ_L4_CLASS_TCP 1178#define ESE_FZ_L4_CLASS_UNKNOWN 0179#define ESF_DZ_RX_L3_CLASS_LBN 42180#define ESF_DZ_RX_L3_CLASS_WIDTH 3181#define ESE_DZ_L3_CLASS_RSVD7 7182#define ESE_DZ_L3_CLASS_IP6_FRAG 6183#define ESE_DZ_L3_CLASS_ARP 5184#define ESE_DZ_L3_CLASS_IP4_FRAG 4185#define ESE_DZ_L3_CLASS_FCOE 3186#define ESE_DZ_L3_CLASS_IP6 2187#define ESE_DZ_L3_CLASS_IP4 1188#define ESE_DZ_L3_CLASS_UNKNOWN 0189#define ESF_DZ_RX_ETH_TAG_CLASS_LBN 39190#define ESF_DZ_RX_ETH_TAG_CLASS_WIDTH 3191#define ESE_DZ_ETH_TAG_CLASS_RSVD7 7192#define ESE_DZ_ETH_TAG_CLASS_RSVD6 6193#define ESE_DZ_ETH_TAG_CLASS_RSVD5 5194#define ESE_DZ_ETH_TAG_CLASS_RSVD4 4195#define ESE_DZ_ETH_TAG_CLASS_RSVD3 3196#define ESE_DZ_ETH_TAG_CLASS_VLAN2 2197#define ESE_DZ_ETH_TAG_CLASS_VLAN1 1198#define ESE_DZ_ETH_TAG_CLASS_NONE 0199#define ESF_DZ_RX_ETH_BASE_CLASS_LBN 36200#define ESF_DZ_RX_ETH_BASE_CLASS_WIDTH 3201#define ESE_DZ_ETH_BASE_CLASS_LLC_SNAP 2202#define ESE_DZ_ETH_BASE_CLASS_LLC 1203#define ESE_DZ_ETH_BASE_CLASS_ETH2 0204#define ESF_DZ_RX_MAC_CLASS_LBN 35205#define ESF_DZ_RX_MAC_CLASS_WIDTH 1206#define ESE_DZ_MAC_CLASS_MCAST 1207#define ESE_DZ_MAC_CLASS_UCAST 0208#define ESF_DD_RX_EV_SOFT1_LBN 32209#define ESF_DD_RX_EV_SOFT1_WIDTH 3210#define ESF_EZ_RX_EV_SOFT1_LBN 34211#define ESF_EZ_RX_EV_SOFT1_WIDTH 1212#define ESF_EZ_RX_ENCAP_HDR_LBN 32213#define ESF_EZ_RX_ENCAP_HDR_WIDTH 2214#define ESE_EZ_ENCAP_HDR_GRE 2215#define ESE_EZ_ENCAP_HDR_VXLAN 1216#define ESE_EZ_ENCAP_HDR_NONE 0217#define ESF_DD_RX_EV_RSVD1_LBN 30218#define ESF_DD_RX_EV_RSVD1_WIDTH 2219#define ESF_EZ_RX_EV_RSVD1_LBN 31220#define ESF_EZ_RX_EV_RSVD1_WIDTH 1221#define ESF_EZ_RX_ABORT_LBN 30222#define ESF_EZ_RX_ABORT_WIDTH 1223#define ESF_DZ_RX_ECC_ERR_LBN 29224#define ESF_DZ_RX_ECC_ERR_WIDTH 1225#define ESF_DZ_RX_TRUNC_ERR_LBN 29226#define ESF_DZ_RX_TRUNC_ERR_WIDTH 1227#define ESF_DZ_RX_CRC1_ERR_LBN 28228#define ESF_DZ_RX_CRC1_ERR_WIDTH 1229#define ESF_DZ_RX_CRC0_ERR_LBN 27230#define ESF_DZ_RX_CRC0_ERR_WIDTH 1231#define ESF_DZ_RX_TCPUDP_CKSUM_ERR_LBN 26232#define ESF_DZ_RX_TCPUDP_CKSUM_ERR_WIDTH 1233#define ESF_DZ_RX_IPCKSUM_ERR_LBN 25234#define ESF_DZ_RX_IPCKSUM_ERR_WIDTH 1235#define ESF_DZ_RX_ECRC_ERR_LBN 24236#define ESF_DZ_RX_ECRC_ERR_WIDTH 1237#define ESF_DZ_RX_QLABEL_LBN 16238#define ESF_DZ_RX_QLABEL_WIDTH 5239#define ESF_DZ_RX_PARSE_INCOMPLETE_LBN 15240#define ESF_DZ_RX_PARSE_INCOMPLETE_WIDTH 1241#define ESF_DZ_RX_CONT_LBN 14242#define ESF_DZ_RX_CONT_WIDTH 1243#define ESF_DZ_RX_BYTES_LBN 0244#define ESF_DZ_RX_BYTES_WIDTH 14245 246/* RX_KER_DESC */247#define ESF_DZ_RX_KER_RESERVED_LBN 62248#define ESF_DZ_RX_KER_RESERVED_WIDTH 2249#define ESF_DZ_RX_KER_BYTE_CNT_LBN 48250#define ESF_DZ_RX_KER_BYTE_CNT_WIDTH 14251#define ESF_DZ_RX_KER_BUF_ADDR_LBN 0252#define ESF_DZ_RX_KER_BUF_ADDR_WIDTH 48253 254/* TX_CSUM_TSTAMP_DESC */255#define ESF_DZ_TX_DESC_IS_OPT_LBN 63256#define ESF_DZ_TX_DESC_IS_OPT_WIDTH 1257#define ESF_DZ_TX_OPTION_TYPE_LBN 60258#define ESF_DZ_TX_OPTION_TYPE_WIDTH 3259#define ESE_DZ_TX_OPTION_DESC_TSO 7260#define ESE_DZ_TX_OPTION_DESC_VLAN 6261#define ESE_DZ_TX_OPTION_DESC_CRC_CSUM 0262#define ESF_DZ_TX_OPTION_TS_AT_TXDP_LBN 8263#define ESF_DZ_TX_OPTION_TS_AT_TXDP_WIDTH 1264#define ESF_DZ_TX_OPTION_INNER_UDP_TCP_CSUM_LBN 7265#define ESF_DZ_TX_OPTION_INNER_UDP_TCP_CSUM_WIDTH 1266#define ESF_DZ_TX_OPTION_INNER_IP_CSUM_LBN 6267#define ESF_DZ_TX_OPTION_INNER_IP_CSUM_WIDTH 1268#define ESF_DZ_TX_TIMESTAMP_LBN 5269#define ESF_DZ_TX_TIMESTAMP_WIDTH 1270#define ESF_DZ_TX_OPTION_CRC_MODE_LBN 2271#define ESF_DZ_TX_OPTION_CRC_MODE_WIDTH 3272#define ESE_DZ_TX_OPTION_CRC_FCOIP_MPA 5273#define ESE_DZ_TX_OPTION_CRC_FCOIP_FCOE 4274#define ESE_DZ_TX_OPTION_CRC_ISCSI_HDR_AND_PYLD 3275#define ESE_DZ_TX_OPTION_CRC_ISCSI_HDR 2276#define ESE_DZ_TX_OPTION_CRC_FCOE 1277#define ESE_DZ_TX_OPTION_CRC_OFF 0278#define ESF_DZ_TX_OPTION_UDP_TCP_CSUM_LBN 1279#define ESF_DZ_TX_OPTION_UDP_TCP_CSUM_WIDTH 1280#define ESF_DZ_TX_OPTION_IP_CSUM_LBN 0281#define ESF_DZ_TX_OPTION_IP_CSUM_WIDTH 1282 283/* TX_EVENT */284#define ESF_DZ_TX_CODE_LBN 60285#define ESF_DZ_TX_CODE_WIDTH 4286#define ESF_DZ_TX_OVERRIDE_HOLDOFF_LBN 59287#define ESF_DZ_TX_OVERRIDE_HOLDOFF_WIDTH 1288#define ESF_DZ_TX_DROP_EVENT_LBN 58289#define ESF_DZ_TX_DROP_EVENT_WIDTH 1290#define ESF_DD_TX_EV_RSVD_LBN 48291#define ESF_DD_TX_EV_RSVD_WIDTH 10292#define ESF_EZ_TCP_UDP_INNER_CHKSUM_ERR_LBN 57293#define ESF_EZ_TCP_UDP_INNER_CHKSUM_ERR_WIDTH 1294#define ESF_EZ_IP_INNER_CHKSUM_ERR_LBN 56295#define ESF_EZ_IP_INNER_CHKSUM_ERR_WIDTH 1296#define ESF_EZ_TX_EV_RSVD_LBN 48297#define ESF_EZ_TX_EV_RSVD_WIDTH 8298#define ESF_DZ_TX_SOFT2_LBN 32299#define ESF_DZ_TX_SOFT2_WIDTH 16300#define ESF_DD_TX_SOFT1_LBN 24301#define ESF_DD_TX_SOFT1_WIDTH 8302#define ESF_EZ_TX_CAN_MERGE_LBN 31303#define ESF_EZ_TX_CAN_MERGE_WIDTH 1304#define ESF_EZ_TX_SOFT1_LBN 24305#define ESF_EZ_TX_SOFT1_WIDTH 7306#define ESF_DZ_TX_QLABEL_LBN 16307#define ESF_DZ_TX_QLABEL_WIDTH 5308#define ESF_DZ_TX_DESCR_INDX_LBN 0309#define ESF_DZ_TX_DESCR_INDX_WIDTH 16310 311/* TX_KER_DESC */312#define ESF_DZ_TX_KER_TYPE_LBN 63313#define ESF_DZ_TX_KER_TYPE_WIDTH 1314#define ESF_DZ_TX_KER_CONT_LBN 62315#define ESF_DZ_TX_KER_CONT_WIDTH 1316#define ESF_DZ_TX_KER_BYTE_CNT_LBN 48317#define ESF_DZ_TX_KER_BYTE_CNT_WIDTH 14318#define ESF_DZ_TX_KER_BUF_ADDR_LBN 0319#define ESF_DZ_TX_KER_BUF_ADDR_WIDTH 48320 321/* TX_PIO_DESC */322#define ESF_DZ_TX_PIO_TYPE_LBN 63323#define ESF_DZ_TX_PIO_TYPE_WIDTH 1324#define ESF_DZ_TX_PIO_OPT_LBN 60325#define ESF_DZ_TX_PIO_OPT_WIDTH 3326#define ESE_DZ_TX_OPTION_DESC_PIO 1327#define ESF_DZ_TX_PIO_CONT_LBN 59328#define ESF_DZ_TX_PIO_CONT_WIDTH 1329#define ESF_DZ_TX_PIO_BYTE_CNT_LBN 32330#define ESF_DZ_TX_PIO_BYTE_CNT_WIDTH 12331#define ESF_DZ_TX_PIO_BUF_ADDR_LBN 0332#define ESF_DZ_TX_PIO_BUF_ADDR_WIDTH 12333 334/* TX_TSO_DESC */335#define ESF_DZ_TX_DESC_IS_OPT_LBN 63336#define ESF_DZ_TX_DESC_IS_OPT_WIDTH 1337#define ESF_DZ_TX_OPTION_TYPE_LBN 60338#define ESF_DZ_TX_OPTION_TYPE_WIDTH 3339#define ESE_DZ_TX_OPTION_DESC_TSO 7340#define ESE_DZ_TX_OPTION_DESC_VLAN 6341#define ESE_DZ_TX_OPTION_DESC_CRC_CSUM 0342#define ESF_DZ_TX_TSO_OPTION_TYPE_LBN 56343#define ESF_DZ_TX_TSO_OPTION_TYPE_WIDTH 4344#define ESE_DZ_TX_TSO_OPTION_DESC_FATSO2B 3345#define ESE_DZ_TX_TSO_OPTION_DESC_FATSO2A 2346#define ESE_DZ_TX_TSO_OPTION_DESC_ENCAP 1347#define ESE_DZ_TX_TSO_OPTION_DESC_NORMAL 0348#define ESF_DZ_TX_TSO_TCP_FLAGS_LBN 48349#define ESF_DZ_TX_TSO_TCP_FLAGS_WIDTH 8350#define ESF_DZ_TX_TSO_IP_ID_LBN 32351#define ESF_DZ_TX_TSO_IP_ID_WIDTH 16352#define ESF_DZ_TX_TSO_TCP_SEQNO_LBN 0353#define ESF_DZ_TX_TSO_TCP_SEQNO_WIDTH 32354 355/* TX_TSO_V2_DESC_A */356#define ESF_DZ_TX_DESC_IS_OPT_LBN 63357#define ESF_DZ_TX_DESC_IS_OPT_WIDTH 1358#define ESF_DZ_TX_OPTION_TYPE_LBN 60359#define ESF_DZ_TX_OPTION_TYPE_WIDTH 3360#define ESE_DZ_TX_OPTION_DESC_TSO 7361#define ESE_DZ_TX_OPTION_DESC_VLAN 6362#define ESE_DZ_TX_OPTION_DESC_CRC_CSUM 0363#define ESF_DZ_TX_TSO_OPTION_TYPE_LBN 56364#define ESF_DZ_TX_TSO_OPTION_TYPE_WIDTH 4365#define ESE_DZ_TX_TSO_OPTION_DESC_FATSO2B 3366#define ESE_DZ_TX_TSO_OPTION_DESC_FATSO2A 2367#define ESE_DZ_TX_TSO_OPTION_DESC_ENCAP 1368#define ESE_DZ_TX_TSO_OPTION_DESC_NORMAL 0369#define ESF_DZ_TX_TSO_IP_ID_LBN 32370#define ESF_DZ_TX_TSO_IP_ID_WIDTH 16371#define ESF_DZ_TX_TSO_TCP_SEQNO_LBN 0372#define ESF_DZ_TX_TSO_TCP_SEQNO_WIDTH 32373 374/* TX_TSO_V2_DESC_B */375#define ESF_DZ_TX_DESC_IS_OPT_LBN 63376#define ESF_DZ_TX_DESC_IS_OPT_WIDTH 1377#define ESF_DZ_TX_OPTION_TYPE_LBN 60378#define ESF_DZ_TX_OPTION_TYPE_WIDTH 3379#define ESE_DZ_TX_OPTION_DESC_TSO 7380#define ESE_DZ_TX_OPTION_DESC_VLAN 6381#define ESE_DZ_TX_OPTION_DESC_CRC_CSUM 0382#define ESF_DZ_TX_TSO_OPTION_TYPE_LBN 56383#define ESF_DZ_TX_TSO_OPTION_TYPE_WIDTH 4384#define ESE_DZ_TX_TSO_OPTION_DESC_FATSO2B 3385#define ESE_DZ_TX_TSO_OPTION_DESC_FATSO2A 2386#define ESE_DZ_TX_TSO_OPTION_DESC_ENCAP 1387#define ESE_DZ_TX_TSO_OPTION_DESC_NORMAL 0388#define ESF_DZ_TX_TSO_TCP_MSS_LBN 32389#define ESF_DZ_TX_TSO_TCP_MSS_WIDTH 16390#define ESF_DZ_TX_TSO_OUTER_IPID_LBN 0391#define ESF_DZ_TX_TSO_OUTER_IPID_WIDTH 16392 393/*************************************************************************/394 395/* TX_DESC_UPD_REG: Transmit descriptor update register.396 * We may write just one dword of these registers.397 */398#define ER_DZ_TX_DESC_UPD_DWORD (ER_DZ_TX_DESC_UPD + 2 * 4)399#define ERF_DZ_TX_DESC_WPTR_DWORD_LBN (ERF_DZ_TX_DESC_WPTR_LBN - 2 * 32)400#define ERF_DZ_TX_DESC_WPTR_DWORD_WIDTH ERF_DZ_TX_DESC_WPTR_WIDTH401 402/* The workaround for bug 35388 requires multiplexing writes through403 * the TX_DESC_UPD_DWORD address.404 * TX_DESC_UPD: 0ppppppppppp (bit 11 lost)405 * EVQ_RPTR: 1000hhhhhhhh, 1001llllllll (split into high and low bits)406 * EVQ_TMR: 11mmvvvvvvvv (bits 8:13 of value lost)407 */408#define ER_DD_EVQ_INDIRECT ER_DZ_TX_DESC_UPD_DWORD409#define ERF_DD_EVQ_IND_RPTR_FLAGS_LBN 8410#define ERF_DD_EVQ_IND_RPTR_FLAGS_WIDTH 4411#define EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH 8412#define EFE_DD_EVQ_IND_RPTR_FLAGS_LOW 9413#define ERF_DD_EVQ_IND_RPTR_LBN 0414#define ERF_DD_EVQ_IND_RPTR_WIDTH 8415#define ERF_DD_EVQ_IND_TIMER_FLAGS_LBN 10416#define ERF_DD_EVQ_IND_TIMER_FLAGS_WIDTH 2417#define EFE_DD_EVQ_IND_TIMER_FLAGS 3418#define ERF_DD_EVQ_IND_TIMER_MODE_LBN 8419#define ERF_DD_EVQ_IND_TIMER_MODE_WIDTH 2420#define ERF_DD_EVQ_IND_TIMER_VAL_LBN 0421#define ERF_DD_EVQ_IND_TIMER_VAL_WIDTH 8422 423/* TX_PIOBUF424 * PIO buffer aperture (paged)425 */426#define ER_DZ_TX_PIOBUF 4096427#define ER_DZ_TX_PIOBUF_SIZE 2048428 429/* RX packet prefix */430#define ES_DZ_RX_PREFIX_HASH_OFST 0431#define ES_DZ_RX_PREFIX_VLAN1_OFST 4432#define ES_DZ_RX_PREFIX_VLAN2_OFST 6433#define ES_DZ_RX_PREFIX_PKTLEN_OFST 8434#define ES_DZ_RX_PREFIX_TSTAMP_OFST 10435#define ES_DZ_RX_PREFIX_SIZE 14436 437#endif /* EFX_EF10_REGS_H */438