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1/* SPDX-License-Identifier: GPL-2.0-only */2/****************************************************************************3 * Driver for Solarflare network controllers and boards4 * Copyright 2005-2006 Fen Systems Ltd.5 * Copyright 2006-2012 Solarflare Communications Inc.6 */7 8#ifndef EF4_FARCH_REGS_H9#define EF4_FARCH_REGS_H10 11/*12 * Falcon hardware architecture definitions have a name prefix following13 * the format:14 *15 * F<type>_<min-rev><max-rev>_16 *17 * The following <type> strings are used:18 *19 * MMIO register MC register Host memory structure20 * -------------------------------------------------------------21 * Address R MCR22 * Bitfield RF MCRF SF23 * Enumerator FE MCFE SE24 *25 * <min-rev> is the first revision to which the definition applies:26 *27 * A: Falcon A1 (SFC4000AB)28 * B: Falcon B0 (SFC4000BA)29 * C: Siena A0 (SFL9021AA)30 *31 * If the definition has been changed or removed in later revisions32 * then <max-rev> is the last revision to which the definition applies;33 * otherwise it is "Z".34 */35 36/**************************************************************************37 *38 * Falcon/Siena registers and descriptors39 *40 **************************************************************************41 */42 43/* ADR_REGION_REG: Address region register */44#define FR_AZ_ADR_REGION 0x0000000045#define FRF_AZ_ADR_REGION3_LBN 9646#define FRF_AZ_ADR_REGION3_WIDTH 1847#define FRF_AZ_ADR_REGION2_LBN 6448#define FRF_AZ_ADR_REGION2_WIDTH 1849#define FRF_AZ_ADR_REGION1_LBN 3250#define FRF_AZ_ADR_REGION1_WIDTH 1851#define FRF_AZ_ADR_REGION0_LBN 052#define FRF_AZ_ADR_REGION0_WIDTH 1853 54/* INT_EN_REG_KER: Kernel driver Interrupt enable register */55#define FR_AZ_INT_EN_KER 0x0000001056#define FRF_AZ_KER_INT_LEVE_SEL_LBN 857#define FRF_AZ_KER_INT_LEVE_SEL_WIDTH 658#define FRF_AZ_KER_INT_CHAR_LBN 459#define FRF_AZ_KER_INT_CHAR_WIDTH 160#define FRF_AZ_KER_INT_KER_LBN 361#define FRF_AZ_KER_INT_KER_WIDTH 162#define FRF_AZ_DRV_INT_EN_KER_LBN 063#define FRF_AZ_DRV_INT_EN_KER_WIDTH 164 65/* INT_EN_REG_CHAR: Char Driver interrupt enable register */66#define FR_BZ_INT_EN_CHAR 0x0000002067#define FRF_BZ_CHAR_INT_LEVE_SEL_LBN 868#define FRF_BZ_CHAR_INT_LEVE_SEL_WIDTH 669#define FRF_BZ_CHAR_INT_CHAR_LBN 470#define FRF_BZ_CHAR_INT_CHAR_WIDTH 171#define FRF_BZ_CHAR_INT_KER_LBN 372#define FRF_BZ_CHAR_INT_KER_WIDTH 173#define FRF_BZ_DRV_INT_EN_CHAR_LBN 074#define FRF_BZ_DRV_INT_EN_CHAR_WIDTH 175 76/* INT_ADR_REG_KER: Interrupt host address for Kernel driver */77#define FR_AZ_INT_ADR_KER 0x0000003078#define FRF_AZ_NORM_INT_VEC_DIS_KER_LBN 6479#define FRF_AZ_NORM_INT_VEC_DIS_KER_WIDTH 180#define FRF_AZ_INT_ADR_KER_LBN 081#define FRF_AZ_INT_ADR_KER_WIDTH 6482 83/* INT_ADR_REG_CHAR: Interrupt host address for Char driver */84#define FR_BZ_INT_ADR_CHAR 0x0000004085#define FRF_BZ_NORM_INT_VEC_DIS_CHAR_LBN 6486#define FRF_BZ_NORM_INT_VEC_DIS_CHAR_WIDTH 187#define FRF_BZ_INT_ADR_CHAR_LBN 088#define FRF_BZ_INT_ADR_CHAR_WIDTH 6489 90/* INT_ACK_KER: Kernel interrupt acknowledge register */91#define FR_AA_INT_ACK_KER 0x0000005092#define FRF_AA_INT_ACK_KER_FIELD_LBN 093#define FRF_AA_INT_ACK_KER_FIELD_WIDTH 3294 95/* INT_ISR0_REG: Function 0 Interrupt Acknowledge Status register */96#define FR_BZ_INT_ISR0 0x0000009097#define FRF_BZ_INT_ISR_REG_LBN 098#define FRF_BZ_INT_ISR_REG_WIDTH 6499 100/* HW_INIT_REG: Hardware initialization register */101#define FR_AZ_HW_INIT 0x000000c0102#define FRF_BB_BDMRD_CPLF_FULL_LBN 124103#define FRF_BB_BDMRD_CPLF_FULL_WIDTH 1104#define FRF_BB_PCIE_CPL_TIMEOUT_CTRL_LBN 121105#define FRF_BB_PCIE_CPL_TIMEOUT_CTRL_WIDTH 3106#define FRF_CZ_TX_MRG_TAGS_LBN 120107#define FRF_CZ_TX_MRG_TAGS_WIDTH 1108#define FRF_AB_TRGT_MASK_ALL_LBN 100109#define FRF_AB_TRGT_MASK_ALL_WIDTH 1110#define FRF_AZ_DOORBELL_DROP_LBN 92111#define FRF_AZ_DOORBELL_DROP_WIDTH 8112#define FRF_AB_TX_RREQ_MASK_EN_LBN 76113#define FRF_AB_TX_RREQ_MASK_EN_WIDTH 1114#define FRF_AB_PE_EIDLE_DIS_LBN 75115#define FRF_AB_PE_EIDLE_DIS_WIDTH 1116#define FRF_AA_FC_BLOCKING_EN_LBN 45117#define FRF_AA_FC_BLOCKING_EN_WIDTH 1118#define FRF_BZ_B2B_REQ_EN_LBN 45119#define FRF_BZ_B2B_REQ_EN_WIDTH 1120#define FRF_AA_B2B_REQ_EN_LBN 44121#define FRF_AA_B2B_REQ_EN_WIDTH 1122#define FRF_BB_FC_BLOCKING_EN_LBN 44123#define FRF_BB_FC_BLOCKING_EN_WIDTH 1124#define FRF_AZ_POST_WR_MASK_LBN 40125#define FRF_AZ_POST_WR_MASK_WIDTH 4126#define FRF_AZ_TLP_TC_LBN 34127#define FRF_AZ_TLP_TC_WIDTH 3128#define FRF_AZ_TLP_ATTR_LBN 32129#define FRF_AZ_TLP_ATTR_WIDTH 2130#define FRF_AB_INTB_VEC_LBN 24131#define FRF_AB_INTB_VEC_WIDTH 5132#define FRF_AB_INTA_VEC_LBN 16133#define FRF_AB_INTA_VEC_WIDTH 5134#define FRF_AZ_WD_TIMER_LBN 8135#define FRF_AZ_WD_TIMER_WIDTH 8136#define FRF_AZ_US_DISABLE_LBN 5137#define FRF_AZ_US_DISABLE_WIDTH 1138#define FRF_AZ_TLP_EP_LBN 4139#define FRF_AZ_TLP_EP_WIDTH 1140#define FRF_AZ_ATTR_SEL_LBN 3141#define FRF_AZ_ATTR_SEL_WIDTH 1142#define FRF_AZ_TD_SEL_LBN 1143#define FRF_AZ_TD_SEL_WIDTH 1144#define FRF_AZ_TLP_TD_LBN 0145#define FRF_AZ_TLP_TD_WIDTH 1146 147/* EE_SPI_HCMD_REG: SPI host command register */148#define FR_AB_EE_SPI_HCMD 0x00000100149#define FRF_AB_EE_SPI_HCMD_CMD_EN_LBN 31150#define FRF_AB_EE_SPI_HCMD_CMD_EN_WIDTH 1151#define FRF_AB_EE_WR_TIMER_ACTIVE_LBN 28152#define FRF_AB_EE_WR_TIMER_ACTIVE_WIDTH 1153#define FRF_AB_EE_SPI_HCMD_SF_SEL_LBN 24154#define FRF_AB_EE_SPI_HCMD_SF_SEL_WIDTH 1155#define FRF_AB_EE_SPI_HCMD_DABCNT_LBN 16156#define FRF_AB_EE_SPI_HCMD_DABCNT_WIDTH 5157#define FRF_AB_EE_SPI_HCMD_READ_LBN 15158#define FRF_AB_EE_SPI_HCMD_READ_WIDTH 1159#define FRF_AB_EE_SPI_HCMD_DUBCNT_LBN 12160#define FRF_AB_EE_SPI_HCMD_DUBCNT_WIDTH 2161#define FRF_AB_EE_SPI_HCMD_ADBCNT_LBN 8162#define FRF_AB_EE_SPI_HCMD_ADBCNT_WIDTH 2163#define FRF_AB_EE_SPI_HCMD_ENC_LBN 0164#define FRF_AB_EE_SPI_HCMD_ENC_WIDTH 8165 166/* USR_EV_CFG: User Level Event Configuration register */167#define FR_CZ_USR_EV_CFG 0x00000100168#define FRF_CZ_USREV_DIS_LBN 16169#define FRF_CZ_USREV_DIS_WIDTH 1170#define FRF_CZ_DFLT_EVQ_LBN 0171#define FRF_CZ_DFLT_EVQ_WIDTH 10172 173/* EE_SPI_HADR_REG: SPI host address register */174#define FR_AB_EE_SPI_HADR 0x00000110175#define FRF_AB_EE_SPI_HADR_DUBYTE_LBN 24176#define FRF_AB_EE_SPI_HADR_DUBYTE_WIDTH 8177#define FRF_AB_EE_SPI_HADR_ADR_LBN 0178#define FRF_AB_EE_SPI_HADR_ADR_WIDTH 24179 180/* EE_SPI_HDATA_REG: SPI host data register */181#define FR_AB_EE_SPI_HDATA 0x00000120182#define FRF_AB_EE_SPI_HDATA3_LBN 96183#define FRF_AB_EE_SPI_HDATA3_WIDTH 32184#define FRF_AB_EE_SPI_HDATA2_LBN 64185#define FRF_AB_EE_SPI_HDATA2_WIDTH 32186#define FRF_AB_EE_SPI_HDATA1_LBN 32187#define FRF_AB_EE_SPI_HDATA1_WIDTH 32188#define FRF_AB_EE_SPI_HDATA0_LBN 0189#define FRF_AB_EE_SPI_HDATA0_WIDTH 32190 191/* EE_BASE_PAGE_REG: Expansion ROM base mirror register */192#define FR_AB_EE_BASE_PAGE 0x00000130193#define FRF_AB_EE_EXPROM_MASK_LBN 16194#define FRF_AB_EE_EXPROM_MASK_WIDTH 13195#define FRF_AB_EE_EXP_ROM_WINDOW_BASE_LBN 0196#define FRF_AB_EE_EXP_ROM_WINDOW_BASE_WIDTH 13197 198/* EE_VPD_CFG0_REG: SPI/VPD configuration register 0 */199#define FR_AB_EE_VPD_CFG0 0x00000140200#define FRF_AB_EE_SF_FASTRD_EN_LBN 127201#define FRF_AB_EE_SF_FASTRD_EN_WIDTH 1202#define FRF_AB_EE_SF_CLOCK_DIV_LBN 120203#define FRF_AB_EE_SF_CLOCK_DIV_WIDTH 7204#define FRF_AB_EE_VPD_WIP_POLL_LBN 119205#define FRF_AB_EE_VPD_WIP_POLL_WIDTH 1206#define FRF_AB_EE_EE_CLOCK_DIV_LBN 112207#define FRF_AB_EE_EE_CLOCK_DIV_WIDTH 7208#define FRF_AB_EE_EE_WR_TMR_VALUE_LBN 96209#define FRF_AB_EE_EE_WR_TMR_VALUE_WIDTH 16210#define FRF_AB_EE_VPDW_LENGTH_LBN 80211#define FRF_AB_EE_VPDW_LENGTH_WIDTH 15212#define FRF_AB_EE_VPDW_BASE_LBN 64213#define FRF_AB_EE_VPDW_BASE_WIDTH 15214#define FRF_AB_EE_VPD_WR_CMD_EN_LBN 56215#define FRF_AB_EE_VPD_WR_CMD_EN_WIDTH 8216#define FRF_AB_EE_VPD_BASE_LBN 32217#define FRF_AB_EE_VPD_BASE_WIDTH 24218#define FRF_AB_EE_VPD_LENGTH_LBN 16219#define FRF_AB_EE_VPD_LENGTH_WIDTH 15220#define FRF_AB_EE_VPD_AD_SIZE_LBN 8221#define FRF_AB_EE_VPD_AD_SIZE_WIDTH 5222#define FRF_AB_EE_VPD_ACCESS_ON_LBN 5223#define FRF_AB_EE_VPD_ACCESS_ON_WIDTH 1224#define FRF_AB_EE_VPD_ACCESS_BLOCK_LBN 4225#define FRF_AB_EE_VPD_ACCESS_BLOCK_WIDTH 1226#define FRF_AB_EE_VPD_DEV_SF_SEL_LBN 2227#define FRF_AB_EE_VPD_DEV_SF_SEL_WIDTH 1228#define FRF_AB_EE_VPD_EN_AD9_MODE_LBN 1229#define FRF_AB_EE_VPD_EN_AD9_MODE_WIDTH 1230#define FRF_AB_EE_VPD_EN_LBN 0231#define FRF_AB_EE_VPD_EN_WIDTH 1232 233/* EE_VPD_SW_CNTL_REG: VPD access SW control register */234#define FR_AB_EE_VPD_SW_CNTL 0x00000150235#define FRF_AB_EE_VPD_CYCLE_PENDING_LBN 31236#define FRF_AB_EE_VPD_CYCLE_PENDING_WIDTH 1237#define FRF_AB_EE_VPD_CYC_WRITE_LBN 28238#define FRF_AB_EE_VPD_CYC_WRITE_WIDTH 1239#define FRF_AB_EE_VPD_CYC_ADR_LBN 0240#define FRF_AB_EE_VPD_CYC_ADR_WIDTH 15241 242/* EE_VPD_SW_DATA_REG: VPD access SW data register */243#define FR_AB_EE_VPD_SW_DATA 0x00000160244#define FRF_AB_EE_VPD_CYC_DAT_LBN 0245#define FRF_AB_EE_VPD_CYC_DAT_WIDTH 32246 247/* PBMX_DBG_IADDR_REG: Capture Module address register */248#define FR_CZ_PBMX_DBG_IADDR 0x000001f0249#define FRF_CZ_PBMX_DBG_IADDR_LBN 0250#define FRF_CZ_PBMX_DBG_IADDR_WIDTH 32251 252/* PCIE_CORE_INDIRECT_REG: Indirect Access to PCIE Core registers */253#define FR_BB_PCIE_CORE_INDIRECT 0x000001f0254#define FRF_BB_PCIE_CORE_TARGET_DATA_LBN 32255#define FRF_BB_PCIE_CORE_TARGET_DATA_WIDTH 32256#define FRF_BB_PCIE_CORE_INDIRECT_ACCESS_DIR_LBN 15257#define FRF_BB_PCIE_CORE_INDIRECT_ACCESS_DIR_WIDTH 1258#define FRF_BB_PCIE_CORE_TARGET_REG_ADRS_LBN 0259#define FRF_BB_PCIE_CORE_TARGET_REG_ADRS_WIDTH 12260 261/* PBMX_DBG_IDATA_REG: Capture Module data register */262#define FR_CZ_PBMX_DBG_IDATA 0x000001f8263#define FRF_CZ_PBMX_DBG_IDATA_LBN 0264#define FRF_CZ_PBMX_DBG_IDATA_WIDTH 64265 266/* NIC_STAT_REG: NIC status register */267#define FR_AB_NIC_STAT 0x00000200268#define FRF_BB_AER_DIS_LBN 34269#define FRF_BB_AER_DIS_WIDTH 1270#define FRF_BB_EE_STRAP_EN_LBN 31271#define FRF_BB_EE_STRAP_EN_WIDTH 1272#define FRF_BB_EE_STRAP_LBN 24273#define FRF_BB_EE_STRAP_WIDTH 4274#define FRF_BB_REVISION_ID_LBN 17275#define FRF_BB_REVISION_ID_WIDTH 7276#define FRF_AB_ONCHIP_SRAM_LBN 16277#define FRF_AB_ONCHIP_SRAM_WIDTH 1278#define FRF_AB_SF_PRST_LBN 9279#define FRF_AB_SF_PRST_WIDTH 1280#define FRF_AB_EE_PRST_LBN 8281#define FRF_AB_EE_PRST_WIDTH 1282#define FRF_AB_ATE_MODE_LBN 3283#define FRF_AB_ATE_MODE_WIDTH 1284#define FRF_AB_STRAP_PINS_LBN 0285#define FRF_AB_STRAP_PINS_WIDTH 3286 287/* GPIO_CTL_REG: GPIO control register */288#define FR_AB_GPIO_CTL 0x00000210289#define FRF_AB_GPIO_OUT3_LBN 112290#define FRF_AB_GPIO_OUT3_WIDTH 16291#define FRF_AB_GPIO_IN3_LBN 104292#define FRF_AB_GPIO_IN3_WIDTH 8293#define FRF_AB_GPIO_PWRUP_VALUE3_LBN 96294#define FRF_AB_GPIO_PWRUP_VALUE3_WIDTH 8295#define FRF_AB_GPIO_OUT2_LBN 80296#define FRF_AB_GPIO_OUT2_WIDTH 16297#define FRF_AB_GPIO_IN2_LBN 72298#define FRF_AB_GPIO_IN2_WIDTH 8299#define FRF_AB_GPIO_PWRUP_VALUE2_LBN 64300#define FRF_AB_GPIO_PWRUP_VALUE2_WIDTH 8301#define FRF_AB_GPIO15_OEN_LBN 63302#define FRF_AB_GPIO15_OEN_WIDTH 1303#define FRF_AB_GPIO14_OEN_LBN 62304#define FRF_AB_GPIO14_OEN_WIDTH 1305#define FRF_AB_GPIO13_OEN_LBN 61306#define FRF_AB_GPIO13_OEN_WIDTH 1307#define FRF_AB_GPIO12_OEN_LBN 60308#define FRF_AB_GPIO12_OEN_WIDTH 1309#define FRF_AB_GPIO11_OEN_LBN 59310#define FRF_AB_GPIO11_OEN_WIDTH 1311#define FRF_AB_GPIO10_OEN_LBN 58312#define FRF_AB_GPIO10_OEN_WIDTH 1313#define FRF_AB_GPIO9_OEN_LBN 57314#define FRF_AB_GPIO9_OEN_WIDTH 1315#define FRF_AB_GPIO8_OEN_LBN 56316#define FRF_AB_GPIO8_OEN_WIDTH 1317#define FRF_AB_GPIO15_OUT_LBN 55318#define FRF_AB_GPIO15_OUT_WIDTH 1319#define FRF_AB_GPIO14_OUT_LBN 54320#define FRF_AB_GPIO14_OUT_WIDTH 1321#define FRF_AB_GPIO13_OUT_LBN 53322#define FRF_AB_GPIO13_OUT_WIDTH 1323#define FRF_AB_GPIO12_OUT_LBN 52324#define FRF_AB_GPIO12_OUT_WIDTH 1325#define FRF_AB_GPIO11_OUT_LBN 51326#define FRF_AB_GPIO11_OUT_WIDTH 1327#define FRF_AB_GPIO10_OUT_LBN 50328#define FRF_AB_GPIO10_OUT_WIDTH 1329#define FRF_AB_GPIO9_OUT_LBN 49330#define FRF_AB_GPIO9_OUT_WIDTH 1331#define FRF_AB_GPIO8_OUT_LBN 48332#define FRF_AB_GPIO8_OUT_WIDTH 1333#define FRF_AB_GPIO15_IN_LBN 47334#define FRF_AB_GPIO15_IN_WIDTH 1335#define FRF_AB_GPIO14_IN_LBN 46336#define FRF_AB_GPIO14_IN_WIDTH 1337#define FRF_AB_GPIO13_IN_LBN 45338#define FRF_AB_GPIO13_IN_WIDTH 1339#define FRF_AB_GPIO12_IN_LBN 44340#define FRF_AB_GPIO12_IN_WIDTH 1341#define FRF_AB_GPIO11_IN_LBN 43342#define FRF_AB_GPIO11_IN_WIDTH 1343#define FRF_AB_GPIO10_IN_LBN 42344#define FRF_AB_GPIO10_IN_WIDTH 1345#define FRF_AB_GPIO9_IN_LBN 41346#define FRF_AB_GPIO9_IN_WIDTH 1347#define FRF_AB_GPIO8_IN_LBN 40348#define FRF_AB_GPIO8_IN_WIDTH 1349#define FRF_AB_GPIO15_PWRUP_VALUE_LBN 39350#define FRF_AB_GPIO15_PWRUP_VALUE_WIDTH 1351#define FRF_AB_GPIO14_PWRUP_VALUE_LBN 38352#define FRF_AB_GPIO14_PWRUP_VALUE_WIDTH 1353#define FRF_AB_GPIO13_PWRUP_VALUE_LBN 37354#define FRF_AB_GPIO13_PWRUP_VALUE_WIDTH 1355#define FRF_AB_GPIO12_PWRUP_VALUE_LBN 36356#define FRF_AB_GPIO12_PWRUP_VALUE_WIDTH 1357#define FRF_AB_GPIO11_PWRUP_VALUE_LBN 35358#define FRF_AB_GPIO11_PWRUP_VALUE_WIDTH 1359#define FRF_AB_GPIO10_PWRUP_VALUE_LBN 34360#define FRF_AB_GPIO10_PWRUP_VALUE_WIDTH 1361#define FRF_AB_GPIO9_PWRUP_VALUE_LBN 33362#define FRF_AB_GPIO9_PWRUP_VALUE_WIDTH 1363#define FRF_AB_GPIO8_PWRUP_VALUE_LBN 32364#define FRF_AB_GPIO8_PWRUP_VALUE_WIDTH 1365#define FRF_AB_CLK156_OUT_EN_LBN 31366#define FRF_AB_CLK156_OUT_EN_WIDTH 1367#define FRF_AB_USE_NIC_CLK_LBN 30368#define FRF_AB_USE_NIC_CLK_WIDTH 1369#define FRF_AB_GPIO5_OEN_LBN 29370#define FRF_AB_GPIO5_OEN_WIDTH 1371#define FRF_AB_GPIO4_OEN_LBN 28372#define FRF_AB_GPIO4_OEN_WIDTH 1373#define FRF_AB_GPIO3_OEN_LBN 27374#define FRF_AB_GPIO3_OEN_WIDTH 1375#define FRF_AB_GPIO2_OEN_LBN 26376#define FRF_AB_GPIO2_OEN_WIDTH 1377#define FRF_AB_GPIO1_OEN_LBN 25378#define FRF_AB_GPIO1_OEN_WIDTH 1379#define FRF_AB_GPIO0_OEN_LBN 24380#define FRF_AB_GPIO0_OEN_WIDTH 1381#define FRF_AB_GPIO7_OUT_LBN 23382#define FRF_AB_GPIO7_OUT_WIDTH 1383#define FRF_AB_GPIO6_OUT_LBN 22384#define FRF_AB_GPIO6_OUT_WIDTH 1385#define FRF_AB_GPIO5_OUT_LBN 21386#define FRF_AB_GPIO5_OUT_WIDTH 1387#define FRF_AB_GPIO4_OUT_LBN 20388#define FRF_AB_GPIO4_OUT_WIDTH 1389#define FRF_AB_GPIO3_OUT_LBN 19390#define FRF_AB_GPIO3_OUT_WIDTH 1391#define FRF_AB_GPIO2_OUT_LBN 18392#define FRF_AB_GPIO2_OUT_WIDTH 1393#define FRF_AB_GPIO1_OUT_LBN 17394#define FRF_AB_GPIO1_OUT_WIDTH 1395#define FRF_AB_GPIO0_OUT_LBN 16396#define FRF_AB_GPIO0_OUT_WIDTH 1397#define FRF_AB_GPIO7_IN_LBN 15398#define FRF_AB_GPIO7_IN_WIDTH 1399#define FRF_AB_GPIO6_IN_LBN 14400#define FRF_AB_GPIO6_IN_WIDTH 1401#define FRF_AB_GPIO5_IN_LBN 13402#define FRF_AB_GPIO5_IN_WIDTH 1403#define FRF_AB_GPIO4_IN_LBN 12404#define FRF_AB_GPIO4_IN_WIDTH 1405#define FRF_AB_GPIO3_IN_LBN 11406#define FRF_AB_GPIO3_IN_WIDTH 1407#define FRF_AB_GPIO2_IN_LBN 10408#define FRF_AB_GPIO2_IN_WIDTH 1409#define FRF_AB_GPIO1_IN_LBN 9410#define FRF_AB_GPIO1_IN_WIDTH 1411#define FRF_AB_GPIO0_IN_LBN 8412#define FRF_AB_GPIO0_IN_WIDTH 1413#define FRF_AB_GPIO7_PWRUP_VALUE_LBN 7414#define FRF_AB_GPIO7_PWRUP_VALUE_WIDTH 1415#define FRF_AB_GPIO6_PWRUP_VALUE_LBN 6416#define FRF_AB_GPIO6_PWRUP_VALUE_WIDTH 1417#define FRF_AB_GPIO5_PWRUP_VALUE_LBN 5418#define FRF_AB_GPIO5_PWRUP_VALUE_WIDTH 1419#define FRF_AB_GPIO4_PWRUP_VALUE_LBN 4420#define FRF_AB_GPIO4_PWRUP_VALUE_WIDTH 1421#define FRF_AB_GPIO3_PWRUP_VALUE_LBN 3422#define FRF_AB_GPIO3_PWRUP_VALUE_WIDTH 1423#define FRF_AB_GPIO2_PWRUP_VALUE_LBN 2424#define FRF_AB_GPIO2_PWRUP_VALUE_WIDTH 1425#define FRF_AB_GPIO1_PWRUP_VALUE_LBN 1426#define FRF_AB_GPIO1_PWRUP_VALUE_WIDTH 1427#define FRF_AB_GPIO0_PWRUP_VALUE_LBN 0428#define FRF_AB_GPIO0_PWRUP_VALUE_WIDTH 1429 430/* GLB_CTL_REG: Global control register */431#define FR_AB_GLB_CTL 0x00000220432#define FRF_AB_EXT_PHY_RST_CTL_LBN 63433#define FRF_AB_EXT_PHY_RST_CTL_WIDTH 1434#define FRF_AB_XAUI_SD_RST_CTL_LBN 62435#define FRF_AB_XAUI_SD_RST_CTL_WIDTH 1436#define FRF_AB_PCIE_SD_RST_CTL_LBN 61437#define FRF_AB_PCIE_SD_RST_CTL_WIDTH 1438#define FRF_AA_PCIX_RST_CTL_LBN 60439#define FRF_AA_PCIX_RST_CTL_WIDTH 1440#define FRF_BB_BIU_RST_CTL_LBN 60441#define FRF_BB_BIU_RST_CTL_WIDTH 1442#define FRF_AB_PCIE_STKY_RST_CTL_LBN 59443#define FRF_AB_PCIE_STKY_RST_CTL_WIDTH 1444#define FRF_AB_PCIE_NSTKY_RST_CTL_LBN 58445#define FRF_AB_PCIE_NSTKY_RST_CTL_WIDTH 1446#define FRF_AB_PCIE_CORE_RST_CTL_LBN 57447#define FRF_AB_PCIE_CORE_RST_CTL_WIDTH 1448#define FRF_AB_XGRX_RST_CTL_LBN 56449#define FRF_AB_XGRX_RST_CTL_WIDTH 1450#define FRF_AB_XGTX_RST_CTL_LBN 55451#define FRF_AB_XGTX_RST_CTL_WIDTH 1452#define FRF_AB_EM_RST_CTL_LBN 54453#define FRF_AB_EM_RST_CTL_WIDTH 1454#define FRF_AB_EV_RST_CTL_LBN 53455#define FRF_AB_EV_RST_CTL_WIDTH 1456#define FRF_AB_SR_RST_CTL_LBN 52457#define FRF_AB_SR_RST_CTL_WIDTH 1458#define FRF_AB_RX_RST_CTL_LBN 51459#define FRF_AB_RX_RST_CTL_WIDTH 1460#define FRF_AB_TX_RST_CTL_LBN 50461#define FRF_AB_TX_RST_CTL_WIDTH 1462#define FRF_AB_EE_RST_CTL_LBN 49463#define FRF_AB_EE_RST_CTL_WIDTH 1464#define FRF_AB_CS_RST_CTL_LBN 48465#define FRF_AB_CS_RST_CTL_WIDTH 1466#define FRF_AB_HOT_RST_CTL_LBN 40467#define FRF_AB_HOT_RST_CTL_WIDTH 2468#define FRF_AB_RST_EXT_PHY_LBN 31469#define FRF_AB_RST_EXT_PHY_WIDTH 1470#define FRF_AB_RST_XAUI_SD_LBN 30471#define FRF_AB_RST_XAUI_SD_WIDTH 1472#define FRF_AB_RST_PCIE_SD_LBN 29473#define FRF_AB_RST_PCIE_SD_WIDTH 1474#define FRF_AA_RST_PCIX_LBN 28475#define FRF_AA_RST_PCIX_WIDTH 1476#define FRF_BB_RST_BIU_LBN 28477#define FRF_BB_RST_BIU_WIDTH 1478#define FRF_AB_RST_PCIE_STKY_LBN 27479#define FRF_AB_RST_PCIE_STKY_WIDTH 1480#define FRF_AB_RST_PCIE_NSTKY_LBN 26481#define FRF_AB_RST_PCIE_NSTKY_WIDTH 1482#define FRF_AB_RST_PCIE_CORE_LBN 25483#define FRF_AB_RST_PCIE_CORE_WIDTH 1484#define FRF_AB_RST_XGRX_LBN 24485#define FRF_AB_RST_XGRX_WIDTH 1486#define FRF_AB_RST_XGTX_LBN 23487#define FRF_AB_RST_XGTX_WIDTH 1488#define FRF_AB_RST_EM_LBN 22489#define FRF_AB_RST_EM_WIDTH 1490#define FRF_AB_RST_EV_LBN 21491#define FRF_AB_RST_EV_WIDTH 1492#define FRF_AB_RST_SR_LBN 20493#define FRF_AB_RST_SR_WIDTH 1494#define FRF_AB_RST_RX_LBN 19495#define FRF_AB_RST_RX_WIDTH 1496#define FRF_AB_RST_TX_LBN 18497#define FRF_AB_RST_TX_WIDTH 1498#define FRF_AB_RST_SF_LBN 17499#define FRF_AB_RST_SF_WIDTH 1500#define FRF_AB_RST_CS_LBN 16501#define FRF_AB_RST_CS_WIDTH 1502#define FRF_AB_INT_RST_DUR_LBN 4503#define FRF_AB_INT_RST_DUR_WIDTH 3504#define FRF_AB_EXT_PHY_RST_DUR_LBN 1505#define FRF_AB_EXT_PHY_RST_DUR_WIDTH 3506#define FFE_AB_EXT_PHY_RST_DUR_10240US 7507#define FFE_AB_EXT_PHY_RST_DUR_5120US 6508#define FFE_AB_EXT_PHY_RST_DUR_2560US 5509#define FFE_AB_EXT_PHY_RST_DUR_1280US 4510#define FFE_AB_EXT_PHY_RST_DUR_640US 3511#define FFE_AB_EXT_PHY_RST_DUR_320US 2512#define FFE_AB_EXT_PHY_RST_DUR_160US 1513#define FFE_AB_EXT_PHY_RST_DUR_80US 0514#define FRF_AB_SWRST_LBN 0515#define FRF_AB_SWRST_WIDTH 1516 517/* FATAL_INTR_REG_KER: Fatal interrupt register for Kernel */518#define FR_AZ_FATAL_INTR_KER 0x00000230519#define FRF_CZ_SRAM_PERR_INT_P_KER_EN_LBN 44520#define FRF_CZ_SRAM_PERR_INT_P_KER_EN_WIDTH 1521#define FRF_AB_PCI_BUSERR_INT_KER_EN_LBN 43522#define FRF_AB_PCI_BUSERR_INT_KER_EN_WIDTH 1523#define FRF_CZ_MBU_PERR_INT_KER_EN_LBN 43524#define FRF_CZ_MBU_PERR_INT_KER_EN_WIDTH 1525#define FRF_AZ_SRAM_OOB_INT_KER_EN_LBN 42526#define FRF_AZ_SRAM_OOB_INT_KER_EN_WIDTH 1527#define FRF_AZ_BUFID_OOB_INT_KER_EN_LBN 41528#define FRF_AZ_BUFID_OOB_INT_KER_EN_WIDTH 1529#define FRF_AZ_MEM_PERR_INT_KER_EN_LBN 40530#define FRF_AZ_MEM_PERR_INT_KER_EN_WIDTH 1531#define FRF_AZ_RBUF_OWN_INT_KER_EN_LBN 39532#define FRF_AZ_RBUF_OWN_INT_KER_EN_WIDTH 1533#define FRF_AZ_TBUF_OWN_INT_KER_EN_LBN 38534#define FRF_AZ_TBUF_OWN_INT_KER_EN_WIDTH 1535#define FRF_AZ_RDESCQ_OWN_INT_KER_EN_LBN 37536#define FRF_AZ_RDESCQ_OWN_INT_KER_EN_WIDTH 1537#define FRF_AZ_TDESCQ_OWN_INT_KER_EN_LBN 36538#define FRF_AZ_TDESCQ_OWN_INT_KER_EN_WIDTH 1539#define FRF_AZ_EVQ_OWN_INT_KER_EN_LBN 35540#define FRF_AZ_EVQ_OWN_INT_KER_EN_WIDTH 1541#define FRF_AZ_EVF_OFLO_INT_KER_EN_LBN 34542#define FRF_AZ_EVF_OFLO_INT_KER_EN_WIDTH 1543#define FRF_AZ_ILL_ADR_INT_KER_EN_LBN 33544#define FRF_AZ_ILL_ADR_INT_KER_EN_WIDTH 1545#define FRF_AZ_SRM_PERR_INT_KER_EN_LBN 32546#define FRF_AZ_SRM_PERR_INT_KER_EN_WIDTH 1547#define FRF_CZ_SRAM_PERR_INT_P_KER_LBN 12548#define FRF_CZ_SRAM_PERR_INT_P_KER_WIDTH 1549#define FRF_AB_PCI_BUSERR_INT_KER_LBN 11550#define FRF_AB_PCI_BUSERR_INT_KER_WIDTH 1551#define FRF_CZ_MBU_PERR_INT_KER_LBN 11552#define FRF_CZ_MBU_PERR_INT_KER_WIDTH 1553#define FRF_AZ_SRAM_OOB_INT_KER_LBN 10554#define FRF_AZ_SRAM_OOB_INT_KER_WIDTH 1555#define FRF_AZ_BUFID_DC_OOB_INT_KER_LBN 9556#define FRF_AZ_BUFID_DC_OOB_INT_KER_WIDTH 1557#define FRF_AZ_MEM_PERR_INT_KER_LBN 8558#define FRF_AZ_MEM_PERR_INT_KER_WIDTH 1559#define FRF_AZ_RBUF_OWN_INT_KER_LBN 7560#define FRF_AZ_RBUF_OWN_INT_KER_WIDTH 1561#define FRF_AZ_TBUF_OWN_INT_KER_LBN 6562#define FRF_AZ_TBUF_OWN_INT_KER_WIDTH 1563#define FRF_AZ_RDESCQ_OWN_INT_KER_LBN 5564#define FRF_AZ_RDESCQ_OWN_INT_KER_WIDTH 1565#define FRF_AZ_TDESCQ_OWN_INT_KER_LBN 4566#define FRF_AZ_TDESCQ_OWN_INT_KER_WIDTH 1567#define FRF_AZ_EVQ_OWN_INT_KER_LBN 3568#define FRF_AZ_EVQ_OWN_INT_KER_WIDTH 1569#define FRF_AZ_EVF_OFLO_INT_KER_LBN 2570#define FRF_AZ_EVF_OFLO_INT_KER_WIDTH 1571#define FRF_AZ_ILL_ADR_INT_KER_LBN 1572#define FRF_AZ_ILL_ADR_INT_KER_WIDTH 1573#define FRF_AZ_SRM_PERR_INT_KER_LBN 0574#define FRF_AZ_SRM_PERR_INT_KER_WIDTH 1575 576/* FATAL_INTR_REG_CHAR: Fatal interrupt register for Char */577#define FR_BZ_FATAL_INTR_CHAR 0x00000240578#define FRF_CZ_SRAM_PERR_INT_P_CHAR_EN_LBN 44579#define FRF_CZ_SRAM_PERR_INT_P_CHAR_EN_WIDTH 1580#define FRF_BB_PCI_BUSERR_INT_CHAR_EN_LBN 43581#define FRF_BB_PCI_BUSERR_INT_CHAR_EN_WIDTH 1582#define FRF_CZ_MBU_PERR_INT_CHAR_EN_LBN 43583#define FRF_CZ_MBU_PERR_INT_CHAR_EN_WIDTH 1584#define FRF_BZ_SRAM_OOB_INT_CHAR_EN_LBN 42585#define FRF_BZ_SRAM_OOB_INT_CHAR_EN_WIDTH 1586#define FRF_BZ_BUFID_OOB_INT_CHAR_EN_LBN 41587#define FRF_BZ_BUFID_OOB_INT_CHAR_EN_WIDTH 1588#define FRF_BZ_MEM_PERR_INT_CHAR_EN_LBN 40589#define FRF_BZ_MEM_PERR_INT_CHAR_EN_WIDTH 1590#define FRF_BZ_RBUF_OWN_INT_CHAR_EN_LBN 39591#define FRF_BZ_RBUF_OWN_INT_CHAR_EN_WIDTH 1592#define FRF_BZ_TBUF_OWN_INT_CHAR_EN_LBN 38593#define FRF_BZ_TBUF_OWN_INT_CHAR_EN_WIDTH 1594#define FRF_BZ_RDESCQ_OWN_INT_CHAR_EN_LBN 37595#define FRF_BZ_RDESCQ_OWN_INT_CHAR_EN_WIDTH 1596#define FRF_BZ_TDESCQ_OWN_INT_CHAR_EN_LBN 36597#define FRF_BZ_TDESCQ_OWN_INT_CHAR_EN_WIDTH 1598#define FRF_BZ_EVQ_OWN_INT_CHAR_EN_LBN 35599#define FRF_BZ_EVQ_OWN_INT_CHAR_EN_WIDTH 1600#define FRF_BZ_EVF_OFLO_INT_CHAR_EN_LBN 34601#define FRF_BZ_EVF_OFLO_INT_CHAR_EN_WIDTH 1602#define FRF_BZ_ILL_ADR_INT_CHAR_EN_LBN 33603#define FRF_BZ_ILL_ADR_INT_CHAR_EN_WIDTH 1604#define FRF_BZ_SRM_PERR_INT_CHAR_EN_LBN 32605#define FRF_BZ_SRM_PERR_INT_CHAR_EN_WIDTH 1606#define FRF_CZ_SRAM_PERR_INT_P_CHAR_LBN 12607#define FRF_CZ_SRAM_PERR_INT_P_CHAR_WIDTH 1608#define FRF_BB_PCI_BUSERR_INT_CHAR_LBN 11609#define FRF_BB_PCI_BUSERR_INT_CHAR_WIDTH 1610#define FRF_CZ_MBU_PERR_INT_CHAR_LBN 11611#define FRF_CZ_MBU_PERR_INT_CHAR_WIDTH 1612#define FRF_BZ_SRAM_OOB_INT_CHAR_LBN 10613#define FRF_BZ_SRAM_OOB_INT_CHAR_WIDTH 1614#define FRF_BZ_BUFID_DC_OOB_INT_CHAR_LBN 9615#define FRF_BZ_BUFID_DC_OOB_INT_CHAR_WIDTH 1616#define FRF_BZ_MEM_PERR_INT_CHAR_LBN 8617#define FRF_BZ_MEM_PERR_INT_CHAR_WIDTH 1618#define FRF_BZ_RBUF_OWN_INT_CHAR_LBN 7619#define FRF_BZ_RBUF_OWN_INT_CHAR_WIDTH 1620#define FRF_BZ_TBUF_OWN_INT_CHAR_LBN 6621#define FRF_BZ_TBUF_OWN_INT_CHAR_WIDTH 1622#define FRF_BZ_RDESCQ_OWN_INT_CHAR_LBN 5623#define FRF_BZ_RDESCQ_OWN_INT_CHAR_WIDTH 1624#define FRF_BZ_TDESCQ_OWN_INT_CHAR_LBN 4625#define FRF_BZ_TDESCQ_OWN_INT_CHAR_WIDTH 1626#define FRF_BZ_EVQ_OWN_INT_CHAR_LBN 3627#define FRF_BZ_EVQ_OWN_INT_CHAR_WIDTH 1628#define FRF_BZ_EVF_OFLO_INT_CHAR_LBN 2629#define FRF_BZ_EVF_OFLO_INT_CHAR_WIDTH 1630#define FRF_BZ_ILL_ADR_INT_CHAR_LBN 1631#define FRF_BZ_ILL_ADR_INT_CHAR_WIDTH 1632#define FRF_BZ_SRM_PERR_INT_CHAR_LBN 0633#define FRF_BZ_SRM_PERR_INT_CHAR_WIDTH 1634 635/* DP_CTRL_REG: Datapath control register */636#define FR_BZ_DP_CTRL 0x00000250637#define FRF_BZ_FLS_EVQ_ID_LBN 0638#define FRF_BZ_FLS_EVQ_ID_WIDTH 12639 640/* MEM_STAT_REG: Memory status register */641#define FR_AZ_MEM_STAT 0x00000260642#define FRF_AB_MEM_PERR_VEC_LBN 53643#define FRF_AB_MEM_PERR_VEC_WIDTH 38644#define FRF_AB_MBIST_CORR_LBN 38645#define FRF_AB_MBIST_CORR_WIDTH 15646#define FRF_AB_MBIST_ERR_LBN 0647#define FRF_AB_MBIST_ERR_WIDTH 40648#define FRF_CZ_MEM_PERR_VEC_LBN 0649#define FRF_CZ_MEM_PERR_VEC_WIDTH 35650 651/* CS_DEBUG_REG: Debug register */652#define FR_AZ_CS_DEBUG 0x00000270653#define FRF_AB_GLB_DEBUG2_SEL_LBN 50654#define FRF_AB_GLB_DEBUG2_SEL_WIDTH 3655#define FRF_AB_DEBUG_BLK_SEL2_LBN 47656#define FRF_AB_DEBUG_BLK_SEL2_WIDTH 3657#define FRF_AB_DEBUG_BLK_SEL1_LBN 44658#define FRF_AB_DEBUG_BLK_SEL1_WIDTH 3659#define FRF_AB_DEBUG_BLK_SEL0_LBN 41660#define FRF_AB_DEBUG_BLK_SEL0_WIDTH 3661#define FRF_CZ_CS_PORT_NUM_LBN 40662#define FRF_CZ_CS_PORT_NUM_WIDTH 2663#define FRF_AB_MISC_DEBUG_ADDR_LBN 36664#define FRF_AB_MISC_DEBUG_ADDR_WIDTH 5665#define FRF_AB_SERDES_DEBUG_ADDR_LBN 31666#define FRF_AB_SERDES_DEBUG_ADDR_WIDTH 5667#define FRF_CZ_CS_PORT_FPE_LBN 1668#define FRF_CZ_CS_PORT_FPE_WIDTH 35669#define FRF_AB_EM_DEBUG_ADDR_LBN 26670#define FRF_AB_EM_DEBUG_ADDR_WIDTH 5671#define FRF_AB_SR_DEBUG_ADDR_LBN 21672#define FRF_AB_SR_DEBUG_ADDR_WIDTH 5673#define FRF_AB_EV_DEBUG_ADDR_LBN 16674#define FRF_AB_EV_DEBUG_ADDR_WIDTH 5675#define FRF_AB_RX_DEBUG_ADDR_LBN 11676#define FRF_AB_RX_DEBUG_ADDR_WIDTH 5677#define FRF_AB_TX_DEBUG_ADDR_LBN 6678#define FRF_AB_TX_DEBUG_ADDR_WIDTH 5679#define FRF_AB_CS_BIU_DEBUG_ADDR_LBN 1680#define FRF_AB_CS_BIU_DEBUG_ADDR_WIDTH 5681#define FRF_AZ_CS_DEBUG_EN_LBN 0682#define FRF_AZ_CS_DEBUG_EN_WIDTH 1683 684/* DRIVER_REG: Driver scratch register [0-7] */685#define FR_AZ_DRIVER 0x00000280686#define FR_AZ_DRIVER_STEP 16687#define FR_AZ_DRIVER_ROWS 8688#define FRF_AZ_DRIVER_DW0_LBN 0689#define FRF_AZ_DRIVER_DW0_WIDTH 32690 691/* ALTERA_BUILD_REG: Altera build register */692#define FR_AZ_ALTERA_BUILD 0x00000300693#define FRF_AZ_ALTERA_BUILD_VER_LBN 0694#define FRF_AZ_ALTERA_BUILD_VER_WIDTH 32695 696/* CSR_SPARE_REG: Spare register */697#define FR_AZ_CSR_SPARE 0x00000310698#define FRF_AB_MEM_PERR_EN_LBN 64699#define FRF_AB_MEM_PERR_EN_WIDTH 38700#define FRF_CZ_MEM_PERR_EN_LBN 64701#define FRF_CZ_MEM_PERR_EN_WIDTH 35702#define FRF_AB_MEM_PERR_EN_TX_DATA_LBN 72703#define FRF_AB_MEM_PERR_EN_TX_DATA_WIDTH 2704#define FRF_AZ_CSR_SPARE_BITS_LBN 0705#define FRF_AZ_CSR_SPARE_BITS_WIDTH 32706 707/* PCIE_SD_CTL0123_REG: PCIE SerDes control register 0 to 3 */708#define FR_AB_PCIE_SD_CTL0123 0x00000320709#define FRF_AB_PCIE_TESTSIG_H_LBN 96710#define FRF_AB_PCIE_TESTSIG_H_WIDTH 19711#define FRF_AB_PCIE_TESTSIG_L_LBN 64712#define FRF_AB_PCIE_TESTSIG_L_WIDTH 19713#define FRF_AB_PCIE_OFFSET_LBN 56714#define FRF_AB_PCIE_OFFSET_WIDTH 8715#define FRF_AB_PCIE_OFFSETEN_H_LBN 55716#define FRF_AB_PCIE_OFFSETEN_H_WIDTH 1717#define FRF_AB_PCIE_OFFSETEN_L_LBN 54718#define FRF_AB_PCIE_OFFSETEN_L_WIDTH 1719#define FRF_AB_PCIE_HIVMODE_H_LBN 53720#define FRF_AB_PCIE_HIVMODE_H_WIDTH 1721#define FRF_AB_PCIE_HIVMODE_L_LBN 52722#define FRF_AB_PCIE_HIVMODE_L_WIDTH 1723#define FRF_AB_PCIE_PARRESET_H_LBN 51724#define FRF_AB_PCIE_PARRESET_H_WIDTH 1725#define FRF_AB_PCIE_PARRESET_L_LBN 50726#define FRF_AB_PCIE_PARRESET_L_WIDTH 1727#define FRF_AB_PCIE_LPBKWDRV_H_LBN 49728#define FRF_AB_PCIE_LPBKWDRV_H_WIDTH 1729#define FRF_AB_PCIE_LPBKWDRV_L_LBN 48730#define FRF_AB_PCIE_LPBKWDRV_L_WIDTH 1731#define FRF_AB_PCIE_LPBK_LBN 40732#define FRF_AB_PCIE_LPBK_WIDTH 8733#define FRF_AB_PCIE_PARLPBK_LBN 32734#define FRF_AB_PCIE_PARLPBK_WIDTH 8735#define FRF_AB_PCIE_RXTERMADJ_H_LBN 30736#define FRF_AB_PCIE_RXTERMADJ_H_WIDTH 2737#define FRF_AB_PCIE_RXTERMADJ_L_LBN 28738#define FRF_AB_PCIE_RXTERMADJ_L_WIDTH 2739#define FFE_AB_PCIE_RXTERMADJ_MIN15PCNT 3740#define FFE_AB_PCIE_RXTERMADJ_PL10PCNT 2741#define FFE_AB_PCIE_RXTERMADJ_MIN17PCNT 1742#define FFE_AB_PCIE_RXTERMADJ_NOMNL 0743#define FRF_AB_PCIE_TXTERMADJ_H_LBN 26744#define FRF_AB_PCIE_TXTERMADJ_H_WIDTH 2745#define FRF_AB_PCIE_TXTERMADJ_L_LBN 24746#define FRF_AB_PCIE_TXTERMADJ_L_WIDTH 2747#define FFE_AB_PCIE_TXTERMADJ_MIN15PCNT 3748#define FFE_AB_PCIE_TXTERMADJ_PL10PCNT 2749#define FFE_AB_PCIE_TXTERMADJ_MIN17PCNT 1750#define FFE_AB_PCIE_TXTERMADJ_NOMNL 0751#define FRF_AB_PCIE_RXEQCTL_H_LBN 18752#define FRF_AB_PCIE_RXEQCTL_H_WIDTH 2753#define FRF_AB_PCIE_RXEQCTL_L_LBN 16754#define FRF_AB_PCIE_RXEQCTL_L_WIDTH 2755#define FFE_AB_PCIE_RXEQCTL_OFF_ALT 3756#define FFE_AB_PCIE_RXEQCTL_OFF 2757#define FFE_AB_PCIE_RXEQCTL_MIN 1758#define FFE_AB_PCIE_RXEQCTL_MAX 0759#define FRF_AB_PCIE_HIDRV_LBN 8760#define FRF_AB_PCIE_HIDRV_WIDTH 8761#define FRF_AB_PCIE_LODRV_LBN 0762#define FRF_AB_PCIE_LODRV_WIDTH 8763 764/* PCIE_SD_CTL45_REG: PCIE SerDes control register 4 and 5 */765#define FR_AB_PCIE_SD_CTL45 0x00000330766#define FRF_AB_PCIE_DTX7_LBN 60767#define FRF_AB_PCIE_DTX7_WIDTH 4768#define FRF_AB_PCIE_DTX6_LBN 56769#define FRF_AB_PCIE_DTX6_WIDTH 4770#define FRF_AB_PCIE_DTX5_LBN 52771#define FRF_AB_PCIE_DTX5_WIDTH 4772#define FRF_AB_PCIE_DTX4_LBN 48773#define FRF_AB_PCIE_DTX4_WIDTH 4774#define FRF_AB_PCIE_DTX3_LBN 44775#define FRF_AB_PCIE_DTX3_WIDTH 4776#define FRF_AB_PCIE_DTX2_LBN 40777#define FRF_AB_PCIE_DTX2_WIDTH 4778#define FRF_AB_PCIE_DTX1_LBN 36779#define FRF_AB_PCIE_DTX1_WIDTH 4780#define FRF_AB_PCIE_DTX0_LBN 32781#define FRF_AB_PCIE_DTX0_WIDTH 4782#define FRF_AB_PCIE_DEQ7_LBN 28783#define FRF_AB_PCIE_DEQ7_WIDTH 4784#define FRF_AB_PCIE_DEQ6_LBN 24785#define FRF_AB_PCIE_DEQ6_WIDTH 4786#define FRF_AB_PCIE_DEQ5_LBN 20787#define FRF_AB_PCIE_DEQ5_WIDTH 4788#define FRF_AB_PCIE_DEQ4_LBN 16789#define FRF_AB_PCIE_DEQ4_WIDTH 4790#define FRF_AB_PCIE_DEQ3_LBN 12791#define FRF_AB_PCIE_DEQ3_WIDTH 4792#define FRF_AB_PCIE_DEQ2_LBN 8793#define FRF_AB_PCIE_DEQ2_WIDTH 4794#define FRF_AB_PCIE_DEQ1_LBN 4795#define FRF_AB_PCIE_DEQ1_WIDTH 4796#define FRF_AB_PCIE_DEQ0_LBN 0797#define FRF_AB_PCIE_DEQ0_WIDTH 4798 799/* PCIE_PCS_CTL_STAT_REG: PCIE PCS control and status register */800#define FR_AB_PCIE_PCS_CTL_STAT 0x00000340801#define FRF_AB_PCIE_PRBSERRCOUNT0_H_LBN 52802#define FRF_AB_PCIE_PRBSERRCOUNT0_H_WIDTH 4803#define FRF_AB_PCIE_PRBSERRCOUNT0_L_LBN 48804#define FRF_AB_PCIE_PRBSERRCOUNT0_L_WIDTH 4805#define FRF_AB_PCIE_PRBSERR_LBN 40806#define FRF_AB_PCIE_PRBSERR_WIDTH 8807#define FRF_AB_PCIE_PRBSERRH0_LBN 32808#define FRF_AB_PCIE_PRBSERRH0_WIDTH 8809#define FRF_AB_PCIE_FASTINIT_H_LBN 15810#define FRF_AB_PCIE_FASTINIT_H_WIDTH 1811#define FRF_AB_PCIE_FASTINIT_L_LBN 14812#define FRF_AB_PCIE_FASTINIT_L_WIDTH 1813#define FRF_AB_PCIE_CTCDISABLE_H_LBN 13814#define FRF_AB_PCIE_CTCDISABLE_H_WIDTH 1815#define FRF_AB_PCIE_CTCDISABLE_L_LBN 12816#define FRF_AB_PCIE_CTCDISABLE_L_WIDTH 1817#define FRF_AB_PCIE_PRBSSYNC_H_LBN 11818#define FRF_AB_PCIE_PRBSSYNC_H_WIDTH 1819#define FRF_AB_PCIE_PRBSSYNC_L_LBN 10820#define FRF_AB_PCIE_PRBSSYNC_L_WIDTH 1821#define FRF_AB_PCIE_PRBSERRACK_H_LBN 9822#define FRF_AB_PCIE_PRBSERRACK_H_WIDTH 1823#define FRF_AB_PCIE_PRBSERRACK_L_LBN 8824#define FRF_AB_PCIE_PRBSERRACK_L_WIDTH 1825#define FRF_AB_PCIE_PRBSSEL_LBN 0826#define FRF_AB_PCIE_PRBSSEL_WIDTH 8827 828/* DEBUG_DATA_OUT_REG: Live Debug and Debug 2 out ports */829#define FR_BB_DEBUG_DATA_OUT 0x00000350830#define FRF_BB_DEBUG2_PORT_LBN 25831#define FRF_BB_DEBUG2_PORT_WIDTH 15832#define FRF_BB_DEBUG1_PORT_LBN 0833#define FRF_BB_DEBUG1_PORT_WIDTH 25834 835/* EVQ_RPTR_REGP0: Event queue read pointer register */836#define FR_BZ_EVQ_RPTR_P0 0x00000400837#define FR_BZ_EVQ_RPTR_P0_STEP 8192838#define FR_BZ_EVQ_RPTR_P0_ROWS 1024839/* EVQ_RPTR_REG_KER: Event queue read pointer register */840#define FR_AA_EVQ_RPTR_KER 0x00011b00841#define FR_AA_EVQ_RPTR_KER_STEP 4842#define FR_AA_EVQ_RPTR_KER_ROWS 4843/* EVQ_RPTR_REG: Event queue read pointer register */844#define FR_BZ_EVQ_RPTR 0x00fa0000845#define FR_BZ_EVQ_RPTR_STEP 16846#define FR_BB_EVQ_RPTR_ROWS 4096847#define FR_CZ_EVQ_RPTR_ROWS 1024848/* EVQ_RPTR_REGP123: Event queue read pointer register */849#define FR_BB_EVQ_RPTR_P123 0x01000400850#define FR_BB_EVQ_RPTR_P123_STEP 8192851#define FR_BB_EVQ_RPTR_P123_ROWS 3072852#define FRF_AZ_EVQ_RPTR_VLD_LBN 15853#define FRF_AZ_EVQ_RPTR_VLD_WIDTH 1854#define FRF_AZ_EVQ_RPTR_LBN 0855#define FRF_AZ_EVQ_RPTR_WIDTH 15856 857/* TIMER_COMMAND_REGP0: Timer Command Registers */858#define FR_BZ_TIMER_COMMAND_P0 0x00000420859#define FR_BZ_TIMER_COMMAND_P0_STEP 8192860#define FR_BZ_TIMER_COMMAND_P0_ROWS 1024861/* TIMER_COMMAND_REG_KER: Timer Command Registers */862#define FR_AA_TIMER_COMMAND_KER 0x00000420863#define FR_AA_TIMER_COMMAND_KER_STEP 8192864#define FR_AA_TIMER_COMMAND_KER_ROWS 4865/* TIMER_COMMAND_REGP123: Timer Command Registers */866#define FR_BB_TIMER_COMMAND_P123 0x01000420867#define FR_BB_TIMER_COMMAND_P123_STEP 8192868#define FR_BB_TIMER_COMMAND_P123_ROWS 3072869#define FRF_CZ_TC_TIMER_MODE_LBN 14870#define FRF_CZ_TC_TIMER_MODE_WIDTH 2871#define FRF_AB_TC_TIMER_MODE_LBN 12872#define FRF_AB_TC_TIMER_MODE_WIDTH 2873#define FRF_CZ_TC_TIMER_VAL_LBN 0874#define FRF_CZ_TC_TIMER_VAL_WIDTH 14875#define FRF_AB_TC_TIMER_VAL_LBN 0876#define FRF_AB_TC_TIMER_VAL_WIDTH 12877 878/* DRV_EV_REG: Driver generated event register */879#define FR_AZ_DRV_EV 0x00000440880#define FRF_AZ_DRV_EV_QID_LBN 64881#define FRF_AZ_DRV_EV_QID_WIDTH 12882#define FRF_AZ_DRV_EV_DATA_LBN 0883#define FRF_AZ_DRV_EV_DATA_WIDTH 64884 885/* EVQ_CTL_REG: Event queue control register */886#define FR_AZ_EVQ_CTL 0x00000450887#define FRF_CZ_RX_EVQ_WAKEUP_MASK_LBN 15888#define FRF_CZ_RX_EVQ_WAKEUP_MASK_WIDTH 10889#define FRF_BB_RX_EVQ_WAKEUP_MASK_LBN 15890#define FRF_BB_RX_EVQ_WAKEUP_MASK_WIDTH 6891#define FRF_AZ_EVQ_OWNERR_CTL_LBN 14892#define FRF_AZ_EVQ_OWNERR_CTL_WIDTH 1893#define FRF_AZ_EVQ_FIFO_AF_TH_LBN 7894#define FRF_AZ_EVQ_FIFO_AF_TH_WIDTH 7895#define FRF_AZ_EVQ_FIFO_NOTAF_TH_LBN 0896#define FRF_AZ_EVQ_FIFO_NOTAF_TH_WIDTH 7897 898/* EVQ_CNT1_REG: Event counter 1 register */899#define FR_AZ_EVQ_CNT1 0x00000460900#define FRF_AZ_EVQ_CNT_PRE_FIFO_LBN 120901#define FRF_AZ_EVQ_CNT_PRE_FIFO_WIDTH 7902#define FRF_AZ_EVQ_CNT_TOBIU_LBN 100903#define FRF_AZ_EVQ_CNT_TOBIU_WIDTH 20904#define FRF_AZ_EVQ_TX_REQ_CNT_LBN 80905#define FRF_AZ_EVQ_TX_REQ_CNT_WIDTH 20906#define FRF_AZ_EVQ_RX_REQ_CNT_LBN 60907#define FRF_AZ_EVQ_RX_REQ_CNT_WIDTH 20908#define FRF_AZ_EVQ_EM_REQ_CNT_LBN 40909#define FRF_AZ_EVQ_EM_REQ_CNT_WIDTH 20910#define FRF_AZ_EVQ_CSR_REQ_CNT_LBN 20911#define FRF_AZ_EVQ_CSR_REQ_CNT_WIDTH 20912#define FRF_AZ_EVQ_ERR_REQ_CNT_LBN 0913#define FRF_AZ_EVQ_ERR_REQ_CNT_WIDTH 20914 915/* EVQ_CNT2_REG: Event counter 2 register */916#define FR_AZ_EVQ_CNT2 0x00000470917#define FRF_AZ_EVQ_UPD_REQ_CNT_LBN 104918#define FRF_AZ_EVQ_UPD_REQ_CNT_WIDTH 20919#define FRF_AZ_EVQ_CLR_REQ_CNT_LBN 84920#define FRF_AZ_EVQ_CLR_REQ_CNT_WIDTH 20921#define FRF_AZ_EVQ_RDY_CNT_LBN 80922#define FRF_AZ_EVQ_RDY_CNT_WIDTH 4923#define FRF_AZ_EVQ_WU_REQ_CNT_LBN 60924#define FRF_AZ_EVQ_WU_REQ_CNT_WIDTH 20925#define FRF_AZ_EVQ_WET_REQ_CNT_LBN 40926#define FRF_AZ_EVQ_WET_REQ_CNT_WIDTH 20927#define FRF_AZ_EVQ_INIT_REQ_CNT_LBN 20928#define FRF_AZ_EVQ_INIT_REQ_CNT_WIDTH 20929#define FRF_AZ_EVQ_TM_REQ_CNT_LBN 0930#define FRF_AZ_EVQ_TM_REQ_CNT_WIDTH 20931 932/* USR_EV_REG: Event mailbox register */933#define FR_CZ_USR_EV 0x00000540934#define FR_CZ_USR_EV_STEP 8192935#define FR_CZ_USR_EV_ROWS 1024936#define FRF_CZ_USR_EV_DATA_LBN 0937#define FRF_CZ_USR_EV_DATA_WIDTH 32938 939/* BUF_TBL_CFG_REG: Buffer table configuration register */940#define FR_AZ_BUF_TBL_CFG 0x00000600941#define FRF_AZ_BUF_TBL_MODE_LBN 3942#define FRF_AZ_BUF_TBL_MODE_WIDTH 1943 944/* SRM_RX_DC_CFG_REG: SRAM receive descriptor cache configuration register */945#define FR_AZ_SRM_RX_DC_CFG 0x00000610946#define FRF_AZ_SRM_CLK_TMP_EN_LBN 21947#define FRF_AZ_SRM_CLK_TMP_EN_WIDTH 1948#define FRF_AZ_SRM_RX_DC_BASE_ADR_LBN 0949#define FRF_AZ_SRM_RX_DC_BASE_ADR_WIDTH 21950 951/* SRM_TX_DC_CFG_REG: SRAM transmit descriptor cache configuration register */952#define FR_AZ_SRM_TX_DC_CFG 0x00000620953#define FRF_AZ_SRM_TX_DC_BASE_ADR_LBN 0954#define FRF_AZ_SRM_TX_DC_BASE_ADR_WIDTH 21955 956/* SRM_CFG_REG: SRAM configuration register */957#define FR_AZ_SRM_CFG 0x00000630958#define FRF_AZ_SRM_OOB_ADR_INTEN_LBN 5959#define FRF_AZ_SRM_OOB_ADR_INTEN_WIDTH 1960#define FRF_AZ_SRM_OOB_BUF_INTEN_LBN 4961#define FRF_AZ_SRM_OOB_BUF_INTEN_WIDTH 1962#define FRF_AZ_SRM_INIT_EN_LBN 3963#define FRF_AZ_SRM_INIT_EN_WIDTH 1964#define FRF_AZ_SRM_NUM_BANK_LBN 2965#define FRF_AZ_SRM_NUM_BANK_WIDTH 1966#define FRF_AZ_SRM_BANK_SIZE_LBN 0967#define FRF_AZ_SRM_BANK_SIZE_WIDTH 2968 969/* BUF_TBL_UPD_REG: Buffer table update register */970#define FR_AZ_BUF_TBL_UPD 0x00000650971#define FRF_AZ_BUF_UPD_CMD_LBN 63972#define FRF_AZ_BUF_UPD_CMD_WIDTH 1973#define FRF_AZ_BUF_CLR_CMD_LBN 62974#define FRF_AZ_BUF_CLR_CMD_WIDTH 1975#define FRF_AZ_BUF_CLR_END_ID_LBN 32976#define FRF_AZ_BUF_CLR_END_ID_WIDTH 20977#define FRF_AZ_BUF_CLR_START_ID_LBN 0978#define FRF_AZ_BUF_CLR_START_ID_WIDTH 20979 980/* SRM_UPD_EVQ_REG: Buffer table update register */981#define FR_AZ_SRM_UPD_EVQ 0x00000660982#define FRF_AZ_SRM_UPD_EVQ_ID_LBN 0983#define FRF_AZ_SRM_UPD_EVQ_ID_WIDTH 12984 985/* SRAM_PARITY_REG: SRAM parity register. */986#define FR_AZ_SRAM_PARITY 0x00000670987#define FRF_CZ_BYPASS_ECC_LBN 3988#define FRF_CZ_BYPASS_ECC_WIDTH 1989#define FRF_CZ_SEC_INT_LBN 2990#define FRF_CZ_SEC_INT_WIDTH 1991#define FRF_CZ_FORCE_SRAM_DOUBLE_ERR_LBN 1992#define FRF_CZ_FORCE_SRAM_DOUBLE_ERR_WIDTH 1993#define FRF_AB_FORCE_SRAM_PERR_LBN 0994#define FRF_AB_FORCE_SRAM_PERR_WIDTH 1995#define FRF_CZ_FORCE_SRAM_SINGLE_ERR_LBN 0996#define FRF_CZ_FORCE_SRAM_SINGLE_ERR_WIDTH 1997 998/* RX_CFG_REG: Receive configuration register */999#define FR_AZ_RX_CFG 0x000008001000#define FRF_CZ_RX_MIN_KBUF_SIZE_LBN 721001#define FRF_CZ_RX_MIN_KBUF_SIZE_WIDTH 141002#define FRF_CZ_RX_HDR_SPLIT_EN_LBN 711003#define FRF_CZ_RX_HDR_SPLIT_EN_WIDTH 11004#define FRF_CZ_RX_HDR_SPLIT_PLD_BUF_SIZE_LBN 621005#define FRF_CZ_RX_HDR_SPLIT_PLD_BUF_SIZE_WIDTH 91006#define FRF_CZ_RX_HDR_SPLIT_HDR_BUF_SIZE_LBN 531007#define FRF_CZ_RX_HDR_SPLIT_HDR_BUF_SIZE_WIDTH 91008#define FRF_CZ_RX_PRE_RFF_IPG_LBN 491009#define FRF_CZ_RX_PRE_RFF_IPG_WIDTH 41010#define FRF_BZ_RX_TCP_SUP_LBN 481011#define FRF_BZ_RX_TCP_SUP_WIDTH 11012#define FRF_BZ_RX_INGR_EN_LBN 471013#define FRF_BZ_RX_INGR_EN_WIDTH 11014#define FRF_BZ_RX_IP_HASH_LBN 461015#define FRF_BZ_RX_IP_HASH_WIDTH 11016#define FRF_BZ_RX_HASH_ALG_LBN 451017#define FRF_BZ_RX_HASH_ALG_WIDTH 11018#define FRF_BZ_RX_HASH_INSRT_HDR_LBN 441019#define FRF_BZ_RX_HASH_INSRT_HDR_WIDTH 11020#define FRF_BZ_RX_DESC_PUSH_EN_LBN 431021#define FRF_BZ_RX_DESC_PUSH_EN_WIDTH 11022#define FRF_BZ_RX_RDW_PATCH_EN_LBN 421023#define FRF_BZ_RX_RDW_PATCH_EN_WIDTH 11024#define FRF_BB_RX_PCI_BURST_SIZE_LBN 391025#define FRF_BB_RX_PCI_BURST_SIZE_WIDTH 31026#define FRF_BZ_RX_OWNERR_CTL_LBN 381027#define FRF_BZ_RX_OWNERR_CTL_WIDTH 11028#define FRF_BZ_RX_XON_TX_TH_LBN 331029#define FRF_BZ_RX_XON_TX_TH_WIDTH 51030#define FRF_AA_RX_DESC_PUSH_EN_LBN 351031#define FRF_AA_RX_DESC_PUSH_EN_WIDTH 11032#define FRF_AA_RX_RDW_PATCH_EN_LBN 341033#define FRF_AA_RX_RDW_PATCH_EN_WIDTH 11034#define FRF_AA_RX_PCI_BURST_SIZE_LBN 311035#define FRF_AA_RX_PCI_BURST_SIZE_WIDTH 31036#define FRF_BZ_RX_XOFF_TX_TH_LBN 281037#define FRF_BZ_RX_XOFF_TX_TH_WIDTH 51038#define FRF_AA_RX_OWNERR_CTL_LBN 301039#define FRF_AA_RX_OWNERR_CTL_WIDTH 11040#define FRF_AA_RX_XON_TX_TH_LBN 251041#define FRF_AA_RX_XON_TX_TH_WIDTH 51042#define FRF_BZ_RX_USR_BUF_SIZE_LBN 191043#define FRF_BZ_RX_USR_BUF_SIZE_WIDTH 91044#define FRF_AA_RX_XOFF_TX_TH_LBN 201045#define FRF_AA_RX_XOFF_TX_TH_WIDTH 51046#define FRF_AA_RX_USR_BUF_SIZE_LBN 111047#define FRF_AA_RX_USR_BUF_SIZE_WIDTH 91048#define FRF_BZ_RX_XON_MAC_TH_LBN 101049#define FRF_BZ_RX_XON_MAC_TH_WIDTH 91050#define FRF_AA_RX_XON_MAC_TH_LBN 61051#define FRF_AA_RX_XON_MAC_TH_WIDTH 51052#define FRF_BZ_RX_XOFF_MAC_TH_LBN 11053#define FRF_BZ_RX_XOFF_MAC_TH_WIDTH 91054#define FRF_AA_RX_XOFF_MAC_TH_LBN 11055#define FRF_AA_RX_XOFF_MAC_TH_WIDTH 51056#define FRF_AZ_RX_XOFF_MAC_EN_LBN 01057#define FRF_AZ_RX_XOFF_MAC_EN_WIDTH 11058 1059/* RX_FILTER_CTL_REG: Receive filter control registers */1060#define FR_BZ_RX_FILTER_CTL 0x000008101061#define FRF_CZ_ETHERNET_WILDCARD_SEARCH_LIMIT_LBN 941062#define FRF_CZ_ETHERNET_WILDCARD_SEARCH_LIMIT_WIDTH 81063#define FRF_CZ_ETHERNET_FULL_SEARCH_LIMIT_LBN 861064#define FRF_CZ_ETHERNET_FULL_SEARCH_LIMIT_WIDTH 81065#define FRF_CZ_RX_FILTER_ALL_VLAN_ETHERTYPES_LBN 851066#define FRF_CZ_RX_FILTER_ALL_VLAN_ETHERTYPES_WIDTH 11067#define FRF_CZ_RX_VLAN_MATCH_ETHERTYPE_LBN 691068#define FRF_CZ_RX_VLAN_MATCH_ETHERTYPE_WIDTH 161069#define FRF_CZ_MULTICAST_NOMATCH_Q_ID_LBN 571070#define FRF_CZ_MULTICAST_NOMATCH_Q_ID_WIDTH 121071#define FRF_CZ_MULTICAST_NOMATCH_RSS_ENABLED_LBN 561072#define FRF_CZ_MULTICAST_NOMATCH_RSS_ENABLED_WIDTH 11073#define FRF_CZ_MULTICAST_NOMATCH_IP_OVERRIDE_LBN 551074#define FRF_CZ_MULTICAST_NOMATCH_IP_OVERRIDE_WIDTH 11075#define FRF_CZ_UNICAST_NOMATCH_Q_ID_LBN 431076#define FRF_CZ_UNICAST_NOMATCH_Q_ID_WIDTH 121077#define FRF_CZ_UNICAST_NOMATCH_RSS_ENABLED_LBN 421078#define FRF_CZ_UNICAST_NOMATCH_RSS_ENABLED_WIDTH 11079#define FRF_CZ_UNICAST_NOMATCH_IP_OVERRIDE_LBN 411080#define FRF_CZ_UNICAST_NOMATCH_IP_OVERRIDE_WIDTH 11081#define FRF_BZ_SCATTER_ENBL_NO_MATCH_Q_LBN 401082#define FRF_BZ_SCATTER_ENBL_NO_MATCH_Q_WIDTH 11083#define FRF_BZ_UDP_FULL_SRCH_LIMIT_LBN 321084#define FRF_BZ_UDP_FULL_SRCH_LIMIT_WIDTH 81085#define FRF_BZ_NUM_KER_LBN 241086#define FRF_BZ_NUM_KER_WIDTH 21087#define FRF_BZ_UDP_WILD_SRCH_LIMIT_LBN 161088#define FRF_BZ_UDP_WILD_SRCH_LIMIT_WIDTH 81089#define FRF_BZ_TCP_WILD_SRCH_LIMIT_LBN 81090#define FRF_BZ_TCP_WILD_SRCH_LIMIT_WIDTH 81091#define FRF_BZ_TCP_FULL_SRCH_LIMIT_LBN 01092#define FRF_BZ_TCP_FULL_SRCH_LIMIT_WIDTH 81093 1094/* RX_FLUSH_DESCQ_REG: Receive flush descriptor queue register */1095#define FR_AZ_RX_FLUSH_DESCQ 0x000008201096#define FRF_AZ_RX_FLUSH_DESCQ_CMD_LBN 241097#define FRF_AZ_RX_FLUSH_DESCQ_CMD_WIDTH 11098#define FRF_AZ_RX_FLUSH_DESCQ_LBN 01099#define FRF_AZ_RX_FLUSH_DESCQ_WIDTH 121100 1101/* RX_DESC_UPD_REGP0: Receive descriptor update register. */1102#define FR_BZ_RX_DESC_UPD_P0 0x000008301103#define FR_BZ_RX_DESC_UPD_P0_STEP 81921104#define FR_BZ_RX_DESC_UPD_P0_ROWS 10241105/* RX_DESC_UPD_REG_KER: Receive descriptor update register. */1106#define FR_AA_RX_DESC_UPD_KER 0x000008301107#define FR_AA_RX_DESC_UPD_KER_STEP 81921108#define FR_AA_RX_DESC_UPD_KER_ROWS 41109/* RX_DESC_UPD_REGP123: Receive descriptor update register. */1110#define FR_BB_RX_DESC_UPD_P123 0x010008301111#define FR_BB_RX_DESC_UPD_P123_STEP 81921112#define FR_BB_RX_DESC_UPD_P123_ROWS 30721113#define FRF_AZ_RX_DESC_WPTR_LBN 961114#define FRF_AZ_RX_DESC_WPTR_WIDTH 121115#define FRF_AZ_RX_DESC_PUSH_CMD_LBN 951116#define FRF_AZ_RX_DESC_PUSH_CMD_WIDTH 11117#define FRF_AZ_RX_DESC_LBN 01118#define FRF_AZ_RX_DESC_WIDTH 641119 1120/* RX_DC_CFG_REG: Receive descriptor cache configuration register */1121#define FR_AZ_RX_DC_CFG 0x000008401122#define FRF_AB_RX_MAX_PF_LBN 21123#define FRF_AB_RX_MAX_PF_WIDTH 21124#define FRF_AZ_RX_DC_SIZE_LBN 01125#define FRF_AZ_RX_DC_SIZE_WIDTH 21126#define FFE_AZ_RX_DC_SIZE_64 31127#define FFE_AZ_RX_DC_SIZE_32 21128#define FFE_AZ_RX_DC_SIZE_16 11129#define FFE_AZ_RX_DC_SIZE_8 01130 1131/* RX_DC_PF_WM_REG: Receive descriptor cache pre-fetch watermark register */1132#define FR_AZ_RX_DC_PF_WM 0x000008501133#define FRF_AZ_RX_DC_PF_HWM_LBN 61134#define FRF_AZ_RX_DC_PF_HWM_WIDTH 61135#define FRF_AZ_RX_DC_PF_LWM_LBN 01136#define FRF_AZ_RX_DC_PF_LWM_WIDTH 61137 1138/* RX_RSS_TKEY_REG: RSS Toeplitz hash key */1139#define FR_BZ_RX_RSS_TKEY 0x000008601140#define FRF_BZ_RX_RSS_TKEY_HI_LBN 641141#define FRF_BZ_RX_RSS_TKEY_HI_WIDTH 641142#define FRF_BZ_RX_RSS_TKEY_LO_LBN 01143#define FRF_BZ_RX_RSS_TKEY_LO_WIDTH 641144 1145/* RX_NODESC_DROP_REG: Receive dropped packet counter register */1146#define FR_AZ_RX_NODESC_DROP 0x000008801147#define FRF_CZ_RX_NODESC_DROP_CNT_LBN 01148#define FRF_CZ_RX_NODESC_DROP_CNT_WIDTH 321149#define FRF_AB_RX_NODESC_DROP_CNT_LBN 01150#define FRF_AB_RX_NODESC_DROP_CNT_WIDTH 161151 1152/* RX_SELF_RST_REG: Receive self reset register */1153#define FR_AA_RX_SELF_RST 0x000008901154#define FRF_AA_RX_ISCSI_DIS_LBN 171155#define FRF_AA_RX_ISCSI_DIS_WIDTH 11156#define FRF_AA_RX_SW_RST_REG_LBN 161157#define FRF_AA_RX_SW_RST_REG_WIDTH 11158#define FRF_AA_RX_NODESC_WAIT_DIS_LBN 91159#define FRF_AA_RX_NODESC_WAIT_DIS_WIDTH 11160#define FRF_AA_RX_SELF_RST_EN_LBN 81161#define FRF_AA_RX_SELF_RST_EN_WIDTH 11162#define FRF_AA_RX_MAX_PF_LAT_LBN 41163#define FRF_AA_RX_MAX_PF_LAT_WIDTH 41164#define FRF_AA_RX_MAX_LU_LAT_LBN 01165#define FRF_AA_RX_MAX_LU_LAT_WIDTH 41166 1167/* RX_DEBUG_REG: undocumented register */1168#define FR_AZ_RX_DEBUG 0x000008a01169#define FRF_AZ_RX_DEBUG_LBN 01170#define FRF_AZ_RX_DEBUG_WIDTH 641171 1172/* RX_PUSH_DROP_REG: Receive descriptor push dropped counter register */1173#define FR_AZ_RX_PUSH_DROP 0x000008b01174#define FRF_AZ_RX_PUSH_DROP_CNT_LBN 01175#define FRF_AZ_RX_PUSH_DROP_CNT_WIDTH 321176 1177/* RX_RSS_IPV6_REG1: IPv6 RSS Toeplitz hash key low bytes */1178#define FR_CZ_RX_RSS_IPV6_REG1 0x000008d01179#define FRF_CZ_RX_RSS_IPV6_TKEY_LO_LBN 01180#define FRF_CZ_RX_RSS_IPV6_TKEY_LO_WIDTH 1281181 1182/* RX_RSS_IPV6_REG2: IPv6 RSS Toeplitz hash key middle bytes */1183#define FR_CZ_RX_RSS_IPV6_REG2 0x000008e01184#define FRF_CZ_RX_RSS_IPV6_TKEY_MID_LBN 01185#define FRF_CZ_RX_RSS_IPV6_TKEY_MID_WIDTH 1281186 1187/* RX_RSS_IPV6_REG3: IPv6 RSS Toeplitz hash key upper bytes and IPv6 RSS settings */1188#define FR_CZ_RX_RSS_IPV6_REG3 0x000008f01189#define FRF_CZ_RX_RSS_IPV6_THASH_ENABLE_LBN 661190#define FRF_CZ_RX_RSS_IPV6_THASH_ENABLE_WIDTH 11191#define FRF_CZ_RX_RSS_IPV6_IP_THASH_ENABLE_LBN 651192#define FRF_CZ_RX_RSS_IPV6_IP_THASH_ENABLE_WIDTH 11193#define FRF_CZ_RX_RSS_IPV6_TCP_SUPPRESS_LBN 641194#define FRF_CZ_RX_RSS_IPV6_TCP_SUPPRESS_WIDTH 11195#define FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN 01196#define FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH 641197 1198/* TX_FLUSH_DESCQ_REG: Transmit flush descriptor queue register */1199#define FR_AZ_TX_FLUSH_DESCQ 0x00000a001200#define FRF_AZ_TX_FLUSH_DESCQ_CMD_LBN 121201#define FRF_AZ_TX_FLUSH_DESCQ_CMD_WIDTH 11202#define FRF_AZ_TX_FLUSH_DESCQ_LBN 01203#define FRF_AZ_TX_FLUSH_DESCQ_WIDTH 121204 1205/* TX_DESC_UPD_REGP0: Transmit descriptor update register. */1206#define FR_BZ_TX_DESC_UPD_P0 0x00000a101207#define FR_BZ_TX_DESC_UPD_P0_STEP 81921208#define FR_BZ_TX_DESC_UPD_P0_ROWS 10241209/* TX_DESC_UPD_REG_KER: Transmit descriptor update register. */1210#define FR_AA_TX_DESC_UPD_KER 0x00000a101211#define FR_AA_TX_DESC_UPD_KER_STEP 81921212#define FR_AA_TX_DESC_UPD_KER_ROWS 81213/* TX_DESC_UPD_REGP123: Transmit descriptor update register. */1214#define FR_BB_TX_DESC_UPD_P123 0x01000a101215#define FR_BB_TX_DESC_UPD_P123_STEP 81921216#define FR_BB_TX_DESC_UPD_P123_ROWS 30721217#define FRF_AZ_TX_DESC_WPTR_LBN 961218#define FRF_AZ_TX_DESC_WPTR_WIDTH 121219#define FRF_AZ_TX_DESC_PUSH_CMD_LBN 951220#define FRF_AZ_TX_DESC_PUSH_CMD_WIDTH 11221#define FRF_AZ_TX_DESC_LBN 01222#define FRF_AZ_TX_DESC_WIDTH 951223 1224/* TX_DC_CFG_REG: Transmit descriptor cache configuration register */1225#define FR_AZ_TX_DC_CFG 0x00000a201226#define FRF_AZ_TX_DC_SIZE_LBN 01227#define FRF_AZ_TX_DC_SIZE_WIDTH 21228#define FFE_AZ_TX_DC_SIZE_32 21229#define FFE_AZ_TX_DC_SIZE_16 11230#define FFE_AZ_TX_DC_SIZE_8 01231 1232/* TX_CHKSM_CFG_REG: Transmit checksum configuration register */1233#define FR_AA_TX_CHKSM_CFG 0x00000a301234#define FRF_AA_TX_Q_CHKSM_DIS_96_127_LBN 961235#define FRF_AA_TX_Q_CHKSM_DIS_96_127_WIDTH 321236#define FRF_AA_TX_Q_CHKSM_DIS_64_95_LBN 641237#define FRF_AA_TX_Q_CHKSM_DIS_64_95_WIDTH 321238#define FRF_AA_TX_Q_CHKSM_DIS_32_63_LBN 321239#define FRF_AA_TX_Q_CHKSM_DIS_32_63_WIDTH 321240#define FRF_AA_TX_Q_CHKSM_DIS_0_31_LBN 01241#define FRF_AA_TX_Q_CHKSM_DIS_0_31_WIDTH 321242 1243/* TX_CFG_REG: Transmit configuration register */1244#define FR_AZ_TX_CFG 0x00000a501245#define FRF_CZ_TX_CONT_LOOKUP_THRESH_RANGE_LBN 1141246#define FRF_CZ_TX_CONT_LOOKUP_THRESH_RANGE_WIDTH 81247#define FRF_CZ_TX_FILTER_TEST_MODE_BIT_LBN 1131248#define FRF_CZ_TX_FILTER_TEST_MODE_BIT_WIDTH 11249#define FRF_CZ_TX_ETH_FILTER_WILD_SEARCH_RANGE_LBN 1051250#define FRF_CZ_TX_ETH_FILTER_WILD_SEARCH_RANGE_WIDTH 81251#define FRF_CZ_TX_ETH_FILTER_FULL_SEARCH_RANGE_LBN 971252#define FRF_CZ_TX_ETH_FILTER_FULL_SEARCH_RANGE_WIDTH 81253#define FRF_CZ_TX_UDPIP_FILTER_WILD_SEARCH_RANGE_LBN 891254#define FRF_CZ_TX_UDPIP_FILTER_WILD_SEARCH_RANGE_WIDTH 81255#define FRF_CZ_TX_UDPIP_FILTER_FULL_SEARCH_RANGE_LBN 811256#define FRF_CZ_TX_UDPIP_FILTER_FULL_SEARCH_RANGE_WIDTH 81257#define FRF_CZ_TX_TCPIP_FILTER_WILD_SEARCH_RANGE_LBN 731258#define FRF_CZ_TX_TCPIP_FILTER_WILD_SEARCH_RANGE_WIDTH 81259#define FRF_CZ_TX_TCPIP_FILTER_FULL_SEARCH_RANGE_LBN 651260#define FRF_CZ_TX_TCPIP_FILTER_FULL_SEARCH_RANGE_WIDTH 81261#define FRF_CZ_TX_FILTER_ALL_VLAN_ETHERTYPES_BIT_LBN 641262#define FRF_CZ_TX_FILTER_ALL_VLAN_ETHERTYPES_BIT_WIDTH 11263#define FRF_CZ_TX_VLAN_MATCH_ETHERTYPE_RANGE_LBN 481264#define FRF_CZ_TX_VLAN_MATCH_ETHERTYPE_RANGE_WIDTH 161265#define FRF_CZ_TX_FILTER_EN_BIT_LBN 471266#define FRF_CZ_TX_FILTER_EN_BIT_WIDTH 11267#define FRF_AZ_TX_IP_ID_P0_OFS_LBN 161268#define FRF_AZ_TX_IP_ID_P0_OFS_WIDTH 151269#define FRF_AZ_TX_NO_EOP_DISC_EN_LBN 51270#define FRF_AZ_TX_NO_EOP_DISC_EN_WIDTH 11271#define FRF_AZ_TX_P1_PRI_EN_LBN 41272#define FRF_AZ_TX_P1_PRI_EN_WIDTH 11273#define FRF_AZ_TX_OWNERR_CTL_LBN 21274#define FRF_AZ_TX_OWNERR_CTL_WIDTH 11275#define FRF_AA_TX_NON_IP_DROP_DIS_LBN 11276#define FRF_AA_TX_NON_IP_DROP_DIS_WIDTH 11277#define FRF_AZ_TX_IP_ID_REP_EN_LBN 01278#define FRF_AZ_TX_IP_ID_REP_EN_WIDTH 11279 1280/* TX_PUSH_DROP_REG: Transmit push dropped register */1281#define FR_AZ_TX_PUSH_DROP 0x00000a601282#define FRF_AZ_TX_PUSH_DROP_CNT_LBN 01283#define FRF_AZ_TX_PUSH_DROP_CNT_WIDTH 321284 1285/* TX_RESERVED_REG: Transmit configuration register */1286#define FR_AZ_TX_RESERVED 0x00000a801287#define FRF_AZ_TX_EVT_CNT_LBN 1211288#define FRF_AZ_TX_EVT_CNT_WIDTH 71289#define FRF_AZ_TX_PREF_AGE_CNT_LBN 1191290#define FRF_AZ_TX_PREF_AGE_CNT_WIDTH 21291#define FRF_AZ_TX_RD_COMP_TMR_LBN 961292#define FRF_AZ_TX_RD_COMP_TMR_WIDTH 231293#define FRF_AZ_TX_PUSH_EN_LBN 891294#define FRF_AZ_TX_PUSH_EN_WIDTH 11295#define FRF_AZ_TX_PUSH_CHK_DIS_LBN 881296#define FRF_AZ_TX_PUSH_CHK_DIS_WIDTH 11297#define FRF_AZ_TX_D_FF_FULL_P0_LBN 851298#define FRF_AZ_TX_D_FF_FULL_P0_WIDTH 11299#define FRF_AZ_TX_DMAR_ST_P0_LBN 811300#define FRF_AZ_TX_DMAR_ST_P0_WIDTH 11301#define FRF_AZ_TX_DMAQ_ST_LBN 781302#define FRF_AZ_TX_DMAQ_ST_WIDTH 11303#define FRF_AZ_TX_RX_SPACER_LBN 641304#define FRF_AZ_TX_RX_SPACER_WIDTH 81305#define FRF_AZ_TX_DROP_ABORT_EN_LBN 601306#define FRF_AZ_TX_DROP_ABORT_EN_WIDTH 11307#define FRF_AZ_TX_SOFT_EVT_EN_LBN 591308#define FRF_AZ_TX_SOFT_EVT_EN_WIDTH 11309#define FRF_AZ_TX_PS_EVT_DIS_LBN 581310#define FRF_AZ_TX_PS_EVT_DIS_WIDTH 11311#define FRF_AZ_TX_RX_SPACER_EN_LBN 571312#define FRF_AZ_TX_RX_SPACER_EN_WIDTH 11313#define FRF_AZ_TX_XP_TIMER_LBN 521314#define FRF_AZ_TX_XP_TIMER_WIDTH 51315#define FRF_AZ_TX_PREF_SPACER_LBN 441316#define FRF_AZ_TX_PREF_SPACER_WIDTH 81317#define FRF_AZ_TX_PREF_WD_TMR_LBN 221318#define FRF_AZ_TX_PREF_WD_TMR_WIDTH 221319#define FRF_AZ_TX_ONLY1TAG_LBN 211320#define FRF_AZ_TX_ONLY1TAG_WIDTH 11321#define FRF_AZ_TX_PREF_THRESHOLD_LBN 191322#define FRF_AZ_TX_PREF_THRESHOLD_WIDTH 21323#define FRF_AZ_TX_ONE_PKT_PER_Q_LBN 181324#define FRF_AZ_TX_ONE_PKT_PER_Q_WIDTH 11325#define FRF_AZ_TX_DIS_NON_IP_EV_LBN 171326#define FRF_AZ_TX_DIS_NON_IP_EV_WIDTH 11327#define FRF_AA_TX_DMA_FF_THR_LBN 161328#define FRF_AA_TX_DMA_FF_THR_WIDTH 11329#define FRF_AZ_TX_DMA_SPACER_LBN 81330#define FRF_AZ_TX_DMA_SPACER_WIDTH 81331#define FRF_AA_TX_TCP_DIS_LBN 71332#define FRF_AA_TX_TCP_DIS_WIDTH 11333#define FRF_BZ_TX_FLUSH_MIN_LEN_EN_LBN 71334#define FRF_BZ_TX_FLUSH_MIN_LEN_EN_WIDTH 11335#define FRF_AA_TX_IP_DIS_LBN 61336#define FRF_AA_TX_IP_DIS_WIDTH 11337#define FRF_AZ_TX_MAX_CPL_LBN 21338#define FRF_AZ_TX_MAX_CPL_WIDTH 21339#define FFE_AZ_TX_MAX_CPL_16 31340#define FFE_AZ_TX_MAX_CPL_8 21341#define FFE_AZ_TX_MAX_CPL_4 11342#define FFE_AZ_TX_MAX_CPL_NOLIMIT 01343#define FRF_AZ_TX_MAX_PREF_LBN 01344#define FRF_AZ_TX_MAX_PREF_WIDTH 21345#define FFE_AZ_TX_MAX_PREF_32 31346#define FFE_AZ_TX_MAX_PREF_16 21347#define FFE_AZ_TX_MAX_PREF_8 11348#define FFE_AZ_TX_MAX_PREF_OFF 01349 1350/* TX_PACE_REG: Transmit pace control register */1351#define FR_BZ_TX_PACE 0x00000a901352#define FRF_BZ_TX_PACE_SB_NOT_AF_LBN 191353#define FRF_BZ_TX_PACE_SB_NOT_AF_WIDTH 101354#define FRF_BZ_TX_PACE_SB_AF_LBN 91355#define FRF_BZ_TX_PACE_SB_AF_WIDTH 101356#define FRF_BZ_TX_PACE_FB_BASE_LBN 51357#define FRF_BZ_TX_PACE_FB_BASE_WIDTH 41358#define FRF_BZ_TX_PACE_BIN_TH_LBN 01359#define FRF_BZ_TX_PACE_BIN_TH_WIDTH 51360 1361/* TX_PACE_DROP_QID_REG: PACE Drop QID Counter */1362#define FR_BZ_TX_PACE_DROP_QID 0x00000aa01363#define FRF_BZ_TX_PACE_QID_DRP_CNT_LBN 01364#define FRF_BZ_TX_PACE_QID_DRP_CNT_WIDTH 161365 1366/* TX_VLAN_REG: Transmit VLAN tag register */1367#define FR_BB_TX_VLAN 0x00000ae01368#define FRF_BB_TX_VLAN_EN_LBN 1271369#define FRF_BB_TX_VLAN_EN_WIDTH 11370#define FRF_BB_TX_VLAN7_PORT1_EN_LBN 1251371#define FRF_BB_TX_VLAN7_PORT1_EN_WIDTH 11372#define FRF_BB_TX_VLAN7_PORT0_EN_LBN 1241373#define FRF_BB_TX_VLAN7_PORT0_EN_WIDTH 11374#define FRF_BB_TX_VLAN7_LBN 1121375#define FRF_BB_TX_VLAN7_WIDTH 121376#define FRF_BB_TX_VLAN6_PORT1_EN_LBN 1091377#define FRF_BB_TX_VLAN6_PORT1_EN_WIDTH 11378#define FRF_BB_TX_VLAN6_PORT0_EN_LBN 1081379#define FRF_BB_TX_VLAN6_PORT0_EN_WIDTH 11380#define FRF_BB_TX_VLAN6_LBN 961381#define FRF_BB_TX_VLAN6_WIDTH 121382#define FRF_BB_TX_VLAN5_PORT1_EN_LBN 931383#define FRF_BB_TX_VLAN5_PORT1_EN_WIDTH 11384#define FRF_BB_TX_VLAN5_PORT0_EN_LBN 921385#define FRF_BB_TX_VLAN5_PORT0_EN_WIDTH 11386#define FRF_BB_TX_VLAN5_LBN 801387#define FRF_BB_TX_VLAN5_WIDTH 121388#define FRF_BB_TX_VLAN4_PORT1_EN_LBN 771389#define FRF_BB_TX_VLAN4_PORT1_EN_WIDTH 11390#define FRF_BB_TX_VLAN4_PORT0_EN_LBN 761391#define FRF_BB_TX_VLAN4_PORT0_EN_WIDTH 11392#define FRF_BB_TX_VLAN4_LBN 641393#define FRF_BB_TX_VLAN4_WIDTH 121394#define FRF_BB_TX_VLAN3_PORT1_EN_LBN 611395#define FRF_BB_TX_VLAN3_PORT1_EN_WIDTH 11396#define FRF_BB_TX_VLAN3_PORT0_EN_LBN 601397#define FRF_BB_TX_VLAN3_PORT0_EN_WIDTH 11398#define FRF_BB_TX_VLAN3_LBN 481399#define FRF_BB_TX_VLAN3_WIDTH 121400#define FRF_BB_TX_VLAN2_PORT1_EN_LBN 451401#define FRF_BB_TX_VLAN2_PORT1_EN_WIDTH 11402#define FRF_BB_TX_VLAN2_PORT0_EN_LBN 441403#define FRF_BB_TX_VLAN2_PORT0_EN_WIDTH 11404#define FRF_BB_TX_VLAN2_LBN 321405#define FRF_BB_TX_VLAN2_WIDTH 121406#define FRF_BB_TX_VLAN1_PORT1_EN_LBN 291407#define FRF_BB_TX_VLAN1_PORT1_EN_WIDTH 11408#define FRF_BB_TX_VLAN1_PORT0_EN_LBN 281409#define FRF_BB_TX_VLAN1_PORT0_EN_WIDTH 11410#define FRF_BB_TX_VLAN1_LBN 161411#define FRF_BB_TX_VLAN1_WIDTH 121412#define FRF_BB_TX_VLAN0_PORT1_EN_LBN 131413#define FRF_BB_TX_VLAN0_PORT1_EN_WIDTH 11414#define FRF_BB_TX_VLAN0_PORT0_EN_LBN 121415#define FRF_BB_TX_VLAN0_PORT0_EN_WIDTH 11416#define FRF_BB_TX_VLAN0_LBN 01417#define FRF_BB_TX_VLAN0_WIDTH 121418 1419/* TX_IPFIL_PORTEN_REG: Transmit filter control register */1420#define FR_BZ_TX_IPFIL_PORTEN 0x00000af01421#define FRF_BZ_TX_MADR0_FIL_EN_LBN 641422#define FRF_BZ_TX_MADR0_FIL_EN_WIDTH 11423#define FRF_BB_TX_IPFIL31_PORT_EN_LBN 621424#define FRF_BB_TX_IPFIL31_PORT_EN_WIDTH 11425#define FRF_BB_TX_IPFIL30_PORT_EN_LBN 601426#define FRF_BB_TX_IPFIL30_PORT_EN_WIDTH 11427#define FRF_BB_TX_IPFIL29_PORT_EN_LBN 581428#define FRF_BB_TX_IPFIL29_PORT_EN_WIDTH 11429#define FRF_BB_TX_IPFIL28_PORT_EN_LBN 561430#define FRF_BB_TX_IPFIL28_PORT_EN_WIDTH 11431#define FRF_BB_TX_IPFIL27_PORT_EN_LBN 541432#define FRF_BB_TX_IPFIL27_PORT_EN_WIDTH 11433#define FRF_BB_TX_IPFIL26_PORT_EN_LBN 521434#define FRF_BB_TX_IPFIL26_PORT_EN_WIDTH 11435#define FRF_BB_TX_IPFIL25_PORT_EN_LBN 501436#define FRF_BB_TX_IPFIL25_PORT_EN_WIDTH 11437#define FRF_BB_TX_IPFIL24_PORT_EN_LBN 481438#define FRF_BB_TX_IPFIL24_PORT_EN_WIDTH 11439#define FRF_BB_TX_IPFIL23_PORT_EN_LBN 461440#define FRF_BB_TX_IPFIL23_PORT_EN_WIDTH 11441#define FRF_BB_TX_IPFIL22_PORT_EN_LBN 441442#define FRF_BB_TX_IPFIL22_PORT_EN_WIDTH 11443#define FRF_BB_TX_IPFIL21_PORT_EN_LBN 421444#define FRF_BB_TX_IPFIL21_PORT_EN_WIDTH 11445#define FRF_BB_TX_IPFIL20_PORT_EN_LBN 401446#define FRF_BB_TX_IPFIL20_PORT_EN_WIDTH 11447#define FRF_BB_TX_IPFIL19_PORT_EN_LBN 381448#define FRF_BB_TX_IPFIL19_PORT_EN_WIDTH 11449#define FRF_BB_TX_IPFIL18_PORT_EN_LBN 361450#define FRF_BB_TX_IPFIL18_PORT_EN_WIDTH 11451#define FRF_BB_TX_IPFIL17_PORT_EN_LBN 341452#define FRF_BB_TX_IPFIL17_PORT_EN_WIDTH 11453#define FRF_BB_TX_IPFIL16_PORT_EN_LBN 321454#define FRF_BB_TX_IPFIL16_PORT_EN_WIDTH 11455#define FRF_BB_TX_IPFIL15_PORT_EN_LBN 301456#define FRF_BB_TX_IPFIL15_PORT_EN_WIDTH 11457#define FRF_BB_TX_IPFIL14_PORT_EN_LBN 281458#define FRF_BB_TX_IPFIL14_PORT_EN_WIDTH 11459#define FRF_BB_TX_IPFIL13_PORT_EN_LBN 261460#define FRF_BB_TX_IPFIL13_PORT_EN_WIDTH 11461#define FRF_BB_TX_IPFIL12_PORT_EN_LBN 241462#define FRF_BB_TX_IPFIL12_PORT_EN_WIDTH 11463#define FRF_BB_TX_IPFIL11_PORT_EN_LBN 221464#define FRF_BB_TX_IPFIL11_PORT_EN_WIDTH 11465#define FRF_BB_TX_IPFIL10_PORT_EN_LBN 201466#define FRF_BB_TX_IPFIL10_PORT_EN_WIDTH 11467#define FRF_BB_TX_IPFIL9_PORT_EN_LBN 181468#define FRF_BB_TX_IPFIL9_PORT_EN_WIDTH 11469#define FRF_BB_TX_IPFIL8_PORT_EN_LBN 161470#define FRF_BB_TX_IPFIL8_PORT_EN_WIDTH 11471#define FRF_BB_TX_IPFIL7_PORT_EN_LBN 141472#define FRF_BB_TX_IPFIL7_PORT_EN_WIDTH 11473#define FRF_BB_TX_IPFIL6_PORT_EN_LBN 121474#define FRF_BB_TX_IPFIL6_PORT_EN_WIDTH 11475#define FRF_BB_TX_IPFIL5_PORT_EN_LBN 101476#define FRF_BB_TX_IPFIL5_PORT_EN_WIDTH 11477#define FRF_BB_TX_IPFIL4_PORT_EN_LBN 81478#define FRF_BB_TX_IPFIL4_PORT_EN_WIDTH 11479#define FRF_BB_TX_IPFIL3_PORT_EN_LBN 61480#define FRF_BB_TX_IPFIL3_PORT_EN_WIDTH 11481#define FRF_BB_TX_IPFIL2_PORT_EN_LBN 41482#define FRF_BB_TX_IPFIL2_PORT_EN_WIDTH 11483#define FRF_BB_TX_IPFIL1_PORT_EN_LBN 21484#define FRF_BB_TX_IPFIL1_PORT_EN_WIDTH 11485#define FRF_BB_TX_IPFIL0_PORT_EN_LBN 01486#define FRF_BB_TX_IPFIL0_PORT_EN_WIDTH 11487 1488/* TX_IPFIL_TBL: Transmit IP source address filter table */1489#define FR_BB_TX_IPFIL_TBL 0x00000b001490#define FR_BB_TX_IPFIL_TBL_STEP 161491#define FR_BB_TX_IPFIL_TBL_ROWS 161492#define FRF_BB_TX_IPFIL_MASK_1_LBN 961493#define FRF_BB_TX_IPFIL_MASK_1_WIDTH 321494#define FRF_BB_TX_IP_SRC_ADR_1_LBN 641495#define FRF_BB_TX_IP_SRC_ADR_1_WIDTH 321496#define FRF_BB_TX_IPFIL_MASK_0_LBN 321497#define FRF_BB_TX_IPFIL_MASK_0_WIDTH 321498#define FRF_BB_TX_IP_SRC_ADR_0_LBN 01499#define FRF_BB_TX_IP_SRC_ADR_0_WIDTH 321500 1501/* MD_TXD_REG: PHY management transmit data register */1502#define FR_AB_MD_TXD 0x00000c001503#define FRF_AB_MD_TXD_LBN 01504#define FRF_AB_MD_TXD_WIDTH 161505 1506/* MD_RXD_REG: PHY management receive data register */1507#define FR_AB_MD_RXD 0x00000c101508#define FRF_AB_MD_RXD_LBN 01509#define FRF_AB_MD_RXD_WIDTH 161510 1511/* MD_CS_REG: PHY management configuration & status register */1512#define FR_AB_MD_CS 0x00000c201513#define FRF_AB_MD_RD_EN_CMD_LBN 151514#define FRF_AB_MD_RD_EN_CMD_WIDTH 11515#define FRF_AB_MD_WR_EN_CMD_LBN 141516#define FRF_AB_MD_WR_EN_CMD_WIDTH 11517#define FRF_AB_MD_ADDR_CMD_LBN 131518#define FRF_AB_MD_ADDR_CMD_WIDTH 11519#define FRF_AB_MD_PT_LBN 71520#define FRF_AB_MD_PT_WIDTH 31521#define FRF_AB_MD_PL_LBN 61522#define FRF_AB_MD_PL_WIDTH 11523#define FRF_AB_MD_INT_CLR_LBN 51524#define FRF_AB_MD_INT_CLR_WIDTH 11525#define FRF_AB_MD_GC_LBN 41526#define FRF_AB_MD_GC_WIDTH 11527#define FRF_AB_MD_PRSP_LBN 31528#define FRF_AB_MD_PRSP_WIDTH 11529#define FRF_AB_MD_RIC_LBN 21530#define FRF_AB_MD_RIC_WIDTH 11531#define FRF_AB_MD_RDC_LBN 11532#define FRF_AB_MD_RDC_WIDTH 11533#define FRF_AB_MD_WRC_LBN 01534#define FRF_AB_MD_WRC_WIDTH 11535 1536/* MD_PHY_ADR_REG: PHY management PHY address register */1537#define FR_AB_MD_PHY_ADR 0x00000c301538#define FRF_AB_MD_PHY_ADR_LBN 01539#define FRF_AB_MD_PHY_ADR_WIDTH 161540 1541/* MD_ID_REG: PHY management ID register */1542#define FR_AB_MD_ID 0x00000c401543#define FRF_AB_MD_PRT_ADR_LBN 111544#define FRF_AB_MD_PRT_ADR_WIDTH 51545#define FRF_AB_MD_DEV_ADR_LBN 61546#define FRF_AB_MD_DEV_ADR_WIDTH 51547 1548/* MD_STAT_REG: PHY management status & mask register */1549#define FR_AB_MD_STAT 0x00000c501550#define FRF_AB_MD_PINT_LBN 41551#define FRF_AB_MD_PINT_WIDTH 11552#define FRF_AB_MD_DONE_LBN 31553#define FRF_AB_MD_DONE_WIDTH 11554#define FRF_AB_MD_BSERR_LBN 21555#define FRF_AB_MD_BSERR_WIDTH 11556#define FRF_AB_MD_LNFL_LBN 11557#define FRF_AB_MD_LNFL_WIDTH 11558#define FRF_AB_MD_BSY_LBN 01559#define FRF_AB_MD_BSY_WIDTH 11560 1561/* MAC_STAT_DMA_REG: Port MAC statistical counter DMA register */1562#define FR_AB_MAC_STAT_DMA 0x00000c601563#define FRF_AB_MAC_STAT_DMA_CMD_LBN 481564#define FRF_AB_MAC_STAT_DMA_CMD_WIDTH 11565#define FRF_AB_MAC_STAT_DMA_ADR_LBN 01566#define FRF_AB_MAC_STAT_DMA_ADR_WIDTH 481567 1568/* MAC_CTRL_REG: Port MAC control register */1569#define FR_AB_MAC_CTRL 0x00000c801570#define FRF_AB_MAC_XOFF_VAL_LBN 161571#define FRF_AB_MAC_XOFF_VAL_WIDTH 161572#define FRF_BB_TXFIFO_DRAIN_EN_LBN 71573#define FRF_BB_TXFIFO_DRAIN_EN_WIDTH 11574#define FRF_AB_MAC_XG_DISTXCRC_LBN 51575#define FRF_AB_MAC_XG_DISTXCRC_WIDTH 11576#define FRF_AB_MAC_BCAD_ACPT_LBN 41577#define FRF_AB_MAC_BCAD_ACPT_WIDTH 11578#define FRF_AB_MAC_UC_PROM_LBN 31579#define FRF_AB_MAC_UC_PROM_WIDTH 11580#define FRF_AB_MAC_LINK_STATUS_LBN 21581#define FRF_AB_MAC_LINK_STATUS_WIDTH 11582#define FRF_AB_MAC_SPEED_LBN 01583#define FRF_AB_MAC_SPEED_WIDTH 21584#define FFE_AB_MAC_SPEED_10G 31585#define FFE_AB_MAC_SPEED_1G 21586#define FFE_AB_MAC_SPEED_100M 11587#define FFE_AB_MAC_SPEED_10M 01588 1589/* GEN_MODE_REG: General Purpose mode register (external interrupt mask) */1590#define FR_BB_GEN_MODE 0x00000c901591#define FRF_BB_XFP_PHY_INT_POL_SEL_LBN 31592#define FRF_BB_XFP_PHY_INT_POL_SEL_WIDTH 11593#define FRF_BB_XG_PHY_INT_POL_SEL_LBN 21594#define FRF_BB_XG_PHY_INT_POL_SEL_WIDTH 11595#define FRF_BB_XFP_PHY_INT_MASK_LBN 11596#define FRF_BB_XFP_PHY_INT_MASK_WIDTH 11597#define FRF_BB_XG_PHY_INT_MASK_LBN 01598#define FRF_BB_XG_PHY_INT_MASK_WIDTH 11599 1600/* MAC_MC_HASH_REG0: Multicast address hash table */1601#define FR_AB_MAC_MC_HASH_REG0 0x00000ca01602#define FRF_AB_MAC_MCAST_HASH0_LBN 01603#define FRF_AB_MAC_MCAST_HASH0_WIDTH 1281604 1605/* MAC_MC_HASH_REG1: Multicast address hash table */1606#define FR_AB_MAC_MC_HASH_REG1 0x00000cb01607#define FRF_AB_MAC_MCAST_HASH1_LBN 01608#define FRF_AB_MAC_MCAST_HASH1_WIDTH 1281609 1610/* GM_CFG1_REG: GMAC configuration register 1 */1611#define FR_AB_GM_CFG1 0x00000e001612#define FRF_AB_GM_SW_RST_LBN 311613#define FRF_AB_GM_SW_RST_WIDTH 11614#define FRF_AB_GM_SIM_RST_LBN 301615#define FRF_AB_GM_SIM_RST_WIDTH 11616#define FRF_AB_GM_RST_RX_MAC_CTL_LBN 191617#define FRF_AB_GM_RST_RX_MAC_CTL_WIDTH 11618#define FRF_AB_GM_RST_TX_MAC_CTL_LBN 181619#define FRF_AB_GM_RST_TX_MAC_CTL_WIDTH 11620#define FRF_AB_GM_RST_RX_FUNC_LBN 171621#define FRF_AB_GM_RST_RX_FUNC_WIDTH 11622#define FRF_AB_GM_RST_TX_FUNC_LBN 161623#define FRF_AB_GM_RST_TX_FUNC_WIDTH 11624#define FRF_AB_GM_LOOP_LBN 81625#define FRF_AB_GM_LOOP_WIDTH 11626#define FRF_AB_GM_RX_FC_EN_LBN 51627#define FRF_AB_GM_RX_FC_EN_WIDTH 11628#define FRF_AB_GM_TX_FC_EN_LBN 41629#define FRF_AB_GM_TX_FC_EN_WIDTH 11630#define FRF_AB_GM_SYNC_RXEN_LBN 31631#define FRF_AB_GM_SYNC_RXEN_WIDTH 11632#define FRF_AB_GM_RX_EN_LBN 21633#define FRF_AB_GM_RX_EN_WIDTH 11634#define FRF_AB_GM_SYNC_TXEN_LBN 11635#define FRF_AB_GM_SYNC_TXEN_WIDTH 11636#define FRF_AB_GM_TX_EN_LBN 01637#define FRF_AB_GM_TX_EN_WIDTH 11638 1639/* GM_CFG2_REG: GMAC configuration register 2 */1640#define FR_AB_GM_CFG2 0x00000e101641#define FRF_AB_GM_PAMBL_LEN_LBN 121642#define FRF_AB_GM_PAMBL_LEN_WIDTH 41643#define FRF_AB_GM_IF_MODE_LBN 81644#define FRF_AB_GM_IF_MODE_WIDTH 21645#define FFE_AB_IF_MODE_BYTE_MODE 21646#define FFE_AB_IF_MODE_NIBBLE_MODE 11647#define FRF_AB_GM_HUGE_FRM_EN_LBN 51648#define FRF_AB_GM_HUGE_FRM_EN_WIDTH 11649#define FRF_AB_GM_LEN_CHK_LBN 41650#define FRF_AB_GM_LEN_CHK_WIDTH 11651#define FRF_AB_GM_PAD_CRC_EN_LBN 21652#define FRF_AB_GM_PAD_CRC_EN_WIDTH 11653#define FRF_AB_GM_CRC_EN_LBN 11654#define FRF_AB_GM_CRC_EN_WIDTH 11655#define FRF_AB_GM_FD_LBN 01656#define FRF_AB_GM_FD_WIDTH 11657 1658/* GM_IPG_REG: GMAC IPG register */1659#define FR_AB_GM_IPG 0x00000e201660#define FRF_AB_GM_NONB2B_IPG1_LBN 241661#define FRF_AB_GM_NONB2B_IPG1_WIDTH 71662#define FRF_AB_GM_NONB2B_IPG2_LBN 161663#define FRF_AB_GM_NONB2B_IPG2_WIDTH 71664#define FRF_AB_GM_MIN_IPG_ENF_LBN 81665#define FRF_AB_GM_MIN_IPG_ENF_WIDTH 81666#define FRF_AB_GM_B2B_IPG_LBN 01667#define FRF_AB_GM_B2B_IPG_WIDTH 71668 1669/* GM_HD_REG: GMAC half duplex register */1670#define FR_AB_GM_HD 0x00000e301671#define FRF_AB_GM_ALT_BOFF_VAL_LBN 201672#define FRF_AB_GM_ALT_BOFF_VAL_WIDTH 41673#define FRF_AB_GM_ALT_BOFF_EN_LBN 191674#define FRF_AB_GM_ALT_BOFF_EN_WIDTH 11675#define FRF_AB_GM_BP_NO_BOFF_LBN 181676#define FRF_AB_GM_BP_NO_BOFF_WIDTH 11677#define FRF_AB_GM_DIS_BOFF_LBN 171678#define FRF_AB_GM_DIS_BOFF_WIDTH 11679#define FRF_AB_GM_EXDEF_TX_EN_LBN 161680#define FRF_AB_GM_EXDEF_TX_EN_WIDTH 11681#define FRF_AB_GM_RTRY_LIMIT_LBN 121682#define FRF_AB_GM_RTRY_LIMIT_WIDTH 41683#define FRF_AB_GM_COL_WIN_LBN 01684#define FRF_AB_GM_COL_WIN_WIDTH 101685 1686/* GM_MAX_FLEN_REG: GMAC maximum frame length register */1687#define FR_AB_GM_MAX_FLEN 0x00000e401688#define FRF_AB_GM_MAX_FLEN_LBN 01689#define FRF_AB_GM_MAX_FLEN_WIDTH 161690 1691/* GM_TEST_REG: GMAC test register */1692#define FR_AB_GM_TEST 0x00000e701693#define FRF_AB_GM_MAX_BOFF_LBN 31694#define FRF_AB_GM_MAX_BOFF_WIDTH 11695#define FRF_AB_GM_REG_TX_FLOW_EN_LBN 21696#define FRF_AB_GM_REG_TX_FLOW_EN_WIDTH 11697#define FRF_AB_GM_TEST_PAUSE_LBN 11698#define FRF_AB_GM_TEST_PAUSE_WIDTH 11699#define FRF_AB_GM_SHORT_SLOT_LBN 01700#define FRF_AB_GM_SHORT_SLOT_WIDTH 11701 1702/* GM_ADR1_REG: GMAC station address register 1 */1703#define FR_AB_GM_ADR1 0x00000f001704#define FRF_AB_GM_ADR_B0_LBN 241705#define FRF_AB_GM_ADR_B0_WIDTH 81706#define FRF_AB_GM_ADR_B1_LBN 161707#define FRF_AB_GM_ADR_B1_WIDTH 81708#define FRF_AB_GM_ADR_B2_LBN 81709#define FRF_AB_GM_ADR_B2_WIDTH 81710#define FRF_AB_GM_ADR_B3_LBN 01711#define FRF_AB_GM_ADR_B3_WIDTH 81712 1713/* GM_ADR2_REG: GMAC station address register 2 */1714#define FR_AB_GM_ADR2 0x00000f101715#define FRF_AB_GM_ADR_B4_LBN 241716#define FRF_AB_GM_ADR_B4_WIDTH 81717#define FRF_AB_GM_ADR_B5_LBN 161718#define FRF_AB_GM_ADR_B5_WIDTH 81719 1720/* GMF_CFG0_REG: GMAC FIFO configuration register 0 */1721#define FR_AB_GMF_CFG0 0x00000f201722#define FRF_AB_GMF_FTFENRPLY_LBN 201723#define FRF_AB_GMF_FTFENRPLY_WIDTH 11724#define FRF_AB_GMF_STFENRPLY_LBN 191725#define FRF_AB_GMF_STFENRPLY_WIDTH 11726#define FRF_AB_GMF_FRFENRPLY_LBN 181727#define FRF_AB_GMF_FRFENRPLY_WIDTH 11728#define FRF_AB_GMF_SRFENRPLY_LBN 171729#define FRF_AB_GMF_SRFENRPLY_WIDTH 11730#define FRF_AB_GMF_WTMENRPLY_LBN 161731#define FRF_AB_GMF_WTMENRPLY_WIDTH 11732#define FRF_AB_GMF_FTFENREQ_LBN 121733#define FRF_AB_GMF_FTFENREQ_WIDTH 11734#define FRF_AB_GMF_STFENREQ_LBN 111735#define FRF_AB_GMF_STFENREQ_WIDTH 11736#define FRF_AB_GMF_FRFENREQ_LBN 101737#define FRF_AB_GMF_FRFENREQ_WIDTH 11738#define FRF_AB_GMF_SRFENREQ_LBN 91739#define FRF_AB_GMF_SRFENREQ_WIDTH 11740#define FRF_AB_GMF_WTMENREQ_LBN 81741#define FRF_AB_GMF_WTMENREQ_WIDTH 11742#define FRF_AB_GMF_HSTRSTFT_LBN 41743#define FRF_AB_GMF_HSTRSTFT_WIDTH 11744#define FRF_AB_GMF_HSTRSTST_LBN 31745#define FRF_AB_GMF_HSTRSTST_WIDTH 11746#define FRF_AB_GMF_HSTRSTFR_LBN 21747#define FRF_AB_GMF_HSTRSTFR_WIDTH 11748#define FRF_AB_GMF_HSTRSTSR_LBN 11749#define FRF_AB_GMF_HSTRSTSR_WIDTH 11750#define FRF_AB_GMF_HSTRSTWT_LBN 01751#define FRF_AB_GMF_HSTRSTWT_WIDTH 11752 1753/* GMF_CFG1_REG: GMAC FIFO configuration register 1 */1754#define FR_AB_GMF_CFG1 0x00000f301755#define FRF_AB_GMF_CFGFRTH_LBN 161756#define FRF_AB_GMF_CFGFRTH_WIDTH 51757#define FRF_AB_GMF_CFGXOFFRTX_LBN 01758#define FRF_AB_GMF_CFGXOFFRTX_WIDTH 161759 1760/* GMF_CFG2_REG: GMAC FIFO configuration register 2 */1761#define FR_AB_GMF_CFG2 0x00000f401762#define FRF_AB_GMF_CFGHWM_LBN 161763#define FRF_AB_GMF_CFGHWM_WIDTH 61764#define FRF_AB_GMF_CFGLWM_LBN 01765#define FRF_AB_GMF_CFGLWM_WIDTH 61766 1767/* GMF_CFG3_REG: GMAC FIFO configuration register 3 */1768#define FR_AB_GMF_CFG3 0x00000f501769#define FRF_AB_GMF_CFGHWMFT_LBN 161770#define FRF_AB_GMF_CFGHWMFT_WIDTH 61771#define FRF_AB_GMF_CFGFTTH_LBN 01772#define FRF_AB_GMF_CFGFTTH_WIDTH 61773 1774/* GMF_CFG4_REG: GMAC FIFO configuration register 4 */1775#define FR_AB_GMF_CFG4 0x00000f601776#define FRF_AB_GMF_HSTFLTRFRM_LBN 01777#define FRF_AB_GMF_HSTFLTRFRM_WIDTH 181778 1779/* GMF_CFG5_REG: GMAC FIFO configuration register 5 */1780#define FR_AB_GMF_CFG5 0x00000f701781#define FRF_AB_GMF_CFGHDPLX_LBN 221782#define FRF_AB_GMF_CFGHDPLX_WIDTH 11783#define FRF_AB_GMF_SRFULL_LBN 211784#define FRF_AB_GMF_SRFULL_WIDTH 11785#define FRF_AB_GMF_HSTSRFULLCLR_LBN 201786#define FRF_AB_GMF_HSTSRFULLCLR_WIDTH 11787#define FRF_AB_GMF_CFGBYTMODE_LBN 191788#define FRF_AB_GMF_CFGBYTMODE_WIDTH 11789#define FRF_AB_GMF_HSTDRPLT64_LBN 181790#define FRF_AB_GMF_HSTDRPLT64_WIDTH 11791#define FRF_AB_GMF_HSTFLTRFRMDC_LBN 01792#define FRF_AB_GMF_HSTFLTRFRMDC_WIDTH 181793 1794/* TX_SRC_MAC_TBL: Transmit IP source address filter table */1795#define FR_BB_TX_SRC_MAC_TBL 0x000010001796#define FR_BB_TX_SRC_MAC_TBL_STEP 161797#define FR_BB_TX_SRC_MAC_TBL_ROWS 161798#define FRF_BB_TX_SRC_MAC_ADR_1_LBN 641799#define FRF_BB_TX_SRC_MAC_ADR_1_WIDTH 481800#define FRF_BB_TX_SRC_MAC_ADR_0_LBN 01801#define FRF_BB_TX_SRC_MAC_ADR_0_WIDTH 481802 1803/* TX_SRC_MAC_CTL_REG: Transmit MAC source address filter control */1804#define FR_BB_TX_SRC_MAC_CTL 0x000011001805#define FRF_BB_TX_SRC_DROP_CTR_LBN 161806#define FRF_BB_TX_SRC_DROP_CTR_WIDTH 161807#define FRF_BB_TX_SRC_FLTR_EN_LBN 151808#define FRF_BB_TX_SRC_FLTR_EN_WIDTH 11809#define FRF_BB_TX_DROP_CTR_CLR_LBN 121810#define FRF_BB_TX_DROP_CTR_CLR_WIDTH 11811#define FRF_BB_TX_MAC_QID_SEL_LBN 01812#define FRF_BB_TX_MAC_QID_SEL_WIDTH 31813 1814/* XM_ADR_LO_REG: XGMAC address register low */1815#define FR_AB_XM_ADR_LO 0x000012001816#define FRF_AB_XM_ADR_LO_LBN 01817#define FRF_AB_XM_ADR_LO_WIDTH 321818 1819/* XM_ADR_HI_REG: XGMAC address register high */1820#define FR_AB_XM_ADR_HI 0x000012101821#define FRF_AB_XM_ADR_HI_LBN 01822#define FRF_AB_XM_ADR_HI_WIDTH 161823 1824/* XM_GLB_CFG_REG: XGMAC global configuration */1825#define FR_AB_XM_GLB_CFG 0x000012201826#define FRF_AB_XM_RMTFLT_GEN_LBN 171827#define FRF_AB_XM_RMTFLT_GEN_WIDTH 11828#define FRF_AB_XM_DEBUG_MODE_LBN 161829#define FRF_AB_XM_DEBUG_MODE_WIDTH 11830#define FRF_AB_XM_RX_STAT_EN_LBN 111831#define FRF_AB_XM_RX_STAT_EN_WIDTH 11832#define FRF_AB_XM_TX_STAT_EN_LBN 101833#define FRF_AB_XM_TX_STAT_EN_WIDTH 11834#define FRF_AB_XM_RX_JUMBO_MODE_LBN 61835#define FRF_AB_XM_RX_JUMBO_MODE_WIDTH 11836#define FRF_AB_XM_WAN_MODE_LBN 51837#define FRF_AB_XM_WAN_MODE_WIDTH 11838#define FRF_AB_XM_INTCLR_MODE_LBN 31839#define FRF_AB_XM_INTCLR_MODE_WIDTH 11840#define FRF_AB_XM_CORE_RST_LBN 01841#define FRF_AB_XM_CORE_RST_WIDTH 11842 1843/* XM_TX_CFG_REG: XGMAC transmit configuration */1844#define FR_AB_XM_TX_CFG 0x000012301845#define FRF_AB_XM_TX_PROG_LBN 241846#define FRF_AB_XM_TX_PROG_WIDTH 11847#define FRF_AB_XM_IPG_LBN 161848#define FRF_AB_XM_IPG_WIDTH 41849#define FRF_AB_XM_FCNTL_LBN 101850#define FRF_AB_XM_FCNTL_WIDTH 11851#define FRF_AB_XM_TXCRC_LBN 81852#define FRF_AB_XM_TXCRC_WIDTH 11853#define FRF_AB_XM_EDRC_LBN 61854#define FRF_AB_XM_EDRC_WIDTH 11855#define FRF_AB_XM_AUTO_PAD_LBN 51856#define FRF_AB_XM_AUTO_PAD_WIDTH 11857#define FRF_AB_XM_TX_PRMBL_LBN 21858#define FRF_AB_XM_TX_PRMBL_WIDTH 11859#define FRF_AB_XM_TXEN_LBN 11860#define FRF_AB_XM_TXEN_WIDTH 11861#define FRF_AB_XM_TX_RST_LBN 01862#define FRF_AB_XM_TX_RST_WIDTH 11863 1864/* XM_RX_CFG_REG: XGMAC receive configuration */1865#define FR_AB_XM_RX_CFG 0x000012401866#define FRF_AB_XM_PASS_LENERR_LBN 261867#define FRF_AB_XM_PASS_LENERR_WIDTH 11868#define FRF_AB_XM_PASS_CRC_ERR_LBN 251869#define FRF_AB_XM_PASS_CRC_ERR_WIDTH 11870#define FRF_AB_XM_PASS_PRMBLE_ERR_LBN 241871#define FRF_AB_XM_PASS_PRMBLE_ERR_WIDTH 11872#define FRF_AB_XM_REJ_BCAST_LBN 201873#define FRF_AB_XM_REJ_BCAST_WIDTH 11874#define FRF_AB_XM_ACPT_ALL_MCAST_LBN 111875#define FRF_AB_XM_ACPT_ALL_MCAST_WIDTH 11876#define FRF_AB_XM_ACPT_ALL_UCAST_LBN 91877#define FRF_AB_XM_ACPT_ALL_UCAST_WIDTH 11878#define FRF_AB_XM_AUTO_DEPAD_LBN 81879#define FRF_AB_XM_AUTO_DEPAD_WIDTH 11880#define FRF_AB_XM_RXCRC_LBN 31881#define FRF_AB_XM_RXCRC_WIDTH 11882#define FRF_AB_XM_RX_PRMBL_LBN 21883#define FRF_AB_XM_RX_PRMBL_WIDTH 11884#define FRF_AB_XM_RXEN_LBN 11885#define FRF_AB_XM_RXEN_WIDTH 11886#define FRF_AB_XM_RX_RST_LBN 01887#define FRF_AB_XM_RX_RST_WIDTH 11888 1889/* XM_MGT_INT_MASK: documentation to be written for sum_XM_MGT_INT_MASK */1890#define FR_AB_XM_MGT_INT_MASK 0x000012501891#define FRF_AB_XM_MSK_STA_INTR_LBN 161892#define FRF_AB_XM_MSK_STA_INTR_WIDTH 11893#define FRF_AB_XM_MSK_STAT_CNTR_HF_LBN 91894#define FRF_AB_XM_MSK_STAT_CNTR_HF_WIDTH 11895#define FRF_AB_XM_MSK_STAT_CNTR_OF_LBN 81896#define FRF_AB_XM_MSK_STAT_CNTR_OF_WIDTH 11897#define FRF_AB_XM_MSK_PRMBLE_ERR_LBN 21898#define FRF_AB_XM_MSK_PRMBLE_ERR_WIDTH 11899#define FRF_AB_XM_MSK_RMTFLT_LBN 11900#define FRF_AB_XM_MSK_RMTFLT_WIDTH 11901#define FRF_AB_XM_MSK_LCLFLT_LBN 01902#define FRF_AB_XM_MSK_LCLFLT_WIDTH 11903 1904/* XM_FC_REG: XGMAC flow control register */1905#define FR_AB_XM_FC 0x000012701906#define FRF_AB_XM_PAUSE_TIME_LBN 161907#define FRF_AB_XM_PAUSE_TIME_WIDTH 161908#define FRF_AB_XM_RX_MAC_STAT_LBN 111909#define FRF_AB_XM_RX_MAC_STAT_WIDTH 11910#define FRF_AB_XM_TX_MAC_STAT_LBN 101911#define FRF_AB_XM_TX_MAC_STAT_WIDTH 11912#define FRF_AB_XM_MCNTL_PASS_LBN 81913#define FRF_AB_XM_MCNTL_PASS_WIDTH 21914#define FRF_AB_XM_REJ_CNTL_UCAST_LBN 61915#define FRF_AB_XM_REJ_CNTL_UCAST_WIDTH 11916#define FRF_AB_XM_REJ_CNTL_MCAST_LBN 51917#define FRF_AB_XM_REJ_CNTL_MCAST_WIDTH 11918#define FRF_AB_XM_ZPAUSE_LBN 21919#define FRF_AB_XM_ZPAUSE_WIDTH 11920#define FRF_AB_XM_XMIT_PAUSE_LBN 11921#define FRF_AB_XM_XMIT_PAUSE_WIDTH 11922#define FRF_AB_XM_DIS_FCNTL_LBN 01923#define FRF_AB_XM_DIS_FCNTL_WIDTH 11924 1925/* XM_PAUSE_TIME_REG: XGMAC pause time register */1926#define FR_AB_XM_PAUSE_TIME 0x000012901927#define FRF_AB_XM_TX_PAUSE_CNT_LBN 161928#define FRF_AB_XM_TX_PAUSE_CNT_WIDTH 161929#define FRF_AB_XM_RX_PAUSE_CNT_LBN 01930#define FRF_AB_XM_RX_PAUSE_CNT_WIDTH 161931 1932/* XM_TX_PARAM_REG: XGMAC transmit parameter register */1933#define FR_AB_XM_TX_PARAM 0x000012d01934#define FRF_AB_XM_TX_JUMBO_MODE_LBN 311935#define FRF_AB_XM_TX_JUMBO_MODE_WIDTH 11936#define FRF_AB_XM_MAX_TX_FRM_SIZE_HI_LBN 191937#define FRF_AB_XM_MAX_TX_FRM_SIZE_HI_WIDTH 111938#define FRF_AB_XM_MAX_TX_FRM_SIZE_LO_LBN 161939#define FRF_AB_XM_MAX_TX_FRM_SIZE_LO_WIDTH 31940#define FRF_AB_XM_PAD_CHAR_LBN 01941#define FRF_AB_XM_PAD_CHAR_WIDTH 81942 1943/* XM_RX_PARAM_REG: XGMAC receive parameter register */1944#define FR_AB_XM_RX_PARAM 0x000012e01945#define FRF_AB_XM_MAX_RX_FRM_SIZE_HI_LBN 31946#define FRF_AB_XM_MAX_RX_FRM_SIZE_HI_WIDTH 111947#define FRF_AB_XM_MAX_RX_FRM_SIZE_LO_LBN 01948#define FRF_AB_XM_MAX_RX_FRM_SIZE_LO_WIDTH 31949 1950/* XM_MGT_INT_MSK_REG: XGMAC management interrupt mask register */1951#define FR_AB_XM_MGT_INT_MSK 0x000012f01952#define FRF_AB_XM_STAT_CNTR_OF_LBN 91953#define FRF_AB_XM_STAT_CNTR_OF_WIDTH 11954#define FRF_AB_XM_STAT_CNTR_HF_LBN 81955#define FRF_AB_XM_STAT_CNTR_HF_WIDTH 11956#define FRF_AB_XM_PRMBLE_ERR_LBN 21957#define FRF_AB_XM_PRMBLE_ERR_WIDTH 11958#define FRF_AB_XM_RMTFLT_LBN 11959#define FRF_AB_XM_RMTFLT_WIDTH 11960#define FRF_AB_XM_LCLFLT_LBN 01961#define FRF_AB_XM_LCLFLT_WIDTH 11962 1963/* XX_PWR_RST_REG: XGXS/XAUI powerdown/reset register */1964#define FR_AB_XX_PWR_RST 0x000013001965#define FRF_AB_XX_PWRDND_SIG_LBN 311966#define FRF_AB_XX_PWRDND_SIG_WIDTH 11967#define FRF_AB_XX_PWRDNC_SIG_LBN 301968#define FRF_AB_XX_PWRDNC_SIG_WIDTH 11969#define FRF_AB_XX_PWRDNB_SIG_LBN 291970#define FRF_AB_XX_PWRDNB_SIG_WIDTH 11971#define FRF_AB_XX_PWRDNA_SIG_LBN 281972#define FRF_AB_XX_PWRDNA_SIG_WIDTH 11973#define FRF_AB_XX_SIM_MODE_LBN 271974#define FRF_AB_XX_SIM_MODE_WIDTH 11975#define FRF_AB_XX_RSTPLLCD_SIG_LBN 251976#define FRF_AB_XX_RSTPLLCD_SIG_WIDTH 11977#define FRF_AB_XX_RSTPLLAB_SIG_LBN 241978#define FRF_AB_XX_RSTPLLAB_SIG_WIDTH 11979#define FRF_AB_XX_RESETD_SIG_LBN 231980#define FRF_AB_XX_RESETD_SIG_WIDTH 11981#define FRF_AB_XX_RESETC_SIG_LBN 221982#define FRF_AB_XX_RESETC_SIG_WIDTH 11983#define FRF_AB_XX_RESETB_SIG_LBN 211984#define FRF_AB_XX_RESETB_SIG_WIDTH 11985#define FRF_AB_XX_RESETA_SIG_LBN 201986#define FRF_AB_XX_RESETA_SIG_WIDTH 11987#define FRF_AB_XX_RSTXGXSRX_SIG_LBN 181988#define FRF_AB_XX_RSTXGXSRX_SIG_WIDTH 11989#define FRF_AB_XX_RSTXGXSTX_SIG_LBN 171990#define FRF_AB_XX_RSTXGXSTX_SIG_WIDTH 11991#define FRF_AB_XX_SD_RST_ACT_LBN 161992#define FRF_AB_XX_SD_RST_ACT_WIDTH 11993#define FRF_AB_XX_PWRDND_EN_LBN 151994#define FRF_AB_XX_PWRDND_EN_WIDTH 11995#define FRF_AB_XX_PWRDNC_EN_LBN 141996#define FRF_AB_XX_PWRDNC_EN_WIDTH 11997#define FRF_AB_XX_PWRDNB_EN_LBN 131998#define FRF_AB_XX_PWRDNB_EN_WIDTH 11999#define FRF_AB_XX_PWRDNA_EN_LBN 122000#define FRF_AB_XX_PWRDNA_EN_WIDTH 12001#define FRF_AB_XX_RSTPLLCD_EN_LBN 92002#define FRF_AB_XX_RSTPLLCD_EN_WIDTH 12003#define FRF_AB_XX_RSTPLLAB_EN_LBN 82004#define FRF_AB_XX_RSTPLLAB_EN_WIDTH 12005#define FRF_AB_XX_RESETD_EN_LBN 72006#define FRF_AB_XX_RESETD_EN_WIDTH 12007#define FRF_AB_XX_RESETC_EN_LBN 62008#define FRF_AB_XX_RESETC_EN_WIDTH 12009#define FRF_AB_XX_RESETB_EN_LBN 52010#define FRF_AB_XX_RESETB_EN_WIDTH 12011#define FRF_AB_XX_RESETA_EN_LBN 42012#define FRF_AB_XX_RESETA_EN_WIDTH 12013#define FRF_AB_XX_RSTXGXSRX_EN_LBN 22014#define FRF_AB_XX_RSTXGXSRX_EN_WIDTH 12015#define FRF_AB_XX_RSTXGXSTX_EN_LBN 12016#define FRF_AB_XX_RSTXGXSTX_EN_WIDTH 12017#define FRF_AB_XX_RST_XX_EN_LBN 02018#define FRF_AB_XX_RST_XX_EN_WIDTH 12019 2020/* XX_SD_CTL_REG: XGXS/XAUI powerdown/reset control register */2021#define FR_AB_XX_SD_CTL 0x000013102022#define FRF_AB_XX_TERMADJ1_LBN 172023#define FRF_AB_XX_TERMADJ1_WIDTH 12024#define FRF_AB_XX_TERMADJ0_LBN 162025#define FRF_AB_XX_TERMADJ0_WIDTH 12026#define FRF_AB_XX_HIDRVD_LBN 152027#define FRF_AB_XX_HIDRVD_WIDTH 12028#define FRF_AB_XX_LODRVD_LBN 142029#define FRF_AB_XX_LODRVD_WIDTH 12030#define FRF_AB_XX_HIDRVC_LBN 132031#define FRF_AB_XX_HIDRVC_WIDTH 12032#define FRF_AB_XX_LODRVC_LBN 122033#define FRF_AB_XX_LODRVC_WIDTH 12034#define FRF_AB_XX_HIDRVB_LBN 112035#define FRF_AB_XX_HIDRVB_WIDTH 12036#define FRF_AB_XX_LODRVB_LBN 102037#define FRF_AB_XX_LODRVB_WIDTH 12038#define FRF_AB_XX_HIDRVA_LBN 92039#define FRF_AB_XX_HIDRVA_WIDTH 12040#define FRF_AB_XX_LODRVA_LBN 82041#define FRF_AB_XX_LODRVA_WIDTH 12042#define FRF_AB_XX_LPBKD_LBN 32043#define FRF_AB_XX_LPBKD_WIDTH 12044#define FRF_AB_XX_LPBKC_LBN 22045#define FRF_AB_XX_LPBKC_WIDTH 12046#define FRF_AB_XX_LPBKB_LBN 12047#define FRF_AB_XX_LPBKB_WIDTH 12048#define FRF_AB_XX_LPBKA_LBN 02049#define FRF_AB_XX_LPBKA_WIDTH 12050 2051/* XX_TXDRV_CTL_REG: XAUI SerDes transmit drive control register */2052#define FR_AB_XX_TXDRV_CTL 0x000013202053#define FRF_AB_XX_DEQD_LBN 282054#define FRF_AB_XX_DEQD_WIDTH 42055#define FRF_AB_XX_DEQC_LBN 242056#define FRF_AB_XX_DEQC_WIDTH 42057#define FRF_AB_XX_DEQB_LBN 202058#define FRF_AB_XX_DEQB_WIDTH 42059#define FRF_AB_XX_DEQA_LBN 162060#define FRF_AB_XX_DEQA_WIDTH 42061#define FRF_AB_XX_DTXD_LBN 122062#define FRF_AB_XX_DTXD_WIDTH 42063#define FRF_AB_XX_DTXC_LBN 82064#define FRF_AB_XX_DTXC_WIDTH 42065#define FRF_AB_XX_DTXB_LBN 42066#define FRF_AB_XX_DTXB_WIDTH 42067#define FRF_AB_XX_DTXA_LBN 02068#define FRF_AB_XX_DTXA_WIDTH 42069 2070/* XX_PRBS_CTL_REG: documentation to be written for sum_XX_PRBS_CTL_REG */2071#define FR_AB_XX_PRBS_CTL 0x000013302072#define FRF_AB_XX_CH3_RX_PRBS_SEL_LBN 302073#define FRF_AB_XX_CH3_RX_PRBS_SEL_WIDTH 22074#define FRF_AB_XX_CH3_RX_PRBS_INV_LBN 292075#define FRF_AB_XX_CH3_RX_PRBS_INV_WIDTH 12076#define FRF_AB_XX_CH3_RX_PRBS_CHKEN_LBN 282077#define FRF_AB_XX_CH3_RX_PRBS_CHKEN_WIDTH 12078#define FRF_AB_XX_CH2_RX_PRBS_SEL_LBN 262079#define FRF_AB_XX_CH2_RX_PRBS_SEL_WIDTH 22080#define FRF_AB_XX_CH2_RX_PRBS_INV_LBN 252081#define FRF_AB_XX_CH2_RX_PRBS_INV_WIDTH 12082#define FRF_AB_XX_CH2_RX_PRBS_CHKEN_LBN 242083#define FRF_AB_XX_CH2_RX_PRBS_CHKEN_WIDTH 12084#define FRF_AB_XX_CH1_RX_PRBS_SEL_LBN 222085#define FRF_AB_XX_CH1_RX_PRBS_SEL_WIDTH 22086#define FRF_AB_XX_CH1_RX_PRBS_INV_LBN 212087#define FRF_AB_XX_CH1_RX_PRBS_INV_WIDTH 12088#define FRF_AB_XX_CH1_RX_PRBS_CHKEN_LBN 202089#define FRF_AB_XX_CH1_RX_PRBS_CHKEN_WIDTH 12090#define FRF_AB_XX_CH0_RX_PRBS_SEL_LBN 182091#define FRF_AB_XX_CH0_RX_PRBS_SEL_WIDTH 22092#define FRF_AB_XX_CH0_RX_PRBS_INV_LBN 172093#define FRF_AB_XX_CH0_RX_PRBS_INV_WIDTH 12094#define FRF_AB_XX_CH0_RX_PRBS_CHKEN_LBN 162095#define FRF_AB_XX_CH0_RX_PRBS_CHKEN_WIDTH 12096#define FRF_AB_XX_CH3_TX_PRBS_SEL_LBN 142097#define FRF_AB_XX_CH3_TX_PRBS_SEL_WIDTH 22098#define FRF_AB_XX_CH3_TX_PRBS_INV_LBN 132099#define FRF_AB_XX_CH3_TX_PRBS_INV_WIDTH 12100#define FRF_AB_XX_CH3_TX_PRBS_CHKEN_LBN 122101#define FRF_AB_XX_CH3_TX_PRBS_CHKEN_WIDTH 12102#define FRF_AB_XX_CH2_TX_PRBS_SEL_LBN 102103#define FRF_AB_XX_CH2_TX_PRBS_SEL_WIDTH 22104#define FRF_AB_XX_CH2_TX_PRBS_INV_LBN 92105#define FRF_AB_XX_CH2_TX_PRBS_INV_WIDTH 12106#define FRF_AB_XX_CH2_TX_PRBS_CHKEN_LBN 82107#define FRF_AB_XX_CH2_TX_PRBS_CHKEN_WIDTH 12108#define FRF_AB_XX_CH1_TX_PRBS_SEL_LBN 62109#define FRF_AB_XX_CH1_TX_PRBS_SEL_WIDTH 22110#define FRF_AB_XX_CH1_TX_PRBS_INV_LBN 52111#define FRF_AB_XX_CH1_TX_PRBS_INV_WIDTH 12112#define FRF_AB_XX_CH1_TX_PRBS_CHKEN_LBN 42113#define FRF_AB_XX_CH1_TX_PRBS_CHKEN_WIDTH 12114#define FRF_AB_XX_CH0_TX_PRBS_SEL_LBN 22115#define FRF_AB_XX_CH0_TX_PRBS_SEL_WIDTH 22116#define FRF_AB_XX_CH0_TX_PRBS_INV_LBN 12117#define FRF_AB_XX_CH0_TX_PRBS_INV_WIDTH 12118#define FRF_AB_XX_CH0_TX_PRBS_CHKEN_LBN 02119#define FRF_AB_XX_CH0_TX_PRBS_CHKEN_WIDTH 12120 2121/* XX_PRBS_CHK_REG: documentation to be written for sum_XX_PRBS_CHK_REG */2122#define FR_AB_XX_PRBS_CHK 0x000013402123#define FRF_AB_XX_REV_LB_EN_LBN 162124#define FRF_AB_XX_REV_LB_EN_WIDTH 12125#define FRF_AB_XX_CH3_DEG_DET_LBN 152126#define FRF_AB_XX_CH3_DEG_DET_WIDTH 12127#define FRF_AB_XX_CH3_LFSR_LOCK_IND_LBN 142128#define FRF_AB_XX_CH3_LFSR_LOCK_IND_WIDTH 12129#define FRF_AB_XX_CH3_PRBS_FRUN_LBN 132130#define FRF_AB_XX_CH3_PRBS_FRUN_WIDTH 12131#define FRF_AB_XX_CH3_ERR_CHK_LBN 122132#define FRF_AB_XX_CH3_ERR_CHK_WIDTH 12133#define FRF_AB_XX_CH2_DEG_DET_LBN 112134#define FRF_AB_XX_CH2_DEG_DET_WIDTH 12135#define FRF_AB_XX_CH2_LFSR_LOCK_IND_LBN 102136#define FRF_AB_XX_CH2_LFSR_LOCK_IND_WIDTH 12137#define FRF_AB_XX_CH2_PRBS_FRUN_LBN 92138#define FRF_AB_XX_CH2_PRBS_FRUN_WIDTH 12139#define FRF_AB_XX_CH2_ERR_CHK_LBN 82140#define FRF_AB_XX_CH2_ERR_CHK_WIDTH 12141#define FRF_AB_XX_CH1_DEG_DET_LBN 72142#define FRF_AB_XX_CH1_DEG_DET_WIDTH 12143#define FRF_AB_XX_CH1_LFSR_LOCK_IND_LBN 62144#define FRF_AB_XX_CH1_LFSR_LOCK_IND_WIDTH 12145#define FRF_AB_XX_CH1_PRBS_FRUN_LBN 52146#define FRF_AB_XX_CH1_PRBS_FRUN_WIDTH 12147#define FRF_AB_XX_CH1_ERR_CHK_LBN 42148#define FRF_AB_XX_CH1_ERR_CHK_WIDTH 12149#define FRF_AB_XX_CH0_DEG_DET_LBN 32150#define FRF_AB_XX_CH0_DEG_DET_WIDTH 12151#define FRF_AB_XX_CH0_LFSR_LOCK_IND_LBN 22152#define FRF_AB_XX_CH0_LFSR_LOCK_IND_WIDTH 12153#define FRF_AB_XX_CH0_PRBS_FRUN_LBN 12154#define FRF_AB_XX_CH0_PRBS_FRUN_WIDTH 12155#define FRF_AB_XX_CH0_ERR_CHK_LBN 02156#define FRF_AB_XX_CH0_ERR_CHK_WIDTH 12157 2158/* XX_PRBS_ERR_REG: documentation to be written for sum_XX_PRBS_ERR_REG */2159#define FR_AB_XX_PRBS_ERR 0x000013502160#define FRF_AB_XX_CH3_PRBS_ERR_CNT_LBN 242161#define FRF_AB_XX_CH3_PRBS_ERR_CNT_WIDTH 82162#define FRF_AB_XX_CH2_PRBS_ERR_CNT_LBN 162163#define FRF_AB_XX_CH2_PRBS_ERR_CNT_WIDTH 82164#define FRF_AB_XX_CH1_PRBS_ERR_CNT_LBN 82165#define FRF_AB_XX_CH1_PRBS_ERR_CNT_WIDTH 82166#define FRF_AB_XX_CH0_PRBS_ERR_CNT_LBN 02167#define FRF_AB_XX_CH0_PRBS_ERR_CNT_WIDTH 82168 2169/* XX_CORE_STAT_REG: XAUI XGXS core status register */2170#define FR_AB_XX_CORE_STAT 0x000013602171#define FRF_AB_XX_FORCE_SIG3_LBN 312172#define FRF_AB_XX_FORCE_SIG3_WIDTH 12173#define FRF_AB_XX_FORCE_SIG3_VAL_LBN 302174#define FRF_AB_XX_FORCE_SIG3_VAL_WIDTH 12175#define FRF_AB_XX_FORCE_SIG2_LBN 292176#define FRF_AB_XX_FORCE_SIG2_WIDTH 12177#define FRF_AB_XX_FORCE_SIG2_VAL_LBN 282178#define FRF_AB_XX_FORCE_SIG2_VAL_WIDTH 12179#define FRF_AB_XX_FORCE_SIG1_LBN 272180#define FRF_AB_XX_FORCE_SIG1_WIDTH 12181#define FRF_AB_XX_FORCE_SIG1_VAL_LBN 262182#define FRF_AB_XX_FORCE_SIG1_VAL_WIDTH 12183#define FRF_AB_XX_FORCE_SIG0_LBN 252184#define FRF_AB_XX_FORCE_SIG0_WIDTH 12185#define FRF_AB_XX_FORCE_SIG0_VAL_LBN 242186#define FRF_AB_XX_FORCE_SIG0_VAL_WIDTH 12187#define FRF_AB_XX_XGXS_LB_EN_LBN 232188#define FRF_AB_XX_XGXS_LB_EN_WIDTH 12189#define FRF_AB_XX_XGMII_LB_EN_LBN 222190#define FRF_AB_XX_XGMII_LB_EN_WIDTH 12191#define FRF_AB_XX_MATCH_FAULT_LBN 212192#define FRF_AB_XX_MATCH_FAULT_WIDTH 12193#define FRF_AB_XX_ALIGN_DONE_LBN 202194#define FRF_AB_XX_ALIGN_DONE_WIDTH 12195#define FRF_AB_XX_SYNC_STAT3_LBN 192196#define FRF_AB_XX_SYNC_STAT3_WIDTH 12197#define FRF_AB_XX_SYNC_STAT2_LBN 182198#define FRF_AB_XX_SYNC_STAT2_WIDTH 12199#define FRF_AB_XX_SYNC_STAT1_LBN 172200#define FRF_AB_XX_SYNC_STAT1_WIDTH 12201#define FRF_AB_XX_SYNC_STAT0_LBN 162202#define FRF_AB_XX_SYNC_STAT0_WIDTH 12203#define FRF_AB_XX_COMMA_DET_CH3_LBN 152204#define FRF_AB_XX_COMMA_DET_CH3_WIDTH 12205#define FRF_AB_XX_COMMA_DET_CH2_LBN 142206#define FRF_AB_XX_COMMA_DET_CH2_WIDTH 12207#define FRF_AB_XX_COMMA_DET_CH1_LBN 132208#define FRF_AB_XX_COMMA_DET_CH1_WIDTH 12209#define FRF_AB_XX_COMMA_DET_CH0_LBN 122210#define FRF_AB_XX_COMMA_DET_CH0_WIDTH 12211#define FRF_AB_XX_CGRP_ALIGN_CH3_LBN 112212#define FRF_AB_XX_CGRP_ALIGN_CH3_WIDTH 12213#define FRF_AB_XX_CGRP_ALIGN_CH2_LBN 102214#define FRF_AB_XX_CGRP_ALIGN_CH2_WIDTH 12215#define FRF_AB_XX_CGRP_ALIGN_CH1_LBN 92216#define FRF_AB_XX_CGRP_ALIGN_CH1_WIDTH 12217#define FRF_AB_XX_CGRP_ALIGN_CH0_LBN 82218#define FRF_AB_XX_CGRP_ALIGN_CH0_WIDTH 12219#define FRF_AB_XX_CHAR_ERR_CH3_LBN 72220#define FRF_AB_XX_CHAR_ERR_CH3_WIDTH 12221#define FRF_AB_XX_CHAR_ERR_CH2_LBN 62222#define FRF_AB_XX_CHAR_ERR_CH2_WIDTH 12223#define FRF_AB_XX_CHAR_ERR_CH1_LBN 52224#define FRF_AB_XX_CHAR_ERR_CH1_WIDTH 12225#define FRF_AB_XX_CHAR_ERR_CH0_LBN 42226#define FRF_AB_XX_CHAR_ERR_CH0_WIDTH 12227#define FRF_AB_XX_DISPERR_CH3_LBN 32228#define FRF_AB_XX_DISPERR_CH3_WIDTH 12229#define FRF_AB_XX_DISPERR_CH2_LBN 22230#define FRF_AB_XX_DISPERR_CH2_WIDTH 12231#define FRF_AB_XX_DISPERR_CH1_LBN 12232#define FRF_AB_XX_DISPERR_CH1_WIDTH 12233#define FRF_AB_XX_DISPERR_CH0_LBN 02234#define FRF_AB_XX_DISPERR_CH0_WIDTH 12235 2236/* RX_DESC_PTR_TBL_KER: Receive descriptor pointer table */2237#define FR_AA_RX_DESC_PTR_TBL_KER 0x000118002238#define FR_AA_RX_DESC_PTR_TBL_KER_STEP 162239#define FR_AA_RX_DESC_PTR_TBL_KER_ROWS 42240/* RX_DESC_PTR_TBL: Receive descriptor pointer table */2241#define FR_BZ_RX_DESC_PTR_TBL 0x00f400002242#define FR_BZ_RX_DESC_PTR_TBL_STEP 162243#define FR_BB_RX_DESC_PTR_TBL_ROWS 40962244#define FR_CZ_RX_DESC_PTR_TBL_ROWS 10242245#define FRF_CZ_RX_HDR_SPLIT_LBN 902246#define FRF_CZ_RX_HDR_SPLIT_WIDTH 12247#define FRF_AA_RX_RESET_LBN 892248#define FRF_AA_RX_RESET_WIDTH 12249#define FRF_AZ_RX_ISCSI_DDIG_EN_LBN 882250#define FRF_AZ_RX_ISCSI_DDIG_EN_WIDTH 12251#define FRF_AZ_RX_ISCSI_HDIG_EN_LBN 872252#define FRF_AZ_RX_ISCSI_HDIG_EN_WIDTH 12253#define FRF_AZ_RX_DESC_PREF_ACT_LBN 862254#define FRF_AZ_RX_DESC_PREF_ACT_WIDTH 12255#define FRF_AZ_RX_DC_HW_RPTR_LBN 802256#define FRF_AZ_RX_DC_HW_RPTR_WIDTH 62257#define FRF_AZ_RX_DESCQ_HW_RPTR_LBN 682258#define FRF_AZ_RX_DESCQ_HW_RPTR_WIDTH 122259#define FRF_AZ_RX_DESCQ_SW_WPTR_LBN 562260#define FRF_AZ_RX_DESCQ_SW_WPTR_WIDTH 122261#define FRF_AZ_RX_DESCQ_BUF_BASE_ID_LBN 362262#define FRF_AZ_RX_DESCQ_BUF_BASE_ID_WIDTH 202263#define FRF_AZ_RX_DESCQ_EVQ_ID_LBN 242264#define FRF_AZ_RX_DESCQ_EVQ_ID_WIDTH 122265#define FRF_AZ_RX_DESCQ_OWNER_ID_LBN 102266#define FRF_AZ_RX_DESCQ_OWNER_ID_WIDTH 142267#define FRF_AZ_RX_DESCQ_LABEL_LBN 52268#define FRF_AZ_RX_DESCQ_LABEL_WIDTH 52269#define FRF_AZ_RX_DESCQ_SIZE_LBN 32270#define FRF_AZ_RX_DESCQ_SIZE_WIDTH 22271#define FFE_AZ_RX_DESCQ_SIZE_4K 32272#define FFE_AZ_RX_DESCQ_SIZE_2K 22273#define FFE_AZ_RX_DESCQ_SIZE_1K 12274#define FFE_AZ_RX_DESCQ_SIZE_512 02275#define FRF_AZ_RX_DESCQ_TYPE_LBN 22276#define FRF_AZ_RX_DESCQ_TYPE_WIDTH 12277#define FRF_AZ_RX_DESCQ_JUMBO_LBN 12278#define FRF_AZ_RX_DESCQ_JUMBO_WIDTH 12279#define FRF_AZ_RX_DESCQ_EN_LBN 02280#define FRF_AZ_RX_DESCQ_EN_WIDTH 12281 2282/* TX_DESC_PTR_TBL_KER: Transmit descriptor pointer */2283#define FR_AA_TX_DESC_PTR_TBL_KER 0x000119002284#define FR_AA_TX_DESC_PTR_TBL_KER_STEP 162285#define FR_AA_TX_DESC_PTR_TBL_KER_ROWS 82286/* TX_DESC_PTR_TBL: Transmit descriptor pointer */2287#define FR_BZ_TX_DESC_PTR_TBL 0x00f500002288#define FR_BZ_TX_DESC_PTR_TBL_STEP 162289#define FR_BB_TX_DESC_PTR_TBL_ROWS 40962290#define FR_CZ_TX_DESC_PTR_TBL_ROWS 10242291#define FRF_CZ_TX_DPT_Q_MASK_WIDTH_LBN 942292#define FRF_CZ_TX_DPT_Q_MASK_WIDTH_WIDTH 22293#define FRF_CZ_TX_DPT_ETH_FILT_EN_LBN 932294#define FRF_CZ_TX_DPT_ETH_FILT_EN_WIDTH 12295#define FRF_CZ_TX_DPT_IP_FILT_EN_LBN 922296#define FRF_CZ_TX_DPT_IP_FILT_EN_WIDTH 12297#define FRF_BZ_TX_NON_IP_DROP_DIS_LBN 912298#define FRF_BZ_TX_NON_IP_DROP_DIS_WIDTH 12299#define FRF_BZ_TX_IP_CHKSM_DIS_LBN 902300#define FRF_BZ_TX_IP_CHKSM_DIS_WIDTH 12301#define FRF_BZ_TX_TCP_CHKSM_DIS_LBN 892302#define FRF_BZ_TX_TCP_CHKSM_DIS_WIDTH 12303#define FRF_AZ_TX_DESCQ_EN_LBN 882304#define FRF_AZ_TX_DESCQ_EN_WIDTH 12305#define FRF_AZ_TX_ISCSI_DDIG_EN_LBN 872306#define FRF_AZ_TX_ISCSI_DDIG_EN_WIDTH 12307#define FRF_AZ_TX_ISCSI_HDIG_EN_LBN 862308#define FRF_AZ_TX_ISCSI_HDIG_EN_WIDTH 12309#define FRF_AZ_TX_DC_HW_RPTR_LBN 802310#define FRF_AZ_TX_DC_HW_RPTR_WIDTH 62311#define FRF_AZ_TX_DESCQ_HW_RPTR_LBN 682312#define FRF_AZ_TX_DESCQ_HW_RPTR_WIDTH 122313#define FRF_AZ_TX_DESCQ_SW_WPTR_LBN 562314#define FRF_AZ_TX_DESCQ_SW_WPTR_WIDTH 122315#define FRF_AZ_TX_DESCQ_BUF_BASE_ID_LBN 362316#define FRF_AZ_TX_DESCQ_BUF_BASE_ID_WIDTH 202317#define FRF_AZ_TX_DESCQ_EVQ_ID_LBN 242318#define FRF_AZ_TX_DESCQ_EVQ_ID_WIDTH 122319#define FRF_AZ_TX_DESCQ_OWNER_ID_LBN 102320#define FRF_AZ_TX_DESCQ_OWNER_ID_WIDTH 142321#define FRF_AZ_TX_DESCQ_LABEL_LBN 52322#define FRF_AZ_TX_DESCQ_LABEL_WIDTH 52323#define FRF_AZ_TX_DESCQ_SIZE_LBN 32324#define FRF_AZ_TX_DESCQ_SIZE_WIDTH 22325#define FFE_AZ_TX_DESCQ_SIZE_4K 32326#define FFE_AZ_TX_DESCQ_SIZE_2K 22327#define FFE_AZ_TX_DESCQ_SIZE_1K 12328#define FFE_AZ_TX_DESCQ_SIZE_512 02329#define FRF_AZ_TX_DESCQ_TYPE_LBN 12330#define FRF_AZ_TX_DESCQ_TYPE_WIDTH 22331#define FRF_AZ_TX_DESCQ_FLUSH_LBN 02332#define FRF_AZ_TX_DESCQ_FLUSH_WIDTH 12333 2334/* EVQ_PTR_TBL_KER: Event queue pointer table */2335#define FR_AA_EVQ_PTR_TBL_KER 0x00011a002336#define FR_AA_EVQ_PTR_TBL_KER_STEP 162337#define FR_AA_EVQ_PTR_TBL_KER_ROWS 42338/* EVQ_PTR_TBL: Event queue pointer table */2339#define FR_BZ_EVQ_PTR_TBL 0x00f600002340#define FR_BZ_EVQ_PTR_TBL_STEP 162341#define FR_CZ_EVQ_PTR_TBL_ROWS 10242342#define FR_BB_EVQ_PTR_TBL_ROWS 40962343#define FRF_BZ_EVQ_RPTR_IGN_LBN 402344#define FRF_BZ_EVQ_RPTR_IGN_WIDTH 12345#define FRF_AB_EVQ_WKUP_OR_INT_EN_LBN 392346#define FRF_AB_EVQ_WKUP_OR_INT_EN_WIDTH 12347#define FRF_CZ_EVQ_DOS_PROTECT_EN_LBN 392348#define FRF_CZ_EVQ_DOS_PROTECT_EN_WIDTH 12349#define FRF_AZ_EVQ_NXT_WPTR_LBN 242350#define FRF_AZ_EVQ_NXT_WPTR_WIDTH 152351#define FRF_AZ_EVQ_EN_LBN 232352#define FRF_AZ_EVQ_EN_WIDTH 12353#define FRF_AZ_EVQ_SIZE_LBN 202354#define FRF_AZ_EVQ_SIZE_WIDTH 32355#define FFE_AZ_EVQ_SIZE_32K 62356#define FFE_AZ_EVQ_SIZE_16K 52357#define FFE_AZ_EVQ_SIZE_8K 42358#define FFE_AZ_EVQ_SIZE_4K 32359#define FFE_AZ_EVQ_SIZE_2K 22360#define FFE_AZ_EVQ_SIZE_1K 12361#define FFE_AZ_EVQ_SIZE_512 02362#define FRF_AZ_EVQ_BUF_BASE_ID_LBN 02363#define FRF_AZ_EVQ_BUF_BASE_ID_WIDTH 202364 2365/* BUF_HALF_TBL_KER: Buffer table in half buffer table mode direct access by driver */2366#define FR_AA_BUF_HALF_TBL_KER 0x000180002367#define FR_AA_BUF_HALF_TBL_KER_STEP 82368#define FR_AA_BUF_HALF_TBL_KER_ROWS 40962369/* BUF_HALF_TBL: Buffer table in half buffer table mode direct access by driver */2370#define FR_BZ_BUF_HALF_TBL 0x008000002371#define FR_BZ_BUF_HALF_TBL_STEP 82372#define FR_CZ_BUF_HALF_TBL_ROWS 1474562373#define FR_BB_BUF_HALF_TBL_ROWS 5242882374#define FRF_AZ_BUF_ADR_HBUF_ODD_LBN 442375#define FRF_AZ_BUF_ADR_HBUF_ODD_WIDTH 202376#define FRF_AZ_BUF_OWNER_ID_HBUF_ODD_LBN 322377#define FRF_AZ_BUF_OWNER_ID_HBUF_ODD_WIDTH 122378#define FRF_AZ_BUF_ADR_HBUF_EVEN_LBN 122379#define FRF_AZ_BUF_ADR_HBUF_EVEN_WIDTH 202380#define FRF_AZ_BUF_OWNER_ID_HBUF_EVEN_LBN 02381#define FRF_AZ_BUF_OWNER_ID_HBUF_EVEN_WIDTH 122382 2383/* BUF_FULL_TBL_KER: Buffer table in full buffer table mode direct access by driver */2384#define FR_AA_BUF_FULL_TBL_KER 0x000180002385#define FR_AA_BUF_FULL_TBL_KER_STEP 82386#define FR_AA_BUF_FULL_TBL_KER_ROWS 40962387/* BUF_FULL_TBL: Buffer table in full buffer table mode direct access by driver */2388#define FR_BZ_BUF_FULL_TBL 0x008000002389#define FR_BZ_BUF_FULL_TBL_STEP 82390#define FR_CZ_BUF_FULL_TBL_ROWS 1474562391#define FR_BB_BUF_FULL_TBL_ROWS 9175042392#define FRF_AZ_BUF_FULL_UNUSED_LBN 512393#define FRF_AZ_BUF_FULL_UNUSED_WIDTH 132394#define FRF_AZ_IP_DAT_BUF_SIZE_LBN 502395#define FRF_AZ_IP_DAT_BUF_SIZE_WIDTH 12396#define FRF_AZ_BUF_ADR_REGION_LBN 482397#define FRF_AZ_BUF_ADR_REGION_WIDTH 22398#define FFE_AZ_BUF_ADR_REGN3 32399#define FFE_AZ_BUF_ADR_REGN2 22400#define FFE_AZ_BUF_ADR_REGN1 12401#define FFE_AZ_BUF_ADR_REGN0 02402#define FRF_AZ_BUF_ADR_FBUF_LBN 142403#define FRF_AZ_BUF_ADR_FBUF_WIDTH 342404#define FRF_AZ_BUF_OWNER_ID_FBUF_LBN 02405#define FRF_AZ_BUF_OWNER_ID_FBUF_WIDTH 142406 2407/* RX_FILTER_TBL0: TCP/IPv4 Receive filter table */2408#define FR_BZ_RX_FILTER_TBL0 0x00f000002409#define FR_BZ_RX_FILTER_TBL0_STEP 322410#define FR_BZ_RX_FILTER_TBL0_ROWS 81922411/* RX_FILTER_TBL1: TCP/IPv4 Receive filter table */2412#define FR_BB_RX_FILTER_TBL1 0x00f000102413#define FR_BB_RX_FILTER_TBL1_STEP 322414#define FR_BB_RX_FILTER_TBL1_ROWS 81922415#define FRF_BZ_RSS_EN_LBN 1102416#define FRF_BZ_RSS_EN_WIDTH 12417#define FRF_BZ_SCATTER_EN_LBN 1092418#define FRF_BZ_SCATTER_EN_WIDTH 12419#define FRF_BZ_TCP_UDP_LBN 1082420#define FRF_BZ_TCP_UDP_WIDTH 12421#define FRF_BZ_RXQ_ID_LBN 962422#define FRF_BZ_RXQ_ID_WIDTH 122423#define FRF_BZ_DEST_IP_LBN 642424#define FRF_BZ_DEST_IP_WIDTH 322425#define FRF_BZ_DEST_PORT_TCP_LBN 482426#define FRF_BZ_DEST_PORT_TCP_WIDTH 162427#define FRF_BZ_SRC_IP_LBN 162428#define FRF_BZ_SRC_IP_WIDTH 322429#define FRF_BZ_SRC_TCP_DEST_UDP_LBN 02430#define FRF_BZ_SRC_TCP_DEST_UDP_WIDTH 162431 2432/* RX_MAC_FILTER_TBL0: Receive Ethernet filter table */2433#define FR_CZ_RX_MAC_FILTER_TBL0 0x00f000102434#define FR_CZ_RX_MAC_FILTER_TBL0_STEP 322435#define FR_CZ_RX_MAC_FILTER_TBL0_ROWS 5122436#define FRF_CZ_RMFT_RSS_EN_LBN 752437#define FRF_CZ_RMFT_RSS_EN_WIDTH 12438#define FRF_CZ_RMFT_SCATTER_EN_LBN 742439#define FRF_CZ_RMFT_SCATTER_EN_WIDTH 12440#define FRF_CZ_RMFT_IP_OVERRIDE_LBN 732441#define FRF_CZ_RMFT_IP_OVERRIDE_WIDTH 12442#define FRF_CZ_RMFT_RXQ_ID_LBN 612443#define FRF_CZ_RMFT_RXQ_ID_WIDTH 122444#define FRF_CZ_RMFT_WILDCARD_MATCH_LBN 602445#define FRF_CZ_RMFT_WILDCARD_MATCH_WIDTH 12446#define FRF_CZ_RMFT_DEST_MAC_LBN 122447#define FRF_CZ_RMFT_DEST_MAC_WIDTH 482448#define FRF_CZ_RMFT_VLAN_ID_LBN 02449#define FRF_CZ_RMFT_VLAN_ID_WIDTH 122450 2451/* TIMER_TBL: Timer table */2452#define FR_BZ_TIMER_TBL 0x00f700002453#define FR_BZ_TIMER_TBL_STEP 162454#define FR_CZ_TIMER_TBL_ROWS 10242455#define FR_BB_TIMER_TBL_ROWS 40962456#define FRF_CZ_TIMER_Q_EN_LBN 332457#define FRF_CZ_TIMER_Q_EN_WIDTH 12458#define FRF_CZ_INT_ARMD_LBN 322459#define FRF_CZ_INT_ARMD_WIDTH 12460#define FRF_CZ_INT_PEND_LBN 312461#define FRF_CZ_INT_PEND_WIDTH 12462#define FRF_CZ_HOST_NOTIFY_MODE_LBN 302463#define FRF_CZ_HOST_NOTIFY_MODE_WIDTH 12464#define FRF_CZ_RELOAD_TIMER_VAL_LBN 162465#define FRF_CZ_RELOAD_TIMER_VAL_WIDTH 142466#define FRF_CZ_TIMER_MODE_LBN 142467#define FRF_CZ_TIMER_MODE_WIDTH 22468#define FFE_CZ_TIMER_MODE_INT_HLDOFF 32469#define FFE_CZ_TIMER_MODE_TRIG_START 22470#define FFE_CZ_TIMER_MODE_IMMED_START 12471#define FFE_CZ_TIMER_MODE_DIS 02472#define FRF_BB_TIMER_MODE_LBN 122473#define FRF_BB_TIMER_MODE_WIDTH 22474#define FFE_BB_TIMER_MODE_INT_HLDOFF 22475#define FFE_BB_TIMER_MODE_TRIG_START 22476#define FFE_BB_TIMER_MODE_IMMED_START 12477#define FFE_BB_TIMER_MODE_DIS 02478#define FRF_CZ_TIMER_VAL_LBN 02479#define FRF_CZ_TIMER_VAL_WIDTH 142480#define FRF_BB_TIMER_VAL_LBN 02481#define FRF_BB_TIMER_VAL_WIDTH 122482 2483/* TX_PACE_TBL: Transmit pacing table */2484#define FR_BZ_TX_PACE_TBL 0x00f800002485#define FR_BZ_TX_PACE_TBL_STEP 162486#define FR_CZ_TX_PACE_TBL_ROWS 10242487#define FR_BB_TX_PACE_TBL_ROWS 40962488#define FRF_BZ_TX_PACE_LBN 02489#define FRF_BZ_TX_PACE_WIDTH 52490 2491/* RX_INDIRECTION_TBL: RX Indirection Table */2492#define FR_BZ_RX_INDIRECTION_TBL 0x00fb00002493#define FR_BZ_RX_INDIRECTION_TBL_STEP 162494#define FR_BZ_RX_INDIRECTION_TBL_ROWS 1282495#define FRF_BZ_IT_QUEUE_LBN 02496#define FRF_BZ_IT_QUEUE_WIDTH 62497 2498/* TX_FILTER_TBL0: TCP/IPv4 Transmit filter table */2499#define FR_CZ_TX_FILTER_TBL0 0x00fc00002500#define FR_CZ_TX_FILTER_TBL0_STEP 162501#define FR_CZ_TX_FILTER_TBL0_ROWS 81922502#define FRF_CZ_TIFT_TCP_UDP_LBN 1082503#define FRF_CZ_TIFT_TCP_UDP_WIDTH 12504#define FRF_CZ_TIFT_TXQ_ID_LBN 962505#define FRF_CZ_TIFT_TXQ_ID_WIDTH 122506#define FRF_CZ_TIFT_DEST_IP_LBN 642507#define FRF_CZ_TIFT_DEST_IP_WIDTH 322508#define FRF_CZ_TIFT_DEST_PORT_TCP_LBN 482509#define FRF_CZ_TIFT_DEST_PORT_TCP_WIDTH 162510#define FRF_CZ_TIFT_SRC_IP_LBN 162511#define FRF_CZ_TIFT_SRC_IP_WIDTH 322512#define FRF_CZ_TIFT_SRC_TCP_DEST_UDP_LBN 02513#define FRF_CZ_TIFT_SRC_TCP_DEST_UDP_WIDTH 162514 2515/* TX_MAC_FILTER_TBL0: Transmit Ethernet filter table */2516#define FR_CZ_TX_MAC_FILTER_TBL0 0x00fe00002517#define FR_CZ_TX_MAC_FILTER_TBL0_STEP 162518#define FR_CZ_TX_MAC_FILTER_TBL0_ROWS 5122519#define FRF_CZ_TMFT_TXQ_ID_LBN 612520#define FRF_CZ_TMFT_TXQ_ID_WIDTH 122521#define FRF_CZ_TMFT_WILDCARD_MATCH_LBN 602522#define FRF_CZ_TMFT_WILDCARD_MATCH_WIDTH 12523#define FRF_CZ_TMFT_SRC_MAC_LBN 122524#define FRF_CZ_TMFT_SRC_MAC_WIDTH 482525#define FRF_CZ_TMFT_VLAN_ID_LBN 02526#define FRF_CZ_TMFT_VLAN_ID_WIDTH 122527 2528/* MC_TREG_SMEM: MC Shared Memory */2529#define FR_CZ_MC_TREG_SMEM 0x00ff00002530#define FR_CZ_MC_TREG_SMEM_STEP 42531#define FR_CZ_MC_TREG_SMEM_ROWS 5122532#define FRF_CZ_MC_TREG_SMEM_ROW_LBN 02533#define FRF_CZ_MC_TREG_SMEM_ROW_WIDTH 322534 2535/* MSIX_VECTOR_TABLE: MSIX Vector Table */2536#define FR_BB_MSIX_VECTOR_TABLE 0x00ff00002537#define FR_BZ_MSIX_VECTOR_TABLE_STEP 162538#define FR_BB_MSIX_VECTOR_TABLE_ROWS 642539/* MSIX_VECTOR_TABLE: MSIX Vector Table */2540#define FR_CZ_MSIX_VECTOR_TABLE 0x000000002541/* FR_BZ_MSIX_VECTOR_TABLE_STEP 16 */2542#define FR_CZ_MSIX_VECTOR_TABLE_ROWS 10242543#define FRF_BZ_MSIX_VECTOR_RESERVED_LBN 972544#define FRF_BZ_MSIX_VECTOR_RESERVED_WIDTH 312545#define FRF_BZ_MSIX_VECTOR_MASK_LBN 962546#define FRF_BZ_MSIX_VECTOR_MASK_WIDTH 12547#define FRF_BZ_MSIX_MESSAGE_DATA_LBN 642548#define FRF_BZ_MSIX_MESSAGE_DATA_WIDTH 322549#define FRF_BZ_MSIX_MESSAGE_ADDRESS_HI_LBN 322550#define FRF_BZ_MSIX_MESSAGE_ADDRESS_HI_WIDTH 322551#define FRF_BZ_MSIX_MESSAGE_ADDRESS_LO_LBN 02552#define FRF_BZ_MSIX_MESSAGE_ADDRESS_LO_WIDTH 322553 2554/* MSIX_PBA_TABLE: MSIX Pending Bit Array */2555#define FR_BB_MSIX_PBA_TABLE 0x00ff20002556#define FR_BZ_MSIX_PBA_TABLE_STEP 42557#define FR_BB_MSIX_PBA_TABLE_ROWS 22558/* MSIX_PBA_TABLE: MSIX Pending Bit Array */2559#define FR_CZ_MSIX_PBA_TABLE 0x000080002560/* FR_BZ_MSIX_PBA_TABLE_STEP 4 */2561#define FR_CZ_MSIX_PBA_TABLE_ROWS 322562#define FRF_BZ_MSIX_PBA_PEND_DWORD_LBN 02563#define FRF_BZ_MSIX_PBA_PEND_DWORD_WIDTH 322564 2565/* SRM_DBG_REG: SRAM debug access */2566#define FR_BZ_SRM_DBG 0x030000002567#define FR_BZ_SRM_DBG_STEP 82568#define FR_CZ_SRM_DBG_ROWS 2621442569#define FR_BB_SRM_DBG_ROWS 20971522570#define FRF_BZ_SRM_DBG_LBN 02571#define FRF_BZ_SRM_DBG_WIDTH 642572 2573/* TB_MSIX_PBA_TABLE: MSIX Pending Bit Array */2574#define FR_CZ_TB_MSIX_PBA_TABLE 0x000080002575#define FR_CZ_TB_MSIX_PBA_TABLE_STEP 42576#define FR_CZ_TB_MSIX_PBA_TABLE_ROWS 10242577#define FRF_CZ_TB_MSIX_PBA_PEND_DWORD_LBN 02578#define FRF_CZ_TB_MSIX_PBA_PEND_DWORD_WIDTH 322579 2580/* DRIVER_EV */2581#define FSF_AZ_DRIVER_EV_SUBCODE_LBN 562582#define FSF_AZ_DRIVER_EV_SUBCODE_WIDTH 42583#define FSE_BZ_TX_DSC_ERROR_EV 152584#define FSE_BZ_RX_DSC_ERROR_EV 142585#define FSE_AA_RX_RECOVER_EV 112586#define FSE_AZ_TIMER_EV 102587#define FSE_AZ_TX_PKT_NON_TCP_UDP 92588#define FSE_AZ_WAKE_UP_EV 62589#define FSE_AZ_SRM_UPD_DONE_EV 52590#define FSE_AB_EVQ_NOT_EN_EV 32591#define FSE_AZ_EVQ_INIT_DONE_EV 22592#define FSE_AZ_RX_DESCQ_FLS_DONE_EV 12593#define FSE_AZ_TX_DESCQ_FLS_DONE_EV 02594#define FSF_AZ_DRIVER_EV_SUBDATA_LBN 02595#define FSF_AZ_DRIVER_EV_SUBDATA_WIDTH 142596 2597/* EVENT_ENTRY */2598#define FSF_AZ_EV_CODE_LBN 602599#define FSF_AZ_EV_CODE_WIDTH 42600#define FSE_CZ_EV_CODE_MCDI_EV 122601#define FSE_CZ_EV_CODE_USER_EV 82602#define FSE_AZ_EV_CODE_DRV_GEN_EV 72603#define FSE_AZ_EV_CODE_GLOBAL_EV 62604#define FSE_AZ_EV_CODE_DRIVER_EV 52605#define FSE_AZ_EV_CODE_TX_EV 22606#define FSE_AZ_EV_CODE_RX_EV 02607#define FSF_AZ_EV_DATA_LBN 02608#define FSF_AZ_EV_DATA_WIDTH 602609 2610/* GLOBAL_EV */2611#define FSF_BB_GLB_EV_RX_RECOVERY_LBN 122612#define FSF_BB_GLB_EV_RX_RECOVERY_WIDTH 12613#define FSF_AA_GLB_EV_RX_RECOVERY_LBN 112614#define FSF_AA_GLB_EV_RX_RECOVERY_WIDTH 12615#define FSF_BB_GLB_EV_XG_MGT_INTR_LBN 112616#define FSF_BB_GLB_EV_XG_MGT_INTR_WIDTH 12617#define FSF_AB_GLB_EV_XFP_PHY0_INTR_LBN 102618#define FSF_AB_GLB_EV_XFP_PHY0_INTR_WIDTH 12619#define FSF_AB_GLB_EV_XG_PHY0_INTR_LBN 92620#define FSF_AB_GLB_EV_XG_PHY0_INTR_WIDTH 12621#define FSF_AB_GLB_EV_G_PHY0_INTR_LBN 72622#define FSF_AB_GLB_EV_G_PHY0_INTR_WIDTH 12623 2624/* LEGACY_INT_VEC */2625#define FSF_AZ_NET_IVEC_FATAL_INT_LBN 642626#define FSF_AZ_NET_IVEC_FATAL_INT_WIDTH 12627#define FSF_AZ_NET_IVEC_INT_Q_LBN 402628#define FSF_AZ_NET_IVEC_INT_Q_WIDTH 42629#define FSF_AZ_NET_IVEC_INT_FLAG_LBN 322630#define FSF_AZ_NET_IVEC_INT_FLAG_WIDTH 12631#define FSF_AZ_NET_IVEC_EVQ_FIFO_HF_LBN 12632#define FSF_AZ_NET_IVEC_EVQ_FIFO_HF_WIDTH 12633#define FSF_AZ_NET_IVEC_EVQ_FIFO_AF_LBN 02634#define FSF_AZ_NET_IVEC_EVQ_FIFO_AF_WIDTH 12635 2636/* MC_XGMAC_FLTR_RULE_DEF */2637#define FSF_CZ_MC_XFRC_MODE_LBN 4162638#define FSF_CZ_MC_XFRC_MODE_WIDTH 12639#define FSE_CZ_MC_XFRC_MODE_LAYERED 12640#define FSE_CZ_MC_XFRC_MODE_SIMPLE 02641#define FSF_CZ_MC_XFRC_HASH_LBN 3842642#define FSF_CZ_MC_XFRC_HASH_WIDTH 322643#define FSF_CZ_MC_XFRC_LAYER4_BYTE_MASK_LBN 2562644#define FSF_CZ_MC_XFRC_LAYER4_BYTE_MASK_WIDTH 1282645#define FSF_CZ_MC_XFRC_LAYER3_BYTE_MASK_LBN 1282646#define FSF_CZ_MC_XFRC_LAYER3_BYTE_MASK_WIDTH 1282647#define FSF_CZ_MC_XFRC_LAYER2_OR_SIMPLE_BYTE_MASK_LBN 02648#define FSF_CZ_MC_XFRC_LAYER2_OR_SIMPLE_BYTE_MASK_WIDTH 1282649 2650/* RX_EV */2651#define FSF_CZ_RX_EV_PKT_NOT_PARSED_LBN 582652#define FSF_CZ_RX_EV_PKT_NOT_PARSED_WIDTH 12653#define FSF_CZ_RX_EV_IPV6_PKT_LBN 572654#define FSF_CZ_RX_EV_IPV6_PKT_WIDTH 12655#define FSF_AZ_RX_EV_PKT_OK_LBN 562656#define FSF_AZ_RX_EV_PKT_OK_WIDTH 12657#define FSF_AZ_RX_EV_PAUSE_FRM_ERR_LBN 552658#define FSF_AZ_RX_EV_PAUSE_FRM_ERR_WIDTH 12659#define FSF_AZ_RX_EV_BUF_OWNER_ID_ERR_LBN 542660#define FSF_AZ_RX_EV_BUF_OWNER_ID_ERR_WIDTH 12661#define FSF_AZ_RX_EV_IP_FRAG_ERR_LBN 532662#define FSF_AZ_RX_EV_IP_FRAG_ERR_WIDTH 12663#define FSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR_LBN 522664#define FSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR_WIDTH 12665#define FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR_LBN 512666#define FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR_WIDTH 12667#define FSF_AZ_RX_EV_ETH_CRC_ERR_LBN 502668#define FSF_AZ_RX_EV_ETH_CRC_ERR_WIDTH 12669#define FSF_AZ_RX_EV_FRM_TRUNC_LBN 492670#define FSF_AZ_RX_EV_FRM_TRUNC_WIDTH 12671#define FSF_AA_RX_EV_DRIB_NIB_LBN 492672#define FSF_AA_RX_EV_DRIB_NIB_WIDTH 12673#define FSF_AZ_RX_EV_TOBE_DISC_LBN 472674#define FSF_AZ_RX_EV_TOBE_DISC_WIDTH 12675#define FSF_AZ_RX_EV_PKT_TYPE_LBN 442676#define FSF_AZ_RX_EV_PKT_TYPE_WIDTH 32677#define FSE_AZ_RX_EV_PKT_TYPE_VLAN_JUMBO 52678#define FSE_AZ_RX_EV_PKT_TYPE_VLAN_LLC 42679#define FSE_AZ_RX_EV_PKT_TYPE_VLAN 32680#define FSE_AZ_RX_EV_PKT_TYPE_JUMBO 22681#define FSE_AZ_RX_EV_PKT_TYPE_LLC 12682#define FSE_AZ_RX_EV_PKT_TYPE_ETH 02683#define FSF_AZ_RX_EV_HDR_TYPE_LBN 422684#define FSF_AZ_RX_EV_HDR_TYPE_WIDTH 22685#define FSE_AZ_RX_EV_HDR_TYPE_OTHER 32686#define FSE_AB_RX_EV_HDR_TYPE_IPV4_OTHER 22687#define FSE_CZ_RX_EV_HDR_TYPE_IPV4V6_OTHER 22688#define FSE_AB_RX_EV_HDR_TYPE_IPV4_UDP 12689#define FSE_CZ_RX_EV_HDR_TYPE_IPV4V6_UDP 12690#define FSE_AB_RX_EV_HDR_TYPE_IPV4_TCP 02691#define FSE_CZ_RX_EV_HDR_TYPE_IPV4V6_TCP 02692#define FSF_AZ_RX_EV_DESC_Q_EMPTY_LBN 412693#define FSF_AZ_RX_EV_DESC_Q_EMPTY_WIDTH 12694#define FSF_AZ_RX_EV_MCAST_HASH_MATCH_LBN 402695#define FSF_AZ_RX_EV_MCAST_HASH_MATCH_WIDTH 12696#define FSF_AZ_RX_EV_MCAST_PKT_LBN 392697#define FSF_AZ_RX_EV_MCAST_PKT_WIDTH 12698#define FSF_AA_RX_EV_RECOVERY_FLAG_LBN 372699#define FSF_AA_RX_EV_RECOVERY_FLAG_WIDTH 12700#define FSF_AZ_RX_EV_Q_LABEL_LBN 322701#define FSF_AZ_RX_EV_Q_LABEL_WIDTH 52702#define FSF_AZ_RX_EV_JUMBO_CONT_LBN 312703#define FSF_AZ_RX_EV_JUMBO_CONT_WIDTH 12704#define FSF_AZ_RX_EV_PORT_LBN 302705#define FSF_AZ_RX_EV_PORT_WIDTH 12706#define FSF_AZ_RX_EV_BYTE_CNT_LBN 162707#define FSF_AZ_RX_EV_BYTE_CNT_WIDTH 142708#define FSF_AZ_RX_EV_SOP_LBN 152709#define FSF_AZ_RX_EV_SOP_WIDTH 12710#define FSF_AZ_RX_EV_ISCSI_PKT_OK_LBN 142711#define FSF_AZ_RX_EV_ISCSI_PKT_OK_WIDTH 12712#define FSF_AZ_RX_EV_ISCSI_DDIG_ERR_LBN 132713#define FSF_AZ_RX_EV_ISCSI_DDIG_ERR_WIDTH 12714#define FSF_AZ_RX_EV_ISCSI_HDIG_ERR_LBN 122715#define FSF_AZ_RX_EV_ISCSI_HDIG_ERR_WIDTH 12716#define FSF_AZ_RX_EV_DESC_PTR_LBN 02717#define FSF_AZ_RX_EV_DESC_PTR_WIDTH 122718 2719/* RX_KER_DESC */2720#define FSF_AZ_RX_KER_BUF_SIZE_LBN 482721#define FSF_AZ_RX_KER_BUF_SIZE_WIDTH 142722#define FSF_AZ_RX_KER_BUF_REGION_LBN 462723#define FSF_AZ_RX_KER_BUF_REGION_WIDTH 22724#define FSF_AZ_RX_KER_BUF_ADDR_LBN 02725#define FSF_AZ_RX_KER_BUF_ADDR_WIDTH 462726 2727/* RX_USER_DESC */2728#define FSF_AZ_RX_USER_2BYTE_OFFSET_LBN 202729#define FSF_AZ_RX_USER_2BYTE_OFFSET_WIDTH 122730#define FSF_AZ_RX_USER_BUF_ID_LBN 02731#define FSF_AZ_RX_USER_BUF_ID_WIDTH 202732 2733/* TX_EV */2734#define FSF_AZ_TX_EV_PKT_ERR_LBN 382735#define FSF_AZ_TX_EV_PKT_ERR_WIDTH 12736#define FSF_AZ_TX_EV_PKT_TOO_BIG_LBN 372737#define FSF_AZ_TX_EV_PKT_TOO_BIG_WIDTH 12738#define FSF_AZ_TX_EV_Q_LABEL_LBN 322739#define FSF_AZ_TX_EV_Q_LABEL_WIDTH 52740#define FSF_AZ_TX_EV_PORT_LBN 162741#define FSF_AZ_TX_EV_PORT_WIDTH 12742#define FSF_AZ_TX_EV_WQ_FF_FULL_LBN 152743#define FSF_AZ_TX_EV_WQ_FF_FULL_WIDTH 12744#define FSF_AZ_TX_EV_BUF_OWNER_ID_ERR_LBN 142745#define FSF_AZ_TX_EV_BUF_OWNER_ID_ERR_WIDTH 12746#define FSF_AZ_TX_EV_COMP_LBN 122747#define FSF_AZ_TX_EV_COMP_WIDTH 12748#define FSF_AZ_TX_EV_DESC_PTR_LBN 02749#define FSF_AZ_TX_EV_DESC_PTR_WIDTH 122750 2751/* TX_KER_DESC */2752#define FSF_AZ_TX_KER_CONT_LBN 622753#define FSF_AZ_TX_KER_CONT_WIDTH 12754#define FSF_AZ_TX_KER_BYTE_COUNT_LBN 482755#define FSF_AZ_TX_KER_BYTE_COUNT_WIDTH 142756#define FSF_AZ_TX_KER_BUF_REGION_LBN 462757#define FSF_AZ_TX_KER_BUF_REGION_WIDTH 22758#define FSF_AZ_TX_KER_BUF_ADDR_LBN 02759#define FSF_AZ_TX_KER_BUF_ADDR_WIDTH 462760 2761/* TX_USER_DESC */2762#define FSF_AZ_TX_USER_SW_EV_EN_LBN 482763#define FSF_AZ_TX_USER_SW_EV_EN_WIDTH 12764#define FSF_AZ_TX_USER_CONT_LBN 462765#define FSF_AZ_TX_USER_CONT_WIDTH 12766#define FSF_AZ_TX_USER_BYTE_CNT_LBN 332767#define FSF_AZ_TX_USER_BYTE_CNT_WIDTH 132768#define FSF_AZ_TX_USER_BUF_ID_LBN 132769#define FSF_AZ_TX_USER_BUF_ID_WIDTH 202770#define FSF_AZ_TX_USER_BYTE_OFS_LBN 02771#define FSF_AZ_TX_USER_BYTE_OFS_WIDTH 132772 2773/* USER_EV */2774#define FSF_CZ_USER_QID_LBN 322775#define FSF_CZ_USER_QID_WIDTH 102776#define FSF_CZ_USER_EV_REG_VALUE_LBN 02777#define FSF_CZ_USER_EV_REG_VALUE_WIDTH 322778 2779/**************************************************************************2780 *2781 * Falcon B0 PCIe core indirect registers2782 *2783 **************************************************************************2784 */2785 2786#define FPCR_BB_PCIE_DEVICE_CTRL_STAT 0x682787 2788#define FPCR_BB_PCIE_LINK_CTRL_STAT 0x702789 2790#define FPCR_BB_ACK_RPL_TIMER 0x7002791#define FPCRF_BB_ACK_TL_LBN 02792#define FPCRF_BB_ACK_TL_WIDTH 162793#define FPCRF_BB_RPL_TL_LBN 162794#define FPCRF_BB_RPL_TL_WIDTH 162795 2796#define FPCR_BB_ACK_FREQ 0x70C2797#define FPCRF_BB_ACK_FREQ_LBN 02798#define FPCRF_BB_ACK_FREQ_WIDTH 72799 2800/**************************************************************************2801 *2802 * Pseudo-registers and fields2803 *2804 **************************************************************************2805 */2806 2807/* Interrupt acknowledge work-around register (A0/A1 only) */2808#define FR_AA_WORK_AROUND_BROKEN_PCI_READS 0x00702809 2810/* EE_SPI_HCMD_REG: SPI host command register */2811/* Values for the EE_SPI_HCMD_SF_SEL register field */2812#define FFE_AB_SPI_DEVICE_EEPROM 02813#define FFE_AB_SPI_DEVICE_FLASH 12814 2815/* NIC_STAT_REG: NIC status register */2816#define FRF_AB_STRAP_10G_LBN 22817#define FRF_AB_STRAP_10G_WIDTH 12818#define FRF_AA_STRAP_PCIE_LBN 02819#define FRF_AA_STRAP_PCIE_WIDTH 12820 2821/* FATAL_INTR_REG_KER: Fatal interrupt register for Kernel */2822#define FRF_AZ_FATAL_INTR_LBN 02823#define FRF_AZ_FATAL_INTR_WIDTH 122824 2825/* SRM_CFG_REG: SRAM configuration register */2826/* We treat the number of SRAM banks and bank size as a single field */2827#define FRF_AZ_SRM_NB_SZ_LBN FRF_AZ_SRM_BANK_SIZE_LBN2828#define FRF_AZ_SRM_NB_SZ_WIDTH \2829 (FRF_AZ_SRM_BANK_SIZE_WIDTH + FRF_AZ_SRM_NUM_BANK_WIDTH)2830#define FFE_AB_SRM_NB1_SZ2M 02831#define FFE_AB_SRM_NB1_SZ4M 12832#define FFE_AB_SRM_NB1_SZ8M 22833#define FFE_AB_SRM_NB_SZ_DEF 32834#define FFE_AB_SRM_NB2_SZ4M 42835#define FFE_AB_SRM_NB2_SZ8M 52836#define FFE_AB_SRM_NB2_SZ16M 62837#define FFE_AB_SRM_NB_SZ_RES 72838 2839/* RX_DESC_UPD_REGP0: Receive descriptor update register. */2840/* We write just the last dword of these registers */2841#define FR_AZ_RX_DESC_UPD_DWORD_P0 \2842 (BUILD_BUG_ON_ZERO(FR_AA_RX_DESC_UPD_KER != FR_BZ_RX_DESC_UPD_P0) + \2843 FR_BZ_RX_DESC_UPD_P0 + 3 * 4)2844#define FRF_AZ_RX_DESC_WPTR_DWORD_LBN (FRF_AZ_RX_DESC_WPTR_LBN - 3 * 32)2845#define FRF_AZ_RX_DESC_WPTR_DWORD_WIDTH FRF_AZ_RX_DESC_WPTR_WIDTH2846 2847/* TX_DESC_UPD_REGP0: Transmit descriptor update register. */2848#define FR_AZ_TX_DESC_UPD_DWORD_P0 \2849 (BUILD_BUG_ON_ZERO(FR_AA_TX_DESC_UPD_KER != FR_BZ_TX_DESC_UPD_P0) + \2850 FR_BZ_TX_DESC_UPD_P0 + 3 * 4)2851#define FRF_AZ_TX_DESC_WPTR_DWORD_LBN (FRF_AZ_TX_DESC_WPTR_LBN - 3 * 32)2852#define FRF_AZ_TX_DESC_WPTR_DWORD_WIDTH FRF_AZ_TX_DESC_WPTR_WIDTH2853 2854/* GMF_CFG4_REG: GMAC FIFO configuration register 4 */2855#define FRF_AB_GMF_HSTFLTRFRM_PAUSE_LBN 122856#define FRF_AB_GMF_HSTFLTRFRM_PAUSE_WIDTH 12857 2858/* GMF_CFG5_REG: GMAC FIFO configuration register 5 */2859#define FRF_AB_GMF_HSTFLTRFRMDC_PAUSE_LBN 122860#define FRF_AB_GMF_HSTFLTRFRMDC_PAUSE_WIDTH 12861 2862/* XM_TX_PARAM_REG: XGMAC transmit parameter register */2863#define FRF_AB_XM_MAX_TX_FRM_SIZE_LBN FRF_AB_XM_MAX_TX_FRM_SIZE_LO_LBN2864#define FRF_AB_XM_MAX_TX_FRM_SIZE_WIDTH (FRF_AB_XM_MAX_TX_FRM_SIZE_HI_WIDTH + \2865 FRF_AB_XM_MAX_TX_FRM_SIZE_LO_WIDTH)2866 2867/* XM_RX_PARAM_REG: XGMAC receive parameter register */2868#define FRF_AB_XM_MAX_RX_FRM_SIZE_LBN FRF_AB_XM_MAX_RX_FRM_SIZE_LO_LBN2869#define FRF_AB_XM_MAX_RX_FRM_SIZE_WIDTH (FRF_AB_XM_MAX_RX_FRM_SIZE_HI_WIDTH + \2870 FRF_AB_XM_MAX_RX_FRM_SIZE_LO_WIDTH)2871 2872/* XX_TXDRV_CTL_REG: XAUI SerDes transmit drive control register */2873/* Default values */2874#define FFE_AB_XX_TXDRV_DEQ_DEF 0xe /* deq=.6 */2875#define FFE_AB_XX_TXDRV_DTX_DEF 0x5 /* 1.25 */2876#define FFE_AB_XX_SD_CTL_DRV_DEF 0 /* 20mA */2877 2878/* XX_CORE_STAT_REG: XAUI XGXS core status register */2879/* XGXS all-lanes status fields */2880#define FRF_AB_XX_SYNC_STAT_LBN FRF_AB_XX_SYNC_STAT0_LBN2881#define FRF_AB_XX_SYNC_STAT_WIDTH 42882#define FRF_AB_XX_COMMA_DET_LBN FRF_AB_XX_COMMA_DET_CH0_LBN2883#define FRF_AB_XX_COMMA_DET_WIDTH 42884#define FRF_AB_XX_CHAR_ERR_LBN FRF_AB_XX_CHAR_ERR_CH0_LBN2885#define FRF_AB_XX_CHAR_ERR_WIDTH 42886#define FRF_AB_XX_DISPERR_LBN FRF_AB_XX_DISPERR_CH0_LBN2887#define FRF_AB_XX_DISPERR_WIDTH 42888#define FFE_AB_XX_STAT_ALL_LANES 0xf2889#define FRF_AB_XX_FORCE_SIG_LBN FRF_AB_XX_FORCE_SIG0_VAL_LBN2890#define FRF_AB_XX_FORCE_SIG_WIDTH 82891#define FFE_AB_XX_FORCE_SIG_ALL_LANES 0xff2892 2893/* RX_MAC_FILTER_TBL0 */2894/* RMFT_DEST_MAC is wider than 32 bits */2895#define FRF_CZ_RMFT_DEST_MAC_LO_LBN FRF_CZ_RMFT_DEST_MAC_LBN2896#define FRF_CZ_RMFT_DEST_MAC_LO_WIDTH 322897#define FRF_CZ_RMFT_DEST_MAC_HI_LBN (FRF_CZ_RMFT_DEST_MAC_LBN + 32)2898#define FRF_CZ_RMFT_DEST_MAC_HI_WIDTH (FRF_CZ_RMFT_DEST_MAC_WIDTH - 32)2899 2900/* TX_MAC_FILTER_TBL0 */2901/* TMFT_SRC_MAC is wider than 32 bits */2902#define FRF_CZ_TMFT_SRC_MAC_LO_LBN FRF_CZ_TMFT_SRC_MAC_LBN2903#define FRF_CZ_TMFT_SRC_MAC_LO_WIDTH 322904#define FRF_CZ_TMFT_SRC_MAC_HI_LBN (FRF_CZ_TMFT_SRC_MAC_LBN + 32)2905#define FRF_CZ_TMFT_SRC_MAC_HI_WIDTH (FRF_CZ_TMFT_SRC_MAC_WIDTH - 32)2906 2907/* TX_PACE_TBL */2908/* Values >20 are documented as reserved, but will result in a queue going2909 * into the fast bin with a pace value of zero. */2910#define FFE_BZ_TX_PACE_OFF 02911#define FFE_BZ_TX_PACE_RESERVED 212912 2913/* DRIVER_EV */2914/* Sub-fields of an RX flush completion event */2915#define FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL_LBN 122916#define FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL_WIDTH 12917#define FSF_AZ_DRIVER_EV_RX_DESCQ_ID_LBN 02918#define FSF_AZ_DRIVER_EV_RX_DESCQ_ID_WIDTH 122919 2920/* EVENT_ENTRY */2921/* Magic number field for event test */2922#define FSF_AZ_DRV_GEN_EV_MAGIC_LBN 02923#define FSF_AZ_DRV_GEN_EV_MAGIC_WIDTH 322924 2925/* RX packet prefix */2926#define FS_BZ_RX_PREFIX_HASH_OFST 122927#define FS_BZ_RX_PREFIX_SIZE 162928 2929#endif /* EF4_FARCH_REGS_H */2930