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1/* SPDX-License-Identifier: GPL-2.0-only */2/****************************************************************************3 * Driver for Solarflare network controllers and boards4 * Copyright 2005-2006 Fen Systems Ltd.5 * Copyright 2005-2013 Solarflare Communications Inc.6 */7 8/* Common definitions for all Efx net driver code */9 10#ifndef EF4_NET_DRIVER_H11#define EF4_NET_DRIVER_H12 13#include <linux/netdevice.h>14#include <linux/etherdevice.h>15#include <linux/ethtool.h>16#include <linux/if_vlan.h>17#include <linux/timer.h>18#include <linux/mdio.h>19#include <linux/list.h>20#include <linux/pci.h>21#include <linux/device.h>22#include <linux/highmem.h>23#include <linux/workqueue.h>24#include <linux/mutex.h>25#include <linux/rwsem.h>26#include <linux/vmalloc.h>27#include <linux/i2c.h>28#include <linux/mtd/mtd.h>29#include <net/busy_poll.h>30 31#include "enum.h"32#include "bitfield.h"33#include "filter.h"34 35/**************************************************************************36 *37 * Build definitions38 *39 **************************************************************************/40 41#define EF4_DRIVER_VERSION "4.1"42 43#ifdef DEBUG44#define EF4_BUG_ON_PARANOID(x) BUG_ON(x)45#define EF4_WARN_ON_PARANOID(x) WARN_ON(x)46#else47#define EF4_BUG_ON_PARANOID(x) do {} while (0)48#define EF4_WARN_ON_PARANOID(x) do {} while (0)49#endif50 51/**************************************************************************52 *53 * Efx data structures54 *55 **************************************************************************/56 57#define EF4_MAX_CHANNELS 32U58#define EF4_MAX_RX_QUEUES EF4_MAX_CHANNELS59#define EF4_EXTRA_CHANNEL_IOV 060#define EF4_EXTRA_CHANNEL_PTP 161#define EF4_MAX_EXTRA_CHANNELS 2U62 63/* Checksum generation is a per-queue option in hardware, so each64 * queue visible to the networking core is backed by two hardware TX65 * queues. */66#define EF4_MAX_TX_TC 267#define EF4_MAX_CORE_TX_QUEUES (EF4_MAX_TX_TC * EF4_MAX_CHANNELS)68#define EF4_TXQ_TYPE_OFFLOAD 1 /* flag */69#define EF4_TXQ_TYPE_HIGHPRI 2 /* flag */70#define EF4_TXQ_TYPES 471#define EF4_MAX_TX_QUEUES (EF4_TXQ_TYPES * EF4_MAX_CHANNELS)72 73/* Maximum possible MTU the driver supports */74#define EF4_MAX_MTU (9 * 1024)75 76/* Minimum MTU, from RFC791 (IP) */77#define EF4_MIN_MTU 6878 79/* Size of an RX scatter buffer. Small enough to pack 2 into a 4K page,80 * and should be a multiple of the cache line size.81 */82#define EF4_RX_USR_BUF_SIZE (2048 - 256)83 84/* If possible, we should ensure cache line alignment at start and end85 * of every buffer. Otherwise, we just need to ensure 4-byte86 * alignment of the network header.87 */88#if NET_IP_ALIGN == 089#define EF4_RX_BUF_ALIGNMENT L1_CACHE_BYTES90#else91#define EF4_RX_BUF_ALIGNMENT 492#endif93 94struct ef4_self_tests;95 96/**97 * struct ef4_buffer - A general-purpose DMA buffer98 * @addr: host base address of the buffer99 * @dma_addr: DMA base address of the buffer100 * @len: Buffer length, in bytes101 *102 * The NIC uses these buffers for its interrupt status registers and103 * MAC stats dumps.104 */105struct ef4_buffer {106 void *addr;107 dma_addr_t dma_addr;108 unsigned int len;109};110 111/**112 * struct ef4_special_buffer - DMA buffer entered into buffer table113 * @buf: Standard &struct ef4_buffer114 * @index: Buffer index within controller;s buffer table115 * @entries: Number of buffer table entries116 *117 * The NIC has a buffer table that maps buffers of size %EF4_BUF_SIZE.118 * Event and descriptor rings are addressed via one or more buffer119 * table entries (and so can be physically non-contiguous, although we120 * currently do not take advantage of that). On Falcon and Siena we121 * have to take care of allocating and initialising the entries122 * ourselves. On later hardware this is managed by the firmware and123 * @index and @entries are left as 0.124 */125struct ef4_special_buffer {126 struct ef4_buffer buf;127 unsigned int index;128 unsigned int entries;129};130 131/**132 * struct ef4_tx_buffer - buffer state for a TX descriptor133 * @skb: When @flags & %EF4_TX_BUF_SKB, the associated socket buffer to be134 * freed when descriptor completes135 * @option: When @flags & %EF4_TX_BUF_OPTION, a NIC-specific option descriptor.136 * @dma_addr: DMA address of the fragment.137 * @flags: Flags for allocation and DMA mapping type138 * @len: Length of this fragment.139 * This field is zero when the queue slot is empty.140 * @unmap_len: Length of this fragment to unmap141 * @dma_offset: Offset of @dma_addr from the address of the backing DMA mapping.142 * Only valid if @unmap_len != 0.143 */144struct ef4_tx_buffer {145 const struct sk_buff *skb;146 union {147 ef4_qword_t option;148 dma_addr_t dma_addr;149 };150 unsigned short flags;151 unsigned short len;152 unsigned short unmap_len;153 unsigned short dma_offset;154};155#define EF4_TX_BUF_CONT 1 /* not last descriptor of packet */156#define EF4_TX_BUF_SKB 2 /* buffer is last part of skb */157#define EF4_TX_BUF_MAP_SINGLE 8 /* buffer was mapped with dma_map_single() */158#define EF4_TX_BUF_OPTION 0x10 /* empty buffer for option descriptor */159 160/**161 * struct ef4_tx_queue - An Efx TX queue162 *163 * This is a ring buffer of TX fragments.164 * Since the TX completion path always executes on the same165 * CPU and the xmit path can operate on different CPUs,166 * performance is increased by ensuring that the completion167 * path and the xmit path operate on different cache lines.168 * This is particularly important if the xmit path is always169 * executing on one CPU which is different from the completion170 * path. There is also a cache line for members which are171 * read but not written on the fast path.172 *173 * @efx: The associated Efx NIC174 * @queue: DMA queue number175 * @channel: The associated channel176 * @core_txq: The networking core TX queue structure177 * @buffer: The software buffer ring178 * @cb_page: Array of pages of copy buffers. Carved up according to179 * %EF4_TX_CB_ORDER into %EF4_TX_CB_SIZE-sized chunks.180 * @txd: The hardware descriptor ring181 * @ptr_mask: The size of the ring minus 1.182 * @initialised: Has hardware queue been initialised?183 * @tx_min_size: Minimum transmit size for this queue. Depends on HW.184 * @read_count: Current read pointer.185 * This is the number of buffers that have been removed from both rings.186 * @old_write_count: The value of @write_count when last checked.187 * This is here for performance reasons. The xmit path will188 * only get the up-to-date value of @write_count if this189 * variable indicates that the queue is empty. This is to190 * avoid cache-line ping-pong between the xmit path and the191 * completion path.192 * @merge_events: Number of TX merged completion events193 * @insert_count: Current insert pointer194 * This is the number of buffers that have been added to the195 * software ring.196 * @write_count: Current write pointer197 * This is the number of buffers that have been added to the198 * hardware ring.199 * @old_read_count: The value of read_count when last checked.200 * This is here for performance reasons. The xmit path will201 * only get the up-to-date value of read_count if this202 * variable indicates that the queue is full. This is to203 * avoid cache-line ping-pong between the xmit path and the204 * completion path.205 * @pushes: Number of times the TX push feature has been used206 * @xmit_more_available: Are any packets waiting to be pushed to the NIC207 * @cb_packets: Number of times the TX copybreak feature has been used208 * @empty_read_count: If the completion path has seen the queue as empty209 * and the transmission path has not yet checked this, the value of210 * @read_count bitwise-added to %EF4_EMPTY_COUNT_VALID; otherwise 0.211 */212struct ef4_tx_queue {213 /* Members which don't change on the fast path */214 struct ef4_nic *efx ____cacheline_aligned_in_smp;215 unsigned queue;216 struct ef4_channel *channel;217 struct netdev_queue *core_txq;218 struct ef4_tx_buffer *buffer;219 struct ef4_buffer *cb_page;220 struct ef4_special_buffer txd;221 unsigned int ptr_mask;222 bool initialised;223 unsigned int tx_min_size;224 225 /* Function pointers used in the fast path. */226 int (*handle_tso)(struct ef4_tx_queue*, struct sk_buff*, bool *);227 228 /* Members used mainly on the completion path */229 unsigned int read_count ____cacheline_aligned_in_smp;230 unsigned int old_write_count;231 unsigned int merge_events;232 unsigned int bytes_compl;233 unsigned int pkts_compl;234 235 /* Members used only on the xmit path */236 unsigned int insert_count ____cacheline_aligned_in_smp;237 unsigned int write_count;238 unsigned int old_read_count;239 unsigned int pushes;240 bool xmit_more_available;241 unsigned int cb_packets;242 /* Statistics to supplement MAC stats */243 unsigned long tx_packets;244 245 /* Members shared between paths and sometimes updated */246 unsigned int empty_read_count ____cacheline_aligned_in_smp;247#define EF4_EMPTY_COUNT_VALID 0x80000000248 atomic_t flush_outstanding;249};250 251#define EF4_TX_CB_ORDER 7252#define EF4_TX_CB_SIZE (1 << EF4_TX_CB_ORDER) - NET_IP_ALIGN253 254/**255 * struct ef4_rx_buffer - An Efx RX data buffer256 * @dma_addr: DMA base address of the buffer257 * @page: The associated page buffer.258 * Will be %NULL if the buffer slot is currently free.259 * @page_offset: If pending: offset in @page of DMA base address.260 * If completed: offset in @page of Ethernet header.261 * @len: If pending: length for DMA descriptor.262 * If completed: received length, excluding hash prefix.263 * @flags: Flags for buffer and packet state. These are only set on the264 * first buffer of a scattered packet.265 */266struct ef4_rx_buffer {267 dma_addr_t dma_addr;268 struct page *page;269 u16 page_offset;270 u16 len;271 u16 flags;272};273#define EF4_RX_BUF_LAST_IN_PAGE 0x0001274#define EF4_RX_PKT_CSUMMED 0x0002275#define EF4_RX_PKT_DISCARD 0x0004276#define EF4_RX_PKT_TCP 0x0040277#define EF4_RX_PKT_PREFIX_LEN 0x0080 /* length is in prefix only */278 279/**280 * struct ef4_rx_page_state - Page-based rx buffer state281 *282 * Inserted at the start of every page allocated for receive buffers.283 * Used to facilitate sharing dma mappings between recycled rx buffers284 * and those passed up to the kernel.285 *286 * @dma_addr: The dma address of this page.287 */288struct ef4_rx_page_state {289 dma_addr_t dma_addr;290 291 unsigned int __pad[] ____cacheline_aligned;292};293 294/**295 * struct ef4_rx_queue - An Efx RX queue296 * @efx: The associated Efx NIC297 * @core_index: Index of network core RX queue. Will be >= 0 iff this298 * is associated with a real RX queue.299 * @buffer: The software buffer ring300 * @rxd: The hardware descriptor ring301 * @ptr_mask: The size of the ring minus 1.302 * @refill_enabled: Enable refill whenever fill level is low303 * @flush_pending: Set when a RX flush is pending. Has the same lifetime as304 * @rxq_flush_pending.305 * @added_count: Number of buffers added to the receive queue.306 * @notified_count: Number of buffers given to NIC (<= @added_count).307 * @removed_count: Number of buffers removed from the receive queue.308 * @scatter_n: Used by NIC specific receive code.309 * @scatter_len: Used by NIC specific receive code.310 * @page_ring: The ring to store DMA mapped pages for reuse.311 * @page_add: Counter to calculate the write pointer for the recycle ring.312 * @page_remove: Counter to calculate the read pointer for the recycle ring.313 * @page_recycle_count: The number of pages that have been recycled.314 * @page_recycle_failed: The number of pages that couldn't be recycled because315 * the kernel still held a reference to them.316 * @page_recycle_full: The number of pages that were released because the317 * recycle ring was full.318 * @page_ptr_mask: The number of pages in the RX recycle ring minus 1.319 * @max_fill: RX descriptor maximum fill level (<= ring size)320 * @fast_fill_trigger: RX descriptor fill level that will trigger a fast fill321 * (<= @max_fill)322 * @min_fill: RX descriptor minimum non-zero fill level.323 * This records the minimum fill level observed when a ring324 * refill was triggered.325 * @recycle_count: RX buffer recycle counter.326 * @slow_fill: Timer used to defer ef4_nic_generate_fill_event().327 */328struct ef4_rx_queue {329 struct ef4_nic *efx;330 int core_index;331 struct ef4_rx_buffer *buffer;332 struct ef4_special_buffer rxd;333 unsigned int ptr_mask;334 bool refill_enabled;335 bool flush_pending;336 337 unsigned int added_count;338 unsigned int notified_count;339 unsigned int removed_count;340 unsigned int scatter_n;341 unsigned int scatter_len;342 struct page **page_ring;343 unsigned int page_add;344 unsigned int page_remove;345 unsigned int page_recycle_count;346 unsigned int page_recycle_failed;347 unsigned int page_recycle_full;348 unsigned int page_ptr_mask;349 unsigned int max_fill;350 unsigned int fast_fill_trigger;351 unsigned int min_fill;352 unsigned int min_overfill;353 unsigned int recycle_count;354 struct timer_list slow_fill;355 unsigned int slow_fill_count;356 /* Statistics to supplement MAC stats */357 unsigned long rx_packets;358};359 360/**361 * struct ef4_channel - An Efx channel362 *363 * A channel comprises an event queue, at least one TX queue, at least364 * one RX queue, and an associated tasklet for processing the event365 * queue.366 *367 * @efx: Associated Efx NIC368 * @channel: Channel instance number369 * @type: Channel type definition370 * @eventq_init: Event queue initialised flag371 * @enabled: Channel enabled indicator372 * @irq: IRQ number (MSI and MSI-X only)373 * @irq_moderation_us: IRQ moderation value (in microseconds)374 * @napi_dev: Net device used with NAPI375 * @napi_str: NAPI control structure376 * @state: state for NAPI vs busy polling377 * @state_lock: lock protecting @state378 * @eventq: Event queue buffer379 * @eventq_mask: Event queue pointer mask380 * @eventq_read_ptr: Event queue read pointer381 * @event_test_cpu: Last CPU to handle interrupt or test event for this channel382 * @irq_count: Number of IRQs since last adaptive moderation decision383 * @irq_mod_score: IRQ moderation score384 * @rps_flow_id: Flow IDs of filters allocated for accelerated RFS,385 * indexed by filter ID386 * @n_rx_tobe_disc: Count of RX_TOBE_DISC errors387 * @n_rx_ip_hdr_chksum_err: Count of RX IP header checksum errors388 * @n_rx_tcp_udp_chksum_err: Count of RX TCP and UDP checksum errors389 * @n_rx_mcast_mismatch: Count of unmatched multicast frames390 * @n_rx_frm_trunc: Count of RX_FRM_TRUNC errors391 * @n_rx_overlength: Count of RX_OVERLENGTH errors392 * @n_skbuff_leaks: Count of skbuffs leaked due to RX overrun393 * @n_rx_nodesc_trunc: Number of RX packets truncated and then dropped due to394 * lack of descriptors395 * @n_rx_merge_events: Number of RX merged completion events396 * @n_rx_merge_packets: Number of RX packets completed by merged events397 * @rx_pkt_n_frags: Number of fragments in next packet to be delivered by398 * __ef4_rx_packet(), or zero if there is none399 * @rx_pkt_index: Ring index of first buffer for next packet to be delivered400 * by __ef4_rx_packet(), if @rx_pkt_n_frags != 0401 * @rx_queue: RX queue for this channel402 * @tx_queue: TX queues for this channel403 */404struct ef4_channel {405 struct ef4_nic *efx;406 int channel;407 const struct ef4_channel_type *type;408 bool eventq_init;409 bool enabled;410 int irq;411 unsigned int irq_moderation_us;412 struct net_device *napi_dev;413 struct napi_struct napi_str;414#ifdef CONFIG_NET_RX_BUSY_POLL415 unsigned long busy_poll_state;416#endif417 struct ef4_special_buffer eventq;418 unsigned int eventq_mask;419 unsigned int eventq_read_ptr;420 int event_test_cpu;421 422 unsigned int irq_count;423 unsigned int irq_mod_score;424#ifdef CONFIG_RFS_ACCEL425 unsigned int rfs_filters_added;426#define RPS_FLOW_ID_INVALID 0xFFFFFFFF427 u32 *rps_flow_id;428#endif429 430 unsigned n_rx_tobe_disc;431 unsigned n_rx_ip_hdr_chksum_err;432 unsigned n_rx_tcp_udp_chksum_err;433 unsigned n_rx_mcast_mismatch;434 unsigned n_rx_frm_trunc;435 unsigned n_rx_overlength;436 unsigned n_skbuff_leaks;437 unsigned int n_rx_nodesc_trunc;438 unsigned int n_rx_merge_events;439 unsigned int n_rx_merge_packets;440 441 unsigned int rx_pkt_n_frags;442 unsigned int rx_pkt_index;443 444 struct ef4_rx_queue rx_queue;445 struct ef4_tx_queue tx_queue[EF4_TXQ_TYPES];446};447 448/**449 * struct ef4_msi_context - Context for each MSI450 * @efx: The associated NIC451 * @index: Index of the channel/IRQ452 * @name: Name of the channel/IRQ453 *454 * Unlike &struct ef4_channel, this is never reallocated and is always455 * safe for the IRQ handler to access.456 */457struct ef4_msi_context {458 struct ef4_nic *efx;459 unsigned int index;460 char name[IFNAMSIZ + 6];461};462 463/**464 * struct ef4_channel_type - distinguishes traffic and extra channels465 * @handle_no_channel: Handle failure to allocate an extra channel466 * @pre_probe: Set up extra state prior to initialisation467 * @post_remove: Tear down extra state after finalisation, if allocated.468 * May be called on channels that have not been probed.469 * @get_name: Generate the channel's name (used for its IRQ handler)470 * @copy: Copy the channel state prior to reallocation. May be %NULL if471 * reallocation is not supported.472 * @receive_skb: Handle an skb ready to be passed to netif_receive_skb()473 * @keep_eventq: Flag for whether event queue should be kept initialised474 * while the device is stopped475 */476struct ef4_channel_type {477 void (*handle_no_channel)(struct ef4_nic *);478 int (*pre_probe)(struct ef4_channel *);479 void (*post_remove)(struct ef4_channel *);480 void (*get_name)(struct ef4_channel *, char *buf, size_t len);481 struct ef4_channel *(*copy)(const struct ef4_channel *);482 bool (*receive_skb)(struct ef4_channel *, struct sk_buff *);483 bool keep_eventq;484};485 486enum ef4_led_mode {487 EF4_LED_OFF = 0,488 EF4_LED_ON = 1,489 EF4_LED_DEFAULT = 2490};491 492#define STRING_TABLE_LOOKUP(val, member) \493 ((val) < member ## _max) ? member ## _names[val] : "(invalid)"494 495extern const char *const ef4_loopback_mode_names[];496extern const unsigned int ef4_loopback_mode_max;497#define LOOPBACK_MODE(efx) \498 STRING_TABLE_LOOKUP((efx)->loopback_mode, ef4_loopback_mode)499 500extern const char *const ef4_reset_type_names[];501extern const unsigned int ef4_reset_type_max;502#define RESET_TYPE(type) \503 STRING_TABLE_LOOKUP(type, ef4_reset_type)504 505enum ef4_int_mode {506 /* Be careful if altering to correct macro below */507 EF4_INT_MODE_MSIX = 0,508 EF4_INT_MODE_MSI = 1,509 EF4_INT_MODE_LEGACY = 2,510 EF4_INT_MODE_MAX /* Insert any new items before this */511};512#define EF4_INT_MODE_USE_MSI(x) (((x)->interrupt_mode) <= EF4_INT_MODE_MSI)513 514enum nic_state {515 STATE_UNINIT = 0, /* device being probed/removed or is frozen */516 STATE_READY = 1, /* hardware ready and netdev registered */517 STATE_DISABLED = 2, /* device disabled due to hardware errors */518 STATE_RECOVERY = 3, /* device recovering from PCI error */519};520 521/* Forward declaration */522struct ef4_nic;523 524/* Pseudo bit-mask flow control field */525#define EF4_FC_RX FLOW_CTRL_RX526#define EF4_FC_TX FLOW_CTRL_TX527#define EF4_FC_AUTO 4528 529/**530 * struct ef4_link_state - Current state of the link531 * @up: Link is up532 * @fd: Link is full-duplex533 * @fc: Actual flow control flags534 * @speed: Link speed (Mbps)535 */536struct ef4_link_state {537 bool up;538 bool fd;539 u8 fc;540 unsigned int speed;541};542 543static inline bool ef4_link_state_equal(const struct ef4_link_state *left,544 const struct ef4_link_state *right)545{546 return left->up == right->up && left->fd == right->fd &&547 left->fc == right->fc && left->speed == right->speed;548}549 550/**551 * struct ef4_phy_operations - Efx PHY operations table552 * @probe: Probe PHY and initialise efx->mdio.mode_support, efx->mdio.mmds,553 * efx->loopback_modes.554 * @init: Initialise PHY555 * @fini: Shut down PHY556 * @reconfigure: Reconfigure PHY (e.g. for new link parameters)557 * @poll: Update @link_state and report whether it changed.558 * Serialised by the mac_lock.559 * @get_link_ksettings: Get ethtool settings. Serialised by the mac_lock.560 * @set_link_ksettings: Set ethtool settings. Serialised by the mac_lock.561 * @set_npage_adv: Set abilities advertised in (Extended) Next Page562 * (only needed where AN bit is set in mmds)563 * @test_alive: Test that PHY is 'alive' (online)564 * @test_name: Get the name of a PHY-specific test/result565 * @run_tests: Run tests and record results as appropriate (offline).566 * Flags are the ethtool tests flags.567 */568struct ef4_phy_operations {569 int (*probe) (struct ef4_nic *efx);570 int (*init) (struct ef4_nic *efx);571 void (*fini) (struct ef4_nic *efx);572 void (*remove) (struct ef4_nic *efx);573 int (*reconfigure) (struct ef4_nic *efx);574 bool (*poll) (struct ef4_nic *efx);575 void (*get_link_ksettings)(struct ef4_nic *efx,576 struct ethtool_link_ksettings *cmd);577 int (*set_link_ksettings)(struct ef4_nic *efx,578 const struct ethtool_link_ksettings *cmd);579 void (*set_npage_adv) (struct ef4_nic *efx, u32);580 int (*test_alive) (struct ef4_nic *efx);581 const char *(*test_name) (struct ef4_nic *efx, unsigned int index);582 int (*run_tests) (struct ef4_nic *efx, int *results, unsigned flags);583 int (*get_module_eeprom) (struct ef4_nic *efx,584 struct ethtool_eeprom *ee,585 u8 *data);586 int (*get_module_info) (struct ef4_nic *efx,587 struct ethtool_modinfo *modinfo);588};589 590/**591 * enum ef4_phy_mode - PHY operating mode flags592 * @PHY_MODE_NORMAL: on and should pass traffic593 * @PHY_MODE_TX_DISABLED: on with TX disabled594 * @PHY_MODE_LOW_POWER: set to low power through MDIO595 * @PHY_MODE_OFF: switched off through external control596 * @PHY_MODE_SPECIAL: on but will not pass traffic597 */598enum ef4_phy_mode {599 PHY_MODE_NORMAL = 0,600 PHY_MODE_TX_DISABLED = 1,601 PHY_MODE_LOW_POWER = 2,602 PHY_MODE_OFF = 4,603 PHY_MODE_SPECIAL = 8,604};605 606static inline bool ef4_phy_mode_disabled(enum ef4_phy_mode mode)607{608 return !!(mode & ~PHY_MODE_TX_DISABLED);609}610 611/**612 * struct ef4_hw_stat_desc - Description of a hardware statistic613 * @name: Name of the statistic as visible through ethtool, or %NULL if614 * it should not be exposed615 * @dma_width: Width in bits (0 for non-DMA statistics)616 * @offset: Offset within stats (ignored for non-DMA statistics)617 */618struct ef4_hw_stat_desc {619 const char *name;620 u16 dma_width;621 u16 offset;622};623 624/* Number of bits used in a multicast filter hash address */625#define EF4_MCAST_HASH_BITS 8626 627/* Number of (single-bit) entries in a multicast filter hash */628#define EF4_MCAST_HASH_ENTRIES (1 << EF4_MCAST_HASH_BITS)629 630/* An Efx multicast filter hash */631union ef4_multicast_hash {632 u8 byte[EF4_MCAST_HASH_ENTRIES / 8];633 ef4_oword_t oword[EF4_MCAST_HASH_ENTRIES / sizeof(ef4_oword_t) / 8];634};635 636/**637 * struct ef4_nic - an Efx NIC638 * @name: Device name (net device name or bus id before net device registered)639 * @pci_dev: The PCI device640 * @node: List node for maintaining primary/secondary function lists641 * @primary: &struct ef4_nic instance for the primary function of this642 * controller. May be the same structure, and may be %NULL if no643 * primary function is bound. Serialised by rtnl_lock.644 * @secondary_list: List of &struct ef4_nic instances for the secondary PCI645 * functions of the controller, if this is for the primary function.646 * Serialised by rtnl_lock.647 * @type: Controller type attributes648 * @legacy_irq: IRQ number649 * @workqueue: Workqueue for port reconfigures and the HW monitor.650 * Work items do not hold and must not acquire RTNL.651 * @workqueue_name: Name of workqueue652 * @reset_work: Scheduled reset workitem653 * @membase_phys: Memory BAR value as physical address654 * @membase: Memory BAR value655 * @interrupt_mode: Interrupt mode656 * @timer_quantum_ns: Interrupt timer quantum, in nanoseconds657 * @timer_max_ns: Interrupt timer maximum value, in nanoseconds658 * @irq_rx_adaptive: Adaptive IRQ moderation enabled for RX event queues659 * @irq_rx_mod_step_us: Step size for IRQ moderation for RX event queues660 * @irq_rx_moderation_us: IRQ moderation time for RX event queues661 * @msg_enable: Log message enable flags662 * @state: Device state number (%STATE_*). Serialised by the rtnl_lock.663 * @reset_pending: Bitmask for pending resets664 * @tx_queue: TX DMA queues665 * @rx_queue: RX DMA queues666 * @channel: Channels667 * @msi_context: Context for each MSI668 * @extra_channel_types: Types of extra (non-traffic) channels that669 * should be allocated for this NIC670 * @rxq_entries: Size of receive queues requested by user.671 * @txq_entries: Size of transmit queues requested by user.672 * @txq_stop_thresh: TX queue fill level at or above which we stop it.673 * @txq_wake_thresh: TX queue fill level at or below which we wake it.674 * @tx_dc_base: Base qword address in SRAM of TX queue descriptor caches675 * @rx_dc_base: Base qword address in SRAM of RX queue descriptor caches676 * @sram_lim_qw: Qword address limit of SRAM677 * @next_buffer_table: First available buffer table id678 * @n_channels: Number of channels in use679 * @n_rx_channels: Number of channels used for RX (= number of RX queues)680 * @n_tx_channels: Number of channels used for TX681 * @rx_ip_align: RX DMA address offset to have IP header aligned in682 * accordance with NET_IP_ALIGN683 * @rx_dma_len: Current maximum RX DMA length684 * @rx_buffer_order: Order (log2) of number of pages for each RX buffer685 * @rx_buffer_truesize: Amortised allocation size of an RX buffer,686 * for use in sk_buff::truesize687 * @rx_prefix_size: Size of RX prefix before packet data688 * @rx_packet_hash_offset: Offset of RX flow hash from start of packet data689 * (valid only if @rx_prefix_size != 0; always negative)690 * @rx_packet_len_offset: Offset of RX packet length from start of packet data691 * (valid only for NICs that set %EF4_RX_PKT_PREFIX_LEN; always negative)692 * @rx_packet_ts_offset: Offset of timestamp from start of packet data693 * (valid only if channel->sync_timestamps_enabled; always negative)694 * @rx_hash_key: Toeplitz hash key for RSS695 * @rx_indir_table: Indirection table for RSS696 * @rx_scatter: Scatter mode enabled for receives697 * @int_error_count: Number of internal errors seen recently698 * @int_error_expire: Time at which error count will be expired699 * @irq_soft_enabled: Are IRQs soft-enabled? If not, IRQ handler will700 * acknowledge but do nothing else.701 * @irq_status: Interrupt status buffer702 * @irq_zero_count: Number of legacy IRQs seen with queue flags == 0703 * @irq_level: IRQ level/index for IRQs not triggered by an event queue704 * @selftest_work: Work item for asynchronous self-test705 * @mtd_list: List of MTDs attached to the NIC706 * @nic_data: Hardware dependent state707 * @mac_lock: MAC access lock. Protects @port_enabled, @phy_mode,708 * ef4_monitor() and ef4_reconfigure_port()709 * @port_enabled: Port enabled indicator.710 * Serialises ef4_stop_all(), ef4_start_all(), ef4_monitor() and711 * ef4_mac_work() with kernel interfaces. Safe to read under any712 * one of the rtnl_lock, mac_lock, or netif_tx_lock, but all three must713 * be held to modify it.714 * @port_initialized: Port initialized?715 * @net_dev: Operating system network device. Consider holding the rtnl lock716 * @fixed_features: Features which cannot be turned off717 * @stats_buffer: DMA buffer for statistics718 * @phy_type: PHY type719 * @phy_op: PHY interface720 * @phy_data: PHY private data (including PHY-specific stats)721 * @mdio: PHY MDIO interface722 * @phy_mode: PHY operating mode. Serialised by @mac_lock.723 * @link_advertising: Autonegotiation advertising flags724 * @link_state: Current state of the link725 * @n_link_state_changes: Number of times the link has changed state726 * @unicast_filter: Flag for Falcon-arch simple unicast filter.727 * Protected by @mac_lock.728 * @multicast_hash: Multicast hash table for Falcon-arch.729 * Protected by @mac_lock.730 * @wanted_fc: Wanted flow control flags731 * @fc_disable: When non-zero flow control is disabled. Typically used to732 * ensure that network back pressure doesn't delay dma queue flushes.733 * Serialised by the rtnl lock.734 * @mac_work: Work item for changing MAC promiscuity and multicast hash735 * @loopback_mode: Loopback status736 * @loopback_modes: Supported loopback mode bitmask737 * @loopback_selftest: Offline self-test private state738 * @filter_sem: Filter table rw_semaphore, for freeing the table739 * @filter_lock: Filter table lock, for mere content changes740 * @filter_state: Architecture-dependent filter table state741 * @rps_expire_channel: Next channel to check for expiry742 * @rps_expire_index: Next index to check for expiry in743 * @rps_expire_channel's @rps_flow_id744 * @active_queues: Count of RX and TX queues that haven't been flushed and drained.745 * @rxq_flush_pending: Count of number of receive queues that need to be flushed.746 * Decremented when the ef4_flush_rx_queue() is called.747 * @rxq_flush_outstanding: Count of number of RX flushes started but not yet748 * completed (either success or failure). Not used when MCDI is used to749 * flush receive queues.750 * @flush_wq: wait queue used by ef4_nic_flush_queues() to wait for flush completions.751 * @vpd_sn: Serial number read from VPD752 * @monitor_work: Hardware monitor workitem753 * @biu_lock: BIU (bus interface unit) lock754 * @last_irq_cpu: Last CPU to handle a possible test interrupt. This755 * field is used by ef4_test_interrupts() to verify that an756 * interrupt has occurred.757 * @stats_lock: Statistics update lock. Must be held when calling758 * ef4_nic_type::{update,start,stop}_stats.759 * @n_rx_noskb_drops: Count of RX packets dropped due to failure to allocate an skb760 *761 * This is stored in the private area of the &struct net_device.762 */763struct ef4_nic {764 /* The following fields should be written very rarely */765 766 char name[IFNAMSIZ];767 struct list_head node;768 struct ef4_nic *primary;769 struct list_head secondary_list;770 struct pci_dev *pci_dev;771 unsigned int port_num;772 const struct ef4_nic_type *type;773 int legacy_irq;774 bool eeh_disabled_legacy_irq;775 struct workqueue_struct *workqueue;776 char workqueue_name[16];777 struct work_struct reset_work;778 resource_size_t membase_phys;779 void __iomem *membase;780 781 enum ef4_int_mode interrupt_mode;782 unsigned int timer_quantum_ns;783 unsigned int timer_max_ns;784 bool irq_rx_adaptive;785 unsigned int irq_mod_step_us;786 unsigned int irq_rx_moderation_us;787 u32 msg_enable;788 789 enum nic_state state;790 unsigned long reset_pending;791 792 struct ef4_channel *channel[EF4_MAX_CHANNELS];793 struct ef4_msi_context msi_context[EF4_MAX_CHANNELS];794 const struct ef4_channel_type *795 extra_channel_type[EF4_MAX_EXTRA_CHANNELS];796 797 unsigned rxq_entries;798 unsigned txq_entries;799 unsigned int txq_stop_thresh;800 unsigned int txq_wake_thresh;801 802 unsigned tx_dc_base;803 unsigned rx_dc_base;804 unsigned sram_lim_qw;805 unsigned next_buffer_table;806 807 unsigned int max_channels;808 unsigned int max_tx_channels;809 unsigned n_channels;810 unsigned n_rx_channels;811 unsigned rss_spread;812 unsigned tx_channel_offset;813 unsigned n_tx_channels;814 unsigned int rx_ip_align;815 unsigned int rx_dma_len;816 unsigned int rx_buffer_order;817 unsigned int rx_buffer_truesize;818 unsigned int rx_page_buf_step;819 unsigned int rx_bufs_per_page;820 unsigned int rx_pages_per_batch;821 unsigned int rx_prefix_size;822 int rx_packet_hash_offset;823 int rx_packet_len_offset;824 int rx_packet_ts_offset;825 u8 rx_hash_key[40];826 u32 rx_indir_table[128];827 bool rx_scatter;828 829 unsigned int_error_count;830 unsigned long int_error_expire;831 832 bool irq_soft_enabled;833 struct ef4_buffer irq_status;834 unsigned irq_zero_count;835 unsigned irq_level;836 struct delayed_work selftest_work;837 838#ifdef CONFIG_SFC_FALCON_MTD839 struct list_head mtd_list;840#endif841 842 void *nic_data;843 844 struct mutex mac_lock;845 struct work_struct mac_work;846 bool port_enabled;847 848 bool mc_bist_for_other_fn;849 bool port_initialized;850 struct net_device *net_dev;851 852 netdev_features_t fixed_features;853 854 struct ef4_buffer stats_buffer;855 u64 rx_nodesc_drops_total;856 u64 rx_nodesc_drops_while_down;857 bool rx_nodesc_drops_prev_state;858 859 unsigned int phy_type;860 const struct ef4_phy_operations *phy_op;861 void *phy_data;862 struct mdio_if_info mdio;863 enum ef4_phy_mode phy_mode;864 865 u32 link_advertising;866 struct ef4_link_state link_state;867 unsigned int n_link_state_changes;868 869 bool unicast_filter;870 union ef4_multicast_hash multicast_hash;871 u8 wanted_fc;872 unsigned fc_disable;873 874 atomic_t rx_reset;875 enum ef4_loopback_mode loopback_mode;876 u64 loopback_modes;877 878 void *loopback_selftest;879 880 struct rw_semaphore filter_sem;881 spinlock_t filter_lock;882 void *filter_state;883#ifdef CONFIG_RFS_ACCEL884 unsigned int rps_expire_channel;885 unsigned int rps_expire_index;886#endif887 888 atomic_t active_queues;889 atomic_t rxq_flush_pending;890 atomic_t rxq_flush_outstanding;891 wait_queue_head_t flush_wq;892 893 char *vpd_sn;894 895 /* The following fields may be written more often */896 897 struct delayed_work monitor_work ____cacheline_aligned_in_smp;898 spinlock_t biu_lock;899 int last_irq_cpu;900 spinlock_t stats_lock;901 atomic_t n_rx_noskb_drops;902};903 904static inline int ef4_dev_registered(struct ef4_nic *efx)905{906 return efx->net_dev->reg_state == NETREG_REGISTERED;907}908 909static inline unsigned int ef4_port_num(struct ef4_nic *efx)910{911 return efx->port_num;912}913 914struct ef4_mtd_partition {915 struct list_head node;916 struct mtd_info mtd;917 const char *dev_type_name;918 const char *type_name;919 char name[IFNAMSIZ + 20];920};921 922/**923 * struct ef4_nic_type - Efx device type definition924 * @mem_bar: Get the memory BAR925 * @mem_map_size: Get memory BAR mapped size926 * @probe: Probe the controller927 * @remove: Free resources allocated by probe()928 * @init: Initialise the controller929 * @dimension_resources: Dimension controller resources (buffer table,930 * and VIs once the available interrupt resources are clear)931 * @fini: Shut down the controller932 * @monitor: Periodic function for polling link state and hardware monitor933 * @map_reset_reason: Map ethtool reset reason to a reset method934 * @map_reset_flags: Map ethtool reset flags to a reset method, if possible935 * @reset: Reset the controller hardware and possibly the PHY. This will936 * be called while the controller is uninitialised.937 * @probe_port: Probe the MAC and PHY938 * @remove_port: Free resources allocated by probe_port()939 * @handle_global_event: Handle a "global" event (may be %NULL)940 * @fini_dmaq: Flush and finalise DMA queues (RX and TX queues)941 * @prepare_flush: Prepare the hardware for flushing the DMA queues942 * (for Falcon architecture)943 * @finish_flush: Clean up after flushing the DMA queues (for Falcon944 * architecture)945 * @prepare_flr: Prepare for an FLR946 * @finish_flr: Clean up after an FLR947 * @describe_stats: Describe statistics for ethtool948 * @update_stats: Update statistics not provided by event handling.949 * Either argument may be %NULL.950 * @start_stats: Start the regular fetching of statistics951 * @pull_stats: Pull stats from the NIC and wait until they arrive.952 * @stop_stats: Stop the regular fetching of statistics953 * @set_id_led: Set state of identifying LED or revert to automatic function954 * @push_irq_moderation: Apply interrupt moderation value955 * @reconfigure_port: Push loopback/power/txdis changes to the MAC and PHY956 * @prepare_enable_fc_tx: Prepare MAC to enable pause frame TX (may be %NULL)957 * @reconfigure_mac: Push MAC address, MTU, flow control and filter settings958 * to the hardware. Serialised by the mac_lock.959 * @check_mac_fault: Check MAC fault state. True if fault present.960 * @get_wol: Get WoL configuration from driver state961 * @set_wol: Push WoL configuration to the NIC962 * @resume_wol: Synchronise WoL state between driver and MC (e.g. after resume)963 * @test_chip: Test registers. May use ef4_farch_test_registers(), and is964 * expected to reset the NIC.965 * @test_nvram: Test validity of NVRAM contents966 * @irq_enable_master: Enable IRQs on the NIC. Each event queue must967 * be separately enabled after this.968 * @irq_test_generate: Generate a test IRQ969 * @irq_disable_non_ev: Disable non-event IRQs on the NIC. Each event970 * queue must be separately disabled before this.971 * @irq_handle_msi: Handle MSI for a channel. The @dev_id argument is972 * a pointer to the &struct ef4_msi_context for the channel.973 * @irq_handle_legacy: Handle legacy interrupt. The @dev_id argument974 * is a pointer to the &struct ef4_nic.975 * @tx_probe: Allocate resources for TX queue976 * @tx_init: Initialise TX queue on the NIC977 * @tx_remove: Free resources for TX queue978 * @tx_write: Write TX descriptors and doorbell979 * @rx_push_rss_config: Write RSS hash key and indirection table to the NIC980 * @rx_probe: Allocate resources for RX queue981 * @rx_init: Initialise RX queue on the NIC982 * @rx_remove: Free resources for RX queue983 * @rx_write: Write RX descriptors and doorbell984 * @rx_defer_refill: Generate a refill reminder event985 * @ev_probe: Allocate resources for event queue986 * @ev_init: Initialise event queue on the NIC987 * @ev_fini: Deinitialise event queue on the NIC988 * @ev_remove: Free resources for event queue989 * @ev_process: Process events for a queue, up to the given NAPI quota990 * @ev_read_ack: Acknowledge read events on a queue, rearming its IRQ991 * @ev_test_generate: Generate a test event992 * @filter_table_probe: Probe filter capabilities and set up filter software state993 * @filter_table_restore: Restore filters removed from hardware994 * @filter_table_remove: Remove filters from hardware and tear down software state995 * @filter_update_rx_scatter: Update filters after change to rx scatter setting996 * @filter_insert: add or replace a filter997 * @filter_remove_safe: remove a filter by ID, carefully998 * @filter_get_safe: retrieve a filter by ID, carefully999 * @filter_clear_rx: Remove all RX filters whose priority is less than or1000 * equal to the given priority and is not %EF4_FILTER_PRI_AUTO1001 * @filter_count_rx_used: Get the number of filters in use at a given priority1002 * @filter_get_rx_id_limit: Get maximum value of a filter id, plus 11003 * @filter_get_rx_ids: Get list of RX filters at a given priority1004 * @filter_rfs_insert: Add or replace a filter for RFS. This must be1005 * atomic. The hardware change may be asynchronous but should1006 * not be delayed for long. It may fail if this can't be done1007 * atomically.1008 * @filter_rfs_expire_one: Consider expiring a filter inserted for RFS.1009 * This must check whether the specified table entry is used by RFS1010 * and that rps_may_expire_flow() returns true for it.1011 * @mtd_probe: Probe and add MTD partitions associated with this net device,1012 * using ef4_mtd_add()1013 * @mtd_rename: Set an MTD partition name using the net device name1014 * @mtd_read: Read from an MTD partition1015 * @mtd_erase: Erase part of an MTD partition1016 * @mtd_write: Write to an MTD partition1017 * @mtd_sync: Wait for write-back to complete on MTD partition. This1018 * also notifies the driver that a writer has finished using this1019 * partition.1020 * @set_mac_address: Set the MAC address of the device1021 * @revision: Hardware architecture revision1022 * @txd_ptr_tbl_base: TX descriptor ring base address1023 * @rxd_ptr_tbl_base: RX descriptor ring base address1024 * @buf_tbl_base: Buffer table base address1025 * @evq_ptr_tbl_base: Event queue pointer table base address1026 * @evq_rptr_tbl_base: Event queue read-pointer table base address1027 * @max_dma_mask: Maximum possible DMA mask1028 * @rx_prefix_size: Size of RX prefix before packet data1029 * @rx_hash_offset: Offset of RX flow hash within prefix1030 * @rx_ts_offset: Offset of timestamp within prefix1031 * @rx_buffer_padding: Size of padding at end of RX packet1032 * @can_rx_scatter: NIC is able to scatter packets to multiple buffers1033 * @always_rx_scatter: NIC will always scatter packets to multiple buffers1034 * @max_interrupt_mode: Highest capability interrupt mode supported1035 * from &enum ef4_init_mode.1036 * @timer_period_max: Maximum period of interrupt timer (in ticks)1037 * @offload_features: net_device feature flags for protocol offload1038 * features implemented in hardware1039 */1040struct ef4_nic_type {1041 unsigned int mem_bar;1042 unsigned int (*mem_map_size)(struct ef4_nic *efx);1043 int (*probe)(struct ef4_nic *efx);1044 void (*remove)(struct ef4_nic *efx);1045 int (*init)(struct ef4_nic *efx);1046 int (*dimension_resources)(struct ef4_nic *efx);1047 void (*fini)(struct ef4_nic *efx);1048 void (*monitor)(struct ef4_nic *efx);1049 enum reset_type (*map_reset_reason)(enum reset_type reason);1050 int (*map_reset_flags)(u32 *flags);1051 int (*reset)(struct ef4_nic *efx, enum reset_type method);1052 int (*probe_port)(struct ef4_nic *efx);1053 void (*remove_port)(struct ef4_nic *efx);1054 bool (*handle_global_event)(struct ef4_channel *channel, ef4_qword_t *);1055 int (*fini_dmaq)(struct ef4_nic *efx);1056 void (*prepare_flush)(struct ef4_nic *efx);1057 void (*finish_flush)(struct ef4_nic *efx);1058 void (*prepare_flr)(struct ef4_nic *efx);1059 void (*finish_flr)(struct ef4_nic *efx);1060 size_t (*describe_stats)(struct ef4_nic *efx, u8 *names);1061 size_t (*update_stats)(struct ef4_nic *efx, u64 *full_stats,1062 struct rtnl_link_stats64 *core_stats);1063 void (*start_stats)(struct ef4_nic *efx);1064 void (*pull_stats)(struct ef4_nic *efx);1065 void (*stop_stats)(struct ef4_nic *efx);1066 void (*set_id_led)(struct ef4_nic *efx, enum ef4_led_mode mode);1067 void (*push_irq_moderation)(struct ef4_channel *channel);1068 int (*reconfigure_port)(struct ef4_nic *efx);1069 void (*prepare_enable_fc_tx)(struct ef4_nic *efx);1070 int (*reconfigure_mac)(struct ef4_nic *efx);1071 bool (*check_mac_fault)(struct ef4_nic *efx);1072 void (*get_wol)(struct ef4_nic *efx, struct ethtool_wolinfo *wol);1073 int (*set_wol)(struct ef4_nic *efx, u32 type);1074 void (*resume_wol)(struct ef4_nic *efx);1075 int (*test_chip)(struct ef4_nic *efx, struct ef4_self_tests *tests);1076 int (*test_nvram)(struct ef4_nic *efx);1077 void (*irq_enable_master)(struct ef4_nic *efx);1078 int (*irq_test_generate)(struct ef4_nic *efx);1079 void (*irq_disable_non_ev)(struct ef4_nic *efx);1080 irqreturn_t (*irq_handle_msi)(int irq, void *dev_id);1081 irqreturn_t (*irq_handle_legacy)(int irq, void *dev_id);1082 int (*tx_probe)(struct ef4_tx_queue *tx_queue);1083 void (*tx_init)(struct ef4_tx_queue *tx_queue);1084 void (*tx_remove)(struct ef4_tx_queue *tx_queue);1085 void (*tx_write)(struct ef4_tx_queue *tx_queue);1086 unsigned int (*tx_limit_len)(struct ef4_tx_queue *tx_queue,1087 dma_addr_t dma_addr, unsigned int len);1088 int (*rx_push_rss_config)(struct ef4_nic *efx, bool user,1089 const u32 *rx_indir_table);1090 int (*rx_probe)(struct ef4_rx_queue *rx_queue);1091 void (*rx_init)(struct ef4_rx_queue *rx_queue);1092 void (*rx_remove)(struct ef4_rx_queue *rx_queue);1093 void (*rx_write)(struct ef4_rx_queue *rx_queue);1094 void (*rx_defer_refill)(struct ef4_rx_queue *rx_queue);1095 int (*ev_probe)(struct ef4_channel *channel);1096 int (*ev_init)(struct ef4_channel *channel);1097 void (*ev_fini)(struct ef4_channel *channel);1098 void (*ev_remove)(struct ef4_channel *channel);1099 int (*ev_process)(struct ef4_channel *channel, int quota);1100 void (*ev_read_ack)(struct ef4_channel *channel);1101 void (*ev_test_generate)(struct ef4_channel *channel);1102 int (*filter_table_probe)(struct ef4_nic *efx);1103 void (*filter_table_restore)(struct ef4_nic *efx);1104 void (*filter_table_remove)(struct ef4_nic *efx);1105 void (*filter_update_rx_scatter)(struct ef4_nic *efx);1106 s32 (*filter_insert)(struct ef4_nic *efx,1107 struct ef4_filter_spec *spec, bool replace);1108 int (*filter_remove_safe)(struct ef4_nic *efx,1109 enum ef4_filter_priority priority,1110 u32 filter_id);1111 int (*filter_get_safe)(struct ef4_nic *efx,1112 enum ef4_filter_priority priority,1113 u32 filter_id, struct ef4_filter_spec *);1114 int (*filter_clear_rx)(struct ef4_nic *efx,1115 enum ef4_filter_priority priority);1116 u32 (*filter_count_rx_used)(struct ef4_nic *efx,1117 enum ef4_filter_priority priority);1118 u32 (*filter_get_rx_id_limit)(struct ef4_nic *efx);1119 s32 (*filter_get_rx_ids)(struct ef4_nic *efx,1120 enum ef4_filter_priority priority,1121 u32 *buf, u32 size);1122#ifdef CONFIG_RFS_ACCEL1123 s32 (*filter_rfs_insert)(struct ef4_nic *efx,1124 struct ef4_filter_spec *spec);1125 bool (*filter_rfs_expire_one)(struct ef4_nic *efx, u32 flow_id,1126 unsigned int index);1127#endif1128#ifdef CONFIG_SFC_FALCON_MTD1129 int (*mtd_probe)(struct ef4_nic *efx);1130 void (*mtd_rename)(struct ef4_mtd_partition *part);1131 int (*mtd_read)(struct mtd_info *mtd, loff_t start, size_t len,1132 size_t *retlen, u8 *buffer);1133 int (*mtd_erase)(struct mtd_info *mtd, loff_t start, size_t len);1134 int (*mtd_write)(struct mtd_info *mtd, loff_t start, size_t len,1135 size_t *retlen, const u8 *buffer);1136 int (*mtd_sync)(struct mtd_info *mtd);1137#endif1138 int (*get_mac_address)(struct ef4_nic *efx, unsigned char *perm_addr);1139 int (*set_mac_address)(struct ef4_nic *efx);1140 1141 int revision;1142 unsigned int txd_ptr_tbl_base;1143 unsigned int rxd_ptr_tbl_base;1144 unsigned int buf_tbl_base;1145 unsigned int evq_ptr_tbl_base;1146 unsigned int evq_rptr_tbl_base;1147 u64 max_dma_mask;1148 unsigned int rx_prefix_size;1149 unsigned int rx_hash_offset;1150 unsigned int rx_ts_offset;1151 unsigned int rx_buffer_padding;1152 bool can_rx_scatter;1153 bool always_rx_scatter;1154 unsigned int max_interrupt_mode;1155 unsigned int timer_period_max;1156 netdev_features_t offload_features;1157 unsigned int max_rx_ip_filters;1158};1159 1160/**************************************************************************1161 *1162 * Prototypes and inline functions1163 *1164 *************************************************************************/1165 1166static inline struct ef4_channel *1167ef4_get_channel(struct ef4_nic *efx, unsigned index)1168{1169 EF4_BUG_ON_PARANOID(index >= efx->n_channels);1170 return efx->channel[index];1171}1172 1173/* Iterate over all used channels */1174#define ef4_for_each_channel(_channel, _efx) \1175 for (_channel = (_efx)->channel[0]; \1176 _channel; \1177 _channel = (_channel->channel + 1 < (_efx)->n_channels) ? \1178 (_efx)->channel[_channel->channel + 1] : NULL)1179 1180/* Iterate over all used channels in reverse */1181#define ef4_for_each_channel_rev(_channel, _efx) \1182 for (_channel = (_efx)->channel[(_efx)->n_channels - 1]; \1183 _channel; \1184 _channel = _channel->channel ? \1185 (_efx)->channel[_channel->channel - 1] : NULL)1186 1187static inline struct ef4_tx_queue *1188ef4_get_tx_queue(struct ef4_nic *efx, unsigned index, unsigned type)1189{1190 EF4_BUG_ON_PARANOID(index >= efx->n_tx_channels ||1191 type >= EF4_TXQ_TYPES);1192 return &efx->channel[efx->tx_channel_offset + index]->tx_queue[type];1193}1194 1195static inline bool ef4_channel_has_tx_queues(struct ef4_channel *channel)1196{1197 return channel->channel - channel->efx->tx_channel_offset <1198 channel->efx->n_tx_channels;1199}1200 1201static inline struct ef4_tx_queue *1202ef4_channel_get_tx_queue(struct ef4_channel *channel, unsigned type)1203{1204 EF4_BUG_ON_PARANOID(!ef4_channel_has_tx_queues(channel) ||1205 type >= EF4_TXQ_TYPES);1206 return &channel->tx_queue[type];1207}1208 1209static inline bool ef4_tx_queue_used(struct ef4_tx_queue *tx_queue)1210{1211 return !(tx_queue->efx->net_dev->num_tc < 2 &&1212 tx_queue->queue & EF4_TXQ_TYPE_HIGHPRI);1213}1214 1215/* Iterate over all TX queues belonging to a channel */1216#define ef4_for_each_channel_tx_queue(_tx_queue, _channel) \1217 if (!ef4_channel_has_tx_queues(_channel)) \1218 ; \1219 else \1220 for (_tx_queue = (_channel)->tx_queue; \1221 _tx_queue < (_channel)->tx_queue + EF4_TXQ_TYPES && \1222 ef4_tx_queue_used(_tx_queue); \1223 _tx_queue++)1224 1225/* Iterate over all possible TX queues belonging to a channel */1226#define ef4_for_each_possible_channel_tx_queue(_tx_queue, _channel) \1227 if (!ef4_channel_has_tx_queues(_channel)) \1228 ; \1229 else \1230 for (_tx_queue = (_channel)->tx_queue; \1231 _tx_queue < (_channel)->tx_queue + EF4_TXQ_TYPES; \1232 _tx_queue++)1233 1234static inline bool ef4_channel_has_rx_queue(struct ef4_channel *channel)1235{1236 return channel->rx_queue.core_index >= 0;1237}1238 1239static inline struct ef4_rx_queue *1240ef4_channel_get_rx_queue(struct ef4_channel *channel)1241{1242 EF4_BUG_ON_PARANOID(!ef4_channel_has_rx_queue(channel));1243 return &channel->rx_queue;1244}1245 1246/* Iterate over all RX queues belonging to a channel */1247#define ef4_for_each_channel_rx_queue(_rx_queue, _channel) \1248 if (!ef4_channel_has_rx_queue(_channel)) \1249 ; \1250 else \1251 for (_rx_queue = &(_channel)->rx_queue; \1252 _rx_queue; \1253 _rx_queue = NULL)1254 1255static inline struct ef4_channel *1256ef4_rx_queue_channel(struct ef4_rx_queue *rx_queue)1257{1258 return container_of(rx_queue, struct ef4_channel, rx_queue);1259}1260 1261static inline int ef4_rx_queue_index(struct ef4_rx_queue *rx_queue)1262{1263 return ef4_rx_queue_channel(rx_queue)->channel;1264}1265 1266/* Returns a pointer to the specified receive buffer in the RX1267 * descriptor queue.1268 */1269static inline struct ef4_rx_buffer *ef4_rx_buffer(struct ef4_rx_queue *rx_queue,1270 unsigned int index)1271{1272 return &rx_queue->buffer[index];1273}1274 1275/**1276 * EF4_MAX_FRAME_LEN - calculate maximum frame length1277 *1278 * This calculates the maximum frame length that will be used for a1279 * given MTU. The frame length will be equal to the MTU plus a1280 * constant amount of header space and padding. This is the quantity1281 * that the net driver will program into the MAC as the maximum frame1282 * length.1283 *1284 * The 10G MAC requires 8-byte alignment on the frame1285 * length, so we round up to the nearest 8.1286 *1287 * Re-clocking by the XGXS on RX can reduce an IPG to 32 bits (half an1288 * XGMII cycle). If the frame length reaches the maximum value in the1289 * same cycle, the XMAC can miss the IPG altogether. We work around1290 * this by adding a further 16 bytes.1291 */1292#define EF4_FRAME_PAD 161293#define EF4_MAX_FRAME_LEN(mtu) \1294 (ALIGN(((mtu) + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN + EF4_FRAME_PAD), 8))1295 1296/* Get all supported features.1297 * If a feature is not fixed, it is present in hw_features.1298 * If a feature is fixed, it does not present in hw_features, but1299 * always in features.1300 */1301static inline netdev_features_t ef4_supported_features(const struct ef4_nic *efx)1302{1303 const struct net_device *net_dev = efx->net_dev;1304 1305 return net_dev->features | net_dev->hw_features;1306}1307 1308/* Get the current TX queue insert index. */1309static inline unsigned int1310ef4_tx_queue_get_insert_index(const struct ef4_tx_queue *tx_queue)1311{1312 return tx_queue->insert_count & tx_queue->ptr_mask;1313}1314 1315/* Get a TX buffer. */1316static inline struct ef4_tx_buffer *1317__ef4_tx_queue_get_insert_buffer(const struct ef4_tx_queue *tx_queue)1318{1319 return &tx_queue->buffer[ef4_tx_queue_get_insert_index(tx_queue)];1320}1321 1322/* Get a TX buffer, checking it's not currently in use. */1323static inline struct ef4_tx_buffer *1324ef4_tx_queue_get_insert_buffer(const struct ef4_tx_queue *tx_queue)1325{1326 struct ef4_tx_buffer *buffer =1327 __ef4_tx_queue_get_insert_buffer(tx_queue);1328 1329 EF4_BUG_ON_PARANOID(buffer->len);1330 EF4_BUG_ON_PARANOID(buffer->flags);1331 EF4_BUG_ON_PARANOID(buffer->unmap_len);1332 1333 return buffer;1334}1335 1336#endif /* EF4_NET_DRIVER_H */1337