19452 lines · c
1/* SPDX-License-Identifier: GPL-2.0-only */2/****************************************************************************3 * Driver for Solarflare network controllers and boards4 * Copyright 2009-2018 Solarflare Communications Inc.5 * Copyright 2019-2020 Xilinx Inc.6 */7 8 9#ifndef MCDI_PCOL_H10#define MCDI_PCOL_H11 12/* Values to be written into FMCR_CZ_RESET_STATE_REG to control boot. */13/* Power-on reset state */14#define MC_FW_STATE_POR (1)15/* If this is set in MC_RESET_STATE_REG then it should be16 * possible to jump into IMEM without loading code from flash. */17#define MC_FW_WARM_BOOT_OK (2)18/* The MC main image has started to boot. */19#define MC_FW_STATE_BOOTING (4)20/* The Scheduler has started. */21#define MC_FW_STATE_SCHED (8)22/* If this is set in MC_RESET_STATE_REG then it should be23 * possible to jump into IMEM without loading code from flash.24 * Unlike a warm boot, assume DMEM has been reloaded, so that25 * the MC persistent data must be reinitialised. */26#define MC_FW_TEPID_BOOT_OK (16)27/* We have entered the main firmware via recovery mode. This28 * means that MC persistent data must be reinitialised, but that29 * we shouldn't touch PCIe config. */30#define MC_FW_RECOVERY_MODE_PCIE_INIT_OK (32)31/* BIST state has been initialized */32#define MC_FW_BIST_INIT_OK (128)33 34/* Siena MC shared memmory offsets */35/* The 'doorbell' addresses are hard-wired to alert the MC when written */36#define MC_SMEM_P0_DOORBELL_OFST 0x00037#define MC_SMEM_P1_DOORBELL_OFST 0x00438/* The rest of these are firmware-defined */39#define MC_SMEM_P0_PDU_OFST 0x00840#define MC_SMEM_P1_PDU_OFST 0x10841#define MC_SMEM_PDU_LEN 0x10042#define MC_SMEM_P0_PTP_TIME_OFST 0x7f043#define MC_SMEM_P0_STATUS_OFST 0x7f844#define MC_SMEM_P1_STATUS_OFST 0x7fc45 46/* Values to be written to the per-port status dword in shared47 * memory on reboot and assert */48#define MC_STATUS_DWORD_REBOOT (0xb007b007)49#define MC_STATUS_DWORD_ASSERT (0xdeaddead)50 51/* Check whether an mcfw version (in host order) belongs to a bootloader */52#define MC_FW_VERSION_IS_BOOTLOADER(_v) (((_v) >> 16) == 0xb007)53 54/* The current version of the MCDI protocol.55 *56 * Note that the ROM burnt into the card only talks V0, so at the very57 * least every driver must support version 0 and MCDI_PCOL_VERSION58 */59#define MCDI_PCOL_VERSION 260 61/* Unused commands: 0x23, 0x27, 0x30, 0x31 */62 63/* MCDI version 164 *65 * Each MCDI request starts with an MCDI_HEADER, which is a 32bit66 * structure, filled in by the client.67 *68 * 0 7 8 16 20 22 23 24 3169 * | CODE | R | LEN | SEQ | Rsvd | E | R | XFLAGS |70 * | | |71 * | | \--- Response72 * | \------- Error73 * \------------------------------ Resync (always set)74 *75 * The client writes it's request into MC shared memory, and rings the76 * doorbell. Each request is completed by either by the MC writing77 * back into shared memory, or by writing out an event.78 *79 * All MCDI commands support completion by shared memory response. Each80 * request may also contain additional data (accounted for by HEADER.LEN),81 * and some response's may also contain additional data (again, accounted82 * for by HEADER.LEN).83 *84 * Some MCDI commands support completion by event, in which any associated85 * response data is included in the event.86 *87 * The protocol requires one response to be delivered for every request, a88 * request should not be sent unless the response for the previous request89 * has been received (either by polling shared memory, or by receiving90 * an event).91 */92 93/** Request/Response structure */94#define MCDI_HEADER_OFST 095#define MCDI_HEADER_CODE_LBN 096#define MCDI_HEADER_CODE_WIDTH 797#define MCDI_HEADER_RESYNC_LBN 798#define MCDI_HEADER_RESYNC_WIDTH 199#define MCDI_HEADER_DATALEN_LBN 8100#define MCDI_HEADER_DATALEN_WIDTH 8101#define MCDI_HEADER_SEQ_LBN 16102#define MCDI_HEADER_SEQ_WIDTH 4103#define MCDI_HEADER_RSVD_LBN 20104#define MCDI_HEADER_RSVD_WIDTH 1105#define MCDI_HEADER_NOT_EPOCH_LBN 21106#define MCDI_HEADER_NOT_EPOCH_WIDTH 1107#define MCDI_HEADER_ERROR_LBN 22108#define MCDI_HEADER_ERROR_WIDTH 1109#define MCDI_HEADER_RESPONSE_LBN 23110#define MCDI_HEADER_RESPONSE_WIDTH 1111#define MCDI_HEADER_XFLAGS_LBN 24112#define MCDI_HEADER_XFLAGS_WIDTH 8113/* Request response using event */114#define MCDI_HEADER_XFLAGS_EVREQ 0x01115/* Request (and signal) early doorbell return */116#define MCDI_HEADER_XFLAGS_DBRET 0x02117 118/* Maximum number of payload bytes */119#define MCDI_CTL_SDU_LEN_MAX_V1 0xfc120#define MCDI_CTL_SDU_LEN_MAX_V2 0x400121 122#define MCDI_CTL_SDU_LEN_MAX MCDI_CTL_SDU_LEN_MAX_V2123 124 125/* The MC can generate events for two reasons:126 * - To advance a shared memory request if XFLAGS_EVREQ was set127 * - As a notification (link state, i2c event), controlled128 * via MC_CMD_LOG_CTRL129 *130 * Both events share a common structure:131 *132 * 0 32 33 36 44 52 60133 * | Data | Cont | Level | Src | Code | Rsvd |134 * |135 * \ There is another event pending in this notification136 *137 * If Code==CMDDONE, then the fields are further interpreted as:138 *139 * - LEVEL==INFO Command succeeded140 * - LEVEL==ERR Command failed141 *142 * 0 8 16 24 32143 * | Seq | Datalen | Errno | Rsvd |144 *145 * These fields are taken directly out of the standard MCDI header, i.e.,146 * LEVEL==ERR, Datalen == 0 => Reboot147 *148 * Events can be squirted out of the UART (using LOG_CTRL) without a149 * MCDI header. An event can be distinguished from a MCDI response by150 * examining the first byte which is 0xc0. This corresponds to the151 * non-existent MCDI command MC_CMD_DEBUG_LOG.152 *153 * 0 7 8154 * | command | Resync | = 0xc0155 *156 * Since the event is written in big-endian byte order, this works157 * providing bits 56-63 of the event are 0xc0.158 *159 * 56 60 63160 * | Rsvd | Code | = 0xc0161 *162 * Which means for convenience the event code is 0xc for all MC163 * generated events.164 */165#define FSE_AZ_EV_CODE_MCDI_EVRESPONSE 0xc166 167 168#define MC_CMD_ERR_CODE_OFST 0169#define MC_CMD_ERR_PROXY_PENDING_HANDLE_OFST 4170 171/* We define 8 "escape" commands to allow172 for command number space extension */173 174#define MC_CMD_CMD_SPACE_ESCAPE_0 0x78175#define MC_CMD_CMD_SPACE_ESCAPE_1 0x79176#define MC_CMD_CMD_SPACE_ESCAPE_2 0x7A177#define MC_CMD_CMD_SPACE_ESCAPE_3 0x7B178#define MC_CMD_CMD_SPACE_ESCAPE_4 0x7C179#define MC_CMD_CMD_SPACE_ESCAPE_5 0x7D180#define MC_CMD_CMD_SPACE_ESCAPE_6 0x7E181#define MC_CMD_CMD_SPACE_ESCAPE_7 0x7F182 183/* Vectors in the boot ROM */184/* Point to the copycode entry point. */185#define SIENA_MC_BOOTROM_COPYCODE_VEC (0x800 - 3 * 0x4)186#define HUNT_MC_BOOTROM_COPYCODE_VEC (0x8000 - 3 * 0x4)187#define MEDFORD_MC_BOOTROM_COPYCODE_VEC (0x10000 - 3 * 0x4)188/* Points to the recovery mode entry point. Misnamed but kept for compatibility. */189#define SIENA_MC_BOOTROM_NOFLASH_VEC (0x800 - 2 * 0x4)190#define HUNT_MC_BOOTROM_NOFLASH_VEC (0x8000 - 2 * 0x4)191#define MEDFORD_MC_BOOTROM_NOFLASH_VEC (0x10000 - 2 * 0x4)192/* Points to the recovery mode entry point. Same as above, but the right name. */193#define SIENA_MC_BOOTROM_RECOVERY_VEC (0x800 - 2 * 0x4)194#define HUNT_MC_BOOTROM_RECOVERY_VEC (0x8000 - 2 * 0x4)195#define MEDFORD_MC_BOOTROM_RECOVERY_VEC (0x10000 - 2 * 0x4)196 197/* Points to noflash mode entry point. */198#define MEDFORD_MC_BOOTROM_REAL_NOFLASH_VEC (0x10000 - 4 * 0x4)199 200/* The command set exported by the boot ROM (MCDI v0) */201#define MC_CMD_GET_VERSION_V0_SUPPORTED_FUNCS { \202 (1 << MC_CMD_READ32) | \203 (1 << MC_CMD_WRITE32) | \204 (1 << MC_CMD_COPYCODE) | \205 (1 << MC_CMD_GET_VERSION), \206 0, 0, 0 }207 208#define MC_CMD_SENSOR_INFO_OUT_OFFSET_OFST(_x) \209 (MC_CMD_SENSOR_ENTRY_OFST + (_x))210 211#define MC_CMD_DBI_WRITE_IN_ADDRESS_OFST(n) \212 (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST + \213 MC_CMD_DBIWROP_TYPEDEF_ADDRESS_OFST + \214 (n) * MC_CMD_DBIWROP_TYPEDEF_LEN)215 216#define MC_CMD_DBI_WRITE_IN_BYTE_MASK_OFST(n) \217 (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST + \218 MC_CMD_DBIWROP_TYPEDEF_BYTE_MASK_OFST + \219 (n) * MC_CMD_DBIWROP_TYPEDEF_LEN)220 221#define MC_CMD_DBI_WRITE_IN_VALUE_OFST(n) \222 (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST + \223 MC_CMD_DBIWROP_TYPEDEF_VALUE_OFST + \224 (n) * MC_CMD_DBIWROP_TYPEDEF_LEN)225 226/* This may be ORed with an EVB_PORT_ID_xxx constant to pass a non-default227 * stack ID (which must be in the range 1-255) along with an EVB port ID.228 */229#define EVB_STACK_ID(n) (((n) & 0xff) << 16)230 231 232/* Version 2 adds an optional argument to error returns: the errno value233 * may be followed by the (0-based) number of the first argument that234 * could not be processed.235 */236#define MC_CMD_ERR_ARG_OFST 4237 238/* MC_CMD_ERR enum: Public MCDI error codes. Error codes that correspond to239 * POSIX errnos should use the same numeric values that linux does. Error codes240 * specific to Solarflare firmware should use values in the range 0x1000 -241 * 0x10ff. The range 0x2000 - 0x20ff is reserved for private error codes (see242 * MC_CMD_ERR_PRIV below).243 */244/* enum: Operation not permitted. */245#define MC_CMD_ERR_EPERM 0x1246/* enum: Non-existent command target */247#define MC_CMD_ERR_ENOENT 0x2248/* enum: assert() has killed the MC */249#define MC_CMD_ERR_EINTR 0x4250/* enum: I/O failure */251#define MC_CMD_ERR_EIO 0x5252/* enum: Already exists */253#define MC_CMD_ERR_EEXIST 0x6254/* enum: Try again */255#define MC_CMD_ERR_EAGAIN 0xb256/* enum: Out of memory */257#define MC_CMD_ERR_ENOMEM 0xc258/* enum: Caller does not hold required locks */259#define MC_CMD_ERR_EACCES 0xd260/* enum: Resource is currently unavailable (e.g. lock contention) */261#define MC_CMD_ERR_EBUSY 0x10262/* enum: No such device */263#define MC_CMD_ERR_ENODEV 0x13264/* enum: Invalid argument to target */265#define MC_CMD_ERR_EINVAL 0x16266/* enum: No space */267#define MC_CMD_ERR_ENOSPC 0x1c268/* enum: Read-only */269#define MC_CMD_ERR_EROFS 0x1e270/* enum: Broken pipe */271#define MC_CMD_ERR_EPIPE 0x20272/* enum: Out of range */273#define MC_CMD_ERR_ERANGE 0x22274/* enum: Non-recursive resource is already acquired */275#define MC_CMD_ERR_EDEADLK 0x23276/* enum: Operation not implemented */277#define MC_CMD_ERR_ENOSYS 0x26278/* enum: Operation timed out */279#define MC_CMD_ERR_ETIME 0x3e280/* enum: Link has been severed */281#define MC_CMD_ERR_ENOLINK 0x43282/* enum: Protocol error */283#define MC_CMD_ERR_EPROTO 0x47284/* enum: Bad message */285#define MC_CMD_ERR_EBADMSG 0x4a286/* enum: Operation not supported */287#define MC_CMD_ERR_ENOTSUP 0x5f288/* enum: Address not available */289#define MC_CMD_ERR_EADDRNOTAVAIL 0x63290/* enum: Not connected */291#define MC_CMD_ERR_ENOTCONN 0x6b292/* enum: Operation already in progress */293#define MC_CMD_ERR_EALREADY 0x72294/* enum: Stale handle. The handle references a resource that no longer exists.295 */296#define MC_CMD_ERR_ESTALE 0x74297/* enum: Resource allocation failed. */298#define MC_CMD_ERR_ALLOC_FAIL 0x1000299/* enum: V-adaptor not found. */300#define MC_CMD_ERR_NO_VADAPTOR 0x1001301/* enum: EVB port not found. */302#define MC_CMD_ERR_NO_EVB_PORT 0x1002303/* enum: V-switch not found. */304#define MC_CMD_ERR_NO_VSWITCH 0x1003305/* enum: Too many VLAN tags. */306#define MC_CMD_ERR_VLAN_LIMIT 0x1004307/* enum: Bad PCI function number. */308#define MC_CMD_ERR_BAD_PCI_FUNC 0x1005309/* enum: Invalid VLAN mode. */310#define MC_CMD_ERR_BAD_VLAN_MODE 0x1006311/* enum: Invalid v-switch type. */312#define MC_CMD_ERR_BAD_VSWITCH_TYPE 0x1007313/* enum: Invalid v-port type. */314#define MC_CMD_ERR_BAD_VPORT_TYPE 0x1008315/* enum: MAC address exists. */316#define MC_CMD_ERR_MAC_EXIST 0x1009317/* enum: Slave core not present */318#define MC_CMD_ERR_SLAVE_NOT_PRESENT 0x100a319/* enum: The datapath is disabled. */320#define MC_CMD_ERR_DATAPATH_DISABLED 0x100b321/* enum: The requesting client is not a function */322#define MC_CMD_ERR_CLIENT_NOT_FN 0x100c323/* enum: The requested operation might require the command to be passed between324 * MCs, and thetransport doesn't support that. Should only ever been seen over325 * the UART.326 */327#define MC_CMD_ERR_TRANSPORT_NOPROXY 0x100d328/* enum: VLAN tag(s) exists */329#define MC_CMD_ERR_VLAN_EXIST 0x100e330/* enum: No MAC address assigned to an EVB port */331#define MC_CMD_ERR_NO_MAC_ADDR 0x100f332/* enum: Notifies the driver that the request has been relayed to an admin333 * function for authorization. The driver should wait for a PROXY_RESPONSE334 * event and then resend its request. This error code is followed by a 32-bit335 * handle that helps matching it with the respective PROXY_RESPONSE event.336 */337#define MC_CMD_ERR_PROXY_PENDING 0x1010338/* enum: The request cannot be passed for authorization because another request339 * from the same function is currently being authorized. The drvier should try340 * again later.341 */342#define MC_CMD_ERR_PROXY_INPROGRESS 0x1011343/* enum: Returned by MC_CMD_PROXY_COMPLETE if the caller is not the function344 * that has enabled proxying or BLOCK_INDEX points to a function that doesn't345 * await an authorization.346 */347#define MC_CMD_ERR_PROXY_UNEXPECTED 0x1012348/* enum: This code is currently only used internally in FW. Its meaning is that349 * an operation failed due to lack of SR-IOV privilege. Normally it is350 * translated to EPERM by send_cmd_err(), but it may also be used to trigger351 * some special mechanism for handling such case, e.g. to relay the failed352 * request to a designated admin function for authorization.353 */354#define MC_CMD_ERR_NO_PRIVILEGE 0x1013355/* enum: Workaround 26807 could not be turned on/off because some functions356 * have already installed filters. See the comment at357 * MC_CMD_WORKAROUND_BUG26807. May also returned for other operations such as358 * sub-variant switching.359 */360#define MC_CMD_ERR_FILTERS_PRESENT 0x1014361/* enum: The clock whose frequency you've attempted to set set doesn't exist on362 * this NIC363 */364#define MC_CMD_ERR_NO_CLOCK 0x1015365/* enum: Returned by MC_CMD_TESTASSERT if the action that should have caused an366 * assertion failed to do so.367 */368#define MC_CMD_ERR_UNREACHABLE 0x1016369/* enum: This command needs to be processed in the background but there were no370 * resources to do so. Send it again after a command has completed.371 */372#define MC_CMD_ERR_QUEUE_FULL 0x1017373/* enum: The operation could not be completed because the PCIe link has gone374 * away. This error code is never expected to be returned over the TLP375 * transport.376 */377#define MC_CMD_ERR_NO_PCIE 0x1018378/* enum: The operation could not be completed because the datapath has gone379 * away. This is distinct from MC_CMD_ERR_DATAPATH_DISABLED in that the380 * datapath absence may be temporary381 */382#define MC_CMD_ERR_NO_DATAPATH 0x1019383/* enum: The operation could not complete because some VIs are allocated */384#define MC_CMD_ERR_VIS_PRESENT 0x101a385/* enum: The operation could not complete because some PIO buffers are386 * allocated387 */388#define MC_CMD_ERR_PIOBUFS_PRESENT 0x101b389 390/* MC_CMD_RESOURCE_SPECIFIER enum */391/* enum: Any */392#define MC_CMD_RESOURCE_INSTANCE_ANY 0xffffffff393#define MC_CMD_RESOURCE_INSTANCE_NONE 0xfffffffe /* enum */394 395/* MC_CMD_FPGA_FLASH_INDEX enum */396#define MC_CMD_FPGA_FLASH_PRIMARY 0x0 /* enum */397#define MC_CMD_FPGA_FLASH_SECONDARY 0x1 /* enum */398 399/* MC_CMD_EXTERNAL_MAE_LINK_MODE enum */400/* enum: Legacy mode as described in XN-200039-TC. */401#define MC_CMD_EXTERNAL_MAE_LINK_MODE_LEGACY 0x0402/* enum: Switchdev mode as described in XN-200039-TC. */403#define MC_CMD_EXTERNAL_MAE_LINK_MODE_SWITCHDEV 0x1404/* enum: Bootstrap mode as described in XN-200039-TC. */405#define MC_CMD_EXTERNAL_MAE_LINK_MODE_BOOTSTRAP 0x2406/* enum: Link-mode change is in-progress as described in XN-200039-TC. */407#define MC_CMD_EXTERNAL_MAE_LINK_MODE_PENDING 0xf408 409/* PCIE_INTERFACE enum: From EF100 onwards, SFC products can have multiple PCIe410 * interfaces. There is a need to refer to interfaces explicitly from drivers411 * (for example, a management driver on one interface administering a function412 * on another interface). This enumeration provides stable identifiers to all413 * interfaces present on a product. Product documentation will specify which414 * interfaces exist and their associated identifier. In general, drivers,415 * should not assign special meanings to specific values. Instead, behaviour416 * should be determined by NIC configuration, which will identify interfaces417 * where appropriate.418 */419/* enum: Primary host interfaces. Typically (i.e. for all known SFC products)420 * the interface exposed on the edge connector (or form factor equivalent).421 */422#define PCIE_INTERFACE_HOST_PRIMARY 0x0423/* enum: Riverhead and keystone products have a second PCIe interface to which424 * an on-NIC ARM module is expected to be connected.425 */426#define PCIE_INTERFACE_NIC_EMBEDDED 0x1427/* enum: For MCDI commands issued over a PCIe interface, this value is428 * translated into the interface over which the command was issued. Not429 * meaningful for other MCDI transports.430 */431#define PCIE_INTERFACE_CALLER 0xffffffff432 433/* MC_CLIENT_ID_SPECIFIER enum */434/* enum: Equivalent to the caller's client ID */435#define MC_CMD_CLIENT_ID_SELF 0xffffffff436 437/* MAE_FIELD_SUPPORT_STATUS enum */438/* enum: The NIC does not support this field. The driver must ensure that any439 * mask associated with this field in a match rule is zeroed. The NIC may440 * either reject requests with an invalid mask for such a field, or may assume441 * that the mask is zero. (This category only exists to describe behaviour for442 * fields that a newer driver might know about but that older firmware does443 * not. It is recommended that firmware report MAE_FIELD_FIELD_MATCH_NEVER for444 * all match fields defined at the time of its compilation. If a driver see a445 * field support status value that it does not recognise, it must treat that446 * field as thought the field was reported as MAE_FIELD_SUPPORTED_MATCH_NEVER,447 * and must never set a non-zero mask value for this field.448 */449#define MAE_FIELD_UNSUPPORTED 0x0450/* enum: The NIC supports this field, but cannot use it in a match rule. The451 * driver must ensure that any mask for such a field in a match rule is zeroed.452 * The NIC will reject requests with an invalid mask for such a field.453 */454#define MAE_FIELD_SUPPORTED_MATCH_NEVER 0x1455/* enum: The NIC supports this field, and must use it in all match rules. The456 * driver must ensure that any mask for such a field is all ones. The NIC will457 * reject requests with an invalid mask for such a field.458 */459#define MAE_FIELD_SUPPORTED_MATCH_ALWAYS 0x2460/* enum: The NIC supports this field, and may optionally use it in match rules.461 * The driver must ensure that any mask for such a field is either all zeroes462 * or all ones. The NIC will reject requests with an invalid mask for such a463 * field.464 */465#define MAE_FIELD_SUPPORTED_MATCH_OPTIONAL 0x3466/* enum: The NIC supports this field, and may optionally use it in match rules.467 * The driver must ensure that any mask for such a field is either all zeroes468 * or a consecutive set of ones following by all zeroes (starting from MSB).469 * The NIC will reject requests with an invalid mask for such a field.470 */471#define MAE_FIELD_SUPPORTED_MATCH_PREFIX 0x4472/* enum: The NIC supports this field, and may optionally use it in match rules.473 * The driver may provide an arbitrary mask for such a field.474 */475#define MAE_FIELD_SUPPORTED_MATCH_MASK 0x5476 477/* MAE_CT_VNI_MODE enum: Controls the layout of the VNI input to the conntrack478 * lookup. (Values are not arbitrary - constrained by table access ABI.)479 */480/* enum: The VNI input to the conntrack lookup will be zero. */481#define MAE_CT_VNI_MODE_ZERO 0x0482/* enum: The VNI input to the conntrack lookup will be the VNI (VXLAN/Geneve)483 * or VSID (NVGRE) field from the packet.484 */485#define MAE_CT_VNI_MODE_VNI 0x1486/* enum: The VNI input to the conntrack lookup will be the VLAN ID from the487 * outermost VLAN tag (in bottom 12 bits; top 12 bits zero).488 */489#define MAE_CT_VNI_MODE_1VLAN 0x2490/* enum: The VNI input to the conntrack lookup will be the VLAN IDs from both491 * VLAN tags (outermost in bottom 12 bits, innermost in top 12 bits).492 */493#define MAE_CT_VNI_MODE_2VLAN 0x3494 495/* MAE_FIELD enum: NB: this enum shares namespace with the support status enum.496 */497/* enum: Source mport upon entering the MAE. */498#define MAE_FIELD_INGRESS_PORT 0x0499#define MAE_FIELD_MARK 0x1 /* enum */500/* enum: Table ID used in action rule. Initially zero, can be changed in action501 * rule response.502 */503#define MAE_FIELD_RECIRC_ID 0x2504#define MAE_FIELD_IS_IP_FRAG 0x3 /* enum */505#define MAE_FIELD_DO_CT 0x4 /* enum */506#define MAE_FIELD_CT_HIT 0x5 /* enum */507/* enum: Undefined unless CT_HIT=1. */508#define MAE_FIELD_CT_MARK 0x6509/* enum: Undefined unless DO_CT=1. */510#define MAE_FIELD_CT_DOMAIN 0x7511/* enum: Undefined unless CT_HIT=1. */512#define MAE_FIELD_CT_PRIVATE_FLAGS 0x8513/* enum: 1 if the packet ingressed the NIC from one of the MACs, else 0. */514#define MAE_FIELD_IS_FROM_NETWORK 0x9515/* enum: 1 if the packet has 1 or more VLAN tags, else 0. */516#define MAE_FIELD_HAS_OVLAN 0xa517/* enum: 1 if the packet has 2 or more VLAN tags, else 0. */518#define MAE_FIELD_HAS_IVLAN 0xb519/* enum: 1 if the outer packet has 1 or more VLAN tags, else 0; only present520 * when encap521 */522#define MAE_FIELD_ENC_HAS_OVLAN 0xc523/* enum: 1 if the outer packet has 2 or more VLAN tags, else 0; only present524 * when encap525 */526#define MAE_FIELD_ENC_HAS_IVLAN 0xd527/* enum: Packet is IP fragment */528#define MAE_FIELD_ENC_IP_FRAG 0xe529#define MAE_FIELD_ETHER_TYPE 0x21 /* enum */530#define MAE_FIELD_VLAN0_TCI 0x22 /* enum */531#define MAE_FIELD_VLAN0_PROTO 0x23 /* enum */532#define MAE_FIELD_VLAN1_TCI 0x24 /* enum */533#define MAE_FIELD_VLAN1_PROTO 0x25 /* enum */534/* enum: Inner when encap */535#define MAE_FIELD_ETH_SADDR 0x28536/* enum: Inner when encap */537#define MAE_FIELD_ETH_DADDR 0x29538/* enum: Inner when encap. NB: IPv4 and IPv6 fields are mutually exclusive. */539#define MAE_FIELD_SRC_IP4 0x2a540/* enum: Inner when encap */541#define MAE_FIELD_SRC_IP6 0x2b542/* enum: Inner when encap */543#define MAE_FIELD_DST_IP4 0x2c544/* enum: Inner when encap */545#define MAE_FIELD_DST_IP6 0x2d546/* enum: Inner when encap */547#define MAE_FIELD_IP_PROTO 0x2e548/* enum: Inner when encap */549#define MAE_FIELD_IP_TOS 0x2f550/* enum: Inner when encap */551#define MAE_FIELD_IP_TTL 0x30552/* enum: Inner when encap TODO: how this is defined? The raw flags +553 * frag_offset from the packet, or some derived value more amenable to ternary554 * matching? TODO: there was a proposal for driver-allocation fields. The555 * driver would provide some instruction for how to extract given field values,556 * and would be given a field id in return. It could then use that field id in557 * its matches. This feels like it would be extremely hard to implement in558 * hardware, but I mention it for completeness.559 */560#define MAE_FIELD_IP_FLAGS 0x31561/* enum: Ports (UDP, TCP) Inner when encap */562#define MAE_FIELD_L4_SPORT 0x32563/* enum: Ports (UDP, TCP) Inner when encap */564#define MAE_FIELD_L4_DPORT 0x33565/* enum: Inner when encap */566#define MAE_FIELD_TCP_FLAGS 0x34567/* enum: TCP packet with any of SYN, FIN or RST flag set */568#define MAE_FIELD_TCP_SYN_FIN_RST 0x35569/* enum: Packet is IP fragment with fragment offset 0 */570#define MAE_FIELD_IP_FIRST_FRAG 0x36571/* enum: The type of encapsulated used for this packet. Value as per572 * ENCAP_TYPE_*.573 */574#define MAE_FIELD_ENCAP_TYPE 0x3f575/* enum: The ID of the outer rule that marked this packet as encapsulated.576 * Useful for implicitly matching on outer fields.577 */578#define MAE_FIELD_OUTER_RULE_ID 0x40579/* enum: Outer; only present when encap */580#define MAE_FIELD_ENC_ETHER_TYPE 0x41581/* enum: Outer; only present when encap */582#define MAE_FIELD_ENC_VLAN0_TCI 0x42583/* enum: Outer; only present when encap */584#define MAE_FIELD_ENC_VLAN0_PROTO 0x43585/* enum: Outer; only present when encap */586#define MAE_FIELD_ENC_VLAN1_TCI 0x44587/* enum: Outer; only present when encap */588#define MAE_FIELD_ENC_VLAN1_PROTO 0x45589/* enum: Outer; only present when encap */590#define MAE_FIELD_ENC_ETH_SADDR 0x48591/* enum: Outer; only present when encap */592#define MAE_FIELD_ENC_ETH_DADDR 0x49593/* enum: Outer; only present when encap */594#define MAE_FIELD_ENC_SRC_IP4 0x4a595/* enum: Outer; only present when encap */596#define MAE_FIELD_ENC_SRC_IP6 0x4b597/* enum: Outer; only present when encap */598#define MAE_FIELD_ENC_DST_IP4 0x4c599/* enum: Outer; only present when encap */600#define MAE_FIELD_ENC_DST_IP6 0x4d601/* enum: Outer; only present when encap */602#define MAE_FIELD_ENC_IP_PROTO 0x4e603/* enum: Outer; only present when encap */604#define MAE_FIELD_ENC_IP_TOS 0x4f605/* enum: Outer; only present when encap */606#define MAE_FIELD_ENC_IP_TTL 0x50607/* enum: Outer; only present when encap */608#define MAE_FIELD_ENC_IP_FLAGS 0x51609/* enum: Outer; only present when encap */610#define MAE_FIELD_ENC_L4_SPORT 0x52611/* enum: Outer; only present when encap */612#define MAE_FIELD_ENC_L4_DPORT 0x53613/* enum: VNI (when VXLAN or GENEVE) VSID (when NVGRE) Bottom 24 bits of Key614 * (when L2GRE) Outer; only present when encap615 */616#define MAE_FIELD_ENC_VNET_ID 0x54617 618/* MAE_MCDI_ENCAP_TYPE enum: Encapsulation type. Defines how the payload will619 * be parsed to an inner frame. Other values are reserved. Unknown values620 * should be treated same as NONE. (Values are not arbitrary - constrained by621 * table access ABI.)622 */623#define MAE_MCDI_ENCAP_TYPE_NONE 0x0 /* enum */624/* enum: Don't assume enum aligns with support bitmask... */625#define MAE_MCDI_ENCAP_TYPE_VXLAN 0x1626#define MAE_MCDI_ENCAP_TYPE_NVGRE 0x2 /* enum */627#define MAE_MCDI_ENCAP_TYPE_GENEVE 0x3 /* enum */628#define MAE_MCDI_ENCAP_TYPE_L2GRE 0x4 /* enum */629 630/* MAE_MPORT_END enum: Selects which end of the logical link identified by an631 * MPORT_SELECTOR is targeted by an operation.632 */633/* enum: Selects the port on the MAE virtual switch */634#define MAE_MPORT_END_MAE 0x1635/* enum: Selects the virtual NIC plugged into the MAE switch */636#define MAE_MPORT_END_VNIC 0x2637 638/* MAE_COUNTER_TYPE enum: The datapath maintains several sets of counters, each639 * being associated with a different table. Note that the same counter ID may640 * be allocated by different counter blocks, so e.g. AR counter 42 is different641 * from CT counter 42. Generation counts are also type-specific. This value is642 * also present in the header of streaming counter packets, in the IDENTIFIER643 * field (see packetiser packet format definitions).644 */645/* enum: Action Rule counters - can be referenced in AR response. */646#define MAE_COUNTER_TYPE_AR 0x0647/* enum: Conntrack counters - can be referenced in CT response. */648#define MAE_COUNTER_TYPE_CT 0x1649/* enum: Outer Rule counters - can be referenced in OR response. */650#define MAE_COUNTER_TYPE_OR 0x2651 652/* TABLE_ID enum: Unique IDs for tables. The 32-bit ID values have been653 * structured with bits [31:24] reserved (0), [23:16] indicating which major654 * block the tables belongs to (0=VNIC TX, none currently; 1=MAE; 2=VNIC RX),655 * [15:8] a unique ID within the block, and [7:0] reserved for future656 * variations of the same table. (All of the tables currently defined within657 * the streaming engines are listed here, but this does not imply that they are658 * all supported - MC_CMD_TABLE_LIST returns the list of actually supported659 * tables.)660 */661/* enum: Outer_Rule_Table in the MAE - refer to SF-123102-TC. */662#define TABLE_ID_OUTER_RULE_TABLE 0x10000663/* enum: Outer_Rule_No_CT_Table in the MAE - refer to SF-123102-TC. */664#define TABLE_ID_OUTER_RULE_NO_CT_TABLE 0x10100665/* enum: Mgmt_Filter_Table in the MAE - refer to SF-123102-TC. */666#define TABLE_ID_MGMT_FILTER_TABLE 0x10200667/* enum: Conntrack_Table in the MAE - refer to SF-123102-TC. */668#define TABLE_ID_CONNTRACK_TABLE 0x10300669/* enum: Action_Rule_Table in the MAE - refer to SF-123102-TC. */670#define TABLE_ID_ACTION_RULE_TABLE 0x10400671/* enum: Mgroup_Default_Action_Set_Table in the MAE - refer to SF-123102-TC. */672#define TABLE_ID_MGROUP_DEFAULT_ACTION_SET_TABLE 0x10500673/* enum: Encap_Hdr_Part1_Table in the MAE - refer to SF-123102-TC. */674#define TABLE_ID_ENCAP_HDR_PART1_TABLE 0x10600675/* enum: Encap_Hdr_Part2_Table in the MAE - refer to SF-123102-TC. */676#define TABLE_ID_ENCAP_HDR_PART2_TABLE 0x10700677/* enum: Replace_Src_MAC_Table in the MAE - refer to SF-123102-TC. */678#define TABLE_ID_REPLACE_SRC_MAC_TABLE 0x10800679/* enum: Replace_Dst_MAC_Table in the MAE - refer to SF-123102-TC. */680#define TABLE_ID_REPLACE_DST_MAC_TABLE 0x10900681/* enum: Dst_Mport_VC_Table in the MAE - refer to SF-123102-TC. */682#define TABLE_ID_DST_MPORT_VC_TABLE 0x10a00683/* enum: LACP_LAG_Config_Table in the MAE - refer to SF-123102-TC. */684#define TABLE_ID_LACP_LAG_CONFIG_TABLE 0x10b00685/* enum: LACP_Balance_Table in the MAE - refer to SF-123102-TC. */686#define TABLE_ID_LACP_BALANCE_TABLE 0x10c00687/* enum: Dst_Mport_Host_Chan_Table in the MAE - refer to SF-123102-TC. */688#define TABLE_ID_DST_MPORT_HOST_CHAN_TABLE 0x10d00689/* enum: VNIC_Rx_Encap_Table in VNIC Rx - refer to SF-123102-TC. */690#define TABLE_ID_VNIC_RX_ENCAP_TABLE 0x20000691/* enum: Steering_Table in VNIC Rx - refer to SF-123102-TC. */692#define TABLE_ID_STEERING_TABLE 0x20100693/* enum: RSS_Context_Table in VNIC Rx - refer to SF-123102-TC. */694#define TABLE_ID_RSS_CONTEXT_TABLE 0x20200695/* enum: Indirection_Table in VNIC Rx - refer to SF-123102-TC. */696#define TABLE_ID_INDIRECTION_TABLE 0x20300697 698/* TABLE_COMPRESSED_VLAN enum: Compressed VLAN TPID as used by some field699 * types; can be calculated by (((ether_type_msb >> 2) & 0x4) ^ 0x4) |700 * (ether_type_msb & 0x3);701 */702#define TABLE_COMPRESSED_VLAN_TPID_8100 0x5 /* enum */703#define TABLE_COMPRESSED_VLAN_TPID_88A8 0x4 /* enum */704#define TABLE_COMPRESSED_VLAN_TPID_9100 0x1 /* enum */705#define TABLE_COMPRESSED_VLAN_TPID_9200 0x2 /* enum */706#define TABLE_COMPRESSED_VLAN_TPID_9300 0x3 /* enum */707 708/* TABLE_NAT_DIR enum: NAT direction. */709#define TABLE_NAT_DIR_SOURCE 0x0 /* enum */710#define TABLE_NAT_DIR_DEST 0x1 /* enum */711 712/* TABLE_RSS_KEY_MODE enum: Defines how the value for Toeplitz hashing for RSS713 * is constructed as a concatenation (indicated here by "++") of packet header714 * fields.715 */716/* enum: IP src addr ++ IP dst addr */717#define TABLE_RSS_KEY_MODE_SA_DA 0x0718/* enum: IP src addr ++ IP dst addr ++ TCP/UDP src port ++ TCP/UDP dst port */719#define TABLE_RSS_KEY_MODE_SA_DA_SP_DP 0x1720/* enum: IP src addr */721#define TABLE_RSS_KEY_MODE_SA 0x2722/* enum: IP dst addr */723#define TABLE_RSS_KEY_MODE_DA 0x3724/* enum: IP src addr ++ TCP/UDP src port */725#define TABLE_RSS_KEY_MODE_SA_SP 0x4726/* enum: IP dest addr ++ TCP dest port */727#define TABLE_RSS_KEY_MODE_DA_DP 0x5728/* enum: Nothing (produces input of 0, resulting in output hash of 0) */729#define TABLE_RSS_KEY_MODE_NONE 0x7730 731/* TABLE_RSS_SPREAD_MODE enum: RSS spreading mode. */732/* enum: RSS uses Indirection_Table lookup. */733#define TABLE_RSS_SPREAD_MODE_INDIRECTION 0x0734/* enum: RSS uses even spreading calculation. */735#define TABLE_RSS_SPREAD_MODE_EVEN 0x1736 737/* TABLE_FIELD_ID enum: Unique IDs for fields. Related concepts have been738 * loosely grouped together into blocks with gaps for expansion, but the values739 * are arbitrary. Field IDs are not specific to particular tables, and in some740 * cases this sharing means that they are not used with the exact names of the741 * corresponding table definitions in SF-123102-TC; however, the mapping should742 * still be clear. The intent is that a list of fields, with their associated743 * bit widths and semantics version code, unambiguously defines the semantics744 * of the fields in a key or response. (Again, this list includes all of the745 * fields currently defined within the streaming engines, but only a subset may746 * actually be used by the supported list of tables.)747 */748/* enum: May appear multiple times within a key or response, and indicates that749 * the field is unused and should be set to 0 (or masked out if permitted by750 * the MASK_VALUE for this field).751 */752#define TABLE_FIELD_ID_UNUSED 0x0753/* enum: Source m-port (a full m-port label). */754#define TABLE_FIELD_ID_SRC_MPORT 0x1755/* enum: Destination m-port (a full m-port label). */756#define TABLE_FIELD_ID_DST_MPORT 0x2757/* enum: Source m-group ID. */758#define TABLE_FIELD_ID_SRC_MGROUP_ID 0x3759/* enum: Physical network port ID (or m-port ID; same thing, for physical760 * network ports).761 */762#define TABLE_FIELD_ID_NETWORK_PORT_ID 0x4763/* enum: True if packet arrived via network port, false if it arrived via host.764 */765#define TABLE_FIELD_ID_IS_FROM_NETWORK 0x5766/* enum: Full virtual channel from capsule header. */767#define TABLE_FIELD_ID_CH_VC 0x6768/* enum: Low bits of virtual channel from capsule header. */769#define TABLE_FIELD_ID_CH_VC_LOW 0x7770/* enum: User mark value in metadata and packet prefix. */771#define TABLE_FIELD_ID_USER_MARK 0x8772/* enum: User flag value in metadata and packet prefix. */773#define TABLE_FIELD_ID_USER_FLAG 0x9774/* enum: Counter ID associated with a response. All-bits-1 is a null value to775 * suppress counting.776 */777#define TABLE_FIELD_ID_COUNTER_ID 0xa778/* enum: Discriminator which may be set by plugins in some lookup keys; this779 * allows plugins to make a reinterpretation of packet fields in these keys780 * without clashing with the normal interpretation.781 */782#define TABLE_FIELD_ID_DISCRIM 0xb783/* enum: Destination MAC address. The mapping from bytes in a frame to the784 * 48-bit value for this field is in network order, i.e. a MAC address of785 * AA:BB:CC:DD:EE:FF becomes a 48-bit value of 0xAABBCCDDEEFF.786 */787#define TABLE_FIELD_ID_DST_MAC 0x14788/* enum: Source MAC address (see notes for DST_MAC). */789#define TABLE_FIELD_ID_SRC_MAC 0x15790/* enum: Outer VLAN tag TPID, compressed to an enumeration. */791#define TABLE_FIELD_ID_OVLAN_TPID_COMPRESSED 0x16792/* enum: Full outer VLAN tag TCI (16 bits). */793#define TABLE_FIELD_ID_OVLAN 0x17794/* enum: Outer VLAN ID (least significant 12 bits of full 16-bit TCI) only. */795#define TABLE_FIELD_ID_OVLAN_VID 0x18796/* enum: Inner VLAN tag TPID, compressed to an enumeration. */797#define TABLE_FIELD_ID_IVLAN_TPID_COMPRESSED 0x19798/* enum: Full inner VLAN tag TCI (16 bits). */799#define TABLE_FIELD_ID_IVLAN 0x1a800/* enum: Inner VLAN ID (least significant 12 bits of full 16-bit TCI) only. */801#define TABLE_FIELD_ID_IVLAN_VID 0x1b802/* enum: Ethertype. */803#define TABLE_FIELD_ID_ETHER_TYPE 0x1c804/* enum: Source IP address, either IPv4 or IPv6. The mapping from bytes in a805 * frame to the 128-bit value for this field is in network order, with IPv4806 * addresses assumed to have 12 bytes of trailing zeroes. i.e. the IPv6 address807 * [2345::6789:ABCD] is 0x2345000000000000000000006789ABCD; the IPv4 address808 * 192.168.1.2 is 0xC0A80102000000000000000000000000.809 */810#define TABLE_FIELD_ID_SRC_IP 0x1d811/* enum: Destination IP address (see notes for SRC_IP). */812#define TABLE_FIELD_ID_DST_IP 0x1e813/* enum: IPv4 Type-of-Service or IPv6 Traffic Class field. */814#define TABLE_FIELD_ID_IP_TOS 0x1f815/* enum: IP Protocol. */816#define TABLE_FIELD_ID_IP_PROTO 0x20817/* enum: Layer 4 source port. */818#define TABLE_FIELD_ID_SRC_PORT 0x21819/* enum: Layer 4 destination port. */820#define TABLE_FIELD_ID_DST_PORT 0x22821/* enum: TCP flags. */822#define TABLE_FIELD_ID_TCP_FLAGS 0x23823/* enum: Virtual Network Identifier (VXLAN) or Virtual Session ID (NVGRE). */824#define TABLE_FIELD_ID_VNI 0x24825/* enum: True if packet has any tunnel encapsulation header. */826#define TABLE_FIELD_ID_HAS_ENCAP 0x32827/* enum: True if encap header has an outer VLAN tag. */828#define TABLE_FIELD_ID_HAS_ENC_OVLAN 0x33829/* enum: True if encap header has an inner VLAN tag. */830#define TABLE_FIELD_ID_HAS_ENC_IVLAN 0x34831/* enum: True if encap header is some sort of IP. */832#define TABLE_FIELD_ID_HAS_ENC_IP 0x35833/* enum: True if encap header is specifically IPv4. */834#define TABLE_FIELD_ID_HAS_ENC_IP4 0x36835/* enum: True if encap header is UDP. */836#define TABLE_FIELD_ID_HAS_ENC_UDP 0x37837/* enum: True if only/inner frame has an outer VLAN tag. */838#define TABLE_FIELD_ID_HAS_OVLAN 0x38839/* enum: True if only/inner frame has an inner VLAN tag. */840#define TABLE_FIELD_ID_HAS_IVLAN 0x39841/* enum: True if only/inner frame is some sort of IP. */842#define TABLE_FIELD_ID_HAS_IP 0x3a843/* enum: True if only/inner frame has a recognised L4 IP protocol (TCP or UDP).844 */845#define TABLE_FIELD_ID_HAS_L4 0x3b846/* enum: True if only/inner frame is an IP fragment. */847#define TABLE_FIELD_ID_IP_FRAG 0x3c848/* enum: True if only/inner frame is the first IP fragment (fragment offset 0).849 */850#define TABLE_FIELD_ID_IP_FIRST_FRAG 0x3d851/* enum: True if only/inner frame has an IP Time-To-Live of <= 1. (Note: the852 * implementation calls this "ip_ttl_is_one" but does in fact match packets853 * with TTL=0 - which we shouldn't be seeing! - as well.)854 */855#define TABLE_FIELD_ID_IP_TTL_LE_ONE 0x3e856/* enum: True if only/inner frame has any of TCP SYN, FIN or RST flags set. */857#define TABLE_FIELD_ID_TCP_INTERESTING_FLAGS 0x3f858/* enum: Plugin channel selection. */859#define TABLE_FIELD_ID_RDP_PL_CHAN 0x50860/* enum: Enable update of CH_ROUTE_RDP_C_PL route bit. */861#define TABLE_FIELD_ID_RDP_C_PL_EN 0x51862/* enum: New value of CH_ROUTE_RDP_C_PL route bit. */863#define TABLE_FIELD_ID_RDP_C_PL 0x52864/* enum: Enable update of CH_ROUTE_RDP_D_PL route bit. */865#define TABLE_FIELD_ID_RDP_D_PL_EN 0x53866/* enum: New value of CH_ROUTE_RDP_D_PL route bit. */867#define TABLE_FIELD_ID_RDP_D_PL 0x54868/* enum: Enable update of CH_ROUTE_RDP_OUT_HOST_CHAN route bit. */869#define TABLE_FIELD_ID_RDP_OUT_HOST_CHAN_EN 0x55870/* enum: New value of CH_ROUTE_RDP_OUT_HOST_CHAN route bit. */871#define TABLE_FIELD_ID_RDP_OUT_HOST_CHAN 0x56872/* enum: Recirculation ID for lookup sequences with two action rule lookups. */873#define TABLE_FIELD_ID_RECIRC_ID 0x64874/* enum: Domain ID passed to conntrack and action rule lookups. */875#define TABLE_FIELD_ID_DOMAIN 0x65876/* enum: Construction mode for encap_tunnel_id - see MAE_CT_VNI_MODE enum. */877#define TABLE_FIELD_ID_CT_VNI_MODE 0x66878/* enum: True to inhibit conntrack lookup if TCP SYN, FIN or RST flag is set.879 */880#define TABLE_FIELD_ID_CT_TCP_FLAGS_INHIBIT 0x67881/* enum: True to do conntrack lookups for IPv4 TCP packets. */882#define TABLE_FIELD_ID_DO_CT_IP4_TCP 0x68883/* enum: True to do conntrack lookups for IPv4 UDP packets. */884#define TABLE_FIELD_ID_DO_CT_IP4_UDP 0x69885/* enum: True to do conntrack lookups for IPv6 TCP packets. */886#define TABLE_FIELD_ID_DO_CT_IP6_TCP 0x6a887/* enum: True to do conntrack lookups for IPv6 UDP packets. */888#define TABLE_FIELD_ID_DO_CT_IP6_UDP 0x6b889/* enum: Outer rule identifier. */890#define TABLE_FIELD_ID_OUTER_RULE_ID 0x6c891/* enum: Encapsulation type - see MAE_MCDI_ENCAP_TYPE enum. */892#define TABLE_FIELD_ID_ENCAP_TYPE 0x6d893/* enum: Encap tunnel ID for conntrack lookups from VNI, VLAN tag(s), or 0,894 * depending on CT_VNI_MODE.895 */896#define TABLE_FIELD_ID_ENCAP_TUNNEL_ID 0x78897/* enum: A conntrack entry identifier, passed to plugins. */898#define TABLE_FIELD_ID_CT_ENTRY_ID 0x79899/* enum: Either source or destination NAT replacement port. */900#define TABLE_FIELD_ID_NAT_PORT 0x7a901/* enum: Either source or destination NAT replacement IPv4 address. Note that902 * this is specifically an IPv4 address (IPv6 is not supported for NAT), with903 * byte mapped to a 32-bit value in network order, i.e. the IPv4 address904 * 192.168.1.2 is the value 0xC0A80102.905 */906#define TABLE_FIELD_ID_NAT_IP 0x7b907/* enum: NAT direction: 0=>source, 1=>destination. */908#define TABLE_FIELD_ID_NAT_DIR 0x7c909/* enum: Conntrack mark value, passed to action rule lookup. Note that this is910 * not related to the "user mark" in the metadata / packet prefix.911 */912#define TABLE_FIELD_ID_CT_MARK 0x7d913/* enum: Private flags for conntrack, passed to action rule lookup. */914#define TABLE_FIELD_ID_CT_PRIV_FLAGS 0x7e915/* enum: True if the conntrack lookup resulted in a hit. */916#define TABLE_FIELD_ID_CT_HIT 0x7f917/* enum: True to suppress delivery when source and destination m-ports match.918 */919#define TABLE_FIELD_ID_SUPPRESS_SELF_DELIVERY 0x8c920/* enum: True to perform tunnel decapsulation. */921#define TABLE_FIELD_ID_DO_DECAP 0x8d922/* enum: True to copy outer frame DSCP to inner on decap. */923#define TABLE_FIELD_ID_DECAP_DSCP_COPY 0x8e924/* enum: True to map outer frame ECN to inner on decap, by RFC 6040 rules. */925#define TABLE_FIELD_ID_DECAP_ECN_RFC6040 0x8f926/* enum: True to replace DSCP field. */927#define TABLE_FIELD_ID_DO_REPLACE_DSCP 0x90928/* enum: True to replace ECN field. */929#define TABLE_FIELD_ID_DO_REPLACE_ECN 0x91930/* enum: True to decrement IP Time-To-Live. */931#define TABLE_FIELD_ID_DO_DECR_IP_TTL 0x92932/* enum: True to replace source MAC address. */933#define TABLE_FIELD_ID_DO_SRC_MAC 0x93934/* enum: True to replace destination MAC address. */935#define TABLE_FIELD_ID_DO_DST_MAC 0x94936/* enum: Number of VLAN tags to pop. Valid values are 0, 1, or 2. */937#define TABLE_FIELD_ID_DO_VLAN_POP 0x95938/* enum: Number of VLANs tags to push. Valid values are 0, 1, or 2. */939#define TABLE_FIELD_ID_DO_VLAN_PUSH 0x96940/* enum: True to count this packet. */941#define TABLE_FIELD_ID_DO_COUNT 0x97942/* enum: True to perform tunnel encapsulation. */943#define TABLE_FIELD_ID_DO_ENCAP 0x98944/* enum: True to copy inner frame DSCP to outer on encap. */945#define TABLE_FIELD_ID_ENCAP_DSCP_COPY 0x99946/* enum: True to copy inner frame ECN to outer on encap. */947#define TABLE_FIELD_ID_ENCAP_ECN_COPY 0x9a948/* enum: True to deliver the packet (otherwise it is dropped). */949#define TABLE_FIELD_ID_DO_DELIVER 0x9b950/* enum: True to set the user flag in the metadata. */951#define TABLE_FIELD_ID_DO_FLAG 0x9c952/* enum: True to update the user mark in the metadata. */953#define TABLE_FIELD_ID_DO_MARK 0x9d954/* enum: True to override the capsule virtual channel for network deliveries.955 */956#define TABLE_FIELD_ID_DO_SET_NET_CHAN 0x9e957/* enum: True to override the reported source m-port for host deliveries. */958#define TABLE_FIELD_ID_DO_SET_SRC_MPORT 0x9f959/* enum: Encap header ID for DO_ENCAP, indexing Encap_Hdr_Part1/2_Table. */960#define TABLE_FIELD_ID_ENCAP_HDR_ID 0xaa961/* enum: New DSCP value for DO_REPLACE_DSCP. */962#define TABLE_FIELD_ID_DSCP_VALUE 0xab963/* enum: If DO_REPLACE_ECN is set, the new value for the ECN field. If964 * DO_REPLACE_ECN is not set, ECN_CONTROL[0] and ECN_CONTROL[1] are set to965 * request remapping of ECT0 and ECT1 ECN codepoints respectively to CE.966 */967#define TABLE_FIELD_ID_ECN_CONTROL 0xac968/* enum: Source MAC ID for DO_SRC_MAC, indexing Replace_Src_MAC_Table. */969#define TABLE_FIELD_ID_SRC_MAC_ID 0xad970/* enum: Destination MAC ID for DO_DST_MAC, indexing Replace_Dst_MAC_Table. */971#define TABLE_FIELD_ID_DST_MAC_ID 0xae972/* enum: Parameter for either DO_SET_NET_CHAN (only bottom 6 bits used in this973 * case) or DO_SET_SRC_MPORT.974 */975#define TABLE_FIELD_ID_REPORTED_SRC_MPORT_OR_NET_CHAN 0xaf976/* enum: 64-byte chunk of added encapsulation header. */977#define TABLE_FIELD_ID_CHUNK64 0xb4978/* enum: 32-byte chunk of added encapsulation header. */979#define TABLE_FIELD_ID_CHUNK32 0xb5980/* enum: 16-byte chunk of added encapsulation header. */981#define TABLE_FIELD_ID_CHUNK16 0xb6982/* enum: 8-byte chunk of added encapsulation header. */983#define TABLE_FIELD_ID_CHUNK8 0xb7984/* enum: 4-byte chunk of added encapsulation header. */985#define TABLE_FIELD_ID_CHUNK4 0xb8986/* enum: 2-byte chunk of added encapsulation header. */987#define TABLE_FIELD_ID_CHUNK2 0xb9988/* enum: Added encapsulation header length in words. */989#define TABLE_FIELD_ID_HDR_LEN_W 0xba990/* enum: Static value for layer 2/3 LACP hash of the encapsulation header. */991#define TABLE_FIELD_ID_ENC_LACP_HASH_L23 0xbb992/* enum: Static value for layer 4 LACP hash of the encapsulation header. */993#define TABLE_FIELD_ID_ENC_LACP_HASH_L4 0xbc994/* enum: True to use the static ENC_LACP_HASH values for the encap header995 * instead of the calculated values for the inner frame when delivering a newly996 * encapsulated packet to a LAG m-port.997 */998#define TABLE_FIELD_ID_USE_ENC_LACP_HASHES 0xbd999/* enum: True to trigger conntrack from first action rule lookup (AR=>CT=>AR1000 * sequence).1001 */1002#define TABLE_FIELD_ID_DO_CT 0xc81003/* enum: True to perform NAT using parameters from conntrack lookup response.1004 */1005#define TABLE_FIELD_ID_DO_NAT 0xc91006/* enum: True to trigger recirculated action rule lookup (AR=>AR sequence). */1007#define TABLE_FIELD_ID_DO_RECIRC 0xca1008/* enum: Next action set payload ID for replay. The null value is all-1-bits.1009 */1010#define TABLE_FIELD_ID_NEXT_ACTION_SET_PAYLOAD 0xcb1011/* enum: Next action set row ID for replay. The null value is all-1-bits. */1012#define TABLE_FIELD_ID_NEXT_ACTION_SET_ROW 0xcc1013/* enum: Action set payload ID for additional delivery to management CPU. The1014 * null value is all-1-bits.1015 */1016#define TABLE_FIELD_ID_MC_ACTION_SET_PAYLOAD 0xcd1017/* enum: Action set row ID for additional delivery to management CPU. The null1018 * value is all-1-bits.1019 */1020#define TABLE_FIELD_ID_MC_ACTION_SET_ROW 0xce1021/* enum: True to include layer 4 in LACP hash on delivery to a LAG m-port. */1022#define TABLE_FIELD_ID_LACP_INC_L4 0xdc1023/* enum: True to request that LACP is performed by a plugin. */1024#define TABLE_FIELD_ID_LACP_PLUGIN 0xdd1025/* enum: LACP_Balance_Table base address divided by 64. */1026#define TABLE_FIELD_ID_BAL_TBL_BASE_DIV64 0xde1027/* enum: Length of balance table region: 0=>64, 1=>128, 2=>256. */1028#define TABLE_FIELD_ID_BAL_TBL_LEN_ID 0xdf1029/* enum: UDP port to match for UDP-based encapsulations; required to be 0 for1030 * other encapsulation types.1031 */1032#define TABLE_FIELD_ID_UDP_PORT 0xe61033/* enum: True to perform RSS based on outer fields rather than inner fields. */1034#define TABLE_FIELD_ID_RSS_ON_OUTER 0xe71035/* enum: True to perform steering table lookup on outer fields rather than1036 * inner fields.1037 */1038#define TABLE_FIELD_ID_STEER_ON_OUTER 0xe81039/* enum: Destination queue ID for host delivery. */1040#define TABLE_FIELD_ID_DST_QID 0xf01041/* enum: True to drop this packet. */1042#define TABLE_FIELD_ID_DROP 0xf11043/* enum: True to strip outer VLAN tag from this packet. */1044#define TABLE_FIELD_ID_VLAN_STRIP 0xf21045/* enum: True to override the user mark field with the supplied USER_MARK, or1046 * false to bitwise-OR the USER_MARK into it.1047 */1048#define TABLE_FIELD_ID_MARK_OVERRIDE 0xf31049/* enum: True to override the user flag field with the supplied USER_FLAG, or1050 * false to bitwise-OR the USER_FLAG into it.1051 */1052#define TABLE_FIELD_ID_FLAG_OVERRIDE 0xf41053/* enum: RSS context ID, indexing the RSS_Context_Table. */1054#define TABLE_FIELD_ID_RSS_CTX_ID 0xfa1055/* enum: True to enable RSS. */1056#define TABLE_FIELD_ID_RSS_EN 0xfb1057/* enum: Toeplitz hash key. */1058#define TABLE_FIELD_ID_KEY 0xfc1059/* enum: Key mode for IPv4 TCP packets - see TABLE_RSS_KEY_MODE enum. */1060#define TABLE_FIELD_ID_TCP_V4_KEY_MODE 0xfd1061/* enum: Key mode for IPv6 TCP packets - see TABLE_RSS_KEY_MODE enum. */1062#define TABLE_FIELD_ID_TCP_V6_KEY_MODE 0xfe1063/* enum: Key mode for IPv4 UDP packets - see TABLE_RSS_KEY_MODE enum. */1064#define TABLE_FIELD_ID_UDP_V4_KEY_MODE 0xff1065/* enum: Key mode for IPv6 UDP packets - see TABLE_RSS_KEY_MODE enum. */1066#define TABLE_FIELD_ID_UDP_V6_KEY_MODE 0x1001067/* enum: Key mode for other IPv4 packets - see TABLE_RSS_KEY_MODE enum. */1068#define TABLE_FIELD_ID_OTHER_V4_KEY_MODE 0x1011069/* enum: Key mode for other IPv6 packets - see TABLE_RSS_KEY_MODE enum. */1070#define TABLE_FIELD_ID_OTHER_V6_KEY_MODE 0x1021071/* enum: Spreading mode - 0=>indirection; 1=>even. */1072#define TABLE_FIELD_ID_SPREAD_MODE 0x1031073/* enum: For indirection spreading mode, the base address of a region within1074 * the Indirection_Table. For even spreading mode, the number of queues to1075 * spread across (only values 1-255 are valid for this mode).1076 */1077#define TABLE_FIELD_ID_INDIR_TBL_BASE 0x1041078/* enum: For indirection spreading mode, identifies the length of a region1079 * within the Indirection_Table, where length = 32 << len_id. Must be set to 01080 * for even spreading mode.1081 */1082#define TABLE_FIELD_ID_INDIR_TBL_LEN_ID 0x1051083/* enum: An offset to be applied to the base destination queue ID. */1084#define TABLE_FIELD_ID_INDIR_OFFSET 0x1061085 1086/* MCDI_EVENT structuredef: The structure of an MCDI_EVENT on Siena/EF10/EF1001087 * platforms1088 */1089#define MCDI_EVENT_LEN 81090#define MCDI_EVENT_CONT_LBN 321091#define MCDI_EVENT_CONT_WIDTH 11092#define MCDI_EVENT_LEVEL_LBN 331093#define MCDI_EVENT_LEVEL_WIDTH 31094/* enum: Info. */1095#define MCDI_EVENT_LEVEL_INFO 0x01096/* enum: Warning. */1097#define MCDI_EVENT_LEVEL_WARN 0x11098/* enum: Error. */1099#define MCDI_EVENT_LEVEL_ERR 0x21100/* enum: Fatal. */1101#define MCDI_EVENT_LEVEL_FATAL 0x31102#define MCDI_EVENT_DATA_OFST 01103#define MCDI_EVENT_DATA_LEN 41104#define MCDI_EVENT_CMDDONE_SEQ_OFST 01105#define MCDI_EVENT_CMDDONE_SEQ_LBN 01106#define MCDI_EVENT_CMDDONE_SEQ_WIDTH 81107#define MCDI_EVENT_CMDDONE_DATALEN_OFST 01108#define MCDI_EVENT_CMDDONE_DATALEN_LBN 81109#define MCDI_EVENT_CMDDONE_DATALEN_WIDTH 81110#define MCDI_EVENT_CMDDONE_ERRNO_OFST 01111#define MCDI_EVENT_CMDDONE_ERRNO_LBN 161112#define MCDI_EVENT_CMDDONE_ERRNO_WIDTH 81113#define MCDI_EVENT_LINKCHANGE_LP_CAP_OFST 01114#define MCDI_EVENT_LINKCHANGE_LP_CAP_LBN 01115#define MCDI_EVENT_LINKCHANGE_LP_CAP_WIDTH 161116#define MCDI_EVENT_LINKCHANGE_SPEED_OFST 01117#define MCDI_EVENT_LINKCHANGE_SPEED_LBN 161118#define MCDI_EVENT_LINKCHANGE_SPEED_WIDTH 41119/* enum: Link is down or link speed could not be determined */1120#define MCDI_EVENT_LINKCHANGE_SPEED_UNKNOWN 0x01121/* enum: 100Mbs */1122#define MCDI_EVENT_LINKCHANGE_SPEED_100M 0x11123/* enum: 1Gbs */1124#define MCDI_EVENT_LINKCHANGE_SPEED_1G 0x21125/* enum: 10Gbs */1126#define MCDI_EVENT_LINKCHANGE_SPEED_10G 0x31127/* enum: 40Gbs */1128#define MCDI_EVENT_LINKCHANGE_SPEED_40G 0x41129/* enum: 25Gbs */1130#define MCDI_EVENT_LINKCHANGE_SPEED_25G 0x51131/* enum: 50Gbs */1132#define MCDI_EVENT_LINKCHANGE_SPEED_50G 0x61133/* enum: 100Gbs */1134#define MCDI_EVENT_LINKCHANGE_SPEED_100G 0x71135#define MCDI_EVENT_LINKCHANGE_FCNTL_OFST 01136#define MCDI_EVENT_LINKCHANGE_FCNTL_LBN 201137#define MCDI_EVENT_LINKCHANGE_FCNTL_WIDTH 41138#define MCDI_EVENT_LINKCHANGE_LINK_FLAGS_OFST 01139#define MCDI_EVENT_LINKCHANGE_LINK_FLAGS_LBN 241140#define MCDI_EVENT_LINKCHANGE_LINK_FLAGS_WIDTH 81141#define MCDI_EVENT_SENSOREVT_MONITOR_OFST 01142#define MCDI_EVENT_SENSOREVT_MONITOR_LBN 01143#define MCDI_EVENT_SENSOREVT_MONITOR_WIDTH 81144#define MCDI_EVENT_SENSOREVT_STATE_OFST 01145#define MCDI_EVENT_SENSOREVT_STATE_LBN 81146#define MCDI_EVENT_SENSOREVT_STATE_WIDTH 81147#define MCDI_EVENT_SENSOREVT_VALUE_OFST 01148#define MCDI_EVENT_SENSOREVT_VALUE_LBN 161149#define MCDI_EVENT_SENSOREVT_VALUE_WIDTH 161150#define MCDI_EVENT_FWALERT_DATA_OFST 01151#define MCDI_EVENT_FWALERT_DATA_LBN 81152#define MCDI_EVENT_FWALERT_DATA_WIDTH 241153#define MCDI_EVENT_FWALERT_REASON_OFST 01154#define MCDI_EVENT_FWALERT_REASON_LBN 01155#define MCDI_EVENT_FWALERT_REASON_WIDTH 81156/* enum: SRAM Access. */1157#define MCDI_EVENT_FWALERT_REASON_SRAM_ACCESS 0x11158#define MCDI_EVENT_FLR_VF_OFST 01159#define MCDI_EVENT_FLR_VF_LBN 01160#define MCDI_EVENT_FLR_VF_WIDTH 81161#define MCDI_EVENT_TX_ERR_TXQ_OFST 01162#define MCDI_EVENT_TX_ERR_TXQ_LBN 01163#define MCDI_EVENT_TX_ERR_TXQ_WIDTH 121164#define MCDI_EVENT_TX_ERR_TYPE_OFST 01165#define MCDI_EVENT_TX_ERR_TYPE_LBN 121166#define MCDI_EVENT_TX_ERR_TYPE_WIDTH 41167/* enum: Descriptor loader reported failure. Specific to EF10-family NICs. */1168#define MCDI_EVENT_TX_ERR_DL_FAIL 0x11169/* enum: Descriptor ring empty and no EOP seen for packet. Specific to1170 * EF10-family NICs1171 */1172#define MCDI_EVENT_TX_ERR_NO_EOP 0x21173/* enum: Overlength packet. Specific to EF10-family NICs. */1174#define MCDI_EVENT_TX_ERR_2BIG 0x31175/* enum: Malformed option descriptor. Specific to EF10-family NICs. */1176#define MCDI_EVENT_TX_BAD_OPTDESC 0x51177/* enum: Option descriptor part way through a packet. Specific to EF10-family1178 * NICs.1179 */1180#define MCDI_EVENT_TX_OPT_IN_PKT 0x81181/* enum: DMA or PIO data access error. Specific to EF10-family NICs */1182#define MCDI_EVENT_TX_ERR_BAD_DMA_OR_PIO 0x91183#define MCDI_EVENT_TX_ERR_INFO_OFST 01184#define MCDI_EVENT_TX_ERR_INFO_LBN 161185#define MCDI_EVENT_TX_ERR_INFO_WIDTH 161186#define MCDI_EVENT_TX_FLUSH_TO_DRIVER_OFST 01187#define MCDI_EVENT_TX_FLUSH_TO_DRIVER_LBN 121188#define MCDI_EVENT_TX_FLUSH_TO_DRIVER_WIDTH 11189#define MCDI_EVENT_TX_FLUSH_TXQ_OFST 01190#define MCDI_EVENT_TX_FLUSH_TXQ_LBN 01191#define MCDI_EVENT_TX_FLUSH_TXQ_WIDTH 121192#define MCDI_EVENT_PTP_ERR_TYPE_OFST 01193#define MCDI_EVENT_PTP_ERR_TYPE_LBN 01194#define MCDI_EVENT_PTP_ERR_TYPE_WIDTH 81195/* enum: PLL lost lock */1196#define MCDI_EVENT_PTP_ERR_PLL_LOST 0x11197/* enum: Filter overflow (PDMA) */1198#define MCDI_EVENT_PTP_ERR_FILTER 0x21199/* enum: FIFO overflow (FPGA) */1200#define MCDI_EVENT_PTP_ERR_FIFO 0x31201/* enum: Merge queue overflow */1202#define MCDI_EVENT_PTP_ERR_QUEUE 0x41203#define MCDI_EVENT_AOE_ERR_TYPE_OFST 01204#define MCDI_EVENT_AOE_ERR_TYPE_LBN 01205#define MCDI_EVENT_AOE_ERR_TYPE_WIDTH 81206/* enum: AOE failed to load - no valid image? */1207#define MCDI_EVENT_AOE_NO_LOAD 0x11208/* enum: AOE FC reported an exception */1209#define MCDI_EVENT_AOE_FC_ASSERT 0x21210/* enum: AOE FC watchdogged */1211#define MCDI_EVENT_AOE_FC_WATCHDOG 0x31212/* enum: AOE FC failed to start */1213#define MCDI_EVENT_AOE_FC_NO_START 0x41214/* enum: Generic AOE fault - likely to have been reported via other means too1215 * but intended for use by aoex driver.1216 */1217#define MCDI_EVENT_AOE_FAULT 0x51218/* enum: Results of reprogramming the CPLD (status in AOE_ERR_DATA) */1219#define MCDI_EVENT_AOE_CPLD_REPROGRAMMED 0x61220/* enum: AOE loaded successfully */1221#define MCDI_EVENT_AOE_LOAD 0x71222/* enum: AOE DMA operation completed (LSB of HOST_HANDLE in AOE_ERR_DATA) */1223#define MCDI_EVENT_AOE_DMA 0x81224/* enum: AOE byteblaster connected/disconnected (Connection status in1225 * AOE_ERR_DATA)1226 */1227#define MCDI_EVENT_AOE_BYTEBLASTER 0x91228/* enum: DDR ECC status update */1229#define MCDI_EVENT_AOE_DDR_ECC_STATUS 0xa1230/* enum: PTP status update */1231#define MCDI_EVENT_AOE_PTP_STATUS 0xb1232/* enum: FPGA header incorrect */1233#define MCDI_EVENT_AOE_FPGA_LOAD_HEADER_ERR 0xc1234/* enum: FPGA Powered Off due to error in powering up FPGA */1235#define MCDI_EVENT_AOE_FPGA_POWER_OFF 0xd1236/* enum: AOE FPGA load failed due to MC to MUM communication failure */1237#define MCDI_EVENT_AOE_FPGA_LOAD_FAILED 0xe1238/* enum: Notify that invalid flash type detected */1239#define MCDI_EVENT_AOE_INVALID_FPGA_FLASH_TYPE 0xf1240/* enum: Notify that the attempt to run FPGA Controller firmware timedout */1241#define MCDI_EVENT_AOE_FC_RUN_TIMEDOUT 0x101242/* enum: Failure to probe one or more FPGA boot flash chips */1243#define MCDI_EVENT_AOE_FPGA_BOOT_FLASH_INVALID 0x111244/* enum: FPGA boot-flash contains an invalid image header */1245#define MCDI_EVENT_AOE_FPGA_BOOT_FLASH_HDR_INVALID 0x121246/* enum: Failed to program clocks required by the FPGA */1247#define MCDI_EVENT_AOE_FPGA_CLOCKS_PROGRAM_FAILED 0x131248/* enum: Notify that FPGA Controller is alive to serve MCDI requests */1249#define MCDI_EVENT_AOE_FC_RUNNING 0x141250#define MCDI_EVENT_AOE_ERR_DATA_OFST 01251#define MCDI_EVENT_AOE_ERR_DATA_LBN 81252#define MCDI_EVENT_AOE_ERR_DATA_WIDTH 81253#define MCDI_EVENT_AOE_ERR_FC_ASSERT_INFO_OFST 01254#define MCDI_EVENT_AOE_ERR_FC_ASSERT_INFO_LBN 81255#define MCDI_EVENT_AOE_ERR_FC_ASSERT_INFO_WIDTH 81256/* enum: FC Assert happened, but the register information is not available */1257#define MCDI_EVENT_AOE_ERR_FC_ASSERT_SEEN 0x01258/* enum: The register information for FC Assert is ready for readinng by driver1259 */1260#define MCDI_EVENT_AOE_ERR_FC_ASSERT_DATA_READY 0x11261#define MCDI_EVENT_AOE_ERR_CODE_FPGA_HEADER_VERIFY_FAILED_OFST 01262#define MCDI_EVENT_AOE_ERR_CODE_FPGA_HEADER_VERIFY_FAILED_LBN 81263#define MCDI_EVENT_AOE_ERR_CODE_FPGA_HEADER_VERIFY_FAILED_WIDTH 81264/* enum: Reading from NV failed */1265#define MCDI_EVENT_AOE_ERR_FPGA_HEADER_NV_READ_FAIL 0x01266/* enum: Invalid Magic Number if FPGA header */1267#define MCDI_EVENT_AOE_ERR_FPGA_HEADER_MAGIC_FAIL 0x11268/* enum: Invalid Silicon type detected in header */1269#define MCDI_EVENT_AOE_ERR_FPGA_HEADER_SILICON_TYPE 0x21270/* enum: Unsupported VRatio */1271#define MCDI_EVENT_AOE_ERR_FPGA_HEADER_VRATIO 0x31272/* enum: Unsupported DDR Type */1273#define MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_TYPE 0x41274/* enum: DDR Voltage out of supported range */1275#define MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_VOLTAGE 0x51276/* enum: Unsupported DDR speed */1277#define MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_SPEED 0x61278/* enum: Unsupported DDR size */1279#define MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_SIZE 0x71280/* enum: Unsupported DDR rank */1281#define MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_RANK 0x81282#define MCDI_EVENT_AOE_ERR_CODE_INVALID_FPGA_FLASH_TYPE_INFO_OFST 01283#define MCDI_EVENT_AOE_ERR_CODE_INVALID_FPGA_FLASH_TYPE_INFO_LBN 81284#define MCDI_EVENT_AOE_ERR_CODE_INVALID_FPGA_FLASH_TYPE_INFO_WIDTH 81285/* enum: Primary boot flash */1286#define MCDI_EVENT_AOE_FLASH_TYPE_BOOT_PRIMARY 0x01287/* enum: Secondary boot flash */1288#define MCDI_EVENT_AOE_FLASH_TYPE_BOOT_SECONDARY 0x11289#define MCDI_EVENT_AOE_ERR_CODE_FPGA_POWER_OFF_OFST 01290#define MCDI_EVENT_AOE_ERR_CODE_FPGA_POWER_OFF_LBN 81291#define MCDI_EVENT_AOE_ERR_CODE_FPGA_POWER_OFF_WIDTH 81292#define MCDI_EVENT_AOE_ERR_CODE_FPGA_LOAD_FAILED_OFST 01293#define MCDI_EVENT_AOE_ERR_CODE_FPGA_LOAD_FAILED_LBN 81294#define MCDI_EVENT_AOE_ERR_CODE_FPGA_LOAD_FAILED_WIDTH 81295#define MCDI_EVENT_RX_ERR_RXQ_OFST 01296#define MCDI_EVENT_RX_ERR_RXQ_LBN 01297#define MCDI_EVENT_RX_ERR_RXQ_WIDTH 121298#define MCDI_EVENT_RX_ERR_TYPE_OFST 01299#define MCDI_EVENT_RX_ERR_TYPE_LBN 121300#define MCDI_EVENT_RX_ERR_TYPE_WIDTH 41301#define MCDI_EVENT_RX_ERR_INFO_OFST 01302#define MCDI_EVENT_RX_ERR_INFO_LBN 161303#define MCDI_EVENT_RX_ERR_INFO_WIDTH 161304#define MCDI_EVENT_RX_FLUSH_TO_DRIVER_OFST 01305#define MCDI_EVENT_RX_FLUSH_TO_DRIVER_LBN 121306#define MCDI_EVENT_RX_FLUSH_TO_DRIVER_WIDTH 11307#define MCDI_EVENT_RX_FLUSH_RXQ_OFST 01308#define MCDI_EVENT_RX_FLUSH_RXQ_LBN 01309#define MCDI_EVENT_RX_FLUSH_RXQ_WIDTH 121310#define MCDI_EVENT_MC_REBOOT_COUNT_OFST 01311#define MCDI_EVENT_MC_REBOOT_COUNT_LBN 01312#define MCDI_EVENT_MC_REBOOT_COUNT_WIDTH 161313#define MCDI_EVENT_MUM_ERR_TYPE_OFST 01314#define MCDI_EVENT_MUM_ERR_TYPE_LBN 01315#define MCDI_EVENT_MUM_ERR_TYPE_WIDTH 81316/* enum: MUM failed to load - no valid image? */1317#define MCDI_EVENT_MUM_NO_LOAD 0x11318/* enum: MUM f/w reported an exception */1319#define MCDI_EVENT_MUM_ASSERT 0x21320/* enum: MUM not kicking watchdog */1321#define MCDI_EVENT_MUM_WATCHDOG 0x31322#define MCDI_EVENT_MUM_ERR_DATA_OFST 01323#define MCDI_EVENT_MUM_ERR_DATA_LBN 81324#define MCDI_EVENT_MUM_ERR_DATA_WIDTH 81325#define MCDI_EVENT_DBRET_SEQ_OFST 01326#define MCDI_EVENT_DBRET_SEQ_LBN 01327#define MCDI_EVENT_DBRET_SEQ_WIDTH 81328#define MCDI_EVENT_SUC_ERR_TYPE_OFST 01329#define MCDI_EVENT_SUC_ERR_TYPE_LBN 01330#define MCDI_EVENT_SUC_ERR_TYPE_WIDTH 81331/* enum: Corrupted or bad SUC application. */1332#define MCDI_EVENT_SUC_BAD_APP 0x11333/* enum: SUC application reported an assert. */1334#define MCDI_EVENT_SUC_ASSERT 0x21335/* enum: SUC application reported an exception. */1336#define MCDI_EVENT_SUC_EXCEPTION 0x31337/* enum: SUC watchdog timer expired. */1338#define MCDI_EVENT_SUC_WATCHDOG 0x41339#define MCDI_EVENT_SUC_ERR_ADDRESS_OFST 01340#define MCDI_EVENT_SUC_ERR_ADDRESS_LBN 81341#define MCDI_EVENT_SUC_ERR_ADDRESS_WIDTH 241342#define MCDI_EVENT_SUC_ERR_DATA_OFST 01343#define MCDI_EVENT_SUC_ERR_DATA_LBN 81344#define MCDI_EVENT_SUC_ERR_DATA_WIDTH 241345#define MCDI_EVENT_LINKCHANGE_V2_LP_CAP_OFST 01346#define MCDI_EVENT_LINKCHANGE_V2_LP_CAP_LBN 01347#define MCDI_EVENT_LINKCHANGE_V2_LP_CAP_WIDTH 241348#define MCDI_EVENT_LINKCHANGE_V2_SPEED_OFST 01349#define MCDI_EVENT_LINKCHANGE_V2_SPEED_LBN 241350#define MCDI_EVENT_LINKCHANGE_V2_SPEED_WIDTH 41351/* Enum values, see field(s): */1352/* MCDI_EVENT/LINKCHANGE_SPEED */1353#define MCDI_EVENT_LINKCHANGE_V2_FLAGS_LINK_UP_OFST 01354#define MCDI_EVENT_LINKCHANGE_V2_FLAGS_LINK_UP_LBN 281355#define MCDI_EVENT_LINKCHANGE_V2_FLAGS_LINK_UP_WIDTH 11356#define MCDI_EVENT_LINKCHANGE_V2_FCNTL_OFST 01357#define MCDI_EVENT_LINKCHANGE_V2_FCNTL_LBN 291358#define MCDI_EVENT_LINKCHANGE_V2_FCNTL_WIDTH 31359/* Enum values, see field(s): */1360/* MC_CMD_SET_MAC/MC_CMD_SET_MAC_IN/FCNTL */1361#define MCDI_EVENT_MODULECHANGE_LD_CAP_OFST 01362#define MCDI_EVENT_MODULECHANGE_LD_CAP_LBN 01363#define MCDI_EVENT_MODULECHANGE_LD_CAP_WIDTH 301364#define MCDI_EVENT_MODULECHANGE_SEQ_OFST 01365#define MCDI_EVENT_MODULECHANGE_SEQ_LBN 301366#define MCDI_EVENT_MODULECHANGE_SEQ_WIDTH 21367#define MCDI_EVENT_DATA_LBN 01368#define MCDI_EVENT_DATA_WIDTH 321369/* Alias for PTP_DATA. */1370#define MCDI_EVENT_SRC_LBN 361371#define MCDI_EVENT_SRC_WIDTH 81372/* Data associated with PTP events which doesn't fit into the main DATA field1373 */1374#define MCDI_EVENT_PTP_DATA_LBN 361375#define MCDI_EVENT_PTP_DATA_WIDTH 81376/* EF100 specific. Defined by QDMA. The phase bit, changes each time round the1377 * event ring1378 */1379#define MCDI_EVENT_EV_EVQ_PHASE_LBN 591380#define MCDI_EVENT_EV_EVQ_PHASE_WIDTH 11381#define MCDI_EVENT_EV_CODE_LBN 601382#define MCDI_EVENT_EV_CODE_WIDTH 41383#define MCDI_EVENT_CODE_LBN 441384#define MCDI_EVENT_CODE_WIDTH 81385/* enum: Event generated by host software */1386#define MCDI_EVENT_SW_EVENT 0x01387/* enum: Bad assert. */1388#define MCDI_EVENT_CODE_BADSSERT 0x11389/* enum: PM Notice. */1390#define MCDI_EVENT_CODE_PMNOTICE 0x21391/* enum: Command done. */1392#define MCDI_EVENT_CODE_CMDDONE 0x31393/* enum: Link change. */1394#define MCDI_EVENT_CODE_LINKCHANGE 0x41395/* enum: Sensor Event. */1396#define MCDI_EVENT_CODE_SENSOREVT 0x51397/* enum: Schedule error. */1398#define MCDI_EVENT_CODE_SCHEDERR 0x61399/* enum: Reboot. */1400#define MCDI_EVENT_CODE_REBOOT 0x71401/* enum: Mac stats DMA. */1402#define MCDI_EVENT_CODE_MAC_STATS_DMA 0x81403/* enum: Firmware alert. */1404#define MCDI_EVENT_CODE_FWALERT 0x91405/* enum: Function level reset. */1406#define MCDI_EVENT_CODE_FLR 0xa1407/* enum: Transmit error */1408#define MCDI_EVENT_CODE_TX_ERR 0xb1409/* enum: Tx flush has completed */1410#define MCDI_EVENT_CODE_TX_FLUSH 0xc1411/* enum: PTP packet received timestamp */1412#define MCDI_EVENT_CODE_PTP_RX 0xd1413/* enum: PTP NIC failure */1414#define MCDI_EVENT_CODE_PTP_FAULT 0xe1415/* enum: PTP PPS event */1416#define MCDI_EVENT_CODE_PTP_PPS 0xf1417/* enum: Rx flush has completed */1418#define MCDI_EVENT_CODE_RX_FLUSH 0x101419/* enum: Receive error */1420#define MCDI_EVENT_CODE_RX_ERR 0x111421/* enum: AOE fault */1422#define MCDI_EVENT_CODE_AOE 0x121423/* enum: Network port calibration failed (VCAL). */1424#define MCDI_EVENT_CODE_VCAL_FAIL 0x131425/* enum: HW PPS event */1426#define MCDI_EVENT_CODE_HW_PPS 0x141427/* enum: The MC has rebooted (huntington and later, siena uses CODE_REBOOT and1428 * a different format)1429 */1430#define MCDI_EVENT_CODE_MC_REBOOT 0x151431/* enum: the MC has detected a parity error */1432#define MCDI_EVENT_CODE_PAR_ERR 0x161433/* enum: the MC has detected a correctable error */1434#define MCDI_EVENT_CODE_ECC_CORR_ERR 0x171435/* enum: the MC has detected an uncorrectable error */1436#define MCDI_EVENT_CODE_ECC_FATAL_ERR 0x181437/* enum: The MC has entered offline BIST mode */1438#define MCDI_EVENT_CODE_MC_BIST 0x191439/* enum: PTP tick event providing current NIC time */1440#define MCDI_EVENT_CODE_PTP_TIME 0x1a1441/* enum: MUM fault */1442#define MCDI_EVENT_CODE_MUM 0x1b1443/* enum: notify the designated PF of a new authorization request */1444#define MCDI_EVENT_CODE_PROXY_REQUEST 0x1c1445/* enum: notify a function that awaits an authorization that its request has1446 * been processed and it may now resend the command1447 */1448#define MCDI_EVENT_CODE_PROXY_RESPONSE 0x1d1449/* enum: MCDI command accepted. New commands can be issued but this command is1450 * not done yet.1451 */1452#define MCDI_EVENT_CODE_DBRET 0x1e1453/* enum: The MC has detected a fault on the SUC */1454#define MCDI_EVENT_CODE_SUC 0x1f1455/* enum: Link change. This event is sent instead of LINKCHANGE if1456 * WANT_V2_LINKCHANGES was set on driver attach.1457 */1458#define MCDI_EVENT_CODE_LINKCHANGE_V2 0x201459/* enum: This event is sent if WANT_V2_LINKCHANGES was set on driver attach1460 * when the local device capabilities changes. This will usually correspond to1461 * a module change.1462 */1463#define MCDI_EVENT_CODE_MODULECHANGE 0x211464/* enum: Notification that the sensors have been added and/or removed from the1465 * sensor table. This event includes the new sensor table generation count, if1466 * this does not match the driver's local copy it is expected to call1467 * DYNAMIC_SENSORS_LIST to refresh it.1468 */1469#define MCDI_EVENT_CODE_DYNAMIC_SENSORS_CHANGE 0x221470/* enum: Notification that a sensor has changed state as a result of a reading1471 * crossing a threshold. This is sent as two events, the first event contains1472 * the handle and the sensor's state (in the SRC field), and the second1473 * contains the value.1474 */1475#define MCDI_EVENT_CODE_DYNAMIC_SENSORS_STATE_CHANGE 0x231476/* enum: Notification that a descriptor proxy function configuration has been1477 * pushed to "live" status (visible to host). SRC field contains the handle of1478 * the affected descriptor proxy function. DATA field contains the generation1479 * count of configuration set applied. See MC_CMD_DESC_PROXY_FUNC_CONFIG_SET /1480 * MC_CMD_DESC_PROXY_FUNC_CONFIG_COMMIT and SF-122927-TC for details.1481 */1482#define MCDI_EVENT_CODE_DESC_PROXY_FUNC_CONFIG_COMMITTED 0x241483/* enum: Notification that a descriptor proxy function has been reset. SRC1484 * field contains the handle of the affected descriptor proxy function. See1485 * SF-122927-TC for details.1486 */1487#define MCDI_EVENT_CODE_DESC_PROXY_FUNC_RESET 0x251488/* enum: Notification that a driver attached to a descriptor proxy function.1489 * SRC field contains the handle of the affected descriptor proxy function. For1490 * Virtio proxy functions this message consists of two MCDI events, where the1491 * first event's (CONT=1) DATA field carries negotiated virtio feature bits 01492 * to 31 and the second (CONT=0) carries bits 32 to 63. For EF100 proxy1493 * functions event length and meaning of DATA field is not yet defined. See1494 * SF-122927-TC for details.1495 */1496#define MCDI_EVENT_CODE_DESC_PROXY_FUNC_DRIVER_ATTACH 0x261497/* enum: Notification that the mport journal has changed since it was last read1498 * and updates can be read using the MC_CMD_MAE_MPORT_READ_JOURNAL command. The1499 * firmware may moderate the events so that an event is not sent for every1500 * change to the journal.1501 */1502#define MCDI_EVENT_CODE_MPORT_JOURNAL_CHANGE 0x271503/* enum: Artificial event generated by host and posted via MC for test1504 * purposes.1505 */1506#define MCDI_EVENT_CODE_TESTGEN 0xfa1507#define MCDI_EVENT_CMDDONE_DATA_OFST 01508#define MCDI_EVENT_CMDDONE_DATA_LEN 41509#define MCDI_EVENT_CMDDONE_DATA_LBN 01510#define MCDI_EVENT_CMDDONE_DATA_WIDTH 321511#define MCDI_EVENT_LINKCHANGE_DATA_OFST 01512#define MCDI_EVENT_LINKCHANGE_DATA_LEN 41513#define MCDI_EVENT_LINKCHANGE_DATA_LBN 01514#define MCDI_EVENT_LINKCHANGE_DATA_WIDTH 321515#define MCDI_EVENT_SENSOREVT_DATA_OFST 01516#define MCDI_EVENT_SENSOREVT_DATA_LEN 41517#define MCDI_EVENT_SENSOREVT_DATA_LBN 01518#define MCDI_EVENT_SENSOREVT_DATA_WIDTH 321519#define MCDI_EVENT_MAC_STATS_DMA_GENERATION_OFST 01520#define MCDI_EVENT_MAC_STATS_DMA_GENERATION_LEN 41521#define MCDI_EVENT_MAC_STATS_DMA_GENERATION_LBN 01522#define MCDI_EVENT_MAC_STATS_DMA_GENERATION_WIDTH 321523#define MCDI_EVENT_TX_ERR_DATA_OFST 01524#define MCDI_EVENT_TX_ERR_DATA_LEN 41525#define MCDI_EVENT_TX_ERR_DATA_LBN 01526#define MCDI_EVENT_TX_ERR_DATA_WIDTH 321527/* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the seconds field of1528 * timestamp1529 */1530#define MCDI_EVENT_PTP_SECONDS_OFST 01531#define MCDI_EVENT_PTP_SECONDS_LEN 41532#define MCDI_EVENT_PTP_SECONDS_LBN 01533#define MCDI_EVENT_PTP_SECONDS_WIDTH 321534/* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the major field of1535 * timestamp1536 */1537#define MCDI_EVENT_PTP_MAJOR_OFST 01538#define MCDI_EVENT_PTP_MAJOR_LEN 41539#define MCDI_EVENT_PTP_MAJOR_LBN 01540#define MCDI_EVENT_PTP_MAJOR_WIDTH 321541/* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the nanoseconds field1542 * of timestamp1543 */1544#define MCDI_EVENT_PTP_NANOSECONDS_OFST 01545#define MCDI_EVENT_PTP_NANOSECONDS_LEN 41546#define MCDI_EVENT_PTP_NANOSECONDS_LBN 01547#define MCDI_EVENT_PTP_NANOSECONDS_WIDTH 321548/* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the minor field of1549 * timestamp1550 */1551#define MCDI_EVENT_PTP_MINOR_OFST 01552#define MCDI_EVENT_PTP_MINOR_LEN 41553#define MCDI_EVENT_PTP_MINOR_LBN 01554#define MCDI_EVENT_PTP_MINOR_WIDTH 321555/* For CODE_PTP_RX events, the lowest four bytes of sourceUUID from PTP packet1556 */1557#define MCDI_EVENT_PTP_UUID_OFST 01558#define MCDI_EVENT_PTP_UUID_LEN 41559#define MCDI_EVENT_PTP_UUID_LBN 01560#define MCDI_EVENT_PTP_UUID_WIDTH 321561#define MCDI_EVENT_RX_ERR_DATA_OFST 01562#define MCDI_EVENT_RX_ERR_DATA_LEN 41563#define MCDI_EVENT_RX_ERR_DATA_LBN 01564#define MCDI_EVENT_RX_ERR_DATA_WIDTH 321565#define MCDI_EVENT_PAR_ERR_DATA_OFST 01566#define MCDI_EVENT_PAR_ERR_DATA_LEN 41567#define MCDI_EVENT_PAR_ERR_DATA_LBN 01568#define MCDI_EVENT_PAR_ERR_DATA_WIDTH 321569#define MCDI_EVENT_ECC_CORR_ERR_DATA_OFST 01570#define MCDI_EVENT_ECC_CORR_ERR_DATA_LEN 41571#define MCDI_EVENT_ECC_CORR_ERR_DATA_LBN 01572#define MCDI_EVENT_ECC_CORR_ERR_DATA_WIDTH 321573#define MCDI_EVENT_ECC_FATAL_ERR_DATA_OFST 01574#define MCDI_EVENT_ECC_FATAL_ERR_DATA_LEN 41575#define MCDI_EVENT_ECC_FATAL_ERR_DATA_LBN 01576#define MCDI_EVENT_ECC_FATAL_ERR_DATA_WIDTH 321577/* For CODE_PTP_TIME events, the major value of the PTP clock */1578#define MCDI_EVENT_PTP_TIME_MAJOR_OFST 01579#define MCDI_EVENT_PTP_TIME_MAJOR_LEN 41580#define MCDI_EVENT_PTP_TIME_MAJOR_LBN 01581#define MCDI_EVENT_PTP_TIME_MAJOR_WIDTH 321582/* For CODE_PTP_TIME events, bits 19-26 of the minor value of the PTP clock */1583#define MCDI_EVENT_PTP_TIME_MINOR_26_19_LBN 361584#define MCDI_EVENT_PTP_TIME_MINOR_26_19_WIDTH 81585/* For CODE_PTP_TIME events, most significant bits of the minor value of the1586 * PTP clock. This is a more generic equivalent of PTP_TIME_MINOR_26_19.1587 */1588#define MCDI_EVENT_PTP_TIME_MINOR_MS_8BITS_LBN 361589#define MCDI_EVENT_PTP_TIME_MINOR_MS_8BITS_WIDTH 81590/* For CODE_PTP_TIME events where report sync status is enabled, indicates1591 * whether the NIC clock has ever been set1592 */1593#define MCDI_EVENT_PTP_TIME_NIC_CLOCK_VALID_LBN 361594#define MCDI_EVENT_PTP_TIME_NIC_CLOCK_VALID_WIDTH 11595/* For CODE_PTP_TIME events where report sync status is enabled, indicates1596 * whether the NIC and System clocks are in sync1597 */1598#define MCDI_EVENT_PTP_TIME_HOST_NIC_IN_SYNC_LBN 371599#define MCDI_EVENT_PTP_TIME_HOST_NIC_IN_SYNC_WIDTH 11600/* For CODE_PTP_TIME events where report sync status is enabled, bits 21-26 of1601 * the minor value of the PTP clock1602 */1603#define MCDI_EVENT_PTP_TIME_MINOR_26_21_LBN 381604#define MCDI_EVENT_PTP_TIME_MINOR_26_21_WIDTH 61605/* For CODE_PTP_TIME events, most significant bits of the minor value of the1606 * PTP clock. This is a more generic equivalent of PTP_TIME_MINOR_26_21.1607 */1608#define MCDI_EVENT_PTP_TIME_MINOR_MS_6BITS_LBN 381609#define MCDI_EVENT_PTP_TIME_MINOR_MS_6BITS_WIDTH 61610#define MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_OFST 01611#define MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_LEN 41612#define MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_LBN 01613#define MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_WIDTH 321614#define MCDI_EVENT_PROXY_RESPONSE_HANDLE_OFST 01615#define MCDI_EVENT_PROXY_RESPONSE_HANDLE_LEN 41616#define MCDI_EVENT_PROXY_RESPONSE_HANDLE_LBN 01617#define MCDI_EVENT_PROXY_RESPONSE_HANDLE_WIDTH 321618/* Zero means that the request has been completed or authorized, and the driver1619 * should resend it. A non-zero value means that the authorization has been1620 * denied, and gives the reason. Typically it will be EPERM.1621 */1622#define MCDI_EVENT_PROXY_RESPONSE_RC_LBN 361623#define MCDI_EVENT_PROXY_RESPONSE_RC_WIDTH 81624#define MCDI_EVENT_DBRET_DATA_OFST 01625#define MCDI_EVENT_DBRET_DATA_LEN 41626#define MCDI_EVENT_DBRET_DATA_LBN 01627#define MCDI_EVENT_DBRET_DATA_WIDTH 321628#define MCDI_EVENT_LINKCHANGE_V2_DATA_OFST 01629#define MCDI_EVENT_LINKCHANGE_V2_DATA_LEN 41630#define MCDI_EVENT_LINKCHANGE_V2_DATA_LBN 01631#define MCDI_EVENT_LINKCHANGE_V2_DATA_WIDTH 321632#define MCDI_EVENT_MODULECHANGE_DATA_OFST 01633#define MCDI_EVENT_MODULECHANGE_DATA_LEN 41634#define MCDI_EVENT_MODULECHANGE_DATA_LBN 01635#define MCDI_EVENT_MODULECHANGE_DATA_WIDTH 321636/* The new generation count after a sensor has been added or deleted. */1637#define MCDI_EVENT_DYNAMIC_SENSORS_GENERATION_OFST 01638#define MCDI_EVENT_DYNAMIC_SENSORS_GENERATION_LEN 41639#define MCDI_EVENT_DYNAMIC_SENSORS_GENERATION_LBN 01640#define MCDI_EVENT_DYNAMIC_SENSORS_GENERATION_WIDTH 321641/* The handle of a dynamic sensor. */1642#define MCDI_EVENT_DYNAMIC_SENSORS_HANDLE_OFST 01643#define MCDI_EVENT_DYNAMIC_SENSORS_HANDLE_LEN 41644#define MCDI_EVENT_DYNAMIC_SENSORS_HANDLE_LBN 01645#define MCDI_EVENT_DYNAMIC_SENSORS_HANDLE_WIDTH 321646/* The current values of a sensor. */1647#define MCDI_EVENT_DYNAMIC_SENSORS_VALUE_OFST 01648#define MCDI_EVENT_DYNAMIC_SENSORS_VALUE_LEN 41649#define MCDI_EVENT_DYNAMIC_SENSORS_VALUE_LBN 01650#define MCDI_EVENT_DYNAMIC_SENSORS_VALUE_WIDTH 321651/* The current state of a sensor. */1652#define MCDI_EVENT_DYNAMIC_SENSORS_STATE_LBN 361653#define MCDI_EVENT_DYNAMIC_SENSORS_STATE_WIDTH 81654#define MCDI_EVENT_DESC_PROXY_DATA_OFST 01655#define MCDI_EVENT_DESC_PROXY_DATA_LEN 41656#define MCDI_EVENT_DESC_PROXY_DATA_LBN 01657#define MCDI_EVENT_DESC_PROXY_DATA_WIDTH 321658/* Generation count of applied configuration set */1659#define MCDI_EVENT_DESC_PROXY_GENERATION_OFST 01660#define MCDI_EVENT_DESC_PROXY_GENERATION_LEN 41661#define MCDI_EVENT_DESC_PROXY_GENERATION_LBN 01662#define MCDI_EVENT_DESC_PROXY_GENERATION_WIDTH 321663/* Virtio features negotiated with the host driver. First event (CONT=1)1664 * carries bits 0 to 31. Second event (CONT=0) carries bits 32 to 63.1665 */1666#define MCDI_EVENT_DESC_PROXY_VIRTIO_FEATURES_OFST 01667#define MCDI_EVENT_DESC_PROXY_VIRTIO_FEATURES_LEN 41668#define MCDI_EVENT_DESC_PROXY_VIRTIO_FEATURES_LBN 01669#define MCDI_EVENT_DESC_PROXY_VIRTIO_FEATURES_WIDTH 321670 1671/* FCDI_EVENT structuredef */1672#define FCDI_EVENT_LEN 81673#define FCDI_EVENT_CONT_LBN 321674#define FCDI_EVENT_CONT_WIDTH 11675#define FCDI_EVENT_LEVEL_LBN 331676#define FCDI_EVENT_LEVEL_WIDTH 31677/* enum: Info. */1678#define FCDI_EVENT_LEVEL_INFO 0x01679/* enum: Warning. */1680#define FCDI_EVENT_LEVEL_WARN 0x11681/* enum: Error. */1682#define FCDI_EVENT_LEVEL_ERR 0x21683/* enum: Fatal. */1684#define FCDI_EVENT_LEVEL_FATAL 0x31685#define FCDI_EVENT_DATA_OFST 01686#define FCDI_EVENT_DATA_LEN 41687#define FCDI_EVENT_LINK_STATE_STATUS_OFST 01688#define FCDI_EVENT_LINK_STATE_STATUS_LBN 01689#define FCDI_EVENT_LINK_STATE_STATUS_WIDTH 11690#define FCDI_EVENT_LINK_DOWN 0x0 /* enum */1691#define FCDI_EVENT_LINK_UP 0x1 /* enum */1692#define FCDI_EVENT_DATA_LBN 01693#define FCDI_EVENT_DATA_WIDTH 321694#define FCDI_EVENT_SRC_LBN 361695#define FCDI_EVENT_SRC_WIDTH 81696#define FCDI_EVENT_EV_CODE_LBN 601697#define FCDI_EVENT_EV_CODE_WIDTH 41698#define FCDI_EVENT_CODE_LBN 441699#define FCDI_EVENT_CODE_WIDTH 81700/* enum: The FC was rebooted. */1701#define FCDI_EVENT_CODE_REBOOT 0x11702/* enum: Bad assert. */1703#define FCDI_EVENT_CODE_ASSERT 0x21704/* enum: DDR3 test result. */1705#define FCDI_EVENT_CODE_DDR_TEST_RESULT 0x31706/* enum: Link status. */1707#define FCDI_EVENT_CODE_LINK_STATE 0x41708/* enum: A timed read is ready to be serviced. */1709#define FCDI_EVENT_CODE_TIMED_READ 0x51710/* enum: One or more PPS IN events */1711#define FCDI_EVENT_CODE_PPS_IN 0x61712/* enum: Tick event from PTP clock */1713#define FCDI_EVENT_CODE_PTP_TICK 0x71714/* enum: ECC error counters */1715#define FCDI_EVENT_CODE_DDR_ECC_STATUS 0x81716/* enum: Current status of PTP */1717#define FCDI_EVENT_CODE_PTP_STATUS 0x91718/* enum: Port id config to map MC-FC port idx */1719#define FCDI_EVENT_CODE_PORT_CONFIG 0xa1720/* enum: Boot result or error code */1721#define FCDI_EVENT_CODE_BOOT_RESULT 0xb1722#define FCDI_EVENT_REBOOT_SRC_LBN 361723#define FCDI_EVENT_REBOOT_SRC_WIDTH 81724#define FCDI_EVENT_REBOOT_FC_FW 0x0 /* enum */1725#define FCDI_EVENT_REBOOT_FC_BOOTLOADER 0x1 /* enum */1726#define FCDI_EVENT_ASSERT_INSTR_ADDRESS_OFST 01727#define FCDI_EVENT_ASSERT_INSTR_ADDRESS_LEN 41728#define FCDI_EVENT_ASSERT_INSTR_ADDRESS_LBN 01729#define FCDI_EVENT_ASSERT_INSTR_ADDRESS_WIDTH 321730#define FCDI_EVENT_ASSERT_TYPE_LBN 361731#define FCDI_EVENT_ASSERT_TYPE_WIDTH 81732#define FCDI_EVENT_DDR_TEST_RESULT_STATUS_CODE_LBN 361733#define FCDI_EVENT_DDR_TEST_RESULT_STATUS_CODE_WIDTH 81734#define FCDI_EVENT_DDR_TEST_RESULT_RESULT_OFST 01735#define FCDI_EVENT_DDR_TEST_RESULT_RESULT_LEN 41736#define FCDI_EVENT_DDR_TEST_RESULT_RESULT_LBN 01737#define FCDI_EVENT_DDR_TEST_RESULT_RESULT_WIDTH 321738#define FCDI_EVENT_LINK_STATE_DATA_OFST 01739#define FCDI_EVENT_LINK_STATE_DATA_LEN 41740#define FCDI_EVENT_LINK_STATE_DATA_LBN 01741#define FCDI_EVENT_LINK_STATE_DATA_WIDTH 321742#define FCDI_EVENT_PTP_STATE_OFST 01743#define FCDI_EVENT_PTP_STATE_LEN 41744#define FCDI_EVENT_PTP_UNDEFINED 0x0 /* enum */1745#define FCDI_EVENT_PTP_SETUP_FAILED 0x1 /* enum */1746#define FCDI_EVENT_PTP_OPERATIONAL 0x2 /* enum */1747#define FCDI_EVENT_PTP_STATE_LBN 01748#define FCDI_EVENT_PTP_STATE_WIDTH 321749#define FCDI_EVENT_DDR_ECC_STATUS_BANK_ID_LBN 361750#define FCDI_EVENT_DDR_ECC_STATUS_BANK_ID_WIDTH 81751#define FCDI_EVENT_DDR_ECC_STATUS_STATUS_OFST 01752#define FCDI_EVENT_DDR_ECC_STATUS_STATUS_LEN 41753#define FCDI_EVENT_DDR_ECC_STATUS_STATUS_LBN 01754#define FCDI_EVENT_DDR_ECC_STATUS_STATUS_WIDTH 321755/* Index of MC port being referred to */1756#define FCDI_EVENT_PORT_CONFIG_SRC_LBN 361757#define FCDI_EVENT_PORT_CONFIG_SRC_WIDTH 81758/* FC Port index that matches the MC port index in SRC */1759#define FCDI_EVENT_PORT_CONFIG_DATA_OFST 01760#define FCDI_EVENT_PORT_CONFIG_DATA_LEN 41761#define FCDI_EVENT_PORT_CONFIG_DATA_LBN 01762#define FCDI_EVENT_PORT_CONFIG_DATA_WIDTH 321763#define FCDI_EVENT_BOOT_RESULT_OFST 01764#define FCDI_EVENT_BOOT_RESULT_LEN 41765/* Enum values, see field(s): */1766/* MC_CMD_AOE/MC_CMD_AOE_OUT_INFO/FC_BOOT_RESULT */1767#define FCDI_EVENT_BOOT_RESULT_LBN 01768#define FCDI_EVENT_BOOT_RESULT_WIDTH 321769 1770/* FCDI_EXTENDED_EVENT_PPS structuredef: Extended FCDI event to send PPS events1771 * to the MC. Note that this structure | is overlayed over a normal FCDI event1772 * such that bits 32-63 containing | event code, level, source etc remain the1773 * same. In this case the data | field of the header is defined to be the1774 * number of timestamps1775 */1776#define FCDI_EXTENDED_EVENT_PPS_LENMIN 161777#define FCDI_EXTENDED_EVENT_PPS_LENMAX 2481778#define FCDI_EXTENDED_EVENT_PPS_LENMAX_MCDI2 10161779#define FCDI_EXTENDED_EVENT_PPS_LEN(num) (8+8*(num))1780#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_NUM(len) (((len)-8)/8)1781/* Number of timestamps following */1782#define FCDI_EXTENDED_EVENT_PPS_COUNT_OFST 01783#define FCDI_EXTENDED_EVENT_PPS_COUNT_LEN 41784#define FCDI_EXTENDED_EVENT_PPS_COUNT_LBN 01785#define FCDI_EXTENDED_EVENT_PPS_COUNT_WIDTH 321786/* Seconds field of a timestamp record */1787#define FCDI_EXTENDED_EVENT_PPS_SECONDS_OFST 81788#define FCDI_EXTENDED_EVENT_PPS_SECONDS_LEN 41789#define FCDI_EXTENDED_EVENT_PPS_SECONDS_LBN 641790#define FCDI_EXTENDED_EVENT_PPS_SECONDS_WIDTH 321791/* Nanoseconds field of a timestamp record */1792#define FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_OFST 121793#define FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_LEN 41794#define FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_LBN 961795#define FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_WIDTH 321796/* Timestamp records comprising the event */1797#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_OFST 81798#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LEN 81799#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LO_OFST 81800#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LO_LEN 41801#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LO_LBN 641802#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LO_WIDTH 321803#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_HI_OFST 121804#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_HI_LEN 41805#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_HI_LBN 961806#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_HI_WIDTH 321807#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_MINNUM 11808#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_MAXNUM 301809#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_MAXNUM_MCDI2 1261810#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LBN 641811#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_WIDTH 641812 1813/* MUM_EVENT structuredef */1814#define MUM_EVENT_LEN 81815#define MUM_EVENT_CONT_LBN 321816#define MUM_EVENT_CONT_WIDTH 11817#define MUM_EVENT_LEVEL_LBN 331818#define MUM_EVENT_LEVEL_WIDTH 31819/* enum: Info. */1820#define MUM_EVENT_LEVEL_INFO 0x01821/* enum: Warning. */1822#define MUM_EVENT_LEVEL_WARN 0x11823/* enum: Error. */1824#define MUM_EVENT_LEVEL_ERR 0x21825/* enum: Fatal. */1826#define MUM_EVENT_LEVEL_FATAL 0x31827#define MUM_EVENT_DATA_OFST 01828#define MUM_EVENT_DATA_LEN 41829#define MUM_EVENT_SENSOR_ID_OFST 01830#define MUM_EVENT_SENSOR_ID_LBN 01831#define MUM_EVENT_SENSOR_ID_WIDTH 81832/* Enum values, see field(s): */1833/* MC_CMD_SENSOR_INFO/MC_CMD_SENSOR_INFO_OUT/MASK */1834#define MUM_EVENT_SENSOR_STATE_OFST 01835#define MUM_EVENT_SENSOR_STATE_LBN 81836#define MUM_EVENT_SENSOR_STATE_WIDTH 81837#define MUM_EVENT_PORT_PHY_READY_OFST 01838#define MUM_EVENT_PORT_PHY_READY_LBN 01839#define MUM_EVENT_PORT_PHY_READY_WIDTH 11840#define MUM_EVENT_PORT_PHY_LINK_UP_OFST 01841#define MUM_EVENT_PORT_PHY_LINK_UP_LBN 11842#define MUM_EVENT_PORT_PHY_LINK_UP_WIDTH 11843#define MUM_EVENT_PORT_PHY_TX_LOL_OFST 01844#define MUM_EVENT_PORT_PHY_TX_LOL_LBN 21845#define MUM_EVENT_PORT_PHY_TX_LOL_WIDTH 11846#define MUM_EVENT_PORT_PHY_RX_LOL_OFST 01847#define MUM_EVENT_PORT_PHY_RX_LOL_LBN 31848#define MUM_EVENT_PORT_PHY_RX_LOL_WIDTH 11849#define MUM_EVENT_PORT_PHY_TX_LOS_OFST 01850#define MUM_EVENT_PORT_PHY_TX_LOS_LBN 41851#define MUM_EVENT_PORT_PHY_TX_LOS_WIDTH 11852#define MUM_EVENT_PORT_PHY_RX_LOS_OFST 01853#define MUM_EVENT_PORT_PHY_RX_LOS_LBN 51854#define MUM_EVENT_PORT_PHY_RX_LOS_WIDTH 11855#define MUM_EVENT_PORT_PHY_TX_FAULT_OFST 01856#define MUM_EVENT_PORT_PHY_TX_FAULT_LBN 61857#define MUM_EVENT_PORT_PHY_TX_FAULT_WIDTH 11858#define MUM_EVENT_DATA_LBN 01859#define MUM_EVENT_DATA_WIDTH 321860#define MUM_EVENT_SRC_LBN 361861#define MUM_EVENT_SRC_WIDTH 81862#define MUM_EVENT_EV_CODE_LBN 601863#define MUM_EVENT_EV_CODE_WIDTH 41864#define MUM_EVENT_CODE_LBN 441865#define MUM_EVENT_CODE_WIDTH 81866/* enum: The MUM was rebooted. */1867#define MUM_EVENT_CODE_REBOOT 0x11868/* enum: Bad assert. */1869#define MUM_EVENT_CODE_ASSERT 0x21870/* enum: Sensor failure. */1871#define MUM_EVENT_CODE_SENSOR 0x31872/* enum: Link fault has been asserted, or has cleared. */1873#define MUM_EVENT_CODE_QSFP_LASI_INTERRUPT 0x41874#define MUM_EVENT_SENSOR_DATA_OFST 01875#define MUM_EVENT_SENSOR_DATA_LEN 41876#define MUM_EVENT_SENSOR_DATA_LBN 01877#define MUM_EVENT_SENSOR_DATA_WIDTH 321878#define MUM_EVENT_PORT_PHY_FLAGS_OFST 01879#define MUM_EVENT_PORT_PHY_FLAGS_LEN 41880#define MUM_EVENT_PORT_PHY_FLAGS_LBN 01881#define MUM_EVENT_PORT_PHY_FLAGS_WIDTH 321882#define MUM_EVENT_PORT_PHY_COPPER_LEN_OFST 01883#define MUM_EVENT_PORT_PHY_COPPER_LEN_LEN 41884#define MUM_EVENT_PORT_PHY_COPPER_LEN_LBN 01885#define MUM_EVENT_PORT_PHY_COPPER_LEN_WIDTH 321886#define MUM_EVENT_PORT_PHY_CAPS_OFST 01887#define MUM_EVENT_PORT_PHY_CAPS_LEN 41888#define MUM_EVENT_PORT_PHY_CAPS_LBN 01889#define MUM_EVENT_PORT_PHY_CAPS_WIDTH 321890#define MUM_EVENT_PORT_PHY_TECH_OFST 01891#define MUM_EVENT_PORT_PHY_TECH_LEN 41892#define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_UNKNOWN 0x0 /* enum */1893#define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_OPTICAL 0x1 /* enum */1894#define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_PASSIVE 0x2 /* enum */1895#define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_PASSIVE_EQUALIZED 0x3 /* enum */1896#define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_ACTIVE_LIMITING 0x4 /* enum */1897#define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_ACTIVE_LINEAR 0x5 /* enum */1898#define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_BASE_T 0x6 /* enum */1899#define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_LOOPBACK_PASSIVE 0x7 /* enum */1900#define MUM_EVENT_PORT_PHY_TECH_LBN 01901#define MUM_EVENT_PORT_PHY_TECH_WIDTH 321902#define MUM_EVENT_PORT_PHY_SRC_DATA_ID_LBN 361903#define MUM_EVENT_PORT_PHY_SRC_DATA_ID_WIDTH 41904#define MUM_EVENT_PORT_PHY_SRC_DATA_ID_FLAGS 0x0 /* enum */1905#define MUM_EVENT_PORT_PHY_SRC_DATA_ID_COPPER_LEN 0x1 /* enum */1906#define MUM_EVENT_PORT_PHY_SRC_DATA_ID_CAPS 0x2 /* enum */1907#define MUM_EVENT_PORT_PHY_SRC_DATA_ID_TECH 0x3 /* enum */1908#define MUM_EVENT_PORT_PHY_SRC_DATA_ID_MAX 0x4 /* enum */1909#define MUM_EVENT_PORT_PHY_SRC_PORT_NO_LBN 401910#define MUM_EVENT_PORT_PHY_SRC_PORT_NO_WIDTH 41911 1912 1913/***********************************/1914/* MC_CMD_READ321915 * Read multiple 32byte words from MC memory. Note - this command really1916 * belongs to INSECURE category but is required by shmboot. The command handler1917 * has additional checks to reject insecure calls.1918 */1919#define MC_CMD_READ32 0x11920#undef MC_CMD_0x1_PRIVILEGE_CTG1921 1922#define MC_CMD_0x1_PRIVILEGE_CTG SRIOV_CTG_ADMIN1923 1924/* MC_CMD_READ32_IN msgrequest */1925#define MC_CMD_READ32_IN_LEN 81926#define MC_CMD_READ32_IN_ADDR_OFST 01927#define MC_CMD_READ32_IN_ADDR_LEN 41928#define MC_CMD_READ32_IN_NUMWORDS_OFST 41929#define MC_CMD_READ32_IN_NUMWORDS_LEN 41930 1931/* MC_CMD_READ32_OUT msgresponse */1932#define MC_CMD_READ32_OUT_LENMIN 41933#define MC_CMD_READ32_OUT_LENMAX 2521934#define MC_CMD_READ32_OUT_LENMAX_MCDI2 10201935#define MC_CMD_READ32_OUT_LEN(num) (0+4*(num))1936#define MC_CMD_READ32_OUT_BUFFER_NUM(len) (((len)-0)/4)1937#define MC_CMD_READ32_OUT_BUFFER_OFST 01938#define MC_CMD_READ32_OUT_BUFFER_LEN 41939#define MC_CMD_READ32_OUT_BUFFER_MINNUM 11940#define MC_CMD_READ32_OUT_BUFFER_MAXNUM 631941#define MC_CMD_READ32_OUT_BUFFER_MAXNUM_MCDI2 2551942 1943 1944/***********************************/1945/* MC_CMD_WRITE321946 * Write multiple 32byte words to MC memory.1947 */1948#define MC_CMD_WRITE32 0x21949#undef MC_CMD_0x2_PRIVILEGE_CTG1950 1951#define MC_CMD_0x2_PRIVILEGE_CTG SRIOV_CTG_INSECURE1952 1953/* MC_CMD_WRITE32_IN msgrequest */1954#define MC_CMD_WRITE32_IN_LENMIN 81955#define MC_CMD_WRITE32_IN_LENMAX 2521956#define MC_CMD_WRITE32_IN_LENMAX_MCDI2 10201957#define MC_CMD_WRITE32_IN_LEN(num) (4+4*(num))1958#define MC_CMD_WRITE32_IN_BUFFER_NUM(len) (((len)-4)/4)1959#define MC_CMD_WRITE32_IN_ADDR_OFST 01960#define MC_CMD_WRITE32_IN_ADDR_LEN 41961#define MC_CMD_WRITE32_IN_BUFFER_OFST 41962#define MC_CMD_WRITE32_IN_BUFFER_LEN 41963#define MC_CMD_WRITE32_IN_BUFFER_MINNUM 11964#define MC_CMD_WRITE32_IN_BUFFER_MAXNUM 621965#define MC_CMD_WRITE32_IN_BUFFER_MAXNUM_MCDI2 2541966 1967/* MC_CMD_WRITE32_OUT msgresponse */1968#define MC_CMD_WRITE32_OUT_LEN 01969 1970 1971/***********************************/1972/* MC_CMD_COPYCODE1973 * Copy MC code between two locations and jump. Note - this command really1974 * belongs to INSECURE category but is required by shmboot. The command handler1975 * has additional checks to reject insecure calls.1976 */1977#define MC_CMD_COPYCODE 0x31978#undef MC_CMD_0x3_PRIVILEGE_CTG1979 1980#define MC_CMD_0x3_PRIVILEGE_CTG SRIOV_CTG_ADMIN1981 1982/* MC_CMD_COPYCODE_IN msgrequest */1983#define MC_CMD_COPYCODE_IN_LEN 161984/* Source address1985 *1986 * The main image should be entered via a copy of a single word from and to a1987 * magic address, which controls various aspects of the boot. The magic address1988 * is a bitfield, with each bit as documented below.1989 */1990#define MC_CMD_COPYCODE_IN_SRC_ADDR_OFST 01991#define MC_CMD_COPYCODE_IN_SRC_ADDR_LEN 41992/* enum: Deprecated; equivalent to setting BOOT_MAGIC_PRESENT (see below) */1993#define MC_CMD_COPYCODE_HUNT_NO_MAGIC_ADDR 0x100001994/* enum: Deprecated; equivalent to setting BOOT_MAGIC_PRESENT and1995 * BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED (see below)1996 */1997#define MC_CMD_COPYCODE_HUNT_NO_DATAPATH_MAGIC_ADDR 0x1d0d01998/* enum: Deprecated; equivalent to setting BOOT_MAGIC_PRESENT,1999 * BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED and BOOT_MAGIC_IGNORE_CONFIG (see2000 * below)2001 */2002#define MC_CMD_COPYCODE_HUNT_IGNORE_CONFIG_MAGIC_ADDR 0x1badc2003#define MC_CMD_COPYCODE_IN_BOOT_MAGIC_PRESENT_OFST 02004#define MC_CMD_COPYCODE_IN_BOOT_MAGIC_PRESENT_LBN 172005#define MC_CMD_COPYCODE_IN_BOOT_MAGIC_PRESENT_WIDTH 12006#define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED_OFST 02007#define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED_LBN 22008#define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED_WIDTH 12009#define MC_CMD_COPYCODE_IN_BOOT_MAGIC_IGNORE_CONFIG_OFST 02010#define MC_CMD_COPYCODE_IN_BOOT_MAGIC_IGNORE_CONFIG_LBN 32011#define MC_CMD_COPYCODE_IN_BOOT_MAGIC_IGNORE_CONFIG_WIDTH 12012#define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SKIP_BOOT_ICORE_SYNC_OFST 02013#define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SKIP_BOOT_ICORE_SYNC_LBN 42014#define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SKIP_BOOT_ICORE_SYNC_WIDTH 12015#define MC_CMD_COPYCODE_IN_BOOT_MAGIC_FORCE_STANDALONE_OFST 02016#define MC_CMD_COPYCODE_IN_BOOT_MAGIC_FORCE_STANDALONE_LBN 52017#define MC_CMD_COPYCODE_IN_BOOT_MAGIC_FORCE_STANDALONE_WIDTH 12018#define MC_CMD_COPYCODE_IN_BOOT_MAGIC_DISABLE_XIP_OFST 02019#define MC_CMD_COPYCODE_IN_BOOT_MAGIC_DISABLE_XIP_LBN 62020#define MC_CMD_COPYCODE_IN_BOOT_MAGIC_DISABLE_XIP_WIDTH 12021/* Destination address */2022#define MC_CMD_COPYCODE_IN_DEST_ADDR_OFST 42023#define MC_CMD_COPYCODE_IN_DEST_ADDR_LEN 42024#define MC_CMD_COPYCODE_IN_NUMWORDS_OFST 82025#define MC_CMD_COPYCODE_IN_NUMWORDS_LEN 42026/* Address of where to jump after copy. */2027#define MC_CMD_COPYCODE_IN_JUMP_OFST 122028#define MC_CMD_COPYCODE_IN_JUMP_LEN 42029/* enum: Control should return to the caller rather than jumping */2030#define MC_CMD_COPYCODE_JUMP_NONE 0x12031 2032/* MC_CMD_COPYCODE_OUT msgresponse */2033#define MC_CMD_COPYCODE_OUT_LEN 02034 2035 2036/***********************************/2037/* MC_CMD_SET_FUNC2038 * Select function for function-specific commands.2039 */2040#define MC_CMD_SET_FUNC 0x42041#undef MC_CMD_0x4_PRIVILEGE_CTG2042 2043#define MC_CMD_0x4_PRIVILEGE_CTG SRIOV_CTG_INSECURE2044 2045/* MC_CMD_SET_FUNC_IN msgrequest */2046#define MC_CMD_SET_FUNC_IN_LEN 42047/* Set function */2048#define MC_CMD_SET_FUNC_IN_FUNC_OFST 02049#define MC_CMD_SET_FUNC_IN_FUNC_LEN 42050 2051/* MC_CMD_SET_FUNC_OUT msgresponse */2052#define MC_CMD_SET_FUNC_OUT_LEN 02053 2054 2055/***********************************/2056/* MC_CMD_GET_BOOT_STATUS2057 * Get the instruction address from which the MC booted.2058 */2059#define MC_CMD_GET_BOOT_STATUS 0x52060#undef MC_CMD_0x5_PRIVILEGE_CTG2061 2062#define MC_CMD_0x5_PRIVILEGE_CTG SRIOV_CTG_GENERAL2063 2064/* MC_CMD_GET_BOOT_STATUS_IN msgrequest */2065#define MC_CMD_GET_BOOT_STATUS_IN_LEN 02066 2067/* MC_CMD_GET_BOOT_STATUS_OUT msgresponse */2068#define MC_CMD_GET_BOOT_STATUS_OUT_LEN 82069/* ?? */2070#define MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_OFST 02071#define MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_LEN 42072/* enum: indicates that the MC wasn't flash booted */2073#define MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_NULL 0xdeadbeef2074#define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_OFST 42075#define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_LEN 42076#define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_WATCHDOG_OFST 42077#define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_WATCHDOG_LBN 02078#define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_WATCHDOG_WIDTH 12079#define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_PRIMARY_OFST 42080#define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_PRIMARY_LBN 12081#define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_PRIMARY_WIDTH 12082#define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_BACKUP_OFST 42083#define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_BACKUP_LBN 22084#define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_BACKUP_WIDTH 12085 2086 2087/***********************************/2088/* MC_CMD_GET_ASSERTS2089 * Get (and optionally clear) the current assertion status. Only2090 * OUT.GLOBAL_FLAGS is guaranteed to exist in the completion payload. The other2091 * fields will only be present if OUT.GLOBAL_FLAGS != NO_FAILS2092 */2093#define MC_CMD_GET_ASSERTS 0x62094#undef MC_CMD_0x6_PRIVILEGE_CTG2095 2096#define MC_CMD_0x6_PRIVILEGE_CTG SRIOV_CTG_ADMIN2097 2098/* MC_CMD_GET_ASSERTS_IN msgrequest */2099#define MC_CMD_GET_ASSERTS_IN_LEN 42100/* Set to clear assertion */2101#define MC_CMD_GET_ASSERTS_IN_CLEAR_OFST 02102#define MC_CMD_GET_ASSERTS_IN_CLEAR_LEN 42103 2104/* MC_CMD_GET_ASSERTS_OUT msgresponse */2105#define MC_CMD_GET_ASSERTS_OUT_LEN 1402106/* Assertion status flag. */2107#define MC_CMD_GET_ASSERTS_OUT_GLOBAL_FLAGS_OFST 02108#define MC_CMD_GET_ASSERTS_OUT_GLOBAL_FLAGS_LEN 42109/* enum: No assertions have failed. */2110#define MC_CMD_GET_ASSERTS_FLAGS_NO_FAILS 0x12111/* enum: A system-level assertion has failed. */2112#define MC_CMD_GET_ASSERTS_FLAGS_SYS_FAIL 0x22113/* enum: A thread-level assertion has failed. */2114#define MC_CMD_GET_ASSERTS_FLAGS_THR_FAIL 0x32115/* enum: The system was reset by the watchdog. */2116#define MC_CMD_GET_ASSERTS_FLAGS_WDOG_FIRED 0x42117/* enum: An illegal address trap stopped the system (huntington and later) */2118#define MC_CMD_GET_ASSERTS_FLAGS_ADDR_TRAP 0x52119/* Failing PC value */2120#define MC_CMD_GET_ASSERTS_OUT_SAVED_PC_OFFS_OFST 42121#define MC_CMD_GET_ASSERTS_OUT_SAVED_PC_OFFS_LEN 42122/* Saved GP regs */2123#define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_OFST 82124#define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_LEN 42125#define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_NUM 312126/* enum: A magic value hinting that the value in this register at the time of2127 * the failure has likely been lost.2128 */2129#define MC_CMD_GET_ASSERTS_REG_NO_DATA 0xda7a10572130/* Failing thread address */2131#define MC_CMD_GET_ASSERTS_OUT_THREAD_OFFS_OFST 1322132#define MC_CMD_GET_ASSERTS_OUT_THREAD_OFFS_LEN 42133#define MC_CMD_GET_ASSERTS_OUT_RESERVED_OFST 1362134#define MC_CMD_GET_ASSERTS_OUT_RESERVED_LEN 42135 2136/* MC_CMD_GET_ASSERTS_OUT_V2 msgresponse: Extended response for MicroBlaze CPUs2137 * found on Riverhead designs2138 */2139#define MC_CMD_GET_ASSERTS_OUT_V2_LEN 2402140/* Assertion status flag. */2141#define MC_CMD_GET_ASSERTS_OUT_V2_GLOBAL_FLAGS_OFST 02142#define MC_CMD_GET_ASSERTS_OUT_V2_GLOBAL_FLAGS_LEN 42143/* enum: No assertions have failed. */2144/* MC_CMD_GET_ASSERTS_FLAGS_NO_FAILS 0x1 */2145/* enum: A system-level assertion has failed. */2146/* MC_CMD_GET_ASSERTS_FLAGS_SYS_FAIL 0x2 */2147/* enum: A thread-level assertion has failed. */2148/* MC_CMD_GET_ASSERTS_FLAGS_THR_FAIL 0x3 */2149/* enum: The system was reset by the watchdog. */2150/* MC_CMD_GET_ASSERTS_FLAGS_WDOG_FIRED 0x4 */2151/* enum: An illegal address trap stopped the system (huntington and later) */2152/* MC_CMD_GET_ASSERTS_FLAGS_ADDR_TRAP 0x5 */2153/* Failing PC value */2154#define MC_CMD_GET_ASSERTS_OUT_V2_SAVED_PC_OFFS_OFST 42155#define MC_CMD_GET_ASSERTS_OUT_V2_SAVED_PC_OFFS_LEN 42156/* Saved GP regs */2157#define MC_CMD_GET_ASSERTS_OUT_V2_GP_REGS_OFFS_OFST 82158#define MC_CMD_GET_ASSERTS_OUT_V2_GP_REGS_OFFS_LEN 42159#define MC_CMD_GET_ASSERTS_OUT_V2_GP_REGS_OFFS_NUM 312160/* enum: A magic value hinting that the value in this register at the time of2161 * the failure has likely been lost.2162 */2163/* MC_CMD_GET_ASSERTS_REG_NO_DATA 0xda7a1057 */2164/* Failing thread address */2165#define MC_CMD_GET_ASSERTS_OUT_V2_THREAD_OFFS_OFST 1322166#define MC_CMD_GET_ASSERTS_OUT_V2_THREAD_OFFS_LEN 42167#define MC_CMD_GET_ASSERTS_OUT_V2_RESERVED_OFST 1362168#define MC_CMD_GET_ASSERTS_OUT_V2_RESERVED_LEN 42169/* Saved Special Function Registers */2170#define MC_CMD_GET_ASSERTS_OUT_V2_SF_REGS_OFFS_OFST 1362171#define MC_CMD_GET_ASSERTS_OUT_V2_SF_REGS_OFFS_LEN 42172#define MC_CMD_GET_ASSERTS_OUT_V2_SF_REGS_OFFS_NUM 262173 2174/* MC_CMD_GET_ASSERTS_OUT_V3 msgresponse: Extended response with asserted2175 * firmware version information2176 */2177#define MC_CMD_GET_ASSERTS_OUT_V3_LEN 3602178/* Assertion status flag. */2179#define MC_CMD_GET_ASSERTS_OUT_V3_GLOBAL_FLAGS_OFST 02180#define MC_CMD_GET_ASSERTS_OUT_V3_GLOBAL_FLAGS_LEN 42181/* enum: No assertions have failed. */2182/* MC_CMD_GET_ASSERTS_FLAGS_NO_FAILS 0x1 */2183/* enum: A system-level assertion has failed. */2184/* MC_CMD_GET_ASSERTS_FLAGS_SYS_FAIL 0x2 */2185/* enum: A thread-level assertion has failed. */2186/* MC_CMD_GET_ASSERTS_FLAGS_THR_FAIL 0x3 */2187/* enum: The system was reset by the watchdog. */2188/* MC_CMD_GET_ASSERTS_FLAGS_WDOG_FIRED 0x4 */2189/* enum: An illegal address trap stopped the system (huntington and later) */2190/* MC_CMD_GET_ASSERTS_FLAGS_ADDR_TRAP 0x5 */2191/* Failing PC value */2192#define MC_CMD_GET_ASSERTS_OUT_V3_SAVED_PC_OFFS_OFST 42193#define MC_CMD_GET_ASSERTS_OUT_V3_SAVED_PC_OFFS_LEN 42194/* Saved GP regs */2195#define MC_CMD_GET_ASSERTS_OUT_V3_GP_REGS_OFFS_OFST 82196#define MC_CMD_GET_ASSERTS_OUT_V3_GP_REGS_OFFS_LEN 42197#define MC_CMD_GET_ASSERTS_OUT_V3_GP_REGS_OFFS_NUM 312198/* enum: A magic value hinting that the value in this register at the time of2199 * the failure has likely been lost.2200 */2201/* MC_CMD_GET_ASSERTS_REG_NO_DATA 0xda7a1057 */2202/* Failing thread address */2203#define MC_CMD_GET_ASSERTS_OUT_V3_THREAD_OFFS_OFST 1322204#define MC_CMD_GET_ASSERTS_OUT_V3_THREAD_OFFS_LEN 42205#define MC_CMD_GET_ASSERTS_OUT_V3_RESERVED_OFST 1362206#define MC_CMD_GET_ASSERTS_OUT_V3_RESERVED_LEN 42207/* Saved Special Function Registers */2208#define MC_CMD_GET_ASSERTS_OUT_V3_SF_REGS_OFFS_OFST 1362209#define MC_CMD_GET_ASSERTS_OUT_V3_SF_REGS_OFFS_LEN 42210#define MC_CMD_GET_ASSERTS_OUT_V3_SF_REGS_OFFS_NUM 262211/* MC firmware unique build ID (as binary SHA-1 value) */2212#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_ID_OFST 2402213#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_ID_LEN 202214/* MC firmware build date (as Unix timestamp) */2215#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_TIMESTAMP_OFST 2602216#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_TIMESTAMP_LEN 82217#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_TIMESTAMP_LO_OFST 2602218#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_TIMESTAMP_LO_LEN 42219#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_TIMESTAMP_LO_LBN 20802220#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_TIMESTAMP_LO_WIDTH 322221#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_TIMESTAMP_HI_OFST 2642222#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_TIMESTAMP_HI_LEN 42223#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_TIMESTAMP_HI_LBN 21122224#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_TIMESTAMP_HI_WIDTH 322225/* MC firmware version number */2226#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_VERSION_OFST 2682227#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_VERSION_LEN 82228#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_VERSION_LO_OFST 2682229#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_VERSION_LO_LEN 42230#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_VERSION_LO_LBN 21442231#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_VERSION_LO_WIDTH 322232#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_VERSION_HI_OFST 2722233#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_VERSION_HI_LEN 42234#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_VERSION_HI_LBN 21762235#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_VERSION_HI_WIDTH 322236/* MC firmware security level */2237#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_SECURITY_LEVEL_OFST 2762238#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_SECURITY_LEVEL_LEN 42239/* MC firmware extra version info (as null-terminated US-ASCII string) */2240#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_EXTRA_INFO_OFST 2802241#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_EXTRA_INFO_LEN 162242/* MC firmware build name (as null-terminated US-ASCII string) */2243#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_NAME_OFST 2962244#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_NAME_LEN 642245 2246 2247/***********************************/2248/* MC_CMD_LOG_CTRL2249 * Configure the output stream for log events such as link state changes,2250 * sensor notifications and MCDI completions2251 */2252#define MC_CMD_LOG_CTRL 0x72253#undef MC_CMD_0x7_PRIVILEGE_CTG2254 2255#define MC_CMD_0x7_PRIVILEGE_CTG SRIOV_CTG_GENERAL2256 2257/* MC_CMD_LOG_CTRL_IN msgrequest */2258#define MC_CMD_LOG_CTRL_IN_LEN 82259/* Log destination */2260#define MC_CMD_LOG_CTRL_IN_LOG_DEST_OFST 02261#define MC_CMD_LOG_CTRL_IN_LOG_DEST_LEN 42262/* enum: UART. */2263#define MC_CMD_LOG_CTRL_IN_LOG_DEST_UART 0x12264/* enum: Event queue. */2265#define MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ 0x22266/* Legacy argument. Must be zero. */2267#define MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ_OFST 42268#define MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ_LEN 42269 2270/* MC_CMD_LOG_CTRL_OUT msgresponse */2271#define MC_CMD_LOG_CTRL_OUT_LEN 02272 2273 2274/***********************************/2275/* MC_CMD_GET_VERSION2276 * Get version information about adapter components.2277 */2278#define MC_CMD_GET_VERSION 0x82279#undef MC_CMD_0x8_PRIVILEGE_CTG2280 2281#define MC_CMD_0x8_PRIVILEGE_CTG SRIOV_CTG_GENERAL2282 2283/* MC_CMD_GET_VERSION_IN msgrequest */2284#define MC_CMD_GET_VERSION_IN_LEN 02285 2286/* MC_CMD_GET_VERSION_EXT_IN msgrequest: Asks for the extended version */2287#define MC_CMD_GET_VERSION_EXT_IN_LEN 42288/* placeholder, set to 0 */2289#define MC_CMD_GET_VERSION_EXT_IN_EXT_FLAGS_OFST 02290#define MC_CMD_GET_VERSION_EXT_IN_EXT_FLAGS_LEN 42291 2292/* MC_CMD_GET_VERSION_V0_OUT msgresponse: deprecated version format */2293#define MC_CMD_GET_VERSION_V0_OUT_LEN 42294#define MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 02295#define MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 42296/* enum: Reserved version number to indicate "any" version. */2297#define MC_CMD_GET_VERSION_OUT_FIRMWARE_ANY 0xffffffff2298/* enum: Bootrom version value for Siena. */2299#define MC_CMD_GET_VERSION_OUT_FIRMWARE_SIENA_BOOTROM 0xb00700002300/* enum: Bootrom version value for Huntington. */2301#define MC_CMD_GET_VERSION_OUT_FIRMWARE_HUNT_BOOTROM 0xb00700012302/* enum: Bootrom version value for Medford2. */2303#define MC_CMD_GET_VERSION_OUT_FIRMWARE_MEDFORD2_BOOTROM 0xb00700022304 2305/* MC_CMD_GET_VERSION_OUT msgresponse */2306#define MC_CMD_GET_VERSION_OUT_LEN 322307/* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */2308/* MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4 */2309/* Enum values, see field(s): */2310/* MC_CMD_GET_VERSION_V0_OUT/MC_CMD_GET_VERSION_OUT_FIRMWARE */2311#define MC_CMD_GET_VERSION_OUT_PCOL_OFST 42312#define MC_CMD_GET_VERSION_OUT_PCOL_LEN 42313/* 128bit mask of functions supported by the current firmware */2314#define MC_CMD_GET_VERSION_OUT_SUPPORTED_FUNCS_OFST 82315#define MC_CMD_GET_VERSION_OUT_SUPPORTED_FUNCS_LEN 162316#define MC_CMD_GET_VERSION_OUT_VERSION_OFST 242317#define MC_CMD_GET_VERSION_OUT_VERSION_LEN 82318#define MC_CMD_GET_VERSION_OUT_VERSION_LO_OFST 242319#define MC_CMD_GET_VERSION_OUT_VERSION_LO_LEN 42320#define MC_CMD_GET_VERSION_OUT_VERSION_LO_LBN 1922321#define MC_CMD_GET_VERSION_OUT_VERSION_LO_WIDTH 322322#define MC_CMD_GET_VERSION_OUT_VERSION_HI_OFST 282323#define MC_CMD_GET_VERSION_OUT_VERSION_HI_LEN 42324#define MC_CMD_GET_VERSION_OUT_VERSION_HI_LBN 2242325#define MC_CMD_GET_VERSION_OUT_VERSION_HI_WIDTH 322326 2327/* MC_CMD_GET_VERSION_EXT_OUT msgresponse */2328#define MC_CMD_GET_VERSION_EXT_OUT_LEN 482329/* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */2330/* MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4 */2331/* Enum values, see field(s): */2332/* MC_CMD_GET_VERSION_V0_OUT/MC_CMD_GET_VERSION_OUT_FIRMWARE */2333#define MC_CMD_GET_VERSION_EXT_OUT_PCOL_OFST 42334#define MC_CMD_GET_VERSION_EXT_OUT_PCOL_LEN 42335/* 128bit mask of functions supported by the current firmware */2336#define MC_CMD_GET_VERSION_EXT_OUT_SUPPORTED_FUNCS_OFST 82337#define MC_CMD_GET_VERSION_EXT_OUT_SUPPORTED_FUNCS_LEN 162338#define MC_CMD_GET_VERSION_EXT_OUT_VERSION_OFST 242339#define MC_CMD_GET_VERSION_EXT_OUT_VERSION_LEN 82340#define MC_CMD_GET_VERSION_EXT_OUT_VERSION_LO_OFST 242341#define MC_CMD_GET_VERSION_EXT_OUT_VERSION_LO_LEN 42342#define MC_CMD_GET_VERSION_EXT_OUT_VERSION_LO_LBN 1922343#define MC_CMD_GET_VERSION_EXT_OUT_VERSION_LO_WIDTH 322344#define MC_CMD_GET_VERSION_EXT_OUT_VERSION_HI_OFST 282345#define MC_CMD_GET_VERSION_EXT_OUT_VERSION_HI_LEN 42346#define MC_CMD_GET_VERSION_EXT_OUT_VERSION_HI_LBN 2242347#define MC_CMD_GET_VERSION_EXT_OUT_VERSION_HI_WIDTH 322348/* extra info */2349#define MC_CMD_GET_VERSION_EXT_OUT_EXTRA_OFST 322350#define MC_CMD_GET_VERSION_EXT_OUT_EXTRA_LEN 162351 2352/* MC_CMD_GET_VERSION_V2_OUT msgresponse: Extended response providing version2353 * information for all adapter components. For Riverhead based designs, base MC2354 * firmware version fields refer to NMC firmware, while CMC firmware data is in2355 * dedicated CMC fields. Flags indicate which data is present in the response2356 * (depending on which components exist on a particular adapter)2357 */2358#define MC_CMD_GET_VERSION_V2_OUT_LEN 3042359/* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */2360/* MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4 */2361/* Enum values, see field(s): */2362/* MC_CMD_GET_VERSION_V0_OUT/MC_CMD_GET_VERSION_OUT_FIRMWARE */2363#define MC_CMD_GET_VERSION_V2_OUT_PCOL_OFST 42364#define MC_CMD_GET_VERSION_V2_OUT_PCOL_LEN 42365/* 128bit mask of functions supported by the current firmware */2366#define MC_CMD_GET_VERSION_V2_OUT_SUPPORTED_FUNCS_OFST 82367#define MC_CMD_GET_VERSION_V2_OUT_SUPPORTED_FUNCS_LEN 162368#define MC_CMD_GET_VERSION_V2_OUT_VERSION_OFST 242369#define MC_CMD_GET_VERSION_V2_OUT_VERSION_LEN 82370#define MC_CMD_GET_VERSION_V2_OUT_VERSION_LO_OFST 242371#define MC_CMD_GET_VERSION_V2_OUT_VERSION_LO_LEN 42372#define MC_CMD_GET_VERSION_V2_OUT_VERSION_LO_LBN 1922373#define MC_CMD_GET_VERSION_V2_OUT_VERSION_LO_WIDTH 322374#define MC_CMD_GET_VERSION_V2_OUT_VERSION_HI_OFST 282375#define MC_CMD_GET_VERSION_V2_OUT_VERSION_HI_LEN 42376#define MC_CMD_GET_VERSION_V2_OUT_VERSION_HI_LBN 2242377#define MC_CMD_GET_VERSION_V2_OUT_VERSION_HI_WIDTH 322378/* extra info */2379#define MC_CMD_GET_VERSION_V2_OUT_EXTRA_OFST 322380#define MC_CMD_GET_VERSION_V2_OUT_EXTRA_LEN 162381/* Flags indicating which extended fields are valid */2382#define MC_CMD_GET_VERSION_V2_OUT_FLAGS_OFST 482383#define MC_CMD_GET_VERSION_V2_OUT_FLAGS_LEN 42384#define MC_CMD_GET_VERSION_V2_OUT_MCFW_EXT_INFO_PRESENT_OFST 482385#define MC_CMD_GET_VERSION_V2_OUT_MCFW_EXT_INFO_PRESENT_LBN 02386#define MC_CMD_GET_VERSION_V2_OUT_MCFW_EXT_INFO_PRESENT_WIDTH 12387#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_EXT_INFO_PRESENT_OFST 482388#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_EXT_INFO_PRESENT_LBN 12389#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_EXT_INFO_PRESENT_WIDTH 12390#define MC_CMD_GET_VERSION_V2_OUT_CMC_EXT_INFO_PRESENT_OFST 482391#define MC_CMD_GET_VERSION_V2_OUT_CMC_EXT_INFO_PRESENT_LBN 22392#define MC_CMD_GET_VERSION_V2_OUT_CMC_EXT_INFO_PRESENT_WIDTH 12393#define MC_CMD_GET_VERSION_V2_OUT_FPGA_EXT_INFO_PRESENT_OFST 482394#define MC_CMD_GET_VERSION_V2_OUT_FPGA_EXT_INFO_PRESENT_LBN 32395#define MC_CMD_GET_VERSION_V2_OUT_FPGA_EXT_INFO_PRESENT_WIDTH 12396#define MC_CMD_GET_VERSION_V2_OUT_BOARD_EXT_INFO_PRESENT_OFST 482397#define MC_CMD_GET_VERSION_V2_OUT_BOARD_EXT_INFO_PRESENT_LBN 42398#define MC_CMD_GET_VERSION_V2_OUT_BOARD_EXT_INFO_PRESENT_WIDTH 12399#define MC_CMD_GET_VERSION_V2_OUT_DATAPATH_HW_VERSION_PRESENT_OFST 482400#define MC_CMD_GET_VERSION_V2_OUT_DATAPATH_HW_VERSION_PRESENT_LBN 52401#define MC_CMD_GET_VERSION_V2_OUT_DATAPATH_HW_VERSION_PRESENT_WIDTH 12402#define MC_CMD_GET_VERSION_V2_OUT_DATAPATH_FW_VERSION_PRESENT_OFST 482403#define MC_CMD_GET_VERSION_V2_OUT_DATAPATH_FW_VERSION_PRESENT_LBN 62404#define MC_CMD_GET_VERSION_V2_OUT_DATAPATH_FW_VERSION_PRESENT_WIDTH 12405#define MC_CMD_GET_VERSION_V2_OUT_SOC_BOOT_VERSION_PRESENT_OFST 482406#define MC_CMD_GET_VERSION_V2_OUT_SOC_BOOT_VERSION_PRESENT_LBN 72407#define MC_CMD_GET_VERSION_V2_OUT_SOC_BOOT_VERSION_PRESENT_WIDTH 12408#define MC_CMD_GET_VERSION_V2_OUT_SOC_UBOOT_VERSION_PRESENT_OFST 482409#define MC_CMD_GET_VERSION_V2_OUT_SOC_UBOOT_VERSION_PRESENT_LBN 82410#define MC_CMD_GET_VERSION_V2_OUT_SOC_UBOOT_VERSION_PRESENT_WIDTH 12411#define MC_CMD_GET_VERSION_V2_OUT_SOC_MAIN_ROOTFS_VERSION_PRESENT_OFST 482412#define MC_CMD_GET_VERSION_V2_OUT_SOC_MAIN_ROOTFS_VERSION_PRESENT_LBN 92413#define MC_CMD_GET_VERSION_V2_OUT_SOC_MAIN_ROOTFS_VERSION_PRESENT_WIDTH 12414#define MC_CMD_GET_VERSION_V2_OUT_SOC_RECOVERY_BUILDROOT_VERSION_PRESENT_OFST 482415#define MC_CMD_GET_VERSION_V2_OUT_SOC_RECOVERY_BUILDROOT_VERSION_PRESENT_LBN 102416#define MC_CMD_GET_VERSION_V2_OUT_SOC_RECOVERY_BUILDROOT_VERSION_PRESENT_WIDTH 12417#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_VERSION_PRESENT_OFST 482418#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_VERSION_PRESENT_LBN 112419#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_VERSION_PRESENT_WIDTH 12420#define MC_CMD_GET_VERSION_V2_OUT_BOARD_VERSION_PRESENT_OFST 482421#define MC_CMD_GET_VERSION_V2_OUT_BOARD_VERSION_PRESENT_LBN 122422#define MC_CMD_GET_VERSION_V2_OUT_BOARD_VERSION_PRESENT_WIDTH 12423#define MC_CMD_GET_VERSION_V2_OUT_BUNDLE_VERSION_PRESENT_OFST 482424#define MC_CMD_GET_VERSION_V2_OUT_BUNDLE_VERSION_PRESENT_LBN 132425#define MC_CMD_GET_VERSION_V2_OUT_BUNDLE_VERSION_PRESENT_WIDTH 12426/* MC firmware unique build ID (as binary SHA-1 value) */2427#define MC_CMD_GET_VERSION_V2_OUT_MCFW_BUILD_ID_OFST 522428#define MC_CMD_GET_VERSION_V2_OUT_MCFW_BUILD_ID_LEN 202429/* MC firmware security level */2430#define MC_CMD_GET_VERSION_V2_OUT_MCFW_SECURITY_LEVEL_OFST 722431#define MC_CMD_GET_VERSION_V2_OUT_MCFW_SECURITY_LEVEL_LEN 42432/* MC firmware build name (as null-terminated US-ASCII string) */2433#define MC_CMD_GET_VERSION_V2_OUT_MCFW_BUILD_NAME_OFST 762434#define MC_CMD_GET_VERSION_V2_OUT_MCFW_BUILD_NAME_LEN 642435/* The SUC firmware version as four numbers - a.b.c.d */2436#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_VERSION_OFST 1402437#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_VERSION_LEN 42438#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_VERSION_NUM 42439/* SUC firmware build date (as 64-bit Unix timestamp) */2440#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_BUILD_DATE_OFST 1562441#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_BUILD_DATE_LEN 82442#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_BUILD_DATE_LO_OFST 1562443#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_BUILD_DATE_LO_LEN 42444#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_BUILD_DATE_LO_LBN 12482445#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_BUILD_DATE_LO_WIDTH 322446#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_BUILD_DATE_HI_OFST 1602447#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_BUILD_DATE_HI_LEN 42448#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_BUILD_DATE_HI_LBN 12802449#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_BUILD_DATE_HI_WIDTH 322450/* The ID of the SUC chip. This is specific to the platform but typically2451 * indicates family, memory sizes etc. See SF-116728-SW for further details.2452 */2453#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_CHIP_ID_OFST 1642454#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_CHIP_ID_LEN 42455/* The CMC firmware version as four numbers - a.b.c.d */2456#define MC_CMD_GET_VERSION_V2_OUT_CMCFW_VERSION_OFST 1682457#define MC_CMD_GET_VERSION_V2_OUT_CMCFW_VERSION_LEN 42458#define MC_CMD_GET_VERSION_V2_OUT_CMCFW_VERSION_NUM 42459/* CMC firmware build date (as 64-bit Unix timestamp) */2460#define MC_CMD_GET_VERSION_V2_OUT_CMCFW_BUILD_DATE_OFST 1842461#define MC_CMD_GET_VERSION_V2_OUT_CMCFW_BUILD_DATE_LEN 82462#define MC_CMD_GET_VERSION_V2_OUT_CMCFW_BUILD_DATE_LO_OFST 1842463#define MC_CMD_GET_VERSION_V2_OUT_CMCFW_BUILD_DATE_LO_LEN 42464#define MC_CMD_GET_VERSION_V2_OUT_CMCFW_BUILD_DATE_LO_LBN 14722465#define MC_CMD_GET_VERSION_V2_OUT_CMCFW_BUILD_DATE_LO_WIDTH 322466#define MC_CMD_GET_VERSION_V2_OUT_CMCFW_BUILD_DATE_HI_OFST 1882467#define MC_CMD_GET_VERSION_V2_OUT_CMCFW_BUILD_DATE_HI_LEN 42468#define MC_CMD_GET_VERSION_V2_OUT_CMCFW_BUILD_DATE_HI_LBN 15042469#define MC_CMD_GET_VERSION_V2_OUT_CMCFW_BUILD_DATE_HI_WIDTH 322470/* FPGA version as three numbers. On Riverhead based systems this field uses2471 * the same encoding as hardware version ID registers (MC_FPGA_BUILD_HWRD_REG):2472 * FPGA_VERSION[0]: x => Image H{x} FPGA_VERSION[1]: Revision letter (0 => A, 12473 * => B, ...) FPGA_VERSION[2]: Sub-revision number2474 */2475#define MC_CMD_GET_VERSION_V2_OUT_FPGA_VERSION_OFST 1922476#define MC_CMD_GET_VERSION_V2_OUT_FPGA_VERSION_LEN 42477#define MC_CMD_GET_VERSION_V2_OUT_FPGA_VERSION_NUM 32478/* Extra FPGA revision information (as null-terminated US-ASCII string) */2479#define MC_CMD_GET_VERSION_V2_OUT_FPGA_EXTRA_OFST 2042480#define MC_CMD_GET_VERSION_V2_OUT_FPGA_EXTRA_LEN 162481/* Board name / adapter model (as null-terminated US-ASCII string) */2482#define MC_CMD_GET_VERSION_V2_OUT_BOARD_NAME_OFST 2202483#define MC_CMD_GET_VERSION_V2_OUT_BOARD_NAME_LEN 162484/* Board revision number */2485#define MC_CMD_GET_VERSION_V2_OUT_BOARD_REVISION_OFST 2362486#define MC_CMD_GET_VERSION_V2_OUT_BOARD_REVISION_LEN 42487/* Board serial number (as null-terminated US-ASCII string) */2488#define MC_CMD_GET_VERSION_V2_OUT_BOARD_SERIAL_OFST 2402489#define MC_CMD_GET_VERSION_V2_OUT_BOARD_SERIAL_LEN 642490 2491/* MC_CMD_GET_VERSION_V3_OUT msgresponse: Extended response providing version2492 * information for all adapter components. For Riverhead based designs, base MC2493 * firmware version fields refer to NMC firmware, while CMC firmware data is in2494 * dedicated CMC fields. Flags indicate which data is present in the response2495 * (depending on which components exist on a particular adapter)2496 */2497#define MC_CMD_GET_VERSION_V3_OUT_LEN 3282498/* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */2499/* MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4 */2500/* Enum values, see field(s): */2501/* MC_CMD_GET_VERSION_V0_OUT/MC_CMD_GET_VERSION_OUT_FIRMWARE */2502#define MC_CMD_GET_VERSION_V3_OUT_PCOL_OFST 42503#define MC_CMD_GET_VERSION_V3_OUT_PCOL_LEN 42504/* 128bit mask of functions supported by the current firmware */2505#define MC_CMD_GET_VERSION_V3_OUT_SUPPORTED_FUNCS_OFST 82506#define MC_CMD_GET_VERSION_V3_OUT_SUPPORTED_FUNCS_LEN 162507#define MC_CMD_GET_VERSION_V3_OUT_VERSION_OFST 242508#define MC_CMD_GET_VERSION_V3_OUT_VERSION_LEN 82509#define MC_CMD_GET_VERSION_V3_OUT_VERSION_LO_OFST 242510#define MC_CMD_GET_VERSION_V3_OUT_VERSION_LO_LEN 42511#define MC_CMD_GET_VERSION_V3_OUT_VERSION_LO_LBN 1922512#define MC_CMD_GET_VERSION_V3_OUT_VERSION_LO_WIDTH 322513#define MC_CMD_GET_VERSION_V3_OUT_VERSION_HI_OFST 282514#define MC_CMD_GET_VERSION_V3_OUT_VERSION_HI_LEN 42515#define MC_CMD_GET_VERSION_V3_OUT_VERSION_HI_LBN 2242516#define MC_CMD_GET_VERSION_V3_OUT_VERSION_HI_WIDTH 322517/* extra info */2518#define MC_CMD_GET_VERSION_V3_OUT_EXTRA_OFST 322519#define MC_CMD_GET_VERSION_V3_OUT_EXTRA_LEN 162520/* Flags indicating which extended fields are valid */2521#define MC_CMD_GET_VERSION_V3_OUT_FLAGS_OFST 482522#define MC_CMD_GET_VERSION_V3_OUT_FLAGS_LEN 42523#define MC_CMD_GET_VERSION_V3_OUT_MCFW_EXT_INFO_PRESENT_OFST 482524#define MC_CMD_GET_VERSION_V3_OUT_MCFW_EXT_INFO_PRESENT_LBN 02525#define MC_CMD_GET_VERSION_V3_OUT_MCFW_EXT_INFO_PRESENT_WIDTH 12526#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_EXT_INFO_PRESENT_OFST 482527#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_EXT_INFO_PRESENT_LBN 12528#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_EXT_INFO_PRESENT_WIDTH 12529#define MC_CMD_GET_VERSION_V3_OUT_CMC_EXT_INFO_PRESENT_OFST 482530#define MC_CMD_GET_VERSION_V3_OUT_CMC_EXT_INFO_PRESENT_LBN 22531#define MC_CMD_GET_VERSION_V3_OUT_CMC_EXT_INFO_PRESENT_WIDTH 12532#define MC_CMD_GET_VERSION_V3_OUT_FPGA_EXT_INFO_PRESENT_OFST 482533#define MC_CMD_GET_VERSION_V3_OUT_FPGA_EXT_INFO_PRESENT_LBN 32534#define MC_CMD_GET_VERSION_V3_OUT_FPGA_EXT_INFO_PRESENT_WIDTH 12535#define MC_CMD_GET_VERSION_V3_OUT_BOARD_EXT_INFO_PRESENT_OFST 482536#define MC_CMD_GET_VERSION_V3_OUT_BOARD_EXT_INFO_PRESENT_LBN 42537#define MC_CMD_GET_VERSION_V3_OUT_BOARD_EXT_INFO_PRESENT_WIDTH 12538#define MC_CMD_GET_VERSION_V3_OUT_DATAPATH_HW_VERSION_PRESENT_OFST 482539#define MC_CMD_GET_VERSION_V3_OUT_DATAPATH_HW_VERSION_PRESENT_LBN 52540#define MC_CMD_GET_VERSION_V3_OUT_DATAPATH_HW_VERSION_PRESENT_WIDTH 12541#define MC_CMD_GET_VERSION_V3_OUT_DATAPATH_FW_VERSION_PRESENT_OFST 482542#define MC_CMD_GET_VERSION_V3_OUT_DATAPATH_FW_VERSION_PRESENT_LBN 62543#define MC_CMD_GET_VERSION_V3_OUT_DATAPATH_FW_VERSION_PRESENT_WIDTH 12544#define MC_CMD_GET_VERSION_V3_OUT_SOC_BOOT_VERSION_PRESENT_OFST 482545#define MC_CMD_GET_VERSION_V3_OUT_SOC_BOOT_VERSION_PRESENT_LBN 72546#define MC_CMD_GET_VERSION_V3_OUT_SOC_BOOT_VERSION_PRESENT_WIDTH 12547#define MC_CMD_GET_VERSION_V3_OUT_SOC_UBOOT_VERSION_PRESENT_OFST 482548#define MC_CMD_GET_VERSION_V3_OUT_SOC_UBOOT_VERSION_PRESENT_LBN 82549#define MC_CMD_GET_VERSION_V3_OUT_SOC_UBOOT_VERSION_PRESENT_WIDTH 12550#define MC_CMD_GET_VERSION_V3_OUT_SOC_MAIN_ROOTFS_VERSION_PRESENT_OFST 482551#define MC_CMD_GET_VERSION_V3_OUT_SOC_MAIN_ROOTFS_VERSION_PRESENT_LBN 92552#define MC_CMD_GET_VERSION_V3_OUT_SOC_MAIN_ROOTFS_VERSION_PRESENT_WIDTH 12553#define MC_CMD_GET_VERSION_V3_OUT_SOC_RECOVERY_BUILDROOT_VERSION_PRESENT_OFST 482554#define MC_CMD_GET_VERSION_V3_OUT_SOC_RECOVERY_BUILDROOT_VERSION_PRESENT_LBN 102555#define MC_CMD_GET_VERSION_V3_OUT_SOC_RECOVERY_BUILDROOT_VERSION_PRESENT_WIDTH 12556#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_VERSION_PRESENT_OFST 482557#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_VERSION_PRESENT_LBN 112558#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_VERSION_PRESENT_WIDTH 12559#define MC_CMD_GET_VERSION_V3_OUT_BOARD_VERSION_PRESENT_OFST 482560#define MC_CMD_GET_VERSION_V3_OUT_BOARD_VERSION_PRESENT_LBN 122561#define MC_CMD_GET_VERSION_V3_OUT_BOARD_VERSION_PRESENT_WIDTH 12562#define MC_CMD_GET_VERSION_V3_OUT_BUNDLE_VERSION_PRESENT_OFST 482563#define MC_CMD_GET_VERSION_V3_OUT_BUNDLE_VERSION_PRESENT_LBN 132564#define MC_CMD_GET_VERSION_V3_OUT_BUNDLE_VERSION_PRESENT_WIDTH 12565/* MC firmware unique build ID (as binary SHA-1 value) */2566#define MC_CMD_GET_VERSION_V3_OUT_MCFW_BUILD_ID_OFST 522567#define MC_CMD_GET_VERSION_V3_OUT_MCFW_BUILD_ID_LEN 202568/* MC firmware security level */2569#define MC_CMD_GET_VERSION_V3_OUT_MCFW_SECURITY_LEVEL_OFST 722570#define MC_CMD_GET_VERSION_V3_OUT_MCFW_SECURITY_LEVEL_LEN 42571/* MC firmware build name (as null-terminated US-ASCII string) */2572#define MC_CMD_GET_VERSION_V3_OUT_MCFW_BUILD_NAME_OFST 762573#define MC_CMD_GET_VERSION_V3_OUT_MCFW_BUILD_NAME_LEN 642574/* The SUC firmware version as four numbers - a.b.c.d */2575#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_VERSION_OFST 1402576#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_VERSION_LEN 42577#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_VERSION_NUM 42578/* SUC firmware build date (as 64-bit Unix timestamp) */2579#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_BUILD_DATE_OFST 1562580#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_BUILD_DATE_LEN 82581#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_BUILD_DATE_LO_OFST 1562582#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_BUILD_DATE_LO_LEN 42583#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_BUILD_DATE_LO_LBN 12482584#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_BUILD_DATE_LO_WIDTH 322585#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_BUILD_DATE_HI_OFST 1602586#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_BUILD_DATE_HI_LEN 42587#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_BUILD_DATE_HI_LBN 12802588#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_BUILD_DATE_HI_WIDTH 322589/* The ID of the SUC chip. This is specific to the platform but typically2590 * indicates family, memory sizes etc. See SF-116728-SW for further details.2591 */2592#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_CHIP_ID_OFST 1642593#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_CHIP_ID_LEN 42594/* The CMC firmware version as four numbers - a.b.c.d */2595#define MC_CMD_GET_VERSION_V3_OUT_CMCFW_VERSION_OFST 1682596#define MC_CMD_GET_VERSION_V3_OUT_CMCFW_VERSION_LEN 42597#define MC_CMD_GET_VERSION_V3_OUT_CMCFW_VERSION_NUM 42598/* CMC firmware build date (as 64-bit Unix timestamp) */2599#define MC_CMD_GET_VERSION_V3_OUT_CMCFW_BUILD_DATE_OFST 1842600#define MC_CMD_GET_VERSION_V3_OUT_CMCFW_BUILD_DATE_LEN 82601#define MC_CMD_GET_VERSION_V3_OUT_CMCFW_BUILD_DATE_LO_OFST 1842602#define MC_CMD_GET_VERSION_V3_OUT_CMCFW_BUILD_DATE_LO_LEN 42603#define MC_CMD_GET_VERSION_V3_OUT_CMCFW_BUILD_DATE_LO_LBN 14722604#define MC_CMD_GET_VERSION_V3_OUT_CMCFW_BUILD_DATE_LO_WIDTH 322605#define MC_CMD_GET_VERSION_V3_OUT_CMCFW_BUILD_DATE_HI_OFST 1882606#define MC_CMD_GET_VERSION_V3_OUT_CMCFW_BUILD_DATE_HI_LEN 42607#define MC_CMD_GET_VERSION_V3_OUT_CMCFW_BUILD_DATE_HI_LBN 15042608#define MC_CMD_GET_VERSION_V3_OUT_CMCFW_BUILD_DATE_HI_WIDTH 322609/* FPGA version as three numbers. On Riverhead based systems this field uses2610 * the same encoding as hardware version ID registers (MC_FPGA_BUILD_HWRD_REG):2611 * FPGA_VERSION[0]: x => Image H{x} FPGA_VERSION[1]: Revision letter (0 => A, 12612 * => B, ...) FPGA_VERSION[2]: Sub-revision number2613 */2614#define MC_CMD_GET_VERSION_V3_OUT_FPGA_VERSION_OFST 1922615#define MC_CMD_GET_VERSION_V3_OUT_FPGA_VERSION_LEN 42616#define MC_CMD_GET_VERSION_V3_OUT_FPGA_VERSION_NUM 32617/* Extra FPGA revision information (as null-terminated US-ASCII string) */2618#define MC_CMD_GET_VERSION_V3_OUT_FPGA_EXTRA_OFST 2042619#define MC_CMD_GET_VERSION_V3_OUT_FPGA_EXTRA_LEN 162620/* Board name / adapter model (as null-terminated US-ASCII string) */2621#define MC_CMD_GET_VERSION_V3_OUT_BOARD_NAME_OFST 2202622#define MC_CMD_GET_VERSION_V3_OUT_BOARD_NAME_LEN 162623/* Board revision number */2624#define MC_CMD_GET_VERSION_V3_OUT_BOARD_REVISION_OFST 2362625#define MC_CMD_GET_VERSION_V3_OUT_BOARD_REVISION_LEN 42626/* Board serial number (as null-terminated US-ASCII string) */2627#define MC_CMD_GET_VERSION_V3_OUT_BOARD_SERIAL_OFST 2402628#define MC_CMD_GET_VERSION_V3_OUT_BOARD_SERIAL_LEN 642629/* The version of the datapath hardware design as three number - a.b.c */2630#define MC_CMD_GET_VERSION_V3_OUT_DATAPATH_HW_VERSION_OFST 3042631#define MC_CMD_GET_VERSION_V3_OUT_DATAPATH_HW_VERSION_LEN 42632#define MC_CMD_GET_VERSION_V3_OUT_DATAPATH_HW_VERSION_NUM 32633/* The version of the firmware library used to control the datapath as three2634 * number - a.b.c2635 */2636#define MC_CMD_GET_VERSION_V3_OUT_DATAPATH_FW_VERSION_OFST 3162637#define MC_CMD_GET_VERSION_V3_OUT_DATAPATH_FW_VERSION_LEN 42638#define MC_CMD_GET_VERSION_V3_OUT_DATAPATH_FW_VERSION_NUM 32639 2640/* MC_CMD_GET_VERSION_V4_OUT msgresponse: Extended response providing SoC2641 * version information2642 */2643#define MC_CMD_GET_VERSION_V4_OUT_LEN 3922644/* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */2645/* MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4 */2646/* Enum values, see field(s): */2647/* MC_CMD_GET_VERSION_V0_OUT/MC_CMD_GET_VERSION_OUT_FIRMWARE */2648#define MC_CMD_GET_VERSION_V4_OUT_PCOL_OFST 42649#define MC_CMD_GET_VERSION_V4_OUT_PCOL_LEN 42650/* 128bit mask of functions supported by the current firmware */2651#define MC_CMD_GET_VERSION_V4_OUT_SUPPORTED_FUNCS_OFST 82652#define MC_CMD_GET_VERSION_V4_OUT_SUPPORTED_FUNCS_LEN 162653#define MC_CMD_GET_VERSION_V4_OUT_VERSION_OFST 242654#define MC_CMD_GET_VERSION_V4_OUT_VERSION_LEN 82655#define MC_CMD_GET_VERSION_V4_OUT_VERSION_LO_OFST 242656#define MC_CMD_GET_VERSION_V4_OUT_VERSION_LO_LEN 42657#define MC_CMD_GET_VERSION_V4_OUT_VERSION_LO_LBN 1922658#define MC_CMD_GET_VERSION_V4_OUT_VERSION_LO_WIDTH 322659#define MC_CMD_GET_VERSION_V4_OUT_VERSION_HI_OFST 282660#define MC_CMD_GET_VERSION_V4_OUT_VERSION_HI_LEN 42661#define MC_CMD_GET_VERSION_V4_OUT_VERSION_HI_LBN 2242662#define MC_CMD_GET_VERSION_V4_OUT_VERSION_HI_WIDTH 322663/* extra info */2664#define MC_CMD_GET_VERSION_V4_OUT_EXTRA_OFST 322665#define MC_CMD_GET_VERSION_V4_OUT_EXTRA_LEN 162666/* Flags indicating which extended fields are valid */2667#define MC_CMD_GET_VERSION_V4_OUT_FLAGS_OFST 482668#define MC_CMD_GET_VERSION_V4_OUT_FLAGS_LEN 42669#define MC_CMD_GET_VERSION_V4_OUT_MCFW_EXT_INFO_PRESENT_OFST 482670#define MC_CMD_GET_VERSION_V4_OUT_MCFW_EXT_INFO_PRESENT_LBN 02671#define MC_CMD_GET_VERSION_V4_OUT_MCFW_EXT_INFO_PRESENT_WIDTH 12672#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_EXT_INFO_PRESENT_OFST 482673#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_EXT_INFO_PRESENT_LBN 12674#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_EXT_INFO_PRESENT_WIDTH 12675#define MC_CMD_GET_VERSION_V4_OUT_CMC_EXT_INFO_PRESENT_OFST 482676#define MC_CMD_GET_VERSION_V4_OUT_CMC_EXT_INFO_PRESENT_LBN 22677#define MC_CMD_GET_VERSION_V4_OUT_CMC_EXT_INFO_PRESENT_WIDTH 12678#define MC_CMD_GET_VERSION_V4_OUT_FPGA_EXT_INFO_PRESENT_OFST 482679#define MC_CMD_GET_VERSION_V4_OUT_FPGA_EXT_INFO_PRESENT_LBN 32680#define MC_CMD_GET_VERSION_V4_OUT_FPGA_EXT_INFO_PRESENT_WIDTH 12681#define MC_CMD_GET_VERSION_V4_OUT_BOARD_EXT_INFO_PRESENT_OFST 482682#define MC_CMD_GET_VERSION_V4_OUT_BOARD_EXT_INFO_PRESENT_LBN 42683#define MC_CMD_GET_VERSION_V4_OUT_BOARD_EXT_INFO_PRESENT_WIDTH 12684#define MC_CMD_GET_VERSION_V4_OUT_DATAPATH_HW_VERSION_PRESENT_OFST 482685#define MC_CMD_GET_VERSION_V4_OUT_DATAPATH_HW_VERSION_PRESENT_LBN 52686#define MC_CMD_GET_VERSION_V4_OUT_DATAPATH_HW_VERSION_PRESENT_WIDTH 12687#define MC_CMD_GET_VERSION_V4_OUT_DATAPATH_FW_VERSION_PRESENT_OFST 482688#define MC_CMD_GET_VERSION_V4_OUT_DATAPATH_FW_VERSION_PRESENT_LBN 62689#define MC_CMD_GET_VERSION_V4_OUT_DATAPATH_FW_VERSION_PRESENT_WIDTH 12690#define MC_CMD_GET_VERSION_V4_OUT_SOC_BOOT_VERSION_PRESENT_OFST 482691#define MC_CMD_GET_VERSION_V4_OUT_SOC_BOOT_VERSION_PRESENT_LBN 72692#define MC_CMD_GET_VERSION_V4_OUT_SOC_BOOT_VERSION_PRESENT_WIDTH 12693#define MC_CMD_GET_VERSION_V4_OUT_SOC_UBOOT_VERSION_PRESENT_OFST 482694#define MC_CMD_GET_VERSION_V4_OUT_SOC_UBOOT_VERSION_PRESENT_LBN 82695#define MC_CMD_GET_VERSION_V4_OUT_SOC_UBOOT_VERSION_PRESENT_WIDTH 12696#define MC_CMD_GET_VERSION_V4_OUT_SOC_MAIN_ROOTFS_VERSION_PRESENT_OFST 482697#define MC_CMD_GET_VERSION_V4_OUT_SOC_MAIN_ROOTFS_VERSION_PRESENT_LBN 92698#define MC_CMD_GET_VERSION_V4_OUT_SOC_MAIN_ROOTFS_VERSION_PRESENT_WIDTH 12699#define MC_CMD_GET_VERSION_V4_OUT_SOC_RECOVERY_BUILDROOT_VERSION_PRESENT_OFST 482700#define MC_CMD_GET_VERSION_V4_OUT_SOC_RECOVERY_BUILDROOT_VERSION_PRESENT_LBN 102701#define MC_CMD_GET_VERSION_V4_OUT_SOC_RECOVERY_BUILDROOT_VERSION_PRESENT_WIDTH 12702#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_VERSION_PRESENT_OFST 482703#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_VERSION_PRESENT_LBN 112704#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_VERSION_PRESENT_WIDTH 12705#define MC_CMD_GET_VERSION_V4_OUT_BOARD_VERSION_PRESENT_OFST 482706#define MC_CMD_GET_VERSION_V4_OUT_BOARD_VERSION_PRESENT_LBN 122707#define MC_CMD_GET_VERSION_V4_OUT_BOARD_VERSION_PRESENT_WIDTH 12708#define MC_CMD_GET_VERSION_V4_OUT_BUNDLE_VERSION_PRESENT_OFST 482709#define MC_CMD_GET_VERSION_V4_OUT_BUNDLE_VERSION_PRESENT_LBN 132710#define MC_CMD_GET_VERSION_V4_OUT_BUNDLE_VERSION_PRESENT_WIDTH 12711/* MC firmware unique build ID (as binary SHA-1 value) */2712#define MC_CMD_GET_VERSION_V4_OUT_MCFW_BUILD_ID_OFST 522713#define MC_CMD_GET_VERSION_V4_OUT_MCFW_BUILD_ID_LEN 202714/* MC firmware security level */2715#define MC_CMD_GET_VERSION_V4_OUT_MCFW_SECURITY_LEVEL_OFST 722716#define MC_CMD_GET_VERSION_V4_OUT_MCFW_SECURITY_LEVEL_LEN 42717/* MC firmware build name (as null-terminated US-ASCII string) */2718#define MC_CMD_GET_VERSION_V4_OUT_MCFW_BUILD_NAME_OFST 762719#define MC_CMD_GET_VERSION_V4_OUT_MCFW_BUILD_NAME_LEN 642720/* The SUC firmware version as four numbers - a.b.c.d */2721#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_VERSION_OFST 1402722#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_VERSION_LEN 42723#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_VERSION_NUM 42724/* SUC firmware build date (as 64-bit Unix timestamp) */2725#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_BUILD_DATE_OFST 1562726#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_BUILD_DATE_LEN 82727#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_BUILD_DATE_LO_OFST 1562728#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_BUILD_DATE_LO_LEN 42729#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_BUILD_DATE_LO_LBN 12482730#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_BUILD_DATE_LO_WIDTH 322731#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_BUILD_DATE_HI_OFST 1602732#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_BUILD_DATE_HI_LEN 42733#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_BUILD_DATE_HI_LBN 12802734#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_BUILD_DATE_HI_WIDTH 322735/* The ID of the SUC chip. This is specific to the platform but typically2736 * indicates family, memory sizes etc. See SF-116728-SW for further details.2737 */2738#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_CHIP_ID_OFST 1642739#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_CHIP_ID_LEN 42740/* The CMC firmware version as four numbers - a.b.c.d */2741#define MC_CMD_GET_VERSION_V4_OUT_CMCFW_VERSION_OFST 1682742#define MC_CMD_GET_VERSION_V4_OUT_CMCFW_VERSION_LEN 42743#define MC_CMD_GET_VERSION_V4_OUT_CMCFW_VERSION_NUM 42744/* CMC firmware build date (as 64-bit Unix timestamp) */2745#define MC_CMD_GET_VERSION_V4_OUT_CMCFW_BUILD_DATE_OFST 1842746#define MC_CMD_GET_VERSION_V4_OUT_CMCFW_BUILD_DATE_LEN 82747#define MC_CMD_GET_VERSION_V4_OUT_CMCFW_BUILD_DATE_LO_OFST 1842748#define MC_CMD_GET_VERSION_V4_OUT_CMCFW_BUILD_DATE_LO_LEN 42749#define MC_CMD_GET_VERSION_V4_OUT_CMCFW_BUILD_DATE_LO_LBN 14722750#define MC_CMD_GET_VERSION_V4_OUT_CMCFW_BUILD_DATE_LO_WIDTH 322751#define MC_CMD_GET_VERSION_V4_OUT_CMCFW_BUILD_DATE_HI_OFST 1882752#define MC_CMD_GET_VERSION_V4_OUT_CMCFW_BUILD_DATE_HI_LEN 42753#define MC_CMD_GET_VERSION_V4_OUT_CMCFW_BUILD_DATE_HI_LBN 15042754#define MC_CMD_GET_VERSION_V4_OUT_CMCFW_BUILD_DATE_HI_WIDTH 322755/* FPGA version as three numbers. On Riverhead based systems this field uses2756 * the same encoding as hardware version ID registers (MC_FPGA_BUILD_HWRD_REG):2757 * FPGA_VERSION[0]: x => Image H{x} FPGA_VERSION[1]: Revision letter (0 => A, 12758 * => B, ...) FPGA_VERSION[2]: Sub-revision number2759 */2760#define MC_CMD_GET_VERSION_V4_OUT_FPGA_VERSION_OFST 1922761#define MC_CMD_GET_VERSION_V4_OUT_FPGA_VERSION_LEN 42762#define MC_CMD_GET_VERSION_V4_OUT_FPGA_VERSION_NUM 32763/* Extra FPGA revision information (as null-terminated US-ASCII string) */2764#define MC_CMD_GET_VERSION_V4_OUT_FPGA_EXTRA_OFST 2042765#define MC_CMD_GET_VERSION_V4_OUT_FPGA_EXTRA_LEN 162766/* Board name / adapter model (as null-terminated US-ASCII string) */2767#define MC_CMD_GET_VERSION_V4_OUT_BOARD_NAME_OFST 2202768#define MC_CMD_GET_VERSION_V4_OUT_BOARD_NAME_LEN 162769/* Board revision number */2770#define MC_CMD_GET_VERSION_V4_OUT_BOARD_REVISION_OFST 2362771#define MC_CMD_GET_VERSION_V4_OUT_BOARD_REVISION_LEN 42772/* Board serial number (as null-terminated US-ASCII string) */2773#define MC_CMD_GET_VERSION_V4_OUT_BOARD_SERIAL_OFST 2402774#define MC_CMD_GET_VERSION_V4_OUT_BOARD_SERIAL_LEN 642775/* The version of the datapath hardware design as three number - a.b.c */2776#define MC_CMD_GET_VERSION_V4_OUT_DATAPATH_HW_VERSION_OFST 3042777#define MC_CMD_GET_VERSION_V4_OUT_DATAPATH_HW_VERSION_LEN 42778#define MC_CMD_GET_VERSION_V4_OUT_DATAPATH_HW_VERSION_NUM 32779/* The version of the firmware library used to control the datapath as three2780 * number - a.b.c2781 */2782#define MC_CMD_GET_VERSION_V4_OUT_DATAPATH_FW_VERSION_OFST 3162783#define MC_CMD_GET_VERSION_V4_OUT_DATAPATH_FW_VERSION_LEN 42784#define MC_CMD_GET_VERSION_V4_OUT_DATAPATH_FW_VERSION_NUM 32785/* The SOC boot version as four numbers - a.b.c.d */2786#define MC_CMD_GET_VERSION_V4_OUT_SOC_BOOT_VERSION_OFST 3282787#define MC_CMD_GET_VERSION_V4_OUT_SOC_BOOT_VERSION_LEN 42788#define MC_CMD_GET_VERSION_V4_OUT_SOC_BOOT_VERSION_NUM 42789/* The SOC uboot version as four numbers - a.b.c.d */2790#define MC_CMD_GET_VERSION_V4_OUT_SOC_UBOOT_VERSION_OFST 3442791#define MC_CMD_GET_VERSION_V4_OUT_SOC_UBOOT_VERSION_LEN 42792#define MC_CMD_GET_VERSION_V4_OUT_SOC_UBOOT_VERSION_NUM 42793/* The SOC main rootfs version as four numbers - a.b.c.d */2794#define MC_CMD_GET_VERSION_V4_OUT_SOC_MAIN_ROOTFS_VERSION_OFST 3602795#define MC_CMD_GET_VERSION_V4_OUT_SOC_MAIN_ROOTFS_VERSION_LEN 42796#define MC_CMD_GET_VERSION_V4_OUT_SOC_MAIN_ROOTFS_VERSION_NUM 42797/* The SOC recovery buildroot version as four numbers - a.b.c.d */2798#define MC_CMD_GET_VERSION_V4_OUT_SOC_RECOVERY_BUILDROOT_VERSION_OFST 3762799#define MC_CMD_GET_VERSION_V4_OUT_SOC_RECOVERY_BUILDROOT_VERSION_LEN 42800#define MC_CMD_GET_VERSION_V4_OUT_SOC_RECOVERY_BUILDROOT_VERSION_NUM 42801 2802/* MC_CMD_GET_VERSION_V5_OUT msgresponse: Extended response providing bundle2803 * and board version information2804 */2805#define MC_CMD_GET_VERSION_V5_OUT_LEN 4242806/* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */2807/* MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4 */2808/* Enum values, see field(s): */2809/* MC_CMD_GET_VERSION_V0_OUT/MC_CMD_GET_VERSION_OUT_FIRMWARE */2810#define MC_CMD_GET_VERSION_V5_OUT_PCOL_OFST 42811#define MC_CMD_GET_VERSION_V5_OUT_PCOL_LEN 42812/* 128bit mask of functions supported by the current firmware */2813#define MC_CMD_GET_VERSION_V5_OUT_SUPPORTED_FUNCS_OFST 82814#define MC_CMD_GET_VERSION_V5_OUT_SUPPORTED_FUNCS_LEN 162815#define MC_CMD_GET_VERSION_V5_OUT_VERSION_OFST 242816#define MC_CMD_GET_VERSION_V5_OUT_VERSION_LEN 82817#define MC_CMD_GET_VERSION_V5_OUT_VERSION_LO_OFST 242818#define MC_CMD_GET_VERSION_V5_OUT_VERSION_LO_LEN 42819#define MC_CMD_GET_VERSION_V5_OUT_VERSION_LO_LBN 1922820#define MC_CMD_GET_VERSION_V5_OUT_VERSION_LO_WIDTH 322821#define MC_CMD_GET_VERSION_V5_OUT_VERSION_HI_OFST 282822#define MC_CMD_GET_VERSION_V5_OUT_VERSION_HI_LEN 42823#define MC_CMD_GET_VERSION_V5_OUT_VERSION_HI_LBN 2242824#define MC_CMD_GET_VERSION_V5_OUT_VERSION_HI_WIDTH 322825/* extra info */2826#define MC_CMD_GET_VERSION_V5_OUT_EXTRA_OFST 322827#define MC_CMD_GET_VERSION_V5_OUT_EXTRA_LEN 162828/* Flags indicating which extended fields are valid */2829#define MC_CMD_GET_VERSION_V5_OUT_FLAGS_OFST 482830#define MC_CMD_GET_VERSION_V5_OUT_FLAGS_LEN 42831#define MC_CMD_GET_VERSION_V5_OUT_MCFW_EXT_INFO_PRESENT_OFST 482832#define MC_CMD_GET_VERSION_V5_OUT_MCFW_EXT_INFO_PRESENT_LBN 02833#define MC_CMD_GET_VERSION_V5_OUT_MCFW_EXT_INFO_PRESENT_WIDTH 12834#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_EXT_INFO_PRESENT_OFST 482835#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_EXT_INFO_PRESENT_LBN 12836#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_EXT_INFO_PRESENT_WIDTH 12837#define MC_CMD_GET_VERSION_V5_OUT_CMC_EXT_INFO_PRESENT_OFST 482838#define MC_CMD_GET_VERSION_V5_OUT_CMC_EXT_INFO_PRESENT_LBN 22839#define MC_CMD_GET_VERSION_V5_OUT_CMC_EXT_INFO_PRESENT_WIDTH 12840#define MC_CMD_GET_VERSION_V5_OUT_FPGA_EXT_INFO_PRESENT_OFST 482841#define MC_CMD_GET_VERSION_V5_OUT_FPGA_EXT_INFO_PRESENT_LBN 32842#define MC_CMD_GET_VERSION_V5_OUT_FPGA_EXT_INFO_PRESENT_WIDTH 12843#define MC_CMD_GET_VERSION_V5_OUT_BOARD_EXT_INFO_PRESENT_OFST 482844#define MC_CMD_GET_VERSION_V5_OUT_BOARD_EXT_INFO_PRESENT_LBN 42845#define MC_CMD_GET_VERSION_V5_OUT_BOARD_EXT_INFO_PRESENT_WIDTH 12846#define MC_CMD_GET_VERSION_V5_OUT_DATAPATH_HW_VERSION_PRESENT_OFST 482847#define MC_CMD_GET_VERSION_V5_OUT_DATAPATH_HW_VERSION_PRESENT_LBN 52848#define MC_CMD_GET_VERSION_V5_OUT_DATAPATH_HW_VERSION_PRESENT_WIDTH 12849#define MC_CMD_GET_VERSION_V5_OUT_DATAPATH_FW_VERSION_PRESENT_OFST 482850#define MC_CMD_GET_VERSION_V5_OUT_DATAPATH_FW_VERSION_PRESENT_LBN 62851#define MC_CMD_GET_VERSION_V5_OUT_DATAPATH_FW_VERSION_PRESENT_WIDTH 12852#define MC_CMD_GET_VERSION_V5_OUT_SOC_BOOT_VERSION_PRESENT_OFST 482853#define MC_CMD_GET_VERSION_V5_OUT_SOC_BOOT_VERSION_PRESENT_LBN 72854#define MC_CMD_GET_VERSION_V5_OUT_SOC_BOOT_VERSION_PRESENT_WIDTH 12855#define MC_CMD_GET_VERSION_V5_OUT_SOC_UBOOT_VERSION_PRESENT_OFST 482856#define MC_CMD_GET_VERSION_V5_OUT_SOC_UBOOT_VERSION_PRESENT_LBN 82857#define MC_CMD_GET_VERSION_V5_OUT_SOC_UBOOT_VERSION_PRESENT_WIDTH 12858#define MC_CMD_GET_VERSION_V5_OUT_SOC_MAIN_ROOTFS_VERSION_PRESENT_OFST 482859#define MC_CMD_GET_VERSION_V5_OUT_SOC_MAIN_ROOTFS_VERSION_PRESENT_LBN 92860#define MC_CMD_GET_VERSION_V5_OUT_SOC_MAIN_ROOTFS_VERSION_PRESENT_WIDTH 12861#define MC_CMD_GET_VERSION_V5_OUT_SOC_RECOVERY_BUILDROOT_VERSION_PRESENT_OFST 482862#define MC_CMD_GET_VERSION_V5_OUT_SOC_RECOVERY_BUILDROOT_VERSION_PRESENT_LBN 102863#define MC_CMD_GET_VERSION_V5_OUT_SOC_RECOVERY_BUILDROOT_VERSION_PRESENT_WIDTH 12864#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_VERSION_PRESENT_OFST 482865#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_VERSION_PRESENT_LBN 112866#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_VERSION_PRESENT_WIDTH 12867#define MC_CMD_GET_VERSION_V5_OUT_BOARD_VERSION_PRESENT_OFST 482868#define MC_CMD_GET_VERSION_V5_OUT_BOARD_VERSION_PRESENT_LBN 122869#define MC_CMD_GET_VERSION_V5_OUT_BOARD_VERSION_PRESENT_WIDTH 12870#define MC_CMD_GET_VERSION_V5_OUT_BUNDLE_VERSION_PRESENT_OFST 482871#define MC_CMD_GET_VERSION_V5_OUT_BUNDLE_VERSION_PRESENT_LBN 132872#define MC_CMD_GET_VERSION_V5_OUT_BUNDLE_VERSION_PRESENT_WIDTH 12873/* MC firmware unique build ID (as binary SHA-1 value) */2874#define MC_CMD_GET_VERSION_V5_OUT_MCFW_BUILD_ID_OFST 522875#define MC_CMD_GET_VERSION_V5_OUT_MCFW_BUILD_ID_LEN 202876/* MC firmware security level */2877#define MC_CMD_GET_VERSION_V5_OUT_MCFW_SECURITY_LEVEL_OFST 722878#define MC_CMD_GET_VERSION_V5_OUT_MCFW_SECURITY_LEVEL_LEN 42879/* MC firmware build name (as null-terminated US-ASCII string) */2880#define MC_CMD_GET_VERSION_V5_OUT_MCFW_BUILD_NAME_OFST 762881#define MC_CMD_GET_VERSION_V5_OUT_MCFW_BUILD_NAME_LEN 642882/* The SUC firmware version as four numbers - a.b.c.d */2883#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_VERSION_OFST 1402884#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_VERSION_LEN 42885#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_VERSION_NUM 42886/* SUC firmware build date (as 64-bit Unix timestamp) */2887#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_BUILD_DATE_OFST 1562888#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_BUILD_DATE_LEN 82889#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_BUILD_DATE_LO_OFST 1562890#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_BUILD_DATE_LO_LEN 42891#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_BUILD_DATE_LO_LBN 12482892#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_BUILD_DATE_LO_WIDTH 322893#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_BUILD_DATE_HI_OFST 1602894#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_BUILD_DATE_HI_LEN 42895#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_BUILD_DATE_HI_LBN 12802896#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_BUILD_DATE_HI_WIDTH 322897/* The ID of the SUC chip. This is specific to the platform but typically2898 * indicates family, memory sizes etc. See SF-116728-SW for further details.2899 */2900#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_CHIP_ID_OFST 1642901#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_CHIP_ID_LEN 42902/* The CMC firmware version as four numbers - a.b.c.d */2903#define MC_CMD_GET_VERSION_V5_OUT_CMCFW_VERSION_OFST 1682904#define MC_CMD_GET_VERSION_V5_OUT_CMCFW_VERSION_LEN 42905#define MC_CMD_GET_VERSION_V5_OUT_CMCFW_VERSION_NUM 42906/* CMC firmware build date (as 64-bit Unix timestamp) */2907#define MC_CMD_GET_VERSION_V5_OUT_CMCFW_BUILD_DATE_OFST 1842908#define MC_CMD_GET_VERSION_V5_OUT_CMCFW_BUILD_DATE_LEN 82909#define MC_CMD_GET_VERSION_V5_OUT_CMCFW_BUILD_DATE_LO_OFST 1842910#define MC_CMD_GET_VERSION_V5_OUT_CMCFW_BUILD_DATE_LO_LEN 42911#define MC_CMD_GET_VERSION_V5_OUT_CMCFW_BUILD_DATE_LO_LBN 14722912#define MC_CMD_GET_VERSION_V5_OUT_CMCFW_BUILD_DATE_LO_WIDTH 322913#define MC_CMD_GET_VERSION_V5_OUT_CMCFW_BUILD_DATE_HI_OFST 1882914#define MC_CMD_GET_VERSION_V5_OUT_CMCFW_BUILD_DATE_HI_LEN 42915#define MC_CMD_GET_VERSION_V5_OUT_CMCFW_BUILD_DATE_HI_LBN 15042916#define MC_CMD_GET_VERSION_V5_OUT_CMCFW_BUILD_DATE_HI_WIDTH 322917/* FPGA version as three numbers. On Riverhead based systems this field uses2918 * the same encoding as hardware version ID registers (MC_FPGA_BUILD_HWRD_REG):2919 * FPGA_VERSION[0]: x => Image H{x} FPGA_VERSION[1]: Revision letter (0 => A, 12920 * => B, ...) FPGA_VERSION[2]: Sub-revision number2921 */2922#define MC_CMD_GET_VERSION_V5_OUT_FPGA_VERSION_OFST 1922923#define MC_CMD_GET_VERSION_V5_OUT_FPGA_VERSION_LEN 42924#define MC_CMD_GET_VERSION_V5_OUT_FPGA_VERSION_NUM 32925/* Extra FPGA revision information (as null-terminated US-ASCII string) */2926#define MC_CMD_GET_VERSION_V5_OUT_FPGA_EXTRA_OFST 2042927#define MC_CMD_GET_VERSION_V5_OUT_FPGA_EXTRA_LEN 162928/* Board name / adapter model (as null-terminated US-ASCII string) */2929#define MC_CMD_GET_VERSION_V5_OUT_BOARD_NAME_OFST 2202930#define MC_CMD_GET_VERSION_V5_OUT_BOARD_NAME_LEN 162931/* Board revision number */2932#define MC_CMD_GET_VERSION_V5_OUT_BOARD_REVISION_OFST 2362933#define MC_CMD_GET_VERSION_V5_OUT_BOARD_REVISION_LEN 42934/* Board serial number (as null-terminated US-ASCII string) */2935#define MC_CMD_GET_VERSION_V5_OUT_BOARD_SERIAL_OFST 2402936#define MC_CMD_GET_VERSION_V5_OUT_BOARD_SERIAL_LEN 642937/* The version of the datapath hardware design as three number - a.b.c */2938#define MC_CMD_GET_VERSION_V5_OUT_DATAPATH_HW_VERSION_OFST 3042939#define MC_CMD_GET_VERSION_V5_OUT_DATAPATH_HW_VERSION_LEN 42940#define MC_CMD_GET_VERSION_V5_OUT_DATAPATH_HW_VERSION_NUM 32941/* The version of the firmware library used to control the datapath as three2942 * number - a.b.c2943 */2944#define MC_CMD_GET_VERSION_V5_OUT_DATAPATH_FW_VERSION_OFST 3162945#define MC_CMD_GET_VERSION_V5_OUT_DATAPATH_FW_VERSION_LEN 42946#define MC_CMD_GET_VERSION_V5_OUT_DATAPATH_FW_VERSION_NUM 32947/* The SOC boot version as four numbers - a.b.c.d */2948#define MC_CMD_GET_VERSION_V5_OUT_SOC_BOOT_VERSION_OFST 3282949#define MC_CMD_GET_VERSION_V5_OUT_SOC_BOOT_VERSION_LEN 42950#define MC_CMD_GET_VERSION_V5_OUT_SOC_BOOT_VERSION_NUM 42951/* The SOC uboot version as four numbers - a.b.c.d */2952#define MC_CMD_GET_VERSION_V5_OUT_SOC_UBOOT_VERSION_OFST 3442953#define MC_CMD_GET_VERSION_V5_OUT_SOC_UBOOT_VERSION_LEN 42954#define MC_CMD_GET_VERSION_V5_OUT_SOC_UBOOT_VERSION_NUM 42955/* The SOC main rootfs version as four numbers - a.b.c.d */2956#define MC_CMD_GET_VERSION_V5_OUT_SOC_MAIN_ROOTFS_VERSION_OFST 3602957#define MC_CMD_GET_VERSION_V5_OUT_SOC_MAIN_ROOTFS_VERSION_LEN 42958#define MC_CMD_GET_VERSION_V5_OUT_SOC_MAIN_ROOTFS_VERSION_NUM 42959/* The SOC recovery buildroot version as four numbers - a.b.c.d */2960#define MC_CMD_GET_VERSION_V5_OUT_SOC_RECOVERY_BUILDROOT_VERSION_OFST 3762961#define MC_CMD_GET_VERSION_V5_OUT_SOC_RECOVERY_BUILDROOT_VERSION_LEN 42962#define MC_CMD_GET_VERSION_V5_OUT_SOC_RECOVERY_BUILDROOT_VERSION_NUM 42963/* Board version as four numbers - a.b.c.d. BOARD_VERSION[0] duplicates the2964 * BOARD_REVISION field2965 */2966#define MC_CMD_GET_VERSION_V5_OUT_BOARD_VERSION_OFST 3922967#define MC_CMD_GET_VERSION_V5_OUT_BOARD_VERSION_LEN 42968#define MC_CMD_GET_VERSION_V5_OUT_BOARD_VERSION_NUM 42969/* Bundle version as four numbers - a.b.c.d */2970#define MC_CMD_GET_VERSION_V5_OUT_BUNDLE_VERSION_OFST 4082971#define MC_CMD_GET_VERSION_V5_OUT_BUNDLE_VERSION_LEN 42972#define MC_CMD_GET_VERSION_V5_OUT_BUNDLE_VERSION_NUM 42973 2974 2975/***********************************/2976/* MC_CMD_PTP2977 * Perform PTP operation2978 */2979#define MC_CMD_PTP 0xb2980#undef MC_CMD_0xb_PRIVILEGE_CTG2981 2982#define MC_CMD_0xb_PRIVILEGE_CTG SRIOV_CTG_GENERAL2983 2984/* MC_CMD_PTP_IN msgrequest */2985#define MC_CMD_PTP_IN_LEN 12986/* PTP operation code */2987#define MC_CMD_PTP_IN_OP_OFST 02988#define MC_CMD_PTP_IN_OP_LEN 12989/* enum: Enable PTP packet timestamping operation. */2990#define MC_CMD_PTP_OP_ENABLE 0x12991/* enum: Disable PTP packet timestamping operation. */2992#define MC_CMD_PTP_OP_DISABLE 0x22993/* enum: Send a PTP packet. This operation is used on Siena and Huntington.2994 * From Medford onwards it is not supported: on those platforms PTP transmit2995 * timestamping is done using the fast path.2996 */2997#define MC_CMD_PTP_OP_TRANSMIT 0x32998/* enum: Read the current NIC time. */2999#define MC_CMD_PTP_OP_READ_NIC_TIME 0x43000/* enum: Get the current PTP status. Note that the clock frequency returned (in3001 * Hz) is rounded to the nearest MHz (e.g. 666000000 for 666666666).3002 */3003#define MC_CMD_PTP_OP_STATUS 0x53004/* enum: Adjust the PTP NIC's time. */3005#define MC_CMD_PTP_OP_ADJUST 0x63006/* enum: Synchronize host and NIC time. */3007#define MC_CMD_PTP_OP_SYNCHRONIZE 0x73008/* enum: Basic manufacturing tests. Siena PTP adapters only. */3009#define MC_CMD_PTP_OP_MANFTEST_BASIC 0x83010/* enum: Packet based manufacturing tests. Siena PTP adapters only. */3011#define MC_CMD_PTP_OP_MANFTEST_PACKET 0x93012/* enum: Reset some of the PTP related statistics */3013#define MC_CMD_PTP_OP_RESET_STATS 0xa3014/* enum: Debug operations to MC. */3015#define MC_CMD_PTP_OP_DEBUG 0xb3016/* enum: Read an FPGA register. Siena PTP adapters only. */3017#define MC_CMD_PTP_OP_FPGAREAD 0xc3018/* enum: Write an FPGA register. Siena PTP adapters only. */3019#define MC_CMD_PTP_OP_FPGAWRITE 0xd3020/* enum: Apply an offset to the NIC clock */3021#define MC_CMD_PTP_OP_CLOCK_OFFSET_ADJUST 0xe3022/* enum: Change the frequency correction applied to the NIC clock */3023#define MC_CMD_PTP_OP_CLOCK_FREQ_ADJUST 0xf3024/* enum: Set the MC packet filter VLAN tags for received PTP packets.3025 * Deprecated for Huntington onwards.3026 */3027#define MC_CMD_PTP_OP_RX_SET_VLAN_FILTER 0x103028/* enum: Set the MC packet filter UUID for received PTP packets. Deprecated for3029 * Huntington onwards.3030 */3031#define MC_CMD_PTP_OP_RX_SET_UUID_FILTER 0x113032/* enum: Set the MC packet filter Domain for received PTP packets. Deprecated3033 * for Huntington onwards.3034 */3035#define MC_CMD_PTP_OP_RX_SET_DOMAIN_FILTER 0x123036/* enum: Set the clock source. Required for snapper tests on Huntington and3037 * Medford. Not implemented for Siena or Medford2.3038 */3039#define MC_CMD_PTP_OP_SET_CLK_SRC 0x133040/* enum: Reset value of Timer Reg. Not implemented. */3041#define MC_CMD_PTP_OP_RST_CLK 0x143042/* enum: Enable the forwarding of PPS events to the host */3043#define MC_CMD_PTP_OP_PPS_ENABLE 0x153044/* enum: Get the time format used by this NIC for PTP operations */3045#define MC_CMD_PTP_OP_GET_TIME_FORMAT 0x163046/* enum: Get the clock attributes. NOTE- extended version of3047 * MC_CMD_PTP_OP_GET_TIME_FORMAT3048 */3049#define MC_CMD_PTP_OP_GET_ATTRIBUTES 0x163050/* enum: Get corrections that should be applied to the various different3051 * timestamps3052 */3053#define MC_CMD_PTP_OP_GET_TIMESTAMP_CORRECTIONS 0x173054/* enum: Subscribe to receive periodic time events indicating the current NIC3055 * time3056 */3057#define MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE 0x183058/* enum: Unsubscribe to stop receiving time events */3059#define MC_CMD_PTP_OP_TIME_EVENT_UNSUBSCRIBE 0x193060/* enum: PPS based manfacturing tests. Requires PPS output to be looped to PPS3061 * input on the same NIC. Siena PTP adapters only.3062 */3063#define MC_CMD_PTP_OP_MANFTEST_PPS 0x1a3064/* enum: Set the PTP sync status. Status is used by firmware to report to event3065 * subscribers.3066 */3067#define MC_CMD_PTP_OP_SET_SYNC_STATUS 0x1b3068/* enum: Above this for future use. */3069#define MC_CMD_PTP_OP_MAX 0x1c3070 3071/* MC_CMD_PTP_IN_ENABLE msgrequest */3072#define MC_CMD_PTP_IN_ENABLE_LEN 163073#define MC_CMD_PTP_IN_CMD_OFST 03074#define MC_CMD_PTP_IN_CMD_LEN 43075#define MC_CMD_PTP_IN_PERIPH_ID_OFST 43076#define MC_CMD_PTP_IN_PERIPH_ID_LEN 43077/* Not used, initialize to 0. Events are always sent to function relative queue3078 * 0.3079 */3080#define MC_CMD_PTP_IN_ENABLE_QUEUE_OFST 83081#define MC_CMD_PTP_IN_ENABLE_QUEUE_LEN 43082/* PTP timestamping mode. Not used from Huntington onwards. */3083#define MC_CMD_PTP_IN_ENABLE_MODE_OFST 123084#define MC_CMD_PTP_IN_ENABLE_MODE_LEN 43085/* enum: PTP, version 1 */3086#define MC_CMD_PTP_MODE_V1 0x03087/* enum: PTP, version 1, with VLAN headers - deprecated */3088#define MC_CMD_PTP_MODE_V1_VLAN 0x13089/* enum: PTP, version 2 */3090#define MC_CMD_PTP_MODE_V2 0x23091/* enum: PTP, version 2, with VLAN headers - deprecated */3092#define MC_CMD_PTP_MODE_V2_VLAN 0x33093/* enum: PTP, version 2, with improved UUID filtering */3094#define MC_CMD_PTP_MODE_V2_ENHANCED 0x43095/* enum: FCoE (seconds and microseconds) */3096#define MC_CMD_PTP_MODE_FCOE 0x53097 3098/* MC_CMD_PTP_IN_DISABLE msgrequest */3099#define MC_CMD_PTP_IN_DISABLE_LEN 83100/* MC_CMD_PTP_IN_CMD_OFST 0 */3101/* MC_CMD_PTP_IN_CMD_LEN 4 */3102/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */3103/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */3104 3105/* MC_CMD_PTP_IN_TRANSMIT msgrequest */3106#define MC_CMD_PTP_IN_TRANSMIT_LENMIN 133107#define MC_CMD_PTP_IN_TRANSMIT_LENMAX 2523108#define MC_CMD_PTP_IN_TRANSMIT_LENMAX_MCDI2 10203109#define MC_CMD_PTP_IN_TRANSMIT_LEN(num) (12+1*(num))3110#define MC_CMD_PTP_IN_TRANSMIT_PACKET_NUM(len) (((len)-12)/1)3111/* MC_CMD_PTP_IN_CMD_OFST 0 */3112/* MC_CMD_PTP_IN_CMD_LEN 4 */3113/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */3114/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */3115/* Transmit packet length */3116#define MC_CMD_PTP_IN_TRANSMIT_LENGTH_OFST 83117#define MC_CMD_PTP_IN_TRANSMIT_LENGTH_LEN 43118/* Transmit packet data */3119#define MC_CMD_PTP_IN_TRANSMIT_PACKET_OFST 123120#define MC_CMD_PTP_IN_TRANSMIT_PACKET_LEN 13121#define MC_CMD_PTP_IN_TRANSMIT_PACKET_MINNUM 13122#define MC_CMD_PTP_IN_TRANSMIT_PACKET_MAXNUM 2403123#define MC_CMD_PTP_IN_TRANSMIT_PACKET_MAXNUM_MCDI2 10083124 3125/* MC_CMD_PTP_IN_READ_NIC_TIME msgrequest */3126#define MC_CMD_PTP_IN_READ_NIC_TIME_LEN 83127/* MC_CMD_PTP_IN_CMD_OFST 0 */3128/* MC_CMD_PTP_IN_CMD_LEN 4 */3129/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */3130/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */3131 3132/* MC_CMD_PTP_IN_READ_NIC_TIME_V2 msgrequest */3133#define MC_CMD_PTP_IN_READ_NIC_TIME_V2_LEN 83134/* MC_CMD_PTP_IN_CMD_OFST 0 */3135/* MC_CMD_PTP_IN_CMD_LEN 4 */3136/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */3137/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */3138 3139/* MC_CMD_PTP_IN_STATUS msgrequest */3140#define MC_CMD_PTP_IN_STATUS_LEN 83141/* MC_CMD_PTP_IN_CMD_OFST 0 */3142/* MC_CMD_PTP_IN_CMD_LEN 4 */3143/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */3144/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */3145 3146/* MC_CMD_PTP_IN_ADJUST msgrequest */3147#define MC_CMD_PTP_IN_ADJUST_LEN 243148/* MC_CMD_PTP_IN_CMD_OFST 0 */3149/* MC_CMD_PTP_IN_CMD_LEN 4 */3150/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */3151/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */3152/* Frequency adjustment 40 bit fixed point ns */3153#define MC_CMD_PTP_IN_ADJUST_FREQ_OFST 83154#define MC_CMD_PTP_IN_ADJUST_FREQ_LEN 83155#define MC_CMD_PTP_IN_ADJUST_FREQ_LO_OFST 83156#define MC_CMD_PTP_IN_ADJUST_FREQ_LO_LEN 43157#define MC_CMD_PTP_IN_ADJUST_FREQ_LO_LBN 643158#define MC_CMD_PTP_IN_ADJUST_FREQ_LO_WIDTH 323159#define MC_CMD_PTP_IN_ADJUST_FREQ_HI_OFST 123160#define MC_CMD_PTP_IN_ADJUST_FREQ_HI_LEN 43161#define MC_CMD_PTP_IN_ADJUST_FREQ_HI_LBN 963162#define MC_CMD_PTP_IN_ADJUST_FREQ_HI_WIDTH 323163/* enum: Number of fractional bits in frequency adjustment */3164#define MC_CMD_PTP_IN_ADJUST_BITS 0x283165/* enum: Number of fractional bits in frequency adjustment when FP44_FREQ_ADJ3166 * is indicated in the MC_CMD_PTP_OUT_GET_ATTRIBUTES command CAPABILITIES3167 * field.3168 */3169#define MC_CMD_PTP_IN_ADJUST_BITS_FP44 0x2c3170/* Time adjustment in seconds */3171#define MC_CMD_PTP_IN_ADJUST_SECONDS_OFST 163172#define MC_CMD_PTP_IN_ADJUST_SECONDS_LEN 43173/* Time adjustment major value */3174#define MC_CMD_PTP_IN_ADJUST_MAJOR_OFST 163175#define MC_CMD_PTP_IN_ADJUST_MAJOR_LEN 43176/* Time adjustment in nanoseconds */3177#define MC_CMD_PTP_IN_ADJUST_NANOSECONDS_OFST 203178#define MC_CMD_PTP_IN_ADJUST_NANOSECONDS_LEN 43179/* Time adjustment minor value */3180#define MC_CMD_PTP_IN_ADJUST_MINOR_OFST 203181#define MC_CMD_PTP_IN_ADJUST_MINOR_LEN 43182 3183/* MC_CMD_PTP_IN_ADJUST_V2 msgrequest */3184#define MC_CMD_PTP_IN_ADJUST_V2_LEN 283185/* MC_CMD_PTP_IN_CMD_OFST 0 */3186/* MC_CMD_PTP_IN_CMD_LEN 4 */3187/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */3188/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */3189/* Frequency adjustment 40 bit fixed point ns */3190#define MC_CMD_PTP_IN_ADJUST_V2_FREQ_OFST 83191#define MC_CMD_PTP_IN_ADJUST_V2_FREQ_LEN 83192#define MC_CMD_PTP_IN_ADJUST_V2_FREQ_LO_OFST 83193#define MC_CMD_PTP_IN_ADJUST_V2_FREQ_LO_LEN 43194#define MC_CMD_PTP_IN_ADJUST_V2_FREQ_LO_LBN 643195#define MC_CMD_PTP_IN_ADJUST_V2_FREQ_LO_WIDTH 323196#define MC_CMD_PTP_IN_ADJUST_V2_FREQ_HI_OFST 123197#define MC_CMD_PTP_IN_ADJUST_V2_FREQ_HI_LEN 43198#define MC_CMD_PTP_IN_ADJUST_V2_FREQ_HI_LBN 963199#define MC_CMD_PTP_IN_ADJUST_V2_FREQ_HI_WIDTH 323200/* enum: Number of fractional bits in frequency adjustment */3201/* MC_CMD_PTP_IN_ADJUST_BITS 0x28 */3202/* enum: Number of fractional bits in frequency adjustment when FP44_FREQ_ADJ3203 * is indicated in the MC_CMD_PTP_OUT_GET_ATTRIBUTES command CAPABILITIES3204 * field.3205 */3206/* MC_CMD_PTP_IN_ADJUST_BITS_FP44 0x2c */3207/* Time adjustment in seconds */3208#define MC_CMD_PTP_IN_ADJUST_V2_SECONDS_OFST 163209#define MC_CMD_PTP_IN_ADJUST_V2_SECONDS_LEN 43210/* Time adjustment major value */3211#define MC_CMD_PTP_IN_ADJUST_V2_MAJOR_OFST 163212#define MC_CMD_PTP_IN_ADJUST_V2_MAJOR_LEN 43213/* Time adjustment in nanoseconds */3214#define MC_CMD_PTP_IN_ADJUST_V2_NANOSECONDS_OFST 203215#define MC_CMD_PTP_IN_ADJUST_V2_NANOSECONDS_LEN 43216/* Time adjustment minor value */3217#define MC_CMD_PTP_IN_ADJUST_V2_MINOR_OFST 203218#define MC_CMD_PTP_IN_ADJUST_V2_MINOR_LEN 43219/* Upper 32bits of major time offset adjustment */3220#define MC_CMD_PTP_IN_ADJUST_V2_MAJOR_HI_OFST 243221#define MC_CMD_PTP_IN_ADJUST_V2_MAJOR_HI_LEN 43222 3223/* MC_CMD_PTP_IN_SYNCHRONIZE msgrequest */3224#define MC_CMD_PTP_IN_SYNCHRONIZE_LEN 203225/* MC_CMD_PTP_IN_CMD_OFST 0 */3226/* MC_CMD_PTP_IN_CMD_LEN 4 */3227/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */3228/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */3229/* Number of time readings to capture */3230#define MC_CMD_PTP_IN_SYNCHRONIZE_NUMTIMESETS_OFST 83231#define MC_CMD_PTP_IN_SYNCHRONIZE_NUMTIMESETS_LEN 43232/* Host address in which to write "synchronization started" indication (643233 * bits)3234 */3235#define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_OFST 123236#define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LEN 83237#define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LO_OFST 123238#define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LO_LEN 43239#define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LO_LBN 963240#define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LO_WIDTH 323241#define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_HI_OFST 163242#define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_HI_LEN 43243#define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_HI_LBN 1283244#define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_HI_WIDTH 323245 3246/* MC_CMD_PTP_IN_MANFTEST_BASIC msgrequest */3247#define MC_CMD_PTP_IN_MANFTEST_BASIC_LEN 83248/* MC_CMD_PTP_IN_CMD_OFST 0 */3249/* MC_CMD_PTP_IN_CMD_LEN 4 */3250/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */3251/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */3252 3253/* MC_CMD_PTP_IN_MANFTEST_PACKET msgrequest */3254#define MC_CMD_PTP_IN_MANFTEST_PACKET_LEN 123255/* MC_CMD_PTP_IN_CMD_OFST 0 */3256/* MC_CMD_PTP_IN_CMD_LEN 4 */3257/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */3258/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */3259/* Enable or disable packet testing */3260#define MC_CMD_PTP_IN_MANFTEST_PACKET_TEST_ENABLE_OFST 83261#define MC_CMD_PTP_IN_MANFTEST_PACKET_TEST_ENABLE_LEN 43262 3263/* MC_CMD_PTP_IN_RESET_STATS msgrequest: Reset PTP statistics */3264#define MC_CMD_PTP_IN_RESET_STATS_LEN 83265/* MC_CMD_PTP_IN_CMD_OFST 0 */3266/* MC_CMD_PTP_IN_CMD_LEN 4 */3267/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */3268/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */3269 3270/* MC_CMD_PTP_IN_DEBUG msgrequest */3271#define MC_CMD_PTP_IN_DEBUG_LEN 123272/* MC_CMD_PTP_IN_CMD_OFST 0 */3273/* MC_CMD_PTP_IN_CMD_LEN 4 */3274/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */3275/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */3276/* Debug operations */3277#define MC_CMD_PTP_IN_DEBUG_DEBUG_PARAM_OFST 83278#define MC_CMD_PTP_IN_DEBUG_DEBUG_PARAM_LEN 43279 3280/* MC_CMD_PTP_IN_FPGAREAD msgrequest */3281#define MC_CMD_PTP_IN_FPGAREAD_LEN 163282/* MC_CMD_PTP_IN_CMD_OFST 0 */3283/* MC_CMD_PTP_IN_CMD_LEN 4 */3284/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */3285/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */3286#define MC_CMD_PTP_IN_FPGAREAD_ADDR_OFST 83287#define MC_CMD_PTP_IN_FPGAREAD_ADDR_LEN 43288#define MC_CMD_PTP_IN_FPGAREAD_NUMBYTES_OFST 123289#define MC_CMD_PTP_IN_FPGAREAD_NUMBYTES_LEN 43290 3291/* MC_CMD_PTP_IN_FPGAWRITE msgrequest */3292#define MC_CMD_PTP_IN_FPGAWRITE_LENMIN 133293#define MC_CMD_PTP_IN_FPGAWRITE_LENMAX 2523294#define MC_CMD_PTP_IN_FPGAWRITE_LENMAX_MCDI2 10203295#define MC_CMD_PTP_IN_FPGAWRITE_LEN(num) (12+1*(num))3296#define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_NUM(len) (((len)-12)/1)3297/* MC_CMD_PTP_IN_CMD_OFST 0 */3298/* MC_CMD_PTP_IN_CMD_LEN 4 */3299/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */3300/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */3301#define MC_CMD_PTP_IN_FPGAWRITE_ADDR_OFST 83302#define MC_CMD_PTP_IN_FPGAWRITE_ADDR_LEN 43303#define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_OFST 123304#define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_LEN 13305#define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_MINNUM 13306#define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_MAXNUM 2403307#define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_MAXNUM_MCDI2 10083308 3309/* MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST msgrequest */3310#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_LEN 163311/* MC_CMD_PTP_IN_CMD_OFST 0 */3312/* MC_CMD_PTP_IN_CMD_LEN 4 */3313/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */3314/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */3315/* Time adjustment in seconds */3316#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_SECONDS_OFST 83317#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_SECONDS_LEN 43318/* Time adjustment major value */3319#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_MAJOR_OFST 83320#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_MAJOR_LEN 43321/* Time adjustment in nanoseconds */3322#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_NANOSECONDS_OFST 123323#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_NANOSECONDS_LEN 43324/* Time adjustment minor value */3325#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_MINOR_OFST 123326#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_MINOR_LEN 43327 3328/* MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2 msgrequest */3329#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_LEN 203330/* MC_CMD_PTP_IN_CMD_OFST 0 */3331/* MC_CMD_PTP_IN_CMD_LEN 4 */3332/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */3333/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */3334/* Time adjustment in seconds */3335#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_SECONDS_OFST 83336#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_SECONDS_LEN 43337/* Time adjustment major value */3338#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_MAJOR_OFST 83339#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_MAJOR_LEN 43340/* Time adjustment in nanoseconds */3341#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_NANOSECONDS_OFST 123342#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_NANOSECONDS_LEN 43343/* Time adjustment minor value */3344#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_MINOR_OFST 123345#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_MINOR_LEN 43346/* Upper 32bits of major time offset adjustment */3347#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_MAJOR_HI_OFST 163348#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_MAJOR_HI_LEN 43349 3350/* MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST msgrequest */3351#define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_LEN 163352/* MC_CMD_PTP_IN_CMD_OFST 0 */3353/* MC_CMD_PTP_IN_CMD_LEN 4 */3354/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */3355/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */3356/* Frequency adjustment 40 bit fixed point ns */3357#define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_OFST 83358#define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_LEN 83359#define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_LO_OFST 83360#define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_LO_LEN 43361#define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_LO_LBN 643362#define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_LO_WIDTH 323363#define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_HI_OFST 123364#define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_HI_LEN 43365#define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_HI_LBN 963366#define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_HI_WIDTH 323367/* Enum values, see field(s): */3368/* MC_CMD_PTP/MC_CMD_PTP_IN_ADJUST/FREQ */3369 3370/* MC_CMD_PTP_IN_RX_SET_VLAN_FILTER msgrequest */3371#define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_LEN 243372/* MC_CMD_PTP_IN_CMD_OFST 0 */3373/* MC_CMD_PTP_IN_CMD_LEN 4 */3374/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */3375/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */3376/* Number of VLAN tags, 0 if not VLAN */3377#define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_NUM_VLAN_TAGS_OFST 83378#define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_NUM_VLAN_TAGS_LEN 43379/* Set of VLAN tags to filter against */3380#define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_OFST 123381#define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_LEN 43382#define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_NUM 33383 3384/* MC_CMD_PTP_IN_RX_SET_UUID_FILTER msgrequest */3385#define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_LEN 203386/* MC_CMD_PTP_IN_CMD_OFST 0 */3387/* MC_CMD_PTP_IN_CMD_LEN 4 */3388/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */3389/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */3390/* 1 to enable UUID filtering, 0 to disable */3391#define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_ENABLE_OFST 83392#define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_ENABLE_LEN 43393/* UUID to filter against */3394#define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_OFST 123395#define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_LEN 83396#define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_LO_OFST 123397#define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_LO_LEN 43398#define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_LO_LBN 963399#define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_LO_WIDTH 323400#define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_HI_OFST 163401#define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_HI_LEN 43402#define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_HI_LBN 1283403#define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_HI_WIDTH 323404 3405/* MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER msgrequest */3406#define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_LEN 163407/* MC_CMD_PTP_IN_CMD_OFST 0 */3408/* MC_CMD_PTP_IN_CMD_LEN 4 */3409/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */3410/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */3411/* 1 to enable Domain filtering, 0 to disable */3412#define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_ENABLE_OFST 83413#define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_ENABLE_LEN 43414/* Domain number to filter against */3415#define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_DOMAIN_OFST 123416#define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_DOMAIN_LEN 43417 3418/* MC_CMD_PTP_IN_SET_CLK_SRC msgrequest */3419#define MC_CMD_PTP_IN_SET_CLK_SRC_LEN 123420/* MC_CMD_PTP_IN_CMD_OFST 0 */3421/* MC_CMD_PTP_IN_CMD_LEN 4 */3422/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */3423/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */3424/* Set the clock source. */3425#define MC_CMD_PTP_IN_SET_CLK_SRC_CLK_OFST 83426#define MC_CMD_PTP_IN_SET_CLK_SRC_CLK_LEN 43427/* enum: Internal. */3428#define MC_CMD_PTP_CLK_SRC_INTERNAL 0x03429/* enum: External. */3430#define MC_CMD_PTP_CLK_SRC_EXTERNAL 0x13431 3432/* MC_CMD_PTP_IN_RST_CLK msgrequest: Reset value of Timer Reg. */3433#define MC_CMD_PTP_IN_RST_CLK_LEN 83434/* MC_CMD_PTP_IN_CMD_OFST 0 */3435/* MC_CMD_PTP_IN_CMD_LEN 4 */3436/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */3437/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */3438 3439/* MC_CMD_PTP_IN_PPS_ENABLE msgrequest */3440#define MC_CMD_PTP_IN_PPS_ENABLE_LEN 123441/* MC_CMD_PTP_IN_CMD_OFST 0 */3442/* MC_CMD_PTP_IN_CMD_LEN 4 */3443/* Enable or disable */3444#define MC_CMD_PTP_IN_PPS_ENABLE_OP_OFST 43445#define MC_CMD_PTP_IN_PPS_ENABLE_OP_LEN 43446/* enum: Enable */3447#define MC_CMD_PTP_ENABLE_PPS 0x03448/* enum: Disable */3449#define MC_CMD_PTP_DISABLE_PPS 0x13450/* Not used, initialize to 0. Events are always sent to function relative queue3451 * 0.3452 */3453#define MC_CMD_PTP_IN_PPS_ENABLE_QUEUE_ID_OFST 83454#define MC_CMD_PTP_IN_PPS_ENABLE_QUEUE_ID_LEN 43455 3456/* MC_CMD_PTP_IN_GET_TIME_FORMAT msgrequest */3457#define MC_CMD_PTP_IN_GET_TIME_FORMAT_LEN 83458/* MC_CMD_PTP_IN_CMD_OFST 0 */3459/* MC_CMD_PTP_IN_CMD_LEN 4 */3460/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */3461/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */3462 3463/* MC_CMD_PTP_IN_GET_ATTRIBUTES msgrequest */3464#define MC_CMD_PTP_IN_GET_ATTRIBUTES_LEN 83465/* MC_CMD_PTP_IN_CMD_OFST 0 */3466/* MC_CMD_PTP_IN_CMD_LEN 4 */3467/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */3468/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */3469 3470/* MC_CMD_PTP_IN_GET_TIMESTAMP_CORRECTIONS msgrequest */3471#define MC_CMD_PTP_IN_GET_TIMESTAMP_CORRECTIONS_LEN 83472/* MC_CMD_PTP_IN_CMD_OFST 0 */3473/* MC_CMD_PTP_IN_CMD_LEN 4 */3474/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */3475/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */3476 3477/* MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE msgrequest */3478#define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_LEN 123479/* MC_CMD_PTP_IN_CMD_OFST 0 */3480/* MC_CMD_PTP_IN_CMD_LEN 4 */3481/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */3482/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */3483/* Original field containing queue ID. Now extended to include flags. */3484#define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_OFST 83485#define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_LEN 43486#define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_ID_OFST 83487#define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_ID_LBN 03488#define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_ID_WIDTH 163489#define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_REPORT_SYNC_STATUS_OFST 83490#define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_REPORT_SYNC_STATUS_LBN 313491#define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_REPORT_SYNC_STATUS_WIDTH 13492 3493/* MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE msgrequest */3494#define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_LEN 163495/* MC_CMD_PTP_IN_CMD_OFST 0 */3496/* MC_CMD_PTP_IN_CMD_LEN 4 */3497/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */3498/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */3499/* Unsubscribe options */3500#define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL_OFST 83501#define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL_LEN 43502/* enum: Unsubscribe a single queue */3503#define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_SINGLE 0x03504/* enum: Unsubscribe all queues */3505#define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_ALL 0x13506/* Event queue ID */3507#define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE_OFST 123508#define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE_LEN 43509 3510/* MC_CMD_PTP_IN_MANFTEST_PPS msgrequest */3511#define MC_CMD_PTP_IN_MANFTEST_PPS_LEN 123512/* MC_CMD_PTP_IN_CMD_OFST 0 */3513/* MC_CMD_PTP_IN_CMD_LEN 4 */3514/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */3515/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */3516/* 1 to enable PPS test mode, 0 to disable and return result. */3517#define MC_CMD_PTP_IN_MANFTEST_PPS_TEST_ENABLE_OFST 83518#define MC_CMD_PTP_IN_MANFTEST_PPS_TEST_ENABLE_LEN 43519 3520/* MC_CMD_PTP_IN_SET_SYNC_STATUS msgrequest */3521#define MC_CMD_PTP_IN_SET_SYNC_STATUS_LEN 243522/* MC_CMD_PTP_IN_CMD_OFST 0 */3523/* MC_CMD_PTP_IN_CMD_LEN 4 */3524/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */3525/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */3526/* NIC - Host System Clock Synchronization status */3527#define MC_CMD_PTP_IN_SET_SYNC_STATUS_STATUS_OFST 83528#define MC_CMD_PTP_IN_SET_SYNC_STATUS_STATUS_LEN 43529/* enum: Host System clock and NIC clock are not in sync */3530#define MC_CMD_PTP_IN_SET_SYNC_STATUS_NOT_IN_SYNC 0x03531/* enum: Host System clock and NIC clock are synchronized */3532#define MC_CMD_PTP_IN_SET_SYNC_STATUS_IN_SYNC 0x13533/* If synchronized, number of seconds until clocks should be considered to be3534 * no longer in sync.3535 */3536#define MC_CMD_PTP_IN_SET_SYNC_STATUS_TIMEOUT_OFST 123537#define MC_CMD_PTP_IN_SET_SYNC_STATUS_TIMEOUT_LEN 43538#define MC_CMD_PTP_IN_SET_SYNC_STATUS_RESERVED0_OFST 163539#define MC_CMD_PTP_IN_SET_SYNC_STATUS_RESERVED0_LEN 43540#define MC_CMD_PTP_IN_SET_SYNC_STATUS_RESERVED1_OFST 203541#define MC_CMD_PTP_IN_SET_SYNC_STATUS_RESERVED1_LEN 43542 3543/* MC_CMD_PTP_OUT msgresponse */3544#define MC_CMD_PTP_OUT_LEN 03545 3546/* MC_CMD_PTP_OUT_TRANSMIT msgresponse */3547#define MC_CMD_PTP_OUT_TRANSMIT_LEN 83548/* Value of seconds timestamp */3549#define MC_CMD_PTP_OUT_TRANSMIT_SECONDS_OFST 03550#define MC_CMD_PTP_OUT_TRANSMIT_SECONDS_LEN 43551/* Timestamp major value */3552#define MC_CMD_PTP_OUT_TRANSMIT_MAJOR_OFST 03553#define MC_CMD_PTP_OUT_TRANSMIT_MAJOR_LEN 43554/* Value of nanoseconds timestamp */3555#define MC_CMD_PTP_OUT_TRANSMIT_NANOSECONDS_OFST 43556#define MC_CMD_PTP_OUT_TRANSMIT_NANOSECONDS_LEN 43557/* Timestamp minor value */3558#define MC_CMD_PTP_OUT_TRANSMIT_MINOR_OFST 43559#define MC_CMD_PTP_OUT_TRANSMIT_MINOR_LEN 43560 3561/* MC_CMD_PTP_OUT_TIME_EVENT_SUBSCRIBE msgresponse */3562#define MC_CMD_PTP_OUT_TIME_EVENT_SUBSCRIBE_LEN 03563 3564/* MC_CMD_PTP_OUT_TIME_EVENT_UNSUBSCRIBE msgresponse */3565#define MC_CMD_PTP_OUT_TIME_EVENT_UNSUBSCRIBE_LEN 03566 3567/* MC_CMD_PTP_OUT_READ_NIC_TIME msgresponse */3568#define MC_CMD_PTP_OUT_READ_NIC_TIME_LEN 83569/* Value of seconds timestamp */3570#define MC_CMD_PTP_OUT_READ_NIC_TIME_SECONDS_OFST 03571#define MC_CMD_PTP_OUT_READ_NIC_TIME_SECONDS_LEN 43572/* Timestamp major value */3573#define MC_CMD_PTP_OUT_READ_NIC_TIME_MAJOR_OFST 03574#define MC_CMD_PTP_OUT_READ_NIC_TIME_MAJOR_LEN 43575/* Value of nanoseconds timestamp */3576#define MC_CMD_PTP_OUT_READ_NIC_TIME_NANOSECONDS_OFST 43577#define MC_CMD_PTP_OUT_READ_NIC_TIME_NANOSECONDS_LEN 43578/* Timestamp minor value */3579#define MC_CMD_PTP_OUT_READ_NIC_TIME_MINOR_OFST 43580#define MC_CMD_PTP_OUT_READ_NIC_TIME_MINOR_LEN 43581 3582/* MC_CMD_PTP_OUT_READ_NIC_TIME_V2 msgresponse */3583#define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_LEN 123584/* Value of seconds timestamp */3585#define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_SECONDS_OFST 03586#define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_SECONDS_LEN 43587/* Timestamp major value */3588#define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MAJOR_OFST 03589#define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MAJOR_LEN 43590/* Value of nanoseconds timestamp */3591#define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_NANOSECONDS_OFST 43592#define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_NANOSECONDS_LEN 43593/* Timestamp minor value */3594#define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MINOR_OFST 43595#define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MINOR_LEN 43596/* Upper 32bits of major timestamp value */3597#define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MAJOR_HI_OFST 83598#define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MAJOR_HI_LEN 43599 3600/* MC_CMD_PTP_OUT_STATUS msgresponse */3601#define MC_CMD_PTP_OUT_STATUS_LEN 643602/* Frequency of NIC's hardware clock */3603#define MC_CMD_PTP_OUT_STATUS_CLOCK_FREQ_OFST 03604#define MC_CMD_PTP_OUT_STATUS_CLOCK_FREQ_LEN 43605/* Number of packets transmitted and timestamped */3606#define MC_CMD_PTP_OUT_STATUS_STATS_TX_OFST 43607#define MC_CMD_PTP_OUT_STATUS_STATS_TX_LEN 43608/* Number of packets received and timestamped */3609#define MC_CMD_PTP_OUT_STATUS_STATS_RX_OFST 83610#define MC_CMD_PTP_OUT_STATUS_STATS_RX_LEN 43611/* Number of packets timestamped by the FPGA */3612#define MC_CMD_PTP_OUT_STATUS_STATS_TS_OFST 123613#define MC_CMD_PTP_OUT_STATUS_STATS_TS_LEN 43614/* Number of packets filter matched */3615#define MC_CMD_PTP_OUT_STATUS_STATS_FM_OFST 163616#define MC_CMD_PTP_OUT_STATUS_STATS_FM_LEN 43617/* Number of packets not filter matched */3618#define MC_CMD_PTP_OUT_STATUS_STATS_NFM_OFST 203619#define MC_CMD_PTP_OUT_STATUS_STATS_NFM_LEN 43620/* Number of PPS overflows (noise on input?) */3621#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFLOW_OFST 243622#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFLOW_LEN 43623/* Number of PPS bad periods */3624#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_BAD_OFST 283625#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_BAD_LEN 43626/* Minimum period of PPS pulse in nanoseconds */3627#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MIN_OFST 323628#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MIN_LEN 43629/* Maximum period of PPS pulse in nanoseconds */3630#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MAX_OFST 363631#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MAX_LEN 43632/* Last period of PPS pulse in nanoseconds */3633#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_LAST_OFST 403634#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_LAST_LEN 43635/* Mean period of PPS pulse in nanoseconds */3636#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MEAN_OFST 443637#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MEAN_LEN 43638/* Minimum offset of PPS pulse in nanoseconds (signed) */3639#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MIN_OFST 483640#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MIN_LEN 43641/* Maximum offset of PPS pulse in nanoseconds (signed) */3642#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MAX_OFST 523643#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MAX_LEN 43644/* Last offset of PPS pulse in nanoseconds (signed) */3645#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_LAST_OFST 563646#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_LAST_LEN 43647/* Mean offset of PPS pulse in nanoseconds (signed) */3648#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MEAN_OFST 603649#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MEAN_LEN 43650 3651/* MC_CMD_PTP_OUT_SYNCHRONIZE msgresponse */3652#define MC_CMD_PTP_OUT_SYNCHRONIZE_LENMIN 203653#define MC_CMD_PTP_OUT_SYNCHRONIZE_LENMAX 2403654#define MC_CMD_PTP_OUT_SYNCHRONIZE_LENMAX_MCDI2 10203655#define MC_CMD_PTP_OUT_SYNCHRONIZE_LEN(num) (0+20*(num))3656#define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_NUM(len) (((len)-0)/20)3657/* A set of host and NIC times */3658#define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_OFST 03659#define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_LEN 203660#define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_MINNUM 13661#define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_MAXNUM 123662#define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_MAXNUM_MCDI2 513663/* Host time immediately before NIC's hardware clock read */3664#define MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTSTART_OFST 03665#define MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTSTART_LEN 43666/* Value of seconds timestamp */3667#define MC_CMD_PTP_OUT_SYNCHRONIZE_SECONDS_OFST 43668#define MC_CMD_PTP_OUT_SYNCHRONIZE_SECONDS_LEN 43669/* Timestamp major value */3670#define MC_CMD_PTP_OUT_SYNCHRONIZE_MAJOR_OFST 43671#define MC_CMD_PTP_OUT_SYNCHRONIZE_MAJOR_LEN 43672/* Value of nanoseconds timestamp */3673#define MC_CMD_PTP_OUT_SYNCHRONIZE_NANOSECONDS_OFST 83674#define MC_CMD_PTP_OUT_SYNCHRONIZE_NANOSECONDS_LEN 43675/* Timestamp minor value */3676#define MC_CMD_PTP_OUT_SYNCHRONIZE_MINOR_OFST 83677#define MC_CMD_PTP_OUT_SYNCHRONIZE_MINOR_LEN 43678/* Host time immediately after NIC's hardware clock read */3679#define MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTEND_OFST 123680#define MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTEND_LEN 43681/* Number of nanoseconds waited after reading NIC's hardware clock */3682#define MC_CMD_PTP_OUT_SYNCHRONIZE_WAITNS_OFST 163683#define MC_CMD_PTP_OUT_SYNCHRONIZE_WAITNS_LEN 43684 3685/* MC_CMD_PTP_OUT_MANFTEST_BASIC msgresponse */3686#define MC_CMD_PTP_OUT_MANFTEST_BASIC_LEN 83687/* Results of testing */3688#define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_RESULT_OFST 03689#define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_RESULT_LEN 43690/* enum: Successful test */3691#define MC_CMD_PTP_MANF_SUCCESS 0x03692/* enum: FPGA load failed */3693#define MC_CMD_PTP_MANF_FPGA_LOAD 0x13694/* enum: FPGA version invalid */3695#define MC_CMD_PTP_MANF_FPGA_VERSION 0x23696/* enum: FPGA registers incorrect */3697#define MC_CMD_PTP_MANF_FPGA_REGISTERS 0x33698/* enum: Oscillator possibly not working? */3699#define MC_CMD_PTP_MANF_OSCILLATOR 0x43700/* enum: Timestamps not increasing */3701#define MC_CMD_PTP_MANF_TIMESTAMPS 0x53702/* enum: Mismatched packet count */3703#define MC_CMD_PTP_MANF_PACKET_COUNT 0x63704/* enum: Mismatched packet count (Siena filter and FPGA) */3705#define MC_CMD_PTP_MANF_FILTER_COUNT 0x73706/* enum: Not enough packets to perform timestamp check */3707#define MC_CMD_PTP_MANF_PACKET_ENOUGH 0x83708/* enum: Timestamp trigger GPIO not working */3709#define MC_CMD_PTP_MANF_GPIO_TRIGGER 0x93710/* enum: Insufficient PPS events to perform checks */3711#define MC_CMD_PTP_MANF_PPS_ENOUGH 0xa3712/* enum: PPS time event period not sufficiently close to 1s. */3713#define MC_CMD_PTP_MANF_PPS_PERIOD 0xb3714/* enum: PPS time event nS reading not sufficiently close to zero. */3715#define MC_CMD_PTP_MANF_PPS_NS 0xc3716/* enum: PTP peripheral registers incorrect */3717#define MC_CMD_PTP_MANF_REGISTERS 0xd3718/* enum: Failed to read time from PTP peripheral */3719#define MC_CMD_PTP_MANF_CLOCK_READ 0xe3720/* Presence of external oscillator */3721#define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_EXTOSC_OFST 43722#define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_EXTOSC_LEN 43723 3724/* MC_CMD_PTP_OUT_MANFTEST_PACKET msgresponse */3725#define MC_CMD_PTP_OUT_MANFTEST_PACKET_LEN 123726/* Results of testing */3727#define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_RESULT_OFST 03728#define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_RESULT_LEN 43729/* Number of packets received by FPGA */3730#define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FPGACOUNT_OFST 43731#define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FPGACOUNT_LEN 43732/* Number of packets received by Siena filters */3733#define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FILTERCOUNT_OFST 83734#define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FILTERCOUNT_LEN 43735 3736/* MC_CMD_PTP_OUT_FPGAREAD msgresponse */3737#define MC_CMD_PTP_OUT_FPGAREAD_LENMIN 13738#define MC_CMD_PTP_OUT_FPGAREAD_LENMAX 2523739#define MC_CMD_PTP_OUT_FPGAREAD_LENMAX_MCDI2 10203740#define MC_CMD_PTP_OUT_FPGAREAD_LEN(num) (0+1*(num))3741#define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_NUM(len) (((len)-0)/1)3742#define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_OFST 03743#define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_LEN 13744#define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_MINNUM 13745#define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_MAXNUM 2523746#define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_MAXNUM_MCDI2 10203747 3748/* MC_CMD_PTP_OUT_GET_TIME_FORMAT msgresponse */3749#define MC_CMD_PTP_OUT_GET_TIME_FORMAT_LEN 43750/* Time format required/used by for this NIC. Applies to all PTP MCDI3751 * operations that pass times between the host and firmware. If this operation3752 * is not supported (older firmware) a format of seconds and nanoseconds should3753 * be assumed. Note this enum is deprecated. Do not add to it- use the3754 * TIME_FORMAT field in MC_CMD_PTP_OUT_GET_ATTRIBUTES instead.3755 */3756#define MC_CMD_PTP_OUT_GET_TIME_FORMAT_FORMAT_OFST 03757#define MC_CMD_PTP_OUT_GET_TIME_FORMAT_FORMAT_LEN 43758/* enum: Times are in seconds and nanoseconds */3759#define MC_CMD_PTP_OUT_GET_TIME_FORMAT_SECONDS_NANOSECONDS 0x03760/* enum: Major register has units of 16 second per tick, minor 8 ns per tick */3761#define MC_CMD_PTP_OUT_GET_TIME_FORMAT_16SECONDS_8NANOSECONDS 0x13762/* enum: Major register has units of seconds, minor 2^-27s per tick */3763#define MC_CMD_PTP_OUT_GET_TIME_FORMAT_SECONDS_27FRACTION 0x23764 3765/* MC_CMD_PTP_OUT_GET_ATTRIBUTES msgresponse */3766#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_LEN 243767/* Time format required/used by for this NIC. Applies to all PTP MCDI3768 * operations that pass times between the host and firmware. If this operation3769 * is not supported (older firmware) a format of seconds and nanoseconds should3770 * be assumed.3771 */3772#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_TIME_FORMAT_OFST 03773#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_TIME_FORMAT_LEN 43774/* enum: Times are in seconds and nanoseconds */3775#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SECONDS_NANOSECONDS 0x03776/* enum: Major register has units of 16 second per tick, minor 8 ns per tick */3777#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_16SECONDS_8NANOSECONDS 0x13778/* enum: Major register has units of seconds, minor 2^-27s per tick */3779#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SECONDS_27FRACTION 0x23780/* enum: Major register units are seconds, minor units are quarter nanoseconds3781 */3782#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SECONDS_QTR_NANOSECONDS 0x33783/* Minimum acceptable value for a corrected synchronization timeset. When3784 * comparing host and NIC clock times, the MC returns a set of samples that3785 * contain the host start and end time, the MC time when the host start was3786 * detected and the time the MC waited between reading the time and detecting3787 * the host end. The corrected sync window is the difference between the host3788 * end and start times minus the time that the MC waited for host end.3789 */3790#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SYNC_WINDOW_MIN_OFST 43791#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SYNC_WINDOW_MIN_LEN 43792/* Various PTP capabilities */3793#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_CAPABILITIES_OFST 83794#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_CAPABILITIES_LEN 43795#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_REPORT_SYNC_STATUS_OFST 83796#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_REPORT_SYNC_STATUS_LBN 03797#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_REPORT_SYNC_STATUS_WIDTH 13798#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RX_TSTAMP_OOB_OFST 83799#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RX_TSTAMP_OOB_LBN 13800#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RX_TSTAMP_OOB_WIDTH 13801#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_64BIT_SECONDS_OFST 83802#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_64BIT_SECONDS_LBN 23803#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_64BIT_SECONDS_WIDTH 13804#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_FP44_FREQ_ADJ_OFST 83805#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_FP44_FREQ_ADJ_LBN 33806#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_FP44_FREQ_ADJ_WIDTH 13807#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED0_OFST 123808#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED0_LEN 43809#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED1_OFST 163810#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED1_LEN 43811#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED2_OFST 203812#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED2_LEN 43813 3814/* MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2 msgresponse */3815#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_LEN 403816/* Time format required/used by for this NIC. Applies to all PTP MCDI3817 * operations that pass times between the host and firmware. If this operation3818 * is not supported (older firmware) a format of seconds and nanoseconds should3819 * be assumed.3820 */3821#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_TIME_FORMAT_OFST 03822#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_TIME_FORMAT_LEN 43823/* enum: Times are in seconds and nanoseconds */3824#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_SECONDS_NANOSECONDS 0x03825/* enum: Major register has units of 16 second per tick, minor 8 ns per tick */3826#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_16SECONDS_8NANOSECONDS 0x13827/* enum: Major register has units of seconds, minor 2^-27s per tick */3828#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_SECONDS_27FRACTION 0x23829/* enum: Major register units are seconds, minor units are quarter nanoseconds3830 */3831#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_SECONDS_QTR_NANOSECONDS 0x33832/* Minimum acceptable value for a corrected synchronization timeset. When3833 * comparing host and NIC clock times, the MC returns a set of samples that3834 * contain the host start and end time, the MC time when the host start was3835 * detected and the time the MC waited between reading the time and detecting3836 * the host end. The corrected sync window is the difference between the host3837 * end and start times minus the time that the MC waited for host end.3838 */3839#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_SYNC_WINDOW_MIN_OFST 43840#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_SYNC_WINDOW_MIN_LEN 43841/* Various PTP capabilities */3842#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_CAPABILITIES_OFST 83843#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_CAPABILITIES_LEN 43844#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_REPORT_SYNC_STATUS_OFST 83845#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_REPORT_SYNC_STATUS_LBN 03846#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_REPORT_SYNC_STATUS_WIDTH 13847#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_RX_TSTAMP_OOB_OFST 83848#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_RX_TSTAMP_OOB_LBN 13849#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_RX_TSTAMP_OOB_WIDTH 13850#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_64BIT_SECONDS_OFST 83851#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_64BIT_SECONDS_LBN 23852#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_64BIT_SECONDS_WIDTH 13853#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_FP44_FREQ_ADJ_OFST 83854#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_FP44_FREQ_ADJ_LBN 33855#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_FP44_FREQ_ADJ_WIDTH 13856#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_RESERVED0_OFST 123857#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_RESERVED0_LEN 43858#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_RESERVED1_OFST 163859#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_RESERVED1_LEN 43860#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_RESERVED2_OFST 203861#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_RESERVED2_LEN 43862/* Minimum supported value for the FREQ field in3863 * MC_CMD_PTP/MC_CMD_PTP_IN_ADJUST and3864 * MC_CMD_PTP/MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST message requests. If this message3865 * response is not supported a value of -0.1 ns should be assumed, which is3866 * equivalent to a -10% adjustment.3867 */3868#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_FREQ_ADJ_MIN_OFST 243869#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_FREQ_ADJ_MIN_LEN 83870#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_FREQ_ADJ_MIN_LO_OFST 243871#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_FREQ_ADJ_MIN_LO_LEN 43872#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_FREQ_ADJ_MIN_LO_LBN 1923873#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_FREQ_ADJ_MIN_LO_WIDTH 323874#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_FREQ_ADJ_MIN_HI_OFST 283875#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_FREQ_ADJ_MIN_HI_LEN 43876#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_FREQ_ADJ_MIN_HI_LBN 2243877#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_FREQ_ADJ_MIN_HI_WIDTH 323878/* Maximum supported value for the FREQ field in3879 * MC_CMD_PTP/MC_CMD_PTP_IN_ADJUST and3880 * MC_CMD_PTP/MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST message requests. If this message3881 * response is not supported a value of 0.1 ns should be assumed, which is3882 * equivalent to a +10% adjustment.3883 */3884#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_FREQ_ADJ_MAX_OFST 323885#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_FREQ_ADJ_MAX_LEN 83886#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_FREQ_ADJ_MAX_LO_OFST 323887#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_FREQ_ADJ_MAX_LO_LEN 43888#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_FREQ_ADJ_MAX_LO_LBN 2563889#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_FREQ_ADJ_MAX_LO_WIDTH 323890#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_FREQ_ADJ_MAX_HI_OFST 363891#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_FREQ_ADJ_MAX_HI_LEN 43892#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_FREQ_ADJ_MAX_HI_LBN 2883893#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_FREQ_ADJ_MAX_HI_WIDTH 323894 3895/* MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS msgresponse */3896#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_LEN 163897/* Uncorrected error on PTP transmit timestamps in NIC clock format */3898#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_TRANSMIT_OFST 03899#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_TRANSMIT_LEN 43900/* Uncorrected error on PTP receive timestamps in NIC clock format */3901#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_RECEIVE_OFST 43902#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_RECEIVE_LEN 43903/* Uncorrected error on PPS output in NIC clock format */3904#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_OUT_OFST 83905#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_OUT_LEN 43906/* Uncorrected error on PPS input in NIC clock format */3907#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_IN_OFST 123908#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_IN_LEN 43909 3910/* MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2 msgresponse */3911#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_LEN 243912/* Uncorrected error on PTP transmit timestamps in NIC clock format */3913#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PTP_TX_OFST 03914#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PTP_TX_LEN 43915/* Uncorrected error on PTP receive timestamps in NIC clock format */3916#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PTP_RX_OFST 43917#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PTP_RX_LEN 43918/* Uncorrected error on PPS output in NIC clock format */3919#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PPS_OUT_OFST 83920#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PPS_OUT_LEN 43921/* Uncorrected error on PPS input in NIC clock format */3922#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PPS_IN_OFST 123923#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PPS_IN_LEN 43924/* Uncorrected error on non-PTP transmit timestamps in NIC clock format */3925#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_GENERAL_TX_OFST 163926#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_GENERAL_TX_LEN 43927/* Uncorrected error on non-PTP receive timestamps in NIC clock format */3928#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_GENERAL_RX_OFST 203929#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_GENERAL_RX_LEN 43930 3931/* MC_CMD_PTP_OUT_MANFTEST_PPS msgresponse */3932#define MC_CMD_PTP_OUT_MANFTEST_PPS_LEN 43933/* Results of testing */3934#define MC_CMD_PTP_OUT_MANFTEST_PPS_TEST_RESULT_OFST 03935#define MC_CMD_PTP_OUT_MANFTEST_PPS_TEST_RESULT_LEN 43936/* Enum values, see field(s): */3937/* MC_CMD_PTP_OUT_MANFTEST_BASIC/TEST_RESULT */3938 3939/* MC_CMD_PTP_OUT_SET_SYNC_STATUS msgresponse */3940#define MC_CMD_PTP_OUT_SET_SYNC_STATUS_LEN 03941 3942 3943/***********************************/3944/* MC_CMD_CSR_READ323945 * Read 32bit words from the indirect memory map.3946 */3947#define MC_CMD_CSR_READ32 0xc3948#undef MC_CMD_0xc_PRIVILEGE_CTG3949 3950#define MC_CMD_0xc_PRIVILEGE_CTG SRIOV_CTG_INSECURE3951 3952/* MC_CMD_CSR_READ32_IN msgrequest */3953#define MC_CMD_CSR_READ32_IN_LEN 123954/* Address */3955#define MC_CMD_CSR_READ32_IN_ADDR_OFST 03956#define MC_CMD_CSR_READ32_IN_ADDR_LEN 43957#define MC_CMD_CSR_READ32_IN_STEP_OFST 43958#define MC_CMD_CSR_READ32_IN_STEP_LEN 43959#define MC_CMD_CSR_READ32_IN_NUMWORDS_OFST 83960#define MC_CMD_CSR_READ32_IN_NUMWORDS_LEN 43961 3962/* MC_CMD_CSR_READ32_OUT msgresponse */3963#define MC_CMD_CSR_READ32_OUT_LENMIN 43964#define MC_CMD_CSR_READ32_OUT_LENMAX 2523965#define MC_CMD_CSR_READ32_OUT_LENMAX_MCDI2 10203966#define MC_CMD_CSR_READ32_OUT_LEN(num) (0+4*(num))3967#define MC_CMD_CSR_READ32_OUT_BUFFER_NUM(len) (((len)-0)/4)3968/* The last dword is the status, not a value read */3969#define MC_CMD_CSR_READ32_OUT_BUFFER_OFST 03970#define MC_CMD_CSR_READ32_OUT_BUFFER_LEN 43971#define MC_CMD_CSR_READ32_OUT_BUFFER_MINNUM 13972#define MC_CMD_CSR_READ32_OUT_BUFFER_MAXNUM 633973#define MC_CMD_CSR_READ32_OUT_BUFFER_MAXNUM_MCDI2 2553974 3975 3976/***********************************/3977/* MC_CMD_CSR_WRITE323978 * Write 32bit dwords to the indirect memory map.3979 */3980#define MC_CMD_CSR_WRITE32 0xd3981#undef MC_CMD_0xd_PRIVILEGE_CTG3982 3983#define MC_CMD_0xd_PRIVILEGE_CTG SRIOV_CTG_INSECURE3984 3985/* MC_CMD_CSR_WRITE32_IN msgrequest */3986#define MC_CMD_CSR_WRITE32_IN_LENMIN 123987#define MC_CMD_CSR_WRITE32_IN_LENMAX 2523988#define MC_CMD_CSR_WRITE32_IN_LENMAX_MCDI2 10203989#define MC_CMD_CSR_WRITE32_IN_LEN(num) (8+4*(num))3990#define MC_CMD_CSR_WRITE32_IN_BUFFER_NUM(len) (((len)-8)/4)3991/* Address */3992#define MC_CMD_CSR_WRITE32_IN_ADDR_OFST 03993#define MC_CMD_CSR_WRITE32_IN_ADDR_LEN 43994#define MC_CMD_CSR_WRITE32_IN_STEP_OFST 43995#define MC_CMD_CSR_WRITE32_IN_STEP_LEN 43996#define MC_CMD_CSR_WRITE32_IN_BUFFER_OFST 83997#define MC_CMD_CSR_WRITE32_IN_BUFFER_LEN 43998#define MC_CMD_CSR_WRITE32_IN_BUFFER_MINNUM 13999#define MC_CMD_CSR_WRITE32_IN_BUFFER_MAXNUM 614000#define MC_CMD_CSR_WRITE32_IN_BUFFER_MAXNUM_MCDI2 2534001 4002/* MC_CMD_CSR_WRITE32_OUT msgresponse */4003#define MC_CMD_CSR_WRITE32_OUT_LEN 44004#define MC_CMD_CSR_WRITE32_OUT_STATUS_OFST 04005#define MC_CMD_CSR_WRITE32_OUT_STATUS_LEN 44006 4007 4008/***********************************/4009/* MC_CMD_HP4010 * These commands are used for HP related features. They are grouped under one4011 * MCDI command to avoid creating too many MCDI commands.4012 */4013#define MC_CMD_HP 0x544014#undef MC_CMD_0x54_PRIVILEGE_CTG4015 4016#define MC_CMD_0x54_PRIVILEGE_CTG SRIOV_CTG_ADMIN4017 4018/* MC_CMD_HP_IN msgrequest */4019#define MC_CMD_HP_IN_LEN 164020/* HP OCSD sub-command. When address is not NULL, request activation of OCSD at4021 * the specified address with the specified interval.When address is NULL,4022 * INTERVAL is interpreted as a command: 0: stop OCSD / 1: Report OCSD current4023 * state / 2: (debug) Show temperature reported by one of the supported4024 * sensors.4025 */4026#define MC_CMD_HP_IN_SUBCMD_OFST 04027#define MC_CMD_HP_IN_SUBCMD_LEN 44028/* enum: OCSD (Option Card Sensor Data) sub-command. */4029#define MC_CMD_HP_IN_OCSD_SUBCMD 0x04030/* enum: Last known valid HP sub-command. */4031#define MC_CMD_HP_IN_LAST_SUBCMD 0x04032/* The address to the array of sensor fields. (Or NULL to use a sub-command.)4033 */4034#define MC_CMD_HP_IN_OCSD_ADDR_OFST 44035#define MC_CMD_HP_IN_OCSD_ADDR_LEN 84036#define MC_CMD_HP_IN_OCSD_ADDR_LO_OFST 44037#define MC_CMD_HP_IN_OCSD_ADDR_LO_LEN 44038#define MC_CMD_HP_IN_OCSD_ADDR_LO_LBN 324039#define MC_CMD_HP_IN_OCSD_ADDR_LO_WIDTH 324040#define MC_CMD_HP_IN_OCSD_ADDR_HI_OFST 84041#define MC_CMD_HP_IN_OCSD_ADDR_HI_LEN 44042#define MC_CMD_HP_IN_OCSD_ADDR_HI_LBN 644043#define MC_CMD_HP_IN_OCSD_ADDR_HI_WIDTH 324044/* The requested update interval, in seconds. (Or the sub-command if ADDR is4045 * NULL.)4046 */4047#define MC_CMD_HP_IN_OCSD_INTERVAL_OFST 124048#define MC_CMD_HP_IN_OCSD_INTERVAL_LEN 44049 4050/* MC_CMD_HP_OUT msgresponse */4051#define MC_CMD_HP_OUT_LEN 44052#define MC_CMD_HP_OUT_OCSD_STATUS_OFST 04053#define MC_CMD_HP_OUT_OCSD_STATUS_LEN 44054/* enum: OCSD stopped for this card. */4055#define MC_CMD_HP_OUT_OCSD_STOPPED 0x14056/* enum: OCSD was successfully started with the address provided. */4057#define MC_CMD_HP_OUT_OCSD_STARTED 0x24058/* enum: OCSD was already started for this card. */4059#define MC_CMD_HP_OUT_OCSD_ALREADY_STARTED 0x34060 4061 4062/***********************************/4063/* MC_CMD_STACKINFO4064 * Get stack information.4065 */4066#define MC_CMD_STACKINFO 0xf4067#undef MC_CMD_0xf_PRIVILEGE_CTG4068 4069#define MC_CMD_0xf_PRIVILEGE_CTG SRIOV_CTG_ADMIN4070 4071/* MC_CMD_STACKINFO_IN msgrequest */4072#define MC_CMD_STACKINFO_IN_LEN 04073 4074/* MC_CMD_STACKINFO_OUT msgresponse */4075#define MC_CMD_STACKINFO_OUT_LENMIN 124076#define MC_CMD_STACKINFO_OUT_LENMAX 2524077#define MC_CMD_STACKINFO_OUT_LENMAX_MCDI2 10204078#define MC_CMD_STACKINFO_OUT_LEN(num) (0+12*(num))4079#define MC_CMD_STACKINFO_OUT_THREAD_INFO_NUM(len) (((len)-0)/12)4080/* (thread ptr, stack size, free space) for each thread in system */4081#define MC_CMD_STACKINFO_OUT_THREAD_INFO_OFST 04082#define MC_CMD_STACKINFO_OUT_THREAD_INFO_LEN 124083#define MC_CMD_STACKINFO_OUT_THREAD_INFO_MINNUM 14084#define MC_CMD_STACKINFO_OUT_THREAD_INFO_MAXNUM 214085#define MC_CMD_STACKINFO_OUT_THREAD_INFO_MAXNUM_MCDI2 854086 4087 4088/***********************************/4089/* MC_CMD_MDIO_READ4090 * MDIO register read.4091 */4092#define MC_CMD_MDIO_READ 0x104093#undef MC_CMD_0x10_PRIVILEGE_CTG4094 4095#define MC_CMD_0x10_PRIVILEGE_CTG SRIOV_CTG_GENERAL4096 4097/* MC_CMD_MDIO_READ_IN msgrequest */4098#define MC_CMD_MDIO_READ_IN_LEN 164099/* Bus number; there are two MDIO buses: one for the internal PHY, and one for4100 * external devices.4101 */4102#define MC_CMD_MDIO_READ_IN_BUS_OFST 04103#define MC_CMD_MDIO_READ_IN_BUS_LEN 44104/* enum: Internal. */4105#define MC_CMD_MDIO_BUS_INTERNAL 0x04106/* enum: External. */4107#define MC_CMD_MDIO_BUS_EXTERNAL 0x14108/* Port address */4109#define MC_CMD_MDIO_READ_IN_PRTAD_OFST 44110#define MC_CMD_MDIO_READ_IN_PRTAD_LEN 44111/* Device Address or clause 22. */4112#define MC_CMD_MDIO_READ_IN_DEVAD_OFST 84113#define MC_CMD_MDIO_READ_IN_DEVAD_LEN 44114/* enum: By default all the MCDI MDIO operations perform clause45 mode. If you4115 * want to use clause22 then set DEVAD = MC_CMD_MDIO_CLAUSE22.4116 */4117#define MC_CMD_MDIO_CLAUSE22 0x204118/* Address */4119#define MC_CMD_MDIO_READ_IN_ADDR_OFST 124120#define MC_CMD_MDIO_READ_IN_ADDR_LEN 44121 4122/* MC_CMD_MDIO_READ_OUT msgresponse */4123#define MC_CMD_MDIO_READ_OUT_LEN 84124/* Value */4125#define MC_CMD_MDIO_READ_OUT_VALUE_OFST 04126#define MC_CMD_MDIO_READ_OUT_VALUE_LEN 44127/* Status the MDIO commands return the raw status bits from the MDIO block. A4128 * "good" transaction should have the DONE bit set and all other bits clear.4129 */4130#define MC_CMD_MDIO_READ_OUT_STATUS_OFST 44131#define MC_CMD_MDIO_READ_OUT_STATUS_LEN 44132/* enum: Good. */4133#define MC_CMD_MDIO_STATUS_GOOD 0x84134 4135 4136/***********************************/4137/* MC_CMD_MDIO_WRITE4138 * MDIO register write.4139 */4140#define MC_CMD_MDIO_WRITE 0x114141#undef MC_CMD_0x11_PRIVILEGE_CTG4142 4143#define MC_CMD_0x11_PRIVILEGE_CTG SRIOV_CTG_ADMIN4144 4145/* MC_CMD_MDIO_WRITE_IN msgrequest */4146#define MC_CMD_MDIO_WRITE_IN_LEN 204147/* Bus number; there are two MDIO buses: one for the internal PHY, and one for4148 * external devices.4149 */4150#define MC_CMD_MDIO_WRITE_IN_BUS_OFST 04151#define MC_CMD_MDIO_WRITE_IN_BUS_LEN 44152/* enum: Internal. */4153/* MC_CMD_MDIO_BUS_INTERNAL 0x0 */4154/* enum: External. */4155/* MC_CMD_MDIO_BUS_EXTERNAL 0x1 */4156/* Port address */4157#define MC_CMD_MDIO_WRITE_IN_PRTAD_OFST 44158#define MC_CMD_MDIO_WRITE_IN_PRTAD_LEN 44159/* Device Address or clause 22. */4160#define MC_CMD_MDIO_WRITE_IN_DEVAD_OFST 84161#define MC_CMD_MDIO_WRITE_IN_DEVAD_LEN 44162/* enum: By default all the MCDI MDIO operations perform clause45 mode. If you4163 * want to use clause22 then set DEVAD = MC_CMD_MDIO_CLAUSE22.4164 */4165/* MC_CMD_MDIO_CLAUSE22 0x20 */4166/* Address */4167#define MC_CMD_MDIO_WRITE_IN_ADDR_OFST 124168#define MC_CMD_MDIO_WRITE_IN_ADDR_LEN 44169/* Value */4170#define MC_CMD_MDIO_WRITE_IN_VALUE_OFST 164171#define MC_CMD_MDIO_WRITE_IN_VALUE_LEN 44172 4173/* MC_CMD_MDIO_WRITE_OUT msgresponse */4174#define MC_CMD_MDIO_WRITE_OUT_LEN 44175/* Status; the MDIO commands return the raw status bits from the MDIO block. A4176 * "good" transaction should have the DONE bit set and all other bits clear.4177 */4178#define MC_CMD_MDIO_WRITE_OUT_STATUS_OFST 04179#define MC_CMD_MDIO_WRITE_OUT_STATUS_LEN 44180/* enum: Good. */4181/* MC_CMD_MDIO_STATUS_GOOD 0x8 */4182 4183 4184/***********************************/4185/* MC_CMD_DBI_WRITE4186 * Write DBI register(s).4187 */4188#define MC_CMD_DBI_WRITE 0x124189#undef MC_CMD_0x12_PRIVILEGE_CTG4190 4191#define MC_CMD_0x12_PRIVILEGE_CTG SRIOV_CTG_INSECURE4192 4193/* MC_CMD_DBI_WRITE_IN msgrequest */4194#define MC_CMD_DBI_WRITE_IN_LENMIN 124195#define MC_CMD_DBI_WRITE_IN_LENMAX 2524196#define MC_CMD_DBI_WRITE_IN_LENMAX_MCDI2 10204197#define MC_CMD_DBI_WRITE_IN_LEN(num) (0+12*(num))4198#define MC_CMD_DBI_WRITE_IN_DBIWROP_NUM(len) (((len)-0)/12)4199/* Each write op consists of an address (offset 0), byte enable/VF/CS2 (offset4200 * 32) and value (offset 64). See MC_CMD_DBIWROP_TYPEDEF.4201 */4202#define MC_CMD_DBI_WRITE_IN_DBIWROP_OFST 04203#define MC_CMD_DBI_WRITE_IN_DBIWROP_LEN 124204#define MC_CMD_DBI_WRITE_IN_DBIWROP_MINNUM 14205#define MC_CMD_DBI_WRITE_IN_DBIWROP_MAXNUM 214206#define MC_CMD_DBI_WRITE_IN_DBIWROP_MAXNUM_MCDI2 854207 4208/* MC_CMD_DBI_WRITE_OUT msgresponse */4209#define MC_CMD_DBI_WRITE_OUT_LEN 04210 4211/* MC_CMD_DBIWROP_TYPEDEF structuredef */4212#define MC_CMD_DBIWROP_TYPEDEF_LEN 124213#define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_OFST 04214#define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_LEN 44215#define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_LBN 04216#define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_WIDTH 324217#define MC_CMD_DBIWROP_TYPEDEF_PARMS_OFST 44218#define MC_CMD_DBIWROP_TYPEDEF_PARMS_LEN 44219#define MC_CMD_DBIWROP_TYPEDEF_VF_NUM_OFST 44220#define MC_CMD_DBIWROP_TYPEDEF_VF_NUM_LBN 164221#define MC_CMD_DBIWROP_TYPEDEF_VF_NUM_WIDTH 164222#define MC_CMD_DBIWROP_TYPEDEF_VF_ACTIVE_OFST 44223#define MC_CMD_DBIWROP_TYPEDEF_VF_ACTIVE_LBN 154224#define MC_CMD_DBIWROP_TYPEDEF_VF_ACTIVE_WIDTH 14225#define MC_CMD_DBIWROP_TYPEDEF_CS2_OFST 44226#define MC_CMD_DBIWROP_TYPEDEF_CS2_LBN 144227#define MC_CMD_DBIWROP_TYPEDEF_CS2_WIDTH 14228#define MC_CMD_DBIWROP_TYPEDEF_PARMS_LBN 324229#define MC_CMD_DBIWROP_TYPEDEF_PARMS_WIDTH 324230#define MC_CMD_DBIWROP_TYPEDEF_VALUE_OFST 84231#define MC_CMD_DBIWROP_TYPEDEF_VALUE_LEN 44232#define MC_CMD_DBIWROP_TYPEDEF_VALUE_LBN 644233#define MC_CMD_DBIWROP_TYPEDEF_VALUE_WIDTH 324234 4235 4236/***********************************/4237/* MC_CMD_PORT_READ324238 * Read a 32-bit register from the indirect port register map. The port to4239 * access is implied by the Shared memory channel used.4240 */4241#define MC_CMD_PORT_READ32 0x144242 4243/* MC_CMD_PORT_READ32_IN msgrequest */4244#define MC_CMD_PORT_READ32_IN_LEN 44245/* Address */4246#define MC_CMD_PORT_READ32_IN_ADDR_OFST 04247#define MC_CMD_PORT_READ32_IN_ADDR_LEN 44248 4249/* MC_CMD_PORT_READ32_OUT msgresponse */4250#define MC_CMD_PORT_READ32_OUT_LEN 84251/* Value */4252#define MC_CMD_PORT_READ32_OUT_VALUE_OFST 04253#define MC_CMD_PORT_READ32_OUT_VALUE_LEN 44254/* Status */4255#define MC_CMD_PORT_READ32_OUT_STATUS_OFST 44256#define MC_CMD_PORT_READ32_OUT_STATUS_LEN 44257 4258 4259/***********************************/4260/* MC_CMD_PORT_WRITE324261 * Write a 32-bit register to the indirect port register map. The port to4262 * access is implied by the Shared memory channel used.4263 */4264#define MC_CMD_PORT_WRITE32 0x154265 4266/* MC_CMD_PORT_WRITE32_IN msgrequest */4267#define MC_CMD_PORT_WRITE32_IN_LEN 84268/* Address */4269#define MC_CMD_PORT_WRITE32_IN_ADDR_OFST 04270#define MC_CMD_PORT_WRITE32_IN_ADDR_LEN 44271/* Value */4272#define MC_CMD_PORT_WRITE32_IN_VALUE_OFST 44273#define MC_CMD_PORT_WRITE32_IN_VALUE_LEN 44274 4275/* MC_CMD_PORT_WRITE32_OUT msgresponse */4276#define MC_CMD_PORT_WRITE32_OUT_LEN 44277/* Status */4278#define MC_CMD_PORT_WRITE32_OUT_STATUS_OFST 04279#define MC_CMD_PORT_WRITE32_OUT_STATUS_LEN 44280 4281 4282/***********************************/4283/* MC_CMD_PORT_READ1284284 * Read a 128-bit register from the indirect port register map. The port to4285 * access is implied by the Shared memory channel used.4286 */4287#define MC_CMD_PORT_READ128 0x164288 4289/* MC_CMD_PORT_READ128_IN msgrequest */4290#define MC_CMD_PORT_READ128_IN_LEN 44291/* Address */4292#define MC_CMD_PORT_READ128_IN_ADDR_OFST 04293#define MC_CMD_PORT_READ128_IN_ADDR_LEN 44294 4295/* MC_CMD_PORT_READ128_OUT msgresponse */4296#define MC_CMD_PORT_READ128_OUT_LEN 204297/* Value */4298#define MC_CMD_PORT_READ128_OUT_VALUE_OFST 04299#define MC_CMD_PORT_READ128_OUT_VALUE_LEN 164300/* Status */4301#define MC_CMD_PORT_READ128_OUT_STATUS_OFST 164302#define MC_CMD_PORT_READ128_OUT_STATUS_LEN 44303 4304 4305/***********************************/4306/* MC_CMD_PORT_WRITE1284307 * Write a 128-bit register to the indirect port register map. The port to4308 * access is implied by the Shared memory channel used.4309 */4310#define MC_CMD_PORT_WRITE128 0x174311 4312/* MC_CMD_PORT_WRITE128_IN msgrequest */4313#define MC_CMD_PORT_WRITE128_IN_LEN 204314/* Address */4315#define MC_CMD_PORT_WRITE128_IN_ADDR_OFST 04316#define MC_CMD_PORT_WRITE128_IN_ADDR_LEN 44317/* Value */4318#define MC_CMD_PORT_WRITE128_IN_VALUE_OFST 44319#define MC_CMD_PORT_WRITE128_IN_VALUE_LEN 164320 4321/* MC_CMD_PORT_WRITE128_OUT msgresponse */4322#define MC_CMD_PORT_WRITE128_OUT_LEN 44323/* Status */4324#define MC_CMD_PORT_WRITE128_OUT_STATUS_OFST 04325#define MC_CMD_PORT_WRITE128_OUT_STATUS_LEN 44326 4327/* MC_CMD_CAPABILITIES structuredef */4328#define MC_CMD_CAPABILITIES_LEN 44329/* Small buf table. */4330#define MC_CMD_CAPABILITIES_SMALL_BUF_TBL_LBN 04331#define MC_CMD_CAPABILITIES_SMALL_BUF_TBL_WIDTH 14332/* Turbo mode (for Maranello). */4333#define MC_CMD_CAPABILITIES_TURBO_LBN 14334#define MC_CMD_CAPABILITIES_TURBO_WIDTH 14335/* Turbo mode active (for Maranello). */4336#define MC_CMD_CAPABILITIES_TURBO_ACTIVE_LBN 24337#define MC_CMD_CAPABILITIES_TURBO_ACTIVE_WIDTH 14338/* PTP offload. */4339#define MC_CMD_CAPABILITIES_PTP_LBN 34340#define MC_CMD_CAPABILITIES_PTP_WIDTH 14341/* AOE mode. */4342#define MC_CMD_CAPABILITIES_AOE_LBN 44343#define MC_CMD_CAPABILITIES_AOE_WIDTH 14344/* AOE mode active. */4345#define MC_CMD_CAPABILITIES_AOE_ACTIVE_LBN 54346#define MC_CMD_CAPABILITIES_AOE_ACTIVE_WIDTH 14347/* AOE mode active. */4348#define MC_CMD_CAPABILITIES_FC_ACTIVE_LBN 64349#define MC_CMD_CAPABILITIES_FC_ACTIVE_WIDTH 14350#define MC_CMD_CAPABILITIES_RESERVED_LBN 74351#define MC_CMD_CAPABILITIES_RESERVED_WIDTH 254352 4353 4354/***********************************/4355/* MC_CMD_GET_BOARD_CFG4356 * Returns the MC firmware configuration structure.4357 */4358#define MC_CMD_GET_BOARD_CFG 0x184359#undef MC_CMD_0x18_PRIVILEGE_CTG4360 4361#define MC_CMD_0x18_PRIVILEGE_CTG SRIOV_CTG_GENERAL4362 4363/* MC_CMD_GET_BOARD_CFG_IN msgrequest */4364#define MC_CMD_GET_BOARD_CFG_IN_LEN 04365 4366/* MC_CMD_GET_BOARD_CFG_OUT msgresponse */4367#define MC_CMD_GET_BOARD_CFG_OUT_LENMIN 964368#define MC_CMD_GET_BOARD_CFG_OUT_LENMAX 1364369#define MC_CMD_GET_BOARD_CFG_OUT_LENMAX_MCDI2 1364370#define MC_CMD_GET_BOARD_CFG_OUT_LEN(num) (72+2*(num))4371#define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_NUM(len) (((len)-72)/2)4372#define MC_CMD_GET_BOARD_CFG_OUT_BOARD_TYPE_OFST 04373#define MC_CMD_GET_BOARD_CFG_OUT_BOARD_TYPE_LEN 44374#define MC_CMD_GET_BOARD_CFG_OUT_BOARD_NAME_OFST 44375#define MC_CMD_GET_BOARD_CFG_OUT_BOARD_NAME_LEN 324376/* Capabilities for Siena Port0 (see struct MC_CMD_CAPABILITIES). Unused on4377 * EF10 and later (use MC_CMD_GET_CAPABILITIES).4378 */4379#define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT0_OFST 364380#define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT0_LEN 44381/* Capabilities for Siena Port1 (see struct MC_CMD_CAPABILITIES). Unused on4382 * EF10 and later (use MC_CMD_GET_CAPABILITIES).4383 */4384#define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT1_OFST 404385#define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT1_LEN 44386/* Base MAC address for Siena Port0. Unused on EF10 and later (use4387 * MC_CMD_GET_MAC_ADDRESSES).4388 */4389#define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0_OFST 444390#define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0_LEN 64391/* Base MAC address for Siena Port1. Unused on EF10 and later (use4392 * MC_CMD_GET_MAC_ADDRESSES).4393 */4394#define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1_OFST 504395#define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1_LEN 64396/* Size of MAC address pool for Siena Port0. Unused on EF10 and later (use4397 * MC_CMD_GET_MAC_ADDRESSES).4398 */4399#define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT0_OFST 564400#define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT0_LEN 44401/* Size of MAC address pool for Siena Port1. Unused on EF10 and later (use4402 * MC_CMD_GET_MAC_ADDRESSES).4403 */4404#define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT1_OFST 604405#define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT1_LEN 44406/* Increment between addresses in MAC address pool for Siena Port0. Unused on4407 * EF10 and later (use MC_CMD_GET_MAC_ADDRESSES).4408 */4409#define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT0_OFST 644410#define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT0_LEN 44411/* Increment between addresses in MAC address pool for Siena Port1. Unused on4412 * EF10 and later (use MC_CMD_GET_MAC_ADDRESSES).4413 */4414#define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT1_OFST 684415#define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT1_LEN 44416/* Siena only. This field contains a 16-bit value for each of the types of4417 * NVRAM area. The values are defined in the firmware/mc/platform/.c file for a4418 * specific board type, but otherwise have no meaning to the MC; they are used4419 * by the driver to manage selection of appropriate firmware updates. Unused on4420 * EF10 and later (use MC_CMD_NVRAM_METADATA).4421 */4422#define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_OFST 724423#define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_LEN 24424#define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MINNUM 124425#define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MAXNUM 324426#define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MAXNUM_MCDI2 324427 4428 4429/***********************************/4430/* MC_CMD_DBI_READX4431 * Read DBI register(s) -- extended functionality4432 */4433#define MC_CMD_DBI_READX 0x194434#undef MC_CMD_0x19_PRIVILEGE_CTG4435 4436#define MC_CMD_0x19_PRIVILEGE_CTG SRIOV_CTG_INSECURE4437 4438/* MC_CMD_DBI_READX_IN msgrequest */4439#define MC_CMD_DBI_READX_IN_LENMIN 84440#define MC_CMD_DBI_READX_IN_LENMAX 2484441#define MC_CMD_DBI_READX_IN_LENMAX_MCDI2 10164442#define MC_CMD_DBI_READX_IN_LEN(num) (0+8*(num))4443#define MC_CMD_DBI_READX_IN_DBIRDOP_NUM(len) (((len)-0)/8)4444/* Each Read op consists of an address (offset 0), VF/CS2) */4445#define MC_CMD_DBI_READX_IN_DBIRDOP_OFST 04446#define MC_CMD_DBI_READX_IN_DBIRDOP_LEN 84447#define MC_CMD_DBI_READX_IN_DBIRDOP_LO_OFST 04448#define MC_CMD_DBI_READX_IN_DBIRDOP_LO_LEN 44449#define MC_CMD_DBI_READX_IN_DBIRDOP_LO_LBN 04450#define MC_CMD_DBI_READX_IN_DBIRDOP_LO_WIDTH 324451#define MC_CMD_DBI_READX_IN_DBIRDOP_HI_OFST 44452#define MC_CMD_DBI_READX_IN_DBIRDOP_HI_LEN 44453#define MC_CMD_DBI_READX_IN_DBIRDOP_HI_LBN 324454#define MC_CMD_DBI_READX_IN_DBIRDOP_HI_WIDTH 324455#define MC_CMD_DBI_READX_IN_DBIRDOP_MINNUM 14456#define MC_CMD_DBI_READX_IN_DBIRDOP_MAXNUM 314457#define MC_CMD_DBI_READX_IN_DBIRDOP_MAXNUM_MCDI2 1274458 4459/* MC_CMD_DBI_READX_OUT msgresponse */4460#define MC_CMD_DBI_READX_OUT_LENMIN 44461#define MC_CMD_DBI_READX_OUT_LENMAX 2524462#define MC_CMD_DBI_READX_OUT_LENMAX_MCDI2 10204463#define MC_CMD_DBI_READX_OUT_LEN(num) (0+4*(num))4464#define MC_CMD_DBI_READX_OUT_VALUE_NUM(len) (((len)-0)/4)4465/* Value */4466#define MC_CMD_DBI_READX_OUT_VALUE_OFST 04467#define MC_CMD_DBI_READX_OUT_VALUE_LEN 44468#define MC_CMD_DBI_READX_OUT_VALUE_MINNUM 14469#define MC_CMD_DBI_READX_OUT_VALUE_MAXNUM 634470#define MC_CMD_DBI_READX_OUT_VALUE_MAXNUM_MCDI2 2554471 4472/* MC_CMD_DBIRDOP_TYPEDEF structuredef */4473#define MC_CMD_DBIRDOP_TYPEDEF_LEN 84474#define MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_OFST 04475#define MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_LEN 44476#define MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_LBN 04477#define MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_WIDTH 324478#define MC_CMD_DBIRDOP_TYPEDEF_PARMS_OFST 44479#define MC_CMD_DBIRDOP_TYPEDEF_PARMS_LEN 44480#define MC_CMD_DBIRDOP_TYPEDEF_VF_NUM_OFST 44481#define MC_CMD_DBIRDOP_TYPEDEF_VF_NUM_LBN 164482#define MC_CMD_DBIRDOP_TYPEDEF_VF_NUM_WIDTH 164483#define MC_CMD_DBIRDOP_TYPEDEF_VF_ACTIVE_OFST 44484#define MC_CMD_DBIRDOP_TYPEDEF_VF_ACTIVE_LBN 154485#define MC_CMD_DBIRDOP_TYPEDEF_VF_ACTIVE_WIDTH 14486#define MC_CMD_DBIRDOP_TYPEDEF_CS2_OFST 44487#define MC_CMD_DBIRDOP_TYPEDEF_CS2_LBN 144488#define MC_CMD_DBIRDOP_TYPEDEF_CS2_WIDTH 14489#define MC_CMD_DBIRDOP_TYPEDEF_PARMS_LBN 324490#define MC_CMD_DBIRDOP_TYPEDEF_PARMS_WIDTH 324491 4492 4493/***********************************/4494/* MC_CMD_SET_RAND_SEED4495 * Set the 16byte seed for the MC pseudo-random generator.4496 */4497#define MC_CMD_SET_RAND_SEED 0x1a4498#undef MC_CMD_0x1a_PRIVILEGE_CTG4499 4500#define MC_CMD_0x1a_PRIVILEGE_CTG SRIOV_CTG_INSECURE4501 4502/* MC_CMD_SET_RAND_SEED_IN msgrequest */4503#define MC_CMD_SET_RAND_SEED_IN_LEN 164504/* Seed value. */4505#define MC_CMD_SET_RAND_SEED_IN_SEED_OFST 04506#define MC_CMD_SET_RAND_SEED_IN_SEED_LEN 164507 4508/* MC_CMD_SET_RAND_SEED_OUT msgresponse */4509#define MC_CMD_SET_RAND_SEED_OUT_LEN 04510 4511 4512/***********************************/4513/* MC_CMD_LTSSM_HIST4514 * Retrieve the history of the LTSSM, if the build supports it.4515 */4516#define MC_CMD_LTSSM_HIST 0x1b4517 4518/* MC_CMD_LTSSM_HIST_IN msgrequest */4519#define MC_CMD_LTSSM_HIST_IN_LEN 04520 4521/* MC_CMD_LTSSM_HIST_OUT msgresponse */4522#define MC_CMD_LTSSM_HIST_OUT_LENMIN 04523#define MC_CMD_LTSSM_HIST_OUT_LENMAX 2524524#define MC_CMD_LTSSM_HIST_OUT_LENMAX_MCDI2 10204525#define MC_CMD_LTSSM_HIST_OUT_LEN(num) (0+4*(num))4526#define MC_CMD_LTSSM_HIST_OUT_DATA_NUM(len) (((len)-0)/4)4527/* variable number of LTSSM values, as bytes. The history is read-to-clear. */4528#define MC_CMD_LTSSM_HIST_OUT_DATA_OFST 04529#define MC_CMD_LTSSM_HIST_OUT_DATA_LEN 44530#define MC_CMD_LTSSM_HIST_OUT_DATA_MINNUM 04531#define MC_CMD_LTSSM_HIST_OUT_DATA_MAXNUM 634532#define MC_CMD_LTSSM_HIST_OUT_DATA_MAXNUM_MCDI2 2554533 4534 4535/***********************************/4536/* MC_CMD_DRV_ATTACH4537 * Inform MCPU that this port is managed on the host (i.e. driver active). For4538 * Huntington, also request the preferred datapath firmware to use if possible4539 * (it may not be possible for this request to be fulfilled; the driver must4540 * issue a subsequent MC_CMD_GET_CAPABILITIES command to determine which4541 * features are actually available). The FIRMWARE_ID field is ignored by older4542 * platforms.4543 */4544#define MC_CMD_DRV_ATTACH 0x1c4545#undef MC_CMD_0x1c_PRIVILEGE_CTG4546 4547#define MC_CMD_0x1c_PRIVILEGE_CTG SRIOV_CTG_GENERAL4548 4549/* MC_CMD_DRV_ATTACH_IN msgrequest */4550#define MC_CMD_DRV_ATTACH_IN_LEN 124551/* new state to set if UPDATE=1 */4552#define MC_CMD_DRV_ATTACH_IN_NEW_STATE_OFST 04553#define MC_CMD_DRV_ATTACH_IN_NEW_STATE_LEN 44554#define MC_CMD_DRV_ATTACH_OFST 04555#define MC_CMD_DRV_ATTACH_LBN 04556#define MC_CMD_DRV_ATTACH_WIDTH 14557#define MC_CMD_DRV_ATTACH_IN_ATTACH_OFST 04558#define MC_CMD_DRV_ATTACH_IN_ATTACH_LBN 04559#define MC_CMD_DRV_ATTACH_IN_ATTACH_WIDTH 14560#define MC_CMD_DRV_PREBOOT_OFST 04561#define MC_CMD_DRV_PREBOOT_LBN 14562#define MC_CMD_DRV_PREBOOT_WIDTH 14563#define MC_CMD_DRV_ATTACH_IN_PREBOOT_OFST 04564#define MC_CMD_DRV_ATTACH_IN_PREBOOT_LBN 14565#define MC_CMD_DRV_ATTACH_IN_PREBOOT_WIDTH 14566#define MC_CMD_DRV_ATTACH_IN_SUBVARIANT_AWARE_OFST 04567#define MC_CMD_DRV_ATTACH_IN_SUBVARIANT_AWARE_LBN 24568#define MC_CMD_DRV_ATTACH_IN_SUBVARIANT_AWARE_WIDTH 14569#define MC_CMD_DRV_ATTACH_IN_WANT_VI_SPREADING_OFST 04570#define MC_CMD_DRV_ATTACH_IN_WANT_VI_SPREADING_LBN 34571#define MC_CMD_DRV_ATTACH_IN_WANT_VI_SPREADING_WIDTH 14572#define MC_CMD_DRV_ATTACH_IN_WANT_V2_LINKCHANGES_OFST 04573#define MC_CMD_DRV_ATTACH_IN_WANT_V2_LINKCHANGES_LBN 44574#define MC_CMD_DRV_ATTACH_IN_WANT_V2_LINKCHANGES_WIDTH 14575#define MC_CMD_DRV_ATTACH_IN_WANT_RX_VI_SPREADING_INHIBIT_OFST 04576#define MC_CMD_DRV_ATTACH_IN_WANT_RX_VI_SPREADING_INHIBIT_LBN 54577#define MC_CMD_DRV_ATTACH_IN_WANT_RX_VI_SPREADING_INHIBIT_WIDTH 14578#define MC_CMD_DRV_ATTACH_IN_WANT_TX_ONLY_SPREADING_OFST 04579#define MC_CMD_DRV_ATTACH_IN_WANT_TX_ONLY_SPREADING_LBN 54580#define MC_CMD_DRV_ATTACH_IN_WANT_TX_ONLY_SPREADING_WIDTH 14581/* 1 to set new state, or 0 to just report the existing state */4582#define MC_CMD_DRV_ATTACH_IN_UPDATE_OFST 44583#define MC_CMD_DRV_ATTACH_IN_UPDATE_LEN 44584/* preferred datapath firmware (for Huntington; ignored for Siena) */4585#define MC_CMD_DRV_ATTACH_IN_FIRMWARE_ID_OFST 84586#define MC_CMD_DRV_ATTACH_IN_FIRMWARE_ID_LEN 44587/* enum: Prefer to use full featured firmware */4588#define MC_CMD_FW_FULL_FEATURED 0x04589/* enum: Prefer to use firmware with fewer features but lower latency */4590#define MC_CMD_FW_LOW_LATENCY 0x14591/* enum: Prefer to use firmware for SolarCapture packed stream mode */4592#define MC_CMD_FW_PACKED_STREAM 0x24593/* enum: Prefer to use firmware with fewer features and simpler TX event4594 * batching but higher TX packet rate4595 */4596#define MC_CMD_FW_HIGH_TX_RATE 0x34597/* enum: Reserved value */4598#define MC_CMD_FW_PACKED_STREAM_HASH_MODE_1 0x44599/* enum: Prefer to use firmware with additional "rules engine" filtering4600 * support4601 */4602#define MC_CMD_FW_RULES_ENGINE 0x54603/* enum: Prefer to use firmware with additional DPDK support */4604#define MC_CMD_FW_DPDK 0x64605/* enum: Prefer to use "l3xudp" custom datapath firmware (see SF-119495-PD and4606 * bug69716)4607 */4608#define MC_CMD_FW_L3XUDP 0x74609/* enum: Requests that the MC keep whatever datapath firmware is currently4610 * running. It's used for test purposes, where we want to be able to shmboot4611 * special test firmware variants. This option is only recognised in eftest4612 * (i.e. non-production) builds.4613 */4614#define MC_CMD_FW_KEEP_CURRENT_EFTEST_ONLY 0xfffffffe4615/* enum: Only this option is allowed for non-admin functions */4616#define MC_CMD_FW_DONT_CARE 0xffffffff4617 4618/* MC_CMD_DRV_ATTACH_IN_V2 msgrequest: Updated DRV_ATTACH to include driver4619 * version4620 */4621#define MC_CMD_DRV_ATTACH_IN_V2_LEN 324622/* new state to set if UPDATE=1 */4623#define MC_CMD_DRV_ATTACH_IN_V2_NEW_STATE_OFST 04624#define MC_CMD_DRV_ATTACH_IN_V2_NEW_STATE_LEN 44625/* MC_CMD_DRV_ATTACH_OFST 0 */4626/* MC_CMD_DRV_ATTACH_LBN 0 */4627/* MC_CMD_DRV_ATTACH_WIDTH 1 */4628#define MC_CMD_DRV_ATTACH_IN_V2_ATTACH_OFST 04629#define MC_CMD_DRV_ATTACH_IN_V2_ATTACH_LBN 04630#define MC_CMD_DRV_ATTACH_IN_V2_ATTACH_WIDTH 14631/* MC_CMD_DRV_PREBOOT_OFST 0 */4632/* MC_CMD_DRV_PREBOOT_LBN 1 */4633/* MC_CMD_DRV_PREBOOT_WIDTH 1 */4634#define MC_CMD_DRV_ATTACH_IN_V2_PREBOOT_OFST 04635#define MC_CMD_DRV_ATTACH_IN_V2_PREBOOT_LBN 14636#define MC_CMD_DRV_ATTACH_IN_V2_PREBOOT_WIDTH 14637#define MC_CMD_DRV_ATTACH_IN_V2_SUBVARIANT_AWARE_OFST 04638#define MC_CMD_DRV_ATTACH_IN_V2_SUBVARIANT_AWARE_LBN 24639#define MC_CMD_DRV_ATTACH_IN_V2_SUBVARIANT_AWARE_WIDTH 14640#define MC_CMD_DRV_ATTACH_IN_V2_WANT_VI_SPREADING_OFST 04641#define MC_CMD_DRV_ATTACH_IN_V2_WANT_VI_SPREADING_LBN 34642#define MC_CMD_DRV_ATTACH_IN_V2_WANT_VI_SPREADING_WIDTH 14643#define MC_CMD_DRV_ATTACH_IN_V2_WANT_V2_LINKCHANGES_OFST 04644#define MC_CMD_DRV_ATTACH_IN_V2_WANT_V2_LINKCHANGES_LBN 44645#define MC_CMD_DRV_ATTACH_IN_V2_WANT_V2_LINKCHANGES_WIDTH 14646#define MC_CMD_DRV_ATTACH_IN_V2_WANT_RX_VI_SPREADING_INHIBIT_OFST 04647#define MC_CMD_DRV_ATTACH_IN_V2_WANT_RX_VI_SPREADING_INHIBIT_LBN 54648#define MC_CMD_DRV_ATTACH_IN_V2_WANT_RX_VI_SPREADING_INHIBIT_WIDTH 14649#define MC_CMD_DRV_ATTACH_IN_V2_WANT_TX_ONLY_SPREADING_OFST 04650#define MC_CMD_DRV_ATTACH_IN_V2_WANT_TX_ONLY_SPREADING_LBN 54651#define MC_CMD_DRV_ATTACH_IN_V2_WANT_TX_ONLY_SPREADING_WIDTH 14652/* 1 to set new state, or 0 to just report the existing state */4653#define MC_CMD_DRV_ATTACH_IN_V2_UPDATE_OFST 44654#define MC_CMD_DRV_ATTACH_IN_V2_UPDATE_LEN 44655/* preferred datapath firmware (for Huntington; ignored for Siena) */4656#define MC_CMD_DRV_ATTACH_IN_V2_FIRMWARE_ID_OFST 84657#define MC_CMD_DRV_ATTACH_IN_V2_FIRMWARE_ID_LEN 44658/* enum: Prefer to use full featured firmware */4659/* MC_CMD_FW_FULL_FEATURED 0x0 */4660/* enum: Prefer to use firmware with fewer features but lower latency */4661/* MC_CMD_FW_LOW_LATENCY 0x1 */4662/* enum: Prefer to use firmware for SolarCapture packed stream mode */4663/* MC_CMD_FW_PACKED_STREAM 0x2 */4664/* enum: Prefer to use firmware with fewer features and simpler TX event4665 * batching but higher TX packet rate4666 */4667/* MC_CMD_FW_HIGH_TX_RATE 0x3 */4668/* enum: Reserved value */4669/* MC_CMD_FW_PACKED_STREAM_HASH_MODE_1 0x4 */4670/* enum: Prefer to use firmware with additional "rules engine" filtering4671 * support4672 */4673/* MC_CMD_FW_RULES_ENGINE 0x5 */4674/* enum: Prefer to use firmware with additional DPDK support */4675/* MC_CMD_FW_DPDK 0x6 */4676/* enum: Prefer to use "l3xudp" custom datapath firmware (see SF-119495-PD and4677 * bug69716)4678 */4679/* MC_CMD_FW_L3XUDP 0x7 */4680/* enum: Requests that the MC keep whatever datapath firmware is currently4681 * running. It's used for test purposes, where we want to be able to shmboot4682 * special test firmware variants. This option is only recognised in eftest4683 * (i.e. non-production) builds.4684 */4685/* MC_CMD_FW_KEEP_CURRENT_EFTEST_ONLY 0xfffffffe */4686/* enum: Only this option is allowed for non-admin functions */4687/* MC_CMD_FW_DONT_CARE 0xffffffff */4688/* Version of the driver to be reported by management protocols (e.g. NC-SI)4689 * handled by the NIC. This is a zero-terminated ASCII string.4690 */4691#define MC_CMD_DRV_ATTACH_IN_V2_DRIVER_VERSION_OFST 124692#define MC_CMD_DRV_ATTACH_IN_V2_DRIVER_VERSION_LEN 204693 4694/* MC_CMD_DRV_ATTACH_OUT msgresponse */4695#define MC_CMD_DRV_ATTACH_OUT_LEN 44696/* previous or existing state, see the bitmask at NEW_STATE */4697#define MC_CMD_DRV_ATTACH_OUT_OLD_STATE_OFST 04698#define MC_CMD_DRV_ATTACH_OUT_OLD_STATE_LEN 44699 4700/* MC_CMD_DRV_ATTACH_EXT_OUT msgresponse */4701#define MC_CMD_DRV_ATTACH_EXT_OUT_LEN 84702/* previous or existing state, see the bitmask at NEW_STATE */4703#define MC_CMD_DRV_ATTACH_EXT_OUT_OLD_STATE_OFST 04704#define MC_CMD_DRV_ATTACH_EXT_OUT_OLD_STATE_LEN 44705/* Flags associated with this function */4706#define MC_CMD_DRV_ATTACH_EXT_OUT_FUNC_FLAGS_OFST 44707#define MC_CMD_DRV_ATTACH_EXT_OUT_FUNC_FLAGS_LEN 44708/* enum: Labels the lowest-numbered function visible to the OS */4709#define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_PRIMARY 0x04710/* enum: The function can control the link state of the physical port it is4711 * bound to.4712 */4713#define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL 0x14714/* enum: The function can perform privileged operations */4715#define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_TRUSTED 0x24716/* enum: The function does not have an active port associated with it. The port4717 * refers to the Sorrento external FPGA port.4718 */4719#define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_NO_ACTIVE_PORT 0x34720/* enum: If set, indicates that VI spreading is currently enabled. Will always4721 * indicate the current state, regardless of the value in the WANT_VI_SPREADING4722 * input.4723 */4724#define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_VI_SPREADING_ENABLED 0x44725/* enum: Used during development only. Should no longer be used. */4726#define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_RX_VI_SPREADING_INHIBITED 0x54727/* enum: If set, indicates that TX only spreading is enabled. Even-numbered4728 * TXQs will use one engine, and odd-numbered TXQs will use the other. This4729 * also has the effect that only even-numbered RXQs will receive traffic.4730 */4731#define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_TX_ONLY_VI_SPREADING_ENABLED 0x54732 4733 4734/***********************************/4735/* MC_CMD_SHMUART4736 * Route UART output to circular buffer in shared memory instead.4737 */4738#define MC_CMD_SHMUART 0x1f4739 4740/* MC_CMD_SHMUART_IN msgrequest */4741#define MC_CMD_SHMUART_IN_LEN 44742/* ??? */4743#define MC_CMD_SHMUART_IN_FLAG_OFST 04744#define MC_CMD_SHMUART_IN_FLAG_LEN 44745 4746/* MC_CMD_SHMUART_OUT msgresponse */4747#define MC_CMD_SHMUART_OUT_LEN 04748 4749 4750/***********************************/4751/* MC_CMD_PORT_RESET4752 * Generic per-port reset. There is no equivalent for per-board reset. Locks4753 * required: None; Return code: 0, ETIME. NOTE: This command is deprecated -4754 * use MC_CMD_ENTITY_RESET instead.4755 */4756#define MC_CMD_PORT_RESET 0x204757#undef MC_CMD_0x20_PRIVILEGE_CTG4758 4759#define MC_CMD_0x20_PRIVILEGE_CTG SRIOV_CTG_GENERAL4760 4761/* MC_CMD_PORT_RESET_IN msgrequest */4762#define MC_CMD_PORT_RESET_IN_LEN 04763 4764/* MC_CMD_PORT_RESET_OUT msgresponse */4765#define MC_CMD_PORT_RESET_OUT_LEN 04766 4767 4768/***********************************/4769/* MC_CMD_ENTITY_RESET4770 * Generic per-resource reset. There is no equivalent for per-board reset.4771 * Locks required: None; Return code: 0, ETIME. NOTE: This command is an4772 * extended version of the deprecated MC_CMD_PORT_RESET with added fields.4773 */4774#define MC_CMD_ENTITY_RESET 0x204775/* MC_CMD_0x20_PRIVILEGE_CTG SRIOV_CTG_GENERAL */4776 4777/* MC_CMD_ENTITY_RESET_IN msgrequest */4778#define MC_CMD_ENTITY_RESET_IN_LEN 44779/* Optional flags field. Omitting this will perform a "legacy" reset action4780 * (TBD).4781 */4782#define MC_CMD_ENTITY_RESET_IN_FLAG_OFST 04783#define MC_CMD_ENTITY_RESET_IN_FLAG_LEN 44784#define MC_CMD_ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET_OFST 04785#define MC_CMD_ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET_LBN 04786#define MC_CMD_ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET_WIDTH 14787 4788/* MC_CMD_ENTITY_RESET_OUT msgresponse */4789#define MC_CMD_ENTITY_RESET_OUT_LEN 04790 4791 4792/***********************************/4793/* MC_CMD_PCIE_CREDITS4794 * Read instantaneous and minimum flow control thresholds.4795 */4796#define MC_CMD_PCIE_CREDITS 0x214797 4798/* MC_CMD_PCIE_CREDITS_IN msgrequest */4799#define MC_CMD_PCIE_CREDITS_IN_LEN 84800/* poll period. 0 is disabled */4801#define MC_CMD_PCIE_CREDITS_IN_POLL_PERIOD_OFST 04802#define MC_CMD_PCIE_CREDITS_IN_POLL_PERIOD_LEN 44803/* wipe statistics */4804#define MC_CMD_PCIE_CREDITS_IN_WIPE_OFST 44805#define MC_CMD_PCIE_CREDITS_IN_WIPE_LEN 44806 4807/* MC_CMD_PCIE_CREDITS_OUT msgresponse */4808#define MC_CMD_PCIE_CREDITS_OUT_LEN 164809#define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_HDR_OFST 04810#define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_HDR_LEN 24811#define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_DATA_OFST 24812#define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_DATA_LEN 24813#define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_HDR_OFST 44814#define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_HDR_LEN 24815#define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_DATA_OFST 64816#define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_DATA_LEN 24817#define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_HDR_OFST 84818#define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_HDR_LEN 24819#define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_DATA_OFST 104820#define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_DATA_LEN 24821#define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_HDR_OFST 124822#define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_HDR_LEN 24823#define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_DATA_OFST 144824#define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_DATA_LEN 24825 4826 4827/***********************************/4828/* MC_CMD_RXD_MONITOR4829 * Get histogram of RX queue fill level.4830 */4831#define MC_CMD_RXD_MONITOR 0x224832 4833/* MC_CMD_RXD_MONITOR_IN msgrequest */4834#define MC_CMD_RXD_MONITOR_IN_LEN 124835#define MC_CMD_RXD_MONITOR_IN_QID_OFST 04836#define MC_CMD_RXD_MONITOR_IN_QID_LEN 44837#define MC_CMD_RXD_MONITOR_IN_POLL_PERIOD_OFST 44838#define MC_CMD_RXD_MONITOR_IN_POLL_PERIOD_LEN 44839#define MC_CMD_RXD_MONITOR_IN_WIPE_OFST 84840#define MC_CMD_RXD_MONITOR_IN_WIPE_LEN 44841 4842/* MC_CMD_RXD_MONITOR_OUT msgresponse */4843#define MC_CMD_RXD_MONITOR_OUT_LEN 804844#define MC_CMD_RXD_MONITOR_OUT_QID_OFST 04845#define MC_CMD_RXD_MONITOR_OUT_QID_LEN 44846#define MC_CMD_RXD_MONITOR_OUT_RING_FILL_OFST 44847#define MC_CMD_RXD_MONITOR_OUT_RING_FILL_LEN 44848#define MC_CMD_RXD_MONITOR_OUT_CACHE_FILL_OFST 84849#define MC_CMD_RXD_MONITOR_OUT_CACHE_FILL_LEN 44850#define MC_CMD_RXD_MONITOR_OUT_RING_LT_1_OFST 124851#define MC_CMD_RXD_MONITOR_OUT_RING_LT_1_LEN 44852#define MC_CMD_RXD_MONITOR_OUT_RING_LT_2_OFST 164853#define MC_CMD_RXD_MONITOR_OUT_RING_LT_2_LEN 44854#define MC_CMD_RXD_MONITOR_OUT_RING_LT_4_OFST 204855#define MC_CMD_RXD_MONITOR_OUT_RING_LT_4_LEN 44856#define MC_CMD_RXD_MONITOR_OUT_RING_LT_8_OFST 244857#define MC_CMD_RXD_MONITOR_OUT_RING_LT_8_LEN 44858#define MC_CMD_RXD_MONITOR_OUT_RING_LT_16_OFST 284859#define MC_CMD_RXD_MONITOR_OUT_RING_LT_16_LEN 44860#define MC_CMD_RXD_MONITOR_OUT_RING_LT_32_OFST 324861#define MC_CMD_RXD_MONITOR_OUT_RING_LT_32_LEN 44862#define MC_CMD_RXD_MONITOR_OUT_RING_LT_64_OFST 364863#define MC_CMD_RXD_MONITOR_OUT_RING_LT_64_LEN 44864#define MC_CMD_RXD_MONITOR_OUT_RING_LT_128_OFST 404865#define MC_CMD_RXD_MONITOR_OUT_RING_LT_128_LEN 44866#define MC_CMD_RXD_MONITOR_OUT_RING_LT_256_OFST 444867#define MC_CMD_RXD_MONITOR_OUT_RING_LT_256_LEN 44868#define MC_CMD_RXD_MONITOR_OUT_RING_GE_256_OFST 484869#define MC_CMD_RXD_MONITOR_OUT_RING_GE_256_LEN 44870#define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_1_OFST 524871#define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_1_LEN 44872#define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_2_OFST 564873#define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_2_LEN 44874#define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_4_OFST 604875#define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_4_LEN 44876#define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_8_OFST 644877#define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_8_LEN 44878#define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_16_OFST 684879#define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_16_LEN 44880#define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_32_OFST 724881#define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_32_LEN 44882#define MC_CMD_RXD_MONITOR_OUT_CACHE_GE_32_OFST 764883#define MC_CMD_RXD_MONITOR_OUT_CACHE_GE_32_LEN 44884 4885 4886/***********************************/4887/* MC_CMD_PUTS4888 * Copy the given ASCII string out onto UART and/or out of the network port.4889 */4890#define MC_CMD_PUTS 0x234891#undef MC_CMD_0x23_PRIVILEGE_CTG4892 4893#define MC_CMD_0x23_PRIVILEGE_CTG SRIOV_CTG_INSECURE4894 4895/* MC_CMD_PUTS_IN msgrequest */4896#define MC_CMD_PUTS_IN_LENMIN 134897#define MC_CMD_PUTS_IN_LENMAX 2524898#define MC_CMD_PUTS_IN_LENMAX_MCDI2 10204899#define MC_CMD_PUTS_IN_LEN(num) (12+1*(num))4900#define MC_CMD_PUTS_IN_STRING_NUM(len) (((len)-12)/1)4901#define MC_CMD_PUTS_IN_DEST_OFST 04902#define MC_CMD_PUTS_IN_DEST_LEN 44903#define MC_CMD_PUTS_IN_UART_OFST 04904#define MC_CMD_PUTS_IN_UART_LBN 04905#define MC_CMD_PUTS_IN_UART_WIDTH 14906#define MC_CMD_PUTS_IN_PORT_OFST 04907#define MC_CMD_PUTS_IN_PORT_LBN 14908#define MC_CMD_PUTS_IN_PORT_WIDTH 14909#define MC_CMD_PUTS_IN_DHOST_OFST 44910#define MC_CMD_PUTS_IN_DHOST_LEN 64911#define MC_CMD_PUTS_IN_STRING_OFST 124912#define MC_CMD_PUTS_IN_STRING_LEN 14913#define MC_CMD_PUTS_IN_STRING_MINNUM 14914#define MC_CMD_PUTS_IN_STRING_MAXNUM 2404915#define MC_CMD_PUTS_IN_STRING_MAXNUM_MCDI2 10084916 4917/* MC_CMD_PUTS_OUT msgresponse */4918#define MC_CMD_PUTS_OUT_LEN 04919 4920 4921/***********************************/4922/* MC_CMD_GET_PHY_CFG4923 * Report PHY configuration. This guarantees to succeed even if the PHY is in a4924 * 'zombie' state. Locks required: None4925 */4926#define MC_CMD_GET_PHY_CFG 0x244927#undef MC_CMD_0x24_PRIVILEGE_CTG4928 4929#define MC_CMD_0x24_PRIVILEGE_CTG SRIOV_CTG_GENERAL4930 4931/* MC_CMD_GET_PHY_CFG_IN msgrequest */4932#define MC_CMD_GET_PHY_CFG_IN_LEN 04933 4934/* MC_CMD_GET_PHY_CFG_OUT msgresponse */4935#define MC_CMD_GET_PHY_CFG_OUT_LEN 724936/* flags */4937#define MC_CMD_GET_PHY_CFG_OUT_FLAGS_OFST 04938#define MC_CMD_GET_PHY_CFG_OUT_FLAGS_LEN 44939#define MC_CMD_GET_PHY_CFG_OUT_PRESENT_OFST 04940#define MC_CMD_GET_PHY_CFG_OUT_PRESENT_LBN 04941#define MC_CMD_GET_PHY_CFG_OUT_PRESENT_WIDTH 14942#define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_SHORT_OFST 04943#define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_SHORT_LBN 14944#define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_SHORT_WIDTH 14945#define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_LONG_OFST 04946#define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_LONG_LBN 24947#define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_LONG_WIDTH 14948#define MC_CMD_GET_PHY_CFG_OUT_LOWPOWER_OFST 04949#define MC_CMD_GET_PHY_CFG_OUT_LOWPOWER_LBN 34950#define MC_CMD_GET_PHY_CFG_OUT_LOWPOWER_WIDTH 14951#define MC_CMD_GET_PHY_CFG_OUT_POWEROFF_OFST 04952#define MC_CMD_GET_PHY_CFG_OUT_POWEROFF_LBN 44953#define MC_CMD_GET_PHY_CFG_OUT_POWEROFF_WIDTH 14954#define MC_CMD_GET_PHY_CFG_OUT_TXDIS_OFST 04955#define MC_CMD_GET_PHY_CFG_OUT_TXDIS_LBN 54956#define MC_CMD_GET_PHY_CFG_OUT_TXDIS_WIDTH 14957#define MC_CMD_GET_PHY_CFG_OUT_BIST_OFST 04958#define MC_CMD_GET_PHY_CFG_OUT_BIST_LBN 64959#define MC_CMD_GET_PHY_CFG_OUT_BIST_WIDTH 14960/* ?? */4961#define MC_CMD_GET_PHY_CFG_OUT_TYPE_OFST 44962#define MC_CMD_GET_PHY_CFG_OUT_TYPE_LEN 44963/* Bitmask of supported capabilities */4964#define MC_CMD_GET_PHY_CFG_OUT_SUPPORTED_CAP_OFST 84965#define MC_CMD_GET_PHY_CFG_OUT_SUPPORTED_CAP_LEN 44966#define MC_CMD_PHY_CAP_10HDX_OFST 84967#define MC_CMD_PHY_CAP_10HDX_LBN 14968#define MC_CMD_PHY_CAP_10HDX_WIDTH 14969#define MC_CMD_PHY_CAP_10FDX_OFST 84970#define MC_CMD_PHY_CAP_10FDX_LBN 24971#define MC_CMD_PHY_CAP_10FDX_WIDTH 14972#define MC_CMD_PHY_CAP_100HDX_OFST 84973#define MC_CMD_PHY_CAP_100HDX_LBN 34974#define MC_CMD_PHY_CAP_100HDX_WIDTH 14975#define MC_CMD_PHY_CAP_100FDX_OFST 84976#define MC_CMD_PHY_CAP_100FDX_LBN 44977#define MC_CMD_PHY_CAP_100FDX_WIDTH 14978#define MC_CMD_PHY_CAP_1000HDX_OFST 84979#define MC_CMD_PHY_CAP_1000HDX_LBN 54980#define MC_CMD_PHY_CAP_1000HDX_WIDTH 14981#define MC_CMD_PHY_CAP_1000FDX_OFST 84982#define MC_CMD_PHY_CAP_1000FDX_LBN 64983#define MC_CMD_PHY_CAP_1000FDX_WIDTH 14984#define MC_CMD_PHY_CAP_10000FDX_OFST 84985#define MC_CMD_PHY_CAP_10000FDX_LBN 74986#define MC_CMD_PHY_CAP_10000FDX_WIDTH 14987#define MC_CMD_PHY_CAP_PAUSE_OFST 84988#define MC_CMD_PHY_CAP_PAUSE_LBN 84989#define MC_CMD_PHY_CAP_PAUSE_WIDTH 14990#define MC_CMD_PHY_CAP_ASYM_OFST 84991#define MC_CMD_PHY_CAP_ASYM_LBN 94992#define MC_CMD_PHY_CAP_ASYM_WIDTH 14993#define MC_CMD_PHY_CAP_AN_OFST 84994#define MC_CMD_PHY_CAP_AN_LBN 104995#define MC_CMD_PHY_CAP_AN_WIDTH 14996#define MC_CMD_PHY_CAP_40000FDX_OFST 84997#define MC_CMD_PHY_CAP_40000FDX_LBN 114998#define MC_CMD_PHY_CAP_40000FDX_WIDTH 14999#define MC_CMD_PHY_CAP_DDM_OFST 85000#define MC_CMD_PHY_CAP_DDM_LBN 125001#define MC_CMD_PHY_CAP_DDM_WIDTH 15002#define MC_CMD_PHY_CAP_100000FDX_OFST 85003#define MC_CMD_PHY_CAP_100000FDX_LBN 135004#define MC_CMD_PHY_CAP_100000FDX_WIDTH 15005#define MC_CMD_PHY_CAP_25000FDX_OFST 85006#define MC_CMD_PHY_CAP_25000FDX_LBN 145007#define MC_CMD_PHY_CAP_25000FDX_WIDTH 15008#define MC_CMD_PHY_CAP_50000FDX_OFST 85009#define MC_CMD_PHY_CAP_50000FDX_LBN 155010#define MC_CMD_PHY_CAP_50000FDX_WIDTH 15011#define MC_CMD_PHY_CAP_BASER_FEC_OFST 85012#define MC_CMD_PHY_CAP_BASER_FEC_LBN 165013#define MC_CMD_PHY_CAP_BASER_FEC_WIDTH 15014#define MC_CMD_PHY_CAP_BASER_FEC_REQUESTED_OFST 85015#define MC_CMD_PHY_CAP_BASER_FEC_REQUESTED_LBN 175016#define MC_CMD_PHY_CAP_BASER_FEC_REQUESTED_WIDTH 15017#define MC_CMD_PHY_CAP_RS_FEC_OFST 85018#define MC_CMD_PHY_CAP_RS_FEC_LBN 185019#define MC_CMD_PHY_CAP_RS_FEC_WIDTH 15020#define MC_CMD_PHY_CAP_RS_FEC_REQUESTED_OFST 85021#define MC_CMD_PHY_CAP_RS_FEC_REQUESTED_LBN 195022#define MC_CMD_PHY_CAP_RS_FEC_REQUESTED_WIDTH 15023#define MC_CMD_PHY_CAP_25G_BASER_FEC_OFST 85024#define MC_CMD_PHY_CAP_25G_BASER_FEC_LBN 205025#define MC_CMD_PHY_CAP_25G_BASER_FEC_WIDTH 15026#define MC_CMD_PHY_CAP_25G_BASER_FEC_REQUESTED_OFST 85027#define MC_CMD_PHY_CAP_25G_BASER_FEC_REQUESTED_LBN 215028#define MC_CMD_PHY_CAP_25G_BASER_FEC_REQUESTED_WIDTH 15029/* ?? */5030#define MC_CMD_GET_PHY_CFG_OUT_CHANNEL_OFST 125031#define MC_CMD_GET_PHY_CFG_OUT_CHANNEL_LEN 45032/* ?? */5033#define MC_CMD_GET_PHY_CFG_OUT_PRT_OFST 165034#define MC_CMD_GET_PHY_CFG_OUT_PRT_LEN 45035/* ?? */5036#define MC_CMD_GET_PHY_CFG_OUT_STATS_MASK_OFST 205037#define MC_CMD_GET_PHY_CFG_OUT_STATS_MASK_LEN 45038/* ?? */5039#define MC_CMD_GET_PHY_CFG_OUT_NAME_OFST 245040#define MC_CMD_GET_PHY_CFG_OUT_NAME_LEN 205041/* ?? */5042#define MC_CMD_GET_PHY_CFG_OUT_MEDIA_TYPE_OFST 445043#define MC_CMD_GET_PHY_CFG_OUT_MEDIA_TYPE_LEN 45044/* enum: Xaui. */5045#define MC_CMD_MEDIA_XAUI 0x15046/* enum: CX4. */5047#define MC_CMD_MEDIA_CX4 0x25048/* enum: KX4. */5049#define MC_CMD_MEDIA_KX4 0x35050/* enum: XFP Far. */5051#define MC_CMD_MEDIA_XFP 0x45052/* enum: SFP+. */5053#define MC_CMD_MEDIA_SFP_PLUS 0x55054/* enum: 10GBaseT. */5055#define MC_CMD_MEDIA_BASE_T 0x65056/* enum: QSFP+. */5057#define MC_CMD_MEDIA_QSFP_PLUS 0x75058/* enum: DSFP. */5059#define MC_CMD_MEDIA_DSFP 0x85060#define MC_CMD_GET_PHY_CFG_OUT_MMD_MASK_OFST 485061#define MC_CMD_GET_PHY_CFG_OUT_MMD_MASK_LEN 45062/* enum: Native clause 22 */5063#define MC_CMD_MMD_CLAUSE22 0x05064#define MC_CMD_MMD_CLAUSE45_PMAPMD 0x1 /* enum */5065#define MC_CMD_MMD_CLAUSE45_WIS 0x2 /* enum */5066#define MC_CMD_MMD_CLAUSE45_PCS 0x3 /* enum */5067#define MC_CMD_MMD_CLAUSE45_PHYXS 0x4 /* enum */5068#define MC_CMD_MMD_CLAUSE45_DTEXS 0x5 /* enum */5069#define MC_CMD_MMD_CLAUSE45_TC 0x6 /* enum */5070#define MC_CMD_MMD_CLAUSE45_AN 0x7 /* enum */5071/* enum: Clause22 proxied over clause45 by PHY. */5072#define MC_CMD_MMD_CLAUSE45_C22EXT 0x1d5073#define MC_CMD_MMD_CLAUSE45_VEND1 0x1e /* enum */5074#define MC_CMD_MMD_CLAUSE45_VEND2 0x1f /* enum */5075#define MC_CMD_GET_PHY_CFG_OUT_REVISION_OFST 525076#define MC_CMD_GET_PHY_CFG_OUT_REVISION_LEN 205077 5078 5079/***********************************/5080/* MC_CMD_START_BIST5081 * Start a BIST test on the PHY. Locks required: PHY_LOCK if doing a PHY BIST5082 * Return code: 0, EINVAL, EACCES (if PHY_LOCK is not held)5083 */5084#define MC_CMD_START_BIST 0x255085#undef MC_CMD_0x25_PRIVILEGE_CTG5086 5087#define MC_CMD_0x25_PRIVILEGE_CTG SRIOV_CTG_ADMIN5088 5089/* MC_CMD_START_BIST_IN msgrequest */5090#define MC_CMD_START_BIST_IN_LEN 45091/* Type of test. */5092#define MC_CMD_START_BIST_IN_TYPE_OFST 05093#define MC_CMD_START_BIST_IN_TYPE_LEN 45094/* enum: Run the PHY's short cable BIST. */5095#define MC_CMD_PHY_BIST_CABLE_SHORT 0x15096/* enum: Run the PHY's long cable BIST. */5097#define MC_CMD_PHY_BIST_CABLE_LONG 0x25098/* enum: Run BIST on the currently selected BPX Serdes (XAUI or XFI) . */5099#define MC_CMD_BPX_SERDES_BIST 0x35100/* enum: Run the MC loopback tests. */5101#define MC_CMD_MC_LOOPBACK_BIST 0x45102/* enum: Run the PHY's standard BIST. */5103#define MC_CMD_PHY_BIST 0x55104/* enum: Run MC RAM test. */5105#define MC_CMD_MC_MEM_BIST 0x65106/* enum: Run Port RAM test. */5107#define MC_CMD_PORT_MEM_BIST 0x75108/* enum: Run register test. */5109#define MC_CMD_REG_BIST 0x85110 5111/* MC_CMD_START_BIST_OUT msgresponse */5112#define MC_CMD_START_BIST_OUT_LEN 05113 5114 5115/***********************************/5116/* MC_CMD_POLL_BIST5117 * Poll for BIST completion. Returns a single status code, and optionally some5118 * PHY specific bist output. The driver should only consume the BIST output5119 * after validating OUTLEN and MC_CMD_GET_PHY_CFG.TYPE. If a driver can't5120 * successfully parse the BIST output, it should still respect the pass/Fail in5121 * OUT.RESULT. Locks required: PHY_LOCK if doing a PHY BIST. Return code: 0,5122 * EACCES (if PHY_LOCK is not held).5123 */5124#define MC_CMD_POLL_BIST 0x265125#undef MC_CMD_0x26_PRIVILEGE_CTG5126 5127#define MC_CMD_0x26_PRIVILEGE_CTG SRIOV_CTG_ADMIN5128 5129/* MC_CMD_POLL_BIST_IN msgrequest */5130#define MC_CMD_POLL_BIST_IN_LEN 05131 5132/* MC_CMD_POLL_BIST_OUT msgresponse */5133#define MC_CMD_POLL_BIST_OUT_LEN 85134/* result */5135#define MC_CMD_POLL_BIST_OUT_RESULT_OFST 05136#define MC_CMD_POLL_BIST_OUT_RESULT_LEN 45137/* enum: Running. */5138#define MC_CMD_POLL_BIST_RUNNING 0x15139/* enum: Passed. */5140#define MC_CMD_POLL_BIST_PASSED 0x25141/* enum: Failed. */5142#define MC_CMD_POLL_BIST_FAILED 0x35143/* enum: Timed-out. */5144#define MC_CMD_POLL_BIST_TIMEOUT 0x45145#define MC_CMD_POLL_BIST_OUT_PRIVATE_OFST 45146#define MC_CMD_POLL_BIST_OUT_PRIVATE_LEN 45147 5148/* MC_CMD_POLL_BIST_OUT_SFT9001 msgresponse */5149#define MC_CMD_POLL_BIST_OUT_SFT9001_LEN 365150/* result */5151/* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */5152/* MC_CMD_POLL_BIST_OUT_RESULT_LEN 4 */5153/* Enum values, see field(s): */5154/* MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */5155#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_A_OFST 45156#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_A_LEN 45157#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_B_OFST 85158#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_B_LEN 45159#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_C_OFST 125160#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_C_LEN 45161#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_D_OFST 165162#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_D_LEN 45163/* Status of each channel A */5164#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_A_OFST 205165#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_A_LEN 45166/* enum: Ok. */5167#define MC_CMD_POLL_BIST_SFT9001_PAIR_OK 0x15168/* enum: Open. */5169#define MC_CMD_POLL_BIST_SFT9001_PAIR_OPEN 0x25170/* enum: Intra-pair short. */5171#define MC_CMD_POLL_BIST_SFT9001_INTRA_PAIR_SHORT 0x35172/* enum: Inter-pair short. */5173#define MC_CMD_POLL_BIST_SFT9001_INTER_PAIR_SHORT 0x45174/* enum: Busy. */5175#define MC_CMD_POLL_BIST_SFT9001_PAIR_BUSY 0x95176/* Status of each channel B */5177#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_B_OFST 245178#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_B_LEN 45179/* Enum values, see field(s): */5180/* CABLE_STATUS_A */5181/* Status of each channel C */5182#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_C_OFST 285183#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_C_LEN 45184/* Enum values, see field(s): */5185/* CABLE_STATUS_A */5186/* Status of each channel D */5187#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_D_OFST 325188#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_D_LEN 45189/* Enum values, see field(s): */5190/* CABLE_STATUS_A */5191 5192/* MC_CMD_POLL_BIST_OUT_MRSFP msgresponse */5193#define MC_CMD_POLL_BIST_OUT_MRSFP_LEN 85194/* result */5195/* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */5196/* MC_CMD_POLL_BIST_OUT_RESULT_LEN 4 */5197/* Enum values, see field(s): */5198/* MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */5199#define MC_CMD_POLL_BIST_OUT_MRSFP_TEST_OFST 45200#define MC_CMD_POLL_BIST_OUT_MRSFP_TEST_LEN 45201/* enum: Complete. */5202#define MC_CMD_POLL_BIST_MRSFP_TEST_COMPLETE 0x05203/* enum: Bus switch off I2C write. */5204#define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_WRITE 0x15205/* enum: Bus switch off I2C no access IO exp. */5206#define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_NO_ACCESS_IO_EXP 0x25207/* enum: Bus switch off I2C no access module. */5208#define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_NO_ACCESS_MODULE 0x35209/* enum: IO exp I2C configure. */5210#define MC_CMD_POLL_BIST_MRSFP_TEST_IO_EXP_I2C_CONFIGURE 0x45211/* enum: Bus switch I2C no cross talk. */5212#define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_I2C_NO_CROSSTALK 0x55213/* enum: Module presence. */5214#define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_PRESENCE 0x65215/* enum: Module ID I2C access. */5216#define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_ID_I2C_ACCESS 0x75217/* enum: Module ID sane value. */5218#define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_ID_SANE_VALUE 0x85219 5220/* MC_CMD_POLL_BIST_OUT_MEM msgresponse */5221#define MC_CMD_POLL_BIST_OUT_MEM_LEN 365222/* result */5223/* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */5224/* MC_CMD_POLL_BIST_OUT_RESULT_LEN 4 */5225/* Enum values, see field(s): */5226/* MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */5227#define MC_CMD_POLL_BIST_OUT_MEM_TEST_OFST 45228#define MC_CMD_POLL_BIST_OUT_MEM_TEST_LEN 45229/* enum: Test has completed. */5230#define MC_CMD_POLL_BIST_MEM_COMPLETE 0x05231/* enum: RAM test - walk ones. */5232#define MC_CMD_POLL_BIST_MEM_MEM_WALK_ONES 0x15233/* enum: RAM test - walk zeros. */5234#define MC_CMD_POLL_BIST_MEM_MEM_WALK_ZEROS 0x25235/* enum: RAM test - walking inversions zeros/ones. */5236#define MC_CMD_POLL_BIST_MEM_MEM_INV_ZERO_ONE 0x35237/* enum: RAM test - walking inversions checkerboard. */5238#define MC_CMD_POLL_BIST_MEM_MEM_INV_CHKBOARD 0x45239/* enum: Register test - set / clear individual bits. */5240#define MC_CMD_POLL_BIST_MEM_REG 0x55241/* enum: ECC error detected. */5242#define MC_CMD_POLL_BIST_MEM_ECC 0x65243/* Failure address, only valid if result is POLL_BIST_FAILED */5244#define MC_CMD_POLL_BIST_OUT_MEM_ADDR_OFST 85245#define MC_CMD_POLL_BIST_OUT_MEM_ADDR_LEN 45246/* Bus or address space to which the failure address corresponds */5247#define MC_CMD_POLL_BIST_OUT_MEM_BUS_OFST 125248#define MC_CMD_POLL_BIST_OUT_MEM_BUS_LEN 45249/* enum: MC MIPS bus. */5250#define MC_CMD_POLL_BIST_MEM_BUS_MC 0x05251/* enum: CSR IREG bus. */5252#define MC_CMD_POLL_BIST_MEM_BUS_CSR 0x15253/* enum: RX0 DPCPU bus. */5254#define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_RX 0x25255/* enum: TX0 DPCPU bus. */5256#define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_TX0 0x35257/* enum: TX1 DPCPU bus. */5258#define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_TX1 0x45259/* enum: RX0 DICPU bus. */5260#define MC_CMD_POLL_BIST_MEM_BUS_DICPU_RX 0x55261/* enum: TX DICPU bus. */5262#define MC_CMD_POLL_BIST_MEM_BUS_DICPU_TX 0x65263/* enum: RX1 DPCPU bus. */5264#define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_RX1 0x75265/* enum: RX1 DICPU bus. */5266#define MC_CMD_POLL_BIST_MEM_BUS_DICPU_RX1 0x85267/* Pattern written to RAM / register */5268#define MC_CMD_POLL_BIST_OUT_MEM_EXPECT_OFST 165269#define MC_CMD_POLL_BIST_OUT_MEM_EXPECT_LEN 45270/* Actual value read from RAM / register */5271#define MC_CMD_POLL_BIST_OUT_MEM_ACTUAL_OFST 205272#define MC_CMD_POLL_BIST_OUT_MEM_ACTUAL_LEN 45273/* ECC error mask */5274#define MC_CMD_POLL_BIST_OUT_MEM_ECC_OFST 245275#define MC_CMD_POLL_BIST_OUT_MEM_ECC_LEN 45276/* ECC parity error mask */5277#define MC_CMD_POLL_BIST_OUT_MEM_ECC_PARITY_OFST 285278#define MC_CMD_POLL_BIST_OUT_MEM_ECC_PARITY_LEN 45279/* ECC fatal error mask */5280#define MC_CMD_POLL_BIST_OUT_MEM_ECC_FATAL_OFST 325281#define MC_CMD_POLL_BIST_OUT_MEM_ECC_FATAL_LEN 45282 5283 5284/***********************************/5285/* MC_CMD_FLUSH_RX_QUEUES5286 * Flush receive queue(s). If SRIOV is enabled (via MC_CMD_SRIOV), then RXQ5287 * flushes should be initiated via this MCDI operation, rather than via5288 * directly writing FLUSH_CMD.5289 *5290 * The flush is completed (either done/fail) asynchronously (after this command5291 * returns). The driver must still wait for flush done/failure events as usual.5292 */5293#define MC_CMD_FLUSH_RX_QUEUES 0x275294 5295/* MC_CMD_FLUSH_RX_QUEUES_IN msgrequest */5296#define MC_CMD_FLUSH_RX_QUEUES_IN_LENMIN 45297#define MC_CMD_FLUSH_RX_QUEUES_IN_LENMAX 2525298#define MC_CMD_FLUSH_RX_QUEUES_IN_LENMAX_MCDI2 10205299#define MC_CMD_FLUSH_RX_QUEUES_IN_LEN(num) (0+4*(num))5300#define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_NUM(len) (((len)-0)/4)5301#define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_OFST 05302#define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_LEN 45303#define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_MINNUM 15304#define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_MAXNUM 635305#define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_MAXNUM_MCDI2 2555306 5307/* MC_CMD_FLUSH_RX_QUEUES_OUT msgresponse */5308#define MC_CMD_FLUSH_RX_QUEUES_OUT_LEN 05309 5310 5311/***********************************/5312/* MC_CMD_GET_LOOPBACK_MODES5313 * Returns a bitmask of loopback modes available at each speed.5314 */5315#define MC_CMD_GET_LOOPBACK_MODES 0x285316#undef MC_CMD_0x28_PRIVILEGE_CTG5317 5318#define MC_CMD_0x28_PRIVILEGE_CTG SRIOV_CTG_GENERAL5319 5320/* MC_CMD_GET_LOOPBACK_MODES_IN msgrequest */5321#define MC_CMD_GET_LOOPBACK_MODES_IN_LEN 05322 5323/* MC_CMD_GET_LOOPBACK_MODES_OUT msgresponse */5324#define MC_CMD_GET_LOOPBACK_MODES_OUT_LEN 405325/* Supported loopbacks. */5326#define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_OFST 05327#define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LEN 85328#define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LO_OFST 05329#define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LO_LEN 45330#define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LO_LBN 05331#define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LO_WIDTH 325332#define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_HI_OFST 45333#define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_HI_LEN 45334#define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_HI_LBN 325335#define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_HI_WIDTH 325336/* enum: None. */5337#define MC_CMD_LOOPBACK_NONE 0x05338/* enum: Data. */5339#define MC_CMD_LOOPBACK_DATA 0x15340/* enum: GMAC. */5341#define MC_CMD_LOOPBACK_GMAC 0x25342/* enum: XGMII. */5343#define MC_CMD_LOOPBACK_XGMII 0x35344/* enum: XGXS. */5345#define MC_CMD_LOOPBACK_XGXS 0x45346/* enum: XAUI. */5347#define MC_CMD_LOOPBACK_XAUI 0x55348/* enum: GMII. */5349#define MC_CMD_LOOPBACK_GMII 0x65350/* enum: SGMII. */5351#define MC_CMD_LOOPBACK_SGMII 0x75352/* enum: XGBR. */5353#define MC_CMD_LOOPBACK_XGBR 0x85354/* enum: XFI. */5355#define MC_CMD_LOOPBACK_XFI 0x95356/* enum: XAUI Far. */5357#define MC_CMD_LOOPBACK_XAUI_FAR 0xa5358/* enum: GMII Far. */5359#define MC_CMD_LOOPBACK_GMII_FAR 0xb5360/* enum: SGMII Far. */5361#define MC_CMD_LOOPBACK_SGMII_FAR 0xc5362/* enum: XFI Far. */5363#define MC_CMD_LOOPBACK_XFI_FAR 0xd5364/* enum: GPhy. */5365#define MC_CMD_LOOPBACK_GPHY 0xe5366/* enum: PhyXS. */5367#define MC_CMD_LOOPBACK_PHYXS 0xf5368/* enum: PCS. */5369#define MC_CMD_LOOPBACK_PCS 0x105370/* enum: PMA-PMD. */5371#define MC_CMD_LOOPBACK_PMAPMD 0x115372/* enum: Cross-Port. */5373#define MC_CMD_LOOPBACK_XPORT 0x125374/* enum: XGMII-Wireside. */5375#define MC_CMD_LOOPBACK_XGMII_WS 0x135376/* enum: XAUI Wireside. */5377#define MC_CMD_LOOPBACK_XAUI_WS 0x145378/* enum: XAUI Wireside Far. */5379#define MC_CMD_LOOPBACK_XAUI_WS_FAR 0x155380/* enum: XAUI Wireside near. */5381#define MC_CMD_LOOPBACK_XAUI_WS_NEAR 0x165382/* enum: GMII Wireside. */5383#define MC_CMD_LOOPBACK_GMII_WS 0x175384/* enum: XFI Wireside. */5385#define MC_CMD_LOOPBACK_XFI_WS 0x185386/* enum: XFI Wireside Far. */5387#define MC_CMD_LOOPBACK_XFI_WS_FAR 0x195388/* enum: PhyXS Wireside. */5389#define MC_CMD_LOOPBACK_PHYXS_WS 0x1a5390/* enum: PMA lanes MAC-Serdes. */5391#define MC_CMD_LOOPBACK_PMA_INT 0x1b5392/* enum: KR Serdes Parallel (Encoder). */5393#define MC_CMD_LOOPBACK_SD_NEAR 0x1c5394/* enum: KR Serdes Serial. */5395#define MC_CMD_LOOPBACK_SD_FAR 0x1d5396/* enum: PMA lanes MAC-Serdes Wireside. */5397#define MC_CMD_LOOPBACK_PMA_INT_WS 0x1e5398/* enum: KR Serdes Parallel Wireside (Full PCS). */5399#define MC_CMD_LOOPBACK_SD_FEP2_WS 0x1f5400/* enum: KR Serdes Parallel Wireside (Sym Aligner to TX). */5401#define MC_CMD_LOOPBACK_SD_FEP1_5_WS 0x205402/* enum: KR Serdes Parallel Wireside (Deserializer to Serializer). */5403#define MC_CMD_LOOPBACK_SD_FEP_WS 0x215404/* enum: KR Serdes Serial Wireside. */5405#define MC_CMD_LOOPBACK_SD_FES_WS 0x225406/* enum: Near side of AOE Siena side port */5407#define MC_CMD_LOOPBACK_AOE_INT_NEAR 0x235408/* enum: Medford Wireside datapath loopback */5409#define MC_CMD_LOOPBACK_DATA_WS 0x245410/* enum: Force link up without setting up any physical loopback (snapper use5411 * only)5412 */5413#define MC_CMD_LOOPBACK_FORCE_EXT_LINK 0x255414/* Supported loopbacks. */5415#define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_OFST 85416#define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_LEN 85417#define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_LO_OFST 85418#define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_LO_LEN 45419#define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_LO_LBN 645420#define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_LO_WIDTH 325421#define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_HI_OFST 125422#define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_HI_LEN 45423#define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_HI_LBN 965424#define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_HI_WIDTH 325425/* Enum values, see field(s): */5426/* 100M */5427/* Supported loopbacks. */5428#define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_OFST 165429#define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_LEN 85430#define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_LO_OFST 165431#define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_LO_LEN 45432#define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_LO_LBN 1285433#define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_LO_WIDTH 325434#define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_HI_OFST 205435#define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_HI_LEN 45436#define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_HI_LBN 1605437#define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_HI_WIDTH 325438/* Enum values, see field(s): */5439/* 100M */5440/* Supported loopbacks. */5441#define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_OFST 245442#define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LEN 85443#define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LO_OFST 245444#define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LO_LEN 45445#define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LO_LBN 1925446#define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LO_WIDTH 325447#define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_HI_OFST 285448#define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_HI_LEN 45449#define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_HI_LBN 2245450#define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_HI_WIDTH 325451/* Enum values, see field(s): */5452/* 100M */5453/* Supported loopbacks. */5454#define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_OFST 325455#define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LEN 85456#define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LO_OFST 325457#define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LO_LEN 45458#define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LO_LBN 2565459#define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LO_WIDTH 325460#define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_HI_OFST 365461#define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_HI_LEN 45462#define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_HI_LBN 2885463#define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_HI_WIDTH 325464/* Enum values, see field(s): */5465/* 100M */5466 5467/* MC_CMD_GET_LOOPBACK_MODES_OUT_V2 msgresponse: Supported loopback modes for5468 * newer NICs with 25G/50G/100G support5469 */5470#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_LEN 645471/* Supported loopbacks. */5472#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_OFST 05473#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_LEN 85474#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_LO_OFST 05475#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_LO_LEN 45476#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_LO_LBN 05477#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_LO_WIDTH 325478#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_HI_OFST 45479#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_HI_LEN 45480#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_HI_LBN 325481#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_HI_WIDTH 325482/* enum: None. */5483/* MC_CMD_LOOPBACK_NONE 0x0 */5484/* enum: Data. */5485/* MC_CMD_LOOPBACK_DATA 0x1 */5486/* enum: GMAC. */5487/* MC_CMD_LOOPBACK_GMAC 0x2 */5488/* enum: XGMII. */5489/* MC_CMD_LOOPBACK_XGMII 0x3 */5490/* enum: XGXS. */5491/* MC_CMD_LOOPBACK_XGXS 0x4 */5492/* enum: XAUI. */5493/* MC_CMD_LOOPBACK_XAUI 0x5 */5494/* enum: GMII. */5495/* MC_CMD_LOOPBACK_GMII 0x6 */5496/* enum: SGMII. */5497/* MC_CMD_LOOPBACK_SGMII 0x7 */5498/* enum: XGBR. */5499/* MC_CMD_LOOPBACK_XGBR 0x8 */5500/* enum: XFI. */5501/* MC_CMD_LOOPBACK_XFI 0x9 */5502/* enum: XAUI Far. */5503/* MC_CMD_LOOPBACK_XAUI_FAR 0xa */5504/* enum: GMII Far. */5505/* MC_CMD_LOOPBACK_GMII_FAR 0xb */5506/* enum: SGMII Far. */5507/* MC_CMD_LOOPBACK_SGMII_FAR 0xc */5508/* enum: XFI Far. */5509/* MC_CMD_LOOPBACK_XFI_FAR 0xd */5510/* enum: GPhy. */5511/* MC_CMD_LOOPBACK_GPHY 0xe */5512/* enum: PhyXS. */5513/* MC_CMD_LOOPBACK_PHYXS 0xf */5514/* enum: PCS. */5515/* MC_CMD_LOOPBACK_PCS 0x10 */5516/* enum: PMA-PMD. */5517/* MC_CMD_LOOPBACK_PMAPMD 0x11 */5518/* enum: Cross-Port. */5519/* MC_CMD_LOOPBACK_XPORT 0x12 */5520/* enum: XGMII-Wireside. */5521/* MC_CMD_LOOPBACK_XGMII_WS 0x13 */5522/* enum: XAUI Wireside. */5523/* MC_CMD_LOOPBACK_XAUI_WS 0x14 */5524/* enum: XAUI Wireside Far. */5525/* MC_CMD_LOOPBACK_XAUI_WS_FAR 0x15 */5526/* enum: XAUI Wireside near. */5527/* MC_CMD_LOOPBACK_XAUI_WS_NEAR 0x16 */5528/* enum: GMII Wireside. */5529/* MC_CMD_LOOPBACK_GMII_WS 0x17 */5530/* enum: XFI Wireside. */5531/* MC_CMD_LOOPBACK_XFI_WS 0x18 */5532/* enum: XFI Wireside Far. */5533/* MC_CMD_LOOPBACK_XFI_WS_FAR 0x19 */5534/* enum: PhyXS Wireside. */5535/* MC_CMD_LOOPBACK_PHYXS_WS 0x1a */5536/* enum: PMA lanes MAC-Serdes. */5537/* MC_CMD_LOOPBACK_PMA_INT 0x1b */5538/* enum: KR Serdes Parallel (Encoder). */5539/* MC_CMD_LOOPBACK_SD_NEAR 0x1c */5540/* enum: KR Serdes Serial. */5541/* MC_CMD_LOOPBACK_SD_FAR 0x1d */5542/* enum: PMA lanes MAC-Serdes Wireside. */5543/* MC_CMD_LOOPBACK_PMA_INT_WS 0x1e */5544/* enum: KR Serdes Parallel Wireside (Full PCS). */5545/* MC_CMD_LOOPBACK_SD_FEP2_WS 0x1f */5546/* enum: KR Serdes Parallel Wireside (Sym Aligner to TX). */5547/* MC_CMD_LOOPBACK_SD_FEP1_5_WS 0x20 */5548/* enum: KR Serdes Parallel Wireside (Deserializer to Serializer). */5549/* MC_CMD_LOOPBACK_SD_FEP_WS 0x21 */5550/* enum: KR Serdes Serial Wireside. */5551/* MC_CMD_LOOPBACK_SD_FES_WS 0x22 */5552/* enum: Near side of AOE Siena side port */5553/* MC_CMD_LOOPBACK_AOE_INT_NEAR 0x23 */5554/* enum: Medford Wireside datapath loopback */5555/* MC_CMD_LOOPBACK_DATA_WS 0x24 */5556/* enum: Force link up without setting up any physical loopback (snapper use5557 * only)5558 */5559/* MC_CMD_LOOPBACK_FORCE_EXT_LINK 0x25 */5560/* Supported loopbacks. */5561#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_OFST 85562#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_LEN 85563#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_LO_OFST 85564#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_LO_LEN 45565#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_LO_LBN 645566#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_LO_WIDTH 325567#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_HI_OFST 125568#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_HI_LEN 45569#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_HI_LBN 965570#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_HI_WIDTH 325571/* Enum values, see field(s): */5572/* 100M */5573/* Supported loopbacks. */5574#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_OFST 165575#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_LEN 85576#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_LO_OFST 165577#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_LO_LEN 45578#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_LO_LBN 1285579#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_LO_WIDTH 325580#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_HI_OFST 205581#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_HI_LEN 45582#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_HI_LBN 1605583#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_HI_WIDTH 325584/* Enum values, see field(s): */5585/* 100M */5586/* Supported loopbacks. */5587#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_OFST 245588#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_LEN 85589#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_LO_OFST 245590#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_LO_LEN 45591#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_LO_LBN 1925592#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_LO_WIDTH 325593#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_HI_OFST 285594#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_HI_LEN 45595#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_HI_LBN 2245596#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_HI_WIDTH 325597/* Enum values, see field(s): */5598/* 100M */5599/* Supported loopbacks. */5600#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_OFST 325601#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_LEN 85602#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_LO_OFST 325603#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_LO_LEN 45604#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_LO_LBN 2565605#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_LO_WIDTH 325606#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_HI_OFST 365607#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_HI_LEN 45608#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_HI_LBN 2885609#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_HI_WIDTH 325610/* Enum values, see field(s): */5611/* 100M */5612/* Supported 25G loopbacks. */5613#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_OFST 405614#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_LEN 85615#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_LO_OFST 405616#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_LO_LEN 45617#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_LO_LBN 3205618#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_LO_WIDTH 325619#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_HI_OFST 445620#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_HI_LEN 45621#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_HI_LBN 3525622#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_HI_WIDTH 325623/* Enum values, see field(s): */5624/* 100M */5625/* Supported 50 loopbacks. */5626#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_OFST 485627#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_LEN 85628#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_LO_OFST 485629#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_LO_LEN 45630#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_LO_LBN 3845631#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_LO_WIDTH 325632#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_HI_OFST 525633#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_HI_LEN 45634#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_HI_LBN 4165635#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_HI_WIDTH 325636/* Enum values, see field(s): */5637/* 100M */5638/* Supported 100G loopbacks. */5639#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_OFST 565640#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_LEN 85641#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_LO_OFST 565642#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_LO_LEN 45643#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_LO_LBN 4485644#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_LO_WIDTH 325645#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_HI_OFST 605646#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_HI_LEN 45647#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_HI_LBN 4805648#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_HI_WIDTH 325649/* Enum values, see field(s): */5650/* 100M */5651 5652/* AN_TYPE structuredef: Auto-negotiation types defined in IEEE802.3 */5653#define AN_TYPE_LEN 45654#define AN_TYPE_TYPE_OFST 05655#define AN_TYPE_TYPE_LEN 45656/* enum: None, AN disabled or not supported */5657#define MC_CMD_AN_NONE 0x05658/* enum: Clause 28 - BASE-T */5659#define MC_CMD_AN_CLAUSE28 0x15660/* enum: Clause 37 - BASE-X */5661#define MC_CMD_AN_CLAUSE37 0x25662/* enum: Clause 73 - BASE-R startup protocol for backplane and copper cable5663 * assemblies. Includes Clause 72/Clause 92 link-training.5664 */5665#define MC_CMD_AN_CLAUSE73 0x35666#define AN_TYPE_TYPE_LBN 05667#define AN_TYPE_TYPE_WIDTH 325668 5669/* FEC_TYPE structuredef: Forward error correction types defined in IEEE802.35670 */5671#define FEC_TYPE_LEN 45672#define FEC_TYPE_TYPE_OFST 05673#define FEC_TYPE_TYPE_LEN 45674/* enum: No FEC */5675#define MC_CMD_FEC_NONE 0x05676/* enum: Clause 74 BASE-R FEC (a.k.a Firecode) */5677#define MC_CMD_FEC_BASER 0x15678/* enum: Clause 91/Clause 108 Reed-Solomon FEC */5679#define MC_CMD_FEC_RS 0x25680#define FEC_TYPE_TYPE_LBN 05681#define FEC_TYPE_TYPE_WIDTH 325682 5683 5684/***********************************/5685/* MC_CMD_GET_LINK5686 * Read the unified MAC/PHY link state. Locks required: None Return code: 0,5687 * ETIME.5688 */5689#define MC_CMD_GET_LINK 0x295690#undef MC_CMD_0x29_PRIVILEGE_CTG5691 5692#define MC_CMD_0x29_PRIVILEGE_CTG SRIOV_CTG_GENERAL5693 5694/* MC_CMD_GET_LINK_IN msgrequest */5695#define MC_CMD_GET_LINK_IN_LEN 05696 5697/* MC_CMD_GET_LINK_OUT msgresponse */5698#define MC_CMD_GET_LINK_OUT_LEN 285699/* Near-side advertised capabilities. Refer to5700 * MC_CMD_GET_PHY_CFG_OUT/SUPPORTED_CAP for bit definitions.5701 */5702#define MC_CMD_GET_LINK_OUT_CAP_OFST 05703#define MC_CMD_GET_LINK_OUT_CAP_LEN 45704/* Link-partner advertised capabilities. Refer to5705 * MC_CMD_GET_PHY_CFG_OUT/SUPPORTED_CAP for bit definitions.5706 */5707#define MC_CMD_GET_LINK_OUT_LP_CAP_OFST 45708#define MC_CMD_GET_LINK_OUT_LP_CAP_LEN 45709/* Autonegotiated speed in mbit/s. The link may still be down even if this5710 * reads non-zero.5711 */5712#define MC_CMD_GET_LINK_OUT_LINK_SPEED_OFST 85713#define MC_CMD_GET_LINK_OUT_LINK_SPEED_LEN 45714/* Current loopback setting. */5715#define MC_CMD_GET_LINK_OUT_LOOPBACK_MODE_OFST 125716#define MC_CMD_GET_LINK_OUT_LOOPBACK_MODE_LEN 45717/* Enum values, see field(s): */5718/* MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */5719#define MC_CMD_GET_LINK_OUT_FLAGS_OFST 165720#define MC_CMD_GET_LINK_OUT_FLAGS_LEN 45721#define MC_CMD_GET_LINK_OUT_LINK_UP_OFST 165722#define MC_CMD_GET_LINK_OUT_LINK_UP_LBN 05723#define MC_CMD_GET_LINK_OUT_LINK_UP_WIDTH 15724#define MC_CMD_GET_LINK_OUT_FULL_DUPLEX_OFST 165725#define MC_CMD_GET_LINK_OUT_FULL_DUPLEX_LBN 15726#define MC_CMD_GET_LINK_OUT_FULL_DUPLEX_WIDTH 15727#define MC_CMD_GET_LINK_OUT_BPX_LINK_OFST 165728#define MC_CMD_GET_LINK_OUT_BPX_LINK_LBN 25729#define MC_CMD_GET_LINK_OUT_BPX_LINK_WIDTH 15730#define MC_CMD_GET_LINK_OUT_PHY_LINK_OFST 165731#define MC_CMD_GET_LINK_OUT_PHY_LINK_LBN 35732#define MC_CMD_GET_LINK_OUT_PHY_LINK_WIDTH 15733#define MC_CMD_GET_LINK_OUT_LINK_FAULT_RX_OFST 165734#define MC_CMD_GET_LINK_OUT_LINK_FAULT_RX_LBN 65735#define MC_CMD_GET_LINK_OUT_LINK_FAULT_RX_WIDTH 15736#define MC_CMD_GET_LINK_OUT_LINK_FAULT_TX_OFST 165737#define MC_CMD_GET_LINK_OUT_LINK_FAULT_TX_LBN 75738#define MC_CMD_GET_LINK_OUT_LINK_FAULT_TX_WIDTH 15739#define MC_CMD_GET_LINK_OUT_MODULE_UP_VALID_OFST 165740#define MC_CMD_GET_LINK_OUT_MODULE_UP_VALID_LBN 85741#define MC_CMD_GET_LINK_OUT_MODULE_UP_VALID_WIDTH 15742#define MC_CMD_GET_LINK_OUT_MODULE_UP_OFST 165743#define MC_CMD_GET_LINK_OUT_MODULE_UP_LBN 95744#define MC_CMD_GET_LINK_OUT_MODULE_UP_WIDTH 15745/* This returns the negotiated flow control value. */5746#define MC_CMD_GET_LINK_OUT_FCNTL_OFST 205747#define MC_CMD_GET_LINK_OUT_FCNTL_LEN 45748/* Enum values, see field(s): */5749/* MC_CMD_SET_MAC/MC_CMD_SET_MAC_IN/FCNTL */5750#define MC_CMD_GET_LINK_OUT_MAC_FAULT_OFST 245751#define MC_CMD_GET_LINK_OUT_MAC_FAULT_LEN 45752#define MC_CMD_MAC_FAULT_XGMII_LOCAL_OFST 245753#define MC_CMD_MAC_FAULT_XGMII_LOCAL_LBN 05754#define MC_CMD_MAC_FAULT_XGMII_LOCAL_WIDTH 15755#define MC_CMD_MAC_FAULT_XGMII_REMOTE_OFST 245756#define MC_CMD_MAC_FAULT_XGMII_REMOTE_LBN 15757#define MC_CMD_MAC_FAULT_XGMII_REMOTE_WIDTH 15758#define MC_CMD_MAC_FAULT_SGMII_REMOTE_OFST 245759#define MC_CMD_MAC_FAULT_SGMII_REMOTE_LBN 25760#define MC_CMD_MAC_FAULT_SGMII_REMOTE_WIDTH 15761#define MC_CMD_MAC_FAULT_PENDING_RECONFIG_OFST 245762#define MC_CMD_MAC_FAULT_PENDING_RECONFIG_LBN 35763#define MC_CMD_MAC_FAULT_PENDING_RECONFIG_WIDTH 15764 5765/* MC_CMD_GET_LINK_OUT_V2 msgresponse: Extended link state information */5766#define MC_CMD_GET_LINK_OUT_V2_LEN 445767/* Near-side advertised capabilities. Refer to5768 * MC_CMD_GET_PHY_CFG_OUT/SUPPORTED_CAP for bit definitions.5769 */5770#define MC_CMD_GET_LINK_OUT_V2_CAP_OFST 05771#define MC_CMD_GET_LINK_OUT_V2_CAP_LEN 45772/* Link-partner advertised capabilities. Refer to5773 * MC_CMD_GET_PHY_CFG_OUT/SUPPORTED_CAP for bit definitions.5774 */5775#define MC_CMD_GET_LINK_OUT_V2_LP_CAP_OFST 45776#define MC_CMD_GET_LINK_OUT_V2_LP_CAP_LEN 45777/* Autonegotiated speed in mbit/s. The link may still be down even if this5778 * reads non-zero.5779 */5780#define MC_CMD_GET_LINK_OUT_V2_LINK_SPEED_OFST 85781#define MC_CMD_GET_LINK_OUT_V2_LINK_SPEED_LEN 45782/* Current loopback setting. */5783#define MC_CMD_GET_LINK_OUT_V2_LOOPBACK_MODE_OFST 125784#define MC_CMD_GET_LINK_OUT_V2_LOOPBACK_MODE_LEN 45785/* Enum values, see field(s): */5786/* MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */5787#define MC_CMD_GET_LINK_OUT_V2_FLAGS_OFST 165788#define MC_CMD_GET_LINK_OUT_V2_FLAGS_LEN 45789#define MC_CMD_GET_LINK_OUT_V2_LINK_UP_OFST 165790#define MC_CMD_GET_LINK_OUT_V2_LINK_UP_LBN 05791#define MC_CMD_GET_LINK_OUT_V2_LINK_UP_WIDTH 15792#define MC_CMD_GET_LINK_OUT_V2_FULL_DUPLEX_OFST 165793#define MC_CMD_GET_LINK_OUT_V2_FULL_DUPLEX_LBN 15794#define MC_CMD_GET_LINK_OUT_V2_FULL_DUPLEX_WIDTH 15795#define MC_CMD_GET_LINK_OUT_V2_BPX_LINK_OFST 165796#define MC_CMD_GET_LINK_OUT_V2_BPX_LINK_LBN 25797#define MC_CMD_GET_LINK_OUT_V2_BPX_LINK_WIDTH 15798#define MC_CMD_GET_LINK_OUT_V2_PHY_LINK_OFST 165799#define MC_CMD_GET_LINK_OUT_V2_PHY_LINK_LBN 35800#define MC_CMD_GET_LINK_OUT_V2_PHY_LINK_WIDTH 15801#define MC_CMD_GET_LINK_OUT_V2_LINK_FAULT_RX_OFST 165802#define MC_CMD_GET_LINK_OUT_V2_LINK_FAULT_RX_LBN 65803#define MC_CMD_GET_LINK_OUT_V2_LINK_FAULT_RX_WIDTH 15804#define MC_CMD_GET_LINK_OUT_V2_LINK_FAULT_TX_OFST 165805#define MC_CMD_GET_LINK_OUT_V2_LINK_FAULT_TX_LBN 75806#define MC_CMD_GET_LINK_OUT_V2_LINK_FAULT_TX_WIDTH 15807#define MC_CMD_GET_LINK_OUT_V2_MODULE_UP_VALID_OFST 165808#define MC_CMD_GET_LINK_OUT_V2_MODULE_UP_VALID_LBN 85809#define MC_CMD_GET_LINK_OUT_V2_MODULE_UP_VALID_WIDTH 15810#define MC_CMD_GET_LINK_OUT_V2_MODULE_UP_OFST 165811#define MC_CMD_GET_LINK_OUT_V2_MODULE_UP_LBN 95812#define MC_CMD_GET_LINK_OUT_V2_MODULE_UP_WIDTH 15813/* This returns the negotiated flow control value. */5814#define MC_CMD_GET_LINK_OUT_V2_FCNTL_OFST 205815#define MC_CMD_GET_LINK_OUT_V2_FCNTL_LEN 45816/* Enum values, see field(s): */5817/* MC_CMD_SET_MAC/MC_CMD_SET_MAC_IN/FCNTL */5818#define MC_CMD_GET_LINK_OUT_V2_MAC_FAULT_OFST 245819#define MC_CMD_GET_LINK_OUT_V2_MAC_FAULT_LEN 45820/* MC_CMD_MAC_FAULT_XGMII_LOCAL_OFST 24 */5821/* MC_CMD_MAC_FAULT_XGMII_LOCAL_LBN 0 */5822/* MC_CMD_MAC_FAULT_XGMII_LOCAL_WIDTH 1 */5823/* MC_CMD_MAC_FAULT_XGMII_REMOTE_OFST 24 */5824/* MC_CMD_MAC_FAULT_XGMII_REMOTE_LBN 1 */5825/* MC_CMD_MAC_FAULT_XGMII_REMOTE_WIDTH 1 */5826/* MC_CMD_MAC_FAULT_SGMII_REMOTE_OFST 24 */5827/* MC_CMD_MAC_FAULT_SGMII_REMOTE_LBN 2 */5828/* MC_CMD_MAC_FAULT_SGMII_REMOTE_WIDTH 1 */5829/* MC_CMD_MAC_FAULT_PENDING_RECONFIG_OFST 24 */5830/* MC_CMD_MAC_FAULT_PENDING_RECONFIG_LBN 3 */5831/* MC_CMD_MAC_FAULT_PENDING_RECONFIG_WIDTH 1 */5832/* True local device capabilities (taking into account currently used PMD/MDI,5833 * e.g. plugged-in module). In general, subset of5834 * MC_CMD_GET_PHY_CFG_OUT/SUPPORTED_CAP, but may include extra _FEC_REQUEST5835 * bits, if the PMD requires FEC. 0 if unknown (e.g. module unplugged). Equal5836 * to SUPPORTED_CAP for non-pluggable PMDs. Refer to5837 * MC_CMD_GET_PHY_CFG_OUT/SUPPORTED_CAP for bit definitions.5838 */5839#define MC_CMD_GET_LINK_OUT_V2_LD_CAP_OFST 285840#define MC_CMD_GET_LINK_OUT_V2_LD_CAP_LEN 45841/* Auto-negotiation type used on the link */5842#define MC_CMD_GET_LINK_OUT_V2_AN_TYPE_OFST 325843#define MC_CMD_GET_LINK_OUT_V2_AN_TYPE_LEN 45844/* Enum values, see field(s): */5845/* AN_TYPE/TYPE */5846/* Forward error correction used on the link */5847#define MC_CMD_GET_LINK_OUT_V2_FEC_TYPE_OFST 365848#define MC_CMD_GET_LINK_OUT_V2_FEC_TYPE_LEN 45849/* Enum values, see field(s): */5850/* FEC_TYPE/TYPE */5851#define MC_CMD_GET_LINK_OUT_V2_EXT_FLAGS_OFST 405852#define MC_CMD_GET_LINK_OUT_V2_EXT_FLAGS_LEN 45853#define MC_CMD_GET_LINK_OUT_V2_PMD_MDI_CONNECTED_OFST 405854#define MC_CMD_GET_LINK_OUT_V2_PMD_MDI_CONNECTED_LBN 05855#define MC_CMD_GET_LINK_OUT_V2_PMD_MDI_CONNECTED_WIDTH 15856#define MC_CMD_GET_LINK_OUT_V2_PMD_READY_OFST 405857#define MC_CMD_GET_LINK_OUT_V2_PMD_READY_LBN 15858#define MC_CMD_GET_LINK_OUT_V2_PMD_READY_WIDTH 15859#define MC_CMD_GET_LINK_OUT_V2_PMD_LINK_UP_OFST 405860#define MC_CMD_GET_LINK_OUT_V2_PMD_LINK_UP_LBN 25861#define MC_CMD_GET_LINK_OUT_V2_PMD_LINK_UP_WIDTH 15862#define MC_CMD_GET_LINK_OUT_V2_PMA_LINK_UP_OFST 405863#define MC_CMD_GET_LINK_OUT_V2_PMA_LINK_UP_LBN 35864#define MC_CMD_GET_LINK_OUT_V2_PMA_LINK_UP_WIDTH 15865#define MC_CMD_GET_LINK_OUT_V2_PCS_LOCK_OFST 405866#define MC_CMD_GET_LINK_OUT_V2_PCS_LOCK_LBN 45867#define MC_CMD_GET_LINK_OUT_V2_PCS_LOCK_WIDTH 15868#define MC_CMD_GET_LINK_OUT_V2_ALIGN_LOCK_OFST 405869#define MC_CMD_GET_LINK_OUT_V2_ALIGN_LOCK_LBN 55870#define MC_CMD_GET_LINK_OUT_V2_ALIGN_LOCK_WIDTH 15871#define MC_CMD_GET_LINK_OUT_V2_HI_BER_OFST 405872#define MC_CMD_GET_LINK_OUT_V2_HI_BER_LBN 65873#define MC_CMD_GET_LINK_OUT_V2_HI_BER_WIDTH 15874#define MC_CMD_GET_LINK_OUT_V2_FEC_LOCK_OFST 405875#define MC_CMD_GET_LINK_OUT_V2_FEC_LOCK_LBN 75876#define MC_CMD_GET_LINK_OUT_V2_FEC_LOCK_WIDTH 15877#define MC_CMD_GET_LINK_OUT_V2_AN_DONE_OFST 405878#define MC_CMD_GET_LINK_OUT_V2_AN_DONE_LBN 85879#define MC_CMD_GET_LINK_OUT_V2_AN_DONE_WIDTH 15880#define MC_CMD_GET_LINK_OUT_V2_PORT_SHUTDOWN_OFST 405881#define MC_CMD_GET_LINK_OUT_V2_PORT_SHUTDOWN_LBN 95882#define MC_CMD_GET_LINK_OUT_V2_PORT_SHUTDOWN_WIDTH 15883 5884 5885/***********************************/5886/* MC_CMD_SET_LINK5887 * Write the unified MAC/PHY link configuration. Locks required: None. Return5888 * code: 0, EINVAL, ETIME, EAGAIN5889 */5890#define MC_CMD_SET_LINK 0x2a5891#undef MC_CMD_0x2a_PRIVILEGE_CTG5892 5893#define MC_CMD_0x2a_PRIVILEGE_CTG SRIOV_CTG_LINK5894 5895/* MC_CMD_SET_LINK_IN msgrequest */5896#define MC_CMD_SET_LINK_IN_LEN 165897/* Near-side advertised capabilities. Refer to5898 * MC_CMD_GET_PHY_CFG_OUT/SUPPORTED_CAP for bit definitions.5899 */5900#define MC_CMD_SET_LINK_IN_CAP_OFST 05901#define MC_CMD_SET_LINK_IN_CAP_LEN 45902/* Flags */5903#define MC_CMD_SET_LINK_IN_FLAGS_OFST 45904#define MC_CMD_SET_LINK_IN_FLAGS_LEN 45905#define MC_CMD_SET_LINK_IN_LOWPOWER_OFST 45906#define MC_CMD_SET_LINK_IN_LOWPOWER_LBN 05907#define MC_CMD_SET_LINK_IN_LOWPOWER_WIDTH 15908#define MC_CMD_SET_LINK_IN_POWEROFF_OFST 45909#define MC_CMD_SET_LINK_IN_POWEROFF_LBN 15910#define MC_CMD_SET_LINK_IN_POWEROFF_WIDTH 15911#define MC_CMD_SET_LINK_IN_TXDIS_OFST 45912#define MC_CMD_SET_LINK_IN_TXDIS_LBN 25913#define MC_CMD_SET_LINK_IN_TXDIS_WIDTH 15914#define MC_CMD_SET_LINK_IN_LINKDOWN_OFST 45915#define MC_CMD_SET_LINK_IN_LINKDOWN_LBN 35916#define MC_CMD_SET_LINK_IN_LINKDOWN_WIDTH 15917/* Loopback mode. */5918#define MC_CMD_SET_LINK_IN_LOOPBACK_MODE_OFST 85919#define MC_CMD_SET_LINK_IN_LOOPBACK_MODE_LEN 45920/* Enum values, see field(s): */5921/* MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */5922/* A loopback speed of "0" is supported, and means (choose any available5923 * speed).5924 */5925#define MC_CMD_SET_LINK_IN_LOOPBACK_SPEED_OFST 125926#define MC_CMD_SET_LINK_IN_LOOPBACK_SPEED_LEN 45927 5928/* MC_CMD_SET_LINK_IN_V2 msgrequest: Updated SET_LINK to include sequence5929 * number to ensure this SET_LINK command corresponds to the latest5930 * MODULECHANGE event.5931 */5932#define MC_CMD_SET_LINK_IN_V2_LEN 175933/* Near-side advertised capabilities. Refer to5934 * MC_CMD_GET_PHY_CFG_OUT/SUPPORTED_CAP for bit definitions.5935 */5936#define MC_CMD_SET_LINK_IN_V2_CAP_OFST 05937#define MC_CMD_SET_LINK_IN_V2_CAP_LEN 45938/* Flags */5939#define MC_CMD_SET_LINK_IN_V2_FLAGS_OFST 45940#define MC_CMD_SET_LINK_IN_V2_FLAGS_LEN 45941#define MC_CMD_SET_LINK_IN_V2_LOWPOWER_OFST 45942#define MC_CMD_SET_LINK_IN_V2_LOWPOWER_LBN 05943#define MC_CMD_SET_LINK_IN_V2_LOWPOWER_WIDTH 15944#define MC_CMD_SET_LINK_IN_V2_POWEROFF_OFST 45945#define MC_CMD_SET_LINK_IN_V2_POWEROFF_LBN 15946#define MC_CMD_SET_LINK_IN_V2_POWEROFF_WIDTH 15947#define MC_CMD_SET_LINK_IN_V2_TXDIS_OFST 45948#define MC_CMD_SET_LINK_IN_V2_TXDIS_LBN 25949#define MC_CMD_SET_LINK_IN_V2_TXDIS_WIDTH 15950#define MC_CMD_SET_LINK_IN_V2_LINKDOWN_OFST 45951#define MC_CMD_SET_LINK_IN_V2_LINKDOWN_LBN 35952#define MC_CMD_SET_LINK_IN_V2_LINKDOWN_WIDTH 15953/* Loopback mode. */5954#define MC_CMD_SET_LINK_IN_V2_LOOPBACK_MODE_OFST 85955#define MC_CMD_SET_LINK_IN_V2_LOOPBACK_MODE_LEN 45956/* Enum values, see field(s): */5957/* MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */5958/* A loopback speed of "0" is supported, and means (choose any available5959 * speed).5960 */5961#define MC_CMD_SET_LINK_IN_V2_LOOPBACK_SPEED_OFST 125962#define MC_CMD_SET_LINK_IN_V2_LOOPBACK_SPEED_LEN 45963#define MC_CMD_SET_LINK_IN_V2_MODULE_SEQ_OFST 165964#define MC_CMD_SET_LINK_IN_V2_MODULE_SEQ_LEN 15965#define MC_CMD_SET_LINK_IN_V2_MODULE_SEQ_NUMBER_OFST 165966#define MC_CMD_SET_LINK_IN_V2_MODULE_SEQ_NUMBER_LBN 05967#define MC_CMD_SET_LINK_IN_V2_MODULE_SEQ_NUMBER_WIDTH 75968#define MC_CMD_SET_LINK_IN_V2_MODULE_SEQ_IGNORE_OFST 165969#define MC_CMD_SET_LINK_IN_V2_MODULE_SEQ_IGNORE_LBN 75970#define MC_CMD_SET_LINK_IN_V2_MODULE_SEQ_IGNORE_WIDTH 15971 5972/* MC_CMD_SET_LINK_OUT msgresponse */5973#define MC_CMD_SET_LINK_OUT_LEN 05974 5975 5976/***********************************/5977/* MC_CMD_SET_ID_LED5978 * Set identification LED state. Locks required: None. Return code: 0, EINVAL5979 */5980#define MC_CMD_SET_ID_LED 0x2b5981#undef MC_CMD_0x2b_PRIVILEGE_CTG5982 5983#define MC_CMD_0x2b_PRIVILEGE_CTG SRIOV_CTG_LINK5984 5985/* MC_CMD_SET_ID_LED_IN msgrequest */5986#define MC_CMD_SET_ID_LED_IN_LEN 45987/* Set LED state. */5988#define MC_CMD_SET_ID_LED_IN_STATE_OFST 05989#define MC_CMD_SET_ID_LED_IN_STATE_LEN 45990#define MC_CMD_LED_OFF 0x0 /* enum */5991#define MC_CMD_LED_ON 0x1 /* enum */5992#define MC_CMD_LED_DEFAULT 0x2 /* enum */5993 5994/* MC_CMD_SET_ID_LED_OUT msgresponse */5995#define MC_CMD_SET_ID_LED_OUT_LEN 05996 5997 5998/***********************************/5999/* MC_CMD_SET_MAC6000 * Set MAC configuration. Locks required: None. Return code: 0, EINVAL6001 */6002#define MC_CMD_SET_MAC 0x2c6003#undef MC_CMD_0x2c_PRIVILEGE_CTG6004 6005#define MC_CMD_0x2c_PRIVILEGE_CTG SRIOV_CTG_GENERAL6006 6007/* MC_CMD_SET_MAC_IN msgrequest */6008#define MC_CMD_SET_MAC_IN_LEN 286009/* The MTU is the MTU programmed directly into the XMAC/GMAC (inclusive of6010 * EtherII, VLAN, bug16011 padding).6011 */6012#define MC_CMD_SET_MAC_IN_MTU_OFST 06013#define MC_CMD_SET_MAC_IN_MTU_LEN 46014#define MC_CMD_SET_MAC_IN_DRAIN_OFST 46015#define MC_CMD_SET_MAC_IN_DRAIN_LEN 46016#define MC_CMD_SET_MAC_IN_ADDR_OFST 86017#define MC_CMD_SET_MAC_IN_ADDR_LEN 86018#define MC_CMD_SET_MAC_IN_ADDR_LO_OFST 86019#define MC_CMD_SET_MAC_IN_ADDR_LO_LEN 46020#define MC_CMD_SET_MAC_IN_ADDR_LO_LBN 646021#define MC_CMD_SET_MAC_IN_ADDR_LO_WIDTH 326022#define MC_CMD_SET_MAC_IN_ADDR_HI_OFST 126023#define MC_CMD_SET_MAC_IN_ADDR_HI_LEN 46024#define MC_CMD_SET_MAC_IN_ADDR_HI_LBN 966025#define MC_CMD_SET_MAC_IN_ADDR_HI_WIDTH 326026#define MC_CMD_SET_MAC_IN_REJECT_OFST 166027#define MC_CMD_SET_MAC_IN_REJECT_LEN 46028#define MC_CMD_SET_MAC_IN_REJECT_UNCST_OFST 166029#define MC_CMD_SET_MAC_IN_REJECT_UNCST_LBN 06030#define MC_CMD_SET_MAC_IN_REJECT_UNCST_WIDTH 16031#define MC_CMD_SET_MAC_IN_REJECT_BRDCST_OFST 166032#define MC_CMD_SET_MAC_IN_REJECT_BRDCST_LBN 16033#define MC_CMD_SET_MAC_IN_REJECT_BRDCST_WIDTH 16034#define MC_CMD_SET_MAC_IN_FCNTL_OFST 206035#define MC_CMD_SET_MAC_IN_FCNTL_LEN 46036/* enum: Flow control is off. */6037#define MC_CMD_FCNTL_OFF 0x06038/* enum: Respond to flow control. */6039#define MC_CMD_FCNTL_RESPOND 0x16040/* enum: Respond to and Issue flow control. */6041#define MC_CMD_FCNTL_BIDIR 0x26042/* enum: Auto neg flow control. */6043#define MC_CMD_FCNTL_AUTO 0x36044/* enum: Priority flow control (eftest builds only). */6045#define MC_CMD_FCNTL_QBB 0x46046/* enum: Issue flow control. */6047#define MC_CMD_FCNTL_GENERATE 0x56048#define MC_CMD_SET_MAC_IN_FLAGS_OFST 246049#define MC_CMD_SET_MAC_IN_FLAGS_LEN 46050#define MC_CMD_SET_MAC_IN_FLAG_INCLUDE_FCS_OFST 246051#define MC_CMD_SET_MAC_IN_FLAG_INCLUDE_FCS_LBN 06052#define MC_CMD_SET_MAC_IN_FLAG_INCLUDE_FCS_WIDTH 16053 6054/* MC_CMD_SET_MAC_EXT_IN msgrequest */6055#define MC_CMD_SET_MAC_EXT_IN_LEN 326056/* The MTU is the MTU programmed directly into the XMAC/GMAC (inclusive of6057 * EtherII, VLAN, bug16011 padding).6058 */6059#define MC_CMD_SET_MAC_EXT_IN_MTU_OFST 06060#define MC_CMD_SET_MAC_EXT_IN_MTU_LEN 46061#define MC_CMD_SET_MAC_EXT_IN_DRAIN_OFST 46062#define MC_CMD_SET_MAC_EXT_IN_DRAIN_LEN 46063#define MC_CMD_SET_MAC_EXT_IN_ADDR_OFST 86064#define MC_CMD_SET_MAC_EXT_IN_ADDR_LEN 86065#define MC_CMD_SET_MAC_EXT_IN_ADDR_LO_OFST 86066#define MC_CMD_SET_MAC_EXT_IN_ADDR_LO_LEN 46067#define MC_CMD_SET_MAC_EXT_IN_ADDR_LO_LBN 646068#define MC_CMD_SET_MAC_EXT_IN_ADDR_LO_WIDTH 326069#define MC_CMD_SET_MAC_EXT_IN_ADDR_HI_OFST 126070#define MC_CMD_SET_MAC_EXT_IN_ADDR_HI_LEN 46071#define MC_CMD_SET_MAC_EXT_IN_ADDR_HI_LBN 966072#define MC_CMD_SET_MAC_EXT_IN_ADDR_HI_WIDTH 326073#define MC_CMD_SET_MAC_EXT_IN_REJECT_OFST 166074#define MC_CMD_SET_MAC_EXT_IN_REJECT_LEN 46075#define MC_CMD_SET_MAC_EXT_IN_REJECT_UNCST_OFST 166076#define MC_CMD_SET_MAC_EXT_IN_REJECT_UNCST_LBN 06077#define MC_CMD_SET_MAC_EXT_IN_REJECT_UNCST_WIDTH 16078#define MC_CMD_SET_MAC_EXT_IN_REJECT_BRDCST_OFST 166079#define MC_CMD_SET_MAC_EXT_IN_REJECT_BRDCST_LBN 16080#define MC_CMD_SET_MAC_EXT_IN_REJECT_BRDCST_WIDTH 16081#define MC_CMD_SET_MAC_EXT_IN_FCNTL_OFST 206082#define MC_CMD_SET_MAC_EXT_IN_FCNTL_LEN 46083/* enum: Flow control is off. */6084/* MC_CMD_FCNTL_OFF 0x0 */6085/* enum: Respond to flow control. */6086/* MC_CMD_FCNTL_RESPOND 0x1 */6087/* enum: Respond to and Issue flow control. */6088/* MC_CMD_FCNTL_BIDIR 0x2 */6089/* enum: Auto neg flow control. */6090/* MC_CMD_FCNTL_AUTO 0x3 */6091/* enum: Priority flow control (eftest builds only). */6092/* MC_CMD_FCNTL_QBB 0x4 */6093/* enum: Issue flow control. */6094/* MC_CMD_FCNTL_GENERATE 0x5 */6095#define MC_CMD_SET_MAC_EXT_IN_FLAGS_OFST 246096#define MC_CMD_SET_MAC_EXT_IN_FLAGS_LEN 46097#define MC_CMD_SET_MAC_EXT_IN_FLAG_INCLUDE_FCS_OFST 246098#define MC_CMD_SET_MAC_EXT_IN_FLAG_INCLUDE_FCS_LBN 06099#define MC_CMD_SET_MAC_EXT_IN_FLAG_INCLUDE_FCS_WIDTH 16100/* Select which parameters to configure. A parameter will only be modified if6101 * the corresponding control flag is set. If SET_MAC_ENHANCED is not set in6102 * capabilities then this field is ignored (and all flags are assumed to be6103 * set).6104 */6105#define MC_CMD_SET_MAC_EXT_IN_CONTROL_OFST 286106#define MC_CMD_SET_MAC_EXT_IN_CONTROL_LEN 46107#define MC_CMD_SET_MAC_EXT_IN_CFG_MTU_OFST 286108#define MC_CMD_SET_MAC_EXT_IN_CFG_MTU_LBN 06109#define MC_CMD_SET_MAC_EXT_IN_CFG_MTU_WIDTH 16110#define MC_CMD_SET_MAC_EXT_IN_CFG_DRAIN_OFST 286111#define MC_CMD_SET_MAC_EXT_IN_CFG_DRAIN_LBN 16112#define MC_CMD_SET_MAC_EXT_IN_CFG_DRAIN_WIDTH 16113#define MC_CMD_SET_MAC_EXT_IN_CFG_REJECT_OFST 286114#define MC_CMD_SET_MAC_EXT_IN_CFG_REJECT_LBN 26115#define MC_CMD_SET_MAC_EXT_IN_CFG_REJECT_WIDTH 16116#define MC_CMD_SET_MAC_EXT_IN_CFG_FCNTL_OFST 286117#define MC_CMD_SET_MAC_EXT_IN_CFG_FCNTL_LBN 36118#define MC_CMD_SET_MAC_EXT_IN_CFG_FCNTL_WIDTH 16119#define MC_CMD_SET_MAC_EXT_IN_CFG_FCS_OFST 286120#define MC_CMD_SET_MAC_EXT_IN_CFG_FCS_LBN 46121#define MC_CMD_SET_MAC_EXT_IN_CFG_FCS_WIDTH 16122 6123/* MC_CMD_SET_MAC_V3_IN msgrequest */6124#define MC_CMD_SET_MAC_V3_IN_LEN 406125/* The MTU is the MTU programmed directly into the XMAC/GMAC (inclusive of6126 * EtherII, VLAN, bug16011 padding).6127 */6128#define MC_CMD_SET_MAC_V3_IN_MTU_OFST 06129#define MC_CMD_SET_MAC_V3_IN_MTU_LEN 46130#define MC_CMD_SET_MAC_V3_IN_DRAIN_OFST 46131#define MC_CMD_SET_MAC_V3_IN_DRAIN_LEN 46132#define MC_CMD_SET_MAC_V3_IN_ADDR_OFST 86133#define MC_CMD_SET_MAC_V3_IN_ADDR_LEN 86134#define MC_CMD_SET_MAC_V3_IN_ADDR_LO_OFST 86135#define MC_CMD_SET_MAC_V3_IN_ADDR_LO_LEN 46136#define MC_CMD_SET_MAC_V3_IN_ADDR_LO_LBN 646137#define MC_CMD_SET_MAC_V3_IN_ADDR_LO_WIDTH 326138#define MC_CMD_SET_MAC_V3_IN_ADDR_HI_OFST 126139#define MC_CMD_SET_MAC_V3_IN_ADDR_HI_LEN 46140#define MC_CMD_SET_MAC_V3_IN_ADDR_HI_LBN 966141#define MC_CMD_SET_MAC_V3_IN_ADDR_HI_WIDTH 326142#define MC_CMD_SET_MAC_V3_IN_REJECT_OFST 166143#define MC_CMD_SET_MAC_V3_IN_REJECT_LEN 46144#define MC_CMD_SET_MAC_V3_IN_REJECT_UNCST_OFST 166145#define MC_CMD_SET_MAC_V3_IN_REJECT_UNCST_LBN 06146#define MC_CMD_SET_MAC_V3_IN_REJECT_UNCST_WIDTH 16147#define MC_CMD_SET_MAC_V3_IN_REJECT_BRDCST_OFST 166148#define MC_CMD_SET_MAC_V3_IN_REJECT_BRDCST_LBN 16149#define MC_CMD_SET_MAC_V3_IN_REJECT_BRDCST_WIDTH 16150#define MC_CMD_SET_MAC_V3_IN_FCNTL_OFST 206151#define MC_CMD_SET_MAC_V3_IN_FCNTL_LEN 46152/* enum: Flow control is off. */6153/* MC_CMD_FCNTL_OFF 0x0 */6154/* enum: Respond to flow control. */6155/* MC_CMD_FCNTL_RESPOND 0x1 */6156/* enum: Respond to and Issue flow control. */6157/* MC_CMD_FCNTL_BIDIR 0x2 */6158/* enum: Auto neg flow control. */6159/* MC_CMD_FCNTL_AUTO 0x3 */6160/* enum: Priority flow control (eftest builds only). */6161/* MC_CMD_FCNTL_QBB 0x4 */6162/* enum: Issue flow control. */6163/* MC_CMD_FCNTL_GENERATE 0x5 */6164#define MC_CMD_SET_MAC_V3_IN_FLAGS_OFST 246165#define MC_CMD_SET_MAC_V3_IN_FLAGS_LEN 46166#define MC_CMD_SET_MAC_V3_IN_FLAG_INCLUDE_FCS_OFST 246167#define MC_CMD_SET_MAC_V3_IN_FLAG_INCLUDE_FCS_LBN 06168#define MC_CMD_SET_MAC_V3_IN_FLAG_INCLUDE_FCS_WIDTH 16169/* Select which parameters to configure. A parameter will only be modified if6170 * the corresponding control flag is set. If SET_MAC_ENHANCED is not set in6171 * capabilities then this field is ignored (and all flags are assumed to be6172 * set).6173 */6174#define MC_CMD_SET_MAC_V3_IN_CONTROL_OFST 286175#define MC_CMD_SET_MAC_V3_IN_CONTROL_LEN 46176#define MC_CMD_SET_MAC_V3_IN_CFG_MTU_OFST 286177#define MC_CMD_SET_MAC_V3_IN_CFG_MTU_LBN 06178#define MC_CMD_SET_MAC_V3_IN_CFG_MTU_WIDTH 16179#define MC_CMD_SET_MAC_V3_IN_CFG_DRAIN_OFST 286180#define MC_CMD_SET_MAC_V3_IN_CFG_DRAIN_LBN 16181#define MC_CMD_SET_MAC_V3_IN_CFG_DRAIN_WIDTH 16182#define MC_CMD_SET_MAC_V3_IN_CFG_REJECT_OFST 286183#define MC_CMD_SET_MAC_V3_IN_CFG_REJECT_LBN 26184#define MC_CMD_SET_MAC_V3_IN_CFG_REJECT_WIDTH 16185#define MC_CMD_SET_MAC_V3_IN_CFG_FCNTL_OFST 286186#define MC_CMD_SET_MAC_V3_IN_CFG_FCNTL_LBN 36187#define MC_CMD_SET_MAC_V3_IN_CFG_FCNTL_WIDTH 16188#define MC_CMD_SET_MAC_V3_IN_CFG_FCS_OFST 286189#define MC_CMD_SET_MAC_V3_IN_CFG_FCS_LBN 46190#define MC_CMD_SET_MAC_V3_IN_CFG_FCS_WIDTH 16191/* Identifies the MAC to update by the specifying the end of a logical MAE6192 * link. Setting TARGET to MAE_LINK_ENDPOINT_COMPAT is equivalent to using the6193 * previous version of the command (MC_CMD_SET_MAC_EXT). Not all possible6194 * combinations of MPORT_END and MPORT_SELECTOR in TARGET will work in all6195 * circumstances. 1. Some will always work (e.g. a VF can always address its6196 * logical MAC using MPORT_SELECTOR=ASSIGNED,LINK_END=VNIC), 2. Some are not6197 * meaningful and will always fail with EINVAL (e.g. attempting to address the6198 * VNIC end of a link to a physical port), 3. Some are meaningful but require6199 * the MCDI client to have the required permission and fail with EPERM6200 * otherwise (e.g. trying to set the MAC on a VF the caller cannot administer),6201 * and 4. Some could be implementation-specific and fail with ENOTSUP if not6202 * available (no examples exist right now). See SF-123581-TC section 4.3 for6203 * more details.6204 */6205#define MC_CMD_SET_MAC_V3_IN_TARGET_OFST 326206#define MC_CMD_SET_MAC_V3_IN_TARGET_LEN 86207#define MC_CMD_SET_MAC_V3_IN_TARGET_LO_OFST 326208#define MC_CMD_SET_MAC_V3_IN_TARGET_LO_LEN 46209#define MC_CMD_SET_MAC_V3_IN_TARGET_LO_LBN 2566210#define MC_CMD_SET_MAC_V3_IN_TARGET_LO_WIDTH 326211#define MC_CMD_SET_MAC_V3_IN_TARGET_HI_OFST 366212#define MC_CMD_SET_MAC_V3_IN_TARGET_HI_LEN 46213#define MC_CMD_SET_MAC_V3_IN_TARGET_HI_LBN 2886214#define MC_CMD_SET_MAC_V3_IN_TARGET_HI_WIDTH 326215#define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_OFST 326216#define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_LEN 46217#define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_FLAT_OFST 326218#define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_FLAT_LEN 46219#define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_TYPE_OFST 356220#define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_TYPE_LEN 16221#define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_MPORT_ID_OFST 326222#define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_MPORT_ID_LEN 36223#define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_PPORT_ID_LBN 2566224#define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_PPORT_ID_WIDTH 46225#define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_FUNC_INTF_ID_LBN 2766226#define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_FUNC_INTF_ID_WIDTH 46227#define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_FUNC_MH_PF_ID_LBN 2726228#define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_FUNC_MH_PF_ID_WIDTH 46229#define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_FUNC_PF_ID_OFST 346230#define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_FUNC_PF_ID_LEN 16231#define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_FUNC_VF_ID_OFST 326232#define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_FUNC_VF_ID_LEN 26233#define MC_CMD_SET_MAC_V3_IN_TARGET_LINK_END_OFST 366234#define MC_CMD_SET_MAC_V3_IN_TARGET_LINK_END_LEN 46235#define MC_CMD_SET_MAC_V3_IN_TARGET_FLAT_OFST 326236#define MC_CMD_SET_MAC_V3_IN_TARGET_FLAT_LEN 86237#define MC_CMD_SET_MAC_V3_IN_TARGET_FLAT_LO_OFST 326238#define MC_CMD_SET_MAC_V3_IN_TARGET_FLAT_LO_LEN 46239#define MC_CMD_SET_MAC_V3_IN_TARGET_FLAT_LO_LBN 2566240#define MC_CMD_SET_MAC_V3_IN_TARGET_FLAT_LO_WIDTH 326241#define MC_CMD_SET_MAC_V3_IN_TARGET_FLAT_HI_OFST 366242#define MC_CMD_SET_MAC_V3_IN_TARGET_FLAT_HI_LEN 46243#define MC_CMD_SET_MAC_V3_IN_TARGET_FLAT_HI_LBN 2886244#define MC_CMD_SET_MAC_V3_IN_TARGET_FLAT_HI_WIDTH 326245 6246/* MC_CMD_SET_MAC_OUT msgresponse */6247#define MC_CMD_SET_MAC_OUT_LEN 06248 6249/* MC_CMD_SET_MAC_V2_OUT msgresponse */6250#define MC_CMD_SET_MAC_V2_OUT_LEN 46251/* MTU as configured after processing the request. See comment at6252 * MC_CMD_SET_MAC_IN/MTU. To query MTU without doing any changes, set CONTROL6253 * to 0.6254 */6255#define MC_CMD_SET_MAC_V2_OUT_MTU_OFST 06256#define MC_CMD_SET_MAC_V2_OUT_MTU_LEN 46257 6258 6259/***********************************/6260/* MC_CMD_PHY_STATS6261 * Get generic PHY statistics. This call returns the statistics for a generic6262 * PHY in a sparse array (indexed by the enumerate). Each value is represented6263 * by a 32bit number. If the DMA_ADDR is 0, then no DMA is performed, and the6264 * statistics may be read from the message response. If DMA_ADDR != 0, then the6265 * statistics are dmad to that (page-aligned location). Locks required: None.6266 * Returns: 0, ETIME6267 */6268#define MC_CMD_PHY_STATS 0x2d6269#undef MC_CMD_0x2d_PRIVILEGE_CTG6270 6271#define MC_CMD_0x2d_PRIVILEGE_CTG SRIOV_CTG_LINK6272 6273/* MC_CMD_PHY_STATS_IN msgrequest */6274#define MC_CMD_PHY_STATS_IN_LEN 86275/* ??? */6276#define MC_CMD_PHY_STATS_IN_DMA_ADDR_OFST 06277#define MC_CMD_PHY_STATS_IN_DMA_ADDR_LEN 86278#define MC_CMD_PHY_STATS_IN_DMA_ADDR_LO_OFST 06279#define MC_CMD_PHY_STATS_IN_DMA_ADDR_LO_LEN 46280#define MC_CMD_PHY_STATS_IN_DMA_ADDR_LO_LBN 06281#define MC_CMD_PHY_STATS_IN_DMA_ADDR_LO_WIDTH 326282#define MC_CMD_PHY_STATS_IN_DMA_ADDR_HI_OFST 46283#define MC_CMD_PHY_STATS_IN_DMA_ADDR_HI_LEN 46284#define MC_CMD_PHY_STATS_IN_DMA_ADDR_HI_LBN 326285#define MC_CMD_PHY_STATS_IN_DMA_ADDR_HI_WIDTH 326286 6287/* MC_CMD_PHY_STATS_OUT_DMA msgresponse */6288#define MC_CMD_PHY_STATS_OUT_DMA_LEN 06289 6290/* MC_CMD_PHY_STATS_OUT_NO_DMA msgresponse */6291#define MC_CMD_PHY_STATS_OUT_NO_DMA_LEN (((MC_CMD_PHY_NSTATS*32))>>3)6292#define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_OFST 06293#define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_LEN 46294#define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_NUM MC_CMD_PHY_NSTATS6295/* enum: OUI. */6296#define MC_CMD_OUI 0x06297/* enum: PMA-PMD Link Up. */6298#define MC_CMD_PMA_PMD_LINK_UP 0x16299/* enum: PMA-PMD RX Fault. */6300#define MC_CMD_PMA_PMD_RX_FAULT 0x26301/* enum: PMA-PMD TX Fault. */6302#define MC_CMD_PMA_PMD_TX_FAULT 0x36303/* enum: PMA-PMD Signal */6304#define MC_CMD_PMA_PMD_SIGNAL 0x46305/* enum: PMA-PMD SNR A. */6306#define MC_CMD_PMA_PMD_SNR_A 0x56307/* enum: PMA-PMD SNR B. */6308#define MC_CMD_PMA_PMD_SNR_B 0x66309/* enum: PMA-PMD SNR C. */6310#define MC_CMD_PMA_PMD_SNR_C 0x76311/* enum: PMA-PMD SNR D. */6312#define MC_CMD_PMA_PMD_SNR_D 0x86313/* enum: PCS Link Up. */6314#define MC_CMD_PCS_LINK_UP 0x96315/* enum: PCS RX Fault. */6316#define MC_CMD_PCS_RX_FAULT 0xa6317/* enum: PCS TX Fault. */6318#define MC_CMD_PCS_TX_FAULT 0xb6319/* enum: PCS BER. */6320#define MC_CMD_PCS_BER 0xc6321/* enum: PCS Block Errors. */6322#define MC_CMD_PCS_BLOCK_ERRORS 0xd6323/* enum: PhyXS Link Up. */6324#define MC_CMD_PHYXS_LINK_UP 0xe6325/* enum: PhyXS RX Fault. */6326#define MC_CMD_PHYXS_RX_FAULT 0xf6327/* enum: PhyXS TX Fault. */6328#define MC_CMD_PHYXS_TX_FAULT 0x106329/* enum: PhyXS Align. */6330#define MC_CMD_PHYXS_ALIGN 0x116331/* enum: PhyXS Sync. */6332#define MC_CMD_PHYXS_SYNC 0x126333/* enum: AN link-up. */6334#define MC_CMD_AN_LINK_UP 0x136335/* enum: AN Complete. */6336#define MC_CMD_AN_COMPLETE 0x146337/* enum: AN 10GBaseT Status. */6338#define MC_CMD_AN_10GBT_STATUS 0x156339/* enum: Clause 22 Link-Up. */6340#define MC_CMD_CL22_LINK_UP 0x166341/* enum: (Last entry) */6342#define MC_CMD_PHY_NSTATS 0x176343 6344 6345/***********************************/6346/* MC_CMD_MAC_STATS6347 * Get generic MAC statistics. This call returns unified statistics maintained6348 * by the MC as it switches between the GMAC and XMAC. The MC will write out6349 * all supported stats. The driver should zero initialise the buffer to6350 * guarantee consistent results. If the DMA_ADDR is 0, then no DMA is6351 * performed, and the statistics may be read from the message response. If6352 * DMA_ADDR != 0, then the statistics are dmad to that (page-aligned location).6353 * Locks required: None. The PERIODIC_CLEAR option is not used and now has no6354 * effect. Returns: 0, ETIME6355 */6356#define MC_CMD_MAC_STATS 0x2e6357#undef MC_CMD_0x2e_PRIVILEGE_CTG6358 6359#define MC_CMD_0x2e_PRIVILEGE_CTG SRIOV_CTG_GENERAL6360 6361/* MC_CMD_MAC_STATS_IN msgrequest */6362#define MC_CMD_MAC_STATS_IN_LEN 206363/* ??? */6364#define MC_CMD_MAC_STATS_IN_DMA_ADDR_OFST 06365#define MC_CMD_MAC_STATS_IN_DMA_ADDR_LEN 86366#define MC_CMD_MAC_STATS_IN_DMA_ADDR_LO_OFST 06367#define MC_CMD_MAC_STATS_IN_DMA_ADDR_LO_LEN 46368#define MC_CMD_MAC_STATS_IN_DMA_ADDR_LO_LBN 06369#define MC_CMD_MAC_STATS_IN_DMA_ADDR_LO_WIDTH 326370#define MC_CMD_MAC_STATS_IN_DMA_ADDR_HI_OFST 46371#define MC_CMD_MAC_STATS_IN_DMA_ADDR_HI_LEN 46372#define MC_CMD_MAC_STATS_IN_DMA_ADDR_HI_LBN 326373#define MC_CMD_MAC_STATS_IN_DMA_ADDR_HI_WIDTH 326374#define MC_CMD_MAC_STATS_IN_CMD_OFST 86375#define MC_CMD_MAC_STATS_IN_CMD_LEN 46376#define MC_CMD_MAC_STATS_IN_DMA_OFST 86377#define MC_CMD_MAC_STATS_IN_DMA_LBN 06378#define MC_CMD_MAC_STATS_IN_DMA_WIDTH 16379#define MC_CMD_MAC_STATS_IN_CLEAR_OFST 86380#define MC_CMD_MAC_STATS_IN_CLEAR_LBN 16381#define MC_CMD_MAC_STATS_IN_CLEAR_WIDTH 16382#define MC_CMD_MAC_STATS_IN_PERIODIC_CHANGE_OFST 86383#define MC_CMD_MAC_STATS_IN_PERIODIC_CHANGE_LBN 26384#define MC_CMD_MAC_STATS_IN_PERIODIC_CHANGE_WIDTH 16385#define MC_CMD_MAC_STATS_IN_PERIODIC_ENABLE_OFST 86386#define MC_CMD_MAC_STATS_IN_PERIODIC_ENABLE_LBN 36387#define MC_CMD_MAC_STATS_IN_PERIODIC_ENABLE_WIDTH 16388#define MC_CMD_MAC_STATS_IN_PERIODIC_CLEAR_OFST 86389#define MC_CMD_MAC_STATS_IN_PERIODIC_CLEAR_LBN 46390#define MC_CMD_MAC_STATS_IN_PERIODIC_CLEAR_WIDTH 16391#define MC_CMD_MAC_STATS_IN_PERIODIC_NOEVENT_OFST 86392#define MC_CMD_MAC_STATS_IN_PERIODIC_NOEVENT_LBN 56393#define MC_CMD_MAC_STATS_IN_PERIODIC_NOEVENT_WIDTH 16394#define MC_CMD_MAC_STATS_IN_PERIOD_MS_OFST 86395#define MC_CMD_MAC_STATS_IN_PERIOD_MS_LBN 166396#define MC_CMD_MAC_STATS_IN_PERIOD_MS_WIDTH 166397/* DMA length. Should be set to MAC_STATS_NUM_STATS * sizeof(uint64_t), as6398 * returned by MC_CMD_GET_CAPABILITIES_V4_OUT. For legacy firmware not6399 * supporting MC_CMD_GET_CAPABILITIES_V4_OUT, DMA_LEN should be set to6400 * MC_CMD_MAC_NSTATS * sizeof(uint64_t)6401 */6402#define MC_CMD_MAC_STATS_IN_DMA_LEN_OFST 126403#define MC_CMD_MAC_STATS_IN_DMA_LEN_LEN 46404/* port id so vadapter stats can be provided */6405#define MC_CMD_MAC_STATS_IN_PORT_ID_OFST 166406#define MC_CMD_MAC_STATS_IN_PORT_ID_LEN 46407 6408/* MC_CMD_MAC_STATS_OUT_DMA msgresponse */6409#define MC_CMD_MAC_STATS_OUT_DMA_LEN 06410 6411/* MC_CMD_MAC_STATS_OUT_NO_DMA msgresponse */6412#define MC_CMD_MAC_STATS_OUT_NO_DMA_LEN (((MC_CMD_MAC_NSTATS*64))>>3)6413#define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_OFST 06414#define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LEN 86415#define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LO_OFST 06416#define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LO_LEN 46417#define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LO_LBN 06418#define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LO_WIDTH 326419#define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_HI_OFST 46420#define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_HI_LEN 46421#define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_HI_LBN 326422#define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_HI_WIDTH 326423#define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS6424#define MC_CMD_MAC_GENERATION_START 0x0 /* enum */6425#define MC_CMD_MAC_DMABUF_START 0x1 /* enum */6426#define MC_CMD_MAC_TX_PKTS 0x1 /* enum */6427#define MC_CMD_MAC_TX_PAUSE_PKTS 0x2 /* enum */6428#define MC_CMD_MAC_TX_CONTROL_PKTS 0x3 /* enum */6429#define MC_CMD_MAC_TX_UNICAST_PKTS 0x4 /* enum */6430#define MC_CMD_MAC_TX_MULTICAST_PKTS 0x5 /* enum */6431#define MC_CMD_MAC_TX_BROADCAST_PKTS 0x6 /* enum */6432#define MC_CMD_MAC_TX_BYTES 0x7 /* enum */6433#define MC_CMD_MAC_TX_BAD_BYTES 0x8 /* enum */6434#define MC_CMD_MAC_TX_LT64_PKTS 0x9 /* enum */6435#define MC_CMD_MAC_TX_64_PKTS 0xa /* enum */6436#define MC_CMD_MAC_TX_65_TO_127_PKTS 0xb /* enum */6437#define MC_CMD_MAC_TX_128_TO_255_PKTS 0xc /* enum */6438#define MC_CMD_MAC_TX_256_TO_511_PKTS 0xd /* enum */6439#define MC_CMD_MAC_TX_512_TO_1023_PKTS 0xe /* enum */6440#define MC_CMD_MAC_TX_1024_TO_15XX_PKTS 0xf /* enum */6441#define MC_CMD_MAC_TX_15XX_TO_JUMBO_PKTS 0x10 /* enum */6442#define MC_CMD_MAC_TX_GTJUMBO_PKTS 0x11 /* enum */6443#define MC_CMD_MAC_TX_BAD_FCS_PKTS 0x12 /* enum */6444#define MC_CMD_MAC_TX_SINGLE_COLLISION_PKTS 0x13 /* enum */6445#define MC_CMD_MAC_TX_MULTIPLE_COLLISION_PKTS 0x14 /* enum */6446#define MC_CMD_MAC_TX_EXCESSIVE_COLLISION_PKTS 0x15 /* enum */6447#define MC_CMD_MAC_TX_LATE_COLLISION_PKTS 0x16 /* enum */6448#define MC_CMD_MAC_TX_DEFERRED_PKTS 0x17 /* enum */6449#define MC_CMD_MAC_TX_EXCESSIVE_DEFERRED_PKTS 0x18 /* enum */6450#define MC_CMD_MAC_TX_NON_TCPUDP_PKTS 0x19 /* enum */6451#define MC_CMD_MAC_TX_MAC_SRC_ERR_PKTS 0x1a /* enum */6452#define MC_CMD_MAC_TX_IP_SRC_ERR_PKTS 0x1b /* enum */6453#define MC_CMD_MAC_RX_PKTS 0x1c /* enum */6454#define MC_CMD_MAC_RX_PAUSE_PKTS 0x1d /* enum */6455#define MC_CMD_MAC_RX_GOOD_PKTS 0x1e /* enum */6456#define MC_CMD_MAC_RX_CONTROL_PKTS 0x1f /* enum */6457#define MC_CMD_MAC_RX_UNICAST_PKTS 0x20 /* enum */6458#define MC_CMD_MAC_RX_MULTICAST_PKTS 0x21 /* enum */6459#define MC_CMD_MAC_RX_BROADCAST_PKTS 0x22 /* enum */6460#define MC_CMD_MAC_RX_BYTES 0x23 /* enum */6461#define MC_CMD_MAC_RX_BAD_BYTES 0x24 /* enum */6462#define MC_CMD_MAC_RX_64_PKTS 0x25 /* enum */6463#define MC_CMD_MAC_RX_65_TO_127_PKTS 0x26 /* enum */6464#define MC_CMD_MAC_RX_128_TO_255_PKTS 0x27 /* enum */6465#define MC_CMD_MAC_RX_256_TO_511_PKTS 0x28 /* enum */6466#define MC_CMD_MAC_RX_512_TO_1023_PKTS 0x29 /* enum */6467#define MC_CMD_MAC_RX_1024_TO_15XX_PKTS 0x2a /* enum */6468#define MC_CMD_MAC_RX_15XX_TO_JUMBO_PKTS 0x2b /* enum */6469#define MC_CMD_MAC_RX_GTJUMBO_PKTS 0x2c /* enum */6470#define MC_CMD_MAC_RX_UNDERSIZE_PKTS 0x2d /* enum */6471#define MC_CMD_MAC_RX_BAD_FCS_PKTS 0x2e /* enum */6472#define MC_CMD_MAC_RX_OVERFLOW_PKTS 0x2f /* enum */6473#define MC_CMD_MAC_RX_FALSE_CARRIER_PKTS 0x30 /* enum */6474#define MC_CMD_MAC_RX_SYMBOL_ERROR_PKTS 0x31 /* enum */6475#define MC_CMD_MAC_RX_ALIGN_ERROR_PKTS 0x32 /* enum */6476#define MC_CMD_MAC_RX_LENGTH_ERROR_PKTS 0x33 /* enum */6477#define MC_CMD_MAC_RX_INTERNAL_ERROR_PKTS 0x34 /* enum */6478#define MC_CMD_MAC_RX_JABBER_PKTS 0x35 /* enum */6479#define MC_CMD_MAC_RX_NODESC_DROPS 0x36 /* enum */6480#define MC_CMD_MAC_RX_LANES01_CHAR_ERR 0x37 /* enum */6481#define MC_CMD_MAC_RX_LANES23_CHAR_ERR 0x38 /* enum */6482#define MC_CMD_MAC_RX_LANES01_DISP_ERR 0x39 /* enum */6483#define MC_CMD_MAC_RX_LANES23_DISP_ERR 0x3a /* enum */6484#define MC_CMD_MAC_RX_MATCH_FAULT 0x3b /* enum */6485/* enum: PM trunc_bb_overflow counter. Valid for EF10 with PM_AND_RXDP_COUNTERS6486 * capability only.6487 */6488#define MC_CMD_MAC_PM_TRUNC_BB_OVERFLOW 0x3c6489/* enum: PM discard_bb_overflow counter. Valid for EF10 with6490 * PM_AND_RXDP_COUNTERS capability only.6491 */6492#define MC_CMD_MAC_PM_DISCARD_BB_OVERFLOW 0x3d6493/* enum: PM trunc_vfifo_full counter. Valid for EF10 with PM_AND_RXDP_COUNTERS6494 * capability only.6495 */6496#define MC_CMD_MAC_PM_TRUNC_VFIFO_FULL 0x3e6497/* enum: PM discard_vfifo_full counter. Valid for EF10 with6498 * PM_AND_RXDP_COUNTERS capability only.6499 */6500#define MC_CMD_MAC_PM_DISCARD_VFIFO_FULL 0x3f6501/* enum: PM trunc_qbb counter. Valid for EF10 with PM_AND_RXDP_COUNTERS6502 * capability only.6503 */6504#define MC_CMD_MAC_PM_TRUNC_QBB 0x406505/* enum: PM discard_qbb counter. Valid for EF10 with PM_AND_RXDP_COUNTERS6506 * capability only.6507 */6508#define MC_CMD_MAC_PM_DISCARD_QBB 0x416509/* enum: PM discard_mapping counter. Valid for EF10 with PM_AND_RXDP_COUNTERS6510 * capability only.6511 */6512#define MC_CMD_MAC_PM_DISCARD_MAPPING 0x426513/* enum: RXDP counter: Number of packets dropped due to the queue being6514 * disabled. Valid for EF10 with PM_AND_RXDP_COUNTERS capability only.6515 */6516#define MC_CMD_MAC_RXDP_Q_DISABLED_PKTS 0x436517/* enum: RXDP counter: Number of packets dropped by the DICPU. Valid for EF106518 * with PM_AND_RXDP_COUNTERS capability only.6519 */6520#define MC_CMD_MAC_RXDP_DI_DROPPED_PKTS 0x456521/* enum: RXDP counter: Number of non-host packets. Valid for EF10 with6522 * PM_AND_RXDP_COUNTERS capability only.6523 */6524#define MC_CMD_MAC_RXDP_STREAMING_PKTS 0x466525/* enum: RXDP counter: Number of times an hlb descriptor fetch was performed.6526 * Valid for EF10 with PM_AND_RXDP_COUNTERS capability only.6527 */6528#define MC_CMD_MAC_RXDP_HLB_FETCH_CONDITIONS 0x476529/* enum: RXDP counter: Number of times the DPCPU waited for an existing6530 * descriptor fetch. Valid for EF10 with PM_AND_RXDP_COUNTERS capability only.6531 */6532#define MC_CMD_MAC_RXDP_HLB_WAIT_CONDITIONS 0x486533#define MC_CMD_MAC_VADAPTER_RX_DMABUF_START 0x4c /* enum */6534#define MC_CMD_MAC_VADAPTER_RX_UNICAST_PACKETS 0x4c /* enum */6535#define MC_CMD_MAC_VADAPTER_RX_UNICAST_BYTES 0x4d /* enum */6536#define MC_CMD_MAC_VADAPTER_RX_MULTICAST_PACKETS 0x4e /* enum */6537#define MC_CMD_MAC_VADAPTER_RX_MULTICAST_BYTES 0x4f /* enum */6538#define MC_CMD_MAC_VADAPTER_RX_BROADCAST_PACKETS 0x50 /* enum */6539#define MC_CMD_MAC_VADAPTER_RX_BROADCAST_BYTES 0x51 /* enum */6540#define MC_CMD_MAC_VADAPTER_RX_BAD_PACKETS 0x52 /* enum */6541#define MC_CMD_MAC_VADAPTER_RX_BAD_BYTES 0x53 /* enum */6542#define MC_CMD_MAC_VADAPTER_RX_OVERFLOW 0x54 /* enum */6543#define MC_CMD_MAC_VADAPTER_TX_DMABUF_START 0x57 /* enum */6544#define MC_CMD_MAC_VADAPTER_TX_UNICAST_PACKETS 0x57 /* enum */6545#define MC_CMD_MAC_VADAPTER_TX_UNICAST_BYTES 0x58 /* enum */6546#define MC_CMD_MAC_VADAPTER_TX_MULTICAST_PACKETS 0x59 /* enum */6547#define MC_CMD_MAC_VADAPTER_TX_MULTICAST_BYTES 0x5a /* enum */6548#define MC_CMD_MAC_VADAPTER_TX_BROADCAST_PACKETS 0x5b /* enum */6549#define MC_CMD_MAC_VADAPTER_TX_BROADCAST_BYTES 0x5c /* enum */6550#define MC_CMD_MAC_VADAPTER_TX_BAD_PACKETS 0x5d /* enum */6551#define MC_CMD_MAC_VADAPTER_TX_BAD_BYTES 0x5e /* enum */6552#define MC_CMD_MAC_VADAPTER_TX_OVERFLOW 0x5f /* enum */6553/* enum: Start of GMAC stats buffer space, for Siena only. */6554#define MC_CMD_GMAC_DMABUF_START 0x406555/* enum: End of GMAC stats buffer space, for Siena only. */6556#define MC_CMD_GMAC_DMABUF_END 0x5f6557/* enum: GENERATION_END value, used together with GENERATION_START to verify6558 * consistency of DMAd data. For legacy firmware / drivers without extended6559 * stats (more precisely, when DMA_LEN == MC_CMD_MAC_NSTATS *6560 * sizeof(uint64_t)), this entry holds the GENERATION_END value. Otherwise,6561 * this value is invalid/ reserved and GENERATION_END is written as the last6562 * 64-bit word of the DMA buffer (at DMA_LEN - sizeof(uint64_t)). Note that6563 * this is consistent with the legacy behaviour, in the sense that entry 96 is6564 * the last 64-bit word in the buffer when DMA_LEN == MC_CMD_MAC_NSTATS *6565 * sizeof(uint64_t). See SF-109306-TC, Section 9.2 for details.6566 */6567#define MC_CMD_MAC_GENERATION_END 0x606568#define MC_CMD_MAC_NSTATS 0x61 /* enum */6569 6570/* MC_CMD_MAC_STATS_V2_OUT_DMA msgresponse */6571#define MC_CMD_MAC_STATS_V2_OUT_DMA_LEN 06572 6573/* MC_CMD_MAC_STATS_V2_OUT_NO_DMA msgresponse */6574#define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_LEN (((MC_CMD_MAC_NSTATS_V2*64))>>3)6575#define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_OFST 06576#define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_LEN 86577#define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_LO_OFST 06578#define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_LO_LEN 46579#define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_LO_LBN 06580#define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_LO_WIDTH 326581#define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_HI_OFST 46582#define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_HI_LEN 46583#define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_HI_LBN 326584#define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_HI_WIDTH 326585#define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS_V26586/* enum: Start of FEC stats buffer space, Medford2 and up */6587#define MC_CMD_MAC_FEC_DMABUF_START 0x616588/* enum: Number of uncorrected FEC codewords on link (RS-FEC only for Medford2)6589 */6590#define MC_CMD_MAC_FEC_UNCORRECTED_ERRORS 0x616591/* enum: Number of corrected FEC codewords on link (RS-FEC only for Medford2)6592 */6593#define MC_CMD_MAC_FEC_CORRECTED_ERRORS 0x626594/* enum: Number of corrected 10-bit symbol errors, lane 0 (RS-FEC only) */6595#define MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE0 0x636596/* enum: Number of corrected 10-bit symbol errors, lane 1 (RS-FEC only) */6597#define MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE1 0x646598/* enum: Number of corrected 10-bit symbol errors, lane 2 (RS-FEC only) */6599#define MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE2 0x656600/* enum: Number of corrected 10-bit symbol errors, lane 3 (RS-FEC only) */6601#define MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE3 0x666602/* enum: This includes the space at offset 103 which is the final6603 * GENERATION_END in a MAC_STATS_V2 response and otherwise unused.6604 */6605#define MC_CMD_MAC_NSTATS_V2 0x686606/* Other enum values, see field(s): */6607/* MC_CMD_MAC_STATS_OUT_NO_DMA/STATISTICS */6608 6609/* MC_CMD_MAC_STATS_V3_OUT_DMA msgresponse */6610#define MC_CMD_MAC_STATS_V3_OUT_DMA_LEN 06611 6612/* MC_CMD_MAC_STATS_V3_OUT_NO_DMA msgresponse */6613#define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_LEN (((MC_CMD_MAC_NSTATS_V3*64))>>3)6614#define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_OFST 06615#define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_LEN 86616#define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_LO_OFST 06617#define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_LO_LEN 46618#define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_LO_LBN 06619#define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_LO_WIDTH 326620#define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_HI_OFST 46621#define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_HI_LEN 46622#define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_HI_LBN 326623#define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_HI_WIDTH 326624#define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS_V36625/* enum: Start of CTPIO stats buffer space, Medford2 and up */6626#define MC_CMD_MAC_CTPIO_DMABUF_START 0x686627/* enum: Number of CTPIO fallbacks because a DMA packet was in progress on the6628 * target VI6629 */6630#define MC_CMD_MAC_CTPIO_VI_BUSY_FALLBACK 0x686631/* enum: Number of times a CTPIO send wrote beyond frame end (informational6632 * only)6633 */6634#define MC_CMD_MAC_CTPIO_LONG_WRITE_SUCCESS 0x696635/* enum: Number of CTPIO failures because the TX doorbell was written before6636 * the end of the frame data6637 */6638#define MC_CMD_MAC_CTPIO_MISSING_DBELL_FAIL 0x6a6639/* enum: Number of CTPIO failures because the internal FIFO overflowed */6640#define MC_CMD_MAC_CTPIO_OVERFLOW_FAIL 0x6b6641/* enum: Number of CTPIO failures because the host did not deliver data fast6642 * enough to avoid MAC underflow6643 */6644#define MC_CMD_MAC_CTPIO_UNDERFLOW_FAIL 0x6c6645/* enum: Number of CTPIO failures because the host did not deliver all the6646 * frame data within the timeout6647 */6648#define MC_CMD_MAC_CTPIO_TIMEOUT_FAIL 0x6d6649/* enum: Number of CTPIO failures because the frame data arrived out of order6650 * or with gaps6651 */6652#define MC_CMD_MAC_CTPIO_NONCONTIG_WR_FAIL 0x6e6653/* enum: Number of CTPIO failures because the host started a new frame before6654 * completing the previous one6655 */6656#define MC_CMD_MAC_CTPIO_FRM_CLOBBER_FAIL 0x6f6657/* enum: Number of CTPIO failures because a write was not a multiple of 32 bits6658 * or not 32-bit aligned6659 */6660#define MC_CMD_MAC_CTPIO_INVALID_WR_FAIL 0x706661/* enum: Number of CTPIO fallbacks because another VI on the same port was6662 * sending a CTPIO frame6663 */6664#define MC_CMD_MAC_CTPIO_VI_CLOBBER_FALLBACK 0x716665/* enum: Number of CTPIO fallbacks because target VI did not have CTPIO enabled6666 */6667#define MC_CMD_MAC_CTPIO_UNQUALIFIED_FALLBACK 0x726668/* enum: Number of CTPIO fallbacks because length in header was less than 296669 * bytes6670 */6671#define MC_CMD_MAC_CTPIO_RUNT_FALLBACK 0x736672/* enum: Total number of successful CTPIO sends on this port */6673#define MC_CMD_MAC_CTPIO_SUCCESS 0x746674/* enum: Total number of CTPIO fallbacks on this port */6675#define MC_CMD_MAC_CTPIO_FALLBACK 0x756676/* enum: Total number of CTPIO poisoned frames on this port, whether erased or6677 * not6678 */6679#define MC_CMD_MAC_CTPIO_POISON 0x766680/* enum: Total number of CTPIO erased frames on this port */6681#define MC_CMD_MAC_CTPIO_ERASE 0x776682/* enum: This includes the space at offset 120 which is the final6683 * GENERATION_END in a MAC_STATS_V3 response and otherwise unused.6684 */6685#define MC_CMD_MAC_NSTATS_V3 0x796686/* Other enum values, see field(s): */6687/* MC_CMD_MAC_STATS_V2_OUT_NO_DMA/STATISTICS */6688 6689/* MC_CMD_MAC_STATS_V4_OUT_DMA msgresponse */6690#define MC_CMD_MAC_STATS_V4_OUT_DMA_LEN 06691 6692/* MC_CMD_MAC_STATS_V4_OUT_NO_DMA msgresponse */6693#define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_LEN (((MC_CMD_MAC_NSTATS_V4*64))>>3)6694#define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_OFST 06695#define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_LEN 86696#define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_LO_OFST 06697#define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_LO_LEN 46698#define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_LO_LBN 06699#define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_LO_WIDTH 326700#define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_HI_OFST 46701#define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_HI_LEN 46702#define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_HI_LBN 326703#define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_HI_WIDTH 326704#define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS_V46705/* enum: Start of V4 stats buffer space */6706#define MC_CMD_MAC_V4_DMABUF_START 0x796707/* enum: RXDP counter: Number of packets truncated because scattering was6708 * disabled.6709 */6710#define MC_CMD_MAC_RXDP_SCATTER_DISABLED_TRUNC 0x796711/* enum: RXDP counter: Number of times the RXDP head of line blocked waiting6712 * for descriptors. Will be zero unless RXDP_HLB_IDLE capability is set.6713 */6714#define MC_CMD_MAC_RXDP_HLB_IDLE 0x7a6715/* enum: RXDP counter: Number of times the RXDP timed out while head of line6716 * blocking. Will be zero unless RXDP_HLB_IDLE capability is set.6717 */6718#define MC_CMD_MAC_RXDP_HLB_TIMEOUT 0x7b6719/* enum: This includes the space at offset 124 which is the final6720 * GENERATION_END in a MAC_STATS_V4 response and otherwise unused.6721 */6722#define MC_CMD_MAC_NSTATS_V4 0x7d6723/* Other enum values, see field(s): */6724/* MC_CMD_MAC_STATS_V3_OUT_NO_DMA/STATISTICS */6725 6726 6727/***********************************/6728/* MC_CMD_SRIOV6729 * to be documented6730 */6731#define MC_CMD_SRIOV 0x306732 6733/* MC_CMD_SRIOV_IN msgrequest */6734#define MC_CMD_SRIOV_IN_LEN 126735#define MC_CMD_SRIOV_IN_ENABLE_OFST 06736#define MC_CMD_SRIOV_IN_ENABLE_LEN 46737#define MC_CMD_SRIOV_IN_VI_BASE_OFST 46738#define MC_CMD_SRIOV_IN_VI_BASE_LEN 46739#define MC_CMD_SRIOV_IN_VF_COUNT_OFST 86740#define MC_CMD_SRIOV_IN_VF_COUNT_LEN 46741 6742/* MC_CMD_SRIOV_OUT msgresponse */6743#define MC_CMD_SRIOV_OUT_LEN 86744#define MC_CMD_SRIOV_OUT_VI_SCALE_OFST 06745#define MC_CMD_SRIOV_OUT_VI_SCALE_LEN 46746#define MC_CMD_SRIOV_OUT_VF_TOTAL_OFST 46747#define MC_CMD_SRIOV_OUT_VF_TOTAL_LEN 46748 6749/* MC_CMD_MEMCPY_RECORD_TYPEDEF structuredef */6750#define MC_CMD_MEMCPY_RECORD_TYPEDEF_LEN 326751/* this is only used for the first record */6752#define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_OFST 06753#define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_LEN 46754#define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_LBN 06755#define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_WIDTH 326756#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_OFST 46757#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_LEN 46758#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_LBN 326759#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_WIDTH 326760#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_OFST 86761#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LEN 86762#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LO_OFST 86763#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LO_LEN 46764#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LO_LBN 646765#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LO_WIDTH 326766#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_HI_OFST 126767#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_HI_LEN 46768#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_HI_LBN 966769#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_HI_WIDTH 326770#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LBN 646771#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_WIDTH 646772#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_OFST 166773#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_LEN 46774#define MC_CMD_MEMCPY_RECORD_TYPEDEF_RID_INLINE 0x100 /* enum */6775#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_LBN 1286776#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_WIDTH 326777#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_OFST 206778#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LEN 86779#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LO_OFST 206780#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LO_LEN 46781#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LO_LBN 1606782#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LO_WIDTH 326783#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_HI_OFST 246784#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_HI_LEN 46785#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_HI_LBN 1926786#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_HI_WIDTH 326787#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LBN 1606788#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_WIDTH 646789#define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_OFST 286790#define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_LEN 46791#define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_LBN 2246792#define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_WIDTH 326793 6794 6795/***********************************/6796/* MC_CMD_MEMCPY6797 * DMA write data into (Rid,Addr), either by dma reading (Rid,Addr), or by data6798 * embedded directly in the command.6799 *6800 * A common pattern is for a client to use generation counts to signal a dma6801 * update of a datastructure. To facilitate this, this MCDI operation can6802 * contain multiple requests which are executed in strict order. Requests take6803 * the form of duplicating the entire MCDI request continuously (including the6804 * requests record, which is ignored in all but the first structure)6805 *6806 * The source data can either come from a DMA from the host, or it can be6807 * embedded within the request directly, thereby eliminating a DMA read. To6808 * indicate this, the client sets FROM_RID=%RID_INLINE, ADDR_HI=0, and6809 * ADDR_LO=offset, and inserts the data at %offset from the start of the6810 * payload. It's the callers responsibility to ensure that the embedded data6811 * doesn't overlap the records.6812 *6813 * Returns: 0, EINVAL (invalid RID)6814 */6815#define MC_CMD_MEMCPY 0x316816 6817/* MC_CMD_MEMCPY_IN msgrequest */6818#define MC_CMD_MEMCPY_IN_LENMIN 326819#define MC_CMD_MEMCPY_IN_LENMAX 2246820#define MC_CMD_MEMCPY_IN_LENMAX_MCDI2 9926821#define MC_CMD_MEMCPY_IN_LEN(num) (0+32*(num))6822#define MC_CMD_MEMCPY_IN_RECORD_NUM(len) (((len)-0)/32)6823/* see MC_CMD_MEMCPY_RECORD_TYPEDEF */6824#define MC_CMD_MEMCPY_IN_RECORD_OFST 06825#define MC_CMD_MEMCPY_IN_RECORD_LEN 326826#define MC_CMD_MEMCPY_IN_RECORD_MINNUM 16827#define MC_CMD_MEMCPY_IN_RECORD_MAXNUM 76828#define MC_CMD_MEMCPY_IN_RECORD_MAXNUM_MCDI2 316829 6830/* MC_CMD_MEMCPY_OUT msgresponse */6831#define MC_CMD_MEMCPY_OUT_LEN 06832 6833 6834/***********************************/6835/* MC_CMD_WOL_FILTER_SET6836 * Set a WoL filter.6837 */6838#define MC_CMD_WOL_FILTER_SET 0x326839#undef MC_CMD_0x32_PRIVILEGE_CTG6840 6841#define MC_CMD_0x32_PRIVILEGE_CTG SRIOV_CTG_LINK6842 6843/* MC_CMD_WOL_FILTER_SET_IN msgrequest */6844#define MC_CMD_WOL_FILTER_SET_IN_LEN 1926845#define MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 06846#define MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 46847#define MC_CMD_FILTER_MODE_SIMPLE 0x0 /* enum */6848#define MC_CMD_FILTER_MODE_STRUCTURED 0xffffffff /* enum */6849/* A type value of 1 is unused. */6850#define MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 46851#define MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 46852/* enum: Magic */6853#define MC_CMD_WOL_TYPE_MAGIC 0x06854/* enum: MS Windows Magic */6855#define MC_CMD_WOL_TYPE_WIN_MAGIC 0x26856/* enum: IPv4 Syn */6857#define MC_CMD_WOL_TYPE_IPV4_SYN 0x36858/* enum: IPv6 Syn */6859#define MC_CMD_WOL_TYPE_IPV6_SYN 0x46860/* enum: Bitmap */6861#define MC_CMD_WOL_TYPE_BITMAP 0x56862/* enum: Link */6863#define MC_CMD_WOL_TYPE_LINK 0x66864/* enum: (Above this for future use) */6865#define MC_CMD_WOL_TYPE_MAX 0x76866#define MC_CMD_WOL_FILTER_SET_IN_DATA_OFST 86867#define MC_CMD_WOL_FILTER_SET_IN_DATA_LEN 46868#define MC_CMD_WOL_FILTER_SET_IN_DATA_NUM 466869 6870/* MC_CMD_WOL_FILTER_SET_IN_MAGIC msgrequest */6871#define MC_CMD_WOL_FILTER_SET_IN_MAGIC_LEN 166872/* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */6873/* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4 */6874/* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */6875/* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4 */6876#define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_OFST 86877#define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LEN 86878#define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LO_OFST 86879#define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LO_LEN 46880#define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LO_LBN 646881#define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LO_WIDTH 326882#define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_HI_OFST 126883#define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_HI_LEN 46884#define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_HI_LBN 966885#define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_HI_WIDTH 326886 6887/* MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN msgrequest */6888#define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_LEN 206889/* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */6890/* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4 */6891/* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */6892/* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4 */6893#define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_IP_OFST 86894#define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_IP_LEN 46895#define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_IP_OFST 126896#define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_IP_LEN 46897#define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_PORT_OFST 166898#define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_PORT_LEN 26899#define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_PORT_OFST 186900#define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_PORT_LEN 26901 6902/* MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN msgrequest */6903#define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_LEN 446904/* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */6905/* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4 */6906/* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */6907/* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4 */6908#define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_IP_OFST 86909#define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_IP_LEN 166910#define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_IP_OFST 246911#define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_IP_LEN 166912#define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_PORT_OFST 406913#define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_PORT_LEN 26914#define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_PORT_OFST 426915#define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_PORT_LEN 26916 6917/* MC_CMD_WOL_FILTER_SET_IN_BITMAP msgrequest */6918#define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN 1876919/* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */6920/* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4 */6921/* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */6922/* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4 */6923#define MC_CMD_WOL_FILTER_SET_IN_BITMAP_MASK_OFST 86924#define MC_CMD_WOL_FILTER_SET_IN_BITMAP_MASK_LEN 486925#define MC_CMD_WOL_FILTER_SET_IN_BITMAP_BITMAP_OFST 566926#define MC_CMD_WOL_FILTER_SET_IN_BITMAP_BITMAP_LEN 1286927#define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN_OFST 1846928#define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN_LEN 16929#define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER3_OFST 1856930#define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER3_LEN 16931#define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER4_OFST 1866932#define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER4_LEN 16933 6934/* MC_CMD_WOL_FILTER_SET_IN_LINK msgrequest */6935#define MC_CMD_WOL_FILTER_SET_IN_LINK_LEN 126936/* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */6937/* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4 */6938/* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */6939/* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4 */6940#define MC_CMD_WOL_FILTER_SET_IN_LINK_MASK_OFST 86941#define MC_CMD_WOL_FILTER_SET_IN_LINK_MASK_LEN 46942#define MC_CMD_WOL_FILTER_SET_IN_LINK_UP_OFST 86943#define MC_CMD_WOL_FILTER_SET_IN_LINK_UP_LBN 06944#define MC_CMD_WOL_FILTER_SET_IN_LINK_UP_WIDTH 16945#define MC_CMD_WOL_FILTER_SET_IN_LINK_DOWN_OFST 86946#define MC_CMD_WOL_FILTER_SET_IN_LINK_DOWN_LBN 16947#define MC_CMD_WOL_FILTER_SET_IN_LINK_DOWN_WIDTH 16948 6949/* MC_CMD_WOL_FILTER_SET_OUT msgresponse */6950#define MC_CMD_WOL_FILTER_SET_OUT_LEN 46951#define MC_CMD_WOL_FILTER_SET_OUT_FILTER_ID_OFST 06952#define MC_CMD_WOL_FILTER_SET_OUT_FILTER_ID_LEN 46953 6954 6955/***********************************/6956/* MC_CMD_WOL_FILTER_REMOVE6957 * Remove a WoL filter. Locks required: None. Returns: 0, EINVAL, ENOSYS6958 */6959#define MC_CMD_WOL_FILTER_REMOVE 0x336960#undef MC_CMD_0x33_PRIVILEGE_CTG6961 6962#define MC_CMD_0x33_PRIVILEGE_CTG SRIOV_CTG_LINK6963 6964/* MC_CMD_WOL_FILTER_REMOVE_IN msgrequest */6965#define MC_CMD_WOL_FILTER_REMOVE_IN_LEN 46966#define MC_CMD_WOL_FILTER_REMOVE_IN_FILTER_ID_OFST 06967#define MC_CMD_WOL_FILTER_REMOVE_IN_FILTER_ID_LEN 46968 6969/* MC_CMD_WOL_FILTER_REMOVE_OUT msgresponse */6970#define MC_CMD_WOL_FILTER_REMOVE_OUT_LEN 06971 6972 6973/***********************************/6974/* MC_CMD_WOL_FILTER_RESET6975 * Reset (i.e. remove all) WoL filters. Locks required: None. Returns: 0,6976 * ENOSYS6977 */6978#define MC_CMD_WOL_FILTER_RESET 0x346979#undef MC_CMD_0x34_PRIVILEGE_CTG6980 6981#define MC_CMD_0x34_PRIVILEGE_CTG SRIOV_CTG_LINK6982 6983/* MC_CMD_WOL_FILTER_RESET_IN msgrequest */6984#define MC_CMD_WOL_FILTER_RESET_IN_LEN 46985#define MC_CMD_WOL_FILTER_RESET_IN_MASK_OFST 06986#define MC_CMD_WOL_FILTER_RESET_IN_MASK_LEN 46987#define MC_CMD_WOL_FILTER_RESET_IN_WAKE_FILTERS 0x1 /* enum */6988#define MC_CMD_WOL_FILTER_RESET_IN_LIGHTSOUT_OFFLOADS 0x2 /* enum */6989 6990/* MC_CMD_WOL_FILTER_RESET_OUT msgresponse */6991#define MC_CMD_WOL_FILTER_RESET_OUT_LEN 06992 6993 6994/***********************************/6995/* MC_CMD_SET_MCAST_HASH6996 * Set the MCAST hash value without otherwise reconfiguring the MAC6997 */6998#define MC_CMD_SET_MCAST_HASH 0x356999 7000/* MC_CMD_SET_MCAST_HASH_IN msgrequest */7001#define MC_CMD_SET_MCAST_HASH_IN_LEN 327002#define MC_CMD_SET_MCAST_HASH_IN_HASH0_OFST 07003#define MC_CMD_SET_MCAST_HASH_IN_HASH0_LEN 167004#define MC_CMD_SET_MCAST_HASH_IN_HASH1_OFST 167005#define MC_CMD_SET_MCAST_HASH_IN_HASH1_LEN 167006 7007/* MC_CMD_SET_MCAST_HASH_OUT msgresponse */7008#define MC_CMD_SET_MCAST_HASH_OUT_LEN 07009 7010 7011/***********************************/7012/* MC_CMD_NVRAM_TYPES7013 * Return bitfield indicating available types of virtual NVRAM partitions.7014 * Locks required: none. Returns: 07015 */7016#define MC_CMD_NVRAM_TYPES 0x367017#undef MC_CMD_0x36_PRIVILEGE_CTG7018 7019#define MC_CMD_0x36_PRIVILEGE_CTG SRIOV_CTG_ADMIN7020 7021/* MC_CMD_NVRAM_TYPES_IN msgrequest */7022#define MC_CMD_NVRAM_TYPES_IN_LEN 07023 7024/* MC_CMD_NVRAM_TYPES_OUT msgresponse */7025#define MC_CMD_NVRAM_TYPES_OUT_LEN 47026/* Bit mask of supported types. */7027#define MC_CMD_NVRAM_TYPES_OUT_TYPES_OFST 07028#define MC_CMD_NVRAM_TYPES_OUT_TYPES_LEN 47029/* enum: Disabled callisto. */7030#define MC_CMD_NVRAM_TYPE_DISABLED_CALLISTO 0x07031/* enum: MC firmware. */7032#define MC_CMD_NVRAM_TYPE_MC_FW 0x17033/* enum: MC backup firmware. */7034#define MC_CMD_NVRAM_TYPE_MC_FW_BACKUP 0x27035/* enum: Static configuration Port0. */7036#define MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT0 0x37037/* enum: Static configuration Port1. */7038#define MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT1 0x47039/* enum: Dynamic configuration Port0. */7040#define MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT0 0x57041/* enum: Dynamic configuration Port1. */7042#define MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT1 0x67043/* enum: Expansion Rom. */7044#define MC_CMD_NVRAM_TYPE_EXP_ROM 0x77045/* enum: Expansion Rom Configuration Port0. */7046#define MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT0 0x87047/* enum: Expansion Rom Configuration Port1. */7048#define MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT1 0x97049/* enum: Phy Configuration Port0. */7050#define MC_CMD_NVRAM_TYPE_PHY_PORT0 0xa7051/* enum: Phy Configuration Port1. */7052#define MC_CMD_NVRAM_TYPE_PHY_PORT1 0xb7053/* enum: Log. */7054#define MC_CMD_NVRAM_TYPE_LOG 0xc7055/* enum: FPGA image. */7056#define MC_CMD_NVRAM_TYPE_FPGA 0xd7057/* enum: FPGA backup image */7058#define MC_CMD_NVRAM_TYPE_FPGA_BACKUP 0xe7059/* enum: FC firmware. */7060#define MC_CMD_NVRAM_TYPE_FC_FW 0xf7061/* enum: FC backup firmware. */7062#define MC_CMD_NVRAM_TYPE_FC_FW_BACKUP 0x107063/* enum: CPLD image. */7064#define MC_CMD_NVRAM_TYPE_CPLD 0x117065/* enum: Licensing information. */7066#define MC_CMD_NVRAM_TYPE_LICENSE 0x127067/* enum: FC Log. */7068#define MC_CMD_NVRAM_TYPE_FC_LOG 0x137069/* enum: Additional flash on FPGA. */7070#define MC_CMD_NVRAM_TYPE_FC_EXTRA 0x147071 7072 7073/***********************************/7074/* MC_CMD_NVRAM_INFO7075 * Read info about a virtual NVRAM partition. Locks required: none. Returns: 0,7076 * EINVAL (bad type).7077 */7078#define MC_CMD_NVRAM_INFO 0x377079#undef MC_CMD_0x37_PRIVILEGE_CTG7080 7081#define MC_CMD_0x37_PRIVILEGE_CTG SRIOV_CTG_ADMIN7082 7083/* MC_CMD_NVRAM_INFO_IN msgrequest */7084#define MC_CMD_NVRAM_INFO_IN_LEN 47085#define MC_CMD_NVRAM_INFO_IN_TYPE_OFST 07086#define MC_CMD_NVRAM_INFO_IN_TYPE_LEN 47087/* Enum values, see field(s): */7088/* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */7089 7090/* MC_CMD_NVRAM_INFO_OUT msgresponse */7091#define MC_CMD_NVRAM_INFO_OUT_LEN 247092#define MC_CMD_NVRAM_INFO_OUT_TYPE_OFST 07093#define MC_CMD_NVRAM_INFO_OUT_TYPE_LEN 47094/* Enum values, see field(s): */7095/* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */7096#define MC_CMD_NVRAM_INFO_OUT_SIZE_OFST 47097#define MC_CMD_NVRAM_INFO_OUT_SIZE_LEN 47098#define MC_CMD_NVRAM_INFO_OUT_ERASESIZE_OFST 87099#define MC_CMD_NVRAM_INFO_OUT_ERASESIZE_LEN 47100#define MC_CMD_NVRAM_INFO_OUT_FLAGS_OFST 127101#define MC_CMD_NVRAM_INFO_OUT_FLAGS_LEN 47102#define MC_CMD_NVRAM_INFO_OUT_PROTECTED_OFST 127103#define MC_CMD_NVRAM_INFO_OUT_PROTECTED_LBN 07104#define MC_CMD_NVRAM_INFO_OUT_PROTECTED_WIDTH 17105#define MC_CMD_NVRAM_INFO_OUT_TLV_OFST 127106#define MC_CMD_NVRAM_INFO_OUT_TLV_LBN 17107#define MC_CMD_NVRAM_INFO_OUT_TLV_WIDTH 17108#define MC_CMD_NVRAM_INFO_OUT_READ_ONLY_IF_TSA_BOUND_OFST 127109#define MC_CMD_NVRAM_INFO_OUT_READ_ONLY_IF_TSA_BOUND_LBN 27110#define MC_CMD_NVRAM_INFO_OUT_READ_ONLY_IF_TSA_BOUND_WIDTH 17111#define MC_CMD_NVRAM_INFO_OUT_CRC_OFST 127112#define MC_CMD_NVRAM_INFO_OUT_CRC_LBN 37113#define MC_CMD_NVRAM_INFO_OUT_CRC_WIDTH 17114#define MC_CMD_NVRAM_INFO_OUT_READ_ONLY_OFST 127115#define MC_CMD_NVRAM_INFO_OUT_READ_ONLY_LBN 57116#define MC_CMD_NVRAM_INFO_OUT_READ_ONLY_WIDTH 17117#define MC_CMD_NVRAM_INFO_OUT_CMAC_OFST 127118#define MC_CMD_NVRAM_INFO_OUT_CMAC_LBN 67119#define MC_CMD_NVRAM_INFO_OUT_CMAC_WIDTH 17120#define MC_CMD_NVRAM_INFO_OUT_A_B_OFST 127121#define MC_CMD_NVRAM_INFO_OUT_A_B_LBN 77122#define MC_CMD_NVRAM_INFO_OUT_A_B_WIDTH 17123#define MC_CMD_NVRAM_INFO_OUT_PHYSDEV_OFST 167124#define MC_CMD_NVRAM_INFO_OUT_PHYSDEV_LEN 47125#define MC_CMD_NVRAM_INFO_OUT_PHYSADDR_OFST 207126#define MC_CMD_NVRAM_INFO_OUT_PHYSADDR_LEN 47127 7128/* MC_CMD_NVRAM_INFO_V2_OUT msgresponse */7129#define MC_CMD_NVRAM_INFO_V2_OUT_LEN 287130#define MC_CMD_NVRAM_INFO_V2_OUT_TYPE_OFST 07131#define MC_CMD_NVRAM_INFO_V2_OUT_TYPE_LEN 47132/* Enum values, see field(s): */7133/* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */7134#define MC_CMD_NVRAM_INFO_V2_OUT_SIZE_OFST 47135#define MC_CMD_NVRAM_INFO_V2_OUT_SIZE_LEN 47136#define MC_CMD_NVRAM_INFO_V2_OUT_ERASESIZE_OFST 87137#define MC_CMD_NVRAM_INFO_V2_OUT_ERASESIZE_LEN 47138#define MC_CMD_NVRAM_INFO_V2_OUT_FLAGS_OFST 127139#define MC_CMD_NVRAM_INFO_V2_OUT_FLAGS_LEN 47140#define MC_CMD_NVRAM_INFO_V2_OUT_PROTECTED_OFST 127141#define MC_CMD_NVRAM_INFO_V2_OUT_PROTECTED_LBN 07142#define MC_CMD_NVRAM_INFO_V2_OUT_PROTECTED_WIDTH 17143#define MC_CMD_NVRAM_INFO_V2_OUT_TLV_OFST 127144#define MC_CMD_NVRAM_INFO_V2_OUT_TLV_LBN 17145#define MC_CMD_NVRAM_INFO_V2_OUT_TLV_WIDTH 17146#define MC_CMD_NVRAM_INFO_V2_OUT_READ_ONLY_IF_TSA_BOUND_OFST 127147#define MC_CMD_NVRAM_INFO_V2_OUT_READ_ONLY_IF_TSA_BOUND_LBN 27148#define MC_CMD_NVRAM_INFO_V2_OUT_READ_ONLY_IF_TSA_BOUND_WIDTH 17149#define MC_CMD_NVRAM_INFO_V2_OUT_READ_ONLY_OFST 127150#define MC_CMD_NVRAM_INFO_V2_OUT_READ_ONLY_LBN 57151#define MC_CMD_NVRAM_INFO_V2_OUT_READ_ONLY_WIDTH 17152#define MC_CMD_NVRAM_INFO_V2_OUT_A_B_OFST 127153#define MC_CMD_NVRAM_INFO_V2_OUT_A_B_LBN 77154#define MC_CMD_NVRAM_INFO_V2_OUT_A_B_WIDTH 17155#define MC_CMD_NVRAM_INFO_V2_OUT_PHYSDEV_OFST 167156#define MC_CMD_NVRAM_INFO_V2_OUT_PHYSDEV_LEN 47157#define MC_CMD_NVRAM_INFO_V2_OUT_PHYSADDR_OFST 207158#define MC_CMD_NVRAM_INFO_V2_OUT_PHYSADDR_LEN 47159/* Writes must be multiples of this size. Added to support the MUM on Sorrento.7160 */7161#define MC_CMD_NVRAM_INFO_V2_OUT_WRITESIZE_OFST 247162#define MC_CMD_NVRAM_INFO_V2_OUT_WRITESIZE_LEN 47163 7164 7165/***********************************/7166/* MC_CMD_NVRAM_UPDATE_START7167 * Start a group of update operations on a virtual NVRAM partition. Locks7168 * required: PHY_LOCK if type==*PHY*. Returns: 0, EINVAL (bad type), EACCES (if7169 * PHY_LOCK required and not held). In an adapter bound to a TSA controller,7170 * MC_CMD_NVRAM_UPDATE_START can only be used on a subset of partition types7171 * i.e. static config, dynamic config and expansion ROM config. Attempting to7172 * perform this operation on a restricted partition will return the error7173 * EPERM.7174 */7175#define MC_CMD_NVRAM_UPDATE_START 0x387176#undef MC_CMD_0x38_PRIVILEGE_CTG7177 7178#define MC_CMD_0x38_PRIVILEGE_CTG SRIOV_CTG_ADMIN7179 7180/* MC_CMD_NVRAM_UPDATE_START_IN msgrequest: Legacy NVRAM_UPDATE_START request.7181 * Use NVRAM_UPDATE_START_V2_IN in new code7182 */7183#define MC_CMD_NVRAM_UPDATE_START_IN_LEN 47184#define MC_CMD_NVRAM_UPDATE_START_IN_TYPE_OFST 07185#define MC_CMD_NVRAM_UPDATE_START_IN_TYPE_LEN 47186/* Enum values, see field(s): */7187/* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */7188 7189/* MC_CMD_NVRAM_UPDATE_START_V2_IN msgrequest: Extended NVRAM_UPDATE_START7190 * request with additional flags indicating version of command in use. See7191 * MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT for details of extended functionality. Use7192 * paired up with NVRAM_UPDATE_FINISH_V2_IN.7193 */7194#define MC_CMD_NVRAM_UPDATE_START_V2_IN_LEN 87195#define MC_CMD_NVRAM_UPDATE_START_V2_IN_TYPE_OFST 07196#define MC_CMD_NVRAM_UPDATE_START_V2_IN_TYPE_LEN 47197/* Enum values, see field(s): */7198/* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */7199#define MC_CMD_NVRAM_UPDATE_START_V2_IN_FLAGS_OFST 47200#define MC_CMD_NVRAM_UPDATE_START_V2_IN_FLAGS_LEN 47201#define MC_CMD_NVRAM_UPDATE_START_V2_IN_FLAG_REPORT_VERIFY_RESULT_OFST 47202#define MC_CMD_NVRAM_UPDATE_START_V2_IN_FLAG_REPORT_VERIFY_RESULT_LBN 07203#define MC_CMD_NVRAM_UPDATE_START_V2_IN_FLAG_REPORT_VERIFY_RESULT_WIDTH 17204 7205/* MC_CMD_NVRAM_UPDATE_START_OUT msgresponse */7206#define MC_CMD_NVRAM_UPDATE_START_OUT_LEN 07207 7208 7209/***********************************/7210/* MC_CMD_NVRAM_READ7211 * Read data from a virtual NVRAM partition. Locks required: PHY_LOCK if7212 * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if7213 * PHY_LOCK required and not held)7214 */7215#define MC_CMD_NVRAM_READ 0x397216#undef MC_CMD_0x39_PRIVILEGE_CTG7217 7218#define MC_CMD_0x39_PRIVILEGE_CTG SRIOV_CTG_ADMIN7219 7220/* MC_CMD_NVRAM_READ_IN msgrequest */7221#define MC_CMD_NVRAM_READ_IN_LEN 127222#define MC_CMD_NVRAM_READ_IN_TYPE_OFST 07223#define MC_CMD_NVRAM_READ_IN_TYPE_LEN 47224/* Enum values, see field(s): */7225/* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */7226#define MC_CMD_NVRAM_READ_IN_OFFSET_OFST 47227#define MC_CMD_NVRAM_READ_IN_OFFSET_LEN 47228/* amount to read in bytes */7229#define MC_CMD_NVRAM_READ_IN_LENGTH_OFST 87230#define MC_CMD_NVRAM_READ_IN_LENGTH_LEN 47231 7232/* MC_CMD_NVRAM_READ_IN_V2 msgrequest */7233#define MC_CMD_NVRAM_READ_IN_V2_LEN 167234#define MC_CMD_NVRAM_READ_IN_V2_TYPE_OFST 07235#define MC_CMD_NVRAM_READ_IN_V2_TYPE_LEN 47236/* Enum values, see field(s): */7237/* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */7238#define MC_CMD_NVRAM_READ_IN_V2_OFFSET_OFST 47239#define MC_CMD_NVRAM_READ_IN_V2_OFFSET_LEN 47240/* amount to read in bytes */7241#define MC_CMD_NVRAM_READ_IN_V2_LENGTH_OFST 87242#define MC_CMD_NVRAM_READ_IN_V2_LENGTH_LEN 47243/* Optional control info. If a partition is stored with an A/B versioning7244 * scheme (i.e. in more than one physical partition in NVRAM) the host can set7245 * this to control which underlying physical partition is used to read data7246 * from. This allows it to perform a read-modify-write-verify with the write7247 * lock continuously held by calling NVRAM_UPDATE_START, reading the old7248 * contents using MODE=TARGET_CURRENT, overwriting the old partition and then7249 * verifying by reading with MODE=TARGET_BACKUP.7250 */7251#define MC_CMD_NVRAM_READ_IN_V2_MODE_OFST 127252#define MC_CMD_NVRAM_READ_IN_V2_MODE_LEN 47253/* enum: Same as omitting MODE: caller sees data in current partition unless it7254 * holds the write lock in which case it sees data in the partition it is7255 * updating.7256 */7257#define MC_CMD_NVRAM_READ_IN_V2_DEFAULT 0x07258/* enum: Read from the current partition of an A/B pair, even if holding the7259 * write lock.7260 */7261#define MC_CMD_NVRAM_READ_IN_V2_TARGET_CURRENT 0x17262/* enum: Read from the non-current (i.e. to be updated) partition of an A/B7263 * pair7264 */7265#define MC_CMD_NVRAM_READ_IN_V2_TARGET_BACKUP 0x27266 7267/* MC_CMD_NVRAM_READ_OUT msgresponse */7268#define MC_CMD_NVRAM_READ_OUT_LENMIN 17269#define MC_CMD_NVRAM_READ_OUT_LENMAX 2527270#define MC_CMD_NVRAM_READ_OUT_LENMAX_MCDI2 10207271#define MC_CMD_NVRAM_READ_OUT_LEN(num) (0+1*(num))7272#define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_NUM(len) (((len)-0)/1)7273#define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_OFST 07274#define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_LEN 17275#define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_MINNUM 17276#define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_MAXNUM 2527277#define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_MAXNUM_MCDI2 10207278 7279 7280/***********************************/7281/* MC_CMD_NVRAM_WRITE7282 * Write data to a virtual NVRAM partition. Locks required: PHY_LOCK if7283 * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if7284 * PHY_LOCK required and not held)7285 */7286#define MC_CMD_NVRAM_WRITE 0x3a7287#undef MC_CMD_0x3a_PRIVILEGE_CTG7288 7289#define MC_CMD_0x3a_PRIVILEGE_CTG SRIOV_CTG_ADMIN7290 7291/* MC_CMD_NVRAM_WRITE_IN msgrequest */7292#define MC_CMD_NVRAM_WRITE_IN_LENMIN 137293#define MC_CMD_NVRAM_WRITE_IN_LENMAX 2527294#define MC_CMD_NVRAM_WRITE_IN_LENMAX_MCDI2 10207295#define MC_CMD_NVRAM_WRITE_IN_LEN(num) (12+1*(num))7296#define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_NUM(len) (((len)-12)/1)7297#define MC_CMD_NVRAM_WRITE_IN_TYPE_OFST 07298#define MC_CMD_NVRAM_WRITE_IN_TYPE_LEN 47299/* Enum values, see field(s): */7300/* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */7301#define MC_CMD_NVRAM_WRITE_IN_OFFSET_OFST 47302#define MC_CMD_NVRAM_WRITE_IN_OFFSET_LEN 47303#define MC_CMD_NVRAM_WRITE_IN_LENGTH_OFST 87304#define MC_CMD_NVRAM_WRITE_IN_LENGTH_LEN 47305#define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_OFST 127306#define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_LEN 17307#define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_MINNUM 17308#define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_MAXNUM 2407309#define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_MAXNUM_MCDI2 10087310 7311/* MC_CMD_NVRAM_WRITE_OUT msgresponse */7312#define MC_CMD_NVRAM_WRITE_OUT_LEN 07313 7314 7315/***********************************/7316/* MC_CMD_NVRAM_ERASE7317 * Erase sector(s) from a virtual NVRAM partition. Locks required: PHY_LOCK if7318 * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if7319 * PHY_LOCK required and not held)7320 */7321#define MC_CMD_NVRAM_ERASE 0x3b7322#undef MC_CMD_0x3b_PRIVILEGE_CTG7323 7324#define MC_CMD_0x3b_PRIVILEGE_CTG SRIOV_CTG_ADMIN7325 7326/* MC_CMD_NVRAM_ERASE_IN msgrequest */7327#define MC_CMD_NVRAM_ERASE_IN_LEN 127328#define MC_CMD_NVRAM_ERASE_IN_TYPE_OFST 07329#define MC_CMD_NVRAM_ERASE_IN_TYPE_LEN 47330/* Enum values, see field(s): */7331/* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */7332#define MC_CMD_NVRAM_ERASE_IN_OFFSET_OFST 47333#define MC_CMD_NVRAM_ERASE_IN_OFFSET_LEN 47334#define MC_CMD_NVRAM_ERASE_IN_LENGTH_OFST 87335#define MC_CMD_NVRAM_ERASE_IN_LENGTH_LEN 47336 7337/* MC_CMD_NVRAM_ERASE_OUT msgresponse */7338#define MC_CMD_NVRAM_ERASE_OUT_LEN 07339 7340 7341/***********************************/7342/* MC_CMD_NVRAM_UPDATE_FINISH7343 * Finish a group of update operations on a virtual NVRAM partition. Locks7344 * required: PHY_LOCK if type==*PHY*. Returns: 0, EINVAL (bad type/offset/7345 * length), EACCES (if PHY_LOCK required and not held). In an adapter bound to7346 * a TSA controller, MC_CMD_NVRAM_UPDATE_FINISH can only be used on a subset of7347 * partition types i.e. static config, dynamic config and expansion ROM config.7348 * Attempting to perform this operation on a restricted partition will return7349 * the error EPERM.7350 */7351#define MC_CMD_NVRAM_UPDATE_FINISH 0x3c7352#undef MC_CMD_0x3c_PRIVILEGE_CTG7353 7354#define MC_CMD_0x3c_PRIVILEGE_CTG SRIOV_CTG_ADMIN7355 7356/* MC_CMD_NVRAM_UPDATE_FINISH_IN msgrequest: Legacy NVRAM_UPDATE_FINISH7357 * request. Use NVRAM_UPDATE_FINISH_V2_IN in new code7358 */7359#define MC_CMD_NVRAM_UPDATE_FINISH_IN_LEN 87360#define MC_CMD_NVRAM_UPDATE_FINISH_IN_TYPE_OFST 07361#define MC_CMD_NVRAM_UPDATE_FINISH_IN_TYPE_LEN 47362/* Enum values, see field(s): */7363/* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */7364#define MC_CMD_NVRAM_UPDATE_FINISH_IN_REBOOT_OFST 47365#define MC_CMD_NVRAM_UPDATE_FINISH_IN_REBOOT_LEN 47366 7367/* MC_CMD_NVRAM_UPDATE_FINISH_V2_IN msgrequest: Extended NVRAM_UPDATE_FINISH7368 * request with additional flags indicating version of NVRAM_UPDATE commands in7369 * use. See MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT for details of extended7370 * functionality. Use paired up with NVRAM_UPDATE_START_V2_IN.7371 */7372#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_LEN 127373#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_TYPE_OFST 07374#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_TYPE_LEN 47375/* Enum values, see field(s): */7376/* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */7377#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_REBOOT_OFST 47378#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_REBOOT_LEN 47379#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAGS_OFST 87380#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAGS_LEN 47381#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_REPORT_VERIFY_RESULT_OFST 87382#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_REPORT_VERIFY_RESULT_LBN 07383#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_REPORT_VERIFY_RESULT_WIDTH 17384#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_RUN_IN_BACKGROUND_OFST 87385#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_RUN_IN_BACKGROUND_LBN 17386#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_RUN_IN_BACKGROUND_WIDTH 17387#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_POLL_VERIFY_RESULT_OFST 87388#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_POLL_VERIFY_RESULT_LBN 27389#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_POLL_VERIFY_RESULT_WIDTH 17390#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_ABORT_OFST 87391#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_ABORT_LBN 37392#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_ABORT_WIDTH 17393 7394/* MC_CMD_NVRAM_UPDATE_FINISH_OUT msgresponse: Legacy NVRAM_UPDATE_FINISH7395 * response. Use NVRAM_UPDATE_FINISH_V2_OUT in new code7396 */7397#define MC_CMD_NVRAM_UPDATE_FINISH_OUT_LEN 07398 7399/* MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT msgresponse:7400 *7401 * Extended NVRAM_UPDATE_FINISH response that communicates the result of secure7402 * firmware validation where applicable back to the host.7403 *7404 * Medford only: For signed firmware images, such as those for medford, the MC7405 * firmware verifies the signature before marking the firmware image as valid.7406 * This process takes a few seconds to complete. So is likely to take more than7407 * the MCDI timeout. Hence signature verification is initiated when7408 * MC_CMD_NVRAM_UPDATE_FINISH_V2_IN is received by the firmware, however, the7409 * MCDI command is run in a background MCDI processing thread. This response7410 * payload includes the results of the signature verification. Note that the7411 * per-partition nvram lock in firmware is only released after the verification7412 * has completed.7413 */7414#define MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT_LEN 47415/* Result of nvram update completion processing. Result codes that indicate an7416 * internal build failure and therefore not expected to be seen by customers in7417 * the field are marked with a prefix 'Internal-error'.7418 */7419#define MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT_RESULT_CODE_OFST 07420#define MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT_RESULT_CODE_LEN 47421/* enum: Invalid return code; only non-zero values are defined. Defined as7422 * unknown for backwards compatibility with NVRAM_UPDATE_FINISH_OUT.7423 */7424#define MC_CMD_NVRAM_VERIFY_RC_UNKNOWN 0x07425/* enum: Verify succeeded without any errors. */7426#define MC_CMD_NVRAM_VERIFY_RC_SUCCESS 0x17427/* enum: CMS format verification failed due to an internal error. */7428#define MC_CMD_NVRAM_VERIFY_RC_CMS_CHECK_FAILED 0x27429/* enum: Invalid CMS format in image metadata. */7430#define MC_CMD_NVRAM_VERIFY_RC_INVALID_CMS_FORMAT 0x37431/* enum: Message digest verification failed due to an internal error. */7432#define MC_CMD_NVRAM_VERIFY_RC_MESSAGE_DIGEST_CHECK_FAILED 0x47433/* enum: Error in message digest calculated over the reflash-header, payload7434 * and reflash-trailer.7435 */7436#define MC_CMD_NVRAM_VERIFY_RC_BAD_MESSAGE_DIGEST 0x57437/* enum: Signature verification failed due to an internal error. */7438#define MC_CMD_NVRAM_VERIFY_RC_SIGNATURE_CHECK_FAILED 0x67439/* enum: There are no valid signatures in the image. */7440#define MC_CMD_NVRAM_VERIFY_RC_NO_VALID_SIGNATURES 0x77441/* enum: Trusted approvers verification failed due to an internal error. */7442#define MC_CMD_NVRAM_VERIFY_RC_TRUSTED_APPROVERS_CHECK_FAILED 0x87443/* enum: The Trusted approver's list is empty. */7444#define MC_CMD_NVRAM_VERIFY_RC_NO_TRUSTED_APPROVERS 0x97445/* enum: Signature chain verification failed due to an internal error. */7446#define MC_CMD_NVRAM_VERIFY_RC_SIGNATURE_CHAIN_CHECK_FAILED 0xa7447/* enum: The signers of the signatures in the image are not listed in the7448 * Trusted approver's list.7449 */7450#define MC_CMD_NVRAM_VERIFY_RC_NO_SIGNATURE_MATCH 0xb7451/* enum: The image contains a test-signed certificate, but the adapter accepts7452 * only production signed images.7453 */7454#define MC_CMD_NVRAM_VERIFY_RC_REJECT_TEST_SIGNED 0xc7455/* enum: The image has a lower security level than the current firmware. */7456#define MC_CMD_NVRAM_VERIFY_RC_SECURITY_LEVEL_DOWNGRADE 0xd7457/* enum: Internal-error. The signed image is missing the 'contents' section,7458 * where the 'contents' section holds the actual image payload to be applied.7459 */7460#define MC_CMD_NVRAM_VERIFY_RC_CONTENT_NOT_FOUND 0xe7461/* enum: Internal-error. The bundle header is invalid. */7462#define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_CONTENT_HEADER_INVALID 0xf7463/* enum: Internal-error. The bundle does not have a valid reflash image layout.7464 */7465#define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_REFLASH_IMAGE_INVALID 0x107466/* enum: Internal-error. The bundle has an inconsistent layout of components or7467 * incorrect checksum.7468 */7469#define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_IMAGE_LAYOUT_INVALID 0x117470/* enum: Internal-error. The bundle manifest is inconsistent with components in7471 * the bundle.7472 */7473#define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_MANIFEST_INVALID 0x127474/* enum: Internal-error. The number of components in a bundle do not match the7475 * number of components advertised by the bundle manifest.7476 */7477#define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_MANIFEST_NUM_COMPONENTS_MISMATCH 0x137478/* enum: Internal-error. The bundle contains too many components for the MC7479 * firmware to process7480 */7481#define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_MANIFEST_TOO_MANY_COMPONENTS 0x147482/* enum: Internal-error. The bundle manifest has an invalid/inconsistent7483 * component.7484 */7485#define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_MANIFEST_COMPONENT_INVALID 0x157486/* enum: Internal-error. The hash of a component does not match the hash stored7487 * in the bundle manifest.7488 */7489#define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_MANIFEST_COMPONENT_HASH_MISMATCH 0x167490/* enum: Internal-error. Component hash calculation failed. */7491#define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_MANIFEST_COMPONENT_HASH_FAILED 0x177492/* enum: Internal-error. The component does not have a valid reflash image7493 * layout.7494 */7495#define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_COMPONENT_REFLASH_IMAGE_INVALID 0x187496/* enum: The bundle processing code failed to copy a component to its target7497 * partition.7498 */7499#define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_COMPONENT_COPY_FAILED 0x197500/* enum: The update operation is in-progress. */7501#define MC_CMD_NVRAM_VERIFY_RC_PENDING 0x1a7502 7503 7504/***********************************/7505/* MC_CMD_REBOOT7506 * Reboot the MC.7507 *7508 * The AFTER_ASSERTION flag is intended to be used when the driver notices an7509 * assertion failure (at which point it is expected to perform a complete tear7510 * down and reinitialise), to allow both ports to reset the MC once in an7511 * atomic fashion.7512 *7513 * Production mc firmwares are generally compiled with REBOOT_ON_ASSERT=1,7514 * which means that they will automatically reboot out of the assertion7515 * handler, so this is in practise an optional operation. It is still7516 * recommended that drivers execute this to support custom firmwares with7517 * REBOOT_ON_ASSERT=0.7518 *7519 * Locks required: NONE Returns: Nothing. You get back a response with ERR=1,7520 * DATALEN=07521 */7522#define MC_CMD_REBOOT 0x3d7523#undef MC_CMD_0x3d_PRIVILEGE_CTG7524 7525#define MC_CMD_0x3d_PRIVILEGE_CTG SRIOV_CTG_ADMIN7526 7527/* MC_CMD_REBOOT_IN msgrequest */7528#define MC_CMD_REBOOT_IN_LEN 47529#define MC_CMD_REBOOT_IN_FLAGS_OFST 07530#define MC_CMD_REBOOT_IN_FLAGS_LEN 47531#define MC_CMD_REBOOT_FLAGS_AFTER_ASSERTION 0x1 /* enum */7532 7533/* MC_CMD_REBOOT_OUT msgresponse */7534#define MC_CMD_REBOOT_OUT_LEN 07535 7536 7537/***********************************/7538/* MC_CMD_SCHEDINFO7539 * Request scheduler info. Locks required: NONE. Returns: An array of7540 * (timeslice,maximum overrun), one for each thread, in ascending order of7541 * thread address.7542 */7543#define MC_CMD_SCHEDINFO 0x3e7544#undef MC_CMD_0x3e_PRIVILEGE_CTG7545 7546#define MC_CMD_0x3e_PRIVILEGE_CTG SRIOV_CTG_ADMIN7547 7548/* MC_CMD_SCHEDINFO_IN msgrequest */7549#define MC_CMD_SCHEDINFO_IN_LEN 07550 7551/* MC_CMD_SCHEDINFO_OUT msgresponse */7552#define MC_CMD_SCHEDINFO_OUT_LENMIN 47553#define MC_CMD_SCHEDINFO_OUT_LENMAX 2527554#define MC_CMD_SCHEDINFO_OUT_LENMAX_MCDI2 10207555#define MC_CMD_SCHEDINFO_OUT_LEN(num) (0+4*(num))7556#define MC_CMD_SCHEDINFO_OUT_DATA_NUM(len) (((len)-0)/4)7557#define MC_CMD_SCHEDINFO_OUT_DATA_OFST 07558#define MC_CMD_SCHEDINFO_OUT_DATA_LEN 47559#define MC_CMD_SCHEDINFO_OUT_DATA_MINNUM 17560#define MC_CMD_SCHEDINFO_OUT_DATA_MAXNUM 637561#define MC_CMD_SCHEDINFO_OUT_DATA_MAXNUM_MCDI2 2557562 7563 7564/***********************************/7565/* MC_CMD_REBOOT_MODE7566 * Set the mode for the next MC reboot. Locks required: NONE. Sets the reboot7567 * mode to the specified value. Returns the old mode.7568 */7569#define MC_CMD_REBOOT_MODE 0x3f7570#undef MC_CMD_0x3f_PRIVILEGE_CTG7571 7572#define MC_CMD_0x3f_PRIVILEGE_CTG SRIOV_CTG_INSECURE7573 7574/* MC_CMD_REBOOT_MODE_IN msgrequest */7575#define MC_CMD_REBOOT_MODE_IN_LEN 47576#define MC_CMD_REBOOT_MODE_IN_VALUE_OFST 07577#define MC_CMD_REBOOT_MODE_IN_VALUE_LEN 47578/* enum: Normal. */7579#define MC_CMD_REBOOT_MODE_NORMAL 0x07580/* enum: Power-on Reset. */7581#define MC_CMD_REBOOT_MODE_POR 0x27582/* enum: Snapper. */7583#define MC_CMD_REBOOT_MODE_SNAPPER 0x37584/* enum: snapper fake POR */7585#define MC_CMD_REBOOT_MODE_SNAPPER_POR 0x47586#define MC_CMD_REBOOT_MODE_IN_FAKE_OFST 07587#define MC_CMD_REBOOT_MODE_IN_FAKE_LBN 77588#define MC_CMD_REBOOT_MODE_IN_FAKE_WIDTH 17589 7590/* MC_CMD_REBOOT_MODE_OUT msgresponse */7591#define MC_CMD_REBOOT_MODE_OUT_LEN 47592#define MC_CMD_REBOOT_MODE_OUT_VALUE_OFST 07593#define MC_CMD_REBOOT_MODE_OUT_VALUE_LEN 47594 7595 7596/***********************************/7597/* MC_CMD_SENSOR_INFO7598 * Returns information about every available sensor.7599 *7600 * Each sensor has a single (16bit) value, and a corresponding state. The7601 * mapping between value and state is nominally determined by the MC, but may7602 * be implemented using up to 2 ranges per sensor.7603 *7604 * This call returns a mask (32bit) of the sensors that are supported by this7605 * platform, then an array of sensor information structures, in order of sensor7606 * type (but without gaps for unimplemented sensors). Each structure defines7607 * the ranges for the corresponding sensor. An unused range is indicated by7608 * equal limit values. If one range is used, a value outside that range results7609 * in STATE_FATAL. If two ranges are used, a value outside the second range7610 * results in STATE_FATAL while a value outside the first and inside the second7611 * range results in STATE_WARNING.7612 *7613 * Sensor masks and sensor information arrays are organised into pages. For7614 * backward compatibility, older host software can only use sensors in page 0.7615 * Bit 32 in the sensor mask was previously unused, and is no reserved for use7616 * as the next page flag.7617 *7618 * If the request does not contain a PAGE value then firmware will only return7619 * page 0 of sensor information, with bit 31 in the sensor mask cleared.7620 *7621 * If the request contains a PAGE value then firmware responds with the sensor7622 * mask and sensor information array for that page of sensors. In this case bit7623 * 31 in the mask is set if another page exists.7624 *7625 * Locks required: None Returns: 07626 */7627#define MC_CMD_SENSOR_INFO 0x417628#undef MC_CMD_0x41_PRIVILEGE_CTG7629 7630#define MC_CMD_0x41_PRIVILEGE_CTG SRIOV_CTG_GENERAL7631 7632/* MC_CMD_SENSOR_INFO_IN msgrequest */7633#define MC_CMD_SENSOR_INFO_IN_LEN 07634 7635/* MC_CMD_SENSOR_INFO_EXT_IN msgrequest */7636#define MC_CMD_SENSOR_INFO_EXT_IN_LEN 47637/* Which page of sensors to report.7638 *7639 * Page 0 contains sensors 0 to 30 (sensor 31 is the next page bit).7640 *7641 * Page 1 contains sensors 32 to 62 (sensor 63 is the next page bit). etc.7642 */7643#define MC_CMD_SENSOR_INFO_EXT_IN_PAGE_OFST 07644#define MC_CMD_SENSOR_INFO_EXT_IN_PAGE_LEN 47645 7646/* MC_CMD_SENSOR_INFO_EXT_IN_V2 msgrequest */7647#define MC_CMD_SENSOR_INFO_EXT_IN_V2_LEN 87648/* Which page of sensors to report.7649 *7650 * Page 0 contains sensors 0 to 30 (sensor 31 is the next page bit).7651 *7652 * Page 1 contains sensors 32 to 62 (sensor 63 is the next page bit). etc.7653 */7654#define MC_CMD_SENSOR_INFO_EXT_IN_V2_PAGE_OFST 07655#define MC_CMD_SENSOR_INFO_EXT_IN_V2_PAGE_LEN 47656/* Flags controlling information retrieved */7657#define MC_CMD_SENSOR_INFO_EXT_IN_V2_FLAGS_OFST 47658#define MC_CMD_SENSOR_INFO_EXT_IN_V2_FLAGS_LEN 47659#define MC_CMD_SENSOR_INFO_EXT_IN_V2_ENGINEERING_OFST 47660#define MC_CMD_SENSOR_INFO_EXT_IN_V2_ENGINEERING_LBN 07661#define MC_CMD_SENSOR_INFO_EXT_IN_V2_ENGINEERING_WIDTH 17662 7663/* MC_CMD_SENSOR_INFO_OUT msgresponse */7664#define MC_CMD_SENSOR_INFO_OUT_LENMIN 47665#define MC_CMD_SENSOR_INFO_OUT_LENMAX 2527666#define MC_CMD_SENSOR_INFO_OUT_LENMAX_MCDI2 10207667#define MC_CMD_SENSOR_INFO_OUT_LEN(num) (4+8*(num))7668#define MC_CMD_SENSOR_INFO_OUT_MC_CMD_SENSOR_ENTRY_NUM(len) (((len)-4)/8)7669#define MC_CMD_SENSOR_INFO_OUT_MASK_OFST 07670#define MC_CMD_SENSOR_INFO_OUT_MASK_LEN 47671/* enum: Controller temperature: degC */7672#define MC_CMD_SENSOR_CONTROLLER_TEMP 0x07673/* enum: Phy common temperature: degC */7674#define MC_CMD_SENSOR_PHY_COMMON_TEMP 0x17675/* enum: Controller cooling: bool */7676#define MC_CMD_SENSOR_CONTROLLER_COOLING 0x27677/* enum: Phy 0 temperature: degC */7678#define MC_CMD_SENSOR_PHY0_TEMP 0x37679/* enum: Phy 0 cooling: bool */7680#define MC_CMD_SENSOR_PHY0_COOLING 0x47681/* enum: Phy 1 temperature: degC */7682#define MC_CMD_SENSOR_PHY1_TEMP 0x57683/* enum: Phy 1 cooling: bool */7684#define MC_CMD_SENSOR_PHY1_COOLING 0x67685/* enum: 1.0v power: mV */7686#define MC_CMD_SENSOR_IN_1V0 0x77687/* enum: 1.2v power: mV */7688#define MC_CMD_SENSOR_IN_1V2 0x87689/* enum: 1.8v power: mV */7690#define MC_CMD_SENSOR_IN_1V8 0x97691/* enum: 2.5v power: mV */7692#define MC_CMD_SENSOR_IN_2V5 0xa7693/* enum: 3.3v power: mV */7694#define MC_CMD_SENSOR_IN_3V3 0xb7695/* enum: 12v power: mV */7696#define MC_CMD_SENSOR_IN_12V0 0xc7697/* enum: 1.2v analogue power: mV */7698#define MC_CMD_SENSOR_IN_1V2A 0xd7699/* enum: reference voltage: mV */7700#define MC_CMD_SENSOR_IN_VREF 0xe7701/* enum: AOE FPGA power: mV */7702#define MC_CMD_SENSOR_OUT_VAOE 0xf7703/* enum: AOE FPGA temperature: degC */7704#define MC_CMD_SENSOR_AOE_TEMP 0x107705/* enum: AOE FPGA PSU temperature: degC */7706#define MC_CMD_SENSOR_PSU_AOE_TEMP 0x117707/* enum: AOE PSU temperature: degC */7708#define MC_CMD_SENSOR_PSU_TEMP 0x127709/* enum: Fan 0 speed: RPM */7710#define MC_CMD_SENSOR_FAN_0 0x137711/* enum: Fan 1 speed: RPM */7712#define MC_CMD_SENSOR_FAN_1 0x147713/* enum: Fan 2 speed: RPM */7714#define MC_CMD_SENSOR_FAN_2 0x157715/* enum: Fan 3 speed: RPM */7716#define MC_CMD_SENSOR_FAN_3 0x167717/* enum: Fan 4 speed: RPM */7718#define MC_CMD_SENSOR_FAN_4 0x177719/* enum: AOE FPGA input power: mV */7720#define MC_CMD_SENSOR_IN_VAOE 0x187721/* enum: AOE FPGA current: mA */7722#define MC_CMD_SENSOR_OUT_IAOE 0x197723/* enum: AOE FPGA input current: mA */7724#define MC_CMD_SENSOR_IN_IAOE 0x1a7725/* enum: NIC power consumption: W */7726#define MC_CMD_SENSOR_NIC_POWER 0x1b7727/* enum: 0.9v power voltage: mV */7728#define MC_CMD_SENSOR_IN_0V9 0x1c7729/* enum: 0.9v power current: mA */7730#define MC_CMD_SENSOR_IN_I0V9 0x1d7731/* enum: 1.2v power current: mA */7732#define MC_CMD_SENSOR_IN_I1V2 0x1e7733/* enum: Not a sensor: reserved for the next page flag */7734#define MC_CMD_SENSOR_PAGE0_NEXT 0x1f7735/* enum: 0.9v power voltage (at ADC): mV */7736#define MC_CMD_SENSOR_IN_0V9_ADC 0x207737/* enum: Controller temperature 2: degC */7738#define MC_CMD_SENSOR_CONTROLLER_2_TEMP 0x217739/* enum: Voltage regulator internal temperature: degC */7740#define MC_CMD_SENSOR_VREG_INTERNAL_TEMP 0x227741/* enum: 0.9V voltage regulator temperature: degC */7742#define MC_CMD_SENSOR_VREG_0V9_TEMP 0x237743/* enum: 1.2V voltage regulator temperature: degC */7744#define MC_CMD_SENSOR_VREG_1V2_TEMP 0x247745/* enum: controller internal temperature sensor voltage (internal ADC): mV */7746#define MC_CMD_SENSOR_CONTROLLER_VPTAT 0x257747/* enum: controller internal temperature (internal ADC): degC */7748#define MC_CMD_SENSOR_CONTROLLER_INTERNAL_TEMP 0x267749/* enum: controller internal temperature sensor voltage (external ADC): mV */7750#define MC_CMD_SENSOR_CONTROLLER_VPTAT_EXTADC 0x277751/* enum: controller internal temperature (external ADC): degC */7752#define MC_CMD_SENSOR_CONTROLLER_INTERNAL_TEMP_EXTADC 0x287753/* enum: ambient temperature: degC */7754#define MC_CMD_SENSOR_AMBIENT_TEMP 0x297755/* enum: air flow: bool */7756#define MC_CMD_SENSOR_AIRFLOW 0x2a7757/* enum: voltage between VSS08D and VSS08D at CSR: mV */7758#define MC_CMD_SENSOR_VDD08D_VSS08D_CSR 0x2b7759/* enum: voltage between VSS08D and VSS08D at CSR (external ADC): mV */7760#define MC_CMD_SENSOR_VDD08D_VSS08D_CSR_EXTADC 0x2c7761/* enum: Hotpoint temperature: degC */7762#define MC_CMD_SENSOR_HOTPOINT_TEMP 0x2d7763/* enum: Port 0 PHY power switch over-current: bool */7764#define MC_CMD_SENSOR_PHY_POWER_PORT0 0x2e7765/* enum: Port 1 PHY power switch over-current: bool */7766#define MC_CMD_SENSOR_PHY_POWER_PORT1 0x2f7767/* enum: Mop-up microcontroller reference voltage: mV */7768#define MC_CMD_SENSOR_MUM_VCC 0x307769/* enum: 0.9v power phase A voltage: mV */7770#define MC_CMD_SENSOR_IN_0V9_A 0x317771/* enum: 0.9v power phase A current: mA */7772#define MC_CMD_SENSOR_IN_I0V9_A 0x327773/* enum: 0.9V voltage regulator phase A temperature: degC */7774#define MC_CMD_SENSOR_VREG_0V9_A_TEMP 0x337775/* enum: 0.9v power phase B voltage: mV */7776#define MC_CMD_SENSOR_IN_0V9_B 0x347777/* enum: 0.9v power phase B current: mA */7778#define MC_CMD_SENSOR_IN_I0V9_B 0x357779/* enum: 0.9V voltage regulator phase B temperature: degC */7780#define MC_CMD_SENSOR_VREG_0V9_B_TEMP 0x367781/* enum: CCOM AVREG 1v2 supply (interval ADC): mV */7782#define MC_CMD_SENSOR_CCOM_AVREG_1V2_SUPPLY 0x377783/* enum: CCOM AVREG 1v2 supply (external ADC): mV */7784#define MC_CMD_SENSOR_CCOM_AVREG_1V2_SUPPLY_EXTADC 0x387785/* enum: CCOM AVREG 1v8 supply (interval ADC): mV */7786#define MC_CMD_SENSOR_CCOM_AVREG_1V8_SUPPLY 0x397787/* enum: CCOM AVREG 1v8 supply (external ADC): mV */7788#define MC_CMD_SENSOR_CCOM_AVREG_1V8_SUPPLY_EXTADC 0x3a7789/* enum: CCOM RTS temperature: degC */7790#define MC_CMD_SENSOR_CONTROLLER_RTS 0x3b7791/* enum: Not a sensor: reserved for the next page flag */7792#define MC_CMD_SENSOR_PAGE1_NEXT 0x3f7793/* enum: controller internal temperature sensor voltage on master core7794 * (internal ADC): mV7795 */7796#define MC_CMD_SENSOR_CONTROLLER_MASTER_VPTAT 0x407797/* enum: controller internal temperature on master core (internal ADC): degC */7798#define MC_CMD_SENSOR_CONTROLLER_MASTER_INTERNAL_TEMP 0x417799/* enum: controller internal temperature sensor voltage on master core7800 * (external ADC): mV7801 */7802#define MC_CMD_SENSOR_CONTROLLER_MASTER_VPTAT_EXTADC 0x427803/* enum: controller internal temperature on master core (external ADC): degC */7804#define MC_CMD_SENSOR_CONTROLLER_MASTER_INTERNAL_TEMP_EXTADC 0x437805/* enum: controller internal temperature on slave core sensor voltage (internal7806 * ADC): mV7807 */7808#define MC_CMD_SENSOR_CONTROLLER_SLAVE_VPTAT 0x447809/* enum: controller internal temperature on slave core (internal ADC): degC */7810#define MC_CMD_SENSOR_CONTROLLER_SLAVE_INTERNAL_TEMP 0x457811/* enum: controller internal temperature on slave core sensor voltage (external7812 * ADC): mV7813 */7814#define MC_CMD_SENSOR_CONTROLLER_SLAVE_VPTAT_EXTADC 0x467815/* enum: controller internal temperature on slave core (external ADC): degC */7816#define MC_CMD_SENSOR_CONTROLLER_SLAVE_INTERNAL_TEMP_EXTADC 0x477817/* enum: Voltage supplied to the SODIMMs from their power supply: mV */7818#define MC_CMD_SENSOR_SODIMM_VOUT 0x497819/* enum: Temperature of SODIMM 0 (if installed): degC */7820#define MC_CMD_SENSOR_SODIMM_0_TEMP 0x4a7821/* enum: Temperature of SODIMM 1 (if installed): degC */7822#define MC_CMD_SENSOR_SODIMM_1_TEMP 0x4b7823/* enum: Voltage supplied to the QSFP #0 from their power supply: mV */7824#define MC_CMD_SENSOR_PHY0_VCC 0x4c7825/* enum: Voltage supplied to the QSFP #1 from their power supply: mV */7826#define MC_CMD_SENSOR_PHY1_VCC 0x4d7827/* enum: Controller die temperature (TDIODE): degC */7828#define MC_CMD_SENSOR_CONTROLLER_TDIODE_TEMP 0x4e7829/* enum: Board temperature (front): degC */7830#define MC_CMD_SENSOR_BOARD_FRONT_TEMP 0x4f7831/* enum: Board temperature (back): degC */7832#define MC_CMD_SENSOR_BOARD_BACK_TEMP 0x507833/* enum: 1.8v power current: mA */7834#define MC_CMD_SENSOR_IN_I1V8 0x517835/* enum: 2.5v power current: mA */7836#define MC_CMD_SENSOR_IN_I2V5 0x527837/* enum: 3.3v power current: mA */7838#define MC_CMD_SENSOR_IN_I3V3 0x537839/* enum: 12v power current: mA */7840#define MC_CMD_SENSOR_IN_I12V0 0x547841/* enum: 1.3v power: mV */7842#define MC_CMD_SENSOR_IN_1V3 0x557843/* enum: 1.3v power current: mA */7844#define MC_CMD_SENSOR_IN_I1V3 0x567845/* enum: Engineering sensor 1 */7846#define MC_CMD_SENSOR_ENGINEERING_1 0x577847/* enum: Engineering sensor 2 */7848#define MC_CMD_SENSOR_ENGINEERING_2 0x587849/* enum: Engineering sensor 3 */7850#define MC_CMD_SENSOR_ENGINEERING_3 0x597851/* enum: Engineering sensor 4 */7852#define MC_CMD_SENSOR_ENGINEERING_4 0x5a7853/* enum: Engineering sensor 5 */7854#define MC_CMD_SENSOR_ENGINEERING_5 0x5b7855/* enum: Engineering sensor 6 */7856#define MC_CMD_SENSOR_ENGINEERING_6 0x5c7857/* enum: Engineering sensor 7 */7858#define MC_CMD_SENSOR_ENGINEERING_7 0x5d7859/* enum: Engineering sensor 8 */7860#define MC_CMD_SENSOR_ENGINEERING_8 0x5e7861/* enum: Not a sensor: reserved for the next page flag */7862#define MC_CMD_SENSOR_PAGE2_NEXT 0x5f7863/* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF */7864#define MC_CMD_SENSOR_ENTRY_OFST 47865#define MC_CMD_SENSOR_ENTRY_LEN 87866#define MC_CMD_SENSOR_ENTRY_LO_OFST 47867#define MC_CMD_SENSOR_ENTRY_LO_LEN 47868#define MC_CMD_SENSOR_ENTRY_LO_LBN 327869#define MC_CMD_SENSOR_ENTRY_LO_WIDTH 327870#define MC_CMD_SENSOR_ENTRY_HI_OFST 87871#define MC_CMD_SENSOR_ENTRY_HI_LEN 47872#define MC_CMD_SENSOR_ENTRY_HI_LBN 647873#define MC_CMD_SENSOR_ENTRY_HI_WIDTH 327874#define MC_CMD_SENSOR_ENTRY_MINNUM 07875#define MC_CMD_SENSOR_ENTRY_MAXNUM 317876#define MC_CMD_SENSOR_ENTRY_MAXNUM_MCDI2 1277877 7878/* MC_CMD_SENSOR_INFO_EXT_OUT msgresponse */7879#define MC_CMD_SENSOR_INFO_EXT_OUT_LENMIN 47880#define MC_CMD_SENSOR_INFO_EXT_OUT_LENMAX 2527881#define MC_CMD_SENSOR_INFO_EXT_OUT_LENMAX_MCDI2 10207882#define MC_CMD_SENSOR_INFO_EXT_OUT_LEN(num) (4+8*(num))7883#define MC_CMD_SENSOR_INFO_EXT_OUT_MC_CMD_SENSOR_ENTRY_NUM(len) (((len)-4)/8)7884#define MC_CMD_SENSOR_INFO_EXT_OUT_MASK_OFST 07885#define MC_CMD_SENSOR_INFO_EXT_OUT_MASK_LEN 47886/* Enum values, see field(s): */7887/* MC_CMD_SENSOR_INFO_OUT */7888#define MC_CMD_SENSOR_INFO_EXT_OUT_NEXT_PAGE_OFST 07889#define MC_CMD_SENSOR_INFO_EXT_OUT_NEXT_PAGE_LBN 317890#define MC_CMD_SENSOR_INFO_EXT_OUT_NEXT_PAGE_WIDTH 17891/* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF */7892/* MC_CMD_SENSOR_ENTRY_OFST 4 */7893/* MC_CMD_SENSOR_ENTRY_LEN 8 */7894/* MC_CMD_SENSOR_ENTRY_LO_OFST 4 */7895/* MC_CMD_SENSOR_ENTRY_LO_LEN 4 */7896/* MC_CMD_SENSOR_ENTRY_LO_LBN 32 */7897/* MC_CMD_SENSOR_ENTRY_LO_WIDTH 32 */7898/* MC_CMD_SENSOR_ENTRY_HI_OFST 8 */7899/* MC_CMD_SENSOR_ENTRY_HI_LEN 4 */7900/* MC_CMD_SENSOR_ENTRY_HI_LBN 64 */7901/* MC_CMD_SENSOR_ENTRY_HI_WIDTH 32 */7902/* MC_CMD_SENSOR_ENTRY_MINNUM 0 */7903/* MC_CMD_SENSOR_ENTRY_MAXNUM 31 */7904/* MC_CMD_SENSOR_ENTRY_MAXNUM_MCDI2 127 */7905 7906/* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF structuredef */7907#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_LEN 87908#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_OFST 07909#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_LEN 27910#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_LBN 07911#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_WIDTH 167912#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_OFST 27913#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_LEN 27914#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_LBN 167915#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_WIDTH 167916#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_OFST 47917#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_LEN 27918#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_LBN 327919#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_WIDTH 167920#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_OFST 67921#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_LEN 27922#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_LBN 487923#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_WIDTH 167924 7925 7926/***********************************/7927/* MC_CMD_READ_SENSORS7928 * Returns the current reading from each sensor. DMAs an array of sensor7929 * readings, in order of sensor type (but without gaps for unimplemented7930 * sensors), into host memory. Each array element is a7931 * MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF dword.7932 *7933 * If the request does not contain the LENGTH field then only sensors 0 to 307934 * are reported, to avoid DMA buffer overflow in older host software. If the7935 * sensor reading require more space than the LENGTH allows, then return7936 * EINVAL.7937 *7938 * The MC will send a SENSOREVT event every time any sensor changes state. The7939 * driver is responsible for ensuring that it doesn't miss any events. The7940 * board will function normally if all sensors are in STATE_OK or7941 * STATE_WARNING. Otherwise the board should not be expected to function.7942 */7943#define MC_CMD_READ_SENSORS 0x427944#undef MC_CMD_0x42_PRIVILEGE_CTG7945 7946#define MC_CMD_0x42_PRIVILEGE_CTG SRIOV_CTG_GENERAL7947 7948/* MC_CMD_READ_SENSORS_IN msgrequest */7949#define MC_CMD_READ_SENSORS_IN_LEN 87950/* DMA address of host buffer for sensor readings (must be 4Kbyte aligned).7951 *7952 * If the address is 0xffffffffffffffff send the readings in the response (used7953 * by cmdclient).7954 */7955#define MC_CMD_READ_SENSORS_IN_DMA_ADDR_OFST 07956#define MC_CMD_READ_SENSORS_IN_DMA_ADDR_LEN 87957#define MC_CMD_READ_SENSORS_IN_DMA_ADDR_LO_OFST 07958#define MC_CMD_READ_SENSORS_IN_DMA_ADDR_LO_LEN 47959#define MC_CMD_READ_SENSORS_IN_DMA_ADDR_LO_LBN 07960#define MC_CMD_READ_SENSORS_IN_DMA_ADDR_LO_WIDTH 327961#define MC_CMD_READ_SENSORS_IN_DMA_ADDR_HI_OFST 47962#define MC_CMD_READ_SENSORS_IN_DMA_ADDR_HI_LEN 47963#define MC_CMD_READ_SENSORS_IN_DMA_ADDR_HI_LBN 327964#define MC_CMD_READ_SENSORS_IN_DMA_ADDR_HI_WIDTH 327965 7966/* MC_CMD_READ_SENSORS_EXT_IN msgrequest */7967#define MC_CMD_READ_SENSORS_EXT_IN_LEN 127968/* DMA address of host buffer for sensor readings (must be 4Kbyte aligned).7969 *7970 * If the address is 0xffffffffffffffff send the readings in the response (used7971 * by cmdclient).7972 */7973#define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_OFST 07974#define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LEN 87975#define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LO_OFST 07976#define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LO_LEN 47977#define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LO_LBN 07978#define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LO_WIDTH 327979#define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_HI_OFST 47980#define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_HI_LEN 47981#define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_HI_LBN 327982#define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_HI_WIDTH 327983/* Size in bytes of host buffer. */7984#define MC_CMD_READ_SENSORS_EXT_IN_LENGTH_OFST 87985#define MC_CMD_READ_SENSORS_EXT_IN_LENGTH_LEN 47986 7987/* MC_CMD_READ_SENSORS_EXT_IN_V2 msgrequest */7988#define MC_CMD_READ_SENSORS_EXT_IN_V2_LEN 167989/* DMA address of host buffer for sensor readings (must be 4Kbyte aligned).7990 *7991 * If the address is 0xffffffffffffffff send the readings in the response (used7992 * by cmdclient).7993 */7994#define MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_OFST 07995#define MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_LEN 87996#define MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_LO_OFST 07997#define MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_LO_LEN 47998#define MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_LO_LBN 07999#define MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_LO_WIDTH 328000#define MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_HI_OFST 48001#define MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_HI_LEN 48002#define MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_HI_LBN 328003#define MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_HI_WIDTH 328004/* Size in bytes of host buffer. */8005#define MC_CMD_READ_SENSORS_EXT_IN_V2_LENGTH_OFST 88006#define MC_CMD_READ_SENSORS_EXT_IN_V2_LENGTH_LEN 48007/* Flags controlling information retrieved */8008#define MC_CMD_READ_SENSORS_EXT_IN_V2_FLAGS_OFST 128009#define MC_CMD_READ_SENSORS_EXT_IN_V2_FLAGS_LEN 48010#define MC_CMD_READ_SENSORS_EXT_IN_V2_ENGINEERING_OFST 128011#define MC_CMD_READ_SENSORS_EXT_IN_V2_ENGINEERING_LBN 08012#define MC_CMD_READ_SENSORS_EXT_IN_V2_ENGINEERING_WIDTH 18013 8014/* MC_CMD_READ_SENSORS_OUT msgresponse */8015#define MC_CMD_READ_SENSORS_OUT_LEN 08016 8017/* MC_CMD_READ_SENSORS_EXT_OUT msgresponse */8018#define MC_CMD_READ_SENSORS_EXT_OUT_LEN 08019 8020/* MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF structuredef */8021#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_LEN 48022#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_OFST 08023#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_LEN 28024#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_LBN 08025#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_WIDTH 168026#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_OFST 28027#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_LEN 18028/* enum: Ok. */8029#define MC_CMD_SENSOR_STATE_OK 0x08030/* enum: Breached warning threshold. */8031#define MC_CMD_SENSOR_STATE_WARNING 0x18032/* enum: Breached fatal threshold. */8033#define MC_CMD_SENSOR_STATE_FATAL 0x28034/* enum: Fault with sensor. */8035#define MC_CMD_SENSOR_STATE_BROKEN 0x38036/* enum: Sensor is working but does not currently have a reading. */8037#define MC_CMD_SENSOR_STATE_NO_READING 0x48038/* enum: Sensor initialisation failed. */8039#define MC_CMD_SENSOR_STATE_INIT_FAILED 0x58040#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_LBN 168041#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_WIDTH 88042#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_OFST 38043#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_LEN 18044/* Enum values, see field(s): */8045/* MC_CMD_SENSOR_INFO/MC_CMD_SENSOR_INFO_OUT/MASK */8046#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_LBN 248047#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_WIDTH 88048 8049 8050/***********************************/8051/* MC_CMD_GET_PHY_STATE8052 * Report current state of PHY. A 'zombie' PHY is a PHY that has failed to boot8053 * (e.g. due to missing or corrupted firmware). Locks required: None. Return8054 * code: 08055 */8056#define MC_CMD_GET_PHY_STATE 0x438057#undef MC_CMD_0x43_PRIVILEGE_CTG8058 8059#define MC_CMD_0x43_PRIVILEGE_CTG SRIOV_CTG_GENERAL8060 8061/* MC_CMD_GET_PHY_STATE_IN msgrequest */8062#define MC_CMD_GET_PHY_STATE_IN_LEN 08063 8064/* MC_CMD_GET_PHY_STATE_OUT msgresponse */8065#define MC_CMD_GET_PHY_STATE_OUT_LEN 48066#define MC_CMD_GET_PHY_STATE_OUT_STATE_OFST 08067#define MC_CMD_GET_PHY_STATE_OUT_STATE_LEN 48068/* enum: Ok. */8069#define MC_CMD_PHY_STATE_OK 0x18070/* enum: Faulty. */8071#define MC_CMD_PHY_STATE_ZOMBIE 0x28072 8073 8074/***********************************/8075/* MC_CMD_SETUP_8021QBB8076 * 802.1Qbb control. 8 Tx queues that map to priorities 0 - 7. Use all 1s to8077 * disable 802.Qbb for a given priority.8078 */8079#define MC_CMD_SETUP_8021QBB 0x448080 8081/* MC_CMD_SETUP_8021QBB_IN msgrequest */8082#define MC_CMD_SETUP_8021QBB_IN_LEN 328083#define MC_CMD_SETUP_8021QBB_IN_TXQS_OFST 08084#define MC_CMD_SETUP_8021QBB_IN_TXQS_LEN 328085 8086/* MC_CMD_SETUP_8021QBB_OUT msgresponse */8087#define MC_CMD_SETUP_8021QBB_OUT_LEN 08088 8089 8090/***********************************/8091/* MC_CMD_WOL_FILTER_GET8092 * Retrieve ID of any WoL filters. Locks required: None. Returns: 0, ENOSYS8093 */8094#define MC_CMD_WOL_FILTER_GET 0x458095#undef MC_CMD_0x45_PRIVILEGE_CTG8096 8097#define MC_CMD_0x45_PRIVILEGE_CTG SRIOV_CTG_LINK8098 8099/* MC_CMD_WOL_FILTER_GET_IN msgrequest */8100#define MC_CMD_WOL_FILTER_GET_IN_LEN 08101 8102/* MC_CMD_WOL_FILTER_GET_OUT msgresponse */8103#define MC_CMD_WOL_FILTER_GET_OUT_LEN 48104#define MC_CMD_WOL_FILTER_GET_OUT_FILTER_ID_OFST 08105#define MC_CMD_WOL_FILTER_GET_OUT_FILTER_ID_LEN 48106 8107 8108/***********************************/8109/* MC_CMD_ADD_LIGHTSOUT_OFFLOAD8110 * Add a protocol offload to NIC for lights-out state. Locks required: None.8111 * Returns: 0, ENOSYS8112 */8113#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD 0x468114#undef MC_CMD_0x46_PRIVILEGE_CTG8115 8116#define MC_CMD_0x46_PRIVILEGE_CTG SRIOV_CTG_LINK8117 8118/* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN msgrequest */8119#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LENMIN 88120#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LENMAX 2528121#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LENMAX_MCDI2 10208122#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LEN(num) (4+4*(num))8123#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_NUM(len) (((len)-4)/4)8124#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 08125#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_LEN 48126#define MC_CMD_LIGHTSOUT_OFFLOAD_PROTOCOL_ARP 0x1 /* enum */8127#define MC_CMD_LIGHTSOUT_OFFLOAD_PROTOCOL_NS 0x2 /* enum */8128#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_OFST 48129#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_LEN 48130#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_MINNUM 18131#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_MAXNUM 628132#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_MAXNUM_MCDI2 2548133 8134/* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP msgrequest */8135#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_LEN 148136/* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 */8137/* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_LEN 4 */8138#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_MAC_OFST 48139#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_MAC_LEN 68140#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_IP_OFST 108141#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_IP_LEN 48142 8143/* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS msgrequest */8144#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_LEN 428145/* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 */8146/* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_LEN 4 */8147#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_MAC_OFST 48148#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_MAC_LEN 68149#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_SNIPV6_OFST 108150#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_SNIPV6_LEN 168151#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_IPV6_OFST 268152#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_IPV6_LEN 168153 8154/* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT msgresponse */8155#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_LEN 48156#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_FILTER_ID_OFST 08157#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_FILTER_ID_LEN 48158 8159 8160/***********************************/8161/* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD8162 * Remove a protocol offload from NIC for lights-out state. Locks required:8163 * None. Returns: 0, ENOSYS8164 */8165#define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD 0x478166#undef MC_CMD_0x47_PRIVILEGE_CTG8167 8168#define MC_CMD_0x47_PRIVILEGE_CTG SRIOV_CTG_LINK8169 8170/* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN msgrequest */8171#define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_LEN 88172#define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 08173#define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_LEN 48174#define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_FILTER_ID_OFST 48175#define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_FILTER_ID_LEN 48176 8177/* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_OUT msgresponse */8178#define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_OUT_LEN 08179 8180 8181/***********************************/8182/* MC_CMD_MAC_RESET_RESTORE8183 * Restore MAC after block reset. Locks required: None. Returns: 0.8184 */8185#define MC_CMD_MAC_RESET_RESTORE 0x488186 8187/* MC_CMD_MAC_RESET_RESTORE_IN msgrequest */8188#define MC_CMD_MAC_RESET_RESTORE_IN_LEN 08189 8190/* MC_CMD_MAC_RESET_RESTORE_OUT msgresponse */8191#define MC_CMD_MAC_RESET_RESTORE_OUT_LEN 08192 8193 8194/***********************************/8195/* MC_CMD_TESTASSERT8196 * Deliberately trigger an assert-detonation in the firmware for testing8197 * purposes (i.e. to allow tests that the driver copes gracefully). Locks8198 * required: None Returns: 08199 */8200#define MC_CMD_TESTASSERT 0x498201#undef MC_CMD_0x49_PRIVILEGE_CTG8202 8203#define MC_CMD_0x49_PRIVILEGE_CTG SRIOV_CTG_ADMIN8204 8205/* MC_CMD_TESTASSERT_IN msgrequest */8206#define MC_CMD_TESTASSERT_IN_LEN 08207 8208/* MC_CMD_TESTASSERT_OUT msgresponse */8209#define MC_CMD_TESTASSERT_OUT_LEN 08210 8211/* MC_CMD_TESTASSERT_V2_IN msgrequest */8212#define MC_CMD_TESTASSERT_V2_IN_LEN 48213/* How to provoke the assertion */8214#define MC_CMD_TESTASSERT_V2_IN_TYPE_OFST 08215#define MC_CMD_TESTASSERT_V2_IN_TYPE_LEN 48216/* enum: Assert using the FAIL_ASSERTION_WITH_USEFUL_VALUES macro. Unless8217 * you're testing firmware, this is what you want.8218 */8219#define MC_CMD_TESTASSERT_V2_IN_FAIL_ASSERTION_WITH_USEFUL_VALUES 0x08220/* enum: Assert using assert(0); */8221#define MC_CMD_TESTASSERT_V2_IN_ASSERT_FALSE 0x18222/* enum: Deliberately trigger a watchdog */8223#define MC_CMD_TESTASSERT_V2_IN_WATCHDOG 0x28224/* enum: Deliberately trigger a trap by loading from an invalid address */8225#define MC_CMD_TESTASSERT_V2_IN_LOAD_TRAP 0x38226/* enum: Deliberately trigger a trap by storing to an invalid address */8227#define MC_CMD_TESTASSERT_V2_IN_STORE_TRAP 0x48228/* enum: Jump to an invalid address */8229#define MC_CMD_TESTASSERT_V2_IN_JUMP_TRAP 0x58230 8231/* MC_CMD_TESTASSERT_V2_OUT msgresponse */8232#define MC_CMD_TESTASSERT_V2_OUT_LEN 08233 8234 8235/***********************************/8236/* MC_CMD_WORKAROUND8237 * Enable/Disable a given workaround. The mcfw will return EINVAL if it doesn't8238 * understand the given workaround number - which should not be treated as a8239 * hard error by client code. This op does not imply any semantics about each8240 * workaround, that's between the driver and the mcfw on a per-workaround8241 * basis. Locks required: None. Returns: 0, EINVAL .8242 */8243#define MC_CMD_WORKAROUND 0x4a8244#undef MC_CMD_0x4a_PRIVILEGE_CTG8245 8246#define MC_CMD_0x4a_PRIVILEGE_CTG SRIOV_CTG_ADMIN8247 8248/* MC_CMD_WORKAROUND_IN msgrequest */8249#define MC_CMD_WORKAROUND_IN_LEN 88250/* The enums here must correspond with those in MC_CMD_GET_WORKAROUND. */8251#define MC_CMD_WORKAROUND_IN_TYPE_OFST 08252#define MC_CMD_WORKAROUND_IN_TYPE_LEN 48253/* enum: Bug 17230 work around. */8254#define MC_CMD_WORKAROUND_BUG17230 0x18255/* enum: Bug 35388 work around (unsafe EVQ writes). */8256#define MC_CMD_WORKAROUND_BUG35388 0x28257/* enum: Bug35017 workaround (A64 tables must be identity map) */8258#define MC_CMD_WORKAROUND_BUG35017 0x38259/* enum: Bug 41750 present (MC_CMD_TRIGGER_INTERRUPT won't work) */8260#define MC_CMD_WORKAROUND_BUG41750 0x48261/* enum: Bug 42008 present (Interrupts can overtake associated events). Caution8262 * - before adding code that queries this workaround, remember that there's8263 * released Monza firmware that doesn't understand MC_CMD_WORKAROUND_BUG42008,8264 * and will hence (incorrectly) report that the bug doesn't exist.8265 */8266#define MC_CMD_WORKAROUND_BUG42008 0x58267/* enum: Bug 26807 features present in firmware (multicast filter chaining)8268 * This feature cannot be turned on/off while there are any filters already8269 * present. The behaviour in such case depends on the acting client's privilege8270 * level. If the client has the admin privilege, then all functions that have8271 * filters installed will be FLRed and the FLR_DONE flag will be set. Otherwise8272 * the command will fail with MC_CMD_ERR_FILTERS_PRESENT.8273 */8274#define MC_CMD_WORKAROUND_BUG26807 0x68275/* enum: Bug 61265 work around (broken EVQ TMR writes). */8276#define MC_CMD_WORKAROUND_BUG61265 0x78277/* 0 = disable the workaround indicated by TYPE; any non-zero value = enable8278 * the workaround8279 */8280#define MC_CMD_WORKAROUND_IN_ENABLED_OFST 48281#define MC_CMD_WORKAROUND_IN_ENABLED_LEN 48282 8283/* MC_CMD_WORKAROUND_OUT msgresponse */8284#define MC_CMD_WORKAROUND_OUT_LEN 08285 8286/* MC_CMD_WORKAROUND_EXT_OUT msgresponse: This response format will be used8287 * when (TYPE == MC_CMD_WORKAROUND_BUG26807)8288 */8289#define MC_CMD_WORKAROUND_EXT_OUT_LEN 48290#define MC_CMD_WORKAROUND_EXT_OUT_FLAGS_OFST 08291#define MC_CMD_WORKAROUND_EXT_OUT_FLAGS_LEN 48292#define MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_OFST 08293#define MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN 08294#define MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_WIDTH 18295 8296 8297/***********************************/8298/* MC_CMD_GET_PHY_MEDIA_INFO8299 * Read media-specific data from PHY (e.g. SFP/SFP+ module ID information for8300 * SFP+ PHYs). The "media type" can be found via GET_PHY_CFG8301 * (GET_PHY_CFG_OUT_MEDIA_TYPE); the valid "page number" input values, and the8302 * output data, are interpreted on a per-type basis. For SFP+, PAGE=0 or 18303 * returns a 128-byte block read from module I2C address 0xA0 offset 0 or 0x80.8304 * For QSFP, PAGE=-1 is the lower (unbanked) page. PAGE=2 is the EEPROM and8305 * PAGE=3 is the module limits. For DSFP, module addressing requires a8306 * "BANK:PAGE". Not every bank has the same number of pages. See the Common8307 * Management Interface Specification (CMIS) for further details. A BANK:PAGE8308 * of "0xffff:0xffff" retrieves the lower (unbanked) page. Locks required -8309 * None. Return code - 0.8310 */8311#define MC_CMD_GET_PHY_MEDIA_INFO 0x4b8312#undef MC_CMD_0x4b_PRIVILEGE_CTG8313 8314#define MC_CMD_0x4b_PRIVILEGE_CTG SRIOV_CTG_ADMIN8315 8316/* MC_CMD_GET_PHY_MEDIA_INFO_IN msgrequest */8317#define MC_CMD_GET_PHY_MEDIA_INFO_IN_LEN 48318#define MC_CMD_GET_PHY_MEDIA_INFO_IN_PAGE_OFST 08319#define MC_CMD_GET_PHY_MEDIA_INFO_IN_PAGE_LEN 48320#define MC_CMD_GET_PHY_MEDIA_INFO_IN_DSFP_PAGE_OFST 08321#define MC_CMD_GET_PHY_MEDIA_INFO_IN_DSFP_PAGE_LBN 08322#define MC_CMD_GET_PHY_MEDIA_INFO_IN_DSFP_PAGE_WIDTH 168323#define MC_CMD_GET_PHY_MEDIA_INFO_IN_DSFP_BANK_OFST 08324#define MC_CMD_GET_PHY_MEDIA_INFO_IN_DSFP_BANK_LBN 168325#define MC_CMD_GET_PHY_MEDIA_INFO_IN_DSFP_BANK_WIDTH 168326 8327/* MC_CMD_GET_PHY_MEDIA_INFO_OUT msgresponse */8328#define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LENMIN 58329#define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LENMAX 2528330#define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LENMAX_MCDI2 10208331#define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LEN(num) (4+1*(num))8332#define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_NUM(len) (((len)-4)/1)8333/* in bytes */8334#define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATALEN_OFST 08335#define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATALEN_LEN 48336#define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_OFST 48337#define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_LEN 18338#define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_MINNUM 18339#define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_MAXNUM 2488340#define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_MAXNUM_MCDI2 10168341 8342 8343/***********************************/8344/* MC_CMD_NVRAM_TEST8345 * Test a particular NVRAM partition for valid contents (where "valid" depends8346 * on the type of partition).8347 */8348#define MC_CMD_NVRAM_TEST 0x4c8349#undef MC_CMD_0x4c_PRIVILEGE_CTG8350 8351#define MC_CMD_0x4c_PRIVILEGE_CTG SRIOV_CTG_ADMIN8352 8353/* MC_CMD_NVRAM_TEST_IN msgrequest */8354#define MC_CMD_NVRAM_TEST_IN_LEN 48355#define MC_CMD_NVRAM_TEST_IN_TYPE_OFST 08356#define MC_CMD_NVRAM_TEST_IN_TYPE_LEN 48357/* Enum values, see field(s): */8358/* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */8359 8360/* MC_CMD_NVRAM_TEST_OUT msgresponse */8361#define MC_CMD_NVRAM_TEST_OUT_LEN 48362#define MC_CMD_NVRAM_TEST_OUT_RESULT_OFST 08363#define MC_CMD_NVRAM_TEST_OUT_RESULT_LEN 48364/* enum: Passed. */8365#define MC_CMD_NVRAM_TEST_PASS 0x08366/* enum: Failed. */8367#define MC_CMD_NVRAM_TEST_FAIL 0x18368/* enum: Not supported. */8369#define MC_CMD_NVRAM_TEST_NOTSUPP 0x28370 8371 8372/***********************************/8373/* MC_CMD_MRSFP_TWEAK8374 * Read status and/or set parameters for the 'mrsfp' driver in mr_rusty builds.8375 * I2C I/O expander bits are always read; if equaliser parameters are supplied,8376 * they are configured first. Locks required: None. Return code: 0, EINVAL.8377 */8378#define MC_CMD_MRSFP_TWEAK 0x4d8379 8380/* MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG msgrequest */8381#define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_LEN 168382/* 0-6 low->high de-emph. */8383#define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_LEVEL_OFST 08384#define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_LEVEL_LEN 48385/* 0-8 low->high ref.V */8386#define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_DT_CFG_OFST 48387#define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_DT_CFG_LEN 48388/* 0-8 0-8 low->high boost */8389#define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_BOOST_OFST 88390#define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_BOOST_LEN 48391/* 0-8 low->high ref.V */8392#define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_DT_CFG_OFST 128393#define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_DT_CFG_LEN 48394 8395/* MC_CMD_MRSFP_TWEAK_IN_READ_ONLY msgrequest */8396#define MC_CMD_MRSFP_TWEAK_IN_READ_ONLY_LEN 08397 8398/* MC_CMD_MRSFP_TWEAK_OUT msgresponse */8399#define MC_CMD_MRSFP_TWEAK_OUT_LEN 128400/* input bits */8401#define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_INPUTS_OFST 08402#define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_INPUTS_LEN 48403/* output bits */8404#define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_OUTPUTS_OFST 48405#define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_OUTPUTS_LEN 48406/* direction */8407#define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_OFST 88408#define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_LEN 48409/* enum: Out. */8410#define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_OUT 0x08411/* enum: In. */8412#define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_IN 0x18413 8414 8415/***********************************/8416/* MC_CMD_SENSOR_SET_LIMS8417 * Adjusts the sensor limits. This is a warranty-voiding operation. Returns:8418 * ENOENT if the sensor specified does not exist, EINVAL if the limits are out8419 * of range.8420 */8421#define MC_CMD_SENSOR_SET_LIMS 0x4e8422#undef MC_CMD_0x4e_PRIVILEGE_CTG8423 8424#define MC_CMD_0x4e_PRIVILEGE_CTG SRIOV_CTG_INSECURE8425 8426/* MC_CMD_SENSOR_SET_LIMS_IN msgrequest */8427#define MC_CMD_SENSOR_SET_LIMS_IN_LEN 208428#define MC_CMD_SENSOR_SET_LIMS_IN_SENSOR_OFST 08429#define MC_CMD_SENSOR_SET_LIMS_IN_SENSOR_LEN 48430/* Enum values, see field(s): */8431/* MC_CMD_SENSOR_INFO/MC_CMD_SENSOR_INFO_OUT/MASK */8432/* interpretation is is sensor-specific. */8433#define MC_CMD_SENSOR_SET_LIMS_IN_LOW0_OFST 48434#define MC_CMD_SENSOR_SET_LIMS_IN_LOW0_LEN 48435/* interpretation is is sensor-specific. */8436#define MC_CMD_SENSOR_SET_LIMS_IN_HI0_OFST 88437#define MC_CMD_SENSOR_SET_LIMS_IN_HI0_LEN 48438/* interpretation is is sensor-specific. */8439#define MC_CMD_SENSOR_SET_LIMS_IN_LOW1_OFST 128440#define MC_CMD_SENSOR_SET_LIMS_IN_LOW1_LEN 48441/* interpretation is is sensor-specific. */8442#define MC_CMD_SENSOR_SET_LIMS_IN_HI1_OFST 168443#define MC_CMD_SENSOR_SET_LIMS_IN_HI1_LEN 48444 8445/* MC_CMD_SENSOR_SET_LIMS_OUT msgresponse */8446#define MC_CMD_SENSOR_SET_LIMS_OUT_LEN 08447 8448 8449/***********************************/8450/* MC_CMD_GET_RESOURCE_LIMITS8451 */8452#define MC_CMD_GET_RESOURCE_LIMITS 0x4f8453 8454/* MC_CMD_GET_RESOURCE_LIMITS_IN msgrequest */8455#define MC_CMD_GET_RESOURCE_LIMITS_IN_LEN 08456 8457/* MC_CMD_GET_RESOURCE_LIMITS_OUT msgresponse */8458#define MC_CMD_GET_RESOURCE_LIMITS_OUT_LEN 168459#define MC_CMD_GET_RESOURCE_LIMITS_OUT_BUFTBL_OFST 08460#define MC_CMD_GET_RESOURCE_LIMITS_OUT_BUFTBL_LEN 48461#define MC_CMD_GET_RESOURCE_LIMITS_OUT_EVQ_OFST 48462#define MC_CMD_GET_RESOURCE_LIMITS_OUT_EVQ_LEN 48463#define MC_CMD_GET_RESOURCE_LIMITS_OUT_RXQ_OFST 88464#define MC_CMD_GET_RESOURCE_LIMITS_OUT_RXQ_LEN 48465#define MC_CMD_GET_RESOURCE_LIMITS_OUT_TXQ_OFST 128466#define MC_CMD_GET_RESOURCE_LIMITS_OUT_TXQ_LEN 48467 8468 8469/***********************************/8470/* MC_CMD_NVRAM_PARTITIONS8471 * Reads the list of available virtual NVRAM partition types. Locks required:8472 * none. Returns: 0, EINVAL (bad type).8473 */8474#define MC_CMD_NVRAM_PARTITIONS 0x518475#undef MC_CMD_0x51_PRIVILEGE_CTG8476 8477#define MC_CMD_0x51_PRIVILEGE_CTG SRIOV_CTG_ADMIN8478 8479/* MC_CMD_NVRAM_PARTITIONS_IN msgrequest */8480#define MC_CMD_NVRAM_PARTITIONS_IN_LEN 08481 8482/* MC_CMD_NVRAM_PARTITIONS_OUT msgresponse */8483#define MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN 48484#define MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX 2528485#define MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX_MCDI2 10208486#define MC_CMD_NVRAM_PARTITIONS_OUT_LEN(num) (4+4*(num))8487#define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_NUM(len) (((len)-4)/4)8488/* total number of partitions */8489#define MC_CMD_NVRAM_PARTITIONS_OUT_NUM_PARTITIONS_OFST 08490#define MC_CMD_NVRAM_PARTITIONS_OUT_NUM_PARTITIONS_LEN 48491/* type ID code for each of NUM_PARTITIONS partitions */8492#define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_OFST 48493#define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_LEN 48494#define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_MINNUM 08495#define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_MAXNUM 628496#define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_MAXNUM_MCDI2 2548497 8498 8499/***********************************/8500/* MC_CMD_NVRAM_METADATA8501 * Reads soft metadata for a virtual NVRAM partition type. Locks required:8502 * none. Returns: 0, EINVAL (bad type).8503 */8504#define MC_CMD_NVRAM_METADATA 0x528505#undef MC_CMD_0x52_PRIVILEGE_CTG8506 8507#define MC_CMD_0x52_PRIVILEGE_CTG SRIOV_CTG_ADMIN8508 8509/* MC_CMD_NVRAM_METADATA_IN msgrequest */8510#define MC_CMD_NVRAM_METADATA_IN_LEN 48511/* Partition type ID code */8512#define MC_CMD_NVRAM_METADATA_IN_TYPE_OFST 08513#define MC_CMD_NVRAM_METADATA_IN_TYPE_LEN 48514 8515/* MC_CMD_NVRAM_METADATA_OUT msgresponse */8516#define MC_CMD_NVRAM_METADATA_OUT_LENMIN 208517#define MC_CMD_NVRAM_METADATA_OUT_LENMAX 2528518#define MC_CMD_NVRAM_METADATA_OUT_LENMAX_MCDI2 10208519#define MC_CMD_NVRAM_METADATA_OUT_LEN(num) (20+1*(num))8520#define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_NUM(len) (((len)-20)/1)8521/* Partition type ID code */8522#define MC_CMD_NVRAM_METADATA_OUT_TYPE_OFST 08523#define MC_CMD_NVRAM_METADATA_OUT_TYPE_LEN 48524#define MC_CMD_NVRAM_METADATA_OUT_FLAGS_OFST 48525#define MC_CMD_NVRAM_METADATA_OUT_FLAGS_LEN 48526#define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_OFST 48527#define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN 08528#define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_WIDTH 18529#define MC_CMD_NVRAM_METADATA_OUT_VERSION_VALID_OFST 48530#define MC_CMD_NVRAM_METADATA_OUT_VERSION_VALID_LBN 18531#define MC_CMD_NVRAM_METADATA_OUT_VERSION_VALID_WIDTH 18532#define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_VALID_OFST 48533#define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_VALID_LBN 28534#define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_VALID_WIDTH 18535/* Subtype ID code for content of this partition */8536#define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_OFST 88537#define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_LEN 48538/* 1st component of W.X.Y.Z version number for content of this partition */8539#define MC_CMD_NVRAM_METADATA_OUT_VERSION_W_OFST 128540#define MC_CMD_NVRAM_METADATA_OUT_VERSION_W_LEN 28541/* 2nd component of W.X.Y.Z version number for content of this partition */8542#define MC_CMD_NVRAM_METADATA_OUT_VERSION_X_OFST 148543#define MC_CMD_NVRAM_METADATA_OUT_VERSION_X_LEN 28544/* 3rd component of W.X.Y.Z version number for content of this partition */8545#define MC_CMD_NVRAM_METADATA_OUT_VERSION_Y_OFST 168546#define MC_CMD_NVRAM_METADATA_OUT_VERSION_Y_LEN 28547/* 4th component of W.X.Y.Z version number for content of this partition */8548#define MC_CMD_NVRAM_METADATA_OUT_VERSION_Z_OFST 188549#define MC_CMD_NVRAM_METADATA_OUT_VERSION_Z_LEN 28550/* Zero-terminated string describing the content of this partition */8551#define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_OFST 208552#define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_LEN 18553#define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_MINNUM 08554#define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_MAXNUM 2328555#define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_MAXNUM_MCDI2 10008556 8557 8558/***********************************/8559/* MC_CMD_GET_MAC_ADDRESSES8560 * Returns the base MAC, count and stride for the requesting function8561 */8562#define MC_CMD_GET_MAC_ADDRESSES 0x558563#undef MC_CMD_0x55_PRIVILEGE_CTG8564 8565#define MC_CMD_0x55_PRIVILEGE_CTG SRIOV_CTG_GENERAL8566 8567/* MC_CMD_GET_MAC_ADDRESSES_IN msgrequest */8568#define MC_CMD_GET_MAC_ADDRESSES_IN_LEN 08569 8570/* MC_CMD_GET_MAC_ADDRESSES_OUT msgresponse */8571#define MC_CMD_GET_MAC_ADDRESSES_OUT_LEN 168572/* Base MAC address */8573#define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE_OFST 08574#define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE_LEN 68575/* Padding */8576#define MC_CMD_GET_MAC_ADDRESSES_OUT_RESERVED_OFST 68577#define MC_CMD_GET_MAC_ADDRESSES_OUT_RESERVED_LEN 28578/* Number of allocated MAC addresses */8579#define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_COUNT_OFST 88580#define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_COUNT_LEN 48581/* Spacing of allocated MAC addresses */8582#define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_STRIDE_OFST 128583#define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_STRIDE_LEN 48584 8585 8586/***********************************/8587/* MC_CMD_CLP8588 * Perform a CLP related operation, see SF-110495-PS for details of CLP8589 * processing. This command has been extended to accomodate the requirements of8590 * different manufacturers which are to be found in SF-119187-TC, SF-119186-TC,8591 * SF-120509-TC and SF-117282-PS.8592 */8593#define MC_CMD_CLP 0x568594#undef MC_CMD_0x56_PRIVILEGE_CTG8595 8596#define MC_CMD_0x56_PRIVILEGE_CTG SRIOV_CTG_ADMIN8597 8598/* MC_CMD_CLP_IN msgrequest */8599#define MC_CMD_CLP_IN_LEN 48600/* Sub operation */8601#define MC_CMD_CLP_IN_OP_OFST 08602#define MC_CMD_CLP_IN_OP_LEN 48603/* enum: Return to factory default settings */8604#define MC_CMD_CLP_OP_DEFAULT 0x18605/* enum: Set MAC address */8606#define MC_CMD_CLP_OP_SET_MAC 0x28607/* enum: Get MAC address */8608#define MC_CMD_CLP_OP_GET_MAC 0x38609/* enum: Set UEFI/GPXE boot mode */8610#define MC_CMD_CLP_OP_SET_BOOT 0x48611/* enum: Get UEFI/GPXE boot mode */8612#define MC_CMD_CLP_OP_GET_BOOT 0x58613 8614/* MC_CMD_CLP_OUT msgresponse */8615#define MC_CMD_CLP_OUT_LEN 08616 8617/* MC_CMD_CLP_IN_DEFAULT msgrequest */8618#define MC_CMD_CLP_IN_DEFAULT_LEN 48619/* MC_CMD_CLP_IN_OP_OFST 0 */8620/* MC_CMD_CLP_IN_OP_LEN 4 */8621 8622/* MC_CMD_CLP_OUT_DEFAULT msgresponse */8623#define MC_CMD_CLP_OUT_DEFAULT_LEN 08624 8625/* MC_CMD_CLP_IN_SET_MAC msgrequest */8626#define MC_CMD_CLP_IN_SET_MAC_LEN 128627/* MC_CMD_CLP_IN_OP_OFST 0 */8628/* MC_CMD_CLP_IN_OP_LEN 4 */8629/* The MAC address assigned to port. A zero MAC address of 00:00:00:00:00:008630 * restores the permanent (factory-programmed) MAC address associated with the8631 * port. A non-zero MAC address persists until a PCIe reset or a power cycle.8632 */8633#define MC_CMD_CLP_IN_SET_MAC_ADDR_OFST 48634#define MC_CMD_CLP_IN_SET_MAC_ADDR_LEN 68635/* Padding */8636#define MC_CMD_CLP_IN_SET_MAC_RESERVED_OFST 108637#define MC_CMD_CLP_IN_SET_MAC_RESERVED_LEN 28638 8639/* MC_CMD_CLP_OUT_SET_MAC msgresponse */8640#define MC_CMD_CLP_OUT_SET_MAC_LEN 08641 8642/* MC_CMD_CLP_IN_SET_MAC_V2 msgrequest */8643#define MC_CMD_CLP_IN_SET_MAC_V2_LEN 168644/* MC_CMD_CLP_IN_OP_OFST 0 */8645/* MC_CMD_CLP_IN_OP_LEN 4 */8646/* The MAC address assigned to port. A zero MAC address of 00:00:00:00:00:008647 * restores the permanent (factory-programmed) MAC address associated with the8648 * port. A non-zero MAC address persists until a PCIe reset or a power cycle.8649 */8650#define MC_CMD_CLP_IN_SET_MAC_V2_ADDR_OFST 48651#define MC_CMD_CLP_IN_SET_MAC_V2_ADDR_LEN 68652/* Padding */8653#define MC_CMD_CLP_IN_SET_MAC_V2_RESERVED_OFST 108654#define MC_CMD_CLP_IN_SET_MAC_V2_RESERVED_LEN 28655#define MC_CMD_CLP_IN_SET_MAC_V2_FLAGS_OFST 128656#define MC_CMD_CLP_IN_SET_MAC_V2_FLAGS_LEN 48657#define MC_CMD_CLP_IN_SET_MAC_V2_VIRTUAL_OFST 128658#define MC_CMD_CLP_IN_SET_MAC_V2_VIRTUAL_LBN 08659#define MC_CMD_CLP_IN_SET_MAC_V2_VIRTUAL_WIDTH 18660 8661/* MC_CMD_CLP_IN_GET_MAC msgrequest */8662#define MC_CMD_CLP_IN_GET_MAC_LEN 48663/* MC_CMD_CLP_IN_OP_OFST 0 */8664/* MC_CMD_CLP_IN_OP_LEN 4 */8665 8666/* MC_CMD_CLP_IN_GET_MAC_V2 msgrequest */8667#define MC_CMD_CLP_IN_GET_MAC_V2_LEN 88668/* MC_CMD_CLP_IN_OP_OFST 0 */8669/* MC_CMD_CLP_IN_OP_LEN 4 */8670#define MC_CMD_CLP_IN_GET_MAC_V2_FLAGS_OFST 48671#define MC_CMD_CLP_IN_GET_MAC_V2_FLAGS_LEN 48672#define MC_CMD_CLP_IN_GET_MAC_V2_PERMANENT_OFST 48673#define MC_CMD_CLP_IN_GET_MAC_V2_PERMANENT_LBN 08674#define MC_CMD_CLP_IN_GET_MAC_V2_PERMANENT_WIDTH 18675 8676/* MC_CMD_CLP_OUT_GET_MAC msgresponse */8677#define MC_CMD_CLP_OUT_GET_MAC_LEN 88678/* MAC address assigned to port */8679#define MC_CMD_CLP_OUT_GET_MAC_ADDR_OFST 08680#define MC_CMD_CLP_OUT_GET_MAC_ADDR_LEN 68681/* Padding */8682#define MC_CMD_CLP_OUT_GET_MAC_RESERVED_OFST 68683#define MC_CMD_CLP_OUT_GET_MAC_RESERVED_LEN 28684 8685/* MC_CMD_CLP_IN_SET_BOOT msgrequest */8686#define MC_CMD_CLP_IN_SET_BOOT_LEN 58687/* MC_CMD_CLP_IN_OP_OFST 0 */8688/* MC_CMD_CLP_IN_OP_LEN 4 */8689/* Boot flag */8690#define MC_CMD_CLP_IN_SET_BOOT_FLAG_OFST 48691#define MC_CMD_CLP_IN_SET_BOOT_FLAG_LEN 18692 8693/* MC_CMD_CLP_OUT_SET_BOOT msgresponse */8694#define MC_CMD_CLP_OUT_SET_BOOT_LEN 08695 8696/* MC_CMD_CLP_IN_GET_BOOT msgrequest */8697#define MC_CMD_CLP_IN_GET_BOOT_LEN 48698/* MC_CMD_CLP_IN_OP_OFST 0 */8699/* MC_CMD_CLP_IN_OP_LEN 4 */8700 8701/* MC_CMD_CLP_OUT_GET_BOOT msgresponse */8702#define MC_CMD_CLP_OUT_GET_BOOT_LEN 48703/* Boot flag */8704#define MC_CMD_CLP_OUT_GET_BOOT_FLAG_OFST 08705#define MC_CMD_CLP_OUT_GET_BOOT_FLAG_LEN 18706/* Padding */8707#define MC_CMD_CLP_OUT_GET_BOOT_RESERVED_OFST 18708#define MC_CMD_CLP_OUT_GET_BOOT_RESERVED_LEN 38709 8710 8711/***********************************/8712/* MC_CMD_MUM8713 * Perform a MUM operation8714 */8715#define MC_CMD_MUM 0x578716#undef MC_CMD_0x57_PRIVILEGE_CTG8717 8718#define MC_CMD_0x57_PRIVILEGE_CTG SRIOV_CTG_INSECURE8719 8720/* MC_CMD_MUM_IN msgrequest */8721#define MC_CMD_MUM_IN_LEN 48722#define MC_CMD_MUM_IN_OP_HDR_OFST 08723#define MC_CMD_MUM_IN_OP_HDR_LEN 48724#define MC_CMD_MUM_IN_OP_OFST 08725#define MC_CMD_MUM_IN_OP_LBN 08726#define MC_CMD_MUM_IN_OP_WIDTH 88727/* enum: NULL MCDI command to MUM */8728#define MC_CMD_MUM_OP_NULL 0x18729/* enum: Get MUM version */8730#define MC_CMD_MUM_OP_GET_VERSION 0x28731/* enum: Issue raw I2C command to MUM */8732#define MC_CMD_MUM_OP_RAW_CMD 0x38733/* enum: Read from registers on devices connected to MUM. */8734#define MC_CMD_MUM_OP_READ 0x48735/* enum: Write to registers on devices connected to MUM. */8736#define MC_CMD_MUM_OP_WRITE 0x58737/* enum: Control UART logging. */8738#define MC_CMD_MUM_OP_LOG 0x68739/* enum: Operations on MUM GPIO lines */8740#define MC_CMD_MUM_OP_GPIO 0x78741/* enum: Get sensor readings from MUM */8742#define MC_CMD_MUM_OP_READ_SENSORS 0x88743/* enum: Initiate clock programming on the MUM */8744#define MC_CMD_MUM_OP_PROGRAM_CLOCKS 0x98745/* enum: Initiate FPGA load from flash on the MUM */8746#define MC_CMD_MUM_OP_FPGA_LOAD 0xa8747/* enum: Request sensor reading from MUM ADC resulting from earlier request via8748 * MUM ATB8749 */8750#define MC_CMD_MUM_OP_READ_ATB_SENSOR 0xb8751/* enum: Send commands relating to the QSFP ports via the MUM for PHY8752 * operations8753 */8754#define MC_CMD_MUM_OP_QSFP 0xc8755/* enum: Request discrete and SODIMM DDR info (type, size, speed grade, voltage8756 * level) from MUM8757 */8758#define MC_CMD_MUM_OP_READ_DDR_INFO 0xd8759 8760/* MC_CMD_MUM_IN_NULL msgrequest */8761#define MC_CMD_MUM_IN_NULL_LEN 48762/* MUM cmd header */8763#define MC_CMD_MUM_IN_CMD_OFST 08764#define MC_CMD_MUM_IN_CMD_LEN 48765 8766/* MC_CMD_MUM_IN_GET_VERSION msgrequest */8767#define MC_CMD_MUM_IN_GET_VERSION_LEN 48768/* MUM cmd header */8769/* MC_CMD_MUM_IN_CMD_OFST 0 */8770/* MC_CMD_MUM_IN_CMD_LEN 4 */8771 8772/* MC_CMD_MUM_IN_READ msgrequest */8773#define MC_CMD_MUM_IN_READ_LEN 168774/* MUM cmd header */8775/* MC_CMD_MUM_IN_CMD_OFST 0 */8776/* MC_CMD_MUM_IN_CMD_LEN 4 */8777/* ID of (device connected to MUM) to read from registers of */8778#define MC_CMD_MUM_IN_READ_DEVICE_OFST 48779#define MC_CMD_MUM_IN_READ_DEVICE_LEN 48780/* enum: Hittite HMC1035 clock generator on Sorrento board */8781#define MC_CMD_MUM_DEV_HITTITE 0x18782/* enum: Hittite HMC1035 clock generator for NIC-side on Sorrento board */8783#define MC_CMD_MUM_DEV_HITTITE_NIC 0x28784/* 32-bit address to read from */8785#define MC_CMD_MUM_IN_READ_ADDR_OFST 88786#define MC_CMD_MUM_IN_READ_ADDR_LEN 48787/* Number of words to read. */8788#define MC_CMD_MUM_IN_READ_NUMWORDS_OFST 128789#define MC_CMD_MUM_IN_READ_NUMWORDS_LEN 48790 8791/* MC_CMD_MUM_IN_WRITE msgrequest */8792#define MC_CMD_MUM_IN_WRITE_LENMIN 168793#define MC_CMD_MUM_IN_WRITE_LENMAX 2528794#define MC_CMD_MUM_IN_WRITE_LENMAX_MCDI2 10208795#define MC_CMD_MUM_IN_WRITE_LEN(num) (12+4*(num))8796#define MC_CMD_MUM_IN_WRITE_BUFFER_NUM(len) (((len)-12)/4)8797/* MUM cmd header */8798/* MC_CMD_MUM_IN_CMD_OFST 0 */8799/* MC_CMD_MUM_IN_CMD_LEN 4 */8800/* ID of (device connected to MUM) to write to registers of */8801#define MC_CMD_MUM_IN_WRITE_DEVICE_OFST 48802#define MC_CMD_MUM_IN_WRITE_DEVICE_LEN 48803/* enum: Hittite HMC1035 clock generator on Sorrento board */8804/* MC_CMD_MUM_DEV_HITTITE 0x1 */8805/* 32-bit address to write to */8806#define MC_CMD_MUM_IN_WRITE_ADDR_OFST 88807#define MC_CMD_MUM_IN_WRITE_ADDR_LEN 48808/* Words to write */8809#define MC_CMD_MUM_IN_WRITE_BUFFER_OFST 128810#define MC_CMD_MUM_IN_WRITE_BUFFER_LEN 48811#define MC_CMD_MUM_IN_WRITE_BUFFER_MINNUM 18812#define MC_CMD_MUM_IN_WRITE_BUFFER_MAXNUM 608813#define MC_CMD_MUM_IN_WRITE_BUFFER_MAXNUM_MCDI2 2528814 8815/* MC_CMD_MUM_IN_RAW_CMD msgrequest */8816#define MC_CMD_MUM_IN_RAW_CMD_LENMIN 178817#define MC_CMD_MUM_IN_RAW_CMD_LENMAX 2528818#define MC_CMD_MUM_IN_RAW_CMD_LENMAX_MCDI2 10208819#define MC_CMD_MUM_IN_RAW_CMD_LEN(num) (16+1*(num))8820#define MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_NUM(len) (((len)-16)/1)8821/* MUM cmd header */8822/* MC_CMD_MUM_IN_CMD_OFST 0 */8823/* MC_CMD_MUM_IN_CMD_LEN 4 */8824/* MUM I2C cmd code */8825#define MC_CMD_MUM_IN_RAW_CMD_CMD_CODE_OFST 48826#define MC_CMD_MUM_IN_RAW_CMD_CMD_CODE_LEN 48827/* Number of bytes to write */8828#define MC_CMD_MUM_IN_RAW_CMD_NUM_WRITE_OFST 88829#define MC_CMD_MUM_IN_RAW_CMD_NUM_WRITE_LEN 48830/* Number of bytes to read */8831#define MC_CMD_MUM_IN_RAW_CMD_NUM_READ_OFST 128832#define MC_CMD_MUM_IN_RAW_CMD_NUM_READ_LEN 48833/* Bytes to write */8834#define MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_OFST 168835#define MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_LEN 18836#define MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_MINNUM 18837#define MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_MAXNUM 2368838#define MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_MAXNUM_MCDI2 10048839 8840/* MC_CMD_MUM_IN_LOG msgrequest */8841#define MC_CMD_MUM_IN_LOG_LEN 88842/* MUM cmd header */8843/* MC_CMD_MUM_IN_CMD_OFST 0 */8844/* MC_CMD_MUM_IN_CMD_LEN 4 */8845#define MC_CMD_MUM_IN_LOG_OP_OFST 48846#define MC_CMD_MUM_IN_LOG_OP_LEN 48847#define MC_CMD_MUM_IN_LOG_OP_UART 0x1 /* enum */8848 8849/* MC_CMD_MUM_IN_LOG_OP_UART msgrequest */8850#define MC_CMD_MUM_IN_LOG_OP_UART_LEN 128851/* MC_CMD_MUM_IN_CMD_OFST 0 */8852/* MC_CMD_MUM_IN_CMD_LEN 4 */8853/* MC_CMD_MUM_IN_LOG_OP_OFST 4 */8854/* MC_CMD_MUM_IN_LOG_OP_LEN 4 */8855/* Enable/disable debug output to UART */8856#define MC_CMD_MUM_IN_LOG_OP_UART_ENABLE_OFST 88857#define MC_CMD_MUM_IN_LOG_OP_UART_ENABLE_LEN 48858 8859/* MC_CMD_MUM_IN_GPIO msgrequest */8860#define MC_CMD_MUM_IN_GPIO_LEN 88861/* MUM cmd header */8862/* MC_CMD_MUM_IN_CMD_OFST 0 */8863/* MC_CMD_MUM_IN_CMD_LEN 4 */8864#define MC_CMD_MUM_IN_GPIO_HDR_OFST 48865#define MC_CMD_MUM_IN_GPIO_HDR_LEN 48866#define MC_CMD_MUM_IN_GPIO_OPCODE_OFST 48867#define MC_CMD_MUM_IN_GPIO_OPCODE_LBN 08868#define MC_CMD_MUM_IN_GPIO_OPCODE_WIDTH 88869#define MC_CMD_MUM_IN_GPIO_IN_READ 0x0 /* enum */8870#define MC_CMD_MUM_IN_GPIO_OUT_WRITE 0x1 /* enum */8871#define MC_CMD_MUM_IN_GPIO_OUT_READ 0x2 /* enum */8872#define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE 0x3 /* enum */8873#define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ 0x4 /* enum */8874#define MC_CMD_MUM_IN_GPIO_OP 0x5 /* enum */8875 8876/* MC_CMD_MUM_IN_GPIO_IN_READ msgrequest */8877#define MC_CMD_MUM_IN_GPIO_IN_READ_LEN 88878/* MC_CMD_MUM_IN_CMD_OFST 0 */8879/* MC_CMD_MUM_IN_CMD_LEN 4 */8880#define MC_CMD_MUM_IN_GPIO_IN_READ_HDR_OFST 48881#define MC_CMD_MUM_IN_GPIO_IN_READ_HDR_LEN 48882 8883/* MC_CMD_MUM_IN_GPIO_OUT_WRITE msgrequest */8884#define MC_CMD_MUM_IN_GPIO_OUT_WRITE_LEN 168885/* MC_CMD_MUM_IN_CMD_OFST 0 */8886/* MC_CMD_MUM_IN_CMD_LEN 4 */8887#define MC_CMD_MUM_IN_GPIO_OUT_WRITE_HDR_OFST 48888#define MC_CMD_MUM_IN_GPIO_OUT_WRITE_HDR_LEN 48889/* The first 32-bit word to be written to the GPIO OUT register. */8890#define MC_CMD_MUM_IN_GPIO_OUT_WRITE_GPIOMASK1_OFST 88891#define MC_CMD_MUM_IN_GPIO_OUT_WRITE_GPIOMASK1_LEN 48892/* The second 32-bit word to be written to the GPIO OUT register. */8893#define MC_CMD_MUM_IN_GPIO_OUT_WRITE_GPIOMASK2_OFST 128894#define MC_CMD_MUM_IN_GPIO_OUT_WRITE_GPIOMASK2_LEN 48895 8896/* MC_CMD_MUM_IN_GPIO_OUT_READ msgrequest */8897#define MC_CMD_MUM_IN_GPIO_OUT_READ_LEN 88898/* MC_CMD_MUM_IN_CMD_OFST 0 */8899/* MC_CMD_MUM_IN_CMD_LEN 4 */8900#define MC_CMD_MUM_IN_GPIO_OUT_READ_HDR_OFST 48901#define MC_CMD_MUM_IN_GPIO_OUT_READ_HDR_LEN 48902 8903/* MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE msgrequest */8904#define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_LEN 168905/* MC_CMD_MUM_IN_CMD_OFST 0 */8906/* MC_CMD_MUM_IN_CMD_LEN 4 */8907#define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_HDR_OFST 48908#define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_HDR_LEN 48909/* The first 32-bit word to be written to the GPIO OUT ENABLE register. */8910#define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_GPIOMASK1_OFST 88911#define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_GPIOMASK1_LEN 48912/* The second 32-bit word to be written to the GPIO OUT ENABLE register. */8913#define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_GPIOMASK2_OFST 128914#define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_GPIOMASK2_LEN 48915 8916/* MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ msgrequest */8917#define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ_LEN 88918/* MC_CMD_MUM_IN_CMD_OFST 0 */8919/* MC_CMD_MUM_IN_CMD_LEN 4 */8920#define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ_HDR_OFST 48921#define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ_HDR_LEN 48922 8923/* MC_CMD_MUM_IN_GPIO_OP msgrequest */8924#define MC_CMD_MUM_IN_GPIO_OP_LEN 88925/* MC_CMD_MUM_IN_CMD_OFST 0 */8926/* MC_CMD_MUM_IN_CMD_LEN 4 */8927#define MC_CMD_MUM_IN_GPIO_OP_HDR_OFST 48928#define MC_CMD_MUM_IN_GPIO_OP_HDR_LEN 48929#define MC_CMD_MUM_IN_GPIO_OP_BITWISE_OP_OFST 48930#define MC_CMD_MUM_IN_GPIO_OP_BITWISE_OP_LBN 88931#define MC_CMD_MUM_IN_GPIO_OP_BITWISE_OP_WIDTH 88932#define MC_CMD_MUM_IN_GPIO_OP_OUT_READ 0x0 /* enum */8933#define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE 0x1 /* enum */8934#define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG 0x2 /* enum */8935#define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE 0x3 /* enum */8936#define MC_CMD_MUM_IN_GPIO_OP_GPIO_NUMBER_OFST 48937#define MC_CMD_MUM_IN_GPIO_OP_GPIO_NUMBER_LBN 168938#define MC_CMD_MUM_IN_GPIO_OP_GPIO_NUMBER_WIDTH 88939 8940/* MC_CMD_MUM_IN_GPIO_OP_OUT_READ msgrequest */8941#define MC_CMD_MUM_IN_GPIO_OP_OUT_READ_LEN 88942/* MC_CMD_MUM_IN_CMD_OFST 0 */8943/* MC_CMD_MUM_IN_CMD_LEN 4 */8944#define MC_CMD_MUM_IN_GPIO_OP_OUT_READ_HDR_OFST 48945#define MC_CMD_MUM_IN_GPIO_OP_OUT_READ_HDR_LEN 48946 8947/* MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE msgrequest */8948#define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_LEN 88949/* MC_CMD_MUM_IN_CMD_OFST 0 */8950/* MC_CMD_MUM_IN_CMD_LEN 4 */8951#define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_HDR_OFST 48952#define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_HDR_LEN 48953#define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_WRITEBIT_OFST 48954#define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_WRITEBIT_LBN 248955#define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_WRITEBIT_WIDTH 88956 8957/* MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG msgrequest */8958#define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_LEN 88959/* MC_CMD_MUM_IN_CMD_OFST 0 */8960/* MC_CMD_MUM_IN_CMD_LEN 4 */8961#define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_HDR_OFST 48962#define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_HDR_LEN 48963#define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_CFG_OFST 48964#define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_CFG_LBN 248965#define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_CFG_WIDTH 88966 8967/* MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE msgrequest */8968#define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_LEN 88969/* MC_CMD_MUM_IN_CMD_OFST 0 */8970/* MC_CMD_MUM_IN_CMD_LEN 4 */8971#define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_HDR_OFST 48972#define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_HDR_LEN 48973#define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_ENABLEBIT_OFST 48974#define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_ENABLEBIT_LBN 248975#define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_ENABLEBIT_WIDTH 88976 8977/* MC_CMD_MUM_IN_READ_SENSORS msgrequest */8978#define MC_CMD_MUM_IN_READ_SENSORS_LEN 88979/* MUM cmd header */8980/* MC_CMD_MUM_IN_CMD_OFST 0 */8981/* MC_CMD_MUM_IN_CMD_LEN 4 */8982#define MC_CMD_MUM_IN_READ_SENSORS_PARAMS_OFST 48983#define MC_CMD_MUM_IN_READ_SENSORS_PARAMS_LEN 48984#define MC_CMD_MUM_IN_READ_SENSORS_SENSOR_ID_OFST 48985#define MC_CMD_MUM_IN_READ_SENSORS_SENSOR_ID_LBN 08986#define MC_CMD_MUM_IN_READ_SENSORS_SENSOR_ID_WIDTH 88987#define MC_CMD_MUM_IN_READ_SENSORS_NUM_SENSORS_OFST 48988#define MC_CMD_MUM_IN_READ_SENSORS_NUM_SENSORS_LBN 88989#define MC_CMD_MUM_IN_READ_SENSORS_NUM_SENSORS_WIDTH 88990 8991/* MC_CMD_MUM_IN_PROGRAM_CLOCKS msgrequest */8992#define MC_CMD_MUM_IN_PROGRAM_CLOCKS_LEN 128993/* MUM cmd header */8994/* MC_CMD_MUM_IN_CMD_OFST 0 */8995/* MC_CMD_MUM_IN_CMD_LEN 4 */8996/* Bit-mask of clocks to be programmed */8997#define MC_CMD_MUM_IN_PROGRAM_CLOCKS_MASK_OFST 48998#define MC_CMD_MUM_IN_PROGRAM_CLOCKS_MASK_LEN 48999#define MC_CMD_MUM_CLOCK_ID_FPGA 0x0 /* enum */9000#define MC_CMD_MUM_CLOCK_ID_DDR 0x1 /* enum */9001#define MC_CMD_MUM_CLOCK_ID_NIC 0x2 /* enum */9002/* Control flags for clock programming */9003#define MC_CMD_MUM_IN_PROGRAM_CLOCKS_FLAGS_OFST 89004#define MC_CMD_MUM_IN_PROGRAM_CLOCKS_FLAGS_LEN 49005#define MC_CMD_MUM_IN_PROGRAM_CLOCKS_OVERCLOCK_110_OFST 89006#define MC_CMD_MUM_IN_PROGRAM_CLOCKS_OVERCLOCK_110_LBN 09007#define MC_CMD_MUM_IN_PROGRAM_CLOCKS_OVERCLOCK_110_WIDTH 19008#define MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_NIC_FROM_FPGA_OFST 89009#define MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_NIC_FROM_FPGA_LBN 19010#define MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_NIC_FROM_FPGA_WIDTH 19011#define MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_REF_FROM_XO_OFST 89012#define MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_REF_FROM_XO_LBN 29013#define MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_REF_FROM_XO_WIDTH 19014 9015/* MC_CMD_MUM_IN_FPGA_LOAD msgrequest */9016#define MC_CMD_MUM_IN_FPGA_LOAD_LEN 89017/* MUM cmd header */9018/* MC_CMD_MUM_IN_CMD_OFST 0 */9019/* MC_CMD_MUM_IN_CMD_LEN 4 */9020/* Enable/Disable FPGA config from flash */9021#define MC_CMD_MUM_IN_FPGA_LOAD_ENABLE_OFST 49022#define MC_CMD_MUM_IN_FPGA_LOAD_ENABLE_LEN 49023 9024/* MC_CMD_MUM_IN_READ_ATB_SENSOR msgrequest */9025#define MC_CMD_MUM_IN_READ_ATB_SENSOR_LEN 49026/* MUM cmd header */9027/* MC_CMD_MUM_IN_CMD_OFST 0 */9028/* MC_CMD_MUM_IN_CMD_LEN 4 */9029 9030/* MC_CMD_MUM_IN_QSFP msgrequest */9031#define MC_CMD_MUM_IN_QSFP_LEN 129032/* MUM cmd header */9033/* MC_CMD_MUM_IN_CMD_OFST 0 */9034/* MC_CMD_MUM_IN_CMD_LEN 4 */9035#define MC_CMD_MUM_IN_QSFP_HDR_OFST 49036#define MC_CMD_MUM_IN_QSFP_HDR_LEN 49037#define MC_CMD_MUM_IN_QSFP_OPCODE_OFST 49038#define MC_CMD_MUM_IN_QSFP_OPCODE_LBN 09039#define MC_CMD_MUM_IN_QSFP_OPCODE_WIDTH 49040#define MC_CMD_MUM_IN_QSFP_INIT 0x0 /* enum */9041#define MC_CMD_MUM_IN_QSFP_RECONFIGURE 0x1 /* enum */9042#define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP 0x2 /* enum */9043#define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO 0x3 /* enum */9044#define MC_CMD_MUM_IN_QSFP_FILL_STATS 0x4 /* enum */9045#define MC_CMD_MUM_IN_QSFP_POLL_BIST 0x5 /* enum */9046#define MC_CMD_MUM_IN_QSFP_IDX_OFST 89047#define MC_CMD_MUM_IN_QSFP_IDX_LEN 49048 9049/* MC_CMD_MUM_IN_QSFP_INIT msgrequest */9050#define MC_CMD_MUM_IN_QSFP_INIT_LEN 169051/* MC_CMD_MUM_IN_CMD_OFST 0 */9052/* MC_CMD_MUM_IN_CMD_LEN 4 */9053#define MC_CMD_MUM_IN_QSFP_INIT_HDR_OFST 49054#define MC_CMD_MUM_IN_QSFP_INIT_HDR_LEN 49055#define MC_CMD_MUM_IN_QSFP_INIT_IDX_OFST 89056#define MC_CMD_MUM_IN_QSFP_INIT_IDX_LEN 49057#define MC_CMD_MUM_IN_QSFP_INIT_CAGE_OFST 129058#define MC_CMD_MUM_IN_QSFP_INIT_CAGE_LEN 49059 9060/* MC_CMD_MUM_IN_QSFP_RECONFIGURE msgrequest */9061#define MC_CMD_MUM_IN_QSFP_RECONFIGURE_LEN 249062/* MC_CMD_MUM_IN_CMD_OFST 0 */9063/* MC_CMD_MUM_IN_CMD_LEN 4 */9064#define MC_CMD_MUM_IN_QSFP_RECONFIGURE_HDR_OFST 49065#define MC_CMD_MUM_IN_QSFP_RECONFIGURE_HDR_LEN 49066#define MC_CMD_MUM_IN_QSFP_RECONFIGURE_IDX_OFST 89067#define MC_CMD_MUM_IN_QSFP_RECONFIGURE_IDX_LEN 49068#define MC_CMD_MUM_IN_QSFP_RECONFIGURE_TX_DISABLE_OFST 129069#define MC_CMD_MUM_IN_QSFP_RECONFIGURE_TX_DISABLE_LEN 49070#define MC_CMD_MUM_IN_QSFP_RECONFIGURE_PORT_LANES_OFST 169071#define MC_CMD_MUM_IN_QSFP_RECONFIGURE_PORT_LANES_LEN 49072#define MC_CMD_MUM_IN_QSFP_RECONFIGURE_PORT_LINK_SPEED_OFST 209073#define MC_CMD_MUM_IN_QSFP_RECONFIGURE_PORT_LINK_SPEED_LEN 49074 9075/* MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP msgrequest */9076#define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_LEN 129077/* MC_CMD_MUM_IN_CMD_OFST 0 */9078/* MC_CMD_MUM_IN_CMD_LEN 4 */9079#define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_HDR_OFST 49080#define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_HDR_LEN 49081#define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_IDX_OFST 89082#define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_IDX_LEN 49083 9084/* MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO msgrequest */9085#define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_LEN 169086/* MC_CMD_MUM_IN_CMD_OFST 0 */9087/* MC_CMD_MUM_IN_CMD_LEN 4 */9088#define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_HDR_OFST 49089#define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_HDR_LEN 49090#define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_IDX_OFST 89091#define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_IDX_LEN 49092#define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_PAGE_OFST 129093#define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_PAGE_LEN 49094 9095/* MC_CMD_MUM_IN_QSFP_FILL_STATS msgrequest */9096#define MC_CMD_MUM_IN_QSFP_FILL_STATS_LEN 129097/* MC_CMD_MUM_IN_CMD_OFST 0 */9098/* MC_CMD_MUM_IN_CMD_LEN 4 */9099#define MC_CMD_MUM_IN_QSFP_FILL_STATS_HDR_OFST 49100#define MC_CMD_MUM_IN_QSFP_FILL_STATS_HDR_LEN 49101#define MC_CMD_MUM_IN_QSFP_FILL_STATS_IDX_OFST 89102#define MC_CMD_MUM_IN_QSFP_FILL_STATS_IDX_LEN 49103 9104/* MC_CMD_MUM_IN_QSFP_POLL_BIST msgrequest */9105#define MC_CMD_MUM_IN_QSFP_POLL_BIST_LEN 129106/* MC_CMD_MUM_IN_CMD_OFST 0 */9107/* MC_CMD_MUM_IN_CMD_LEN 4 */9108#define MC_CMD_MUM_IN_QSFP_POLL_BIST_HDR_OFST 49109#define MC_CMD_MUM_IN_QSFP_POLL_BIST_HDR_LEN 49110#define MC_CMD_MUM_IN_QSFP_POLL_BIST_IDX_OFST 89111#define MC_CMD_MUM_IN_QSFP_POLL_BIST_IDX_LEN 49112 9113/* MC_CMD_MUM_IN_READ_DDR_INFO msgrequest */9114#define MC_CMD_MUM_IN_READ_DDR_INFO_LEN 49115/* MUM cmd header */9116/* MC_CMD_MUM_IN_CMD_OFST 0 */9117/* MC_CMD_MUM_IN_CMD_LEN 4 */9118 9119/* MC_CMD_MUM_OUT msgresponse */9120#define MC_CMD_MUM_OUT_LEN 09121 9122/* MC_CMD_MUM_OUT_NULL msgresponse */9123#define MC_CMD_MUM_OUT_NULL_LEN 09124 9125/* MC_CMD_MUM_OUT_GET_VERSION msgresponse */9126#define MC_CMD_MUM_OUT_GET_VERSION_LEN 129127#define MC_CMD_MUM_OUT_GET_VERSION_FIRMWARE_OFST 09128#define MC_CMD_MUM_OUT_GET_VERSION_FIRMWARE_LEN 49129#define MC_CMD_MUM_OUT_GET_VERSION_VERSION_OFST 49130#define MC_CMD_MUM_OUT_GET_VERSION_VERSION_LEN 89131#define MC_CMD_MUM_OUT_GET_VERSION_VERSION_LO_OFST 49132#define MC_CMD_MUM_OUT_GET_VERSION_VERSION_LO_LEN 49133#define MC_CMD_MUM_OUT_GET_VERSION_VERSION_LO_LBN 329134#define MC_CMD_MUM_OUT_GET_VERSION_VERSION_LO_WIDTH 329135#define MC_CMD_MUM_OUT_GET_VERSION_VERSION_HI_OFST 89136#define MC_CMD_MUM_OUT_GET_VERSION_VERSION_HI_LEN 49137#define MC_CMD_MUM_OUT_GET_VERSION_VERSION_HI_LBN 649138#define MC_CMD_MUM_OUT_GET_VERSION_VERSION_HI_WIDTH 329139 9140/* MC_CMD_MUM_OUT_RAW_CMD msgresponse */9141#define MC_CMD_MUM_OUT_RAW_CMD_LENMIN 19142#define MC_CMD_MUM_OUT_RAW_CMD_LENMAX 2529143#define MC_CMD_MUM_OUT_RAW_CMD_LENMAX_MCDI2 10209144#define MC_CMD_MUM_OUT_RAW_CMD_LEN(num) (0+1*(num))9145#define MC_CMD_MUM_OUT_RAW_CMD_DATA_NUM(len) (((len)-0)/1)9146/* returned data */9147#define MC_CMD_MUM_OUT_RAW_CMD_DATA_OFST 09148#define MC_CMD_MUM_OUT_RAW_CMD_DATA_LEN 19149#define MC_CMD_MUM_OUT_RAW_CMD_DATA_MINNUM 19150#define MC_CMD_MUM_OUT_RAW_CMD_DATA_MAXNUM 2529151#define MC_CMD_MUM_OUT_RAW_CMD_DATA_MAXNUM_MCDI2 10209152 9153/* MC_CMD_MUM_OUT_READ msgresponse */9154#define MC_CMD_MUM_OUT_READ_LENMIN 49155#define MC_CMD_MUM_OUT_READ_LENMAX 2529156#define MC_CMD_MUM_OUT_READ_LENMAX_MCDI2 10209157#define MC_CMD_MUM_OUT_READ_LEN(num) (0+4*(num))9158#define MC_CMD_MUM_OUT_READ_BUFFER_NUM(len) (((len)-0)/4)9159#define MC_CMD_MUM_OUT_READ_BUFFER_OFST 09160#define MC_CMD_MUM_OUT_READ_BUFFER_LEN 49161#define MC_CMD_MUM_OUT_READ_BUFFER_MINNUM 19162#define MC_CMD_MUM_OUT_READ_BUFFER_MAXNUM 639163#define MC_CMD_MUM_OUT_READ_BUFFER_MAXNUM_MCDI2 2559164 9165/* MC_CMD_MUM_OUT_WRITE msgresponse */9166#define MC_CMD_MUM_OUT_WRITE_LEN 09167 9168/* MC_CMD_MUM_OUT_LOG msgresponse */9169#define MC_CMD_MUM_OUT_LOG_LEN 09170 9171/* MC_CMD_MUM_OUT_LOG_OP_UART msgresponse */9172#define MC_CMD_MUM_OUT_LOG_OP_UART_LEN 09173 9174/* MC_CMD_MUM_OUT_GPIO_IN_READ msgresponse */9175#define MC_CMD_MUM_OUT_GPIO_IN_READ_LEN 89176/* The first 32-bit word read from the GPIO IN register. */9177#define MC_CMD_MUM_OUT_GPIO_IN_READ_GPIOMASK1_OFST 09178#define MC_CMD_MUM_OUT_GPIO_IN_READ_GPIOMASK1_LEN 49179/* The second 32-bit word read from the GPIO IN register. */9180#define MC_CMD_MUM_OUT_GPIO_IN_READ_GPIOMASK2_OFST 49181#define MC_CMD_MUM_OUT_GPIO_IN_READ_GPIOMASK2_LEN 49182 9183/* MC_CMD_MUM_OUT_GPIO_OUT_WRITE msgresponse */9184#define MC_CMD_MUM_OUT_GPIO_OUT_WRITE_LEN 09185 9186/* MC_CMD_MUM_OUT_GPIO_OUT_READ msgresponse */9187#define MC_CMD_MUM_OUT_GPIO_OUT_READ_LEN 89188/* The first 32-bit word read from the GPIO OUT register. */9189#define MC_CMD_MUM_OUT_GPIO_OUT_READ_GPIOMASK1_OFST 09190#define MC_CMD_MUM_OUT_GPIO_OUT_READ_GPIOMASK1_LEN 49191/* The second 32-bit word read from the GPIO OUT register. */9192#define MC_CMD_MUM_OUT_GPIO_OUT_READ_GPIOMASK2_OFST 49193#define MC_CMD_MUM_OUT_GPIO_OUT_READ_GPIOMASK2_LEN 49194 9195/* MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_WRITE msgresponse */9196#define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_WRITE_LEN 09197 9198/* MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ msgresponse */9199#define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_LEN 89200#define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_GPIOMASK1_OFST 09201#define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_GPIOMASK1_LEN 49202#define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_GPIOMASK2_OFST 49203#define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_GPIOMASK2_LEN 49204 9205/* MC_CMD_MUM_OUT_GPIO_OP_OUT_READ msgresponse */9206#define MC_CMD_MUM_OUT_GPIO_OP_OUT_READ_LEN 49207#define MC_CMD_MUM_OUT_GPIO_OP_OUT_READ_BIT_READ_OFST 09208#define MC_CMD_MUM_OUT_GPIO_OP_OUT_READ_BIT_READ_LEN 49209 9210/* MC_CMD_MUM_OUT_GPIO_OP_OUT_WRITE msgresponse */9211#define MC_CMD_MUM_OUT_GPIO_OP_OUT_WRITE_LEN 09212 9213/* MC_CMD_MUM_OUT_GPIO_OP_OUT_CONFIG msgresponse */9214#define MC_CMD_MUM_OUT_GPIO_OP_OUT_CONFIG_LEN 09215 9216/* MC_CMD_MUM_OUT_GPIO_OP_OUT_ENABLE msgresponse */9217#define MC_CMD_MUM_OUT_GPIO_OP_OUT_ENABLE_LEN 09218 9219/* MC_CMD_MUM_OUT_READ_SENSORS msgresponse */9220#define MC_CMD_MUM_OUT_READ_SENSORS_LENMIN 49221#define MC_CMD_MUM_OUT_READ_SENSORS_LENMAX 2529222#define MC_CMD_MUM_OUT_READ_SENSORS_LENMAX_MCDI2 10209223#define MC_CMD_MUM_OUT_READ_SENSORS_LEN(num) (0+4*(num))9224#define MC_CMD_MUM_OUT_READ_SENSORS_DATA_NUM(len) (((len)-0)/4)9225#define MC_CMD_MUM_OUT_READ_SENSORS_DATA_OFST 09226#define MC_CMD_MUM_OUT_READ_SENSORS_DATA_LEN 49227#define MC_CMD_MUM_OUT_READ_SENSORS_DATA_MINNUM 19228#define MC_CMD_MUM_OUT_READ_SENSORS_DATA_MAXNUM 639229#define MC_CMD_MUM_OUT_READ_SENSORS_DATA_MAXNUM_MCDI2 2559230#define MC_CMD_MUM_OUT_READ_SENSORS_READING_OFST 09231#define MC_CMD_MUM_OUT_READ_SENSORS_READING_LBN 09232#define MC_CMD_MUM_OUT_READ_SENSORS_READING_WIDTH 169233#define MC_CMD_MUM_OUT_READ_SENSORS_STATE_OFST 09234#define MC_CMD_MUM_OUT_READ_SENSORS_STATE_LBN 169235#define MC_CMD_MUM_OUT_READ_SENSORS_STATE_WIDTH 89236#define MC_CMD_MUM_OUT_READ_SENSORS_TYPE_OFST 09237#define MC_CMD_MUM_OUT_READ_SENSORS_TYPE_LBN 249238#define MC_CMD_MUM_OUT_READ_SENSORS_TYPE_WIDTH 89239 9240/* MC_CMD_MUM_OUT_PROGRAM_CLOCKS msgresponse */9241#define MC_CMD_MUM_OUT_PROGRAM_CLOCKS_LEN 49242#define MC_CMD_MUM_OUT_PROGRAM_CLOCKS_OK_MASK_OFST 09243#define MC_CMD_MUM_OUT_PROGRAM_CLOCKS_OK_MASK_LEN 49244 9245/* MC_CMD_MUM_OUT_FPGA_LOAD msgresponse */9246#define MC_CMD_MUM_OUT_FPGA_LOAD_LEN 09247 9248/* MC_CMD_MUM_OUT_READ_ATB_SENSOR msgresponse */9249#define MC_CMD_MUM_OUT_READ_ATB_SENSOR_LEN 49250#define MC_CMD_MUM_OUT_READ_ATB_SENSOR_RESULT_OFST 09251#define MC_CMD_MUM_OUT_READ_ATB_SENSOR_RESULT_LEN 49252 9253/* MC_CMD_MUM_OUT_QSFP_INIT msgresponse */9254#define MC_CMD_MUM_OUT_QSFP_INIT_LEN 09255 9256/* MC_CMD_MUM_OUT_QSFP_RECONFIGURE msgresponse */9257#define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_LEN 89258#define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LP_CAP_OFST 09259#define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LP_CAP_LEN 49260#define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_FLAGS_OFST 49261#define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_FLAGS_LEN 49262#define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_READY_OFST 49263#define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_READY_LBN 09264#define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_READY_WIDTH 19265#define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LINK_UP_OFST 49266#define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LINK_UP_LBN 19267#define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LINK_UP_WIDTH 19268 9269/* MC_CMD_MUM_OUT_QSFP_GET_SUPPORTED_CAP msgresponse */9270#define MC_CMD_MUM_OUT_QSFP_GET_SUPPORTED_CAP_LEN 49271#define MC_CMD_MUM_OUT_QSFP_GET_SUPPORTED_CAP_PORT_PHY_LP_CAP_OFST 09272#define MC_CMD_MUM_OUT_QSFP_GET_SUPPORTED_CAP_PORT_PHY_LP_CAP_LEN 49273 9274/* MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO msgresponse */9275#define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_LENMIN 59276#define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_LENMAX 2529277#define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_LENMAX_MCDI2 10209278#define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_LEN(num) (4+1*(num))9279#define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_NUM(len) (((len)-4)/1)9280/* in bytes */9281#define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATALEN_OFST 09282#define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATALEN_LEN 49283#define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_OFST 49284#define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_LEN 19285#define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_MINNUM 19286#define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_MAXNUM 2489287#define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_MAXNUM_MCDI2 10169288 9289/* MC_CMD_MUM_OUT_QSFP_FILL_STATS msgresponse */9290#define MC_CMD_MUM_OUT_QSFP_FILL_STATS_LEN 89291#define MC_CMD_MUM_OUT_QSFP_FILL_STATS_PORT_PHY_STATS_PMA_PMD_LINK_UP_OFST 09292#define MC_CMD_MUM_OUT_QSFP_FILL_STATS_PORT_PHY_STATS_PMA_PMD_LINK_UP_LEN 49293#define MC_CMD_MUM_OUT_QSFP_FILL_STATS_PORT_PHY_STATS_PCS_LINK_UP_OFST 49294#define MC_CMD_MUM_OUT_QSFP_FILL_STATS_PORT_PHY_STATS_PCS_LINK_UP_LEN 49295 9296/* MC_CMD_MUM_OUT_QSFP_POLL_BIST msgresponse */9297#define MC_CMD_MUM_OUT_QSFP_POLL_BIST_LEN 49298#define MC_CMD_MUM_OUT_QSFP_POLL_BIST_TEST_OFST 09299#define MC_CMD_MUM_OUT_QSFP_POLL_BIST_TEST_LEN 49300 9301/* MC_CMD_MUM_OUT_READ_DDR_INFO msgresponse */9302#define MC_CMD_MUM_OUT_READ_DDR_INFO_LENMIN 249303#define MC_CMD_MUM_OUT_READ_DDR_INFO_LENMAX 2489304#define MC_CMD_MUM_OUT_READ_DDR_INFO_LENMAX_MCDI2 10169305#define MC_CMD_MUM_OUT_READ_DDR_INFO_LEN(num) (8+8*(num))9306#define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_NUM(len) (((len)-8)/8)9307/* Discrete (soldered) DDR resistor strap info */9308#define MC_CMD_MUM_OUT_READ_DDR_INFO_DISCRETE_DDR_INFO_OFST 09309#define MC_CMD_MUM_OUT_READ_DDR_INFO_DISCRETE_DDR_INFO_LEN 49310#define MC_CMD_MUM_OUT_READ_DDR_INFO_VRATIO_OFST 09311#define MC_CMD_MUM_OUT_READ_DDR_INFO_VRATIO_LBN 09312#define MC_CMD_MUM_OUT_READ_DDR_INFO_VRATIO_WIDTH 169313#define MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED1_OFST 09314#define MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED1_LBN 169315#define MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED1_WIDTH 169316/* Number of SODIMM info records */9317#define MC_CMD_MUM_OUT_READ_DDR_INFO_NUM_RECORDS_OFST 49318#define MC_CMD_MUM_OUT_READ_DDR_INFO_NUM_RECORDS_LEN 49319/* Array of SODIMM info records */9320#define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_OFST 89321#define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_LEN 89322#define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_LO_OFST 89323#define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_LO_LEN 49324#define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_LO_LBN 649325#define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_LO_WIDTH 329326#define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_HI_OFST 129327#define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_HI_LEN 49328#define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_HI_LBN 969329#define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_HI_WIDTH 329330#define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_MINNUM 29331#define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_MAXNUM 309332#define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_MAXNUM_MCDI2 1269333#define MC_CMD_MUM_OUT_READ_DDR_INFO_BANK_ID_OFST 89334#define MC_CMD_MUM_OUT_READ_DDR_INFO_BANK_ID_LBN 09335#define MC_CMD_MUM_OUT_READ_DDR_INFO_BANK_ID_WIDTH 89336/* enum: SODIMM bank 1 (Top SODIMM for Sorrento) */9337#define MC_CMD_MUM_OUT_READ_DDR_INFO_BANK1 0x09338/* enum: SODIMM bank 2 (Bottom SODDIMM for Sorrento) */9339#define MC_CMD_MUM_OUT_READ_DDR_INFO_BANK2 0x19340/* enum: Total number of SODIMM banks */9341#define MC_CMD_MUM_OUT_READ_DDR_INFO_NUM_BANKS 0x29342#define MC_CMD_MUM_OUT_READ_DDR_INFO_TYPE_OFST 89343#define MC_CMD_MUM_OUT_READ_DDR_INFO_TYPE_LBN 89344#define MC_CMD_MUM_OUT_READ_DDR_INFO_TYPE_WIDTH 89345#define MC_CMD_MUM_OUT_READ_DDR_INFO_RANK_OFST 89346#define MC_CMD_MUM_OUT_READ_DDR_INFO_RANK_LBN 169347#define MC_CMD_MUM_OUT_READ_DDR_INFO_RANK_WIDTH 49348#define MC_CMD_MUM_OUT_READ_DDR_INFO_VOLTAGE_OFST 89349#define MC_CMD_MUM_OUT_READ_DDR_INFO_VOLTAGE_LBN 209350#define MC_CMD_MUM_OUT_READ_DDR_INFO_VOLTAGE_WIDTH 49351#define MC_CMD_MUM_OUT_READ_DDR_INFO_NOT_POWERED 0x0 /* enum */9352#define MC_CMD_MUM_OUT_READ_DDR_INFO_1V25 0x1 /* enum */9353#define MC_CMD_MUM_OUT_READ_DDR_INFO_1V35 0x2 /* enum */9354#define MC_CMD_MUM_OUT_READ_DDR_INFO_1V5 0x3 /* enum */9355/* enum: Values 5-15 are reserved for future usage */9356#define MC_CMD_MUM_OUT_READ_DDR_INFO_1V8 0x49357#define MC_CMD_MUM_OUT_READ_DDR_INFO_SIZE_OFST 89358#define MC_CMD_MUM_OUT_READ_DDR_INFO_SIZE_LBN 249359#define MC_CMD_MUM_OUT_READ_DDR_INFO_SIZE_WIDTH 89360#define MC_CMD_MUM_OUT_READ_DDR_INFO_SPEED_OFST 89361#define MC_CMD_MUM_OUT_READ_DDR_INFO_SPEED_LBN 329362#define MC_CMD_MUM_OUT_READ_DDR_INFO_SPEED_WIDTH 169363#define MC_CMD_MUM_OUT_READ_DDR_INFO_STATE_OFST 89364#define MC_CMD_MUM_OUT_READ_DDR_INFO_STATE_LBN 489365#define MC_CMD_MUM_OUT_READ_DDR_INFO_STATE_WIDTH 49366/* enum: No module present */9367#define MC_CMD_MUM_OUT_READ_DDR_INFO_ABSENT 0x09368/* enum: Module present supported and powered on */9369#define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_POWERED 0x19370/* enum: Module present but bad type */9371#define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_TYPE 0x29372/* enum: Module present but incompatible voltage */9373#define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_VOLTAGE 0x39374/* enum: Module present but unknown SPD */9375#define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_SPD 0x49376/* enum: Module present but slot cannot support it */9377#define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_SLOT 0x59378/* enum: Modules may or may not be present, but cannot establish contact by I2C9379 */9380#define MC_CMD_MUM_OUT_READ_DDR_INFO_NOT_REACHABLE 0x69381#define MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED2_OFST 89382#define MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED2_LBN 529383#define MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED2_WIDTH 129384 9385/* MC_CMD_DYNAMIC_SENSORS_LIMITS structuredef: Set of sensor limits. This9386 * should match the equivalent structure in the sensor_query SPHINX service.9387 */9388#define MC_CMD_DYNAMIC_SENSORS_LIMITS_LEN 249389/* A value below this will trigger a warning event. */9390#define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_WARNING_OFST 09391#define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_WARNING_LEN 49392#define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_WARNING_LBN 09393#define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_WARNING_WIDTH 329394/* A value below this will trigger a critical event. */9395#define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_CRITICAL_OFST 49396#define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_CRITICAL_LEN 49397#define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_CRITICAL_LBN 329398#define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_CRITICAL_WIDTH 329399/* A value below this will shut down the card. */9400#define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_FATAL_OFST 89401#define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_FATAL_LEN 49402#define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_FATAL_LBN 649403#define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_FATAL_WIDTH 329404/* A value above this will trigger a warning event. */9405#define MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_WARNING_OFST 129406#define MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_WARNING_LEN 49407#define MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_WARNING_LBN 969408#define MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_WARNING_WIDTH 329409/* A value above this will trigger a critical event. */9410#define MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_CRITICAL_OFST 169411#define MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_CRITICAL_LEN 49412#define MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_CRITICAL_LBN 1289413#define MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_CRITICAL_WIDTH 329414/* A value above this will shut down the card. */9415#define MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_FATAL_OFST 209416#define MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_FATAL_LEN 49417#define MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_FATAL_LBN 1609418#define MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_FATAL_WIDTH 329419 9420/* MC_CMD_DYNAMIC_SENSORS_DESCRIPTION structuredef: Description of a sensor.9421 * This should match the equivalent structure in the sensor_query SPHINX9422 * service.9423 */9424#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_LEN 649425/* The handle used to identify the sensor in calls to9426 * MC_CMD_DYNAMIC_SENSORS_GET_VALUES9427 */9428#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_HANDLE_OFST 09429#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_HANDLE_LEN 49430#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_HANDLE_LBN 09431#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_HANDLE_WIDTH 329432/* A human-readable name for the sensor (zero terminated string, max 32 bytes)9433 */9434#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_NAME_OFST 49435#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_NAME_LEN 329436#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_NAME_LBN 329437#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_NAME_WIDTH 2569438/* The type of the sensor device, and by implication the unit of that the9439 * values will be reported in9440 */9441#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_TYPE_OFST 369442#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_TYPE_LEN 49443/* enum: A voltage sensor. Unit is mV */9444#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_VOLTAGE 0x09445/* enum: A current sensor. Unit is mA */9446#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_CURRENT 0x19447/* enum: A power sensor. Unit is mW */9448#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_POWER 0x29449/* enum: A temperature sensor. Unit is Celsius */9450#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_TEMPERATURE 0x39451/* enum: A cooling fan sensor. Unit is RPM */9452#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_FAN 0x49453#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_TYPE_LBN 2889454#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_TYPE_WIDTH 329455/* A single MC_CMD_DYNAMIC_SENSORS_LIMITS structure */9456#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_LIMITS_OFST 409457#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_LIMITS_LEN 249458#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_LIMITS_LBN 3209459#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_LIMITS_WIDTH 1929460 9461/* MC_CMD_DYNAMIC_SENSORS_READING structuredef: State and value of a sensor.9462 * This should match the equivalent structure in the sensor_query SPHINX9463 * service.9464 */9465#define MC_CMD_DYNAMIC_SENSORS_READING_LEN 129466/* The handle used to identify the sensor */9467#define MC_CMD_DYNAMIC_SENSORS_READING_HANDLE_OFST 09468#define MC_CMD_DYNAMIC_SENSORS_READING_HANDLE_LEN 49469#define MC_CMD_DYNAMIC_SENSORS_READING_HANDLE_LBN 09470#define MC_CMD_DYNAMIC_SENSORS_READING_HANDLE_WIDTH 329471/* The current value of the sensor */9472#define MC_CMD_DYNAMIC_SENSORS_READING_VALUE_OFST 49473#define MC_CMD_DYNAMIC_SENSORS_READING_VALUE_LEN 49474#define MC_CMD_DYNAMIC_SENSORS_READING_VALUE_LBN 329475#define MC_CMD_DYNAMIC_SENSORS_READING_VALUE_WIDTH 329476/* The sensor's condition, e.g. good, broken or removed */9477#define MC_CMD_DYNAMIC_SENSORS_READING_STATE_OFST 89478#define MC_CMD_DYNAMIC_SENSORS_READING_STATE_LEN 49479/* enum: Sensor working normally within limits */9480#define MC_CMD_DYNAMIC_SENSORS_READING_OK 0x09481/* enum: Warning threshold breached */9482#define MC_CMD_DYNAMIC_SENSORS_READING_WARNING 0x19483/* enum: Critical threshold breached */9484#define MC_CMD_DYNAMIC_SENSORS_READING_CRITICAL 0x29485/* enum: Fatal threshold breached */9486#define MC_CMD_DYNAMIC_SENSORS_READING_FATAL 0x39487/* enum: Sensor not working */9488#define MC_CMD_DYNAMIC_SENSORS_READING_BROKEN 0x49489/* enum: Sensor working but no reading available */9490#define MC_CMD_DYNAMIC_SENSORS_READING_NO_READING 0x59491/* enum: Sensor initialization failed */9492#define MC_CMD_DYNAMIC_SENSORS_READING_INIT_FAILED 0x69493#define MC_CMD_DYNAMIC_SENSORS_READING_STATE_LBN 649494#define MC_CMD_DYNAMIC_SENSORS_READING_STATE_WIDTH 329495 9496 9497/***********************************/9498/* MC_CMD_DYNAMIC_SENSORS_LIST9499 * Return a complete list of handles for sensors currently managed by the MC,9500 * and a generation count for this version of the sensor table. On systems9501 * advertising the DYNAMIC_SENSORS capability bit, this replaces the9502 * MC_CMD_READ_SENSORS command. On multi-MC systems this may include sensors9503 * added by the NMC.9504 *9505 * Sensor handles are persistent for the lifetime of the sensor and are used to9506 * identify sensors in MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS and9507 * MC_CMD_DYNAMIC_SENSORS_GET_VALUES.9508 *9509 * The generation count is maintained by the MC, is persistent across reboots9510 * and will be incremented each time the sensor table is modified. When the9511 * table is modified, a CODE_DYNAMIC_SENSORS_CHANGE event will be generated9512 * containing the new generation count. The driver should compare this against9513 * the current generation count, and if it is different, call9514 * MC_CMD_DYNAMIC_SENSORS_LIST again to update it's copy of the sensor table.9515 *9516 * The sensor count is provided to allow a future path to supporting more than9517 * MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_HANDLES_MAXNUM_MCDI2 sensors, i.e.9518 * the maximum number that will fit in a single response. As this is a fairly9519 * large number (253) it is not anticipated that this will be needed in the9520 * near future, so can currently be ignored.9521 *9522 * On Riverhead this command is implemented as a wrapper for `list` in the9523 * sensor_query SPHINX service.9524 */9525#define MC_CMD_DYNAMIC_SENSORS_LIST 0x669526#undef MC_CMD_0x66_PRIVILEGE_CTG9527 9528#define MC_CMD_0x66_PRIVILEGE_CTG SRIOV_CTG_GENERAL9529 9530/* MC_CMD_DYNAMIC_SENSORS_LIST_IN msgrequest */9531#define MC_CMD_DYNAMIC_SENSORS_LIST_IN_LEN 09532 9533/* MC_CMD_DYNAMIC_SENSORS_LIST_OUT msgresponse */9534#define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_LENMIN 89535#define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_LENMAX 2529536#define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_LENMAX_MCDI2 10209537#define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_LEN(num) (8+4*(num))9538#define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_HANDLES_NUM(len) (((len)-8)/4)9539/* Generation count, which will be updated each time a sensor is added to or9540 * removed from the MC sensor table.9541 */9542#define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_GENERATION_OFST 09543#define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_GENERATION_LEN 49544/* Number of sensors managed by the MC. Note that in principle, this can be9545 * larger than the size of the HANDLES array.9546 */9547#define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_COUNT_OFST 49548#define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_COUNT_LEN 49549/* Array of sensor handles */9550#define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_HANDLES_OFST 89551#define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_HANDLES_LEN 49552#define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_HANDLES_MINNUM 09553#define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_HANDLES_MAXNUM 619554#define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_HANDLES_MAXNUM_MCDI2 2539555 9556 9557/***********************************/9558/* MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS9559 * Get descriptions for a set of sensors, specified as an array of sensor9560 * handles as returned by MC_CMD_DYNAMIC_SENSORS_LIST9561 *9562 * Any handles which do not correspond to a sensor currently managed by the MC9563 * will be dropped from from the response. This may happen when a sensor table9564 * update is in progress, and effectively means the set of usable sensors is9565 * the intersection between the sets of sensors known to the driver and the MC.9566 *9567 * On Riverhead this command is implemented as a wrapper for9568 * `get_descriptions` in the sensor_query SPHINX service.9569 */9570#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS 0x679571#undef MC_CMD_0x67_PRIVILEGE_CTG9572 9573#define MC_CMD_0x67_PRIVILEGE_CTG SRIOV_CTG_GENERAL9574 9575/* MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN msgrequest */9576#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_LENMIN 09577#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_LENMAX 2529578#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_LENMAX_MCDI2 10209579#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_LEN(num) (0+4*(num))9580#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_HANDLES_NUM(len) (((len)-0)/4)9581/* Array of sensor handles */9582#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_HANDLES_OFST 09583#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_HANDLES_LEN 49584#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_HANDLES_MINNUM 09585#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_HANDLES_MAXNUM 639586#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_HANDLES_MAXNUM_MCDI2 2559587 9588/* MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT msgresponse */9589#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_LENMIN 09590#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_LENMAX 1929591#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_LENMAX_MCDI2 9609592#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_LEN(num) (0+64*(num))9593#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_SENSORS_NUM(len) (((len)-0)/64)9594/* Array of MC_CMD_DYNAMIC_SENSORS_DESCRIPTION structures */9595#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_SENSORS_OFST 09596#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_SENSORS_LEN 649597#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_SENSORS_MINNUM 09598#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_SENSORS_MAXNUM 39599#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_SENSORS_MAXNUM_MCDI2 159600 9601 9602/***********************************/9603/* MC_CMD_DYNAMIC_SENSORS_GET_READINGS9604 * Read the state and value for a set of sensors, specified as an array of9605 * sensor handles as returned by MC_CMD_DYNAMIC_SENSORS_LIST.9606 *9607 * In the case of a broken sensor, then the state of the response's9608 * MC_CMD_DYNAMIC_SENSORS_VALUE entry will be set to BROKEN, and any value9609 * provided should be treated as erroneous.9610 *9611 * Any handles which do not correspond to a sensor currently managed by the MC9612 * will be dropped from from the response. This may happen when a sensor table9613 * update is in progress, and effectively means the set of usable sensors is9614 * the intersection between the sets of sensors known to the driver and the MC.9615 *9616 * On Riverhead this command is implemented as a wrapper for `get_readings`9617 * in the sensor_query SPHINX service.9618 */9619#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS 0x689620#undef MC_CMD_0x68_PRIVILEGE_CTG9621 9622#define MC_CMD_0x68_PRIVILEGE_CTG SRIOV_CTG_GENERAL9623 9624/* MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN msgrequest */9625#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_LENMIN 09626#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_LENMAX 2529627#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_LENMAX_MCDI2 10209628#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_LEN(num) (0+4*(num))9629#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_HANDLES_NUM(len) (((len)-0)/4)9630/* Array of sensor handles */9631#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_HANDLES_OFST 09632#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_HANDLES_LEN 49633#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_HANDLES_MINNUM 09634#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_HANDLES_MAXNUM 639635#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_HANDLES_MAXNUM_MCDI2 2559636 9637/* MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT msgresponse */9638#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_LENMIN 09639#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_LENMAX 2529640#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_LENMAX_MCDI2 10209641#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_LEN(num) (0+12*(num))9642#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_VALUES_NUM(len) (((len)-0)/12)9643/* Array of MC_CMD_DYNAMIC_SENSORS_READING structures */9644#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_VALUES_OFST 09645#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_VALUES_LEN 129646#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_VALUES_MINNUM 09647#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_VALUES_MAXNUM 219648#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_VALUES_MAXNUM_MCDI2 859649 9650 9651/***********************************/9652/* MC_CMD_EVENT_CTRL9653 * Configure which categories of unsolicited events the driver expects to9654 * receive (Riverhead).9655 */9656#define MC_CMD_EVENT_CTRL 0x699657#undef MC_CMD_0x69_PRIVILEGE_CTG9658 9659#define MC_CMD_0x69_PRIVILEGE_CTG SRIOV_CTG_GENERAL9660 9661/* MC_CMD_EVENT_CTRL_IN msgrequest */9662#define MC_CMD_EVENT_CTRL_IN_LENMIN 09663#define MC_CMD_EVENT_CTRL_IN_LENMAX 2529664#define MC_CMD_EVENT_CTRL_IN_LENMAX_MCDI2 10209665#define MC_CMD_EVENT_CTRL_IN_LEN(num) (0+4*(num))9666#define MC_CMD_EVENT_CTRL_IN_EVENT_TYPE_NUM(len) (((len)-0)/4)9667/* Array of event categories for which the driver wishes to receive events. */9668#define MC_CMD_EVENT_CTRL_IN_EVENT_TYPE_OFST 09669#define MC_CMD_EVENT_CTRL_IN_EVENT_TYPE_LEN 49670#define MC_CMD_EVENT_CTRL_IN_EVENT_TYPE_MINNUM 09671#define MC_CMD_EVENT_CTRL_IN_EVENT_TYPE_MAXNUM 639672#define MC_CMD_EVENT_CTRL_IN_EVENT_TYPE_MAXNUM_MCDI2 2559673/* enum: Driver wishes to receive LINKCHANGE events. */9674#define MC_CMD_EVENT_CTRL_IN_MCDI_EVENT_CODE_LINKCHANGE 0x09675/* enum: Driver wishes to receive SENSOR_CHANGE and SENSOR_STATE_CHANGE events.9676 */9677#define MC_CMD_EVENT_CTRL_IN_MCDI_EVENT_CODE_SENSOREVT 0x19678/* enum: Driver wishes to receive receive errors. */9679#define MC_CMD_EVENT_CTRL_IN_MCDI_EVENT_CODE_RX_ERR 0x29680/* enum: Driver wishes to receive transmit errors. */9681#define MC_CMD_EVENT_CTRL_IN_MCDI_EVENT_CODE_TX_ERR 0x39682/* enum: Driver wishes to receive firmware alerts. */9683#define MC_CMD_EVENT_CTRL_IN_MCDI_EVENT_CODE_FWALERT 0x49684/* enum: Driver wishes to receive reboot events. */9685#define MC_CMD_EVENT_CTRL_IN_MCDI_EVENT_CODE_MC_REBOOT 0x59686 9687/* MC_CMD_EVENT_CTRL_OUT msgrequest */9688#define MC_CMD_EVENT_CTRL_OUT_LEN 09689 9690/* EVB_PORT_ID structuredef */9691#define EVB_PORT_ID_LEN 49692#define EVB_PORT_ID_PORT_ID_OFST 09693#define EVB_PORT_ID_PORT_ID_LEN 49694/* enum: An invalid port handle. */9695#define EVB_PORT_ID_NULL 0x09696/* enum: The port assigned to this function.. */9697#define EVB_PORT_ID_ASSIGNED 0x10000009698/* enum: External network port 0 */9699#define EVB_PORT_ID_MAC0 0x20000009700/* enum: External network port 1 */9701#define EVB_PORT_ID_MAC1 0x20000019702/* enum: External network port 2 */9703#define EVB_PORT_ID_MAC2 0x20000029704/* enum: External network port 3 */9705#define EVB_PORT_ID_MAC3 0x20000039706#define EVB_PORT_ID_PORT_ID_LBN 09707#define EVB_PORT_ID_PORT_ID_WIDTH 329708 9709/* EVB_VLAN_TAG structuredef */9710#define EVB_VLAN_TAG_LEN 29711/* The VLAN tag value */9712#define EVB_VLAN_TAG_VLAN_ID_LBN 09713#define EVB_VLAN_TAG_VLAN_ID_WIDTH 129714#define EVB_VLAN_TAG_MODE_LBN 129715#define EVB_VLAN_TAG_MODE_WIDTH 49716/* enum: Insert the VLAN. */9717#define EVB_VLAN_TAG_INSERT 0x09718/* enum: Replace the VLAN if already present. */9719#define EVB_VLAN_TAG_REPLACE 0x19720 9721/* BUFTBL_ENTRY structuredef */9722#define BUFTBL_ENTRY_LEN 129723/* the owner ID */9724#define BUFTBL_ENTRY_OID_OFST 09725#define BUFTBL_ENTRY_OID_LEN 29726#define BUFTBL_ENTRY_OID_LBN 09727#define BUFTBL_ENTRY_OID_WIDTH 169728/* the page parameter as one of ESE_DZ_SMC_PAGE_SIZE_ */9729#define BUFTBL_ENTRY_PGSZ_OFST 29730#define BUFTBL_ENTRY_PGSZ_LEN 29731#define BUFTBL_ENTRY_PGSZ_LBN 169732#define BUFTBL_ENTRY_PGSZ_WIDTH 169733/* the raw 64-bit address field from the SMC, not adjusted for page size */9734#define BUFTBL_ENTRY_RAWADDR_OFST 49735#define BUFTBL_ENTRY_RAWADDR_LEN 89736#define BUFTBL_ENTRY_RAWADDR_LO_OFST 49737#define BUFTBL_ENTRY_RAWADDR_LO_LEN 49738#define BUFTBL_ENTRY_RAWADDR_LO_LBN 329739#define BUFTBL_ENTRY_RAWADDR_LO_WIDTH 329740#define BUFTBL_ENTRY_RAWADDR_HI_OFST 89741#define BUFTBL_ENTRY_RAWADDR_HI_LEN 49742#define BUFTBL_ENTRY_RAWADDR_HI_LBN 649743#define BUFTBL_ENTRY_RAWADDR_HI_WIDTH 329744#define BUFTBL_ENTRY_RAWADDR_LBN 329745#define BUFTBL_ENTRY_RAWADDR_WIDTH 649746 9747/* NVRAM_PARTITION_TYPE structuredef */9748#define NVRAM_PARTITION_TYPE_LEN 29749#define NVRAM_PARTITION_TYPE_ID_OFST 09750#define NVRAM_PARTITION_TYPE_ID_LEN 29751/* enum: Primary MC firmware partition */9752#define NVRAM_PARTITION_TYPE_MC_FIRMWARE 0x1009753/* enum: NMC firmware partition (this is intentionally an alias of MC_FIRMWARE)9754 */9755#define NVRAM_PARTITION_TYPE_NMC_FIRMWARE 0x1009756/* enum: Secondary MC firmware partition */9757#define NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP 0x2009758/* enum: Expansion ROM partition */9759#define NVRAM_PARTITION_TYPE_EXPANSION_ROM 0x3009760/* enum: Static configuration TLV partition */9761#define NVRAM_PARTITION_TYPE_STATIC_CONFIG 0x4009762/* enum: Factory configuration TLV partition (this is intentionally an alias of9763 * STATIC_CONFIG)9764 */9765#define NVRAM_PARTITION_TYPE_FACTORY_CONFIG 0x4009766/* enum: Dynamic configuration TLV partition */9767#define NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG 0x5009768/* enum: User configuration TLV partition (this is intentionally an alias of9769 * DYNAMIC_CONFIG)9770 */9771#define NVRAM_PARTITION_TYPE_USER_CONFIG 0x5009772/* enum: Expansion ROM configuration data for port 0 */9773#define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0 0x6009774/* enum: Synonym for EXPROM_CONFIG_PORT0 as used in pmap files */9775#define NVRAM_PARTITION_TYPE_EXPROM_CONFIG 0x6009776/* enum: Expansion ROM configuration data for port 1 */9777#define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1 0x6019778/* enum: Expansion ROM configuration data for port 2 */9779#define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2 0x6029780/* enum: Expansion ROM configuration data for port 3 */9781#define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3 0x6039782/* enum: Non-volatile log output partition */9783#define NVRAM_PARTITION_TYPE_LOG 0x7009784/* enum: Non-volatile log output partition for NMC firmware (this is9785 * intentionally an alias of LOG)9786 */9787#define NVRAM_PARTITION_TYPE_NMC_LOG 0x7009788/* enum: Non-volatile log output of second core on dual-core device */9789#define NVRAM_PARTITION_TYPE_LOG_SLAVE 0x7019790/* enum: Device state dump output partition */9791#define NVRAM_PARTITION_TYPE_DUMP 0x8009792/* enum: Crash log partition for NMC firmware */9793#define NVRAM_PARTITION_TYPE_NMC_CRASH_LOG 0x8019794/* enum: Application license key storage partition */9795#define NVRAM_PARTITION_TYPE_LICENSE 0x9009796/* enum: Start of range used for PHY partitions (low 8 bits are the PHY ID) */9797#define NVRAM_PARTITION_TYPE_PHY_MIN 0xa009798/* enum: End of range used for PHY partitions (low 8 bits are the PHY ID) */9799#define NVRAM_PARTITION_TYPE_PHY_MAX 0xaff9800/* enum: Primary FPGA partition */9801#define NVRAM_PARTITION_TYPE_FPGA 0xb009802/* enum: Secondary FPGA partition */9803#define NVRAM_PARTITION_TYPE_FPGA_BACKUP 0xb019804/* enum: FC firmware partition */9805#define NVRAM_PARTITION_TYPE_FC_FIRMWARE 0xb029806/* enum: FC License partition */9807#define NVRAM_PARTITION_TYPE_FC_LICENSE 0xb039808/* enum: Non-volatile log output partition for FC */9809#define NVRAM_PARTITION_TYPE_FC_LOG 0xb049810/* enum: FPGA Stage 1 bitstream */9811#define NVRAM_PARTITION_TYPE_FPGA_STAGE1 0xb059812/* enum: FPGA Stage 2 bitstream */9813#define NVRAM_PARTITION_TYPE_FPGA_STAGE2 0xb069814/* enum: FPGA User XCLBIN / Programmable Region 0 bitstream */9815#define NVRAM_PARTITION_TYPE_FPGA_REGION0 0xb079816/* enum: FPGA User XCLBIN (this is intentionally an alias of FPGA_REGION0) */9817#define NVRAM_PARTITION_TYPE_FPGA_XCLBIN_USER 0xb079818/* enum: FPGA jump instruction (a.k.a. boot) partition to select Stage19819 * bitstream9820 */9821#define NVRAM_PARTITION_TYPE_FPGA_JUMP 0xb089822/* enum: FPGA Validate XCLBIN */9823#define NVRAM_PARTITION_TYPE_FPGA_XCLBIN_VALIDATE 0xb099824/* enum: FPGA XOCL Configuration information */9825#define NVRAM_PARTITION_TYPE_FPGA_XOCL_CONFIG 0xb0a9826/* enum: MUM firmware partition */9827#define NVRAM_PARTITION_TYPE_MUM_FIRMWARE 0xc009828/* enum: SUC firmware partition (this is intentionally an alias of9829 * MUM_FIRMWARE)9830 */9831#define NVRAM_PARTITION_TYPE_SUC_FIRMWARE 0xc009832/* enum: MUM Non-volatile log output partition. */9833#define NVRAM_PARTITION_TYPE_MUM_LOG 0xc019834/* enum: SUC Non-volatile log output partition (this is intentionally an alias9835 * of MUM_LOG).9836 */9837#define NVRAM_PARTITION_TYPE_SUC_LOG 0xc019838/* enum: MUM Application table partition. */9839#define NVRAM_PARTITION_TYPE_MUM_APPTABLE 0xc029840/* enum: MUM boot rom partition. */9841#define NVRAM_PARTITION_TYPE_MUM_BOOT_ROM 0xc039842/* enum: MUM production signatures & calibration rom partition. */9843#define NVRAM_PARTITION_TYPE_MUM_PROD_ROM 0xc049844/* enum: MUM user signatures & calibration rom partition. */9845#define NVRAM_PARTITION_TYPE_MUM_USER_ROM 0xc059846/* enum: MUM fuses and lockbits partition. */9847#define NVRAM_PARTITION_TYPE_MUM_FUSELOCK 0xc069848/* enum: UEFI expansion ROM if separate from PXE */9849#define NVRAM_PARTITION_TYPE_EXPANSION_UEFI 0xd009850/* enum: Used by the expansion ROM for logging */9851#define NVRAM_PARTITION_TYPE_PXE_LOG 0x10009852/* enum: Non-volatile log output partition for Expansion ROM (this is9853 * intentionally an alias of PXE_LOG).9854 */9855#define NVRAM_PARTITION_TYPE_EXPROM_LOG 0x10009856/* enum: Used for XIP code of shmbooted images */9857#define NVRAM_PARTITION_TYPE_XIP_SCRATCH 0x11009858/* enum: Spare partition 2 */9859#define NVRAM_PARTITION_TYPE_SPARE_2 0x12009860/* enum: Manufacturing partition. Used during manufacture to pass information9861 * between XJTAG and Manftest.9862 */9863#define NVRAM_PARTITION_TYPE_MANUFACTURING 0x13009864/* enum: Deployment configuration TLV partition (this is intentionally an alias9865 * of MANUFACTURING)9866 */9867#define NVRAM_PARTITION_TYPE_DEPLOYMENT_CONFIG 0x13009868/* enum: Spare partition 4 */9869#define NVRAM_PARTITION_TYPE_SPARE_4 0x14009870/* enum: Spare partition 5 */9871#define NVRAM_PARTITION_TYPE_SPARE_5 0x15009872/* enum: Partition for reporting MC status. See mc_flash_layout.h9873 * medford_mc_status_hdr_t for layout on Medford.9874 */9875#define NVRAM_PARTITION_TYPE_STATUS 0x16009876/* enum: Spare partition 13 */9877#define NVRAM_PARTITION_TYPE_SPARE_13 0x17009878/* enum: Spare partition 14 */9879#define NVRAM_PARTITION_TYPE_SPARE_14 0x18009880/* enum: Spare partition 15 */9881#define NVRAM_PARTITION_TYPE_SPARE_15 0x19009882/* enum: Spare partition 16 */9883#define NVRAM_PARTITION_TYPE_SPARE_16 0x1a009884/* enum: Factory defaults for dynamic configuration */9885#define NVRAM_PARTITION_TYPE_DYNCONFIG_DEFAULTS 0x1b009886/* enum: Factory defaults for expansion ROM configuration */9887#define NVRAM_PARTITION_TYPE_ROMCONFIG_DEFAULTS 0x1c009888/* enum: Field Replaceable Unit inventory information for use on IPMI9889 * platforms. See SF-119124-PS. The STATIC_CONFIG partition may contain a9890 * subset of the information stored in this partition.9891 */9892#define NVRAM_PARTITION_TYPE_FRU_INFORMATION 0x1d009893/* enum: Bundle image partition */9894#define NVRAM_PARTITION_TYPE_BUNDLE 0x1e009895/* enum: Bundle metadata partition that holds additional information related to9896 * a bundle update in TLV format9897 */9898#define NVRAM_PARTITION_TYPE_BUNDLE_METADATA 0x1e019899/* enum: Bundle update non-volatile log output partition */9900#define NVRAM_PARTITION_TYPE_BUNDLE_LOG 0x1e029901/* enum: Partition for Solarflare gPXE bootrom installed via Bundle update. */9902#define NVRAM_PARTITION_TYPE_EXPANSION_ROM_INTERNAL 0x1e039903/* enum: Partition to store ASN.1 format Bundle Signature for checking. */9904#define NVRAM_PARTITION_TYPE_BUNDLE_SIGNATURE 0x1e049905/* enum: Test partition on SmartNIC system microcontroller (SUC) */9906#define NVRAM_PARTITION_TYPE_SUC_TEST 0x1f009907/* enum: System microcontroller access to primary FPGA flash. */9908#define NVRAM_PARTITION_TYPE_SUC_FPGA_PRIMARY 0x1f019909/* enum: System microcontroller access to secondary FPGA flash (if present) */9910#define NVRAM_PARTITION_TYPE_SUC_FPGA_SECONDARY 0x1f029911/* enum: System microcontroller access to primary System-on-Chip flash */9912#define NVRAM_PARTITION_TYPE_SUC_SOC_PRIMARY 0x1f039913/* enum: System microcontroller access to secondary System-on-Chip flash (if9914 * present)9915 */9916#define NVRAM_PARTITION_TYPE_SUC_SOC_SECONDARY 0x1f049917/* enum: System microcontroller critical failure logs. Contains structured9918 * details of sensors leading up to a critical failure (where the board is shut9919 * down).9920 */9921#define NVRAM_PARTITION_TYPE_SUC_FAILURE_LOG 0x1f059922/* enum: System-on-Chip configuration information (see XN-200467-PS). */9923#define NVRAM_PARTITION_TYPE_SUC_SOC_CONFIG 0x1f079924/* enum: System-on-Chip update information. */9925#define NVRAM_PARTITION_TYPE_SOC_UPDATE 0x20039926/* enum: Start of reserved value range (firmware may use for any purpose) */9927#define NVRAM_PARTITION_TYPE_RESERVED_VALUES_MIN 0xff009928/* enum: End of reserved value range (firmware may use for any purpose) */9929#define NVRAM_PARTITION_TYPE_RESERVED_VALUES_MAX 0xfffd9930/* enum: Recovery partition map (provided if real map is missing or corrupt) */9931#define NVRAM_PARTITION_TYPE_RECOVERY_MAP 0xfffe9932/* enum: Recovery Flash Partition Table, see SF-122606-TC. (this is9933 * intentionally an alias of RECOVERY_MAP)9934 */9935#define NVRAM_PARTITION_TYPE_RECOVERY_FPT 0xfffe9936/* enum: Partition map (real map as stored in flash) */9937#define NVRAM_PARTITION_TYPE_PARTITION_MAP 0xffff9938/* enum: Flash Partition Table, see SF-122606-TC. (this is intentionally an9939 * alias of PARTITION_MAP)9940 */9941#define NVRAM_PARTITION_TYPE_FPT 0xffff9942#define NVRAM_PARTITION_TYPE_ID_LBN 09943#define NVRAM_PARTITION_TYPE_ID_WIDTH 169944 9945/* LICENSED_APP_ID structuredef */9946#define LICENSED_APP_ID_LEN 49947#define LICENSED_APP_ID_ID_OFST 09948#define LICENSED_APP_ID_ID_LEN 49949/* enum: OpenOnload */9950#define LICENSED_APP_ID_ONLOAD 0x19951/* enum: PTP timestamping */9952#define LICENSED_APP_ID_PTP 0x29953/* enum: SolarCapture Pro */9954#define LICENSED_APP_ID_SOLARCAPTURE_PRO 0x49955/* enum: SolarSecure filter engine */9956#define LICENSED_APP_ID_SOLARSECURE 0x89957/* enum: Performance monitor */9958#define LICENSED_APP_ID_PERF_MONITOR 0x109959/* enum: SolarCapture Live */9960#define LICENSED_APP_ID_SOLARCAPTURE_LIVE 0x209961/* enum: Capture SolarSystem */9962#define LICENSED_APP_ID_CAPTURE_SOLARSYSTEM 0x409963/* enum: Network Access Control */9964#define LICENSED_APP_ID_NETWORK_ACCESS_CONTROL 0x809965/* enum: TCP Direct */9966#define LICENSED_APP_ID_TCP_DIRECT 0x1009967/* enum: Low Latency */9968#define LICENSED_APP_ID_LOW_LATENCY 0x2009969/* enum: SolarCapture Tap */9970#define LICENSED_APP_ID_SOLARCAPTURE_TAP 0x4009971/* enum: Capture SolarSystem 40G */9972#define LICENSED_APP_ID_CAPTURE_SOLARSYSTEM_40G 0x8009973/* enum: Capture SolarSystem 1G */9974#define LICENSED_APP_ID_CAPTURE_SOLARSYSTEM_1G 0x10009975/* enum: ScaleOut Onload */9976#define LICENSED_APP_ID_SCALEOUT_ONLOAD 0x20009977/* enum: SCS Network Analytics Dashboard */9978#define LICENSED_APP_ID_DSHBRD 0x40009979/* enum: SolarCapture Trading Analytics */9980#define LICENSED_APP_ID_SCATRD 0x80009981#define LICENSED_APP_ID_ID_LBN 09982#define LICENSED_APP_ID_ID_WIDTH 329983 9984/* LICENSED_FEATURES structuredef */9985#define LICENSED_FEATURES_LEN 89986/* Bitmask of licensed firmware features */9987#define LICENSED_FEATURES_MASK_OFST 09988#define LICENSED_FEATURES_MASK_LEN 89989#define LICENSED_FEATURES_MASK_LO_OFST 09990#define LICENSED_FEATURES_MASK_LO_LEN 49991#define LICENSED_FEATURES_MASK_LO_LBN 09992#define LICENSED_FEATURES_MASK_LO_WIDTH 329993#define LICENSED_FEATURES_MASK_HI_OFST 49994#define LICENSED_FEATURES_MASK_HI_LEN 49995#define LICENSED_FEATURES_MASK_HI_LBN 329996#define LICENSED_FEATURES_MASK_HI_WIDTH 329997#define LICENSED_FEATURES_RX_CUT_THROUGH_OFST 09998#define LICENSED_FEATURES_RX_CUT_THROUGH_LBN 09999#define LICENSED_FEATURES_RX_CUT_THROUGH_WIDTH 110000#define LICENSED_FEATURES_PIO_OFST 010001#define LICENSED_FEATURES_PIO_LBN 110002#define LICENSED_FEATURES_PIO_WIDTH 110003#define LICENSED_FEATURES_EVQ_TIMER_OFST 010004#define LICENSED_FEATURES_EVQ_TIMER_LBN 210005#define LICENSED_FEATURES_EVQ_TIMER_WIDTH 110006#define LICENSED_FEATURES_CLOCK_OFST 010007#define LICENSED_FEATURES_CLOCK_LBN 310008#define LICENSED_FEATURES_CLOCK_WIDTH 110009#define LICENSED_FEATURES_RX_TIMESTAMPS_OFST 010010#define LICENSED_FEATURES_RX_TIMESTAMPS_LBN 410011#define LICENSED_FEATURES_RX_TIMESTAMPS_WIDTH 110012#define LICENSED_FEATURES_TX_TIMESTAMPS_OFST 010013#define LICENSED_FEATURES_TX_TIMESTAMPS_LBN 510014#define LICENSED_FEATURES_TX_TIMESTAMPS_WIDTH 110015#define LICENSED_FEATURES_RX_SNIFF_OFST 010016#define LICENSED_FEATURES_RX_SNIFF_LBN 610017#define LICENSED_FEATURES_RX_SNIFF_WIDTH 110018#define LICENSED_FEATURES_TX_SNIFF_OFST 010019#define LICENSED_FEATURES_TX_SNIFF_LBN 710020#define LICENSED_FEATURES_TX_SNIFF_WIDTH 110021#define LICENSED_FEATURES_PROXY_FILTER_OPS_OFST 010022#define LICENSED_FEATURES_PROXY_FILTER_OPS_LBN 810023#define LICENSED_FEATURES_PROXY_FILTER_OPS_WIDTH 110024#define LICENSED_FEATURES_EVENT_CUT_THROUGH_OFST 010025#define LICENSED_FEATURES_EVENT_CUT_THROUGH_LBN 910026#define LICENSED_FEATURES_EVENT_CUT_THROUGH_WIDTH 110027#define LICENSED_FEATURES_MASK_LBN 010028#define LICENSED_FEATURES_MASK_WIDTH 6410029 10030/* LICENSED_V3_APPS structuredef */10031#define LICENSED_V3_APPS_LEN 810032/* Bitmask of licensed applications */10033#define LICENSED_V3_APPS_MASK_OFST 010034#define LICENSED_V3_APPS_MASK_LEN 810035#define LICENSED_V3_APPS_MASK_LO_OFST 010036#define LICENSED_V3_APPS_MASK_LO_LEN 410037#define LICENSED_V3_APPS_MASK_LO_LBN 010038#define LICENSED_V3_APPS_MASK_LO_WIDTH 3210039#define LICENSED_V3_APPS_MASK_HI_OFST 410040#define LICENSED_V3_APPS_MASK_HI_LEN 410041#define LICENSED_V3_APPS_MASK_HI_LBN 3210042#define LICENSED_V3_APPS_MASK_HI_WIDTH 3210043#define LICENSED_V3_APPS_ONLOAD_OFST 010044#define LICENSED_V3_APPS_ONLOAD_LBN 010045#define LICENSED_V3_APPS_ONLOAD_WIDTH 110046#define LICENSED_V3_APPS_PTP_OFST 010047#define LICENSED_V3_APPS_PTP_LBN 110048#define LICENSED_V3_APPS_PTP_WIDTH 110049#define LICENSED_V3_APPS_SOLARCAPTURE_PRO_OFST 010050#define LICENSED_V3_APPS_SOLARCAPTURE_PRO_LBN 210051#define LICENSED_V3_APPS_SOLARCAPTURE_PRO_WIDTH 110052#define LICENSED_V3_APPS_SOLARSECURE_OFST 010053#define LICENSED_V3_APPS_SOLARSECURE_LBN 310054#define LICENSED_V3_APPS_SOLARSECURE_WIDTH 110055#define LICENSED_V3_APPS_PERF_MONITOR_OFST 010056#define LICENSED_V3_APPS_PERF_MONITOR_LBN 410057#define LICENSED_V3_APPS_PERF_MONITOR_WIDTH 110058#define LICENSED_V3_APPS_SOLARCAPTURE_LIVE_OFST 010059#define LICENSED_V3_APPS_SOLARCAPTURE_LIVE_LBN 510060#define LICENSED_V3_APPS_SOLARCAPTURE_LIVE_WIDTH 110061#define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_OFST 010062#define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_LBN 610063#define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_WIDTH 110064#define LICENSED_V3_APPS_NETWORK_ACCESS_CONTROL_OFST 010065#define LICENSED_V3_APPS_NETWORK_ACCESS_CONTROL_LBN 710066#define LICENSED_V3_APPS_NETWORK_ACCESS_CONTROL_WIDTH 110067#define LICENSED_V3_APPS_TCP_DIRECT_OFST 010068#define LICENSED_V3_APPS_TCP_DIRECT_LBN 810069#define LICENSED_V3_APPS_TCP_DIRECT_WIDTH 110070#define LICENSED_V3_APPS_LOW_LATENCY_OFST 010071#define LICENSED_V3_APPS_LOW_LATENCY_LBN 910072#define LICENSED_V3_APPS_LOW_LATENCY_WIDTH 110073#define LICENSED_V3_APPS_SOLARCAPTURE_TAP_OFST 010074#define LICENSED_V3_APPS_SOLARCAPTURE_TAP_LBN 1010075#define LICENSED_V3_APPS_SOLARCAPTURE_TAP_WIDTH 110076#define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_40G_OFST 010077#define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_40G_LBN 1110078#define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_40G_WIDTH 110079#define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_1G_OFST 010080#define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_1G_LBN 1210081#define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_1G_WIDTH 110082#define LICENSED_V3_APPS_SCALEOUT_ONLOAD_OFST 010083#define LICENSED_V3_APPS_SCALEOUT_ONLOAD_LBN 1310084#define LICENSED_V3_APPS_SCALEOUT_ONLOAD_WIDTH 110085#define LICENSED_V3_APPS_DSHBRD_OFST 010086#define LICENSED_V3_APPS_DSHBRD_LBN 1410087#define LICENSED_V3_APPS_DSHBRD_WIDTH 110088#define LICENSED_V3_APPS_SCATRD_OFST 010089#define LICENSED_V3_APPS_SCATRD_LBN 1510090#define LICENSED_V3_APPS_SCATRD_WIDTH 110091#define LICENSED_V3_APPS_MASK_LBN 010092#define LICENSED_V3_APPS_MASK_WIDTH 6410093 10094/* LICENSED_V3_FEATURES structuredef */10095#define LICENSED_V3_FEATURES_LEN 810096/* Bitmask of licensed firmware features */10097#define LICENSED_V3_FEATURES_MASK_OFST 010098#define LICENSED_V3_FEATURES_MASK_LEN 810099#define LICENSED_V3_FEATURES_MASK_LO_OFST 010100#define LICENSED_V3_FEATURES_MASK_LO_LEN 410101#define LICENSED_V3_FEATURES_MASK_LO_LBN 010102#define LICENSED_V3_FEATURES_MASK_LO_WIDTH 3210103#define LICENSED_V3_FEATURES_MASK_HI_OFST 410104#define LICENSED_V3_FEATURES_MASK_HI_LEN 410105#define LICENSED_V3_FEATURES_MASK_HI_LBN 3210106#define LICENSED_V3_FEATURES_MASK_HI_WIDTH 3210107#define LICENSED_V3_FEATURES_RX_CUT_THROUGH_OFST 010108#define LICENSED_V3_FEATURES_RX_CUT_THROUGH_LBN 010109#define LICENSED_V3_FEATURES_RX_CUT_THROUGH_WIDTH 110110#define LICENSED_V3_FEATURES_PIO_OFST 010111#define LICENSED_V3_FEATURES_PIO_LBN 110112#define LICENSED_V3_FEATURES_PIO_WIDTH 110113#define LICENSED_V3_FEATURES_EVQ_TIMER_OFST 010114#define LICENSED_V3_FEATURES_EVQ_TIMER_LBN 210115#define LICENSED_V3_FEATURES_EVQ_TIMER_WIDTH 110116#define LICENSED_V3_FEATURES_CLOCK_OFST 010117#define LICENSED_V3_FEATURES_CLOCK_LBN 310118#define LICENSED_V3_FEATURES_CLOCK_WIDTH 110119#define LICENSED_V3_FEATURES_RX_TIMESTAMPS_OFST 010120#define LICENSED_V3_FEATURES_RX_TIMESTAMPS_LBN 410121#define LICENSED_V3_FEATURES_RX_TIMESTAMPS_WIDTH 110122#define LICENSED_V3_FEATURES_TX_TIMESTAMPS_OFST 010123#define LICENSED_V3_FEATURES_TX_TIMESTAMPS_LBN 510124#define LICENSED_V3_FEATURES_TX_TIMESTAMPS_WIDTH 110125#define LICENSED_V3_FEATURES_RX_SNIFF_OFST 010126#define LICENSED_V3_FEATURES_RX_SNIFF_LBN 610127#define LICENSED_V3_FEATURES_RX_SNIFF_WIDTH 110128#define LICENSED_V3_FEATURES_TX_SNIFF_OFST 010129#define LICENSED_V3_FEATURES_TX_SNIFF_LBN 710130#define LICENSED_V3_FEATURES_TX_SNIFF_WIDTH 110131#define LICENSED_V3_FEATURES_PROXY_FILTER_OPS_OFST 010132#define LICENSED_V3_FEATURES_PROXY_FILTER_OPS_LBN 810133#define LICENSED_V3_FEATURES_PROXY_FILTER_OPS_WIDTH 110134#define LICENSED_V3_FEATURES_EVENT_CUT_THROUGH_OFST 010135#define LICENSED_V3_FEATURES_EVENT_CUT_THROUGH_LBN 910136#define LICENSED_V3_FEATURES_EVENT_CUT_THROUGH_WIDTH 110137#define LICENSED_V3_FEATURES_MASK_LBN 010138#define LICENSED_V3_FEATURES_MASK_WIDTH 6410139 10140/* TX_TIMESTAMP_EVENT structuredef */10141#define TX_TIMESTAMP_EVENT_LEN 610142/* lower 16 bits of timestamp data */10143#define TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_OFST 010144#define TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_LEN 210145#define TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_LBN 010146#define TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_WIDTH 1610147/* Type of TX event, ordinary TX completion, low or high part of TX timestamp10148 */10149#define TX_TIMESTAMP_EVENT_TX_EV_TYPE_OFST 310150#define TX_TIMESTAMP_EVENT_TX_EV_TYPE_LEN 110151/* enum: This is a TX completion event, not a timestamp */10152#define TX_TIMESTAMP_EVENT_TX_EV_COMPLETION 0x010153/* enum: This is a TX completion event for a CTPIO transmit. The event format10154 * is the same as for TX_EV_COMPLETION.10155 */10156#define TX_TIMESTAMP_EVENT_TX_EV_CTPIO_COMPLETION 0x1110157/* enum: This is the low part of a TX timestamp for a CTPIO transmission. The10158 * event format is the same as for TX_EV_TSTAMP_LO10159 */10160#define TX_TIMESTAMP_EVENT_TX_EV_CTPIO_TS_LO 0x1210161/* enum: This is the high part of a TX timestamp for a CTPIO transmission. The10162 * event format is the same as for TX_EV_TSTAMP_HI10163 */10164#define TX_TIMESTAMP_EVENT_TX_EV_CTPIO_TS_HI 0x1310165/* enum: This is the low part of a TX timestamp event */10166#define TX_TIMESTAMP_EVENT_TX_EV_TSTAMP_LO 0x5110167/* enum: This is the high part of a TX timestamp event */10168#define TX_TIMESTAMP_EVENT_TX_EV_TSTAMP_HI 0x5210169#define TX_TIMESTAMP_EVENT_TX_EV_TYPE_LBN 2410170#define TX_TIMESTAMP_EVENT_TX_EV_TYPE_WIDTH 810171/* upper 16 bits of timestamp data */10172#define TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_OFST 410173#define TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_LEN 210174#define TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_LBN 3210175#define TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_WIDTH 1610176 10177/* RSS_MODE structuredef */10178#define RSS_MODE_LEN 110179/* The RSS mode for a particular packet type is a value from 0 - 15 which can10180 * be considered as 4 bits selecting which fields are included in the hash. (A10181 * value 0 effectively disables RSS spreading for the packet type.) The YAML10182 * generation tools require this structure to be a whole number of bytes wide,10183 * but only 4 bits are relevant.10184 */10185#define RSS_MODE_HASH_SELECTOR_OFST 010186#define RSS_MODE_HASH_SELECTOR_LEN 110187#define RSS_MODE_HASH_SRC_ADDR_OFST 010188#define RSS_MODE_HASH_SRC_ADDR_LBN 010189#define RSS_MODE_HASH_SRC_ADDR_WIDTH 110190#define RSS_MODE_HASH_DST_ADDR_OFST 010191#define RSS_MODE_HASH_DST_ADDR_LBN 110192#define RSS_MODE_HASH_DST_ADDR_WIDTH 110193#define RSS_MODE_HASH_SRC_PORT_OFST 010194#define RSS_MODE_HASH_SRC_PORT_LBN 210195#define RSS_MODE_HASH_SRC_PORT_WIDTH 110196#define RSS_MODE_HASH_DST_PORT_OFST 010197#define RSS_MODE_HASH_DST_PORT_LBN 310198#define RSS_MODE_HASH_DST_PORT_WIDTH 110199#define RSS_MODE_HASH_SELECTOR_LBN 010200#define RSS_MODE_HASH_SELECTOR_WIDTH 810201 10202/* CTPIO_STATS_MAP structuredef */10203#define CTPIO_STATS_MAP_LEN 410204/* The (function relative) VI number */10205#define CTPIO_STATS_MAP_VI_OFST 010206#define CTPIO_STATS_MAP_VI_LEN 210207#define CTPIO_STATS_MAP_VI_LBN 010208#define CTPIO_STATS_MAP_VI_WIDTH 1610209/* The target bucket for the VI */10210#define CTPIO_STATS_MAP_BUCKET_OFST 210211#define CTPIO_STATS_MAP_BUCKET_LEN 210212#define CTPIO_STATS_MAP_BUCKET_LBN 1610213#define CTPIO_STATS_MAP_BUCKET_WIDTH 1610214 10215 10216/***********************************/10217/* MC_CMD_READ_REGS10218 * Get a dump of the MCPU registers10219 */10220#define MC_CMD_READ_REGS 0x5010221#undef MC_CMD_0x50_PRIVILEGE_CTG10222 10223#define MC_CMD_0x50_PRIVILEGE_CTG SRIOV_CTG_INSECURE10224 10225/* MC_CMD_READ_REGS_IN msgrequest */10226#define MC_CMD_READ_REGS_IN_LEN 010227 10228/* MC_CMD_READ_REGS_OUT msgresponse */10229#define MC_CMD_READ_REGS_OUT_LEN 30810230/* Whether the corresponding register entry contains a valid value */10231#define MC_CMD_READ_REGS_OUT_MASK_OFST 010232#define MC_CMD_READ_REGS_OUT_MASK_LEN 1610233/* Same order as MIPS GDB (r0-r31, sr, lo, hi, bad, cause, 32 x float, fsr,10234 * fir, fp)10235 */10236#define MC_CMD_READ_REGS_OUT_REGS_OFST 1610237#define MC_CMD_READ_REGS_OUT_REGS_LEN 410238#define MC_CMD_READ_REGS_OUT_REGS_NUM 7310239 10240 10241/***********************************/10242/* MC_CMD_INIT_EVQ10243 * Set up an event queue according to the supplied parameters. The IN arguments10244 * end with an address for each 4k of host memory required to back the EVQ.10245 */10246#define MC_CMD_INIT_EVQ 0x8010247#undef MC_CMD_0x80_PRIVILEGE_CTG10248 10249#define MC_CMD_0x80_PRIVILEGE_CTG SRIOV_CTG_GENERAL10250 10251/* MC_CMD_INIT_EVQ_IN msgrequest */10252#define MC_CMD_INIT_EVQ_IN_LENMIN 4410253#define MC_CMD_INIT_EVQ_IN_LENMAX 54810254#define MC_CMD_INIT_EVQ_IN_LENMAX_MCDI2 54810255#define MC_CMD_INIT_EVQ_IN_LEN(num) (36+8*(num))10256#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_NUM(len) (((len)-36)/8)10257/* Size, in entries */10258#define MC_CMD_INIT_EVQ_IN_SIZE_OFST 010259#define MC_CMD_INIT_EVQ_IN_SIZE_LEN 410260/* Desired instance. Must be set to a specific instance, which is a function10261 * local queue index. The calling client must be the currently-assigned user of10262 * this VI (see MC_CMD_SET_VI_USER).10263 */10264#define MC_CMD_INIT_EVQ_IN_INSTANCE_OFST 410265#define MC_CMD_INIT_EVQ_IN_INSTANCE_LEN 410266/* The initial timer value. The load value is ignored if the timer mode is DIS.10267 */10268#define MC_CMD_INIT_EVQ_IN_TMR_LOAD_OFST 810269#define MC_CMD_INIT_EVQ_IN_TMR_LOAD_LEN 410270/* The reload value is ignored in one-shot modes */10271#define MC_CMD_INIT_EVQ_IN_TMR_RELOAD_OFST 1210272#define MC_CMD_INIT_EVQ_IN_TMR_RELOAD_LEN 410273/* tbd */10274#define MC_CMD_INIT_EVQ_IN_FLAGS_OFST 1610275#define MC_CMD_INIT_EVQ_IN_FLAGS_LEN 410276#define MC_CMD_INIT_EVQ_IN_FLAG_INTERRUPTING_OFST 1610277#define MC_CMD_INIT_EVQ_IN_FLAG_INTERRUPTING_LBN 010278#define MC_CMD_INIT_EVQ_IN_FLAG_INTERRUPTING_WIDTH 110279#define MC_CMD_INIT_EVQ_IN_FLAG_RPTR_DOS_OFST 1610280#define MC_CMD_INIT_EVQ_IN_FLAG_RPTR_DOS_LBN 110281#define MC_CMD_INIT_EVQ_IN_FLAG_RPTR_DOS_WIDTH 110282#define MC_CMD_INIT_EVQ_IN_FLAG_INT_ARMD_OFST 1610283#define MC_CMD_INIT_EVQ_IN_FLAG_INT_ARMD_LBN 210284#define MC_CMD_INIT_EVQ_IN_FLAG_INT_ARMD_WIDTH 110285#define MC_CMD_INIT_EVQ_IN_FLAG_CUT_THRU_OFST 1610286#define MC_CMD_INIT_EVQ_IN_FLAG_CUT_THRU_LBN 310287#define MC_CMD_INIT_EVQ_IN_FLAG_CUT_THRU_WIDTH 110288#define MC_CMD_INIT_EVQ_IN_FLAG_RX_MERGE_OFST 1610289#define MC_CMD_INIT_EVQ_IN_FLAG_RX_MERGE_LBN 410290#define MC_CMD_INIT_EVQ_IN_FLAG_RX_MERGE_WIDTH 110291#define MC_CMD_INIT_EVQ_IN_FLAG_TX_MERGE_OFST 1610292#define MC_CMD_INIT_EVQ_IN_FLAG_TX_MERGE_LBN 510293#define MC_CMD_INIT_EVQ_IN_FLAG_TX_MERGE_WIDTH 110294#define MC_CMD_INIT_EVQ_IN_FLAG_USE_TIMER_OFST 1610295#define MC_CMD_INIT_EVQ_IN_FLAG_USE_TIMER_LBN 610296#define MC_CMD_INIT_EVQ_IN_FLAG_USE_TIMER_WIDTH 110297#define MC_CMD_INIT_EVQ_IN_TMR_MODE_OFST 2010298#define MC_CMD_INIT_EVQ_IN_TMR_MODE_LEN 410299/* enum: Disabled */10300#define MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS 0x010301/* enum: Immediate */10302#define MC_CMD_INIT_EVQ_IN_TMR_IMMED_START 0x110303/* enum: Triggered */10304#define MC_CMD_INIT_EVQ_IN_TMR_TRIG_START 0x210305/* enum: Hold-off */10306#define MC_CMD_INIT_EVQ_IN_TMR_INT_HLDOFF 0x310307/* Target EVQ for wakeups if in wakeup mode. */10308#define MC_CMD_INIT_EVQ_IN_TARGET_EVQ_OFST 2410309#define MC_CMD_INIT_EVQ_IN_TARGET_EVQ_LEN 410310/* Target interrupt if in interrupting mode (note union with target EVQ). Use10311 * MC_CMD_RESOURCE_INSTANCE_ANY unless a specific one required for test10312 * purposes.10313 */10314#define MC_CMD_INIT_EVQ_IN_IRQ_NUM_OFST 2410315#define MC_CMD_INIT_EVQ_IN_IRQ_NUM_LEN 410316/* Event Counter Mode. */10317#define MC_CMD_INIT_EVQ_IN_COUNT_MODE_OFST 2810318#define MC_CMD_INIT_EVQ_IN_COUNT_MODE_LEN 410319/* enum: Disabled */10320#define MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS 0x010321/* enum: Disabled */10322#define MC_CMD_INIT_EVQ_IN_COUNT_MODE_RX 0x110323/* enum: Disabled */10324#define MC_CMD_INIT_EVQ_IN_COUNT_MODE_TX 0x210325/* enum: Disabled */10326#define MC_CMD_INIT_EVQ_IN_COUNT_MODE_RXTX 0x310327/* Event queue packet count threshold. */10328#define MC_CMD_INIT_EVQ_IN_COUNT_THRSHLD_OFST 3210329#define MC_CMD_INIT_EVQ_IN_COUNT_THRSHLD_LEN 410330/* 64-bit address of 4k of 4k-aligned host memory buffer */10331#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_OFST 3610332#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_LEN 810333#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_LO_OFST 3610334#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_LO_LEN 410335#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_LO_LBN 28810336#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_LO_WIDTH 3210337#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_HI_OFST 4010338#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_HI_LEN 410339#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_HI_LBN 32010340#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_HI_WIDTH 3210341#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_MINNUM 110342#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_MAXNUM 6410343#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_MAXNUM_MCDI2 6410344 10345/* MC_CMD_INIT_EVQ_OUT msgresponse */10346#define MC_CMD_INIT_EVQ_OUT_LEN 410347/* Only valid if INTRFLAG was true */10348#define MC_CMD_INIT_EVQ_OUT_IRQ_OFST 010349#define MC_CMD_INIT_EVQ_OUT_IRQ_LEN 410350 10351/* MC_CMD_INIT_EVQ_V2_IN msgrequest */10352#define MC_CMD_INIT_EVQ_V2_IN_LENMIN 4410353#define MC_CMD_INIT_EVQ_V2_IN_LENMAX 54810354#define MC_CMD_INIT_EVQ_V2_IN_LENMAX_MCDI2 54810355#define MC_CMD_INIT_EVQ_V2_IN_LEN(num) (36+8*(num))10356#define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_NUM(len) (((len)-36)/8)10357/* Size, in entries */10358#define MC_CMD_INIT_EVQ_V2_IN_SIZE_OFST 010359#define MC_CMD_INIT_EVQ_V2_IN_SIZE_LEN 410360/* Desired instance. Must be set to a specific instance, which is a function10361 * local queue index. The calling client must be the currently-assigned user of10362 * this VI (see MC_CMD_SET_VI_USER).10363 */10364#define MC_CMD_INIT_EVQ_V2_IN_INSTANCE_OFST 410365#define MC_CMD_INIT_EVQ_V2_IN_INSTANCE_LEN 410366/* The initial timer value. The load value is ignored if the timer mode is DIS.10367 */10368#define MC_CMD_INIT_EVQ_V2_IN_TMR_LOAD_OFST 810369#define MC_CMD_INIT_EVQ_V2_IN_TMR_LOAD_LEN 410370/* The reload value is ignored in one-shot modes */10371#define MC_CMD_INIT_EVQ_V2_IN_TMR_RELOAD_OFST 1210372#define MC_CMD_INIT_EVQ_V2_IN_TMR_RELOAD_LEN 410373/* tbd */10374#define MC_CMD_INIT_EVQ_V2_IN_FLAGS_OFST 1610375#define MC_CMD_INIT_EVQ_V2_IN_FLAGS_LEN 410376#define MC_CMD_INIT_EVQ_V2_IN_FLAG_INTERRUPTING_OFST 1610377#define MC_CMD_INIT_EVQ_V2_IN_FLAG_INTERRUPTING_LBN 010378#define MC_CMD_INIT_EVQ_V2_IN_FLAG_INTERRUPTING_WIDTH 110379#define MC_CMD_INIT_EVQ_V2_IN_FLAG_RPTR_DOS_OFST 1610380#define MC_CMD_INIT_EVQ_V2_IN_FLAG_RPTR_DOS_LBN 110381#define MC_CMD_INIT_EVQ_V2_IN_FLAG_RPTR_DOS_WIDTH 110382#define MC_CMD_INIT_EVQ_V2_IN_FLAG_INT_ARMD_OFST 1610383#define MC_CMD_INIT_EVQ_V2_IN_FLAG_INT_ARMD_LBN 210384#define MC_CMD_INIT_EVQ_V2_IN_FLAG_INT_ARMD_WIDTH 110385#define MC_CMD_INIT_EVQ_V2_IN_FLAG_CUT_THRU_OFST 1610386#define MC_CMD_INIT_EVQ_V2_IN_FLAG_CUT_THRU_LBN 310387#define MC_CMD_INIT_EVQ_V2_IN_FLAG_CUT_THRU_WIDTH 110388#define MC_CMD_INIT_EVQ_V2_IN_FLAG_RX_MERGE_OFST 1610389#define MC_CMD_INIT_EVQ_V2_IN_FLAG_RX_MERGE_LBN 410390#define MC_CMD_INIT_EVQ_V2_IN_FLAG_RX_MERGE_WIDTH 110391#define MC_CMD_INIT_EVQ_V2_IN_FLAG_TX_MERGE_OFST 1610392#define MC_CMD_INIT_EVQ_V2_IN_FLAG_TX_MERGE_LBN 510393#define MC_CMD_INIT_EVQ_V2_IN_FLAG_TX_MERGE_WIDTH 110394#define MC_CMD_INIT_EVQ_V2_IN_FLAG_USE_TIMER_OFST 1610395#define MC_CMD_INIT_EVQ_V2_IN_FLAG_USE_TIMER_LBN 610396#define MC_CMD_INIT_EVQ_V2_IN_FLAG_USE_TIMER_WIDTH 110397#define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_OFST 1610398#define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_LBN 710399#define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_WIDTH 410400/* enum: All initialisation flags specified by host. */10401#define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_MANUAL 0x010402/* enum: MEDFORD only. Certain initialisation flags specified by host may be10403 * over-ridden by firmware based on licenses and firmware variant in order to10404 * provide the lowest latency achievable. See10405 * MC_CMD_INIT_EVQ_V2/MC_CMD_INIT_EVQ_V2_OUT/FLAGS for list of affected flags.10406 */10407#define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_LOW_LATENCY 0x110408/* enum: MEDFORD only. Certain initialisation flags specified by host may be10409 * over-ridden by firmware based on licenses and firmware variant in order to10410 * provide the best throughput achievable. See10411 * MC_CMD_INIT_EVQ_V2/MC_CMD_INIT_EVQ_V2_OUT/FLAGS for list of affected flags.10412 */10413#define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_THROUGHPUT 0x210414/* enum: MEDFORD only. Certain initialisation flags may be over-ridden by10415 * firmware based on licenses and firmware variant. See10416 * MC_CMD_INIT_EVQ_V2/MC_CMD_INIT_EVQ_V2_OUT/FLAGS for list of affected flags.10417 */10418#define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_AUTO 0x310419#define MC_CMD_INIT_EVQ_V2_IN_FLAG_EXT_WIDTH_OFST 1610420#define MC_CMD_INIT_EVQ_V2_IN_FLAG_EXT_WIDTH_LBN 1110421#define MC_CMD_INIT_EVQ_V2_IN_FLAG_EXT_WIDTH_WIDTH 110422#define MC_CMD_INIT_EVQ_V2_IN_TMR_MODE_OFST 2010423#define MC_CMD_INIT_EVQ_V2_IN_TMR_MODE_LEN 410424/* enum: Disabled */10425#define MC_CMD_INIT_EVQ_V2_IN_TMR_MODE_DIS 0x010426/* enum: Immediate */10427#define MC_CMD_INIT_EVQ_V2_IN_TMR_IMMED_START 0x110428/* enum: Triggered */10429#define MC_CMD_INIT_EVQ_V2_IN_TMR_TRIG_START 0x210430/* enum: Hold-off */10431#define MC_CMD_INIT_EVQ_V2_IN_TMR_INT_HLDOFF 0x310432/* Target EVQ for wakeups if in wakeup mode. */10433#define MC_CMD_INIT_EVQ_V2_IN_TARGET_EVQ_OFST 2410434#define MC_CMD_INIT_EVQ_V2_IN_TARGET_EVQ_LEN 410435/* Target interrupt if in interrupting mode (note union with target EVQ). Use10436 * MC_CMD_RESOURCE_INSTANCE_ANY unless a specific one required for test10437 * purposes.10438 */10439#define MC_CMD_INIT_EVQ_V2_IN_IRQ_NUM_OFST 2410440#define MC_CMD_INIT_EVQ_V2_IN_IRQ_NUM_LEN 410441/* Event Counter Mode. */10442#define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_OFST 2810443#define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_LEN 410444/* enum: Disabled */10445#define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_DIS 0x010446/* enum: Disabled */10447#define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_RX 0x110448/* enum: Disabled */10449#define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_TX 0x210450/* enum: Disabled */10451#define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_RXTX 0x310452/* Event queue packet count threshold. */10453#define MC_CMD_INIT_EVQ_V2_IN_COUNT_THRSHLD_OFST 3210454#define MC_CMD_INIT_EVQ_V2_IN_COUNT_THRSHLD_LEN 410455/* 64-bit address of 4k of 4k-aligned host memory buffer */10456#define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_OFST 3610457#define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_LEN 810458#define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_LO_OFST 3610459#define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_LO_LEN 410460#define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_LO_LBN 28810461#define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_LO_WIDTH 3210462#define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_HI_OFST 4010463#define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_HI_LEN 410464#define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_HI_LBN 32010465#define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_HI_WIDTH 3210466#define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_MINNUM 110467#define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_MAXNUM 6410468#define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_MAXNUM_MCDI2 6410469 10470/* MC_CMD_INIT_EVQ_V2_OUT msgresponse */10471#define MC_CMD_INIT_EVQ_V2_OUT_LEN 810472/* Only valid if INTRFLAG was true */10473#define MC_CMD_INIT_EVQ_V2_OUT_IRQ_OFST 010474#define MC_CMD_INIT_EVQ_V2_OUT_IRQ_LEN 410475/* Actual configuration applied on the card */10476#define MC_CMD_INIT_EVQ_V2_OUT_FLAGS_OFST 410477#define MC_CMD_INIT_EVQ_V2_OUT_FLAGS_LEN 410478#define MC_CMD_INIT_EVQ_V2_OUT_FLAG_CUT_THRU_OFST 410479#define MC_CMD_INIT_EVQ_V2_OUT_FLAG_CUT_THRU_LBN 010480#define MC_CMD_INIT_EVQ_V2_OUT_FLAG_CUT_THRU_WIDTH 110481#define MC_CMD_INIT_EVQ_V2_OUT_FLAG_RX_MERGE_OFST 410482#define MC_CMD_INIT_EVQ_V2_OUT_FLAG_RX_MERGE_LBN 110483#define MC_CMD_INIT_EVQ_V2_OUT_FLAG_RX_MERGE_WIDTH 110484#define MC_CMD_INIT_EVQ_V2_OUT_FLAG_TX_MERGE_OFST 410485#define MC_CMD_INIT_EVQ_V2_OUT_FLAG_TX_MERGE_LBN 210486#define MC_CMD_INIT_EVQ_V2_OUT_FLAG_TX_MERGE_WIDTH 110487#define MC_CMD_INIT_EVQ_V2_OUT_FLAG_RXQ_FORCE_EV_MERGING_OFST 410488#define MC_CMD_INIT_EVQ_V2_OUT_FLAG_RXQ_FORCE_EV_MERGING_LBN 310489#define MC_CMD_INIT_EVQ_V2_OUT_FLAG_RXQ_FORCE_EV_MERGING_WIDTH 110490 10491/* MC_CMD_INIT_EVQ_V3_IN msgrequest: Extended request to specify per-queue10492 * event merge timeouts.10493 */10494#define MC_CMD_INIT_EVQ_V3_IN_LEN 55610495/* Size, in entries */10496#define MC_CMD_INIT_EVQ_V3_IN_SIZE_OFST 010497#define MC_CMD_INIT_EVQ_V3_IN_SIZE_LEN 410498/* Desired instance. Must be set to a specific instance, which is a function10499 * local queue index. The calling client must be the currently-assigned user of10500 * this VI (see MC_CMD_SET_VI_USER).10501 */10502#define MC_CMD_INIT_EVQ_V3_IN_INSTANCE_OFST 410503#define MC_CMD_INIT_EVQ_V3_IN_INSTANCE_LEN 410504/* The initial timer value. The load value is ignored if the timer mode is DIS.10505 */10506#define MC_CMD_INIT_EVQ_V3_IN_TMR_LOAD_OFST 810507#define MC_CMD_INIT_EVQ_V3_IN_TMR_LOAD_LEN 410508/* The reload value is ignored in one-shot modes */10509#define MC_CMD_INIT_EVQ_V3_IN_TMR_RELOAD_OFST 1210510#define MC_CMD_INIT_EVQ_V3_IN_TMR_RELOAD_LEN 410511/* tbd */10512#define MC_CMD_INIT_EVQ_V3_IN_FLAGS_OFST 1610513#define MC_CMD_INIT_EVQ_V3_IN_FLAGS_LEN 410514#define MC_CMD_INIT_EVQ_V3_IN_FLAG_INTERRUPTING_OFST 1610515#define MC_CMD_INIT_EVQ_V3_IN_FLAG_INTERRUPTING_LBN 010516#define MC_CMD_INIT_EVQ_V3_IN_FLAG_INTERRUPTING_WIDTH 110517#define MC_CMD_INIT_EVQ_V3_IN_FLAG_RPTR_DOS_OFST 1610518#define MC_CMD_INIT_EVQ_V3_IN_FLAG_RPTR_DOS_LBN 110519#define MC_CMD_INIT_EVQ_V3_IN_FLAG_RPTR_DOS_WIDTH 110520#define MC_CMD_INIT_EVQ_V3_IN_FLAG_INT_ARMD_OFST 1610521#define MC_CMD_INIT_EVQ_V3_IN_FLAG_INT_ARMD_LBN 210522#define MC_CMD_INIT_EVQ_V3_IN_FLAG_INT_ARMD_WIDTH 110523#define MC_CMD_INIT_EVQ_V3_IN_FLAG_CUT_THRU_OFST 1610524#define MC_CMD_INIT_EVQ_V3_IN_FLAG_CUT_THRU_LBN 310525#define MC_CMD_INIT_EVQ_V3_IN_FLAG_CUT_THRU_WIDTH 110526#define MC_CMD_INIT_EVQ_V3_IN_FLAG_RX_MERGE_OFST 1610527#define MC_CMD_INIT_EVQ_V3_IN_FLAG_RX_MERGE_LBN 410528#define MC_CMD_INIT_EVQ_V3_IN_FLAG_RX_MERGE_WIDTH 110529#define MC_CMD_INIT_EVQ_V3_IN_FLAG_TX_MERGE_OFST 1610530#define MC_CMD_INIT_EVQ_V3_IN_FLAG_TX_MERGE_LBN 510531#define MC_CMD_INIT_EVQ_V3_IN_FLAG_TX_MERGE_WIDTH 110532#define MC_CMD_INIT_EVQ_V3_IN_FLAG_USE_TIMER_OFST 1610533#define MC_CMD_INIT_EVQ_V3_IN_FLAG_USE_TIMER_LBN 610534#define MC_CMD_INIT_EVQ_V3_IN_FLAG_USE_TIMER_WIDTH 110535#define MC_CMD_INIT_EVQ_V3_IN_FLAG_TYPE_OFST 1610536#define MC_CMD_INIT_EVQ_V3_IN_FLAG_TYPE_LBN 710537#define MC_CMD_INIT_EVQ_V3_IN_FLAG_TYPE_WIDTH 410538/* enum: All initialisation flags specified by host. */10539#define MC_CMD_INIT_EVQ_V3_IN_FLAG_TYPE_MANUAL 0x010540/* enum: MEDFORD only. Certain initialisation flags specified by host may be10541 * over-ridden by firmware based on licenses and firmware variant in order to10542 * provide the lowest latency achievable. See10543 * MC_CMD_INIT_EVQ_V2/MC_CMD_INIT_EVQ_V2_OUT/FLAGS for list of affected flags.10544 */10545#define MC_CMD_INIT_EVQ_V3_IN_FLAG_TYPE_LOW_LATENCY 0x110546/* enum: MEDFORD only. Certain initialisation flags specified by host may be10547 * over-ridden by firmware based on licenses and firmware variant in order to10548 * provide the best throughput achievable. See10549 * MC_CMD_INIT_EVQ_V2/MC_CMD_INIT_EVQ_V2_OUT/FLAGS for list of affected flags.10550 */10551#define MC_CMD_INIT_EVQ_V3_IN_FLAG_TYPE_THROUGHPUT 0x210552/* enum: MEDFORD only. Certain initialisation flags may be over-ridden by10553 * firmware based on licenses and firmware variant. See10554 * MC_CMD_INIT_EVQ_V2/MC_CMD_INIT_EVQ_V2_OUT/FLAGS for list of affected flags.10555 */10556#define MC_CMD_INIT_EVQ_V3_IN_FLAG_TYPE_AUTO 0x310557#define MC_CMD_INIT_EVQ_V3_IN_FLAG_EXT_WIDTH_OFST 1610558#define MC_CMD_INIT_EVQ_V3_IN_FLAG_EXT_WIDTH_LBN 1110559#define MC_CMD_INIT_EVQ_V3_IN_FLAG_EXT_WIDTH_WIDTH 110560#define MC_CMD_INIT_EVQ_V3_IN_TMR_MODE_OFST 2010561#define MC_CMD_INIT_EVQ_V3_IN_TMR_MODE_LEN 410562/* enum: Disabled */10563#define MC_CMD_INIT_EVQ_V3_IN_TMR_MODE_DIS 0x010564/* enum: Immediate */10565#define MC_CMD_INIT_EVQ_V3_IN_TMR_IMMED_START 0x110566/* enum: Triggered */10567#define MC_CMD_INIT_EVQ_V3_IN_TMR_TRIG_START 0x210568/* enum: Hold-off */10569#define MC_CMD_INIT_EVQ_V3_IN_TMR_INT_HLDOFF 0x310570/* Target EVQ for wakeups if in wakeup mode. */10571#define MC_CMD_INIT_EVQ_V3_IN_TARGET_EVQ_OFST 2410572#define MC_CMD_INIT_EVQ_V3_IN_TARGET_EVQ_LEN 410573/* Target interrupt if in interrupting mode (note union with target EVQ). Use10574 * MC_CMD_RESOURCE_INSTANCE_ANY unless a specific one required for test10575 * purposes.10576 */10577#define MC_CMD_INIT_EVQ_V3_IN_IRQ_NUM_OFST 2410578#define MC_CMD_INIT_EVQ_V3_IN_IRQ_NUM_LEN 410579/* Event Counter Mode. */10580#define MC_CMD_INIT_EVQ_V3_IN_COUNT_MODE_OFST 2810581#define MC_CMD_INIT_EVQ_V3_IN_COUNT_MODE_LEN 410582/* enum: Disabled */10583#define MC_CMD_INIT_EVQ_V3_IN_COUNT_MODE_DIS 0x010584/* enum: Disabled */10585#define MC_CMD_INIT_EVQ_V3_IN_COUNT_MODE_RX 0x110586/* enum: Disabled */10587#define MC_CMD_INIT_EVQ_V3_IN_COUNT_MODE_TX 0x210588/* enum: Disabled */10589#define MC_CMD_INIT_EVQ_V3_IN_COUNT_MODE_RXTX 0x310590/* Event queue packet count threshold. */10591#define MC_CMD_INIT_EVQ_V3_IN_COUNT_THRSHLD_OFST 3210592#define MC_CMD_INIT_EVQ_V3_IN_COUNT_THRSHLD_LEN 410593/* 64-bit address of 4k of 4k-aligned host memory buffer */10594#define MC_CMD_INIT_EVQ_V3_IN_DMA_ADDR_OFST 3610595#define MC_CMD_INIT_EVQ_V3_IN_DMA_ADDR_LEN 810596#define MC_CMD_INIT_EVQ_V3_IN_DMA_ADDR_LO_OFST 3610597#define MC_CMD_INIT_EVQ_V3_IN_DMA_ADDR_LO_LEN 410598#define MC_CMD_INIT_EVQ_V3_IN_DMA_ADDR_LO_LBN 28810599#define MC_CMD_INIT_EVQ_V3_IN_DMA_ADDR_LO_WIDTH 3210600#define MC_CMD_INIT_EVQ_V3_IN_DMA_ADDR_HI_OFST 4010601#define MC_CMD_INIT_EVQ_V3_IN_DMA_ADDR_HI_LEN 410602#define MC_CMD_INIT_EVQ_V3_IN_DMA_ADDR_HI_LBN 32010603#define MC_CMD_INIT_EVQ_V3_IN_DMA_ADDR_HI_WIDTH 3210604#define MC_CMD_INIT_EVQ_V3_IN_DMA_ADDR_MINNUM 110605#define MC_CMD_INIT_EVQ_V3_IN_DMA_ADDR_MAXNUM 6410606#define MC_CMD_INIT_EVQ_V3_IN_DMA_ADDR_MAXNUM_MCDI2 6410607/* Receive event merge timeout to configure, in nanoseconds. The valid range10608 * and granularity are device specific. Specify 0 to use the firmware's default10609 * value. This field is ignored and per-queue merging is disabled if10610 * MC_CMD_INIT_EVQ/MC_CMD_INIT_EVQ_IN/FLAG_RX_MERGE is not set.10611 */10612#define MC_CMD_INIT_EVQ_V3_IN_RX_MERGE_TIMEOUT_NS_OFST 54810613#define MC_CMD_INIT_EVQ_V3_IN_RX_MERGE_TIMEOUT_NS_LEN 410614/* Transmit event merge timeout to configure, in nanoseconds. The valid range10615 * and granularity are device specific. Specify 0 to use the firmware's default10616 * value. This field is ignored and per-queue merging is disabled if10617 * MC_CMD_INIT_EVQ/MC_CMD_INIT_EVQ_IN/FLAG_TX_MERGE is not set.10618 */10619#define MC_CMD_INIT_EVQ_V3_IN_TX_MERGE_TIMEOUT_NS_OFST 55210620#define MC_CMD_INIT_EVQ_V3_IN_TX_MERGE_TIMEOUT_NS_LEN 410621 10622/* MC_CMD_INIT_EVQ_V3_OUT msgresponse */10623#define MC_CMD_INIT_EVQ_V3_OUT_LEN 810624/* Only valid if INTRFLAG was true */10625#define MC_CMD_INIT_EVQ_V3_OUT_IRQ_OFST 010626#define MC_CMD_INIT_EVQ_V3_OUT_IRQ_LEN 410627/* Actual configuration applied on the card */10628#define MC_CMD_INIT_EVQ_V3_OUT_FLAGS_OFST 410629#define MC_CMD_INIT_EVQ_V3_OUT_FLAGS_LEN 410630#define MC_CMD_INIT_EVQ_V3_OUT_FLAG_CUT_THRU_OFST 410631#define MC_CMD_INIT_EVQ_V3_OUT_FLAG_CUT_THRU_LBN 010632#define MC_CMD_INIT_EVQ_V3_OUT_FLAG_CUT_THRU_WIDTH 110633#define MC_CMD_INIT_EVQ_V3_OUT_FLAG_RX_MERGE_OFST 410634#define MC_CMD_INIT_EVQ_V3_OUT_FLAG_RX_MERGE_LBN 110635#define MC_CMD_INIT_EVQ_V3_OUT_FLAG_RX_MERGE_WIDTH 110636#define MC_CMD_INIT_EVQ_V3_OUT_FLAG_TX_MERGE_OFST 410637#define MC_CMD_INIT_EVQ_V3_OUT_FLAG_TX_MERGE_LBN 210638#define MC_CMD_INIT_EVQ_V3_OUT_FLAG_TX_MERGE_WIDTH 110639#define MC_CMD_INIT_EVQ_V3_OUT_FLAG_RXQ_FORCE_EV_MERGING_OFST 410640#define MC_CMD_INIT_EVQ_V3_OUT_FLAG_RXQ_FORCE_EV_MERGING_LBN 310641#define MC_CMD_INIT_EVQ_V3_OUT_FLAG_RXQ_FORCE_EV_MERGING_WIDTH 110642 10643/* QUEUE_CRC_MODE structuredef */10644#define QUEUE_CRC_MODE_LEN 110645#define QUEUE_CRC_MODE_MODE_LBN 010646#define QUEUE_CRC_MODE_MODE_WIDTH 410647/* enum: No CRC. */10648#define QUEUE_CRC_MODE_NONE 0x010649/* enum: CRC Fiber channel over ethernet. */10650#define QUEUE_CRC_MODE_FCOE 0x110651/* enum: CRC (digest) iSCSI header only. */10652#define QUEUE_CRC_MODE_ISCSI_HDR 0x210653/* enum: CRC (digest) iSCSI header and payload. */10654#define QUEUE_CRC_MODE_ISCSI 0x310655/* enum: CRC Fiber channel over IP over ethernet. */10656#define QUEUE_CRC_MODE_FCOIPOE 0x410657/* enum: CRC MPA. */10658#define QUEUE_CRC_MODE_MPA 0x510659#define QUEUE_CRC_MODE_SPARE_LBN 410660#define QUEUE_CRC_MODE_SPARE_WIDTH 410661 10662 10663/***********************************/10664/* MC_CMD_INIT_RXQ10665 * set up a receive queue according to the supplied parameters. The IN10666 * arguments end with an address for each 4k of host memory required to back10667 * the RXQ.10668 */10669#define MC_CMD_INIT_RXQ 0x8110670#undef MC_CMD_0x81_PRIVILEGE_CTG10671 10672#define MC_CMD_0x81_PRIVILEGE_CTG SRIOV_CTG_GENERAL10673 10674/* MC_CMD_INIT_RXQ_IN msgrequest: Legacy RXQ_INIT request. Use extended version10675 * in new code.10676 */10677#define MC_CMD_INIT_RXQ_IN_LENMIN 3610678#define MC_CMD_INIT_RXQ_IN_LENMAX 25210679#define MC_CMD_INIT_RXQ_IN_LENMAX_MCDI2 102010680#define MC_CMD_INIT_RXQ_IN_LEN(num) (28+8*(num))10681#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_NUM(len) (((len)-28)/8)10682/* Size, in entries */10683#define MC_CMD_INIT_RXQ_IN_SIZE_OFST 010684#define MC_CMD_INIT_RXQ_IN_SIZE_LEN 410685/* The EVQ to send events to. This is an index originally specified to INIT_EVQ10686 */10687#define MC_CMD_INIT_RXQ_IN_TARGET_EVQ_OFST 410688#define MC_CMD_INIT_RXQ_IN_TARGET_EVQ_LEN 410689/* The value to put in the event data. Check hardware spec. for valid range. */10690#define MC_CMD_INIT_RXQ_IN_LABEL_OFST 810691#define MC_CMD_INIT_RXQ_IN_LABEL_LEN 410692/* Desired instance. Must be set to a specific instance, which is a function10693 * local queue index. The calling client must be the currently-assigned user of10694 * this VI (see MC_CMD_SET_VI_USER).10695 */10696#define MC_CMD_INIT_RXQ_IN_INSTANCE_OFST 1210697#define MC_CMD_INIT_RXQ_IN_INSTANCE_LEN 410698/* There will be more flags here. */10699#define MC_CMD_INIT_RXQ_IN_FLAGS_OFST 1610700#define MC_CMD_INIT_RXQ_IN_FLAGS_LEN 410701#define MC_CMD_INIT_RXQ_IN_FLAG_BUFF_MODE_OFST 1610702#define MC_CMD_INIT_RXQ_IN_FLAG_BUFF_MODE_LBN 010703#define MC_CMD_INIT_RXQ_IN_FLAG_BUFF_MODE_WIDTH 110704#define MC_CMD_INIT_RXQ_IN_FLAG_HDR_SPLIT_OFST 1610705#define MC_CMD_INIT_RXQ_IN_FLAG_HDR_SPLIT_LBN 110706#define MC_CMD_INIT_RXQ_IN_FLAG_HDR_SPLIT_WIDTH 110707#define MC_CMD_INIT_RXQ_IN_FLAG_TIMESTAMP_OFST 1610708#define MC_CMD_INIT_RXQ_IN_FLAG_TIMESTAMP_LBN 210709#define MC_CMD_INIT_RXQ_IN_FLAG_TIMESTAMP_WIDTH 110710#define MC_CMD_INIT_RXQ_IN_CRC_MODE_OFST 1610711#define MC_CMD_INIT_RXQ_IN_CRC_MODE_LBN 310712#define MC_CMD_INIT_RXQ_IN_CRC_MODE_WIDTH 410713#define MC_CMD_INIT_RXQ_IN_FLAG_CHAIN_OFST 1610714#define MC_CMD_INIT_RXQ_IN_FLAG_CHAIN_LBN 710715#define MC_CMD_INIT_RXQ_IN_FLAG_CHAIN_WIDTH 110716#define MC_CMD_INIT_RXQ_IN_FLAG_PREFIX_OFST 1610717#define MC_CMD_INIT_RXQ_IN_FLAG_PREFIX_LBN 810718#define MC_CMD_INIT_RXQ_IN_FLAG_PREFIX_WIDTH 110719#define MC_CMD_INIT_RXQ_IN_FLAG_DISABLE_SCATTER_OFST 1610720#define MC_CMD_INIT_RXQ_IN_FLAG_DISABLE_SCATTER_LBN 910721#define MC_CMD_INIT_RXQ_IN_FLAG_DISABLE_SCATTER_WIDTH 110722#define MC_CMD_INIT_RXQ_IN_UNUSED_OFST 1610723#define MC_CMD_INIT_RXQ_IN_UNUSED_LBN 1010724#define MC_CMD_INIT_RXQ_IN_UNUSED_WIDTH 110725/* Owner ID to use if in buffer mode (zero if physical) */10726#define MC_CMD_INIT_RXQ_IN_OWNER_ID_OFST 2010727#define MC_CMD_INIT_RXQ_IN_OWNER_ID_LEN 410728/* The port ID associated with the v-adaptor which should contain this DMAQ. */10729#define MC_CMD_INIT_RXQ_IN_PORT_ID_OFST 2410730#define MC_CMD_INIT_RXQ_IN_PORT_ID_LEN 410731/* 64-bit address of 4k of 4k-aligned host memory buffer */10732#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_OFST 2810733#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_LEN 810734#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_LO_OFST 2810735#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_LO_LEN 410736#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_LO_LBN 22410737#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_LO_WIDTH 3210738#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_HI_OFST 3210739#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_HI_LEN 410740#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_HI_LBN 25610741#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_HI_WIDTH 3210742#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_MINNUM 110743#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_MAXNUM 2810744#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_MAXNUM_MCDI2 12410745 10746/* MC_CMD_INIT_RXQ_EXT_IN msgrequest: Extended RXQ_INIT with additional mode10747 * flags10748 */10749#define MC_CMD_INIT_RXQ_EXT_IN_LEN 54410750/* Size, in entries */10751#define MC_CMD_INIT_RXQ_EXT_IN_SIZE_OFST 010752#define MC_CMD_INIT_RXQ_EXT_IN_SIZE_LEN 410753/* The EVQ to send events to. This is an index originally specified to10754 * INIT_EVQ. If DMA_MODE == PACKED_STREAM this must be equal to INSTANCE.10755 */10756#define MC_CMD_INIT_RXQ_EXT_IN_TARGET_EVQ_OFST 410757#define MC_CMD_INIT_RXQ_EXT_IN_TARGET_EVQ_LEN 410758/* The value to put in the event data. Check hardware spec. for valid range.10759 * This field is ignored if DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER or DMA_MODE10760 * == PACKED_STREAM.10761 */10762#define MC_CMD_INIT_RXQ_EXT_IN_LABEL_OFST 810763#define MC_CMD_INIT_RXQ_EXT_IN_LABEL_LEN 410764/* Desired instance. Must be set to a specific instance, which is a function10765 * local queue index. The calling client must be the currently-assigned user of10766 * this VI (see MC_CMD_SET_VI_USER).10767 */10768#define MC_CMD_INIT_RXQ_EXT_IN_INSTANCE_OFST 1210769#define MC_CMD_INIT_RXQ_EXT_IN_INSTANCE_LEN 410770/* There will be more flags here. */10771#define MC_CMD_INIT_RXQ_EXT_IN_FLAGS_OFST 1610772#define MC_CMD_INIT_RXQ_EXT_IN_FLAGS_LEN 410773#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_BUFF_MODE_OFST 1610774#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_BUFF_MODE_LBN 010775#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_BUFF_MODE_WIDTH 110776#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_HDR_SPLIT_OFST 1610777#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_HDR_SPLIT_LBN 110778#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_HDR_SPLIT_WIDTH 110779#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_TIMESTAMP_OFST 1610780#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_TIMESTAMP_LBN 210781#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_TIMESTAMP_WIDTH 110782#define MC_CMD_INIT_RXQ_EXT_IN_CRC_MODE_OFST 1610783#define MC_CMD_INIT_RXQ_EXT_IN_CRC_MODE_LBN 310784#define MC_CMD_INIT_RXQ_EXT_IN_CRC_MODE_WIDTH 410785#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_CHAIN_OFST 1610786#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_CHAIN_LBN 710787#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_CHAIN_WIDTH 110788#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_PREFIX_OFST 1610789#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_PREFIX_LBN 810790#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_PREFIX_WIDTH 110791#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_DISABLE_SCATTER_OFST 1610792#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_DISABLE_SCATTER_LBN 910793#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_DISABLE_SCATTER_WIDTH 110794#define MC_CMD_INIT_RXQ_EXT_IN_DMA_MODE_OFST 1610795#define MC_CMD_INIT_RXQ_EXT_IN_DMA_MODE_LBN 1010796#define MC_CMD_INIT_RXQ_EXT_IN_DMA_MODE_WIDTH 410797/* enum: One packet per descriptor (for normal networking) */10798#define MC_CMD_INIT_RXQ_EXT_IN_SINGLE_PACKET 0x010799/* enum: Pack multiple packets into large descriptors (for SolarCapture) */10800#define MC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM 0x110801/* enum: Pack multiple packets into large descriptors using the format designed10802 * to maximise packet rate. This mode uses 1 "bucket" per descriptor with10803 * multiple fixed-size packet buffers within each bucket. For a full10804 * description see SF-119419-TC. This mode is only supported by "dpdk" datapath10805 * firmware.10806 */10807#define MC_CMD_INIT_RXQ_EXT_IN_EQUAL_STRIDE_SUPER_BUFFER 0x210808/* enum: Deprecated name for EQUAL_STRIDE_SUPER_BUFFER. */10809#define MC_CMD_INIT_RXQ_EXT_IN_EQUAL_STRIDE_PACKED_STREAM 0x210810#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_SNAPSHOT_MODE_OFST 1610811#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_SNAPSHOT_MODE_LBN 1410812#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_SNAPSHOT_MODE_WIDTH 110813#define MC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM_BUFF_SIZE_OFST 1610814#define MC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM_BUFF_SIZE_LBN 1510815#define MC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM_BUFF_SIZE_WIDTH 310816#define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_1M 0x0 /* enum */10817#define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_512K 0x1 /* enum */10818#define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_256K 0x2 /* enum */10819#define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_128K 0x3 /* enum */10820#define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_64K 0x4 /* enum */10821#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_WANT_OUTER_CLASSES_OFST 1610822#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_WANT_OUTER_CLASSES_LBN 1810823#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_WANT_OUTER_CLASSES_WIDTH 110824#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_FORCE_EV_MERGING_OFST 1610825#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_FORCE_EV_MERGING_LBN 1910826#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_FORCE_EV_MERGING_WIDTH 110827#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_NO_CONT_EV_OFST 1610828#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_NO_CONT_EV_LBN 2010829#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_NO_CONT_EV_WIDTH 110830/* Owner ID to use if in buffer mode (zero if physical) */10831#define MC_CMD_INIT_RXQ_EXT_IN_OWNER_ID_OFST 2010832#define MC_CMD_INIT_RXQ_EXT_IN_OWNER_ID_LEN 410833/* The port ID associated with the v-adaptor which should contain this DMAQ. */10834#define MC_CMD_INIT_RXQ_EXT_IN_PORT_ID_OFST 2410835#define MC_CMD_INIT_RXQ_EXT_IN_PORT_ID_LEN 410836/* 64-bit address of 4k of 4k-aligned host memory buffer */10837#define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_OFST 2810838#define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_LEN 810839#define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_LO_OFST 2810840#define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_LO_LEN 410841#define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_LO_LBN 22410842#define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_LO_WIDTH 3210843#define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_HI_OFST 3210844#define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_HI_LEN 410845#define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_HI_LBN 25610846#define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_HI_WIDTH 3210847#define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_MINNUM 010848#define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_MAXNUM 6410849#define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_MAXNUM_MCDI2 6410850/* Maximum length of packet to receive, if SNAPSHOT_MODE flag is set */10851#define MC_CMD_INIT_RXQ_EXT_IN_SNAPSHOT_LENGTH_OFST 54010852#define MC_CMD_INIT_RXQ_EXT_IN_SNAPSHOT_LENGTH_LEN 410853 10854/* MC_CMD_INIT_RXQ_V3_IN msgrequest */10855#define MC_CMD_INIT_RXQ_V3_IN_LEN 56010856/* Size, in entries */10857#define MC_CMD_INIT_RXQ_V3_IN_SIZE_OFST 010858#define MC_CMD_INIT_RXQ_V3_IN_SIZE_LEN 410859/* The EVQ to send events to. This is an index originally specified to10860 * INIT_EVQ. If DMA_MODE == PACKED_STREAM this must be equal to INSTANCE.10861 */10862#define MC_CMD_INIT_RXQ_V3_IN_TARGET_EVQ_OFST 410863#define MC_CMD_INIT_RXQ_V3_IN_TARGET_EVQ_LEN 410864/* The value to put in the event data. Check hardware spec. for valid range.10865 * This field is ignored if DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER or DMA_MODE10866 * == PACKED_STREAM.10867 */10868#define MC_CMD_INIT_RXQ_V3_IN_LABEL_OFST 810869#define MC_CMD_INIT_RXQ_V3_IN_LABEL_LEN 410870/* Desired instance. Must be set to a specific instance, which is a function10871 * local queue index. The calling client must be the currently-assigned user of10872 * this VI (see MC_CMD_SET_VI_USER).10873 */10874#define MC_CMD_INIT_RXQ_V3_IN_INSTANCE_OFST 1210875#define MC_CMD_INIT_RXQ_V3_IN_INSTANCE_LEN 410876/* There will be more flags here. */10877#define MC_CMD_INIT_RXQ_V3_IN_FLAGS_OFST 1610878#define MC_CMD_INIT_RXQ_V3_IN_FLAGS_LEN 410879#define MC_CMD_INIT_RXQ_V3_IN_FLAG_BUFF_MODE_OFST 1610880#define MC_CMD_INIT_RXQ_V3_IN_FLAG_BUFF_MODE_LBN 010881#define MC_CMD_INIT_RXQ_V3_IN_FLAG_BUFF_MODE_WIDTH 110882#define MC_CMD_INIT_RXQ_V3_IN_FLAG_HDR_SPLIT_OFST 1610883#define MC_CMD_INIT_RXQ_V3_IN_FLAG_HDR_SPLIT_LBN 110884#define MC_CMD_INIT_RXQ_V3_IN_FLAG_HDR_SPLIT_WIDTH 110885#define MC_CMD_INIT_RXQ_V3_IN_FLAG_TIMESTAMP_OFST 1610886#define MC_CMD_INIT_RXQ_V3_IN_FLAG_TIMESTAMP_LBN 210887#define MC_CMD_INIT_RXQ_V3_IN_FLAG_TIMESTAMP_WIDTH 110888#define MC_CMD_INIT_RXQ_V3_IN_CRC_MODE_OFST 1610889#define MC_CMD_INIT_RXQ_V3_IN_CRC_MODE_LBN 310890#define MC_CMD_INIT_RXQ_V3_IN_CRC_MODE_WIDTH 410891#define MC_CMD_INIT_RXQ_V3_IN_FLAG_CHAIN_OFST 1610892#define MC_CMD_INIT_RXQ_V3_IN_FLAG_CHAIN_LBN 710893#define MC_CMD_INIT_RXQ_V3_IN_FLAG_CHAIN_WIDTH 110894#define MC_CMD_INIT_RXQ_V3_IN_FLAG_PREFIX_OFST 1610895#define MC_CMD_INIT_RXQ_V3_IN_FLAG_PREFIX_LBN 810896#define MC_CMD_INIT_RXQ_V3_IN_FLAG_PREFIX_WIDTH 110897#define MC_CMD_INIT_RXQ_V3_IN_FLAG_DISABLE_SCATTER_OFST 1610898#define MC_CMD_INIT_RXQ_V3_IN_FLAG_DISABLE_SCATTER_LBN 910899#define MC_CMD_INIT_RXQ_V3_IN_FLAG_DISABLE_SCATTER_WIDTH 110900#define MC_CMD_INIT_RXQ_V3_IN_DMA_MODE_OFST 1610901#define MC_CMD_INIT_RXQ_V3_IN_DMA_MODE_LBN 1010902#define MC_CMD_INIT_RXQ_V3_IN_DMA_MODE_WIDTH 410903/* enum: One packet per descriptor (for normal networking) */10904#define MC_CMD_INIT_RXQ_V3_IN_SINGLE_PACKET 0x010905/* enum: Pack multiple packets into large descriptors (for SolarCapture) */10906#define MC_CMD_INIT_RXQ_V3_IN_PACKED_STREAM 0x110907/* enum: Pack multiple packets into large descriptors using the format designed10908 * to maximise packet rate. This mode uses 1 "bucket" per descriptor with10909 * multiple fixed-size packet buffers within each bucket. For a full10910 * description see SF-119419-TC. This mode is only supported by "dpdk" datapath10911 * firmware.10912 */10913#define MC_CMD_INIT_RXQ_V3_IN_EQUAL_STRIDE_SUPER_BUFFER 0x210914/* enum: Deprecated name for EQUAL_STRIDE_SUPER_BUFFER. */10915#define MC_CMD_INIT_RXQ_V3_IN_EQUAL_STRIDE_PACKED_STREAM 0x210916#define MC_CMD_INIT_RXQ_V3_IN_FLAG_SNAPSHOT_MODE_OFST 1610917#define MC_CMD_INIT_RXQ_V3_IN_FLAG_SNAPSHOT_MODE_LBN 1410918#define MC_CMD_INIT_RXQ_V3_IN_FLAG_SNAPSHOT_MODE_WIDTH 110919#define MC_CMD_INIT_RXQ_V3_IN_PACKED_STREAM_BUFF_SIZE_OFST 1610920#define MC_CMD_INIT_RXQ_V3_IN_PACKED_STREAM_BUFF_SIZE_LBN 1510921#define MC_CMD_INIT_RXQ_V3_IN_PACKED_STREAM_BUFF_SIZE_WIDTH 310922#define MC_CMD_INIT_RXQ_V3_IN_PS_BUFF_1M 0x0 /* enum */10923#define MC_CMD_INIT_RXQ_V3_IN_PS_BUFF_512K 0x1 /* enum */10924#define MC_CMD_INIT_RXQ_V3_IN_PS_BUFF_256K 0x2 /* enum */10925#define MC_CMD_INIT_RXQ_V3_IN_PS_BUFF_128K 0x3 /* enum */10926#define MC_CMD_INIT_RXQ_V3_IN_PS_BUFF_64K 0x4 /* enum */10927#define MC_CMD_INIT_RXQ_V3_IN_FLAG_WANT_OUTER_CLASSES_OFST 1610928#define MC_CMD_INIT_RXQ_V3_IN_FLAG_WANT_OUTER_CLASSES_LBN 1810929#define MC_CMD_INIT_RXQ_V3_IN_FLAG_WANT_OUTER_CLASSES_WIDTH 110930#define MC_CMD_INIT_RXQ_V3_IN_FLAG_FORCE_EV_MERGING_OFST 1610931#define MC_CMD_INIT_RXQ_V3_IN_FLAG_FORCE_EV_MERGING_LBN 1910932#define MC_CMD_INIT_RXQ_V3_IN_FLAG_FORCE_EV_MERGING_WIDTH 110933#define MC_CMD_INIT_RXQ_V3_IN_FLAG_NO_CONT_EV_OFST 1610934#define MC_CMD_INIT_RXQ_V3_IN_FLAG_NO_CONT_EV_LBN 2010935#define MC_CMD_INIT_RXQ_V3_IN_FLAG_NO_CONT_EV_WIDTH 110936/* Owner ID to use if in buffer mode (zero if physical) */10937#define MC_CMD_INIT_RXQ_V3_IN_OWNER_ID_OFST 2010938#define MC_CMD_INIT_RXQ_V3_IN_OWNER_ID_LEN 410939/* The port ID associated with the v-adaptor which should contain this DMAQ. */10940#define MC_CMD_INIT_RXQ_V3_IN_PORT_ID_OFST 2410941#define MC_CMD_INIT_RXQ_V3_IN_PORT_ID_LEN 410942/* 64-bit address of 4k of 4k-aligned host memory buffer */10943#define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_OFST 2810944#define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_LEN 810945#define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_LO_OFST 2810946#define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_LO_LEN 410947#define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_LO_LBN 22410948#define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_LO_WIDTH 3210949#define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_HI_OFST 3210950#define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_HI_LEN 410951#define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_HI_LBN 25610952#define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_HI_WIDTH 3210953#define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_MINNUM 010954#define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_MAXNUM 6410955#define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_MAXNUM_MCDI2 6410956/* Maximum length of packet to receive, if SNAPSHOT_MODE flag is set */10957#define MC_CMD_INIT_RXQ_V3_IN_SNAPSHOT_LENGTH_OFST 54010958#define MC_CMD_INIT_RXQ_V3_IN_SNAPSHOT_LENGTH_LEN 410959/* The number of packet buffers that will be contained within each10960 * EQUAL_STRIDE_SUPER_BUFFER format bucket supplied by the driver. This field10961 * is ignored unless DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER.10962 */10963#define MC_CMD_INIT_RXQ_V3_IN_ES_PACKET_BUFFERS_PER_BUCKET_OFST 54410964#define MC_CMD_INIT_RXQ_V3_IN_ES_PACKET_BUFFERS_PER_BUCKET_LEN 410965/* The length in bytes of the area in each packet buffer that can be written to10966 * by the adapter. This is used to store the packet prefix and the packet10967 * payload. This length does not include any end padding added by the driver.10968 * This field is ignored unless DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER.10969 */10970#define MC_CMD_INIT_RXQ_V3_IN_ES_MAX_DMA_LEN_OFST 54810971#define MC_CMD_INIT_RXQ_V3_IN_ES_MAX_DMA_LEN_LEN 410972/* The length in bytes of a single packet buffer within a10973 * EQUAL_STRIDE_SUPER_BUFFER format bucket. This field is ignored unless10974 * DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER.10975 */10976#define MC_CMD_INIT_RXQ_V3_IN_ES_PACKET_STRIDE_OFST 55210977#define MC_CMD_INIT_RXQ_V3_IN_ES_PACKET_STRIDE_LEN 410978/* The maximum time in nanoseconds that the datapath will be backpressured if10979 * there are no RX descriptors available. If the timeout is reached and there10980 * are still no descriptors then the packet will be dropped. A timeout of 010981 * means the datapath will never be blocked. This field is ignored unless10982 * DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER.10983 */10984#define MC_CMD_INIT_RXQ_V3_IN_ES_HEAD_OF_LINE_BLOCK_TIMEOUT_OFST 55610985#define MC_CMD_INIT_RXQ_V3_IN_ES_HEAD_OF_LINE_BLOCK_TIMEOUT_LEN 410986 10987/* MC_CMD_INIT_RXQ_V4_IN msgrequest: INIT_RXQ request with new field required10988 * for systems with a QDMA (currently, Riverhead)10989 */10990#define MC_CMD_INIT_RXQ_V4_IN_LEN 56410991/* Size, in entries */10992#define MC_CMD_INIT_RXQ_V4_IN_SIZE_OFST 010993#define MC_CMD_INIT_RXQ_V4_IN_SIZE_LEN 410994/* The EVQ to send events to. This is an index originally specified to10995 * INIT_EVQ. If DMA_MODE == PACKED_STREAM this must be equal to INSTANCE.10996 */10997#define MC_CMD_INIT_RXQ_V4_IN_TARGET_EVQ_OFST 410998#define MC_CMD_INIT_RXQ_V4_IN_TARGET_EVQ_LEN 410999/* The value to put in the event data. Check hardware spec. for valid range.11000 * This field is ignored if DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER or DMA_MODE11001 * == PACKED_STREAM.11002 */11003#define MC_CMD_INIT_RXQ_V4_IN_LABEL_OFST 811004#define MC_CMD_INIT_RXQ_V4_IN_LABEL_LEN 411005/* Desired instance. Must be set to a specific instance, which is a function11006 * local queue index. The calling client must be the currently-assigned user of11007 * this VI (see MC_CMD_SET_VI_USER).11008 */11009#define MC_CMD_INIT_RXQ_V4_IN_INSTANCE_OFST 1211010#define MC_CMD_INIT_RXQ_V4_IN_INSTANCE_LEN 411011/* There will be more flags here. */11012#define MC_CMD_INIT_RXQ_V4_IN_FLAGS_OFST 1611013#define MC_CMD_INIT_RXQ_V4_IN_FLAGS_LEN 411014#define MC_CMD_INIT_RXQ_V4_IN_FLAG_BUFF_MODE_OFST 1611015#define MC_CMD_INIT_RXQ_V4_IN_FLAG_BUFF_MODE_LBN 011016#define MC_CMD_INIT_RXQ_V4_IN_FLAG_BUFF_MODE_WIDTH 111017#define MC_CMD_INIT_RXQ_V4_IN_FLAG_HDR_SPLIT_OFST 1611018#define MC_CMD_INIT_RXQ_V4_IN_FLAG_HDR_SPLIT_LBN 111019#define MC_CMD_INIT_RXQ_V4_IN_FLAG_HDR_SPLIT_WIDTH 111020#define MC_CMD_INIT_RXQ_V4_IN_FLAG_TIMESTAMP_OFST 1611021#define MC_CMD_INIT_RXQ_V4_IN_FLAG_TIMESTAMP_LBN 211022#define MC_CMD_INIT_RXQ_V4_IN_FLAG_TIMESTAMP_WIDTH 111023#define MC_CMD_INIT_RXQ_V4_IN_CRC_MODE_OFST 1611024#define MC_CMD_INIT_RXQ_V4_IN_CRC_MODE_LBN 311025#define MC_CMD_INIT_RXQ_V4_IN_CRC_MODE_WIDTH 411026#define MC_CMD_INIT_RXQ_V4_IN_FLAG_CHAIN_OFST 1611027#define MC_CMD_INIT_RXQ_V4_IN_FLAG_CHAIN_LBN 711028#define MC_CMD_INIT_RXQ_V4_IN_FLAG_CHAIN_WIDTH 111029#define MC_CMD_INIT_RXQ_V4_IN_FLAG_PREFIX_OFST 1611030#define MC_CMD_INIT_RXQ_V4_IN_FLAG_PREFIX_LBN 811031#define MC_CMD_INIT_RXQ_V4_IN_FLAG_PREFIX_WIDTH 111032#define MC_CMD_INIT_RXQ_V4_IN_FLAG_DISABLE_SCATTER_OFST 1611033#define MC_CMD_INIT_RXQ_V4_IN_FLAG_DISABLE_SCATTER_LBN 911034#define MC_CMD_INIT_RXQ_V4_IN_FLAG_DISABLE_SCATTER_WIDTH 111035#define MC_CMD_INIT_RXQ_V4_IN_DMA_MODE_OFST 1611036#define MC_CMD_INIT_RXQ_V4_IN_DMA_MODE_LBN 1011037#define MC_CMD_INIT_RXQ_V4_IN_DMA_MODE_WIDTH 411038/* enum: One packet per descriptor (for normal networking) */11039#define MC_CMD_INIT_RXQ_V4_IN_SINGLE_PACKET 0x011040/* enum: Pack multiple packets into large descriptors (for SolarCapture) */11041#define MC_CMD_INIT_RXQ_V4_IN_PACKED_STREAM 0x111042/* enum: Pack multiple packets into large descriptors using the format designed11043 * to maximise packet rate. This mode uses 1 "bucket" per descriptor with11044 * multiple fixed-size packet buffers within each bucket. For a full11045 * description see SF-119419-TC. This mode is only supported by "dpdk" datapath11046 * firmware.11047 */11048#define MC_CMD_INIT_RXQ_V4_IN_EQUAL_STRIDE_SUPER_BUFFER 0x211049/* enum: Deprecated name for EQUAL_STRIDE_SUPER_BUFFER. */11050#define MC_CMD_INIT_RXQ_V4_IN_EQUAL_STRIDE_PACKED_STREAM 0x211051#define MC_CMD_INIT_RXQ_V4_IN_FLAG_SNAPSHOT_MODE_OFST 1611052#define MC_CMD_INIT_RXQ_V4_IN_FLAG_SNAPSHOT_MODE_LBN 1411053#define MC_CMD_INIT_RXQ_V4_IN_FLAG_SNAPSHOT_MODE_WIDTH 111054#define MC_CMD_INIT_RXQ_V4_IN_PACKED_STREAM_BUFF_SIZE_OFST 1611055#define MC_CMD_INIT_RXQ_V4_IN_PACKED_STREAM_BUFF_SIZE_LBN 1511056#define MC_CMD_INIT_RXQ_V4_IN_PACKED_STREAM_BUFF_SIZE_WIDTH 311057#define MC_CMD_INIT_RXQ_V4_IN_PS_BUFF_1M 0x0 /* enum */11058#define MC_CMD_INIT_RXQ_V4_IN_PS_BUFF_512K 0x1 /* enum */11059#define MC_CMD_INIT_RXQ_V4_IN_PS_BUFF_256K 0x2 /* enum */11060#define MC_CMD_INIT_RXQ_V4_IN_PS_BUFF_128K 0x3 /* enum */11061#define MC_CMD_INIT_RXQ_V4_IN_PS_BUFF_64K 0x4 /* enum */11062#define MC_CMD_INIT_RXQ_V4_IN_FLAG_WANT_OUTER_CLASSES_OFST 1611063#define MC_CMD_INIT_RXQ_V4_IN_FLAG_WANT_OUTER_CLASSES_LBN 1811064#define MC_CMD_INIT_RXQ_V4_IN_FLAG_WANT_OUTER_CLASSES_WIDTH 111065#define MC_CMD_INIT_RXQ_V4_IN_FLAG_FORCE_EV_MERGING_OFST 1611066#define MC_CMD_INIT_RXQ_V4_IN_FLAG_FORCE_EV_MERGING_LBN 1911067#define MC_CMD_INIT_RXQ_V4_IN_FLAG_FORCE_EV_MERGING_WIDTH 111068#define MC_CMD_INIT_RXQ_V4_IN_FLAG_NO_CONT_EV_OFST 1611069#define MC_CMD_INIT_RXQ_V4_IN_FLAG_NO_CONT_EV_LBN 2011070#define MC_CMD_INIT_RXQ_V4_IN_FLAG_NO_CONT_EV_WIDTH 111071/* Owner ID to use if in buffer mode (zero if physical) */11072#define MC_CMD_INIT_RXQ_V4_IN_OWNER_ID_OFST 2011073#define MC_CMD_INIT_RXQ_V4_IN_OWNER_ID_LEN 411074/* The port ID associated with the v-adaptor which should contain this DMAQ. */11075#define MC_CMD_INIT_RXQ_V4_IN_PORT_ID_OFST 2411076#define MC_CMD_INIT_RXQ_V4_IN_PORT_ID_LEN 411077/* 64-bit address of 4k of 4k-aligned host memory buffer */11078#define MC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_OFST 2811079#define MC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_LEN 811080#define MC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_LO_OFST 2811081#define MC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_LO_LEN 411082#define MC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_LO_LBN 22411083#define MC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_LO_WIDTH 3211084#define MC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_HI_OFST 3211085#define MC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_HI_LEN 411086#define MC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_HI_LBN 25611087#define MC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_HI_WIDTH 3211088#define MC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_MINNUM 011089#define MC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_MAXNUM 6411090#define MC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_MAXNUM_MCDI2 6411091/* Maximum length of packet to receive, if SNAPSHOT_MODE flag is set */11092#define MC_CMD_INIT_RXQ_V4_IN_SNAPSHOT_LENGTH_OFST 54011093#define MC_CMD_INIT_RXQ_V4_IN_SNAPSHOT_LENGTH_LEN 411094/* The number of packet buffers that will be contained within each11095 * EQUAL_STRIDE_SUPER_BUFFER format bucket supplied by the driver. This field11096 * is ignored unless DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER.11097 */11098#define MC_CMD_INIT_RXQ_V4_IN_ES_PACKET_BUFFERS_PER_BUCKET_OFST 54411099#define MC_CMD_INIT_RXQ_V4_IN_ES_PACKET_BUFFERS_PER_BUCKET_LEN 411100/* The length in bytes of the area in each packet buffer that can be written to11101 * by the adapter. This is used to store the packet prefix and the packet11102 * payload. This length does not include any end padding added by the driver.11103 * This field is ignored unless DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER.11104 */11105#define MC_CMD_INIT_RXQ_V4_IN_ES_MAX_DMA_LEN_OFST 54811106#define MC_CMD_INIT_RXQ_V4_IN_ES_MAX_DMA_LEN_LEN 411107/* The length in bytes of a single packet buffer within a11108 * EQUAL_STRIDE_SUPER_BUFFER format bucket. This field is ignored unless11109 * DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER.11110 */11111#define MC_CMD_INIT_RXQ_V4_IN_ES_PACKET_STRIDE_OFST 55211112#define MC_CMD_INIT_RXQ_V4_IN_ES_PACKET_STRIDE_LEN 411113/* The maximum time in nanoseconds that the datapath will be backpressured if11114 * there are no RX descriptors available. If the timeout is reached and there11115 * are still no descriptors then the packet will be dropped. A timeout of 011116 * means the datapath will never be blocked. This field is ignored unless11117 * DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER.11118 */11119#define MC_CMD_INIT_RXQ_V4_IN_ES_HEAD_OF_LINE_BLOCK_TIMEOUT_OFST 55611120#define MC_CMD_INIT_RXQ_V4_IN_ES_HEAD_OF_LINE_BLOCK_TIMEOUT_LEN 411121/* V4 message data */11122#define MC_CMD_INIT_RXQ_V4_IN_V4_DATA_OFST 56011123#define MC_CMD_INIT_RXQ_V4_IN_V4_DATA_LEN 411124/* Size in bytes of buffers attached to descriptors posted to this queue. Set11125 * to zero if using this message on non-QDMA based platforms. Currently in11126 * Riverhead there is a global limit of eight different buffer sizes across all11127 * active queues. A 2KB and 4KB buffer is guaranteed to be available, but a11128 * request for a different buffer size will fail if there are already eight11129 * other buffer sizes in use. In future Riverhead this limit will go away and11130 * any size will be accepted.11131 */11132#define MC_CMD_INIT_RXQ_V4_IN_BUFFER_SIZE_BYTES_OFST 56011133#define MC_CMD_INIT_RXQ_V4_IN_BUFFER_SIZE_BYTES_LEN 411134 11135/* MC_CMD_INIT_RXQ_V5_IN msgrequest: INIT_RXQ request with ability to request a11136 * different RX packet prefix11137 */11138#define MC_CMD_INIT_RXQ_V5_IN_LEN 56811139/* Size, in entries */11140#define MC_CMD_INIT_RXQ_V5_IN_SIZE_OFST 011141#define MC_CMD_INIT_RXQ_V5_IN_SIZE_LEN 411142/* The EVQ to send events to. This is an index originally specified to11143 * INIT_EVQ. If DMA_MODE == PACKED_STREAM this must be equal to INSTANCE.11144 */11145#define MC_CMD_INIT_RXQ_V5_IN_TARGET_EVQ_OFST 411146#define MC_CMD_INIT_RXQ_V5_IN_TARGET_EVQ_LEN 411147/* The value to put in the event data. Check hardware spec. for valid range.11148 * This field is ignored if DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER or DMA_MODE11149 * == PACKED_STREAM.11150 */11151#define MC_CMD_INIT_RXQ_V5_IN_LABEL_OFST 811152#define MC_CMD_INIT_RXQ_V5_IN_LABEL_LEN 411153/* Desired instance. Must be set to a specific instance, which is a function11154 * local queue index. The calling client must be the currently-assigned user of11155 * this VI (see MC_CMD_SET_VI_USER).11156 */11157#define MC_CMD_INIT_RXQ_V5_IN_INSTANCE_OFST 1211158#define MC_CMD_INIT_RXQ_V5_IN_INSTANCE_LEN 411159/* There will be more flags here. */11160#define MC_CMD_INIT_RXQ_V5_IN_FLAGS_OFST 1611161#define MC_CMD_INIT_RXQ_V5_IN_FLAGS_LEN 411162#define MC_CMD_INIT_RXQ_V5_IN_FLAG_BUFF_MODE_OFST 1611163#define MC_CMD_INIT_RXQ_V5_IN_FLAG_BUFF_MODE_LBN 011164#define MC_CMD_INIT_RXQ_V5_IN_FLAG_BUFF_MODE_WIDTH 111165#define MC_CMD_INIT_RXQ_V5_IN_FLAG_HDR_SPLIT_OFST 1611166#define MC_CMD_INIT_RXQ_V5_IN_FLAG_HDR_SPLIT_LBN 111167#define MC_CMD_INIT_RXQ_V5_IN_FLAG_HDR_SPLIT_WIDTH 111168#define MC_CMD_INIT_RXQ_V5_IN_FLAG_TIMESTAMP_OFST 1611169#define MC_CMD_INIT_RXQ_V5_IN_FLAG_TIMESTAMP_LBN 211170#define MC_CMD_INIT_RXQ_V5_IN_FLAG_TIMESTAMP_WIDTH 111171#define MC_CMD_INIT_RXQ_V5_IN_CRC_MODE_OFST 1611172#define MC_CMD_INIT_RXQ_V5_IN_CRC_MODE_LBN 311173#define MC_CMD_INIT_RXQ_V5_IN_CRC_MODE_WIDTH 411174#define MC_CMD_INIT_RXQ_V5_IN_FLAG_CHAIN_OFST 1611175#define MC_CMD_INIT_RXQ_V5_IN_FLAG_CHAIN_LBN 711176#define MC_CMD_INIT_RXQ_V5_IN_FLAG_CHAIN_WIDTH 111177#define MC_CMD_INIT_RXQ_V5_IN_FLAG_PREFIX_OFST 1611178#define MC_CMD_INIT_RXQ_V5_IN_FLAG_PREFIX_LBN 811179#define MC_CMD_INIT_RXQ_V5_IN_FLAG_PREFIX_WIDTH 111180#define MC_CMD_INIT_RXQ_V5_IN_FLAG_DISABLE_SCATTER_OFST 1611181#define MC_CMD_INIT_RXQ_V5_IN_FLAG_DISABLE_SCATTER_LBN 911182#define MC_CMD_INIT_RXQ_V5_IN_FLAG_DISABLE_SCATTER_WIDTH 111183#define MC_CMD_INIT_RXQ_V5_IN_DMA_MODE_OFST 1611184#define MC_CMD_INIT_RXQ_V5_IN_DMA_MODE_LBN 1011185#define MC_CMD_INIT_RXQ_V5_IN_DMA_MODE_WIDTH 411186/* enum: One packet per descriptor (for normal networking) */11187#define MC_CMD_INIT_RXQ_V5_IN_SINGLE_PACKET 0x011188/* enum: Pack multiple packets into large descriptors (for SolarCapture) */11189#define MC_CMD_INIT_RXQ_V5_IN_PACKED_STREAM 0x111190/* enum: Pack multiple packets into large descriptors using the format designed11191 * to maximise packet rate. This mode uses 1 "bucket" per descriptor with11192 * multiple fixed-size packet buffers within each bucket. For a full11193 * description see SF-119419-TC. This mode is only supported by "dpdk" datapath11194 * firmware.11195 */11196#define MC_CMD_INIT_RXQ_V5_IN_EQUAL_STRIDE_SUPER_BUFFER 0x211197/* enum: Deprecated name for EQUAL_STRIDE_SUPER_BUFFER. */11198#define MC_CMD_INIT_RXQ_V5_IN_EQUAL_STRIDE_PACKED_STREAM 0x211199#define MC_CMD_INIT_RXQ_V5_IN_FLAG_SNAPSHOT_MODE_OFST 1611200#define MC_CMD_INIT_RXQ_V5_IN_FLAG_SNAPSHOT_MODE_LBN 1411201#define MC_CMD_INIT_RXQ_V5_IN_FLAG_SNAPSHOT_MODE_WIDTH 111202#define MC_CMD_INIT_RXQ_V5_IN_PACKED_STREAM_BUFF_SIZE_OFST 1611203#define MC_CMD_INIT_RXQ_V5_IN_PACKED_STREAM_BUFF_SIZE_LBN 1511204#define MC_CMD_INIT_RXQ_V5_IN_PACKED_STREAM_BUFF_SIZE_WIDTH 311205#define MC_CMD_INIT_RXQ_V5_IN_PS_BUFF_1M 0x0 /* enum */11206#define MC_CMD_INIT_RXQ_V5_IN_PS_BUFF_512K 0x1 /* enum */11207#define MC_CMD_INIT_RXQ_V5_IN_PS_BUFF_256K 0x2 /* enum */11208#define MC_CMD_INIT_RXQ_V5_IN_PS_BUFF_128K 0x3 /* enum */11209#define MC_CMD_INIT_RXQ_V5_IN_PS_BUFF_64K 0x4 /* enum */11210#define MC_CMD_INIT_RXQ_V5_IN_FLAG_WANT_OUTER_CLASSES_OFST 1611211#define MC_CMD_INIT_RXQ_V5_IN_FLAG_WANT_OUTER_CLASSES_LBN 1811212#define MC_CMD_INIT_RXQ_V5_IN_FLAG_WANT_OUTER_CLASSES_WIDTH 111213#define MC_CMD_INIT_RXQ_V5_IN_FLAG_FORCE_EV_MERGING_OFST 1611214#define MC_CMD_INIT_RXQ_V5_IN_FLAG_FORCE_EV_MERGING_LBN 1911215#define MC_CMD_INIT_RXQ_V5_IN_FLAG_FORCE_EV_MERGING_WIDTH 111216#define MC_CMD_INIT_RXQ_V5_IN_FLAG_NO_CONT_EV_OFST 1611217#define MC_CMD_INIT_RXQ_V5_IN_FLAG_NO_CONT_EV_LBN 2011218#define MC_CMD_INIT_RXQ_V5_IN_FLAG_NO_CONT_EV_WIDTH 111219/* Owner ID to use if in buffer mode (zero if physical) */11220#define MC_CMD_INIT_RXQ_V5_IN_OWNER_ID_OFST 2011221#define MC_CMD_INIT_RXQ_V5_IN_OWNER_ID_LEN 411222/* The port ID associated with the v-adaptor which should contain this DMAQ. */11223#define MC_CMD_INIT_RXQ_V5_IN_PORT_ID_OFST 2411224#define MC_CMD_INIT_RXQ_V5_IN_PORT_ID_LEN 411225/* 64-bit address of 4k of 4k-aligned host memory buffer */11226#define MC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_OFST 2811227#define MC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_LEN 811228#define MC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_LO_OFST 2811229#define MC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_LO_LEN 411230#define MC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_LO_LBN 22411231#define MC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_LO_WIDTH 3211232#define MC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_HI_OFST 3211233#define MC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_HI_LEN 411234#define MC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_HI_LBN 25611235#define MC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_HI_WIDTH 3211236#define MC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_MINNUM 011237#define MC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_MAXNUM 6411238#define MC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_MAXNUM_MCDI2 6411239/* Maximum length of packet to receive, if SNAPSHOT_MODE flag is set */11240#define MC_CMD_INIT_RXQ_V5_IN_SNAPSHOT_LENGTH_OFST 54011241#define MC_CMD_INIT_RXQ_V5_IN_SNAPSHOT_LENGTH_LEN 411242/* The number of packet buffers that will be contained within each11243 * EQUAL_STRIDE_SUPER_BUFFER format bucket supplied by the driver. This field11244 * is ignored unless DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER.11245 */11246#define MC_CMD_INIT_RXQ_V5_IN_ES_PACKET_BUFFERS_PER_BUCKET_OFST 54411247#define MC_CMD_INIT_RXQ_V5_IN_ES_PACKET_BUFFERS_PER_BUCKET_LEN 411248/* The length in bytes of the area in each packet buffer that can be written to11249 * by the adapter. This is used to store the packet prefix and the packet11250 * payload. This length does not include any end padding added by the driver.11251 * This field is ignored unless DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER.11252 */11253#define MC_CMD_INIT_RXQ_V5_IN_ES_MAX_DMA_LEN_OFST 54811254#define MC_CMD_INIT_RXQ_V5_IN_ES_MAX_DMA_LEN_LEN 411255/* The length in bytes of a single packet buffer within a11256 * EQUAL_STRIDE_SUPER_BUFFER format bucket. This field is ignored unless11257 * DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER.11258 */11259#define MC_CMD_INIT_RXQ_V5_IN_ES_PACKET_STRIDE_OFST 55211260#define MC_CMD_INIT_RXQ_V5_IN_ES_PACKET_STRIDE_LEN 411261/* The maximum time in nanoseconds that the datapath will be backpressured if11262 * there are no RX descriptors available. If the timeout is reached and there11263 * are still no descriptors then the packet will be dropped. A timeout of 011264 * means the datapath will never be blocked. This field is ignored unless11265 * DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER.11266 */11267#define MC_CMD_INIT_RXQ_V5_IN_ES_HEAD_OF_LINE_BLOCK_TIMEOUT_OFST 55611268#define MC_CMD_INIT_RXQ_V5_IN_ES_HEAD_OF_LINE_BLOCK_TIMEOUT_LEN 411269/* V4 message data */11270#define MC_CMD_INIT_RXQ_V5_IN_V4_DATA_OFST 56011271#define MC_CMD_INIT_RXQ_V5_IN_V4_DATA_LEN 411272/* Size in bytes of buffers attached to descriptors posted to this queue. Set11273 * to zero if using this message on non-QDMA based platforms. Currently in11274 * Riverhead there is a global limit of eight different buffer sizes across all11275 * active queues. A 2KB and 4KB buffer is guaranteed to be available, but a11276 * request for a different buffer size will fail if there are already eight11277 * other buffer sizes in use. In future Riverhead this limit will go away and11278 * any size will be accepted.11279 */11280#define MC_CMD_INIT_RXQ_V5_IN_BUFFER_SIZE_BYTES_OFST 56011281#define MC_CMD_INIT_RXQ_V5_IN_BUFFER_SIZE_BYTES_LEN 411282/* Prefix id for the RX prefix format to use on packets delivered this queue.11283 * Zero is always a valid prefix id and means the default prefix format11284 * documented for the platform. Other prefix ids can be obtained by calling11285 * MC_CMD_GET_RX_PREFIX_ID with a requested set of prefix fields.11286 */11287#define MC_CMD_INIT_RXQ_V5_IN_RX_PREFIX_ID_OFST 56411288#define MC_CMD_INIT_RXQ_V5_IN_RX_PREFIX_ID_LEN 411289 11290/* MC_CMD_INIT_RXQ_OUT msgresponse */11291#define MC_CMD_INIT_RXQ_OUT_LEN 011292 11293/* MC_CMD_INIT_RXQ_EXT_OUT msgresponse */11294#define MC_CMD_INIT_RXQ_EXT_OUT_LEN 011295 11296/* MC_CMD_INIT_RXQ_V3_OUT msgresponse */11297#define MC_CMD_INIT_RXQ_V3_OUT_LEN 011298 11299/* MC_CMD_INIT_RXQ_V4_OUT msgresponse */11300#define MC_CMD_INIT_RXQ_V4_OUT_LEN 011301 11302/* MC_CMD_INIT_RXQ_V5_OUT msgresponse */11303#define MC_CMD_INIT_RXQ_V5_OUT_LEN 011304 11305 11306/***********************************/11307/* MC_CMD_INIT_TXQ11308 */11309#define MC_CMD_INIT_TXQ 0x8211310#undef MC_CMD_0x82_PRIVILEGE_CTG11311 11312#define MC_CMD_0x82_PRIVILEGE_CTG SRIOV_CTG_GENERAL11313 11314/* MC_CMD_INIT_TXQ_IN msgrequest: Legacy INIT_TXQ request. Use extended version11315 * in new code.11316 */11317#define MC_CMD_INIT_TXQ_IN_LENMIN 3611318#define MC_CMD_INIT_TXQ_IN_LENMAX 25211319#define MC_CMD_INIT_TXQ_IN_LENMAX_MCDI2 102011320#define MC_CMD_INIT_TXQ_IN_LEN(num) (28+8*(num))11321#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_NUM(len) (((len)-28)/8)11322/* Size, in entries */11323#define MC_CMD_INIT_TXQ_IN_SIZE_OFST 011324#define MC_CMD_INIT_TXQ_IN_SIZE_LEN 411325/* The EVQ to send events to. This is an index originally specified to11326 * INIT_EVQ.11327 */11328#define MC_CMD_INIT_TXQ_IN_TARGET_EVQ_OFST 411329#define MC_CMD_INIT_TXQ_IN_TARGET_EVQ_LEN 411330/* The value to put in the event data. Check hardware spec. for valid range. */11331#define MC_CMD_INIT_TXQ_IN_LABEL_OFST 811332#define MC_CMD_INIT_TXQ_IN_LABEL_LEN 411333/* Desired instance. Must be set to a specific instance, which is a function11334 * local queue index. The calling client must be the currently-assigned user of11335 * this VI (see MC_CMD_SET_VI_USER).11336 */11337#define MC_CMD_INIT_TXQ_IN_INSTANCE_OFST 1211338#define MC_CMD_INIT_TXQ_IN_INSTANCE_LEN 411339/* There will be more flags here. */11340#define MC_CMD_INIT_TXQ_IN_FLAGS_OFST 1611341#define MC_CMD_INIT_TXQ_IN_FLAGS_LEN 411342#define MC_CMD_INIT_TXQ_IN_FLAG_BUFF_MODE_OFST 1611343#define MC_CMD_INIT_TXQ_IN_FLAG_BUFF_MODE_LBN 011344#define MC_CMD_INIT_TXQ_IN_FLAG_BUFF_MODE_WIDTH 111345#define MC_CMD_INIT_TXQ_IN_FLAG_IP_CSUM_DIS_OFST 1611346#define MC_CMD_INIT_TXQ_IN_FLAG_IP_CSUM_DIS_LBN 111347#define MC_CMD_INIT_TXQ_IN_FLAG_IP_CSUM_DIS_WIDTH 111348#define MC_CMD_INIT_TXQ_IN_FLAG_TCP_CSUM_DIS_OFST 1611349#define MC_CMD_INIT_TXQ_IN_FLAG_TCP_CSUM_DIS_LBN 211350#define MC_CMD_INIT_TXQ_IN_FLAG_TCP_CSUM_DIS_WIDTH 111351#define MC_CMD_INIT_TXQ_IN_FLAG_TCP_UDP_ONLY_OFST 1611352#define MC_CMD_INIT_TXQ_IN_FLAG_TCP_UDP_ONLY_LBN 311353#define MC_CMD_INIT_TXQ_IN_FLAG_TCP_UDP_ONLY_WIDTH 111354#define MC_CMD_INIT_TXQ_IN_CRC_MODE_OFST 1611355#define MC_CMD_INIT_TXQ_IN_CRC_MODE_LBN 411356#define MC_CMD_INIT_TXQ_IN_CRC_MODE_WIDTH 411357#define MC_CMD_INIT_TXQ_IN_FLAG_TIMESTAMP_OFST 1611358#define MC_CMD_INIT_TXQ_IN_FLAG_TIMESTAMP_LBN 811359#define MC_CMD_INIT_TXQ_IN_FLAG_TIMESTAMP_WIDTH 111360#define MC_CMD_INIT_TXQ_IN_FLAG_PACER_BYPASS_OFST 1611361#define MC_CMD_INIT_TXQ_IN_FLAG_PACER_BYPASS_LBN 911362#define MC_CMD_INIT_TXQ_IN_FLAG_PACER_BYPASS_WIDTH 111363#define MC_CMD_INIT_TXQ_IN_FLAG_INNER_IP_CSUM_EN_OFST 1611364#define MC_CMD_INIT_TXQ_IN_FLAG_INNER_IP_CSUM_EN_LBN 1011365#define MC_CMD_INIT_TXQ_IN_FLAG_INNER_IP_CSUM_EN_WIDTH 111366#define MC_CMD_INIT_TXQ_IN_FLAG_INNER_TCP_CSUM_EN_OFST 1611367#define MC_CMD_INIT_TXQ_IN_FLAG_INNER_TCP_CSUM_EN_LBN 1111368#define MC_CMD_INIT_TXQ_IN_FLAG_INNER_TCP_CSUM_EN_WIDTH 111369/* Owner ID to use if in buffer mode (zero if physical) */11370#define MC_CMD_INIT_TXQ_IN_OWNER_ID_OFST 2011371#define MC_CMD_INIT_TXQ_IN_OWNER_ID_LEN 411372/* The port ID associated with the v-adaptor which should contain this DMAQ. */11373#define MC_CMD_INIT_TXQ_IN_PORT_ID_OFST 2411374#define MC_CMD_INIT_TXQ_IN_PORT_ID_LEN 411375/* 64-bit address of 4k of 4k-aligned host memory buffer */11376#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_OFST 2811377#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_LEN 811378#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_LO_OFST 2811379#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_LO_LEN 411380#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_LO_LBN 22411381#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_LO_WIDTH 3211382#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_HI_OFST 3211383#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_HI_LEN 411384#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_HI_LBN 25611385#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_HI_WIDTH 3211386#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_MINNUM 111387#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_MAXNUM 2811388#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_MAXNUM_MCDI2 12411389 11390/* MC_CMD_INIT_TXQ_EXT_IN msgrequest: Extended INIT_TXQ with additional mode11391 * flags11392 */11393#define MC_CMD_INIT_TXQ_EXT_IN_LEN 54411394/* Size, in entries */11395#define MC_CMD_INIT_TXQ_EXT_IN_SIZE_OFST 011396#define MC_CMD_INIT_TXQ_EXT_IN_SIZE_LEN 411397/* The EVQ to send events to. This is an index originally specified to11398 * INIT_EVQ.11399 */11400#define MC_CMD_INIT_TXQ_EXT_IN_TARGET_EVQ_OFST 411401#define MC_CMD_INIT_TXQ_EXT_IN_TARGET_EVQ_LEN 411402/* The value to put in the event data. Check hardware spec. for valid range. */11403#define MC_CMD_INIT_TXQ_EXT_IN_LABEL_OFST 811404#define MC_CMD_INIT_TXQ_EXT_IN_LABEL_LEN 411405/* Desired instance. Must be set to a specific instance, which is a function11406 * local queue index. The calling client must be the currently-assigned user of11407 * this VI (see MC_CMD_SET_VI_USER).11408 */11409#define MC_CMD_INIT_TXQ_EXT_IN_INSTANCE_OFST 1211410#define MC_CMD_INIT_TXQ_EXT_IN_INSTANCE_LEN 411411/* There will be more flags here. */11412#define MC_CMD_INIT_TXQ_EXT_IN_FLAGS_OFST 1611413#define MC_CMD_INIT_TXQ_EXT_IN_FLAGS_LEN 411414#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_BUFF_MODE_OFST 1611415#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_BUFF_MODE_LBN 011416#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_BUFF_MODE_WIDTH 111417#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_IP_CSUM_DIS_OFST 1611418#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_IP_CSUM_DIS_LBN 111419#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_IP_CSUM_DIS_WIDTH 111420#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_CSUM_DIS_OFST 1611421#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_CSUM_DIS_LBN 211422#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_CSUM_DIS_WIDTH 111423#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_UDP_ONLY_OFST 1611424#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_UDP_ONLY_LBN 311425#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_UDP_ONLY_WIDTH 111426#define MC_CMD_INIT_TXQ_EXT_IN_CRC_MODE_OFST 1611427#define MC_CMD_INIT_TXQ_EXT_IN_CRC_MODE_LBN 411428#define MC_CMD_INIT_TXQ_EXT_IN_CRC_MODE_WIDTH 411429#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TIMESTAMP_OFST 1611430#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TIMESTAMP_LBN 811431#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TIMESTAMP_WIDTH 111432#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_PACER_BYPASS_OFST 1611433#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_PACER_BYPASS_LBN 911434#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_PACER_BYPASS_WIDTH 111435#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_IP_CSUM_EN_OFST 1611436#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_IP_CSUM_EN_LBN 1011437#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_IP_CSUM_EN_WIDTH 111438#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_TCP_CSUM_EN_OFST 1611439#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_TCP_CSUM_EN_LBN 1111440#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_TCP_CSUM_EN_WIDTH 111441#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TSOV2_EN_OFST 1611442#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TSOV2_EN_LBN 1211443#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TSOV2_EN_WIDTH 111444#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_CTPIO_OFST 1611445#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_CTPIO_LBN 1311446#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_CTPIO_WIDTH 111447#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_CTPIO_UTHRESH_OFST 1611448#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_CTPIO_UTHRESH_LBN 1411449#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_CTPIO_UTHRESH_WIDTH 111450#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_M2M_D2C_OFST 1611451#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_M2M_D2C_LBN 1511452#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_M2M_D2C_WIDTH 111453#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_DESC_PROXY_OFST 1611454#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_DESC_PROXY_LBN 1611455#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_DESC_PROXY_WIDTH 111456#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_ABS_TARGET_EVQ_OFST 1611457#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_ABS_TARGET_EVQ_LBN 1711458#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_ABS_TARGET_EVQ_WIDTH 111459/* Owner ID to use if in buffer mode (zero if physical) */11460#define MC_CMD_INIT_TXQ_EXT_IN_OWNER_ID_OFST 2011461#define MC_CMD_INIT_TXQ_EXT_IN_OWNER_ID_LEN 411462/* The port ID associated with the v-adaptor which should contain this DMAQ. */11463#define MC_CMD_INIT_TXQ_EXT_IN_PORT_ID_OFST 2411464#define MC_CMD_INIT_TXQ_EXT_IN_PORT_ID_LEN 411465/* 64-bit address of 4k of 4k-aligned host memory buffer */11466#define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_OFST 2811467#define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_LEN 811468#define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_LO_OFST 2811469#define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_LO_LEN 411470#define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_LO_LBN 22411471#define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_LO_WIDTH 3211472#define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_HI_OFST 3211473#define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_HI_LEN 411474#define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_HI_LBN 25611475#define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_HI_WIDTH 3211476#define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_MINNUM 011477#define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_MAXNUM 6411478#define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_MAXNUM_MCDI2 6411479/* Flags related to Qbb flow control mode. */11480#define MC_CMD_INIT_TXQ_EXT_IN_QBB_FLAGS_OFST 54011481#define MC_CMD_INIT_TXQ_EXT_IN_QBB_FLAGS_LEN 411482#define MC_CMD_INIT_TXQ_EXT_IN_QBB_ENABLE_OFST 54011483#define MC_CMD_INIT_TXQ_EXT_IN_QBB_ENABLE_LBN 011484#define MC_CMD_INIT_TXQ_EXT_IN_QBB_ENABLE_WIDTH 111485#define MC_CMD_INIT_TXQ_EXT_IN_QBB_PRIORITY_OFST 54011486#define MC_CMD_INIT_TXQ_EXT_IN_QBB_PRIORITY_LBN 111487#define MC_CMD_INIT_TXQ_EXT_IN_QBB_PRIORITY_WIDTH 311488 11489/* MC_CMD_INIT_TXQ_OUT msgresponse */11490#define MC_CMD_INIT_TXQ_OUT_LEN 011491 11492 11493/***********************************/11494/* MC_CMD_FINI_EVQ11495 * Teardown an EVQ.11496 *11497 * All DMAQs or EVQs that point to the EVQ to tear down must be torn down first11498 * or the operation will fail with EBUSY11499 */11500#define MC_CMD_FINI_EVQ 0x8311501#undef MC_CMD_0x83_PRIVILEGE_CTG11502 11503#define MC_CMD_0x83_PRIVILEGE_CTG SRIOV_CTG_GENERAL11504 11505/* MC_CMD_FINI_EVQ_IN msgrequest */11506#define MC_CMD_FINI_EVQ_IN_LEN 411507/* Instance of EVQ to destroy. Should be the same instance as that previously11508 * passed to INIT_EVQ11509 */11510#define MC_CMD_FINI_EVQ_IN_INSTANCE_OFST 011511#define MC_CMD_FINI_EVQ_IN_INSTANCE_LEN 411512 11513/* MC_CMD_FINI_EVQ_OUT msgresponse */11514#define MC_CMD_FINI_EVQ_OUT_LEN 011515 11516 11517/***********************************/11518/* MC_CMD_FINI_RXQ11519 * Teardown a RXQ.11520 */11521#define MC_CMD_FINI_RXQ 0x8411522#undef MC_CMD_0x84_PRIVILEGE_CTG11523 11524#define MC_CMD_0x84_PRIVILEGE_CTG SRIOV_CTG_GENERAL11525 11526/* MC_CMD_FINI_RXQ_IN msgrequest */11527#define MC_CMD_FINI_RXQ_IN_LEN 411528/* Instance of RXQ to destroy */11529#define MC_CMD_FINI_RXQ_IN_INSTANCE_OFST 011530#define MC_CMD_FINI_RXQ_IN_INSTANCE_LEN 411531 11532/* MC_CMD_FINI_RXQ_OUT msgresponse */11533#define MC_CMD_FINI_RXQ_OUT_LEN 011534 11535 11536/***********************************/11537/* MC_CMD_FINI_TXQ11538 * Teardown a TXQ.11539 */11540#define MC_CMD_FINI_TXQ 0x8511541#undef MC_CMD_0x85_PRIVILEGE_CTG11542 11543#define MC_CMD_0x85_PRIVILEGE_CTG SRIOV_CTG_GENERAL11544 11545/* MC_CMD_FINI_TXQ_IN msgrequest */11546#define MC_CMD_FINI_TXQ_IN_LEN 411547/* Instance of TXQ to destroy */11548#define MC_CMD_FINI_TXQ_IN_INSTANCE_OFST 011549#define MC_CMD_FINI_TXQ_IN_INSTANCE_LEN 411550 11551/* MC_CMD_FINI_TXQ_OUT msgresponse */11552#define MC_CMD_FINI_TXQ_OUT_LEN 011553 11554 11555/***********************************/11556/* MC_CMD_DRIVER_EVENT11557 * Generate an event on an EVQ belonging to the function issuing the command.11558 */11559#define MC_CMD_DRIVER_EVENT 0x8611560#undef MC_CMD_0x86_PRIVILEGE_CTG11561 11562#define MC_CMD_0x86_PRIVILEGE_CTG SRIOV_CTG_GENERAL11563 11564/* MC_CMD_DRIVER_EVENT_IN msgrequest */11565#define MC_CMD_DRIVER_EVENT_IN_LEN 1211566/* Handle of target EVQ */11567#define MC_CMD_DRIVER_EVENT_IN_EVQ_OFST 011568#define MC_CMD_DRIVER_EVENT_IN_EVQ_LEN 411569/* Bits 0 - 63 of event */11570#define MC_CMD_DRIVER_EVENT_IN_DATA_OFST 411571#define MC_CMD_DRIVER_EVENT_IN_DATA_LEN 811572#define MC_CMD_DRIVER_EVENT_IN_DATA_LO_OFST 411573#define MC_CMD_DRIVER_EVENT_IN_DATA_LO_LEN 411574#define MC_CMD_DRIVER_EVENT_IN_DATA_LO_LBN 3211575#define MC_CMD_DRIVER_EVENT_IN_DATA_LO_WIDTH 3211576#define MC_CMD_DRIVER_EVENT_IN_DATA_HI_OFST 811577#define MC_CMD_DRIVER_EVENT_IN_DATA_HI_LEN 411578#define MC_CMD_DRIVER_EVENT_IN_DATA_HI_LBN 6411579#define MC_CMD_DRIVER_EVENT_IN_DATA_HI_WIDTH 3211580 11581/* MC_CMD_DRIVER_EVENT_OUT msgresponse */11582#define MC_CMD_DRIVER_EVENT_OUT_LEN 011583 11584 11585/***********************************/11586/* MC_CMD_PROXY_CMD11587 * Execute an arbitrary MCDI command on behalf of a different function, subject11588 * to security restrictions. The command to be proxied follows immediately11589 * afterward in the host buffer (or on the UART). This command supercedes11590 * MC_CMD_SET_FUNC, which remains available for Siena but now deprecated.11591 */11592#define MC_CMD_PROXY_CMD 0x5b11593#undef MC_CMD_0x5b_PRIVILEGE_CTG11594 11595#define MC_CMD_0x5b_PRIVILEGE_CTG SRIOV_CTG_ADMIN11596 11597/* MC_CMD_PROXY_CMD_IN msgrequest */11598#define MC_CMD_PROXY_CMD_IN_LEN 411599/* The handle of the target function. */11600#define MC_CMD_PROXY_CMD_IN_TARGET_OFST 011601#define MC_CMD_PROXY_CMD_IN_TARGET_LEN 411602#define MC_CMD_PROXY_CMD_IN_TARGET_PF_OFST 011603#define MC_CMD_PROXY_CMD_IN_TARGET_PF_LBN 011604#define MC_CMD_PROXY_CMD_IN_TARGET_PF_WIDTH 1611605#define MC_CMD_PROXY_CMD_IN_TARGET_VF_OFST 011606#define MC_CMD_PROXY_CMD_IN_TARGET_VF_LBN 1611607#define MC_CMD_PROXY_CMD_IN_TARGET_VF_WIDTH 1611608#define MC_CMD_PROXY_CMD_IN_VF_NULL 0xffff /* enum */11609 11610/* MC_CMD_PROXY_CMD_OUT msgresponse */11611#define MC_CMD_PROXY_CMD_OUT_LEN 011612 11613/* MC_PROXY_STATUS_BUFFER structuredef: Host memory status buffer used to11614 * manage proxied requests11615 */11616#define MC_PROXY_STATUS_BUFFER_LEN 1611617/* Handle allocated by the firmware for this proxy transaction */11618#define MC_PROXY_STATUS_BUFFER_HANDLE_OFST 011619#define MC_PROXY_STATUS_BUFFER_HANDLE_LEN 411620/* enum: An invalid handle. */11621#define MC_PROXY_STATUS_BUFFER_HANDLE_INVALID 0x011622#define MC_PROXY_STATUS_BUFFER_HANDLE_LBN 011623#define MC_PROXY_STATUS_BUFFER_HANDLE_WIDTH 3211624/* The requesting physical function number */11625#define MC_PROXY_STATUS_BUFFER_PF_OFST 411626#define MC_PROXY_STATUS_BUFFER_PF_LEN 211627#define MC_PROXY_STATUS_BUFFER_PF_LBN 3211628#define MC_PROXY_STATUS_BUFFER_PF_WIDTH 1611629/* The requesting virtual function number. Set to VF_NULL if the target is a11630 * PF.11631 */11632#define MC_PROXY_STATUS_BUFFER_VF_OFST 611633#define MC_PROXY_STATUS_BUFFER_VF_LEN 211634#define MC_PROXY_STATUS_BUFFER_VF_LBN 4811635#define MC_PROXY_STATUS_BUFFER_VF_WIDTH 1611636/* The target function RID. */11637#define MC_PROXY_STATUS_BUFFER_RID_OFST 811638#define MC_PROXY_STATUS_BUFFER_RID_LEN 211639#define MC_PROXY_STATUS_BUFFER_RID_LBN 6411640#define MC_PROXY_STATUS_BUFFER_RID_WIDTH 1611641/* The status of the proxy as described in MC_CMD_PROXY_COMPLETE. */11642#define MC_PROXY_STATUS_BUFFER_STATUS_OFST 1011643#define MC_PROXY_STATUS_BUFFER_STATUS_LEN 211644#define MC_PROXY_STATUS_BUFFER_STATUS_LBN 8011645#define MC_PROXY_STATUS_BUFFER_STATUS_WIDTH 1611646/* If a request is authorized rather than carried out by the host, this is the11647 * elevated privilege mask granted to the requesting function.11648 */11649#define MC_PROXY_STATUS_BUFFER_GRANTED_PRIVILEGES_OFST 1211650#define MC_PROXY_STATUS_BUFFER_GRANTED_PRIVILEGES_LEN 411651#define MC_PROXY_STATUS_BUFFER_GRANTED_PRIVILEGES_LBN 9611652#define MC_PROXY_STATUS_BUFFER_GRANTED_PRIVILEGES_WIDTH 3211653 11654 11655/***********************************/11656/* MC_CMD_PROXY_CONFIGURE11657 * Enable/disable authorization of MCDI requests from unprivileged functions by11658 * a designated admin function11659 */11660#define MC_CMD_PROXY_CONFIGURE 0x5811661#undef MC_CMD_0x58_PRIVILEGE_CTG11662 11663#define MC_CMD_0x58_PRIVILEGE_CTG SRIOV_CTG_ADMIN11664 11665/* MC_CMD_PROXY_CONFIGURE_IN msgrequest */11666#define MC_CMD_PROXY_CONFIGURE_IN_LEN 10811667#define MC_CMD_PROXY_CONFIGURE_IN_FLAGS_OFST 011668#define MC_CMD_PROXY_CONFIGURE_IN_FLAGS_LEN 411669#define MC_CMD_PROXY_CONFIGURE_IN_ENABLE_OFST 011670#define MC_CMD_PROXY_CONFIGURE_IN_ENABLE_LBN 011671#define MC_CMD_PROXY_CONFIGURE_IN_ENABLE_WIDTH 111672/* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS11673 * of blocks, each of the size REQUEST_BLOCK_SIZE.11674 */11675#define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_OFST 411676#define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_LEN 811677#define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_LO_OFST 411678#define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_LO_LEN 411679#define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_LO_LBN 3211680#define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_LO_WIDTH 3211681#define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_HI_OFST 811682#define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_HI_LEN 411683#define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_HI_LBN 6411684#define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_HI_WIDTH 3211685/* Must be a power of 2 */11686#define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BLOCK_SIZE_OFST 1211687#define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BLOCK_SIZE_LEN 411688/* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS11689 * of blocks, each of the size REPLY_BLOCK_SIZE.11690 */11691#define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_OFST 1611692#define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_LEN 811693#define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_LO_OFST 1611694#define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_LO_LEN 411695#define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_LO_LBN 12811696#define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_LO_WIDTH 3211697#define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_HI_OFST 2011698#define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_HI_LEN 411699#define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_HI_LBN 16011700#define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_HI_WIDTH 3211701/* Must be a power of 2 */11702#define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BLOCK_SIZE_OFST 2411703#define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BLOCK_SIZE_LEN 411704/* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS11705 * of blocks, each of the size STATUS_BLOCK_SIZE. This buffer is only needed if11706 * host intends to complete proxied operations by using MC_CMD_PROXY_CMD.11707 */11708#define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_OFST 2811709#define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_LEN 811710#define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_LO_OFST 2811711#define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_LO_LEN 411712#define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_LO_LBN 22411713#define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_LO_WIDTH 3211714#define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_HI_OFST 3211715#define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_HI_LEN 411716#define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_HI_LBN 25611717#define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_HI_WIDTH 3211718/* Must be a power of 2, or zero if this buffer is not provided */11719#define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BLOCK_SIZE_OFST 3611720#define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BLOCK_SIZE_LEN 411721/* Applies to all three buffers */11722#define MC_CMD_PROXY_CONFIGURE_IN_NUM_BLOCKS_OFST 4011723#define MC_CMD_PROXY_CONFIGURE_IN_NUM_BLOCKS_LEN 411724/* A bit mask defining which MCDI operations may be proxied */11725#define MC_CMD_PROXY_CONFIGURE_IN_ALLOWED_MCDI_MASK_OFST 4411726#define MC_CMD_PROXY_CONFIGURE_IN_ALLOWED_MCDI_MASK_LEN 6411727 11728/* MC_CMD_PROXY_CONFIGURE_EXT_IN msgrequest */11729#define MC_CMD_PROXY_CONFIGURE_EXT_IN_LEN 11211730#define MC_CMD_PROXY_CONFIGURE_EXT_IN_FLAGS_OFST 011731#define MC_CMD_PROXY_CONFIGURE_EXT_IN_FLAGS_LEN 411732#define MC_CMD_PROXY_CONFIGURE_EXT_IN_ENABLE_OFST 011733#define MC_CMD_PROXY_CONFIGURE_EXT_IN_ENABLE_LBN 011734#define MC_CMD_PROXY_CONFIGURE_EXT_IN_ENABLE_WIDTH 111735/* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS11736 * of blocks, each of the size REQUEST_BLOCK_SIZE.11737 */11738#define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_OFST 411739#define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_LEN 811740#define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_LO_OFST 411741#define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_LO_LEN 411742#define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_LO_LBN 3211743#define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_LO_WIDTH 3211744#define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_HI_OFST 811745#define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_HI_LEN 411746#define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_HI_LBN 6411747#define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_HI_WIDTH 3211748/* Must be a power of 2 */11749#define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BLOCK_SIZE_OFST 1211750#define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BLOCK_SIZE_LEN 411751/* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS11752 * of blocks, each of the size REPLY_BLOCK_SIZE.11753 */11754#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_OFST 1611755#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_LEN 811756#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_LO_OFST 1611757#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_LO_LEN 411758#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_LO_LBN 12811759#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_LO_WIDTH 3211760#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_HI_OFST 2011761#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_HI_LEN 411762#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_HI_LBN 16011763#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_HI_WIDTH 3211764/* Must be a power of 2 */11765#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BLOCK_SIZE_OFST 2411766#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BLOCK_SIZE_LEN 411767/* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS11768 * of blocks, each of the size STATUS_BLOCK_SIZE. This buffer is only needed if11769 * host intends to complete proxied operations by using MC_CMD_PROXY_CMD.11770 */11771#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_OFST 2811772#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_LEN 811773#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_LO_OFST 2811774#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_LO_LEN 411775#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_LO_LBN 22411776#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_LO_WIDTH 3211777#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_HI_OFST 3211778#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_HI_LEN 411779#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_HI_LBN 25611780#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_HI_WIDTH 3211781/* Must be a power of 2, or zero if this buffer is not provided */11782#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BLOCK_SIZE_OFST 3611783#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BLOCK_SIZE_LEN 411784/* Applies to all three buffers */11785#define MC_CMD_PROXY_CONFIGURE_EXT_IN_NUM_BLOCKS_OFST 4011786#define MC_CMD_PROXY_CONFIGURE_EXT_IN_NUM_BLOCKS_LEN 411787/* A bit mask defining which MCDI operations may be proxied */11788#define MC_CMD_PROXY_CONFIGURE_EXT_IN_ALLOWED_MCDI_MASK_OFST 4411789#define MC_CMD_PROXY_CONFIGURE_EXT_IN_ALLOWED_MCDI_MASK_LEN 6411790#define MC_CMD_PROXY_CONFIGURE_EXT_IN_RESERVED_OFST 10811791#define MC_CMD_PROXY_CONFIGURE_EXT_IN_RESERVED_LEN 411792 11793/* MC_CMD_PROXY_CONFIGURE_OUT msgresponse */11794#define MC_CMD_PROXY_CONFIGURE_OUT_LEN 011795 11796 11797/***********************************/11798/* MC_CMD_PROXY_COMPLETE11799 * Tells FW that a requested proxy operation has either been completed (by11800 * using MC_CMD_PROXY_CMD) or authorized/declined. May only be sent by the11801 * function that enabled proxying/authorization (by using11802 * MC_CMD_PROXY_CONFIGURE).11803 */11804#define MC_CMD_PROXY_COMPLETE 0x5f11805#undef MC_CMD_0x5f_PRIVILEGE_CTG11806 11807#define MC_CMD_0x5f_PRIVILEGE_CTG SRIOV_CTG_ADMIN11808 11809/* MC_CMD_PROXY_COMPLETE_IN msgrequest */11810#define MC_CMD_PROXY_COMPLETE_IN_LEN 1211811#define MC_CMD_PROXY_COMPLETE_IN_BLOCK_INDEX_OFST 011812#define MC_CMD_PROXY_COMPLETE_IN_BLOCK_INDEX_LEN 411813#define MC_CMD_PROXY_COMPLETE_IN_STATUS_OFST 411814#define MC_CMD_PROXY_COMPLETE_IN_STATUS_LEN 411815/* enum: The operation has been completed by using MC_CMD_PROXY_CMD, the reply11816 * is stored in the REPLY_BUFF.11817 */11818#define MC_CMD_PROXY_COMPLETE_IN_COMPLETE 0x011819/* enum: The operation has been authorized. The originating function may now11820 * try again.11821 */11822#define MC_CMD_PROXY_COMPLETE_IN_AUTHORIZED 0x111823/* enum: The operation has been declined. */11824#define MC_CMD_PROXY_COMPLETE_IN_DECLINED 0x211825/* enum: The authorization failed because the relevant application did not11826 * respond in time.11827 */11828#define MC_CMD_PROXY_COMPLETE_IN_TIMEDOUT 0x311829#define MC_CMD_PROXY_COMPLETE_IN_HANDLE_OFST 811830#define MC_CMD_PROXY_COMPLETE_IN_HANDLE_LEN 411831 11832/* MC_CMD_PROXY_COMPLETE_OUT msgresponse */11833#define MC_CMD_PROXY_COMPLETE_OUT_LEN 011834 11835 11836/***********************************/11837/* MC_CMD_ALLOC_BUFTBL_CHUNK11838 * Allocate a set of buffer table entries using the specified owner ID. This11839 * operation allocates the required buffer table entries (and fails if it11840 * cannot do so). The buffer table entries will initially be zeroed.11841 */11842#define MC_CMD_ALLOC_BUFTBL_CHUNK 0x8711843#undef MC_CMD_0x87_PRIVILEGE_CTG11844 11845#define MC_CMD_0x87_PRIVILEGE_CTG SRIOV_CTG_ONLOAD11846 11847/* MC_CMD_ALLOC_BUFTBL_CHUNK_IN msgrequest */11848#define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_LEN 811849/* Owner ID to use */11850#define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_OWNER_OFST 011851#define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_OWNER_LEN 411852/* Size of buffer table pages to use, in bytes (note that only a few values are11853 * legal on any specific hardware).11854 */11855#define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_PAGE_SIZE_OFST 411856#define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_PAGE_SIZE_LEN 411857 11858/* MC_CMD_ALLOC_BUFTBL_CHUNK_OUT msgresponse */11859#define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_LEN 1211860#define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_HANDLE_OFST 011861#define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_HANDLE_LEN 411862#define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_NUMENTRIES_OFST 411863#define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_NUMENTRIES_LEN 411864/* Buffer table IDs for use in DMA descriptors. */11865#define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_ID_OFST 811866#define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_ID_LEN 411867 11868 11869/***********************************/11870/* MC_CMD_PROGRAM_BUFTBL_ENTRIES11871 * Reprogram a set of buffer table entries in the specified chunk.11872 */11873#define MC_CMD_PROGRAM_BUFTBL_ENTRIES 0x8811874#undef MC_CMD_0x88_PRIVILEGE_CTG11875 11876#define MC_CMD_0x88_PRIVILEGE_CTG SRIOV_CTG_ONLOAD11877 11878/* MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN msgrequest */11879#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LENMIN 2011880#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LENMAX 26811881#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LENMAX_MCDI2 26811882#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LEN(num) (12+8*(num))11883#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_NUM(len) (((len)-12)/8)11884#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_HANDLE_OFST 011885#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_HANDLE_LEN 411886/* ID */11887#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_FIRSTID_OFST 411888#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_FIRSTID_LEN 411889/* Num entries */11890#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_NUMENTRIES_OFST 811891#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_NUMENTRIES_LEN 411892/* Buffer table entry address */11893#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_OFST 1211894#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_LEN 811895#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_LO_OFST 1211896#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_LO_LEN 411897#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_LO_LBN 9611898#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_LO_WIDTH 3211899#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_HI_OFST 1611900#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_HI_LEN 411901#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_HI_LBN 12811902#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_HI_WIDTH 3211903#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_MINNUM 111904#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_MAXNUM 3211905#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_MAXNUM_MCDI2 3211906 11907/* MC_CMD_PROGRAM_BUFTBL_ENTRIES_OUT msgresponse */11908#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_OUT_LEN 011909 11910 11911/***********************************/11912/* MC_CMD_FREE_BUFTBL_CHUNK11913 */11914#define MC_CMD_FREE_BUFTBL_CHUNK 0x8911915#undef MC_CMD_0x89_PRIVILEGE_CTG11916 11917#define MC_CMD_0x89_PRIVILEGE_CTG SRIOV_CTG_ONLOAD11918 11919/* MC_CMD_FREE_BUFTBL_CHUNK_IN msgrequest */11920#define MC_CMD_FREE_BUFTBL_CHUNK_IN_LEN 411921#define MC_CMD_FREE_BUFTBL_CHUNK_IN_HANDLE_OFST 011922#define MC_CMD_FREE_BUFTBL_CHUNK_IN_HANDLE_LEN 411923 11924/* MC_CMD_FREE_BUFTBL_CHUNK_OUT msgresponse */11925#define MC_CMD_FREE_BUFTBL_CHUNK_OUT_LEN 011926 11927 11928/***********************************/11929/* MC_CMD_FILTER_OP11930 * Multiplexed MCDI call for filter operations11931 */11932#define MC_CMD_FILTER_OP 0x8a11933#undef MC_CMD_0x8a_PRIVILEGE_CTG11934 11935#define MC_CMD_0x8a_PRIVILEGE_CTG SRIOV_CTG_GENERAL11936 11937/* MC_CMD_FILTER_OP_IN msgrequest */11938#define MC_CMD_FILTER_OP_IN_LEN 10811939/* identifies the type of operation requested */11940#define MC_CMD_FILTER_OP_IN_OP_OFST 011941#define MC_CMD_FILTER_OP_IN_OP_LEN 411942/* enum: single-recipient filter insert */11943#define MC_CMD_FILTER_OP_IN_OP_INSERT 0x011944/* enum: single-recipient filter remove */11945#define MC_CMD_FILTER_OP_IN_OP_REMOVE 0x111946/* enum: multi-recipient filter subscribe */11947#define MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE 0x211948/* enum: multi-recipient filter unsubscribe */11949#define MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE 0x311950/* enum: replace one recipient with another (warning - the filter handle may11951 * change)11952 */11953#define MC_CMD_FILTER_OP_IN_OP_REPLACE 0x411954/* filter handle (for remove / unsubscribe operations) */11955#define MC_CMD_FILTER_OP_IN_HANDLE_OFST 411956#define MC_CMD_FILTER_OP_IN_HANDLE_LEN 811957#define MC_CMD_FILTER_OP_IN_HANDLE_LO_OFST 411958#define MC_CMD_FILTER_OP_IN_HANDLE_LO_LEN 411959#define MC_CMD_FILTER_OP_IN_HANDLE_LO_LBN 3211960#define MC_CMD_FILTER_OP_IN_HANDLE_LO_WIDTH 3211961#define MC_CMD_FILTER_OP_IN_HANDLE_HI_OFST 811962#define MC_CMD_FILTER_OP_IN_HANDLE_HI_LEN 411963#define MC_CMD_FILTER_OP_IN_HANDLE_HI_LBN 6411964#define MC_CMD_FILTER_OP_IN_HANDLE_HI_WIDTH 3211965/* The port ID associated with the v-adaptor which should contain this filter.11966 */11967#define MC_CMD_FILTER_OP_IN_PORT_ID_OFST 1211968#define MC_CMD_FILTER_OP_IN_PORT_ID_LEN 411969/* fields to include in match criteria */11970#define MC_CMD_FILTER_OP_IN_MATCH_FIELDS_OFST 1611971#define MC_CMD_FILTER_OP_IN_MATCH_FIELDS_LEN 411972#define MC_CMD_FILTER_OP_IN_MATCH_SRC_IP_OFST 1611973#define MC_CMD_FILTER_OP_IN_MATCH_SRC_IP_LBN 011974#define MC_CMD_FILTER_OP_IN_MATCH_SRC_IP_WIDTH 111975#define MC_CMD_FILTER_OP_IN_MATCH_DST_IP_OFST 1611976#define MC_CMD_FILTER_OP_IN_MATCH_DST_IP_LBN 111977#define MC_CMD_FILTER_OP_IN_MATCH_DST_IP_WIDTH 111978#define MC_CMD_FILTER_OP_IN_MATCH_SRC_MAC_OFST 1611979#define MC_CMD_FILTER_OP_IN_MATCH_SRC_MAC_LBN 211980#define MC_CMD_FILTER_OP_IN_MATCH_SRC_MAC_WIDTH 111981#define MC_CMD_FILTER_OP_IN_MATCH_SRC_PORT_OFST 1611982#define MC_CMD_FILTER_OP_IN_MATCH_SRC_PORT_LBN 311983#define MC_CMD_FILTER_OP_IN_MATCH_SRC_PORT_WIDTH 111984#define MC_CMD_FILTER_OP_IN_MATCH_DST_MAC_OFST 1611985#define MC_CMD_FILTER_OP_IN_MATCH_DST_MAC_LBN 411986#define MC_CMD_FILTER_OP_IN_MATCH_DST_MAC_WIDTH 111987#define MC_CMD_FILTER_OP_IN_MATCH_DST_PORT_OFST 1611988#define MC_CMD_FILTER_OP_IN_MATCH_DST_PORT_LBN 511989#define MC_CMD_FILTER_OP_IN_MATCH_DST_PORT_WIDTH 111990#define MC_CMD_FILTER_OP_IN_MATCH_ETHER_TYPE_OFST 1611991#define MC_CMD_FILTER_OP_IN_MATCH_ETHER_TYPE_LBN 611992#define MC_CMD_FILTER_OP_IN_MATCH_ETHER_TYPE_WIDTH 111993#define MC_CMD_FILTER_OP_IN_MATCH_INNER_VLAN_OFST 1611994#define MC_CMD_FILTER_OP_IN_MATCH_INNER_VLAN_LBN 711995#define MC_CMD_FILTER_OP_IN_MATCH_INNER_VLAN_WIDTH 111996#define MC_CMD_FILTER_OP_IN_MATCH_OUTER_VLAN_OFST 1611997#define MC_CMD_FILTER_OP_IN_MATCH_OUTER_VLAN_LBN 811998#define MC_CMD_FILTER_OP_IN_MATCH_OUTER_VLAN_WIDTH 111999#define MC_CMD_FILTER_OP_IN_MATCH_IP_PROTO_OFST 1612000#define MC_CMD_FILTER_OP_IN_MATCH_IP_PROTO_LBN 912001#define MC_CMD_FILTER_OP_IN_MATCH_IP_PROTO_WIDTH 112002#define MC_CMD_FILTER_OP_IN_MATCH_FWDEF0_OFST 1612003#define MC_CMD_FILTER_OP_IN_MATCH_FWDEF0_LBN 1012004#define MC_CMD_FILTER_OP_IN_MATCH_FWDEF0_WIDTH 112005#define MC_CMD_FILTER_OP_IN_MATCH_FWDEF1_OFST 1612006#define MC_CMD_FILTER_OP_IN_MATCH_FWDEF1_LBN 1112007#define MC_CMD_FILTER_OP_IN_MATCH_FWDEF1_WIDTH 112008#define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_IPV4_MCAST_DST_OFST 1612009#define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_IPV4_MCAST_DST_LBN 2912010#define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_IPV4_MCAST_DST_WIDTH 112011#define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_OFST 1612012#define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_LBN 3012013#define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_WIDTH 112014#define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_OFST 1612015#define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_LBN 3112016#define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_WIDTH 112017/* receive destination */12018#define MC_CMD_FILTER_OP_IN_RX_DEST_OFST 2012019#define MC_CMD_FILTER_OP_IN_RX_DEST_LEN 412020/* enum: drop packets */12021#define MC_CMD_FILTER_OP_IN_RX_DEST_DROP 0x012022/* enum: receive to host */12023#define MC_CMD_FILTER_OP_IN_RX_DEST_HOST 0x112024/* enum: receive to MC */12025#define MC_CMD_FILTER_OP_IN_RX_DEST_MC 0x212026/* enum: loop back to TXDP 0 */12027#define MC_CMD_FILTER_OP_IN_RX_DEST_TX0 0x312028/* enum: loop back to TXDP 1 */12029#define MC_CMD_FILTER_OP_IN_RX_DEST_TX1 0x412030/* receive queue handle (for multiple queue modes, this is the base queue) */12031#define MC_CMD_FILTER_OP_IN_RX_QUEUE_OFST 2412032#define MC_CMD_FILTER_OP_IN_RX_QUEUE_LEN 412033/* receive mode */12034#define MC_CMD_FILTER_OP_IN_RX_MODE_OFST 2812035#define MC_CMD_FILTER_OP_IN_RX_MODE_LEN 412036/* enum: receive to just the specified queue */12037#define MC_CMD_FILTER_OP_IN_RX_MODE_SIMPLE 0x012038/* enum: receive to multiple queues using RSS context */12039#define MC_CMD_FILTER_OP_IN_RX_MODE_RSS 0x112040/* enum: receive to multiple queues using .1p mapping */12041#define MC_CMD_FILTER_OP_IN_RX_MODE_DOT1P_MAPPING 0x212042/* enum: install a filter entry that will never match; for test purposes only12043 */12044#define MC_CMD_FILTER_OP_IN_RX_MODE_TEST_NEVER_MATCH 0x8000000012045/* RSS context (for RX_MODE_RSS) or .1p mapping handle (for12046 * RX_MODE_DOT1P_MAPPING), as returned by MC_CMD_RSS_CONTEXT_ALLOC or12047 * MC_CMD_DOT1P_MAPPING_ALLOC.12048 */12049#define MC_CMD_FILTER_OP_IN_RX_CONTEXT_OFST 3212050#define MC_CMD_FILTER_OP_IN_RX_CONTEXT_LEN 412051/* transmit domain (reserved; set to 0) */12052#define MC_CMD_FILTER_OP_IN_TX_DOMAIN_OFST 3612053#define MC_CMD_FILTER_OP_IN_TX_DOMAIN_LEN 412054/* transmit destination (either set the MAC and/or PM bits for explicit12055 * control, or set this field to TX_DEST_DEFAULT for sensible default12056 * behaviour)12057 */12058#define MC_CMD_FILTER_OP_IN_TX_DEST_OFST 4012059#define MC_CMD_FILTER_OP_IN_TX_DEST_LEN 412060/* enum: request default behaviour (based on filter type) */12061#define MC_CMD_FILTER_OP_IN_TX_DEST_DEFAULT 0xffffffff12062#define MC_CMD_FILTER_OP_IN_TX_DEST_MAC_OFST 4012063#define MC_CMD_FILTER_OP_IN_TX_DEST_MAC_LBN 012064#define MC_CMD_FILTER_OP_IN_TX_DEST_MAC_WIDTH 112065#define MC_CMD_FILTER_OP_IN_TX_DEST_PM_OFST 4012066#define MC_CMD_FILTER_OP_IN_TX_DEST_PM_LBN 112067#define MC_CMD_FILTER_OP_IN_TX_DEST_PM_WIDTH 112068/* source MAC address to match (as bytes in network order) */12069#define MC_CMD_FILTER_OP_IN_SRC_MAC_OFST 4412070#define MC_CMD_FILTER_OP_IN_SRC_MAC_LEN 612071/* source port to match (as bytes in network order) */12072#define MC_CMD_FILTER_OP_IN_SRC_PORT_OFST 5012073#define MC_CMD_FILTER_OP_IN_SRC_PORT_LEN 212074/* destination MAC address to match (as bytes in network order) */12075#define MC_CMD_FILTER_OP_IN_DST_MAC_OFST 5212076#define MC_CMD_FILTER_OP_IN_DST_MAC_LEN 612077/* destination port to match (as bytes in network order) */12078#define MC_CMD_FILTER_OP_IN_DST_PORT_OFST 5812079#define MC_CMD_FILTER_OP_IN_DST_PORT_LEN 212080/* Ethernet type to match (as bytes in network order) */12081#define MC_CMD_FILTER_OP_IN_ETHER_TYPE_OFST 6012082#define MC_CMD_FILTER_OP_IN_ETHER_TYPE_LEN 212083/* Inner VLAN tag to match (as bytes in network order) */12084#define MC_CMD_FILTER_OP_IN_INNER_VLAN_OFST 6212085#define MC_CMD_FILTER_OP_IN_INNER_VLAN_LEN 212086/* Outer VLAN tag to match (as bytes in network order) */12087#define MC_CMD_FILTER_OP_IN_OUTER_VLAN_OFST 6412088#define MC_CMD_FILTER_OP_IN_OUTER_VLAN_LEN 212089/* IP protocol to match (in low byte; set high byte to 0) */12090#define MC_CMD_FILTER_OP_IN_IP_PROTO_OFST 6612091#define MC_CMD_FILTER_OP_IN_IP_PROTO_LEN 212092/* Firmware defined register 0 to match (reserved; set to 0) */12093#define MC_CMD_FILTER_OP_IN_FWDEF0_OFST 6812094#define MC_CMD_FILTER_OP_IN_FWDEF0_LEN 412095/* Firmware defined register 1 to match (reserved; set to 0) */12096#define MC_CMD_FILTER_OP_IN_FWDEF1_OFST 7212097#define MC_CMD_FILTER_OP_IN_FWDEF1_LEN 412098/* source IP address to match (as bytes in network order; set last 12 bytes to12099 * 0 for IPv4 address)12100 */12101#define MC_CMD_FILTER_OP_IN_SRC_IP_OFST 7612102#define MC_CMD_FILTER_OP_IN_SRC_IP_LEN 1612103/* destination IP address to match (as bytes in network order; set last 1212104 * bytes to 0 for IPv4 address)12105 */12106#define MC_CMD_FILTER_OP_IN_DST_IP_OFST 9212107#define MC_CMD_FILTER_OP_IN_DST_IP_LEN 1612108 12109/* MC_CMD_FILTER_OP_EXT_IN msgrequest: Extension to MC_CMD_FILTER_OP_IN to12110 * include handling of VXLAN/NVGRE encapsulated frame filtering (which is12111 * supported on Medford only).12112 */12113#define MC_CMD_FILTER_OP_EXT_IN_LEN 17212114/* identifies the type of operation requested */12115#define MC_CMD_FILTER_OP_EXT_IN_OP_OFST 012116#define MC_CMD_FILTER_OP_EXT_IN_OP_LEN 412117/* Enum values, see field(s): */12118/* MC_CMD_FILTER_OP_IN/OP */12119/* filter handle (for remove / unsubscribe operations) */12120#define MC_CMD_FILTER_OP_EXT_IN_HANDLE_OFST 412121#define MC_CMD_FILTER_OP_EXT_IN_HANDLE_LEN 812122#define MC_CMD_FILTER_OP_EXT_IN_HANDLE_LO_OFST 412123#define MC_CMD_FILTER_OP_EXT_IN_HANDLE_LO_LEN 412124#define MC_CMD_FILTER_OP_EXT_IN_HANDLE_LO_LBN 3212125#define MC_CMD_FILTER_OP_EXT_IN_HANDLE_LO_WIDTH 3212126#define MC_CMD_FILTER_OP_EXT_IN_HANDLE_HI_OFST 812127#define MC_CMD_FILTER_OP_EXT_IN_HANDLE_HI_LEN 412128#define MC_CMD_FILTER_OP_EXT_IN_HANDLE_HI_LBN 6412129#define MC_CMD_FILTER_OP_EXT_IN_HANDLE_HI_WIDTH 3212130/* The port ID associated with the v-adaptor which should contain this filter.12131 */12132#define MC_CMD_FILTER_OP_EXT_IN_PORT_ID_OFST 1212133#define MC_CMD_FILTER_OP_EXT_IN_PORT_ID_LEN 412134/* fields to include in match criteria */12135#define MC_CMD_FILTER_OP_EXT_IN_MATCH_FIELDS_OFST 1612136#define MC_CMD_FILTER_OP_EXT_IN_MATCH_FIELDS_LEN 412137#define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_IP_OFST 1612138#define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_IP_LBN 012139#define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_IP_WIDTH 112140#define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_IP_OFST 1612141#define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_IP_LBN 112142#define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_IP_WIDTH 112143#define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_MAC_OFST 1612144#define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_MAC_LBN 212145#define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_MAC_WIDTH 112146#define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_PORT_OFST 1612147#define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_PORT_LBN 312148#define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_PORT_WIDTH 112149#define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_MAC_OFST 1612150#define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_MAC_LBN 412151#define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_MAC_WIDTH 112152#define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_PORT_OFST 1612153#define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_PORT_LBN 512154#define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_PORT_WIDTH 112155#define MC_CMD_FILTER_OP_EXT_IN_MATCH_ETHER_TYPE_OFST 1612156#define MC_CMD_FILTER_OP_EXT_IN_MATCH_ETHER_TYPE_LBN 612157#define MC_CMD_FILTER_OP_EXT_IN_MATCH_ETHER_TYPE_WIDTH 112158#define MC_CMD_FILTER_OP_EXT_IN_MATCH_INNER_VLAN_OFST 1612159#define MC_CMD_FILTER_OP_EXT_IN_MATCH_INNER_VLAN_LBN 712160#define MC_CMD_FILTER_OP_EXT_IN_MATCH_INNER_VLAN_WIDTH 112161#define MC_CMD_FILTER_OP_EXT_IN_MATCH_OUTER_VLAN_OFST 1612162#define MC_CMD_FILTER_OP_EXT_IN_MATCH_OUTER_VLAN_LBN 812163#define MC_CMD_FILTER_OP_EXT_IN_MATCH_OUTER_VLAN_WIDTH 112164#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IP_PROTO_OFST 1612165#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IP_PROTO_LBN 912166#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IP_PROTO_WIDTH 112167#define MC_CMD_FILTER_OP_EXT_IN_MATCH_FWDEF0_OFST 1612168#define MC_CMD_FILTER_OP_EXT_IN_MATCH_FWDEF0_LBN 1012169#define MC_CMD_FILTER_OP_EXT_IN_MATCH_FWDEF0_WIDTH 112170#define MC_CMD_FILTER_OP_EXT_IN_MATCH_VNI_OR_VSID_OFST 1612171#define MC_CMD_FILTER_OP_EXT_IN_MATCH_VNI_OR_VSID_LBN 1112172#define MC_CMD_FILTER_OP_EXT_IN_MATCH_VNI_OR_VSID_WIDTH 112173#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_IP_OFST 1612174#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_IP_LBN 1212175#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_IP_WIDTH 112176#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_IP_OFST 1612177#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_IP_LBN 1312178#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_IP_WIDTH 112179#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_MAC_OFST 1612180#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_MAC_LBN 1412181#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_MAC_WIDTH 112182#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_PORT_OFST 1612183#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_PORT_LBN 1512184#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_PORT_WIDTH 112185#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_MAC_OFST 1612186#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_MAC_LBN 1612187#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_MAC_WIDTH 112188#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_PORT_OFST 1612189#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_PORT_LBN 1712190#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_PORT_WIDTH 112191#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_ETHER_TYPE_OFST 1612192#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_ETHER_TYPE_LBN 1812193#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_ETHER_TYPE_WIDTH 112194#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_INNER_VLAN_OFST 1612195#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_INNER_VLAN_LBN 1912196#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_INNER_VLAN_WIDTH 112197#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_OUTER_VLAN_OFST 1612198#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_OUTER_VLAN_LBN 2012199#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_OUTER_VLAN_WIDTH 112200#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_IP_PROTO_OFST 1612201#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_IP_PROTO_LBN 2112202#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_IP_PROTO_WIDTH 112203#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF0_OFST 1612204#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF0_LBN 2212205#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF0_WIDTH 112206#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF1_OFST 1612207#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF1_LBN 2312208#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF1_WIDTH 112209#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_OFST 1612210#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_LBN 2412211#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_WIDTH 112212#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_OFST 1612213#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_LBN 2512214#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_WIDTH 112215#define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_IPV4_MCAST_DST_OFST 1612216#define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_IPV4_MCAST_DST_LBN 2912217#define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_IPV4_MCAST_DST_WIDTH 112218#define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_MCAST_DST_OFST 1612219#define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_MCAST_DST_LBN 3012220#define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_MCAST_DST_WIDTH 112221#define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_UCAST_DST_OFST 1612222#define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_UCAST_DST_LBN 3112223#define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_UCAST_DST_WIDTH 112224/* receive destination */12225#define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_OFST 2012226#define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_LEN 412227/* enum: drop packets */12228#define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_DROP 0x012229/* enum: receive to host */12230#define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_HOST 0x112231/* enum: receive to MC */12232#define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_MC 0x212233/* enum: loop back to TXDP 0 */12234#define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_TX0 0x312235/* enum: loop back to TXDP 1 */12236#define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_TX1 0x412237/* receive queue handle (for multiple queue modes, this is the base queue) */12238#define MC_CMD_FILTER_OP_EXT_IN_RX_QUEUE_OFST 2412239#define MC_CMD_FILTER_OP_EXT_IN_RX_QUEUE_LEN 412240/* receive mode */12241#define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_OFST 2812242#define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_LEN 412243/* enum: receive to just the specified queue */12244#define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_SIMPLE 0x012245/* enum: receive to multiple queues using RSS context */12246#define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_RSS 0x112247/* enum: receive to multiple queues using .1p mapping */12248#define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_DOT1P_MAPPING 0x212249/* enum: install a filter entry that will never match; for test purposes only12250 */12251#define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_TEST_NEVER_MATCH 0x8000000012252/* RSS context (for RX_MODE_RSS) or .1p mapping handle (for12253 * RX_MODE_DOT1P_MAPPING), as returned by MC_CMD_RSS_CONTEXT_ALLOC or12254 * MC_CMD_DOT1P_MAPPING_ALLOC.12255 */12256#define MC_CMD_FILTER_OP_EXT_IN_RX_CONTEXT_OFST 3212257#define MC_CMD_FILTER_OP_EXT_IN_RX_CONTEXT_LEN 412258/* transmit domain (reserved; set to 0) */12259#define MC_CMD_FILTER_OP_EXT_IN_TX_DOMAIN_OFST 3612260#define MC_CMD_FILTER_OP_EXT_IN_TX_DOMAIN_LEN 412261/* transmit destination (either set the MAC and/or PM bits for explicit12262 * control, or set this field to TX_DEST_DEFAULT for sensible default12263 * behaviour)12264 */12265#define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_OFST 4012266#define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_LEN 412267/* enum: request default behaviour (based on filter type) */12268#define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_DEFAULT 0xffffffff12269#define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_MAC_OFST 4012270#define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_MAC_LBN 012271#define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_MAC_WIDTH 112272#define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_PM_OFST 4012273#define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_PM_LBN 112274#define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_PM_WIDTH 112275/* source MAC address to match (as bytes in network order) */12276#define MC_CMD_FILTER_OP_EXT_IN_SRC_MAC_OFST 4412277#define MC_CMD_FILTER_OP_EXT_IN_SRC_MAC_LEN 612278/* source port to match (as bytes in network order) */12279#define MC_CMD_FILTER_OP_EXT_IN_SRC_PORT_OFST 5012280#define MC_CMD_FILTER_OP_EXT_IN_SRC_PORT_LEN 212281/* destination MAC address to match (as bytes in network order) */12282#define MC_CMD_FILTER_OP_EXT_IN_DST_MAC_OFST 5212283#define MC_CMD_FILTER_OP_EXT_IN_DST_MAC_LEN 612284/* destination port to match (as bytes in network order) */12285#define MC_CMD_FILTER_OP_EXT_IN_DST_PORT_OFST 5812286#define MC_CMD_FILTER_OP_EXT_IN_DST_PORT_LEN 212287/* Ethernet type to match (as bytes in network order) */12288#define MC_CMD_FILTER_OP_EXT_IN_ETHER_TYPE_OFST 6012289#define MC_CMD_FILTER_OP_EXT_IN_ETHER_TYPE_LEN 212290/* Inner VLAN tag to match (as bytes in network order) */12291#define MC_CMD_FILTER_OP_EXT_IN_INNER_VLAN_OFST 6212292#define MC_CMD_FILTER_OP_EXT_IN_INNER_VLAN_LEN 212293/* Outer VLAN tag to match (as bytes in network order) */12294#define MC_CMD_FILTER_OP_EXT_IN_OUTER_VLAN_OFST 6412295#define MC_CMD_FILTER_OP_EXT_IN_OUTER_VLAN_LEN 212296/* IP protocol to match (in low byte; set high byte to 0) */12297#define MC_CMD_FILTER_OP_EXT_IN_IP_PROTO_OFST 6612298#define MC_CMD_FILTER_OP_EXT_IN_IP_PROTO_LEN 212299/* Firmware defined register 0 to match (reserved; set to 0) */12300#define MC_CMD_FILTER_OP_EXT_IN_FWDEF0_OFST 6812301#define MC_CMD_FILTER_OP_EXT_IN_FWDEF0_LEN 412302/* VNI (for VXLAN/Geneve, when IP protocol is UDP) or VSID (for NVGRE, when IP12303 * protocol is GRE) to match (as bytes in network order; set last byte to 0 for12304 * VXLAN/NVGRE, or 1 for Geneve)12305 */12306#define MC_CMD_FILTER_OP_EXT_IN_VNI_OR_VSID_OFST 7212307#define MC_CMD_FILTER_OP_EXT_IN_VNI_OR_VSID_LEN 412308#define MC_CMD_FILTER_OP_EXT_IN_VNI_VALUE_OFST 7212309#define MC_CMD_FILTER_OP_EXT_IN_VNI_VALUE_LBN 012310#define MC_CMD_FILTER_OP_EXT_IN_VNI_VALUE_WIDTH 2412311#define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_OFST 7212312#define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_LBN 2412313#define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_WIDTH 812314/* enum: Match VXLAN traffic with this VNI */12315#define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_VXLAN 0x012316/* enum: Match Geneve traffic with this VNI */12317#define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_GENEVE 0x112318/* enum: Reserved for experimental development use */12319#define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_EXPERIMENTAL 0xfe12320#define MC_CMD_FILTER_OP_EXT_IN_VSID_VALUE_OFST 7212321#define MC_CMD_FILTER_OP_EXT_IN_VSID_VALUE_LBN 012322#define MC_CMD_FILTER_OP_EXT_IN_VSID_VALUE_WIDTH 2412323#define MC_CMD_FILTER_OP_EXT_IN_VSID_TYPE_OFST 7212324#define MC_CMD_FILTER_OP_EXT_IN_VSID_TYPE_LBN 2412325#define MC_CMD_FILTER_OP_EXT_IN_VSID_TYPE_WIDTH 812326/* enum: Match NVGRE traffic with this VSID */12327#define MC_CMD_FILTER_OP_EXT_IN_VSID_TYPE_NVGRE 0x012328/* source IP address to match (as bytes in network order; set last 12 bytes to12329 * 0 for IPv4 address)12330 */12331#define MC_CMD_FILTER_OP_EXT_IN_SRC_IP_OFST 7612332#define MC_CMD_FILTER_OP_EXT_IN_SRC_IP_LEN 1612333/* destination IP address to match (as bytes in network order; set last 1212334 * bytes to 0 for IPv4 address)12335 */12336#define MC_CMD_FILTER_OP_EXT_IN_DST_IP_OFST 9212337#define MC_CMD_FILTER_OP_EXT_IN_DST_IP_LEN 1612338/* VXLAN/NVGRE inner frame source MAC address to match (as bytes in network12339 * order)12340 */12341#define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_MAC_OFST 10812342#define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_MAC_LEN 612343/* VXLAN/NVGRE inner frame source port to match (as bytes in network order) */12344#define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_PORT_OFST 11412345#define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_PORT_LEN 212346/* VXLAN/NVGRE inner frame destination MAC address to match (as bytes in12347 * network order)12348 */12349#define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_MAC_OFST 11612350#define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_MAC_LEN 612351/* VXLAN/NVGRE inner frame destination port to match (as bytes in network12352 * order)12353 */12354#define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_PORT_OFST 12212355#define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_PORT_LEN 212356/* VXLAN/NVGRE inner frame Ethernet type to match (as bytes in network order)12357 */12358#define MC_CMD_FILTER_OP_EXT_IN_IFRM_ETHER_TYPE_OFST 12412359#define MC_CMD_FILTER_OP_EXT_IN_IFRM_ETHER_TYPE_LEN 212360/* VXLAN/NVGRE inner frame Inner VLAN tag to match (as bytes in network order)12361 */12362#define MC_CMD_FILTER_OP_EXT_IN_IFRM_INNER_VLAN_OFST 12612363#define MC_CMD_FILTER_OP_EXT_IN_IFRM_INNER_VLAN_LEN 212364/* VXLAN/NVGRE inner frame Outer VLAN tag to match (as bytes in network order)12365 */12366#define MC_CMD_FILTER_OP_EXT_IN_IFRM_OUTER_VLAN_OFST 12812367#define MC_CMD_FILTER_OP_EXT_IN_IFRM_OUTER_VLAN_LEN 212368/* VXLAN/NVGRE inner frame IP protocol to match (in low byte; set high byte to12369 * 0)12370 */12371#define MC_CMD_FILTER_OP_EXT_IN_IFRM_IP_PROTO_OFST 13012372#define MC_CMD_FILTER_OP_EXT_IN_IFRM_IP_PROTO_LEN 212373/* VXLAN/NVGRE inner frame Firmware defined register 0 to match (reserved; set12374 * to 0)12375 */12376#define MC_CMD_FILTER_OP_EXT_IN_IFRM_FWDEF0_OFST 13212377#define MC_CMD_FILTER_OP_EXT_IN_IFRM_FWDEF0_LEN 412378/* VXLAN/NVGRE inner frame Firmware defined register 1 to match (reserved; set12379 * to 0)12380 */12381#define MC_CMD_FILTER_OP_EXT_IN_IFRM_FWDEF1_OFST 13612382#define MC_CMD_FILTER_OP_EXT_IN_IFRM_FWDEF1_LEN 412383/* VXLAN/NVGRE inner frame source IP address to match (as bytes in network12384 * order; set last 12 bytes to 0 for IPv4 address)12385 */12386#define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_IP_OFST 14012387#define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_IP_LEN 1612388/* VXLAN/NVGRE inner frame destination IP address to match (as bytes in network12389 * order; set last 12 bytes to 0 for IPv4 address)12390 */12391#define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_IP_OFST 15612392#define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_IP_LEN 1612393 12394/* MC_CMD_FILTER_OP_V3_IN msgrequest: FILTER_OP extension to support additional12395 * filter actions for EF100. Some of these actions are also supported on EF10,12396 * for Intel's DPDK (Data Plane Development Kit, dpdk.org) via its rte_flow12397 * API. In the latter case, this extension is only useful with the sfc_efx12398 * driver included as part of DPDK, used in conjunction with the dpdk datapath12399 * firmware variant.12400 */12401#define MC_CMD_FILTER_OP_V3_IN_LEN 18012402/* identifies the type of operation requested */12403#define MC_CMD_FILTER_OP_V3_IN_OP_OFST 012404#define MC_CMD_FILTER_OP_V3_IN_OP_LEN 412405/* Enum values, see field(s): */12406/* MC_CMD_FILTER_OP_IN/OP */12407/* filter handle (for remove / unsubscribe operations) */12408#define MC_CMD_FILTER_OP_V3_IN_HANDLE_OFST 412409#define MC_CMD_FILTER_OP_V3_IN_HANDLE_LEN 812410#define MC_CMD_FILTER_OP_V3_IN_HANDLE_LO_OFST 412411#define MC_CMD_FILTER_OP_V3_IN_HANDLE_LO_LEN 412412#define MC_CMD_FILTER_OP_V3_IN_HANDLE_LO_LBN 3212413#define MC_CMD_FILTER_OP_V3_IN_HANDLE_LO_WIDTH 3212414#define MC_CMD_FILTER_OP_V3_IN_HANDLE_HI_OFST 812415#define MC_CMD_FILTER_OP_V3_IN_HANDLE_HI_LEN 412416#define MC_CMD_FILTER_OP_V3_IN_HANDLE_HI_LBN 6412417#define MC_CMD_FILTER_OP_V3_IN_HANDLE_HI_WIDTH 3212418/* The port ID associated with the v-adaptor which should contain this filter.12419 */12420#define MC_CMD_FILTER_OP_V3_IN_PORT_ID_OFST 1212421#define MC_CMD_FILTER_OP_V3_IN_PORT_ID_LEN 412422/* fields to include in match criteria */12423#define MC_CMD_FILTER_OP_V3_IN_MATCH_FIELDS_OFST 1612424#define MC_CMD_FILTER_OP_V3_IN_MATCH_FIELDS_LEN 412425#define MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_IP_OFST 1612426#define MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_IP_LBN 012427#define MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_IP_WIDTH 112428#define MC_CMD_FILTER_OP_V3_IN_MATCH_DST_IP_OFST 1612429#define MC_CMD_FILTER_OP_V3_IN_MATCH_DST_IP_LBN 112430#define MC_CMD_FILTER_OP_V3_IN_MATCH_DST_IP_WIDTH 112431#define MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_MAC_OFST 1612432#define MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_MAC_LBN 212433#define MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_MAC_WIDTH 112434#define MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_PORT_OFST 1612435#define MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_PORT_LBN 312436#define MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_PORT_WIDTH 112437#define MC_CMD_FILTER_OP_V3_IN_MATCH_DST_MAC_OFST 1612438#define MC_CMD_FILTER_OP_V3_IN_MATCH_DST_MAC_LBN 412439#define MC_CMD_FILTER_OP_V3_IN_MATCH_DST_MAC_WIDTH 112440#define MC_CMD_FILTER_OP_V3_IN_MATCH_DST_PORT_OFST 1612441#define MC_CMD_FILTER_OP_V3_IN_MATCH_DST_PORT_LBN 512442#define MC_CMD_FILTER_OP_V3_IN_MATCH_DST_PORT_WIDTH 112443#define MC_CMD_FILTER_OP_V3_IN_MATCH_ETHER_TYPE_OFST 1612444#define MC_CMD_FILTER_OP_V3_IN_MATCH_ETHER_TYPE_LBN 612445#define MC_CMD_FILTER_OP_V3_IN_MATCH_ETHER_TYPE_WIDTH 112446#define MC_CMD_FILTER_OP_V3_IN_MATCH_INNER_VLAN_OFST 1612447#define MC_CMD_FILTER_OP_V3_IN_MATCH_INNER_VLAN_LBN 712448#define MC_CMD_FILTER_OP_V3_IN_MATCH_INNER_VLAN_WIDTH 112449#define MC_CMD_FILTER_OP_V3_IN_MATCH_OUTER_VLAN_OFST 1612450#define MC_CMD_FILTER_OP_V3_IN_MATCH_OUTER_VLAN_LBN 812451#define MC_CMD_FILTER_OP_V3_IN_MATCH_OUTER_VLAN_WIDTH 112452#define MC_CMD_FILTER_OP_V3_IN_MATCH_IP_PROTO_OFST 1612453#define MC_CMD_FILTER_OP_V3_IN_MATCH_IP_PROTO_LBN 912454#define MC_CMD_FILTER_OP_V3_IN_MATCH_IP_PROTO_WIDTH 112455#define MC_CMD_FILTER_OP_V3_IN_MATCH_FWDEF0_OFST 1612456#define MC_CMD_FILTER_OP_V3_IN_MATCH_FWDEF0_LBN 1012457#define MC_CMD_FILTER_OP_V3_IN_MATCH_FWDEF0_WIDTH 112458#define MC_CMD_FILTER_OP_V3_IN_MATCH_VNI_OR_VSID_OFST 1612459#define MC_CMD_FILTER_OP_V3_IN_MATCH_VNI_OR_VSID_LBN 1112460#define MC_CMD_FILTER_OP_V3_IN_MATCH_VNI_OR_VSID_WIDTH 112461#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_IP_OFST 1612462#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_IP_LBN 1212463#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_IP_WIDTH 112464#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_IP_OFST 1612465#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_IP_LBN 1312466#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_IP_WIDTH 112467#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_MAC_OFST 1612468#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_MAC_LBN 1412469#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_MAC_WIDTH 112470#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_PORT_OFST 1612471#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_PORT_LBN 1512472#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_PORT_WIDTH 112473#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_MAC_OFST 1612474#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_MAC_LBN 1612475#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_MAC_WIDTH 112476#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_PORT_OFST 1612477#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_PORT_LBN 1712478#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_PORT_WIDTH 112479#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_ETHER_TYPE_OFST 1612480#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_ETHER_TYPE_LBN 1812481#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_ETHER_TYPE_WIDTH 112482#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_INNER_VLAN_OFST 1612483#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_INNER_VLAN_LBN 1912484#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_INNER_VLAN_WIDTH 112485#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_OUTER_VLAN_OFST 1612486#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_OUTER_VLAN_LBN 2012487#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_OUTER_VLAN_WIDTH 112488#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_IP_PROTO_OFST 1612489#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_IP_PROTO_LBN 2112490#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_IP_PROTO_WIDTH 112491#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_FWDEF0_OFST 1612492#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_FWDEF0_LBN 2212493#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_FWDEF0_WIDTH 112494#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_FWDEF1_OFST 1612495#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_FWDEF1_LBN 2312496#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_FWDEF1_WIDTH 112497#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_OFST 1612498#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_LBN 2412499#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_WIDTH 112500#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_OFST 1612501#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_LBN 2512502#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_WIDTH 112503#define MC_CMD_FILTER_OP_V3_IN_MATCH_UNKNOWN_IPV4_MCAST_DST_OFST 1612504#define MC_CMD_FILTER_OP_V3_IN_MATCH_UNKNOWN_IPV4_MCAST_DST_LBN 2912505#define MC_CMD_FILTER_OP_V3_IN_MATCH_UNKNOWN_IPV4_MCAST_DST_WIDTH 112506#define MC_CMD_FILTER_OP_V3_IN_MATCH_UNKNOWN_MCAST_DST_OFST 1612507#define MC_CMD_FILTER_OP_V3_IN_MATCH_UNKNOWN_MCAST_DST_LBN 3012508#define MC_CMD_FILTER_OP_V3_IN_MATCH_UNKNOWN_MCAST_DST_WIDTH 112509#define MC_CMD_FILTER_OP_V3_IN_MATCH_UNKNOWN_UCAST_DST_OFST 1612510#define MC_CMD_FILTER_OP_V3_IN_MATCH_UNKNOWN_UCAST_DST_LBN 3112511#define MC_CMD_FILTER_OP_V3_IN_MATCH_UNKNOWN_UCAST_DST_WIDTH 112512/* receive destination */12513#define MC_CMD_FILTER_OP_V3_IN_RX_DEST_OFST 2012514#define MC_CMD_FILTER_OP_V3_IN_RX_DEST_LEN 412515/* enum: drop packets */12516#define MC_CMD_FILTER_OP_V3_IN_RX_DEST_DROP 0x012517/* enum: receive to host */12518#define MC_CMD_FILTER_OP_V3_IN_RX_DEST_HOST 0x112519/* enum: receive to MC */12520#define MC_CMD_FILTER_OP_V3_IN_RX_DEST_MC 0x212521/* enum: loop back to TXDP 0 */12522#define MC_CMD_FILTER_OP_V3_IN_RX_DEST_TX0 0x312523/* enum: loop back to TXDP 1 */12524#define MC_CMD_FILTER_OP_V3_IN_RX_DEST_TX1 0x412525/* receive queue handle (for multiple queue modes, this is the base queue) */12526#define MC_CMD_FILTER_OP_V3_IN_RX_QUEUE_OFST 2412527#define MC_CMD_FILTER_OP_V3_IN_RX_QUEUE_LEN 412528/* receive mode */12529#define MC_CMD_FILTER_OP_V3_IN_RX_MODE_OFST 2812530#define MC_CMD_FILTER_OP_V3_IN_RX_MODE_LEN 412531/* enum: receive to just the specified queue */12532#define MC_CMD_FILTER_OP_V3_IN_RX_MODE_SIMPLE 0x012533/* enum: receive to multiple queues using RSS context */12534#define MC_CMD_FILTER_OP_V3_IN_RX_MODE_RSS 0x112535/* enum: receive to multiple queues using .1p mapping */12536#define MC_CMD_FILTER_OP_V3_IN_RX_MODE_DOT1P_MAPPING 0x212537/* enum: install a filter entry that will never match; for test purposes only12538 */12539#define MC_CMD_FILTER_OP_V3_IN_RX_MODE_TEST_NEVER_MATCH 0x8000000012540/* RSS context (for RX_MODE_RSS) or .1p mapping handle (for12541 * RX_MODE_DOT1P_MAPPING), as returned by MC_CMD_RSS_CONTEXT_ALLOC or12542 * MC_CMD_DOT1P_MAPPING_ALLOC.12543 */12544#define MC_CMD_FILTER_OP_V3_IN_RX_CONTEXT_OFST 3212545#define MC_CMD_FILTER_OP_V3_IN_RX_CONTEXT_LEN 412546/* transmit domain (reserved; set to 0) */12547#define MC_CMD_FILTER_OP_V3_IN_TX_DOMAIN_OFST 3612548#define MC_CMD_FILTER_OP_V3_IN_TX_DOMAIN_LEN 412549/* transmit destination (either set the MAC and/or PM bits for explicit12550 * control, or set this field to TX_DEST_DEFAULT for sensible default12551 * behaviour)12552 */12553#define MC_CMD_FILTER_OP_V3_IN_TX_DEST_OFST 4012554#define MC_CMD_FILTER_OP_V3_IN_TX_DEST_LEN 412555/* enum: request default behaviour (based on filter type) */12556#define MC_CMD_FILTER_OP_V3_IN_TX_DEST_DEFAULT 0xffffffff12557#define MC_CMD_FILTER_OP_V3_IN_TX_DEST_MAC_OFST 4012558#define MC_CMD_FILTER_OP_V3_IN_TX_DEST_MAC_LBN 012559#define MC_CMD_FILTER_OP_V3_IN_TX_DEST_MAC_WIDTH 112560#define MC_CMD_FILTER_OP_V3_IN_TX_DEST_PM_OFST 4012561#define MC_CMD_FILTER_OP_V3_IN_TX_DEST_PM_LBN 112562#define MC_CMD_FILTER_OP_V3_IN_TX_DEST_PM_WIDTH 112563/* source MAC address to match (as bytes in network order) */12564#define MC_CMD_FILTER_OP_V3_IN_SRC_MAC_OFST 4412565#define MC_CMD_FILTER_OP_V3_IN_SRC_MAC_LEN 612566/* source port to match (as bytes in network order) */12567#define MC_CMD_FILTER_OP_V3_IN_SRC_PORT_OFST 5012568#define MC_CMD_FILTER_OP_V3_IN_SRC_PORT_LEN 212569/* destination MAC address to match (as bytes in network order) */12570#define MC_CMD_FILTER_OP_V3_IN_DST_MAC_OFST 5212571#define MC_CMD_FILTER_OP_V3_IN_DST_MAC_LEN 612572/* destination port to match (as bytes in network order) */12573#define MC_CMD_FILTER_OP_V3_IN_DST_PORT_OFST 5812574#define MC_CMD_FILTER_OP_V3_IN_DST_PORT_LEN 212575/* Ethernet type to match (as bytes in network order) */12576#define MC_CMD_FILTER_OP_V3_IN_ETHER_TYPE_OFST 6012577#define MC_CMD_FILTER_OP_V3_IN_ETHER_TYPE_LEN 212578/* Inner VLAN tag to match (as bytes in network order) */12579#define MC_CMD_FILTER_OP_V3_IN_INNER_VLAN_OFST 6212580#define MC_CMD_FILTER_OP_V3_IN_INNER_VLAN_LEN 212581/* Outer VLAN tag to match (as bytes in network order) */12582#define MC_CMD_FILTER_OP_V3_IN_OUTER_VLAN_OFST 6412583#define MC_CMD_FILTER_OP_V3_IN_OUTER_VLAN_LEN 212584/* IP protocol to match (in low byte; set high byte to 0) */12585#define MC_CMD_FILTER_OP_V3_IN_IP_PROTO_OFST 6612586#define MC_CMD_FILTER_OP_V3_IN_IP_PROTO_LEN 212587/* Firmware defined register 0 to match (reserved; set to 0) */12588#define MC_CMD_FILTER_OP_V3_IN_FWDEF0_OFST 6812589#define MC_CMD_FILTER_OP_V3_IN_FWDEF0_LEN 412590/* VNI (for VXLAN/Geneve, when IP protocol is UDP) or VSID (for NVGRE, when IP12591 * protocol is GRE) to match (as bytes in network order; set last byte to 0 for12592 * VXLAN/NVGRE, or 1 for Geneve)12593 */12594#define MC_CMD_FILTER_OP_V3_IN_VNI_OR_VSID_OFST 7212595#define MC_CMD_FILTER_OP_V3_IN_VNI_OR_VSID_LEN 412596#define MC_CMD_FILTER_OP_V3_IN_VNI_VALUE_OFST 7212597#define MC_CMD_FILTER_OP_V3_IN_VNI_VALUE_LBN 012598#define MC_CMD_FILTER_OP_V3_IN_VNI_VALUE_WIDTH 2412599#define MC_CMD_FILTER_OP_V3_IN_VNI_TYPE_OFST 7212600#define MC_CMD_FILTER_OP_V3_IN_VNI_TYPE_LBN 2412601#define MC_CMD_FILTER_OP_V3_IN_VNI_TYPE_WIDTH 812602/* enum: Match VXLAN traffic with this VNI */12603#define MC_CMD_FILTER_OP_V3_IN_VNI_TYPE_VXLAN 0x012604/* enum: Match Geneve traffic with this VNI */12605#define MC_CMD_FILTER_OP_V3_IN_VNI_TYPE_GENEVE 0x112606/* enum: Reserved for experimental development use */12607#define MC_CMD_FILTER_OP_V3_IN_VNI_TYPE_EXPERIMENTAL 0xfe12608#define MC_CMD_FILTER_OP_V3_IN_VSID_VALUE_OFST 7212609#define MC_CMD_FILTER_OP_V3_IN_VSID_VALUE_LBN 012610#define MC_CMD_FILTER_OP_V3_IN_VSID_VALUE_WIDTH 2412611#define MC_CMD_FILTER_OP_V3_IN_VSID_TYPE_OFST 7212612#define MC_CMD_FILTER_OP_V3_IN_VSID_TYPE_LBN 2412613#define MC_CMD_FILTER_OP_V3_IN_VSID_TYPE_WIDTH 812614/* enum: Match NVGRE traffic with this VSID */12615#define MC_CMD_FILTER_OP_V3_IN_VSID_TYPE_NVGRE 0x012616/* source IP address to match (as bytes in network order; set last 12 bytes to12617 * 0 for IPv4 address)12618 */12619#define MC_CMD_FILTER_OP_V3_IN_SRC_IP_OFST 7612620#define MC_CMD_FILTER_OP_V3_IN_SRC_IP_LEN 1612621/* destination IP address to match (as bytes in network order; set last 1212622 * bytes to 0 for IPv4 address)12623 */12624#define MC_CMD_FILTER_OP_V3_IN_DST_IP_OFST 9212625#define MC_CMD_FILTER_OP_V3_IN_DST_IP_LEN 1612626/* VXLAN/NVGRE inner frame source MAC address to match (as bytes in network12627 * order)12628 */12629#define MC_CMD_FILTER_OP_V3_IN_IFRM_SRC_MAC_OFST 10812630#define MC_CMD_FILTER_OP_V3_IN_IFRM_SRC_MAC_LEN 612631/* VXLAN/NVGRE inner frame source port to match (as bytes in network order) */12632#define MC_CMD_FILTER_OP_V3_IN_IFRM_SRC_PORT_OFST 11412633#define MC_CMD_FILTER_OP_V3_IN_IFRM_SRC_PORT_LEN 212634/* VXLAN/NVGRE inner frame destination MAC address to match (as bytes in12635 * network order)12636 */12637#define MC_CMD_FILTER_OP_V3_IN_IFRM_DST_MAC_OFST 11612638#define MC_CMD_FILTER_OP_V3_IN_IFRM_DST_MAC_LEN 612639/* VXLAN/NVGRE inner frame destination port to match (as bytes in network12640 * order)12641 */12642#define MC_CMD_FILTER_OP_V3_IN_IFRM_DST_PORT_OFST 12212643#define MC_CMD_FILTER_OP_V3_IN_IFRM_DST_PORT_LEN 212644/* VXLAN/NVGRE inner frame Ethernet type to match (as bytes in network order)12645 */12646#define MC_CMD_FILTER_OP_V3_IN_IFRM_ETHER_TYPE_OFST 12412647#define MC_CMD_FILTER_OP_V3_IN_IFRM_ETHER_TYPE_LEN 212648/* VXLAN/NVGRE inner frame Inner VLAN tag to match (as bytes in network order)12649 */12650#define MC_CMD_FILTER_OP_V3_IN_IFRM_INNER_VLAN_OFST 12612651#define MC_CMD_FILTER_OP_V3_IN_IFRM_INNER_VLAN_LEN 212652/* VXLAN/NVGRE inner frame Outer VLAN tag to match (as bytes in network order)12653 */12654#define MC_CMD_FILTER_OP_V3_IN_IFRM_OUTER_VLAN_OFST 12812655#define MC_CMD_FILTER_OP_V3_IN_IFRM_OUTER_VLAN_LEN 212656/* VXLAN/NVGRE inner frame IP protocol to match (in low byte; set high byte to12657 * 0)12658 */12659#define MC_CMD_FILTER_OP_V3_IN_IFRM_IP_PROTO_OFST 13012660#define MC_CMD_FILTER_OP_V3_IN_IFRM_IP_PROTO_LEN 212661/* VXLAN/NVGRE inner frame Firmware defined register 0 to match (reserved; set12662 * to 0)12663 */12664#define MC_CMD_FILTER_OP_V3_IN_IFRM_FWDEF0_OFST 13212665#define MC_CMD_FILTER_OP_V3_IN_IFRM_FWDEF0_LEN 412666/* VXLAN/NVGRE inner frame Firmware defined register 1 to match (reserved; set12667 * to 0)12668 */12669#define MC_CMD_FILTER_OP_V3_IN_IFRM_FWDEF1_OFST 13612670#define MC_CMD_FILTER_OP_V3_IN_IFRM_FWDEF1_LEN 412671/* VXLAN/NVGRE inner frame source IP address to match (as bytes in network12672 * order; set last 12 bytes to 0 for IPv4 address)12673 */12674#define MC_CMD_FILTER_OP_V3_IN_IFRM_SRC_IP_OFST 14012675#define MC_CMD_FILTER_OP_V3_IN_IFRM_SRC_IP_LEN 1612676/* VXLAN/NVGRE inner frame destination IP address to match (as bytes in network12677 * order; set last 12 bytes to 0 for IPv4 address)12678 */12679#define MC_CMD_FILTER_OP_V3_IN_IFRM_DST_IP_OFST 15612680#define MC_CMD_FILTER_OP_V3_IN_IFRM_DST_IP_LEN 1612681/* Flags controlling mutations of the packet and/or metadata when the filter is12682 * matched. The user_mark and user_flag fields' logic is as follows: if12683 * (req.MATCH_BITOR_FLAG == 1) user_flag = req.MATCH_SET_FLAG bit_or user_flag;12684 * else user_flag = req.MATCH_SET_FLAG; if (req.MATCH_SET_MARK == 0) user_mark12685 * = 0; else if (req.MATCH_BITOR_MARK == 1) user_mark = req.MATCH_SET_MARK12686 * bit_or user_mark; else user_mark = req.MATCH_SET_MARK; N.B. These flags12687 * overlap with the MATCH_ACTION field, which is deprecated in favour of this12688 * field. For the cases where these flags induce a valid encoding of the12689 * MATCH_ACTION field, the semantics agree.12690 */12691#define MC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_FLAGS_OFST 17212692#define MC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_FLAGS_LEN 412693#define MC_CMD_FILTER_OP_V3_IN_MATCH_SET_FLAG_OFST 17212694#define MC_CMD_FILTER_OP_V3_IN_MATCH_SET_FLAG_LBN 012695#define MC_CMD_FILTER_OP_V3_IN_MATCH_SET_FLAG_WIDTH 112696#define MC_CMD_FILTER_OP_V3_IN_MATCH_SET_MARK_OFST 17212697#define MC_CMD_FILTER_OP_V3_IN_MATCH_SET_MARK_LBN 112698#define MC_CMD_FILTER_OP_V3_IN_MATCH_SET_MARK_WIDTH 112699#define MC_CMD_FILTER_OP_V3_IN_MATCH_BITOR_FLAG_OFST 17212700#define MC_CMD_FILTER_OP_V3_IN_MATCH_BITOR_FLAG_LBN 212701#define MC_CMD_FILTER_OP_V3_IN_MATCH_BITOR_FLAG_WIDTH 112702#define MC_CMD_FILTER_OP_V3_IN_MATCH_BITOR_MARK_OFST 17212703#define MC_CMD_FILTER_OP_V3_IN_MATCH_BITOR_MARK_LBN 312704#define MC_CMD_FILTER_OP_V3_IN_MATCH_BITOR_MARK_WIDTH 112705#define MC_CMD_FILTER_OP_V3_IN_MATCH_STRIP_VLAN_OFST 17212706#define MC_CMD_FILTER_OP_V3_IN_MATCH_STRIP_VLAN_LBN 412707#define MC_CMD_FILTER_OP_V3_IN_MATCH_STRIP_VLAN_WIDTH 112708/* Deprecated: the overlapping MATCH_ACTION_FLAGS field exposes all of the12709 * functionality of this field in an ABI-backwards-compatible manner, and12710 * should be used instead. Any future extensions should be made to the12711 * MATCH_ACTION_FLAGS field, and not to this field. Set an action for all12712 * packets matching this filter. The DPDK driver and (on EF10) dpdk f/w variant12713 * use their own specific delivery structures, which are documented in the DPDK12714 * Firmware Driver Interface (SF-119419-TC). Requesting anything other than12715 * MATCH_ACTION_NONE on an EF10 NIC running another f/w variant will cause the12716 * filter insertion to fail with ENOTSUP.12717 */12718#define MC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_OFST 17212719#define MC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_LEN 412720/* enum: do nothing extra */12721#define MC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_NONE 0x012722/* enum: Set the match flag in the packet prefix for packets matching the12723 * filter (only with dpdk firmware, otherwise fails with ENOTSUP). Used to12724 * support the DPDK rte_flow "FLAG" action.12725 */12726#define MC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_FLAG 0x112727/* enum: Insert MATCH_MARK_VALUE into the packet prefix for packets matching12728 * the filter (only with dpdk firmware, otherwise fails with ENOTSUP). Used to12729 * support the DPDK rte_flow "MARK" action.12730 */12731#define MC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_MARK 0x212732/* the mark value for MATCH_ACTION_MARK. Requesting a value larger than the12733 * maximum (obtained from MC_CMD_GET_CAPABILITIES_V5/FILTER_ACTION_MARK_MAX)12734 * will cause the filter insertion to fail with EINVAL.12735 */12736#define MC_CMD_FILTER_OP_V3_IN_MATCH_MARK_VALUE_OFST 17612737#define MC_CMD_FILTER_OP_V3_IN_MATCH_MARK_VALUE_LEN 412738 12739/* MC_CMD_FILTER_OP_OUT msgresponse */12740#define MC_CMD_FILTER_OP_OUT_LEN 1212741/* identifies the type of operation requested */12742#define MC_CMD_FILTER_OP_OUT_OP_OFST 012743#define MC_CMD_FILTER_OP_OUT_OP_LEN 412744/* Enum values, see field(s): */12745/* MC_CMD_FILTER_OP_IN/OP */12746/* Returned filter handle (for insert / subscribe operations). Note that these12747 * handles should be considered opaque to the host, although a value of12748 * 0xFFFFFFFF_FFFFFFFF is guaranteed never to be a valid handle.12749 */12750#define MC_CMD_FILTER_OP_OUT_HANDLE_OFST 412751#define MC_CMD_FILTER_OP_OUT_HANDLE_LEN 812752#define MC_CMD_FILTER_OP_OUT_HANDLE_LO_OFST 412753#define MC_CMD_FILTER_OP_OUT_HANDLE_LO_LEN 412754#define MC_CMD_FILTER_OP_OUT_HANDLE_LO_LBN 3212755#define MC_CMD_FILTER_OP_OUT_HANDLE_LO_WIDTH 3212756#define MC_CMD_FILTER_OP_OUT_HANDLE_HI_OFST 812757#define MC_CMD_FILTER_OP_OUT_HANDLE_HI_LEN 412758#define MC_CMD_FILTER_OP_OUT_HANDLE_HI_LBN 6412759#define MC_CMD_FILTER_OP_OUT_HANDLE_HI_WIDTH 3212760/* enum: guaranteed invalid filter handle (low 32 bits) */12761#define MC_CMD_FILTER_OP_OUT_HANDLE_LO_INVALID 0xffffffff12762/* enum: guaranteed invalid filter handle (high 32 bits) */12763#define MC_CMD_FILTER_OP_OUT_HANDLE_HI_INVALID 0xffffffff12764 12765/* MC_CMD_FILTER_OP_EXT_OUT msgresponse */12766#define MC_CMD_FILTER_OP_EXT_OUT_LEN 1212767/* identifies the type of operation requested */12768#define MC_CMD_FILTER_OP_EXT_OUT_OP_OFST 012769#define MC_CMD_FILTER_OP_EXT_OUT_OP_LEN 412770/* Enum values, see field(s): */12771/* MC_CMD_FILTER_OP_EXT_IN/OP */12772/* Returned filter handle (for insert / subscribe operations). Note that these12773 * handles should be considered opaque to the host, although a value of12774 * 0xFFFFFFFF_FFFFFFFF is guaranteed never to be a valid handle.12775 */12776#define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_OFST 412777#define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_LEN 812778#define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_LO_OFST 412779#define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_LO_LEN 412780#define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_LO_LBN 3212781#define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_LO_WIDTH 3212782#define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_HI_OFST 812783#define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_HI_LEN 412784#define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_HI_LBN 6412785#define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_HI_WIDTH 3212786/* Enum values, see field(s): */12787/* MC_CMD_FILTER_OP_OUT/HANDLE */12788 12789 12790/***********************************/12791/* MC_CMD_GET_PARSER_DISP_INFO12792 * Get information related to the parser-dispatcher subsystem12793 */12794#define MC_CMD_GET_PARSER_DISP_INFO 0xe412795#undef MC_CMD_0xe4_PRIVILEGE_CTG12796 12797#define MC_CMD_0xe4_PRIVILEGE_CTG SRIOV_CTG_GENERAL12798 12799/* MC_CMD_GET_PARSER_DISP_INFO_IN msgrequest */12800#define MC_CMD_GET_PARSER_DISP_INFO_IN_LEN 412801/* identifies the type of operation requested */12802#define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_OFST 012803#define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_LEN 412804/* enum: read the list of supported RX filter matches */12805#define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_RX_MATCHES 0x112806/* enum: read flags indicating restrictions on filter insertion for the calling12807 * client12808 */12809#define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_RESTRICTIONS 0x212810/* enum: read properties relating to security rules (Medford-only; for use by12811 * SolarSecure apps, not directly by drivers. See SF-114946-SW.)12812 */12813#define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SECURITY_RULE_INFO 0x312814/* enum: read the list of supported RX filter matches for VXLAN/NVGRE12815 * encapsulated frames, which follow a different match sequence to normal12816 * frames (Medford only)12817 */12818#define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_ENCAP_RX_MATCHES 0x412819/* enum: read the list of supported matches for the encapsulation detection12820 * rules inserted by MC_CMD_VNIC_ENCAP_RULE_ADD. (ef100 and later)12821 */12822#define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_VNIC_ENCAP_MATCHES 0x512823/* enum: read the supported encapsulation types for the VNIC */12824#define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_VNIC_ENCAP_TYPES 0x612825 12826/* MC_CMD_GET_PARSER_DISP_INFO_OUT msgresponse */12827#define MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMIN 812828#define MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMAX 25212829#define MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMAX_MCDI2 102012830#define MC_CMD_GET_PARSER_DISP_INFO_OUT_LEN(num) (8+4*(num))12831#define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_NUM(len) (((len)-8)/4)12832/* identifies the type of operation requested */12833#define MC_CMD_GET_PARSER_DISP_INFO_OUT_OP_OFST 012834#define MC_CMD_GET_PARSER_DISP_INFO_OUT_OP_LEN 412835/* Enum values, see field(s): */12836/* MC_CMD_GET_PARSER_DISP_INFO_IN/OP */12837/* number of supported match types */12838#define MC_CMD_GET_PARSER_DISP_INFO_OUT_NUM_SUPPORTED_MATCHES_OFST 412839#define MC_CMD_GET_PARSER_DISP_INFO_OUT_NUM_SUPPORTED_MATCHES_LEN 412840/* array of supported match types (valid MATCH_FIELDS values for12841 * MC_CMD_FILTER_OP) sorted in decreasing priority order12842 */12843#define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_OFST 812844#define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_LEN 412845#define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MINNUM 012846#define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MAXNUM 6112847#define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MAXNUM_MCDI2 25312848 12849/* MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT msgresponse */12850#define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_LEN 812851/* identifies the type of operation requested */12852#define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_OP_OFST 012853#define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_OP_LEN 412854/* Enum values, see field(s): */12855/* MC_CMD_GET_PARSER_DISP_INFO_IN/OP */12856/* bitfield of filter insertion restrictions */12857#define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_RESTRICTION_FLAGS_OFST 412858#define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_RESTRICTION_FLAGS_LEN 412859#define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_DST_IP_MCAST_ONLY_OFST 412860#define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_DST_IP_MCAST_ONLY_LBN 012861#define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_DST_IP_MCAST_ONLY_WIDTH 112862 12863/* MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT msgresponse: This response is12864 * returned if a MC_CMD_GET_PARSER_DISP_INFO_IN request is sent with OP value12865 * OP_GET_SUPPORTED_VNIC_ENCAP_MATCHES. It contains information about the12866 * supported match types that can be used in the encapsulation detection rules12867 * inserted by MC_CMD_VNIC_ENCAP_RULE_ADD.12868 */12869#define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_LENMIN 812870#define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_LENMAX 25212871#define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_LENMAX_MCDI2 102012872#define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_LEN(num) (8+4*(num))12873#define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_SUPPORTED_MATCHES_NUM(len) (((len)-8)/4)12874/* The op code OP_GET_SUPPORTED_VNIC_ENCAP_MATCHES is returned. */12875#define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_OP_OFST 012876#define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_OP_LEN 412877/* Enum values, see field(s): */12878/* MC_CMD_GET_PARSER_DISP_INFO_IN/OP */12879/* number of supported match types */12880#define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_NUM_SUPPORTED_MATCHES_OFST 412881#define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_NUM_SUPPORTED_MATCHES_LEN 412882/* array of supported match types (valid MATCH_FLAGS values for12883 * MC_CMD_VNIC_ENCAP_RULE_ADD) sorted in decreasing priority order12884 */12885#define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_SUPPORTED_MATCHES_OFST 812886#define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_SUPPORTED_MATCHES_LEN 412887#define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_SUPPORTED_MATCHES_MINNUM 012888#define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_SUPPORTED_MATCHES_MAXNUM 6112889#define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_SUPPORTED_MATCHES_MAXNUM_MCDI2 25312890 12891/* MC_CMD_GET_PARSER_DISP_SUPPORTED_VNIC_ENCAP_TYPES_OUT msgresponse: Returns12892 * the supported encapsulation types for the VNIC12893 */12894#define MC_CMD_GET_PARSER_DISP_SUPPORTED_VNIC_ENCAP_TYPES_OUT_LEN 812895/* The op code OP_GET_SUPPORTED_VNIC_ENCAP_TYPES is returned */12896#define MC_CMD_GET_PARSER_DISP_SUPPORTED_VNIC_ENCAP_TYPES_OUT_OP_OFST 012897#define MC_CMD_GET_PARSER_DISP_SUPPORTED_VNIC_ENCAP_TYPES_OUT_OP_LEN 412898/* Enum values, see field(s): */12899/* MC_CMD_GET_PARSER_DISP_INFO_IN/OP */12900#define MC_CMD_GET_PARSER_DISP_SUPPORTED_VNIC_ENCAP_TYPES_OUT_ENCAP_TYPES_SUPPORTED_OFST 412901#define MC_CMD_GET_PARSER_DISP_SUPPORTED_VNIC_ENCAP_TYPES_OUT_ENCAP_TYPES_SUPPORTED_LEN 412902#define MC_CMD_GET_PARSER_DISP_SUPPORTED_VNIC_ENCAP_TYPES_OUT_ENCAP_TYPE_VXLAN_OFST 412903#define MC_CMD_GET_PARSER_DISP_SUPPORTED_VNIC_ENCAP_TYPES_OUT_ENCAP_TYPE_VXLAN_LBN 012904#define MC_CMD_GET_PARSER_DISP_SUPPORTED_VNIC_ENCAP_TYPES_OUT_ENCAP_TYPE_VXLAN_WIDTH 112905#define MC_CMD_GET_PARSER_DISP_SUPPORTED_VNIC_ENCAP_TYPES_OUT_ENCAP_TYPE_NVGRE_OFST 412906#define MC_CMD_GET_PARSER_DISP_SUPPORTED_VNIC_ENCAP_TYPES_OUT_ENCAP_TYPE_NVGRE_LBN 112907#define MC_CMD_GET_PARSER_DISP_SUPPORTED_VNIC_ENCAP_TYPES_OUT_ENCAP_TYPE_NVGRE_WIDTH 112908#define MC_CMD_GET_PARSER_DISP_SUPPORTED_VNIC_ENCAP_TYPES_OUT_ENCAP_TYPE_GENEVE_OFST 412909#define MC_CMD_GET_PARSER_DISP_SUPPORTED_VNIC_ENCAP_TYPES_OUT_ENCAP_TYPE_GENEVE_LBN 212910#define MC_CMD_GET_PARSER_DISP_SUPPORTED_VNIC_ENCAP_TYPES_OUT_ENCAP_TYPE_GENEVE_WIDTH 112911#define MC_CMD_GET_PARSER_DISP_SUPPORTED_VNIC_ENCAP_TYPES_OUT_ENCAP_TYPE_L2GRE_OFST 412912#define MC_CMD_GET_PARSER_DISP_SUPPORTED_VNIC_ENCAP_TYPES_OUT_ENCAP_TYPE_L2GRE_LBN 312913#define MC_CMD_GET_PARSER_DISP_SUPPORTED_VNIC_ENCAP_TYPES_OUT_ENCAP_TYPE_L2GRE_WIDTH 112914 12915 12916/***********************************/12917/* MC_CMD_PARSER_DISP_RW12918 * Direct read/write of parser-dispatcher state (DICPUs and LUE) for debugging.12919 * Please note that this interface is only of use to debug tools which have12920 * knowledge of firmware and hardware data structures; nothing here is intended12921 * for use by normal driver code. Note that although this command is in the12922 * Admin privilege group, in tamperproof adapters, only read operations are12923 * permitted.12924 */12925#define MC_CMD_PARSER_DISP_RW 0xe512926#undef MC_CMD_0xe5_PRIVILEGE_CTG12927 12928#define MC_CMD_0xe5_PRIVILEGE_CTG SRIOV_CTG_ADMIN12929 12930/* MC_CMD_PARSER_DISP_RW_IN msgrequest */12931#define MC_CMD_PARSER_DISP_RW_IN_LEN 3212932/* identifies the target of the operation */12933#define MC_CMD_PARSER_DISP_RW_IN_TARGET_OFST 012934#define MC_CMD_PARSER_DISP_RW_IN_TARGET_LEN 412935/* enum: RX dispatcher CPU */12936#define MC_CMD_PARSER_DISP_RW_IN_RX_DICPU 0x012937/* enum: TX dispatcher CPU */12938#define MC_CMD_PARSER_DISP_RW_IN_TX_DICPU 0x112939/* enum: Lookup engine (with original metadata format). Deprecated; used only12940 * by cmdclient as a fallback for very old Huntington firmware, and not12941 * supported in firmware beyond v6.4.0.1005. Use LUE_VERSIONED_METADATA12942 * instead.12943 */12944#define MC_CMD_PARSER_DISP_RW_IN_LUE 0x212945/* enum: Lookup engine (with requested metadata format) */12946#define MC_CMD_PARSER_DISP_RW_IN_LUE_VERSIONED_METADATA 0x312947/* enum: RX0 dispatcher CPU (alias for RX_DICPU; Medford has 2 RX DICPUs) */12948#define MC_CMD_PARSER_DISP_RW_IN_RX0_DICPU 0x012949/* enum: RX1 dispatcher CPU (only valid for Medford) */12950#define MC_CMD_PARSER_DISP_RW_IN_RX1_DICPU 0x412951/* enum: Miscellaneous other state (only valid for Medford) */12952#define MC_CMD_PARSER_DISP_RW_IN_MISC_STATE 0x512953/* identifies the type of operation requested */12954#define MC_CMD_PARSER_DISP_RW_IN_OP_OFST 412955#define MC_CMD_PARSER_DISP_RW_IN_OP_LEN 412956/* enum: Read a word of DICPU DMEM or a LUE entry */12957#define MC_CMD_PARSER_DISP_RW_IN_READ 0x012958/* enum: Write a word of DICPU DMEM or a LUE entry. Not permitted on12959 * tamperproof adapters.12960 */12961#define MC_CMD_PARSER_DISP_RW_IN_WRITE 0x112962/* enum: Read-modify-write a word of DICPU DMEM (not valid for LUE). Not12963 * permitted on tamperproof adapters.12964 */12965#define MC_CMD_PARSER_DISP_RW_IN_RMW 0x212966/* data memory address (DICPU targets) or LUE index (LUE targets) */12967#define MC_CMD_PARSER_DISP_RW_IN_ADDRESS_OFST 812968#define MC_CMD_PARSER_DISP_RW_IN_ADDRESS_LEN 412969/* selector (for MISC_STATE target) */12970#define MC_CMD_PARSER_DISP_RW_IN_SELECTOR_OFST 812971#define MC_CMD_PARSER_DISP_RW_IN_SELECTOR_LEN 412972/* enum: Port to datapath mapping */12973#define MC_CMD_PARSER_DISP_RW_IN_PORT_DP_MAPPING 0x112974/* value to write (for DMEM writes) */12975#define MC_CMD_PARSER_DISP_RW_IN_DMEM_WRITE_VALUE_OFST 1212976#define MC_CMD_PARSER_DISP_RW_IN_DMEM_WRITE_VALUE_LEN 412977/* XOR value (for DMEM read-modify-writes: new = (old & mask) ^ value) */12978#define MC_CMD_PARSER_DISP_RW_IN_DMEM_RMW_XOR_VALUE_OFST 1212979#define MC_CMD_PARSER_DISP_RW_IN_DMEM_RMW_XOR_VALUE_LEN 412980/* AND mask (for DMEM read-modify-writes: new = (old & mask) ^ value) */12981#define MC_CMD_PARSER_DISP_RW_IN_DMEM_RMW_AND_MASK_OFST 1612982#define MC_CMD_PARSER_DISP_RW_IN_DMEM_RMW_AND_MASK_LEN 412983/* metadata format (for LUE reads using LUE_VERSIONED_METADATA) */12984#define MC_CMD_PARSER_DISP_RW_IN_LUE_READ_METADATA_VERSION_OFST 1212985#define MC_CMD_PARSER_DISP_RW_IN_LUE_READ_METADATA_VERSION_LEN 412986/* value to write (for LUE writes) */12987#define MC_CMD_PARSER_DISP_RW_IN_LUE_WRITE_VALUE_OFST 1212988#define MC_CMD_PARSER_DISP_RW_IN_LUE_WRITE_VALUE_LEN 2012989 12990/* MC_CMD_PARSER_DISP_RW_OUT msgresponse */12991#define MC_CMD_PARSER_DISP_RW_OUT_LEN 5212992/* value read (for DMEM reads) */12993#define MC_CMD_PARSER_DISP_RW_OUT_DMEM_READ_VALUE_OFST 012994#define MC_CMD_PARSER_DISP_RW_OUT_DMEM_READ_VALUE_LEN 412995/* value read (for LUE reads) */12996#define MC_CMD_PARSER_DISP_RW_OUT_LUE_READ_VALUE_OFST 012997#define MC_CMD_PARSER_DISP_RW_OUT_LUE_READ_VALUE_LEN 2012998/* up to 8 32-bit words of additional soft state from the LUE manager (the12999 * exact content is firmware-dependent and intended only for debug use)13000 */13001#define MC_CMD_PARSER_DISP_RW_OUT_LUE_MGR_STATE_OFST 2013002#define MC_CMD_PARSER_DISP_RW_OUT_LUE_MGR_STATE_LEN 3213003/* datapath(s) used for each port (for MISC_STATE PORT_DP_MAPPING selector) */13004#define MC_CMD_PARSER_DISP_RW_OUT_PORT_DP_MAPPING_OFST 013005#define MC_CMD_PARSER_DISP_RW_OUT_PORT_DP_MAPPING_LEN 413006#define MC_CMD_PARSER_DISP_RW_OUT_PORT_DP_MAPPING_NUM 413007#define MC_CMD_PARSER_DISP_RW_OUT_DP0 0x1 /* enum */13008#define MC_CMD_PARSER_DISP_RW_OUT_DP1 0x2 /* enum */13009 13010 13011/***********************************/13012/* MC_CMD_GET_PF_COUNT13013 * Get number of PFs on the device.13014 */13015#define MC_CMD_GET_PF_COUNT 0xb613016#undef MC_CMD_0xb6_PRIVILEGE_CTG13017 13018#define MC_CMD_0xb6_PRIVILEGE_CTG SRIOV_CTG_GENERAL13019 13020/* MC_CMD_GET_PF_COUNT_IN msgrequest */13021#define MC_CMD_GET_PF_COUNT_IN_LEN 013022 13023/* MC_CMD_GET_PF_COUNT_OUT msgresponse */13024#define MC_CMD_GET_PF_COUNT_OUT_LEN 113025/* Identifies the number of PFs on the device. */13026#define MC_CMD_GET_PF_COUNT_OUT_PF_COUNT_OFST 013027#define MC_CMD_GET_PF_COUNT_OUT_PF_COUNT_LEN 113028 13029 13030/***********************************/13031/* MC_CMD_SET_PF_COUNT13032 * Set number of PFs on the device.13033 */13034#define MC_CMD_SET_PF_COUNT 0xb713035 13036/* MC_CMD_SET_PF_COUNT_IN msgrequest */13037#define MC_CMD_SET_PF_COUNT_IN_LEN 413038/* New number of PFs on the device. */13039#define MC_CMD_SET_PF_COUNT_IN_PF_COUNT_OFST 013040#define MC_CMD_SET_PF_COUNT_IN_PF_COUNT_LEN 413041 13042/* MC_CMD_SET_PF_COUNT_OUT msgresponse */13043#define MC_CMD_SET_PF_COUNT_OUT_LEN 013044 13045 13046/***********************************/13047/* MC_CMD_GET_PORT_ASSIGNMENT13048 * Get port assignment for current PCI function.13049 */13050#define MC_CMD_GET_PORT_ASSIGNMENT 0xb813051#undef MC_CMD_0xb8_PRIVILEGE_CTG13052 13053#define MC_CMD_0xb8_PRIVILEGE_CTG SRIOV_CTG_GENERAL13054 13055/* MC_CMD_GET_PORT_ASSIGNMENT_IN msgrequest */13056#define MC_CMD_GET_PORT_ASSIGNMENT_IN_LEN 013057 13058/* MC_CMD_GET_PORT_ASSIGNMENT_OUT msgresponse */13059#define MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN 413060/* Identifies the port assignment for this function. On EF100, it is possible13061 * for the function to have no network port assigned (either because it is not13062 * yet configured, or assigning a port to a given function personality makes no13063 * sense - e.g. virtio-blk), in which case the return value is NULL_PORT.13064 */13065#define MC_CMD_GET_PORT_ASSIGNMENT_OUT_PORT_OFST 013066#define MC_CMD_GET_PORT_ASSIGNMENT_OUT_PORT_LEN 413067/* enum: Special value to indicate no port is assigned to a function. */13068#define MC_CMD_GET_PORT_ASSIGNMENT_OUT_NULL_PORT 0xffffffff13069 13070 13071/***********************************/13072/* MC_CMD_SET_PORT_ASSIGNMENT13073 * Set port assignment for current PCI function.13074 */13075#define MC_CMD_SET_PORT_ASSIGNMENT 0xb913076#undef MC_CMD_0xb9_PRIVILEGE_CTG13077 13078#define MC_CMD_0xb9_PRIVILEGE_CTG SRIOV_CTG_ADMIN13079 13080/* MC_CMD_SET_PORT_ASSIGNMENT_IN msgrequest */13081#define MC_CMD_SET_PORT_ASSIGNMENT_IN_LEN 413082/* Identifies the port assignment for this function. */13083#define MC_CMD_SET_PORT_ASSIGNMENT_IN_PORT_OFST 013084#define MC_CMD_SET_PORT_ASSIGNMENT_IN_PORT_LEN 413085 13086/* MC_CMD_SET_PORT_ASSIGNMENT_OUT msgresponse */13087#define MC_CMD_SET_PORT_ASSIGNMENT_OUT_LEN 013088 13089 13090/***********************************/13091/* MC_CMD_ALLOC_VIS13092 * Allocate VIs for current PCI function.13093 */13094#define MC_CMD_ALLOC_VIS 0x8b13095#undef MC_CMD_0x8b_PRIVILEGE_CTG13096 13097#define MC_CMD_0x8b_PRIVILEGE_CTG SRIOV_CTG_GENERAL13098 13099/* MC_CMD_ALLOC_VIS_IN msgrequest */13100#define MC_CMD_ALLOC_VIS_IN_LEN 813101/* The minimum number of VIs that is acceptable */13102#define MC_CMD_ALLOC_VIS_IN_MIN_VI_COUNT_OFST 013103#define MC_CMD_ALLOC_VIS_IN_MIN_VI_COUNT_LEN 413104/* The maximum number of VIs that would be useful */13105#define MC_CMD_ALLOC_VIS_IN_MAX_VI_COUNT_OFST 413106#define MC_CMD_ALLOC_VIS_IN_MAX_VI_COUNT_LEN 413107 13108/* MC_CMD_ALLOC_VIS_OUT msgresponse: Huntington-compatible VI_ALLOC request.13109 * Use extended version in new code.13110 */13111#define MC_CMD_ALLOC_VIS_OUT_LEN 813112/* The number of VIs allocated on this function */13113#define MC_CMD_ALLOC_VIS_OUT_VI_COUNT_OFST 013114#define MC_CMD_ALLOC_VIS_OUT_VI_COUNT_LEN 413115/* The base absolute VI number allocated to this function. Required to13116 * correctly interpret wakeup events.13117 */13118#define MC_CMD_ALLOC_VIS_OUT_VI_BASE_OFST 413119#define MC_CMD_ALLOC_VIS_OUT_VI_BASE_LEN 413120 13121/* MC_CMD_ALLOC_VIS_EXT_OUT msgresponse */13122#define MC_CMD_ALLOC_VIS_EXT_OUT_LEN 1213123/* The number of VIs allocated on this function */13124#define MC_CMD_ALLOC_VIS_EXT_OUT_VI_COUNT_OFST 013125#define MC_CMD_ALLOC_VIS_EXT_OUT_VI_COUNT_LEN 413126/* The base absolute VI number allocated to this function. Required to13127 * correctly interpret wakeup events.13128 */13129#define MC_CMD_ALLOC_VIS_EXT_OUT_VI_BASE_OFST 413130#define MC_CMD_ALLOC_VIS_EXT_OUT_VI_BASE_LEN 413131/* Function's port vi_shift value (always 0 on Huntington) */13132#define MC_CMD_ALLOC_VIS_EXT_OUT_VI_SHIFT_OFST 813133#define MC_CMD_ALLOC_VIS_EXT_OUT_VI_SHIFT_LEN 413134 13135 13136/***********************************/13137/* MC_CMD_FREE_VIS13138 * Free VIs for current PCI function. Any linked PIO buffers will be unlinked,13139 * but not freed.13140 */13141#define MC_CMD_FREE_VIS 0x8c13142#undef MC_CMD_0x8c_PRIVILEGE_CTG13143 13144#define MC_CMD_0x8c_PRIVILEGE_CTG SRIOV_CTG_GENERAL13145 13146/* MC_CMD_FREE_VIS_IN msgrequest */13147#define MC_CMD_FREE_VIS_IN_LEN 013148 13149/* MC_CMD_FREE_VIS_OUT msgresponse */13150#define MC_CMD_FREE_VIS_OUT_LEN 013151 13152 13153/***********************************/13154/* MC_CMD_GET_SRIOV_CFG13155 * Get SRIOV config for this PF.13156 */13157#define MC_CMD_GET_SRIOV_CFG 0xba13158#undef MC_CMD_0xba_PRIVILEGE_CTG13159 13160#define MC_CMD_0xba_PRIVILEGE_CTG SRIOV_CTG_GENERAL13161 13162/* MC_CMD_GET_SRIOV_CFG_IN msgrequest */13163#define MC_CMD_GET_SRIOV_CFG_IN_LEN 013164 13165/* MC_CMD_GET_SRIOV_CFG_OUT msgresponse */13166#define MC_CMD_GET_SRIOV_CFG_OUT_LEN 2013167/* Number of VFs currently enabled. */13168#define MC_CMD_GET_SRIOV_CFG_OUT_VF_CURRENT_OFST 013169#define MC_CMD_GET_SRIOV_CFG_OUT_VF_CURRENT_LEN 413170/* Max number of VFs before sriov stride and offset may need to be changed. */13171#define MC_CMD_GET_SRIOV_CFG_OUT_VF_MAX_OFST 413172#define MC_CMD_GET_SRIOV_CFG_OUT_VF_MAX_LEN 413173#define MC_CMD_GET_SRIOV_CFG_OUT_FLAGS_OFST 813174#define MC_CMD_GET_SRIOV_CFG_OUT_FLAGS_LEN 413175#define MC_CMD_GET_SRIOV_CFG_OUT_VF_ENABLED_OFST 813176#define MC_CMD_GET_SRIOV_CFG_OUT_VF_ENABLED_LBN 013177#define MC_CMD_GET_SRIOV_CFG_OUT_VF_ENABLED_WIDTH 113178/* RID offset of first VF from PF. */13179#define MC_CMD_GET_SRIOV_CFG_OUT_VF_OFFSET_OFST 1213180#define MC_CMD_GET_SRIOV_CFG_OUT_VF_OFFSET_LEN 413181/* RID offset of each subsequent VF from the previous. */13182#define MC_CMD_GET_SRIOV_CFG_OUT_VF_STRIDE_OFST 1613183#define MC_CMD_GET_SRIOV_CFG_OUT_VF_STRIDE_LEN 413184 13185 13186/***********************************/13187/* MC_CMD_SET_SRIOV_CFG13188 * Set SRIOV config for this PF.13189 */13190#define MC_CMD_SET_SRIOV_CFG 0xbb13191#undef MC_CMD_0xbb_PRIVILEGE_CTG13192 13193#define MC_CMD_0xbb_PRIVILEGE_CTG SRIOV_CTG_ADMIN13194 13195/* MC_CMD_SET_SRIOV_CFG_IN msgrequest */13196#define MC_CMD_SET_SRIOV_CFG_IN_LEN 2013197/* Number of VFs currently enabled. */13198#define MC_CMD_SET_SRIOV_CFG_IN_VF_CURRENT_OFST 013199#define MC_CMD_SET_SRIOV_CFG_IN_VF_CURRENT_LEN 413200/* Max number of VFs before sriov stride and offset may need to be changed. */13201#define MC_CMD_SET_SRIOV_CFG_IN_VF_MAX_OFST 413202#define MC_CMD_SET_SRIOV_CFG_IN_VF_MAX_LEN 413203#define MC_CMD_SET_SRIOV_CFG_IN_FLAGS_OFST 813204#define MC_CMD_SET_SRIOV_CFG_IN_FLAGS_LEN 413205#define MC_CMD_SET_SRIOV_CFG_IN_VF_ENABLED_OFST 813206#define MC_CMD_SET_SRIOV_CFG_IN_VF_ENABLED_LBN 013207#define MC_CMD_SET_SRIOV_CFG_IN_VF_ENABLED_WIDTH 113208/* RID offset of first VF from PF, or 0 for no change, or13209 * MC_CMD_RESOURCE_INSTANCE_ANY to allow the system to allocate an offset.13210 */13211#define MC_CMD_SET_SRIOV_CFG_IN_VF_OFFSET_OFST 1213212#define MC_CMD_SET_SRIOV_CFG_IN_VF_OFFSET_LEN 413213/* RID offset of each subsequent VF from the previous, 0 for no change, or13214 * MC_CMD_RESOURCE_INSTANCE_ANY to allow the system to allocate a stride.13215 */13216#define MC_CMD_SET_SRIOV_CFG_IN_VF_STRIDE_OFST 1613217#define MC_CMD_SET_SRIOV_CFG_IN_VF_STRIDE_LEN 413218 13219/* MC_CMD_SET_SRIOV_CFG_OUT msgresponse */13220#define MC_CMD_SET_SRIOV_CFG_OUT_LEN 013221 13222 13223/***********************************/13224/* MC_CMD_GET_VI_ALLOC_INFO13225 * Get information about number of VI's and base VI number allocated to this13226 * function. This message is not available to dynamic clients created by13227 * MC_CMD_CLIENT_ALLOC.13228 */13229#define MC_CMD_GET_VI_ALLOC_INFO 0x8d13230#undef MC_CMD_0x8d_PRIVILEGE_CTG13231 13232#define MC_CMD_0x8d_PRIVILEGE_CTG SRIOV_CTG_GENERAL13233 13234/* MC_CMD_GET_VI_ALLOC_INFO_IN msgrequest */13235#define MC_CMD_GET_VI_ALLOC_INFO_IN_LEN 013236 13237/* MC_CMD_GET_VI_ALLOC_INFO_OUT msgresponse */13238#define MC_CMD_GET_VI_ALLOC_INFO_OUT_LEN 1213239/* The number of VIs allocated on this function */13240#define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_COUNT_OFST 013241#define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_COUNT_LEN 413242/* The base absolute VI number allocated to this function. Required to13243 * correctly interpret wakeup events.13244 */13245#define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_BASE_OFST 413246#define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_BASE_LEN 413247/* Function's port vi_shift value (always 0 on Huntington) */13248#define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_SHIFT_OFST 813249#define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_SHIFT_LEN 413250 13251 13252/***********************************/13253/* MC_CMD_DUMP_VI_STATE13254 * For CmdClient use. Dump pertinent information on a specific absolute VI. The13255 * VI must be owned by the calling client or one of its ancestors; usership of13256 * the VI (as set by MC_CMD_SET_VI_USER) is not sufficient.13257 */13258#define MC_CMD_DUMP_VI_STATE 0x8e13259#undef MC_CMD_0x8e_PRIVILEGE_CTG13260 13261#define MC_CMD_0x8e_PRIVILEGE_CTG SRIOV_CTG_GENERAL13262 13263/* MC_CMD_DUMP_VI_STATE_IN msgrequest */13264#define MC_CMD_DUMP_VI_STATE_IN_LEN 413265/* The VI number to query. */13266#define MC_CMD_DUMP_VI_STATE_IN_VI_NUMBER_OFST 013267#define MC_CMD_DUMP_VI_STATE_IN_VI_NUMBER_LEN 413268 13269/* MC_CMD_DUMP_VI_STATE_OUT msgresponse */13270#define MC_CMD_DUMP_VI_STATE_OUT_LEN 10013271/* The PF part of the function owning this VI. */13272#define MC_CMD_DUMP_VI_STATE_OUT_OWNER_PF_OFST 013273#define MC_CMD_DUMP_VI_STATE_OUT_OWNER_PF_LEN 213274/* The VF part of the function owning this VI. */13275#define MC_CMD_DUMP_VI_STATE_OUT_OWNER_VF_OFST 213276#define MC_CMD_DUMP_VI_STATE_OUT_OWNER_VF_LEN 213277/* Base of VIs allocated to this function. */13278#define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_BASE_OFST 413279#define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_BASE_LEN 213280/* Count of VIs allocated to the owner function. */13281#define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_COUNT_OFST 613282#define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_COUNT_LEN 213283/* Base interrupt vector allocated to this function. */13284#define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_BASE_OFST 813285#define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_BASE_LEN 213286/* Number of interrupt vectors allocated to this function. */13287#define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_COUNT_OFST 1013288#define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_COUNT_LEN 213289/* Raw evq ptr table data. */13290#define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_OFST 1213291#define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_LEN 813292#define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_LO_OFST 1213293#define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_LO_LEN 413294#define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_LO_LBN 9613295#define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_LO_WIDTH 3213296#define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_HI_OFST 1613297#define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_HI_LEN 413298#define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_HI_LBN 12813299#define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_HI_WIDTH 3213300/* Raw evq timer table data. */13301#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_OFST 2013302#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_LEN 813303#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_LO_OFST 2013304#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_LO_LEN 413305#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_LO_LBN 16013306#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_LO_WIDTH 3213307#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_HI_OFST 2413308#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_HI_LEN 413309#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_HI_LBN 19213310#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_HI_WIDTH 3213311/* Combined metadata field. */13312#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_OFST 2813313#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_LEN 413314#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_BASE_OFST 2813315#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_BASE_LBN 013316#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_BASE_WIDTH 1613317#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_NPAGES_OFST 2813318#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_NPAGES_LBN 1613319#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_NPAGES_WIDTH 813320#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_WKUP_REF_OFST 2813321#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_WKUP_REF_LBN 2413322#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_WKUP_REF_WIDTH 813323/* TXDPCPU raw table data for queue. */13324#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_OFST 3213325#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_LEN 813326#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_LO_OFST 3213327#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_LO_LEN 413328#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_LO_LBN 25613329#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_LO_WIDTH 3213330#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_HI_OFST 3613331#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_HI_LEN 413332#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_HI_LBN 28813333#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_HI_WIDTH 3213334/* TXDPCPU raw table data for queue. */13335#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_OFST 4013336#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_LEN 813337#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_LO_OFST 4013338#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_LO_LEN 413339#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_LO_LBN 32013340#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_LO_WIDTH 3213341#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_HI_OFST 4413342#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_HI_LEN 413343#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_HI_LBN 35213344#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_HI_WIDTH 3213345/* TXDPCPU raw table data for queue. */13346#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_OFST 4813347#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_LEN 813348#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_LO_OFST 4813349#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_LO_LEN 413350#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_LO_LBN 38413351#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_LO_WIDTH 3213352#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_HI_OFST 5213353#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_HI_LEN 413354#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_HI_LBN 41613355#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_HI_WIDTH 3213356/* Combined metadata field. */13357#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_OFST 5613358#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_LEN 813359#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_LO_OFST 5613360#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_LO_LEN 413361#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_LO_LBN 44813362#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_LO_WIDTH 3213363#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_HI_OFST 6013364#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_HI_LEN 413365#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_HI_LBN 48013366#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_HI_WIDTH 3213367#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_BASE_OFST 5613368#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_BASE_LBN 013369#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_BASE_WIDTH 1613370#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_NPAGES_OFST 5613371#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_NPAGES_LBN 1613372#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_NPAGES_WIDTH 813373#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_QSTATE_OFST 5613374#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_QSTATE_LBN 2413375#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_QSTATE_WIDTH 813376#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_WAITCOUNT_OFST 5613377#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_WAITCOUNT_LBN 3213378#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_WAITCOUNT_WIDTH 813379#define MC_CMD_DUMP_VI_STATE_OUT_VI_PADDING_OFST 5613380#define MC_CMD_DUMP_VI_STATE_OUT_VI_PADDING_LBN 4013381#define MC_CMD_DUMP_VI_STATE_OUT_VI_PADDING_WIDTH 2413382/* RXDPCPU raw table data for queue. */13383#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_OFST 6413384#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_LEN 813385#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_LO_OFST 6413386#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_LO_LEN 413387#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_LO_LBN 51213388#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_LO_WIDTH 3213389#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_HI_OFST 6813390#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_HI_LEN 413391#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_HI_LBN 54413392#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_HI_WIDTH 3213393/* RXDPCPU raw table data for queue. */13394#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_OFST 7213395#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_LEN 813396#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_LO_OFST 7213397#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_LO_LEN 413398#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_LO_LBN 57613399#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_LO_WIDTH 3213400#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_HI_OFST 7613401#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_HI_LEN 413402#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_HI_LBN 60813403#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_HI_WIDTH 3213404/* Reserved, currently 0. */13405#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_OFST 8013406#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_LEN 813407#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_LO_OFST 8013408#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_LO_LEN 413409#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_LO_LBN 64013410#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_LO_WIDTH 3213411#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_HI_OFST 8413412#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_HI_LEN 413413#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_HI_LBN 67213414#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_HI_WIDTH 3213415/* Combined metadata field. */13416#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_OFST 8813417#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_LEN 813418#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_LO_OFST 8813419#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_LO_LEN 413420#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_LO_LBN 70413421#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_LO_WIDTH 3213422#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_HI_OFST 9213423#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_HI_LEN 413424#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_HI_LBN 73613425#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_HI_WIDTH 3213426#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_BASE_OFST 8813427#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_BASE_LBN 013428#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_BASE_WIDTH 1613429#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_NPAGES_OFST 8813430#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_NPAGES_LBN 1613431#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_NPAGES_WIDTH 813432#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_QSTATE_OFST 8813433#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_QSTATE_LBN 2413434#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_QSTATE_WIDTH 813435#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_WAITCOUNT_OFST 8813436#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_WAITCOUNT_LBN 3213437#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_WAITCOUNT_WIDTH 813438/* Current user, as assigned by MC_CMD_SET_VI_USER. */13439#define MC_CMD_DUMP_VI_STATE_OUT_USER_CLIENT_ID_OFST 9613440#define MC_CMD_DUMP_VI_STATE_OUT_USER_CLIENT_ID_LEN 413441 13442 13443/***********************************/13444/* MC_CMD_ALLOC_PIOBUF13445 * Allocate a push I/O buffer for later use with a tx queue.13446 */13447#define MC_CMD_ALLOC_PIOBUF 0x8f13448#undef MC_CMD_0x8f_PRIVILEGE_CTG13449 13450#define MC_CMD_0x8f_PRIVILEGE_CTG SRIOV_CTG_ONLOAD13451 13452/* MC_CMD_ALLOC_PIOBUF_IN msgrequest */13453#define MC_CMD_ALLOC_PIOBUF_IN_LEN 013454 13455/* MC_CMD_ALLOC_PIOBUF_OUT msgresponse */13456#define MC_CMD_ALLOC_PIOBUF_OUT_LEN 413457/* Handle for allocated push I/O buffer. */13458#define MC_CMD_ALLOC_PIOBUF_OUT_PIOBUF_HANDLE_OFST 013459#define MC_CMD_ALLOC_PIOBUF_OUT_PIOBUF_HANDLE_LEN 413460 13461 13462/***********************************/13463/* MC_CMD_FREE_PIOBUF13464 * Free a push I/O buffer.13465 */13466#define MC_CMD_FREE_PIOBUF 0x9013467#undef MC_CMD_0x90_PRIVILEGE_CTG13468 13469#define MC_CMD_0x90_PRIVILEGE_CTG SRIOV_CTG_ONLOAD13470 13471/* MC_CMD_FREE_PIOBUF_IN msgrequest */13472#define MC_CMD_FREE_PIOBUF_IN_LEN 413473/* Handle for allocated push I/O buffer. */13474#define MC_CMD_FREE_PIOBUF_IN_PIOBUF_HANDLE_OFST 013475#define MC_CMD_FREE_PIOBUF_IN_PIOBUF_HANDLE_LEN 413476 13477/* MC_CMD_FREE_PIOBUF_OUT msgresponse */13478#define MC_CMD_FREE_PIOBUF_OUT_LEN 013479 13480 13481/***********************************/13482/* MC_CMD_GET_VI_TLP_PROCESSING13483 * Get TLP steering and ordering information for a VI. The caller must have the13484 * GRP_FUNC_DMA privilege and must be the currently-assigned user of this VI or13485 * an ancestor of the current user (see MC_CMD_SET_VI_USER).13486 */13487#define MC_CMD_GET_VI_TLP_PROCESSING 0xb013488#undef MC_CMD_0xb0_PRIVILEGE_CTG13489 13490#define MC_CMD_0xb0_PRIVILEGE_CTG SRIOV_CTG_GENERAL13491 13492/* MC_CMD_GET_VI_TLP_PROCESSING_IN msgrequest */13493#define MC_CMD_GET_VI_TLP_PROCESSING_IN_LEN 413494/* VI number to get information for. */13495#define MC_CMD_GET_VI_TLP_PROCESSING_IN_INSTANCE_OFST 013496#define MC_CMD_GET_VI_TLP_PROCESSING_IN_INSTANCE_LEN 413497 13498/* MC_CMD_GET_VI_TLP_PROCESSING_OUT msgresponse */13499#define MC_CMD_GET_VI_TLP_PROCESSING_OUT_LEN 413500/* Transaction processing steering hint 1 for use with the Rx Queue. */13501#define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG1_RX_OFST 013502#define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG1_RX_LEN 113503/* Transaction processing steering hint 2 for use with the Ev Queue. */13504#define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG2_EV_OFST 113505#define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG2_EV_LEN 113506/* Use Relaxed ordering model for TLPs on this VI. */13507#define MC_CMD_GET_VI_TLP_PROCESSING_OUT_RELAXED_ORDERING_LBN 1613508#define MC_CMD_GET_VI_TLP_PROCESSING_OUT_RELAXED_ORDERING_WIDTH 113509/* Use ID based ordering for TLPs on this VI. */13510#define MC_CMD_GET_VI_TLP_PROCESSING_OUT_ID_BASED_ORDERING_LBN 1713511#define MC_CMD_GET_VI_TLP_PROCESSING_OUT_ID_BASED_ORDERING_WIDTH 113512/* Set no snoop bit for TLPs on this VI. */13513#define MC_CMD_GET_VI_TLP_PROCESSING_OUT_NO_SNOOP_LBN 1813514#define MC_CMD_GET_VI_TLP_PROCESSING_OUT_NO_SNOOP_WIDTH 113515/* Enable TPH for TLPs on this VI. */13516#define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_ON_LBN 1913517#define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_ON_WIDTH 113518#define MC_CMD_GET_VI_TLP_PROCESSING_OUT_DATA_OFST 013519#define MC_CMD_GET_VI_TLP_PROCESSING_OUT_DATA_LEN 413520 13521 13522/***********************************/13523/* MC_CMD_SET_VI_TLP_PROCESSING13524 * Set TLP steering and ordering information for a VI. The caller must have the13525 * GRP_FUNC_DMA privilege and must be the currently-assigned user of this VI or13526 * an ancestor of the current user (see MC_CMD_SET_VI_USER).13527 */13528#define MC_CMD_SET_VI_TLP_PROCESSING 0xb113529#undef MC_CMD_0xb1_PRIVILEGE_CTG13530 13531#define MC_CMD_0xb1_PRIVILEGE_CTG SRIOV_CTG_GENERAL13532 13533/* MC_CMD_SET_VI_TLP_PROCESSING_IN msgrequest */13534#define MC_CMD_SET_VI_TLP_PROCESSING_IN_LEN 813535/* VI number to set information for. */13536#define MC_CMD_SET_VI_TLP_PROCESSING_IN_INSTANCE_OFST 013537#define MC_CMD_SET_VI_TLP_PROCESSING_IN_INSTANCE_LEN 413538/* Transaction processing steering hint 1 for use with the Rx Queue. */13539#define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG1_RX_OFST 413540#define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG1_RX_LEN 113541/* Transaction processing steering hint 2 for use with the Ev Queue. */13542#define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG2_EV_OFST 513543#define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG2_EV_LEN 113544/* Use Relaxed ordering model for TLPs on this VI. */13545#define MC_CMD_SET_VI_TLP_PROCESSING_IN_RELAXED_ORDERING_LBN 4813546#define MC_CMD_SET_VI_TLP_PROCESSING_IN_RELAXED_ORDERING_WIDTH 113547/* Use ID based ordering for TLPs on this VI. */13548#define MC_CMD_SET_VI_TLP_PROCESSING_IN_ID_BASED_ORDERING_LBN 4913549#define MC_CMD_SET_VI_TLP_PROCESSING_IN_ID_BASED_ORDERING_WIDTH 113550/* Set the no snoop bit for TLPs on this VI. */13551#define MC_CMD_SET_VI_TLP_PROCESSING_IN_NO_SNOOP_LBN 5013552#define MC_CMD_SET_VI_TLP_PROCESSING_IN_NO_SNOOP_WIDTH 113553/* Enable TPH for TLPs on this VI. */13554#define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_ON_LBN 5113555#define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_ON_WIDTH 113556#define MC_CMD_SET_VI_TLP_PROCESSING_IN_DATA_OFST 413557#define MC_CMD_SET_VI_TLP_PROCESSING_IN_DATA_LEN 413558 13559/* MC_CMD_SET_VI_TLP_PROCESSING_OUT msgresponse */13560#define MC_CMD_SET_VI_TLP_PROCESSING_OUT_LEN 013561 13562 13563/***********************************/13564/* MC_CMD_GET_TLP_PROCESSING_GLOBALS13565 * Get global PCIe steering and transaction processing configuration.13566 */13567#define MC_CMD_GET_TLP_PROCESSING_GLOBALS 0xbc13568#undef MC_CMD_0xbc_PRIVILEGE_CTG13569 13570#define MC_CMD_0xbc_PRIVILEGE_CTG SRIOV_CTG_ADMIN13571 13572/* MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN msgrequest */13573#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_LEN 413574#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_OFST 013575#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_LEN 413576/* enum: MISC. */13577#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_MISC 0x013578/* enum: IDO. */13579#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_IDO 0x113580/* enum: RO. */13581#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_RO 0x213582/* enum: TPH Type. */13583#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_TPH_TYPE 0x313584 13585/* MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT msgresponse */13586#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_LEN 813587#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_GLOBAL_CATEGORY_OFST 013588#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_GLOBAL_CATEGORY_LEN 413589/* Enum values, see field(s): */13590/* MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN/TLP_GLOBAL_CATEGORY */13591/* Amalgamated TLP info word. */13592#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_WORD_OFST 413593#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_WORD_LEN 413594#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_WTAG_EN_OFST 413595#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_WTAG_EN_LBN 013596#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_WTAG_EN_WIDTH 113597#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_SPARE_OFST 413598#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_SPARE_LBN 113599#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_SPARE_WIDTH 3113600#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_DL_EN_OFST 413601#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_DL_EN_LBN 013602#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_DL_EN_WIDTH 113603#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_TX_EN_OFST 413604#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_TX_EN_LBN 113605#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_TX_EN_WIDTH 113606#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_EV_EN_OFST 413607#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_EV_EN_LBN 213608#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_EV_EN_WIDTH 113609#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_RX_EN_OFST 413610#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_RX_EN_LBN 313611#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_RX_EN_WIDTH 113612#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_SPARE_OFST 413613#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_SPARE_LBN 413614#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_SPARE_WIDTH 2813615#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_RXDMA_EN_OFST 413616#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_RXDMA_EN_LBN 013617#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_RXDMA_EN_WIDTH 113618#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_TXDMA_EN_OFST 413619#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_TXDMA_EN_LBN 113620#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_TXDMA_EN_WIDTH 113621#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_DL_EN_OFST 413622#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_DL_EN_LBN 213623#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_DL_EN_WIDTH 113624#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_SPARE_OFST 413625#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_SPARE_LBN 313626#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_SPARE_WIDTH 2913627#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_MSIX_OFST 413628#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_MSIX_LBN 013629#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_MSIX_WIDTH 213630#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_DL_OFST 413631#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_DL_LBN 213632#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_DL_WIDTH 213633#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_TX_OFST 413634#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_TX_LBN 413635#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_TX_WIDTH 213636#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_EV_OFST 413637#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_EV_LBN 613638#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_EV_WIDTH 213639#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_RX_OFST 413640#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_RX_LBN 813641#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_RX_WIDTH 213642#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TLP_TYPE_SPARE_OFST 413643#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TLP_TYPE_SPARE_LBN 913644#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TLP_TYPE_SPARE_WIDTH 2313645 13646 13647/***********************************/13648/* MC_CMD_SET_TLP_PROCESSING_GLOBALS13649 * Set global PCIe steering and transaction processing configuration.13650 */13651#define MC_CMD_SET_TLP_PROCESSING_GLOBALS 0xbd13652#undef MC_CMD_0xbd_PRIVILEGE_CTG13653 13654#define MC_CMD_0xbd_PRIVILEGE_CTG SRIOV_CTG_ADMIN13655 13656/* MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN msgrequest */13657#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_LEN 813658#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_OFST 013659#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_LEN 413660/* Enum values, see field(s): */13661/* MC_CMD_GET_TLP_PROCESSING_GLOBALS/MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN/TLP_GLOBAL_CATEGORY */13662/* Amalgamated TLP info word. */13663#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_WORD_OFST 413664#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_WORD_LEN 413665#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_MISC_WTAG_EN_OFST 413666#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_MISC_WTAG_EN_LBN 013667#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_MISC_WTAG_EN_WIDTH 113668#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_DL_EN_OFST 413669#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_DL_EN_LBN 013670#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_DL_EN_WIDTH 113671#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_TX_EN_OFST 413672#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_TX_EN_LBN 113673#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_TX_EN_WIDTH 113674#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_EV_EN_OFST 413675#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_EV_EN_LBN 213676#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_EV_EN_WIDTH 113677#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_RX_EN_OFST 413678#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_RX_EN_LBN 313679#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_RX_EN_WIDTH 113680#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_RXDMA_EN_OFST 413681#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_RXDMA_EN_LBN 013682#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_RXDMA_EN_WIDTH 113683#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_TXDMA_EN_OFST 413684#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_TXDMA_EN_LBN 113685#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_TXDMA_EN_WIDTH 113686#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_DL_EN_OFST 413687#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_DL_EN_LBN 213688#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_DL_EN_WIDTH 113689#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_MSIX_OFST 413690#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_MSIX_LBN 013691#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_MSIX_WIDTH 213692#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_DL_OFST 413693#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_DL_LBN 213694#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_DL_WIDTH 213695#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_TX_OFST 413696#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_TX_LBN 413697#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_TX_WIDTH 213698#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_EV_OFST 413699#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_EV_LBN 613700#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_EV_WIDTH 213701#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_RX_OFST 413702#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_RX_LBN 813703#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_RX_WIDTH 213704#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_SPARE_OFST 413705#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_SPARE_LBN 1013706#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_SPARE_WIDTH 2213707 13708/* MC_CMD_SET_TLP_PROCESSING_GLOBALS_OUT msgresponse */13709#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_OUT_LEN 013710 13711 13712/***********************************/13713/* MC_CMD_SATELLITE_DOWNLOAD13714 * Download a new set of images to the satellite CPUs from the host.13715 */13716#define MC_CMD_SATELLITE_DOWNLOAD 0x9113717#undef MC_CMD_0x91_PRIVILEGE_CTG13718 13719#define MC_CMD_0x91_PRIVILEGE_CTG SRIOV_CTG_ADMIN13720 13721/* MC_CMD_SATELLITE_DOWNLOAD_IN msgrequest: The reset requirements for the CPUs13722 * are subtle, and so downloads must proceed in a number of phases.13723 *13724 * 1) PHASE_RESET with a target of TARGET_ALL and chunk ID/length of 0.13725 *13726 * 2) PHASE_IMEMS for each of the IMEM targets (target IDs 0-11). Each download13727 * may consist of multiple chunks. The final chunk (with CHUNK_ID_LAST) should13728 * be a checksum (a simple 32-bit sum) of the transferred data. An individual13729 * download may be aborted using CHUNK_ID_ABORT.13730 *13731 * 3) PHASE_VECTORS for each of the vector table targets (target IDs 12-15),13732 * similar to PHASE_IMEMS.13733 *13734 * 4) PHASE_READY with a target of TARGET_ALL and chunk ID/length of 0.13735 *13736 * After any error (a requested abort is not considered to be an error) the13737 * sequence must be restarted from PHASE_RESET.13738 */13739#define MC_CMD_SATELLITE_DOWNLOAD_IN_LENMIN 2013740#define MC_CMD_SATELLITE_DOWNLOAD_IN_LENMAX 25213741#define MC_CMD_SATELLITE_DOWNLOAD_IN_LENMAX_MCDI2 102013742#define MC_CMD_SATELLITE_DOWNLOAD_IN_LEN(num) (16+4*(num))13743#define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_NUM(len) (((len)-16)/4)13744/* Download phase. (Note: the IDLE phase is used internally and is never valid13745 * in a command from the host.)13746 */13747#define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_OFST 013748#define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_LEN 413749#define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_IDLE 0x0 /* enum */13750#define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_RESET 0x1 /* enum */13751#define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_IMEMS 0x2 /* enum */13752#define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_VECTORS 0x3 /* enum */13753#define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_READY 0x4 /* enum */13754/* Target for download. (These match the blob numbers defined in13755 * mc_flash_layout.h.)13756 */13757#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_OFST 413758#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_LEN 413759/* enum: Valid in phase 2 (PHASE_IMEMS) only */13760#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDI_TEXT 0x013761/* enum: Valid in phase 2 (PHASE_IMEMS) only */13762#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDI_TEXT 0x113763/* enum: Valid in phase 2 (PHASE_IMEMS) only */13764#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDP_TEXT 0x213765/* enum: Valid in phase 2 (PHASE_IMEMS) only */13766#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDP_TEXT 0x313767/* enum: Valid in phase 2 (PHASE_IMEMS) only */13768#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_HR_LUT 0x413769/* enum: Valid in phase 2 (PHASE_IMEMS) only */13770#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_HR_LUT_CFG 0x513771/* enum: Valid in phase 2 (PHASE_IMEMS) only */13772#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_HR_LUT 0x613773/* enum: Valid in phase 2 (PHASE_IMEMS) only */13774#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_HR_LUT_CFG 0x713775/* enum: Valid in phase 2 (PHASE_IMEMS) only */13776#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_HR_PGM 0x813777/* enum: Valid in phase 2 (PHASE_IMEMS) only */13778#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_SL_PGM 0x913779/* enum: Valid in phase 2 (PHASE_IMEMS) only */13780#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_HR_PGM 0xa13781/* enum: Valid in phase 2 (PHASE_IMEMS) only */13782#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_SL_PGM 0xb13783/* enum: Valid in phase 3 (PHASE_VECTORS) only */13784#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDI_VTBL0 0xc13785/* enum: Valid in phase 3 (PHASE_VECTORS) only */13786#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDI_VTBL0 0xd13787/* enum: Valid in phase 3 (PHASE_VECTORS) only */13788#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDI_VTBL1 0xe13789/* enum: Valid in phase 3 (PHASE_VECTORS) only */13790#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDI_VTBL1 0xf13791/* enum: Valid in phases 1 (PHASE_RESET) and 4 (PHASE_READY) only */13792#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_ALL 0xffffffff13793/* Chunk ID, or CHUNK_ID_LAST or CHUNK_ID_ABORT */13794#define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_OFST 813795#define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_LEN 413796/* enum: Last chunk, containing checksum rather than data */13797#define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_LAST 0xffffffff13798/* enum: Abort download of this item */13799#define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_ABORT 0xfffffffe13800/* Length of this chunk in bytes */13801#define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_LEN_OFST 1213802#define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_LEN_LEN 413803/* Data for this chunk */13804#define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_OFST 1613805#define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_LEN 413806#define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_MINNUM 113807#define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_MAXNUM 5913808#define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_MAXNUM_MCDI2 25113809 13810/* MC_CMD_SATELLITE_DOWNLOAD_OUT msgresponse */13811#define MC_CMD_SATELLITE_DOWNLOAD_OUT_LEN 813812/* Same as MC_CMD_ERR field, but included as 0 in success cases */13813#define MC_CMD_SATELLITE_DOWNLOAD_OUT_RESULT_OFST 013814#define MC_CMD_SATELLITE_DOWNLOAD_OUT_RESULT_LEN 413815/* Extra status information */13816#define MC_CMD_SATELLITE_DOWNLOAD_OUT_INFO_OFST 413817#define MC_CMD_SATELLITE_DOWNLOAD_OUT_INFO_LEN 413818/* enum: Code download OK, completed. */13819#define MC_CMD_SATELLITE_DOWNLOAD_OUT_OK_COMPLETE 0x013820/* enum: Code download aborted as requested. */13821#define MC_CMD_SATELLITE_DOWNLOAD_OUT_OK_ABORTED 0x113822/* enum: Code download OK so far, send next chunk. */13823#define MC_CMD_SATELLITE_DOWNLOAD_OUT_OK_NEXT_CHUNK 0x213824/* enum: Download phases out of sequence */13825#define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_PHASE 0x10013826/* enum: Bad target for this phase */13827#define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_TARGET 0x10113828/* enum: Chunk ID out of sequence */13829#define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_CHUNK_ID 0x20013830/* enum: Chunk length zero or too large */13831#define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_CHUNK_LEN 0x20113832/* enum: Checksum was incorrect */13833#define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_CHECKSUM 0x30013834 13835 13836/***********************************/13837/* MC_CMD_GET_CAPABILITIES13838 * Get device capabilities.13839 *13840 * This is supplementary to the MC_CMD_GET_BOARD_CFG command, and intended to13841 * reference inherent device capabilities as opposed to current NVRAM config.13842 */13843#define MC_CMD_GET_CAPABILITIES 0xbe13844#undef MC_CMD_0xbe_PRIVILEGE_CTG13845 13846#define MC_CMD_0xbe_PRIVILEGE_CTG SRIOV_CTG_GENERAL13847 13848/* MC_CMD_GET_CAPABILITIES_IN msgrequest */13849#define MC_CMD_GET_CAPABILITIES_IN_LEN 013850 13851/* MC_CMD_GET_CAPABILITIES_OUT msgresponse */13852#define MC_CMD_GET_CAPABILITIES_OUT_LEN 2013853/* First word of flags. */13854#define MC_CMD_GET_CAPABILITIES_OUT_FLAGS1_OFST 013855#define MC_CMD_GET_CAPABILITIES_OUT_FLAGS1_LEN 413856#define MC_CMD_GET_CAPABILITIES_OUT_VPORT_RECONFIGURE_OFST 013857#define MC_CMD_GET_CAPABILITIES_OUT_VPORT_RECONFIGURE_LBN 313858#define MC_CMD_GET_CAPABILITIES_OUT_VPORT_RECONFIGURE_WIDTH 113859#define MC_CMD_GET_CAPABILITIES_OUT_TX_STRIPING_OFST 013860#define MC_CMD_GET_CAPABILITIES_OUT_TX_STRIPING_LBN 413861#define MC_CMD_GET_CAPABILITIES_OUT_TX_STRIPING_WIDTH 113862#define MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_QUERY_OFST 013863#define MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_QUERY_LBN 513864#define MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_QUERY_WIDTH 113865#define MC_CMD_GET_CAPABILITIES_OUT_EVB_PORT_VLAN_RESTRICT_OFST 013866#define MC_CMD_GET_CAPABILITIES_OUT_EVB_PORT_VLAN_RESTRICT_LBN 613867#define MC_CMD_GET_CAPABILITIES_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 113868#define MC_CMD_GET_CAPABILITIES_OUT_DRV_ATTACH_PREBOOT_OFST 013869#define MC_CMD_GET_CAPABILITIES_OUT_DRV_ATTACH_PREBOOT_LBN 713870#define MC_CMD_GET_CAPABILITIES_OUT_DRV_ATTACH_PREBOOT_WIDTH 113871#define MC_CMD_GET_CAPABILITIES_OUT_RX_FORCE_EVENT_MERGING_OFST 013872#define MC_CMD_GET_CAPABILITIES_OUT_RX_FORCE_EVENT_MERGING_LBN 813873#define MC_CMD_GET_CAPABILITIES_OUT_RX_FORCE_EVENT_MERGING_WIDTH 113874#define MC_CMD_GET_CAPABILITIES_OUT_SET_MAC_ENHANCED_OFST 013875#define MC_CMD_GET_CAPABILITIES_OUT_SET_MAC_ENHANCED_LBN 913876#define MC_CMD_GET_CAPABILITIES_OUT_SET_MAC_ENHANCED_WIDTH 113877#define MC_CMD_GET_CAPABILITIES_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 013878#define MC_CMD_GET_CAPABILITIES_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 1013879#define MC_CMD_GET_CAPABILITIES_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 113880#define MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 013881#define MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 1113882#define MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 113883#define MC_CMD_GET_CAPABILITIES_OUT_TX_MAC_SECURITY_FILTERING_OFST 013884#define MC_CMD_GET_CAPABILITIES_OUT_TX_MAC_SECURITY_FILTERING_LBN 1213885#define MC_CMD_GET_CAPABILITIES_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 113886#define MC_CMD_GET_CAPABILITIES_OUT_ADDITIONAL_RSS_MODES_OFST 013887#define MC_CMD_GET_CAPABILITIES_OUT_ADDITIONAL_RSS_MODES_LBN 1313888#define MC_CMD_GET_CAPABILITIES_OUT_ADDITIONAL_RSS_MODES_WIDTH 113889#define MC_CMD_GET_CAPABILITIES_OUT_QBB_OFST 013890#define MC_CMD_GET_CAPABILITIES_OUT_QBB_LBN 1413891#define MC_CMD_GET_CAPABILITIES_OUT_QBB_WIDTH 113892#define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 013893#define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 1513894#define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 113895#define MC_CMD_GET_CAPABILITIES_OUT_RX_RSS_LIMITED_OFST 013896#define MC_CMD_GET_CAPABILITIES_OUT_RX_RSS_LIMITED_LBN 1613897#define MC_CMD_GET_CAPABILITIES_OUT_RX_RSS_LIMITED_WIDTH 113898#define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_OFST 013899#define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_LBN 1713900#define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_WIDTH 113901#define MC_CMD_GET_CAPABILITIES_OUT_RX_INCLUDE_FCS_OFST 013902#define MC_CMD_GET_CAPABILITIES_OUT_RX_INCLUDE_FCS_LBN 1813903#define MC_CMD_GET_CAPABILITIES_OUT_RX_INCLUDE_FCS_WIDTH 113904#define MC_CMD_GET_CAPABILITIES_OUT_TX_VLAN_INSERTION_OFST 013905#define MC_CMD_GET_CAPABILITIES_OUT_TX_VLAN_INSERTION_LBN 1913906#define MC_CMD_GET_CAPABILITIES_OUT_TX_VLAN_INSERTION_WIDTH 113907#define MC_CMD_GET_CAPABILITIES_OUT_RX_VLAN_STRIPPING_OFST 013908#define MC_CMD_GET_CAPABILITIES_OUT_RX_VLAN_STRIPPING_LBN 2013909#define MC_CMD_GET_CAPABILITIES_OUT_RX_VLAN_STRIPPING_WIDTH 113910#define MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_OFST 013911#define MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN 2113912#define MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_WIDTH 113913#define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_0_OFST 013914#define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_0_LBN 2213915#define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_0_WIDTH 113916#define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_OFST 013917#define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_LBN 2313918#define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_WIDTH 113919#define MC_CMD_GET_CAPABILITIES_OUT_RX_TIMESTAMP_OFST 013920#define MC_CMD_GET_CAPABILITIES_OUT_RX_TIMESTAMP_LBN 2413921#define MC_CMD_GET_CAPABILITIES_OUT_RX_TIMESTAMP_WIDTH 113922#define MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_OFST 013923#define MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN 2513924#define MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_WIDTH 113925#define MC_CMD_GET_CAPABILITIES_OUT_MCAST_FILTER_CHAINING_OFST 013926#define MC_CMD_GET_CAPABILITIES_OUT_MCAST_FILTER_CHAINING_LBN 2613927#define MC_CMD_GET_CAPABILITIES_OUT_MCAST_FILTER_CHAINING_WIDTH 113928#define MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_OFST 013929#define MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_LBN 2713930#define MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_WIDTH 113931#define MC_CMD_GET_CAPABILITIES_OUT_RX_DISABLE_SCATTER_OFST 013932#define MC_CMD_GET_CAPABILITIES_OUT_RX_DISABLE_SCATTER_LBN 2813933#define MC_CMD_GET_CAPABILITIES_OUT_RX_DISABLE_SCATTER_WIDTH 113934#define MC_CMD_GET_CAPABILITIES_OUT_TX_MCAST_UDP_LOOPBACK_OFST 013935#define MC_CMD_GET_CAPABILITIES_OUT_TX_MCAST_UDP_LOOPBACK_LBN 2913936#define MC_CMD_GET_CAPABILITIES_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 113937#define MC_CMD_GET_CAPABILITIES_OUT_EVB_OFST 013938#define MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN 3013939#define MC_CMD_GET_CAPABILITIES_OUT_EVB_WIDTH 113940#define MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_OFST 013941#define MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN 3113942#define MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_WIDTH 113943/* RxDPCPU firmware id. */13944#define MC_CMD_GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID_OFST 413945#define MC_CMD_GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID_LEN 213946/* enum: Standard RXDP firmware */13947#define MC_CMD_GET_CAPABILITIES_OUT_RXDP 0x013948/* enum: Low latency RXDP firmware */13949#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_LOW_LATENCY 0x113950/* enum: Packed stream RXDP firmware */13951#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_PACKED_STREAM 0x213952/* enum: Rules engine RXDP firmware */13953#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_RULES_ENGINE 0x513954/* enum: DPDK RXDP firmware */13955#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_DPDK 0x613956/* enum: BIST RXDP firmware */13957#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_BIST 0x10a13958/* enum: RXDP Test firmware image 1 */13959#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x10113960/* enum: RXDP Test firmware image 2 */13961#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x10213962/* enum: RXDP Test firmware image 3 */13963#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x10313964/* enum: RXDP Test firmware image 4 */13965#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x10413966/* enum: RXDP Test firmware image 5 */13967#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_BACKPRESSURE 0x10513968/* enum: RXDP Test firmware image 6 */13969#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_PACKET_EDITS 0x10613970/* enum: RXDP Test firmware image 7 */13971#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x10713972/* enum: RXDP Test firmware image 8 */13973#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_DISABLE_DL 0x10813974/* enum: RXDP Test firmware image 9 */13975#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b13976/* enum: RXDP Test firmware image 10 */13977#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_SLOW 0x10c13978/* TxDPCPU firmware id. */13979#define MC_CMD_GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID_OFST 613980#define MC_CMD_GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID_LEN 213981/* enum: Standard TXDP firmware */13982#define MC_CMD_GET_CAPABILITIES_OUT_TXDP 0x013983/* enum: Low latency TXDP firmware */13984#define MC_CMD_GET_CAPABILITIES_OUT_TXDP_LOW_LATENCY 0x113985/* enum: High packet rate TXDP firmware */13986#define MC_CMD_GET_CAPABILITIES_OUT_TXDP_HIGH_PACKET_RATE 0x313987/* enum: Rules engine TXDP firmware */13988#define MC_CMD_GET_CAPABILITIES_OUT_TXDP_RULES_ENGINE 0x513989/* enum: DPDK TXDP firmware */13990#define MC_CMD_GET_CAPABILITIES_OUT_TXDP_DPDK 0x613991/* enum: BIST TXDP firmware */13992#define MC_CMD_GET_CAPABILITIES_OUT_TXDP_BIST 0x12d13993/* enum: TXDP Test firmware image 1 */13994#define MC_CMD_GET_CAPABILITIES_OUT_TXDP_TEST_FW_TSO_EDIT 0x10113995/* enum: TXDP Test firmware image 2 */13996#define MC_CMD_GET_CAPABILITIES_OUT_TXDP_TEST_FW_PACKET_EDITS 0x10213997/* enum: TXDP CSR bus test firmware */13998#define MC_CMD_GET_CAPABILITIES_OUT_TXDP_TEST_FW_CSR 0x10313999#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_OFST 814000#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_LEN 214001#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_REV_OFST 814002#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_REV_LBN 014003#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_REV_WIDTH 1214004#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_TYPE_OFST 814005#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_TYPE_LBN 1214006#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_TYPE_WIDTH 414007/* enum: reserved value - do not use (may indicate alternative interpretation14008 * of REV field in future)14009 */14010#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_RESERVED 0x014011/* enum: Trivial RX PD firmware for early Huntington development (Huntington14012 * development only)14013 */14014#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_FIRST_PKT 0x114015/* enum: RX PD firmware for telemetry prototyping (Medford2 development only)14016 */14017#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x114018/* enum: RX PD firmware with approximately Siena-compatible behaviour14019 * (Huntington development only)14020 */14021#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x214022/* enum: Full featured RX PD production firmware */14023#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x314024/* enum: (deprecated original name for the FULL_FEATURED variant) */14025#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_VSWITCH 0x314026/* enum: siena_compat variant RX PD firmware using PM rather than MAC14027 * (Huntington development only)14028 */14029#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x414030/* enum: Low latency RX PD production firmware */14031#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x514032/* enum: Packed stream RX PD production firmware */14033#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x614034/* enum: RX PD firmware handling layer 2 only for high packet rate performance14035 * tests (Medford development only)14036 */14037#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x714038/* enum: Rules engine RX PD production firmware */14039#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x814040/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */14041#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_L3XUDP 0x914042/* enum: DPDK RX PD production firmware */14043#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_DPDK 0xa14044/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */14045#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe14046/* enum: RX PD firmware parsing but not filtering network overlay tunnel14047 * encapsulations (Medford development only)14048 */14049#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf14050#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_OFST 1014051#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_LEN 214052#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_REV_OFST 1014053#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_REV_LBN 014054#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_REV_WIDTH 1214055#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_TYPE_OFST 1014056#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_TYPE_LBN 1214057#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_TYPE_WIDTH 414058/* enum: reserved value - do not use (may indicate alternative interpretation14059 * of REV field in future)14060 */14061#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_RESERVED 0x014062/* enum: Trivial TX PD firmware for early Huntington development (Huntington14063 * development only)14064 */14065#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_FIRST_PKT 0x114066/* enum: TX PD firmware for telemetry prototyping (Medford2 development only)14067 */14068#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x114069/* enum: TX PD firmware with approximately Siena-compatible behaviour14070 * (Huntington development only)14071 */14072#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x214073/* enum: Full featured TX PD production firmware */14074#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x314075/* enum: (deprecated original name for the FULL_FEATURED variant) */14076#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_VSWITCH 0x314077/* enum: siena_compat variant TX PD firmware using PM rather than MAC14078 * (Huntington development only)14079 */14080#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x414081#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */14082/* enum: TX PD firmware handling layer 2 only for high packet rate performance14083 * tests (Medford development only)14084 */14085#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x714086/* enum: Rules engine TX PD production firmware */14087#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x814088/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */14089#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_L3XUDP 0x914090/* enum: DPDK TX PD production firmware */14091#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_DPDK 0xa14092/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */14093#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe14094/* Hardware capabilities of NIC */14095#define MC_CMD_GET_CAPABILITIES_OUT_HW_CAPABILITIES_OFST 1214096#define MC_CMD_GET_CAPABILITIES_OUT_HW_CAPABILITIES_LEN 414097/* Licensed capabilities */14098#define MC_CMD_GET_CAPABILITIES_OUT_LICENSE_CAPABILITIES_OFST 1614099#define MC_CMD_GET_CAPABILITIES_OUT_LICENSE_CAPABILITIES_LEN 414100 14101/* MC_CMD_GET_CAPABILITIES_V2_IN msgrequest */14102#define MC_CMD_GET_CAPABILITIES_V2_IN_LEN 014103 14104/* MC_CMD_GET_CAPABILITIES_V2_OUT msgresponse */14105#define MC_CMD_GET_CAPABILITIES_V2_OUT_LEN 7214106/* First word of flags. */14107#define MC_CMD_GET_CAPABILITIES_V2_OUT_FLAGS1_OFST 014108#define MC_CMD_GET_CAPABILITIES_V2_OUT_FLAGS1_LEN 414109#define MC_CMD_GET_CAPABILITIES_V2_OUT_VPORT_RECONFIGURE_OFST 014110#define MC_CMD_GET_CAPABILITIES_V2_OUT_VPORT_RECONFIGURE_LBN 314111#define MC_CMD_GET_CAPABILITIES_V2_OUT_VPORT_RECONFIGURE_WIDTH 114112#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_STRIPING_OFST 014113#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_STRIPING_LBN 414114#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_STRIPING_WIDTH 114115#define MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_QUERY_OFST 014116#define MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_QUERY_LBN 514117#define MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_QUERY_WIDTH 114118#define MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_PORT_VLAN_RESTRICT_OFST 014119#define MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_PORT_VLAN_RESTRICT_LBN 614120#define MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 114121#define MC_CMD_GET_CAPABILITIES_V2_OUT_DRV_ATTACH_PREBOOT_OFST 014122#define MC_CMD_GET_CAPABILITIES_V2_OUT_DRV_ATTACH_PREBOOT_LBN 714123#define MC_CMD_GET_CAPABILITIES_V2_OUT_DRV_ATTACH_PREBOOT_WIDTH 114124#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_FORCE_EVENT_MERGING_OFST 014125#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_FORCE_EVENT_MERGING_LBN 814126#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_FORCE_EVENT_MERGING_WIDTH 114127#define MC_CMD_GET_CAPABILITIES_V2_OUT_SET_MAC_ENHANCED_OFST 014128#define MC_CMD_GET_CAPABILITIES_V2_OUT_SET_MAC_ENHANCED_LBN 914129#define MC_CMD_GET_CAPABILITIES_V2_OUT_SET_MAC_ENHANCED_WIDTH 114130#define MC_CMD_GET_CAPABILITIES_V2_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 014131#define MC_CMD_GET_CAPABILITIES_V2_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 1014132#define MC_CMD_GET_CAPABILITIES_V2_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 114133#define MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 014134#define MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 1114135#define MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 114136#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_SECURITY_FILTERING_OFST 014137#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_SECURITY_FILTERING_LBN 1214138#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 114139#define MC_CMD_GET_CAPABILITIES_V2_OUT_ADDITIONAL_RSS_MODES_OFST 014140#define MC_CMD_GET_CAPABILITIES_V2_OUT_ADDITIONAL_RSS_MODES_LBN 1314141#define MC_CMD_GET_CAPABILITIES_V2_OUT_ADDITIONAL_RSS_MODES_WIDTH 114142#define MC_CMD_GET_CAPABILITIES_V2_OUT_QBB_OFST 014143#define MC_CMD_GET_CAPABILITIES_V2_OUT_QBB_LBN 1414144#define MC_CMD_GET_CAPABILITIES_V2_OUT_QBB_WIDTH 114145#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 014146#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 1514147#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 114148#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_RSS_LIMITED_OFST 014149#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_RSS_LIMITED_LBN 1614150#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_RSS_LIMITED_WIDTH 114151#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_OFST 014152#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_LBN 1714153#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_WIDTH 114154#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_INCLUDE_FCS_OFST 014155#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_INCLUDE_FCS_LBN 1814156#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_INCLUDE_FCS_WIDTH 114157#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_VLAN_INSERTION_OFST 014158#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_VLAN_INSERTION_LBN 1914159#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_VLAN_INSERTION_WIDTH 114160#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_VLAN_STRIPPING_OFST 014161#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_VLAN_STRIPPING_LBN 2014162#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_VLAN_STRIPPING_WIDTH 114163#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_OFST 014164#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_LBN 2114165#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_WIDTH 114166#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_0_OFST 014167#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_0_LBN 2214168#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_0_WIDTH 114169#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_14_OFST 014170#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_14_LBN 2314171#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_14_WIDTH 114172#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_TIMESTAMP_OFST 014173#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_TIMESTAMP_LBN 2414174#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_TIMESTAMP_WIDTH 114175#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_BATCHING_OFST 014176#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_BATCHING_LBN 2514177#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_BATCHING_WIDTH 114178#define MC_CMD_GET_CAPABILITIES_V2_OUT_MCAST_FILTER_CHAINING_OFST 014179#define MC_CMD_GET_CAPABILITIES_V2_OUT_MCAST_FILTER_CHAINING_LBN 2614180#define MC_CMD_GET_CAPABILITIES_V2_OUT_MCAST_FILTER_CHAINING_WIDTH 114181#define MC_CMD_GET_CAPABILITIES_V2_OUT_PM_AND_RXDP_COUNTERS_OFST 014182#define MC_CMD_GET_CAPABILITIES_V2_OUT_PM_AND_RXDP_COUNTERS_LBN 2714183#define MC_CMD_GET_CAPABILITIES_V2_OUT_PM_AND_RXDP_COUNTERS_WIDTH 114184#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DISABLE_SCATTER_OFST 014185#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DISABLE_SCATTER_LBN 2814186#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DISABLE_SCATTER_WIDTH 114187#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MCAST_UDP_LOOPBACK_OFST 014188#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MCAST_UDP_LOOPBACK_LBN 2914189#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 114190#define MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_OFST 014191#define MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_LBN 3014192#define MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_WIDTH 114193#define MC_CMD_GET_CAPABILITIES_V2_OUT_VXLAN_NVGRE_OFST 014194#define MC_CMD_GET_CAPABILITIES_V2_OUT_VXLAN_NVGRE_LBN 3114195#define MC_CMD_GET_CAPABILITIES_V2_OUT_VXLAN_NVGRE_WIDTH 114196/* RxDPCPU firmware id. */14197#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DPCPU_FW_ID_OFST 414198#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DPCPU_FW_ID_LEN 214199/* enum: Standard RXDP firmware */14200#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP 0x014201/* enum: Low latency RXDP firmware */14202#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_LOW_LATENCY 0x114203/* enum: Packed stream RXDP firmware */14204#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_PACKED_STREAM 0x214205/* enum: Rules engine RXDP firmware */14206#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_RULES_ENGINE 0x514207/* enum: DPDK RXDP firmware */14208#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_DPDK 0x614209/* enum: BIST RXDP firmware */14210#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_BIST 0x10a14211/* enum: RXDP Test firmware image 1 */14212#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x10114213/* enum: RXDP Test firmware image 2 */14214#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x10214215/* enum: RXDP Test firmware image 3 */14216#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x10314217/* enum: RXDP Test firmware image 4 */14218#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x10414219/* enum: RXDP Test firmware image 5 */14220#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_BACKPRESSURE 0x10514221/* enum: RXDP Test firmware image 6 */14222#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_PACKET_EDITS 0x10614223/* enum: RXDP Test firmware image 7 */14224#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x10714225/* enum: RXDP Test firmware image 8 */14226#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_DISABLE_DL 0x10814227/* enum: RXDP Test firmware image 9 */14228#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b14229/* enum: RXDP Test firmware image 10 */14230#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_SLOW 0x10c14231/* TxDPCPU firmware id. */14232#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_DPCPU_FW_ID_OFST 614233#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_DPCPU_FW_ID_LEN 214234/* enum: Standard TXDP firmware */14235#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP 0x014236/* enum: Low latency TXDP firmware */14237#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_LOW_LATENCY 0x114238/* enum: High packet rate TXDP firmware */14239#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_HIGH_PACKET_RATE 0x314240/* enum: Rules engine TXDP firmware */14241#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_RULES_ENGINE 0x514242/* enum: DPDK TXDP firmware */14243#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_DPDK 0x614244/* enum: BIST TXDP firmware */14245#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_BIST 0x12d14246/* enum: TXDP Test firmware image 1 */14247#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_TEST_FW_TSO_EDIT 0x10114248/* enum: TXDP Test firmware image 2 */14249#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_TEST_FW_PACKET_EDITS 0x10214250/* enum: TXDP CSR bus test firmware */14251#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_TEST_FW_CSR 0x10314252#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_OFST 814253#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_LEN 214254#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_REV_OFST 814255#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_REV_LBN 014256#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_REV_WIDTH 1214257#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_TYPE_OFST 814258#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_TYPE_LBN 1214259#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_TYPE_WIDTH 414260/* enum: reserved value - do not use (may indicate alternative interpretation14261 * of REV field in future)14262 */14263#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_RESERVED 0x014264/* enum: Trivial RX PD firmware for early Huntington development (Huntington14265 * development only)14266 */14267#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_FIRST_PKT 0x114268/* enum: RX PD firmware for telemetry prototyping (Medford2 development only)14269 */14270#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x114271/* enum: RX PD firmware with approximately Siena-compatible behaviour14272 * (Huntington development only)14273 */14274#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x214275/* enum: Full featured RX PD production firmware */14276#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x314277/* enum: (deprecated original name for the FULL_FEATURED variant) */14278#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_VSWITCH 0x314279/* enum: siena_compat variant RX PD firmware using PM rather than MAC14280 * (Huntington development only)14281 */14282#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x414283/* enum: Low latency RX PD production firmware */14284#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x514285/* enum: Packed stream RX PD production firmware */14286#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x614287/* enum: RX PD firmware handling layer 2 only for high packet rate performance14288 * tests (Medford development only)14289 */14290#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x714291/* enum: Rules engine RX PD production firmware */14292#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x814293/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */14294#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_L3XUDP 0x914295/* enum: DPDK RX PD production firmware */14296#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_DPDK 0xa14297/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */14298#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe14299/* enum: RX PD firmware parsing but not filtering network overlay tunnel14300 * encapsulations (Medford development only)14301 */14302#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf14303#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_OFST 1014304#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_LEN 214305#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_REV_OFST 1014306#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_REV_LBN 014307#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_REV_WIDTH 1214308#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_TYPE_OFST 1014309#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_TYPE_LBN 1214310#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_TYPE_WIDTH 414311/* enum: reserved value - do not use (may indicate alternative interpretation14312 * of REV field in future)14313 */14314#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_RESERVED 0x014315/* enum: Trivial TX PD firmware for early Huntington development (Huntington14316 * development only)14317 */14318#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_FIRST_PKT 0x114319/* enum: TX PD firmware for telemetry prototyping (Medford2 development only)14320 */14321#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x114322/* enum: TX PD firmware with approximately Siena-compatible behaviour14323 * (Huntington development only)14324 */14325#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x214326/* enum: Full featured TX PD production firmware */14327#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x314328/* enum: (deprecated original name for the FULL_FEATURED variant) */14329#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_VSWITCH 0x314330/* enum: siena_compat variant TX PD firmware using PM rather than MAC14331 * (Huntington development only)14332 */14333#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x414334#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */14335/* enum: TX PD firmware handling layer 2 only for high packet rate performance14336 * tests (Medford development only)14337 */14338#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x714339/* enum: Rules engine TX PD production firmware */14340#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x814341/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */14342#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_L3XUDP 0x914343/* enum: DPDK TX PD production firmware */14344#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_DPDK 0xa14345/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */14346#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe14347/* Hardware capabilities of NIC */14348#define MC_CMD_GET_CAPABILITIES_V2_OUT_HW_CAPABILITIES_OFST 1214349#define MC_CMD_GET_CAPABILITIES_V2_OUT_HW_CAPABILITIES_LEN 414350/* Licensed capabilities */14351#define MC_CMD_GET_CAPABILITIES_V2_OUT_LICENSE_CAPABILITIES_OFST 1614352#define MC_CMD_GET_CAPABILITIES_V2_OUT_LICENSE_CAPABILITIES_LEN 414353/* Second word of flags. Not present on older firmware (check the length). */14354#define MC_CMD_GET_CAPABILITIES_V2_OUT_FLAGS2_OFST 2014355#define MC_CMD_GET_CAPABILITIES_V2_OUT_FLAGS2_LEN 414356#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_OFST 2014357#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_LBN 014358#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_WIDTH 114359#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_ENCAP_OFST 2014360#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_ENCAP_LBN 114361#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_ENCAP_WIDTH 114362#define MC_CMD_GET_CAPABILITIES_V2_OUT_EVQ_TIMER_CTRL_OFST 2014363#define MC_CMD_GET_CAPABILITIES_V2_OUT_EVQ_TIMER_CTRL_LBN 214364#define MC_CMD_GET_CAPABILITIES_V2_OUT_EVQ_TIMER_CTRL_WIDTH 114365#define MC_CMD_GET_CAPABILITIES_V2_OUT_EVENT_CUT_THROUGH_OFST 2014366#define MC_CMD_GET_CAPABILITIES_V2_OUT_EVENT_CUT_THROUGH_LBN 314367#define MC_CMD_GET_CAPABILITIES_V2_OUT_EVENT_CUT_THROUGH_WIDTH 114368#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_CUT_THROUGH_OFST 2014369#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_CUT_THROUGH_LBN 414370#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_CUT_THROUGH_WIDTH 114371#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_VFIFO_ULL_MODE_OFST 2014372#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_VFIFO_ULL_MODE_LBN 514373#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_VFIFO_ULL_MODE_WIDTH 114374#define MC_CMD_GET_CAPABILITIES_V2_OUT_MAC_STATS_40G_TX_SIZE_BINS_OFST 2014375#define MC_CMD_GET_CAPABILITIES_V2_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 614376#define MC_CMD_GET_CAPABILITIES_V2_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 114377#define MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_EVQ_TYPE_SUPPORTED_OFST 2014378#define MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_EVQ_TYPE_SUPPORTED_LBN 714379#define MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_EVQ_TYPE_SUPPORTED_WIDTH 114380#define MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_EVQ_V2_OFST 2014381#define MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_EVQ_V2_LBN 714382#define MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_EVQ_V2_WIDTH 114383#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_TIMESTAMPING_OFST 2014384#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_TIMESTAMPING_LBN 814385#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_TIMESTAMPING_WIDTH 114386#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TIMESTAMP_OFST 2014387#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TIMESTAMP_LBN 914388#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TIMESTAMP_WIDTH 114389#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_SNIFF_OFST 2014390#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_SNIFF_LBN 1014391#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_SNIFF_WIDTH 114392#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_SNIFF_OFST 2014393#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_SNIFF_LBN 1114394#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_SNIFF_WIDTH 114395#define MC_CMD_GET_CAPABILITIES_V2_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_OFST 2014396#define MC_CMD_GET_CAPABILITIES_V2_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_LBN 1214397#define MC_CMD_GET_CAPABILITIES_V2_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 114398#define MC_CMD_GET_CAPABILITIES_V2_OUT_MCDI_BACKGROUND_OFST 2014399#define MC_CMD_GET_CAPABILITIES_V2_OUT_MCDI_BACKGROUND_LBN 1314400#define MC_CMD_GET_CAPABILITIES_V2_OUT_MCDI_BACKGROUND_WIDTH 114401#define MC_CMD_GET_CAPABILITIES_V2_OUT_MCDI_DB_RETURN_OFST 2014402#define MC_CMD_GET_CAPABILITIES_V2_OUT_MCDI_DB_RETURN_LBN 1414403#define MC_CMD_GET_CAPABILITIES_V2_OUT_MCDI_DB_RETURN_WIDTH 114404#define MC_CMD_GET_CAPABILITIES_V2_OUT_CTPIO_OFST 2014405#define MC_CMD_GET_CAPABILITIES_V2_OUT_CTPIO_LBN 1514406#define MC_CMD_GET_CAPABILITIES_V2_OUT_CTPIO_WIDTH 114407#define MC_CMD_GET_CAPABILITIES_V2_OUT_TSA_SUPPORT_OFST 2014408#define MC_CMD_GET_CAPABILITIES_V2_OUT_TSA_SUPPORT_LBN 1614409#define MC_CMD_GET_CAPABILITIES_V2_OUT_TSA_SUPPORT_WIDTH 114410#define MC_CMD_GET_CAPABILITIES_V2_OUT_TSA_BOUND_OFST 2014411#define MC_CMD_GET_CAPABILITIES_V2_OUT_TSA_BOUND_LBN 1714412#define MC_CMD_GET_CAPABILITIES_V2_OUT_TSA_BOUND_WIDTH 114413#define MC_CMD_GET_CAPABILITIES_V2_OUT_SF_ADAPTER_AUTHENTICATION_OFST 2014414#define MC_CMD_GET_CAPABILITIES_V2_OUT_SF_ADAPTER_AUTHENTICATION_LBN 1814415#define MC_CMD_GET_CAPABILITIES_V2_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 114416#define MC_CMD_GET_CAPABILITIES_V2_OUT_FILTER_ACTION_FLAG_OFST 2014417#define MC_CMD_GET_CAPABILITIES_V2_OUT_FILTER_ACTION_FLAG_LBN 1914418#define MC_CMD_GET_CAPABILITIES_V2_OUT_FILTER_ACTION_FLAG_WIDTH 114419#define MC_CMD_GET_CAPABILITIES_V2_OUT_FILTER_ACTION_MARK_OFST 2014420#define MC_CMD_GET_CAPABILITIES_V2_OUT_FILTER_ACTION_MARK_LBN 2014421#define MC_CMD_GET_CAPABILITIES_V2_OUT_FILTER_ACTION_MARK_WIDTH 114422#define MC_CMD_GET_CAPABILITIES_V2_OUT_EQUAL_STRIDE_SUPER_BUFFER_OFST 2014423#define MC_CMD_GET_CAPABILITIES_V2_OUT_EQUAL_STRIDE_SUPER_BUFFER_LBN 2114424#define MC_CMD_GET_CAPABILITIES_V2_OUT_EQUAL_STRIDE_SUPER_BUFFER_WIDTH 114425#define MC_CMD_GET_CAPABILITIES_V2_OUT_EQUAL_STRIDE_PACKED_STREAM_OFST 2014426#define MC_CMD_GET_CAPABILITIES_V2_OUT_EQUAL_STRIDE_PACKED_STREAM_LBN 2114427#define MC_CMD_GET_CAPABILITIES_V2_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 114428#define MC_CMD_GET_CAPABILITIES_V2_OUT_L3XUDP_SUPPORT_OFST 2014429#define MC_CMD_GET_CAPABILITIES_V2_OUT_L3XUDP_SUPPORT_LBN 2214430#define MC_CMD_GET_CAPABILITIES_V2_OUT_L3XUDP_SUPPORT_WIDTH 114431#define MC_CMD_GET_CAPABILITIES_V2_OUT_FW_SUBVARIANT_NO_TX_CSUM_OFST 2014432#define MC_CMD_GET_CAPABILITIES_V2_OUT_FW_SUBVARIANT_NO_TX_CSUM_LBN 2314433#define MC_CMD_GET_CAPABILITIES_V2_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 114434#define MC_CMD_GET_CAPABILITIES_V2_OUT_VI_SPREADING_OFST 2014435#define MC_CMD_GET_CAPABILITIES_V2_OUT_VI_SPREADING_LBN 2414436#define MC_CMD_GET_CAPABILITIES_V2_OUT_VI_SPREADING_WIDTH 114437#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_HLB_IDLE_OFST 2014438#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_HLB_IDLE_LBN 2514439#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_HLB_IDLE_WIDTH 114440#define MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_RXQ_NO_CONT_EV_OFST 2014441#define MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_RXQ_NO_CONT_EV_LBN 2614442#define MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_RXQ_NO_CONT_EV_WIDTH 114443#define MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_RXQ_WITH_BUFFER_SIZE_OFST 2014444#define MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_RXQ_WITH_BUFFER_SIZE_LBN 2714445#define MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_RXQ_WITH_BUFFER_SIZE_WIDTH 114446#define MC_CMD_GET_CAPABILITIES_V2_OUT_BUNDLE_UPDATE_OFST 2014447#define MC_CMD_GET_CAPABILITIES_V2_OUT_BUNDLE_UPDATE_LBN 2814448#define MC_CMD_GET_CAPABILITIES_V2_OUT_BUNDLE_UPDATE_WIDTH 114449#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V3_OFST 2014450#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V3_LBN 2914451#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V3_WIDTH 114452#define MC_CMD_GET_CAPABILITIES_V2_OUT_DYNAMIC_SENSORS_OFST 2014453#define MC_CMD_GET_CAPABILITIES_V2_OUT_DYNAMIC_SENSORS_LBN 3014454#define MC_CMD_GET_CAPABILITIES_V2_OUT_DYNAMIC_SENSORS_WIDTH 114455#define MC_CMD_GET_CAPABILITIES_V2_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_OFST 2014456#define MC_CMD_GET_CAPABILITIES_V2_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_LBN 3114457#define MC_CMD_GET_CAPABILITIES_V2_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_WIDTH 114458/* Number of FATSOv2 contexts per datapath supported by this NIC (when14459 * TX_TSO_V2 == 1). Not present on older firmware (check the length).14460 */14461#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_N_CONTEXTS_OFST 2414462#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_N_CONTEXTS_LEN 214463/* One byte per PF containing the number of the external port assigned to this14464 * PF, indexed by PF number. Special values indicate that a PF is either not14465 * present or not assigned.14466 */14467#define MC_CMD_GET_CAPABILITIES_V2_OUT_PFS_TO_PORTS_ASSIGNMENT_OFST 2614468#define MC_CMD_GET_CAPABILITIES_V2_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 114469#define MC_CMD_GET_CAPABILITIES_V2_OUT_PFS_TO_PORTS_ASSIGNMENT_NUM 1614470/* enum: The caller is not permitted to access information on this PF. */14471#define MC_CMD_GET_CAPABILITIES_V2_OUT_ACCESS_NOT_PERMITTED 0xff14472/* enum: PF does not exist. */14473#define MC_CMD_GET_CAPABILITIES_V2_OUT_PF_NOT_PRESENT 0xfe14474/* enum: PF does exist but is not assigned to any external port. */14475#define MC_CMD_GET_CAPABILITIES_V2_OUT_PF_NOT_ASSIGNED 0xfd14476/* enum: This value indicates that PF is assigned, but it cannot be expressed14477 * in this field. It is intended for a possible future situation where a more14478 * complex scheme of PFs to ports mapping is being used. The future driver14479 * should look for a new field supporting the new scheme. The current/old14480 * driver should treat this value as PF_NOT_ASSIGNED.14481 */14482#define MC_CMD_GET_CAPABILITIES_V2_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc14483/* One byte per PF containing the number of its VFs, indexed by PF number. A14484 * special value indicates that a PF is not present.14485 */14486#define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VFS_PER_PF_OFST 4214487#define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VFS_PER_PF_LEN 114488#define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VFS_PER_PF_NUM 1614489/* enum: The caller is not permitted to access information on this PF. */14490/* MC_CMD_GET_CAPABILITIES_V2_OUT_ACCESS_NOT_PERMITTED 0xff */14491/* enum: PF does not exist. */14492/* MC_CMD_GET_CAPABILITIES_V2_OUT_PF_NOT_PRESENT 0xfe */14493/* Number of VIs available for each external port */14494#define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VIS_PER_PORT_OFST 5814495#define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VIS_PER_PORT_LEN 214496#define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VIS_PER_PORT_NUM 414497/* Size of RX descriptor cache expressed as binary logarithm The actual size14498 * equals (2 ^ RX_DESC_CACHE_SIZE)14499 */14500#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DESC_CACHE_SIZE_OFST 6614501#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DESC_CACHE_SIZE_LEN 114502/* Size of TX descriptor cache expressed as binary logarithm The actual size14503 * equals (2 ^ TX_DESC_CACHE_SIZE)14504 */14505#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_DESC_CACHE_SIZE_OFST 6714506#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_DESC_CACHE_SIZE_LEN 114507/* Total number of available PIO buffers */14508#define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_PIO_BUFFS_OFST 6814509#define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_PIO_BUFFS_LEN 214510/* Size of a single PIO buffer */14511#define MC_CMD_GET_CAPABILITIES_V2_OUT_SIZE_PIO_BUFF_OFST 7014512#define MC_CMD_GET_CAPABILITIES_V2_OUT_SIZE_PIO_BUFF_LEN 214513 14514/* MC_CMD_GET_CAPABILITIES_V3_OUT msgresponse */14515#define MC_CMD_GET_CAPABILITIES_V3_OUT_LEN 7614516/* First word of flags. */14517#define MC_CMD_GET_CAPABILITIES_V3_OUT_FLAGS1_OFST 014518#define MC_CMD_GET_CAPABILITIES_V3_OUT_FLAGS1_LEN 414519#define MC_CMD_GET_CAPABILITIES_V3_OUT_VPORT_RECONFIGURE_OFST 014520#define MC_CMD_GET_CAPABILITIES_V3_OUT_VPORT_RECONFIGURE_LBN 314521#define MC_CMD_GET_CAPABILITIES_V3_OUT_VPORT_RECONFIGURE_WIDTH 114522#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_STRIPING_OFST 014523#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_STRIPING_LBN 414524#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_STRIPING_WIDTH 114525#define MC_CMD_GET_CAPABILITIES_V3_OUT_VADAPTOR_QUERY_OFST 014526#define MC_CMD_GET_CAPABILITIES_V3_OUT_VADAPTOR_QUERY_LBN 514527#define MC_CMD_GET_CAPABILITIES_V3_OUT_VADAPTOR_QUERY_WIDTH 114528#define MC_CMD_GET_CAPABILITIES_V3_OUT_EVB_PORT_VLAN_RESTRICT_OFST 014529#define MC_CMD_GET_CAPABILITIES_V3_OUT_EVB_PORT_VLAN_RESTRICT_LBN 614530#define MC_CMD_GET_CAPABILITIES_V3_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 114531#define MC_CMD_GET_CAPABILITIES_V3_OUT_DRV_ATTACH_PREBOOT_OFST 014532#define MC_CMD_GET_CAPABILITIES_V3_OUT_DRV_ATTACH_PREBOOT_LBN 714533#define MC_CMD_GET_CAPABILITIES_V3_OUT_DRV_ATTACH_PREBOOT_WIDTH 114534#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_FORCE_EVENT_MERGING_OFST 014535#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_FORCE_EVENT_MERGING_LBN 814536#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_FORCE_EVENT_MERGING_WIDTH 114537#define MC_CMD_GET_CAPABILITIES_V3_OUT_SET_MAC_ENHANCED_OFST 014538#define MC_CMD_GET_CAPABILITIES_V3_OUT_SET_MAC_ENHANCED_LBN 914539#define MC_CMD_GET_CAPABILITIES_V3_OUT_SET_MAC_ENHANCED_WIDTH 114540#define MC_CMD_GET_CAPABILITIES_V3_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 014541#define MC_CMD_GET_CAPABILITIES_V3_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 1014542#define MC_CMD_GET_CAPABILITIES_V3_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 114543#define MC_CMD_GET_CAPABILITIES_V3_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 014544#define MC_CMD_GET_CAPABILITIES_V3_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 1114545#define MC_CMD_GET_CAPABILITIES_V3_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 114546#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MAC_SECURITY_FILTERING_OFST 014547#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MAC_SECURITY_FILTERING_LBN 1214548#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 114549#define MC_CMD_GET_CAPABILITIES_V3_OUT_ADDITIONAL_RSS_MODES_OFST 014550#define MC_CMD_GET_CAPABILITIES_V3_OUT_ADDITIONAL_RSS_MODES_LBN 1314551#define MC_CMD_GET_CAPABILITIES_V3_OUT_ADDITIONAL_RSS_MODES_WIDTH 114552#define MC_CMD_GET_CAPABILITIES_V3_OUT_QBB_OFST 014553#define MC_CMD_GET_CAPABILITIES_V3_OUT_QBB_LBN 1414554#define MC_CMD_GET_CAPABILITIES_V3_OUT_QBB_WIDTH 114555#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 014556#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 1514557#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 114558#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_RSS_LIMITED_OFST 014559#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_RSS_LIMITED_LBN 1614560#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_RSS_LIMITED_WIDTH 114561#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PACKED_STREAM_OFST 014562#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PACKED_STREAM_LBN 1714563#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PACKED_STREAM_WIDTH 114564#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_INCLUDE_FCS_OFST 014565#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_INCLUDE_FCS_LBN 1814566#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_INCLUDE_FCS_WIDTH 114567#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_VLAN_INSERTION_OFST 014568#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_VLAN_INSERTION_LBN 1914569#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_VLAN_INSERTION_WIDTH 114570#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_VLAN_STRIPPING_OFST 014571#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_VLAN_STRIPPING_LBN 2014572#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_VLAN_STRIPPING_WIDTH 114573#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_OFST 014574#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_LBN 2114575#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_WIDTH 114576#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PREFIX_LEN_0_OFST 014577#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PREFIX_LEN_0_LBN 2214578#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PREFIX_LEN_0_WIDTH 114579#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PREFIX_LEN_14_OFST 014580#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PREFIX_LEN_14_LBN 2314581#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PREFIX_LEN_14_WIDTH 114582#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_TIMESTAMP_OFST 014583#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_TIMESTAMP_LBN 2414584#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_TIMESTAMP_WIDTH 114585#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_BATCHING_OFST 014586#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_BATCHING_LBN 2514587#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_BATCHING_WIDTH 114588#define MC_CMD_GET_CAPABILITIES_V3_OUT_MCAST_FILTER_CHAINING_OFST 014589#define MC_CMD_GET_CAPABILITIES_V3_OUT_MCAST_FILTER_CHAINING_LBN 2614590#define MC_CMD_GET_CAPABILITIES_V3_OUT_MCAST_FILTER_CHAINING_WIDTH 114591#define MC_CMD_GET_CAPABILITIES_V3_OUT_PM_AND_RXDP_COUNTERS_OFST 014592#define MC_CMD_GET_CAPABILITIES_V3_OUT_PM_AND_RXDP_COUNTERS_LBN 2714593#define MC_CMD_GET_CAPABILITIES_V3_OUT_PM_AND_RXDP_COUNTERS_WIDTH 114594#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DISABLE_SCATTER_OFST 014595#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DISABLE_SCATTER_LBN 2814596#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DISABLE_SCATTER_WIDTH 114597#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MCAST_UDP_LOOPBACK_OFST 014598#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MCAST_UDP_LOOPBACK_LBN 2914599#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 114600#define MC_CMD_GET_CAPABILITIES_V3_OUT_EVB_OFST 014601#define MC_CMD_GET_CAPABILITIES_V3_OUT_EVB_LBN 3014602#define MC_CMD_GET_CAPABILITIES_V3_OUT_EVB_WIDTH 114603#define MC_CMD_GET_CAPABILITIES_V3_OUT_VXLAN_NVGRE_OFST 014604#define MC_CMD_GET_CAPABILITIES_V3_OUT_VXLAN_NVGRE_LBN 3114605#define MC_CMD_GET_CAPABILITIES_V3_OUT_VXLAN_NVGRE_WIDTH 114606/* RxDPCPU firmware id. */14607#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DPCPU_FW_ID_OFST 414608#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DPCPU_FW_ID_LEN 214609/* enum: Standard RXDP firmware */14610#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP 0x014611/* enum: Low latency RXDP firmware */14612#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_LOW_LATENCY 0x114613/* enum: Packed stream RXDP firmware */14614#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_PACKED_STREAM 0x214615/* enum: Rules engine RXDP firmware */14616#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_RULES_ENGINE 0x514617/* enum: DPDK RXDP firmware */14618#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_DPDK 0x614619/* enum: BIST RXDP firmware */14620#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_BIST 0x10a14621/* enum: RXDP Test firmware image 1 */14622#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x10114623/* enum: RXDP Test firmware image 2 */14624#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x10214625/* enum: RXDP Test firmware image 3 */14626#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x10314627/* enum: RXDP Test firmware image 4 */14628#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x10414629/* enum: RXDP Test firmware image 5 */14630#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_BACKPRESSURE 0x10514631/* enum: RXDP Test firmware image 6 */14632#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_PACKET_EDITS 0x10614633/* enum: RXDP Test firmware image 7 */14634#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x10714635/* enum: RXDP Test firmware image 8 */14636#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_DISABLE_DL 0x10814637/* enum: RXDP Test firmware image 9 */14638#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b14639/* enum: RXDP Test firmware image 10 */14640#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_SLOW 0x10c14641/* TxDPCPU firmware id. */14642#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_DPCPU_FW_ID_OFST 614643#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_DPCPU_FW_ID_LEN 214644/* enum: Standard TXDP firmware */14645#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP 0x014646/* enum: Low latency TXDP firmware */14647#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_LOW_LATENCY 0x114648/* enum: High packet rate TXDP firmware */14649#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_HIGH_PACKET_RATE 0x314650/* enum: Rules engine TXDP firmware */14651#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_RULES_ENGINE 0x514652/* enum: DPDK TXDP firmware */14653#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_DPDK 0x614654/* enum: BIST TXDP firmware */14655#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_BIST 0x12d14656/* enum: TXDP Test firmware image 1 */14657#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_TEST_FW_TSO_EDIT 0x10114658/* enum: TXDP Test firmware image 2 */14659#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_TEST_FW_PACKET_EDITS 0x10214660/* enum: TXDP CSR bus test firmware */14661#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_TEST_FW_CSR 0x10314662#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_OFST 814663#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_LEN 214664#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_REV_OFST 814665#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_REV_LBN 014666#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_REV_WIDTH 1214667#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_TYPE_OFST 814668#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_TYPE_LBN 1214669#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_TYPE_WIDTH 414670/* enum: reserved value - do not use (may indicate alternative interpretation14671 * of REV field in future)14672 */14673#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_RESERVED 0x014674/* enum: Trivial RX PD firmware for early Huntington development (Huntington14675 * development only)14676 */14677#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_FIRST_PKT 0x114678/* enum: RX PD firmware for telemetry prototyping (Medford2 development only)14679 */14680#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x114681/* enum: RX PD firmware with approximately Siena-compatible behaviour14682 * (Huntington development only)14683 */14684#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x214685/* enum: Full featured RX PD production firmware */14686#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x314687/* enum: (deprecated original name for the FULL_FEATURED variant) */14688#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_VSWITCH 0x314689/* enum: siena_compat variant RX PD firmware using PM rather than MAC14690 * (Huntington development only)14691 */14692#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x414693/* enum: Low latency RX PD production firmware */14694#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x514695/* enum: Packed stream RX PD production firmware */14696#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x614697/* enum: RX PD firmware handling layer 2 only for high packet rate performance14698 * tests (Medford development only)14699 */14700#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x714701/* enum: Rules engine RX PD production firmware */14702#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x814703/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */14704#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_L3XUDP 0x914705/* enum: DPDK RX PD production firmware */14706#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_DPDK 0xa14707/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */14708#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe14709/* enum: RX PD firmware parsing but not filtering network overlay tunnel14710 * encapsulations (Medford development only)14711 */14712#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf14713#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_OFST 1014714#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_LEN 214715#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_REV_OFST 1014716#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_REV_LBN 014717#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_REV_WIDTH 1214718#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_TYPE_OFST 1014719#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_TYPE_LBN 1214720#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_TYPE_WIDTH 414721/* enum: reserved value - do not use (may indicate alternative interpretation14722 * of REV field in future)14723 */14724#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_RESERVED 0x014725/* enum: Trivial TX PD firmware for early Huntington development (Huntington14726 * development only)14727 */14728#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_FIRST_PKT 0x114729/* enum: TX PD firmware for telemetry prototyping (Medford2 development only)14730 */14731#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x114732/* enum: TX PD firmware with approximately Siena-compatible behaviour14733 * (Huntington development only)14734 */14735#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x214736/* enum: Full featured TX PD production firmware */14737#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x314738/* enum: (deprecated original name for the FULL_FEATURED variant) */14739#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_VSWITCH 0x314740/* enum: siena_compat variant TX PD firmware using PM rather than MAC14741 * (Huntington development only)14742 */14743#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x414744#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */14745/* enum: TX PD firmware handling layer 2 only for high packet rate performance14746 * tests (Medford development only)14747 */14748#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x714749/* enum: Rules engine TX PD production firmware */14750#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x814751/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */14752#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_L3XUDP 0x914753/* enum: DPDK TX PD production firmware */14754#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_DPDK 0xa14755/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */14756#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe14757/* Hardware capabilities of NIC */14758#define MC_CMD_GET_CAPABILITIES_V3_OUT_HW_CAPABILITIES_OFST 1214759#define MC_CMD_GET_CAPABILITIES_V3_OUT_HW_CAPABILITIES_LEN 414760/* Licensed capabilities */14761#define MC_CMD_GET_CAPABILITIES_V3_OUT_LICENSE_CAPABILITIES_OFST 1614762#define MC_CMD_GET_CAPABILITIES_V3_OUT_LICENSE_CAPABILITIES_LEN 414763/* Second word of flags. Not present on older firmware (check the length). */14764#define MC_CMD_GET_CAPABILITIES_V3_OUT_FLAGS2_OFST 2014765#define MC_CMD_GET_CAPABILITIES_V3_OUT_FLAGS2_LEN 414766#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_OFST 2014767#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_LBN 014768#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_WIDTH 114769#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_ENCAP_OFST 2014770#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_ENCAP_LBN 114771#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_ENCAP_WIDTH 114772#define MC_CMD_GET_CAPABILITIES_V3_OUT_EVQ_TIMER_CTRL_OFST 2014773#define MC_CMD_GET_CAPABILITIES_V3_OUT_EVQ_TIMER_CTRL_LBN 214774#define MC_CMD_GET_CAPABILITIES_V3_OUT_EVQ_TIMER_CTRL_WIDTH 114775#define MC_CMD_GET_CAPABILITIES_V3_OUT_EVENT_CUT_THROUGH_OFST 2014776#define MC_CMD_GET_CAPABILITIES_V3_OUT_EVENT_CUT_THROUGH_LBN 314777#define MC_CMD_GET_CAPABILITIES_V3_OUT_EVENT_CUT_THROUGH_WIDTH 114778#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_CUT_THROUGH_OFST 2014779#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_CUT_THROUGH_LBN 414780#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_CUT_THROUGH_WIDTH 114781#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_VFIFO_ULL_MODE_OFST 2014782#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_VFIFO_ULL_MODE_LBN 514783#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_VFIFO_ULL_MODE_WIDTH 114784#define MC_CMD_GET_CAPABILITIES_V3_OUT_MAC_STATS_40G_TX_SIZE_BINS_OFST 2014785#define MC_CMD_GET_CAPABILITIES_V3_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 614786#define MC_CMD_GET_CAPABILITIES_V3_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 114787#define MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_EVQ_TYPE_SUPPORTED_OFST 2014788#define MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_EVQ_TYPE_SUPPORTED_LBN 714789#define MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_EVQ_TYPE_SUPPORTED_WIDTH 114790#define MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_EVQ_V2_OFST 2014791#define MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_EVQ_V2_LBN 714792#define MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_EVQ_V2_WIDTH 114793#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MAC_TIMESTAMPING_OFST 2014794#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MAC_TIMESTAMPING_LBN 814795#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MAC_TIMESTAMPING_WIDTH 114796#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TIMESTAMP_OFST 2014797#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TIMESTAMP_LBN 914798#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TIMESTAMP_WIDTH 114799#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_SNIFF_OFST 2014800#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_SNIFF_LBN 1014801#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_SNIFF_WIDTH 114802#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_SNIFF_OFST 2014803#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_SNIFF_LBN 1114804#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_SNIFF_WIDTH 114805#define MC_CMD_GET_CAPABILITIES_V3_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_OFST 2014806#define MC_CMD_GET_CAPABILITIES_V3_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_LBN 1214807#define MC_CMD_GET_CAPABILITIES_V3_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 114808#define MC_CMD_GET_CAPABILITIES_V3_OUT_MCDI_BACKGROUND_OFST 2014809#define MC_CMD_GET_CAPABILITIES_V3_OUT_MCDI_BACKGROUND_LBN 1314810#define MC_CMD_GET_CAPABILITIES_V3_OUT_MCDI_BACKGROUND_WIDTH 114811#define MC_CMD_GET_CAPABILITIES_V3_OUT_MCDI_DB_RETURN_OFST 2014812#define MC_CMD_GET_CAPABILITIES_V3_OUT_MCDI_DB_RETURN_LBN 1414813#define MC_CMD_GET_CAPABILITIES_V3_OUT_MCDI_DB_RETURN_WIDTH 114814#define MC_CMD_GET_CAPABILITIES_V3_OUT_CTPIO_OFST 2014815#define MC_CMD_GET_CAPABILITIES_V3_OUT_CTPIO_LBN 1514816#define MC_CMD_GET_CAPABILITIES_V3_OUT_CTPIO_WIDTH 114817#define MC_CMD_GET_CAPABILITIES_V3_OUT_TSA_SUPPORT_OFST 2014818#define MC_CMD_GET_CAPABILITIES_V3_OUT_TSA_SUPPORT_LBN 1614819#define MC_CMD_GET_CAPABILITIES_V3_OUT_TSA_SUPPORT_WIDTH 114820#define MC_CMD_GET_CAPABILITIES_V3_OUT_TSA_BOUND_OFST 2014821#define MC_CMD_GET_CAPABILITIES_V3_OUT_TSA_BOUND_LBN 1714822#define MC_CMD_GET_CAPABILITIES_V3_OUT_TSA_BOUND_WIDTH 114823#define MC_CMD_GET_CAPABILITIES_V3_OUT_SF_ADAPTER_AUTHENTICATION_OFST 2014824#define MC_CMD_GET_CAPABILITIES_V3_OUT_SF_ADAPTER_AUTHENTICATION_LBN 1814825#define MC_CMD_GET_CAPABILITIES_V3_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 114826#define MC_CMD_GET_CAPABILITIES_V3_OUT_FILTER_ACTION_FLAG_OFST 2014827#define MC_CMD_GET_CAPABILITIES_V3_OUT_FILTER_ACTION_FLAG_LBN 1914828#define MC_CMD_GET_CAPABILITIES_V3_OUT_FILTER_ACTION_FLAG_WIDTH 114829#define MC_CMD_GET_CAPABILITIES_V3_OUT_FILTER_ACTION_MARK_OFST 2014830#define MC_CMD_GET_CAPABILITIES_V3_OUT_FILTER_ACTION_MARK_LBN 2014831#define MC_CMD_GET_CAPABILITIES_V3_OUT_FILTER_ACTION_MARK_WIDTH 114832#define MC_CMD_GET_CAPABILITIES_V3_OUT_EQUAL_STRIDE_SUPER_BUFFER_OFST 2014833#define MC_CMD_GET_CAPABILITIES_V3_OUT_EQUAL_STRIDE_SUPER_BUFFER_LBN 2114834#define MC_CMD_GET_CAPABILITIES_V3_OUT_EQUAL_STRIDE_SUPER_BUFFER_WIDTH 114835#define MC_CMD_GET_CAPABILITIES_V3_OUT_EQUAL_STRIDE_PACKED_STREAM_OFST 2014836#define MC_CMD_GET_CAPABILITIES_V3_OUT_EQUAL_STRIDE_PACKED_STREAM_LBN 2114837#define MC_CMD_GET_CAPABILITIES_V3_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 114838#define MC_CMD_GET_CAPABILITIES_V3_OUT_L3XUDP_SUPPORT_OFST 2014839#define MC_CMD_GET_CAPABILITIES_V3_OUT_L3XUDP_SUPPORT_LBN 2214840#define MC_CMD_GET_CAPABILITIES_V3_OUT_L3XUDP_SUPPORT_WIDTH 114841#define MC_CMD_GET_CAPABILITIES_V3_OUT_FW_SUBVARIANT_NO_TX_CSUM_OFST 2014842#define MC_CMD_GET_CAPABILITIES_V3_OUT_FW_SUBVARIANT_NO_TX_CSUM_LBN 2314843#define MC_CMD_GET_CAPABILITIES_V3_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 114844#define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_SPREADING_OFST 2014845#define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_SPREADING_LBN 2414846#define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_SPREADING_WIDTH 114847#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_HLB_IDLE_OFST 2014848#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_HLB_IDLE_LBN 2514849#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_HLB_IDLE_WIDTH 114850#define MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_RXQ_NO_CONT_EV_OFST 2014851#define MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_RXQ_NO_CONT_EV_LBN 2614852#define MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_RXQ_NO_CONT_EV_WIDTH 114853#define MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_RXQ_WITH_BUFFER_SIZE_OFST 2014854#define MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_RXQ_WITH_BUFFER_SIZE_LBN 2714855#define MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_RXQ_WITH_BUFFER_SIZE_WIDTH 114856#define MC_CMD_GET_CAPABILITIES_V3_OUT_BUNDLE_UPDATE_OFST 2014857#define MC_CMD_GET_CAPABILITIES_V3_OUT_BUNDLE_UPDATE_LBN 2814858#define MC_CMD_GET_CAPABILITIES_V3_OUT_BUNDLE_UPDATE_WIDTH 114859#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V3_OFST 2014860#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V3_LBN 2914861#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V3_WIDTH 114862#define MC_CMD_GET_CAPABILITIES_V3_OUT_DYNAMIC_SENSORS_OFST 2014863#define MC_CMD_GET_CAPABILITIES_V3_OUT_DYNAMIC_SENSORS_LBN 3014864#define MC_CMD_GET_CAPABILITIES_V3_OUT_DYNAMIC_SENSORS_WIDTH 114865#define MC_CMD_GET_CAPABILITIES_V3_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_OFST 2014866#define MC_CMD_GET_CAPABILITIES_V3_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_LBN 3114867#define MC_CMD_GET_CAPABILITIES_V3_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_WIDTH 114868/* Number of FATSOv2 contexts per datapath supported by this NIC (when14869 * TX_TSO_V2 == 1). Not present on older firmware (check the length).14870 */14871#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_N_CONTEXTS_OFST 2414872#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_N_CONTEXTS_LEN 214873/* One byte per PF containing the number of the external port assigned to this14874 * PF, indexed by PF number. Special values indicate that a PF is either not14875 * present or not assigned.14876 */14877#define MC_CMD_GET_CAPABILITIES_V3_OUT_PFS_TO_PORTS_ASSIGNMENT_OFST 2614878#define MC_CMD_GET_CAPABILITIES_V3_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 114879#define MC_CMD_GET_CAPABILITIES_V3_OUT_PFS_TO_PORTS_ASSIGNMENT_NUM 1614880/* enum: The caller is not permitted to access information on this PF. */14881#define MC_CMD_GET_CAPABILITIES_V3_OUT_ACCESS_NOT_PERMITTED 0xff14882/* enum: PF does not exist. */14883#define MC_CMD_GET_CAPABILITIES_V3_OUT_PF_NOT_PRESENT 0xfe14884/* enum: PF does exist but is not assigned to any external port. */14885#define MC_CMD_GET_CAPABILITIES_V3_OUT_PF_NOT_ASSIGNED 0xfd14886/* enum: This value indicates that PF is assigned, but it cannot be expressed14887 * in this field. It is intended for a possible future situation where a more14888 * complex scheme of PFs to ports mapping is being used. The future driver14889 * should look for a new field supporting the new scheme. The current/old14890 * driver should treat this value as PF_NOT_ASSIGNED.14891 */14892#define MC_CMD_GET_CAPABILITIES_V3_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc14893/* One byte per PF containing the number of its VFs, indexed by PF number. A14894 * special value indicates that a PF is not present.14895 */14896#define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VFS_PER_PF_OFST 4214897#define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VFS_PER_PF_LEN 114898#define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VFS_PER_PF_NUM 1614899/* enum: The caller is not permitted to access information on this PF. */14900/* MC_CMD_GET_CAPABILITIES_V3_OUT_ACCESS_NOT_PERMITTED 0xff */14901/* enum: PF does not exist. */14902/* MC_CMD_GET_CAPABILITIES_V3_OUT_PF_NOT_PRESENT 0xfe */14903/* Number of VIs available for each external port */14904#define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VIS_PER_PORT_OFST 5814905#define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VIS_PER_PORT_LEN 214906#define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VIS_PER_PORT_NUM 414907/* Size of RX descriptor cache expressed as binary logarithm The actual size14908 * equals (2 ^ RX_DESC_CACHE_SIZE)14909 */14910#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DESC_CACHE_SIZE_OFST 6614911#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DESC_CACHE_SIZE_LEN 114912/* Size of TX descriptor cache expressed as binary logarithm The actual size14913 * equals (2 ^ TX_DESC_CACHE_SIZE)14914 */14915#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_DESC_CACHE_SIZE_OFST 6714916#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_DESC_CACHE_SIZE_LEN 114917/* Total number of available PIO buffers */14918#define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_PIO_BUFFS_OFST 6814919#define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_PIO_BUFFS_LEN 214920/* Size of a single PIO buffer */14921#define MC_CMD_GET_CAPABILITIES_V3_OUT_SIZE_PIO_BUFF_OFST 7014922#define MC_CMD_GET_CAPABILITIES_V3_OUT_SIZE_PIO_BUFF_LEN 214923/* On chips later than Medford the amount of address space assigned to each VI14924 * is configurable. This is a global setting that the driver must query to14925 * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available14926 * with 8k VI windows.14927 */14928#define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_OFST 7214929#define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_LEN 114930/* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k.14931 * CTPIO is not mapped.14932 */14933#define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_8K 0x014934/* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */14935#define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_16K 0x114936/* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */14937#define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_64K 0x214938/* Number of vFIFOs per adapter that can be used for VFIFO Stuffing14939 * (SF-115995-SW) in the present configuration of firmware and port mode.14940 */14941#define MC_CMD_GET_CAPABILITIES_V3_OUT_VFIFO_STUFFING_NUM_VFIFOS_OFST 7314942#define MC_CMD_GET_CAPABILITIES_V3_OUT_VFIFO_STUFFING_NUM_VFIFOS_LEN 114943/* Number of buffers per adapter that can be used for VFIFO Stuffing14944 * (SF-115995-SW) in the present configuration of firmware and port mode.14945 */14946#define MC_CMD_GET_CAPABILITIES_V3_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_OFST 7414947#define MC_CMD_GET_CAPABILITIES_V3_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_LEN 214948 14949/* MC_CMD_GET_CAPABILITIES_V4_OUT msgresponse */14950#define MC_CMD_GET_CAPABILITIES_V4_OUT_LEN 7814951/* First word of flags. */14952#define MC_CMD_GET_CAPABILITIES_V4_OUT_FLAGS1_OFST 014953#define MC_CMD_GET_CAPABILITIES_V4_OUT_FLAGS1_LEN 414954#define MC_CMD_GET_CAPABILITIES_V4_OUT_VPORT_RECONFIGURE_OFST 014955#define MC_CMD_GET_CAPABILITIES_V4_OUT_VPORT_RECONFIGURE_LBN 314956#define MC_CMD_GET_CAPABILITIES_V4_OUT_VPORT_RECONFIGURE_WIDTH 114957#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_STRIPING_OFST 014958#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_STRIPING_LBN 414959#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_STRIPING_WIDTH 114960#define MC_CMD_GET_CAPABILITIES_V4_OUT_VADAPTOR_QUERY_OFST 014961#define MC_CMD_GET_CAPABILITIES_V4_OUT_VADAPTOR_QUERY_LBN 514962#define MC_CMD_GET_CAPABILITIES_V4_OUT_VADAPTOR_QUERY_WIDTH 114963#define MC_CMD_GET_CAPABILITIES_V4_OUT_EVB_PORT_VLAN_RESTRICT_OFST 014964#define MC_CMD_GET_CAPABILITIES_V4_OUT_EVB_PORT_VLAN_RESTRICT_LBN 614965#define MC_CMD_GET_CAPABILITIES_V4_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 114966#define MC_CMD_GET_CAPABILITIES_V4_OUT_DRV_ATTACH_PREBOOT_OFST 014967#define MC_CMD_GET_CAPABILITIES_V4_OUT_DRV_ATTACH_PREBOOT_LBN 714968#define MC_CMD_GET_CAPABILITIES_V4_OUT_DRV_ATTACH_PREBOOT_WIDTH 114969#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_FORCE_EVENT_MERGING_OFST 014970#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_FORCE_EVENT_MERGING_LBN 814971#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_FORCE_EVENT_MERGING_WIDTH 114972#define MC_CMD_GET_CAPABILITIES_V4_OUT_SET_MAC_ENHANCED_OFST 014973#define MC_CMD_GET_CAPABILITIES_V4_OUT_SET_MAC_ENHANCED_LBN 914974#define MC_CMD_GET_CAPABILITIES_V4_OUT_SET_MAC_ENHANCED_WIDTH 114975#define MC_CMD_GET_CAPABILITIES_V4_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 014976#define MC_CMD_GET_CAPABILITIES_V4_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 1014977#define MC_CMD_GET_CAPABILITIES_V4_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 114978#define MC_CMD_GET_CAPABILITIES_V4_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 014979#define MC_CMD_GET_CAPABILITIES_V4_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 1114980#define MC_CMD_GET_CAPABILITIES_V4_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 114981#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MAC_SECURITY_FILTERING_OFST 014982#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MAC_SECURITY_FILTERING_LBN 1214983#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 114984#define MC_CMD_GET_CAPABILITIES_V4_OUT_ADDITIONAL_RSS_MODES_OFST 014985#define MC_CMD_GET_CAPABILITIES_V4_OUT_ADDITIONAL_RSS_MODES_LBN 1314986#define MC_CMD_GET_CAPABILITIES_V4_OUT_ADDITIONAL_RSS_MODES_WIDTH 114987#define MC_CMD_GET_CAPABILITIES_V4_OUT_QBB_OFST 014988#define MC_CMD_GET_CAPABILITIES_V4_OUT_QBB_LBN 1414989#define MC_CMD_GET_CAPABILITIES_V4_OUT_QBB_WIDTH 114990#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 014991#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 1514992#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 114993#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_RSS_LIMITED_OFST 014994#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_RSS_LIMITED_LBN 1614995#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_RSS_LIMITED_WIDTH 114996#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PACKED_STREAM_OFST 014997#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PACKED_STREAM_LBN 1714998#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PACKED_STREAM_WIDTH 114999#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_INCLUDE_FCS_OFST 015000#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_INCLUDE_FCS_LBN 1815001#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_INCLUDE_FCS_WIDTH 115002#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_VLAN_INSERTION_OFST 015003#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_VLAN_INSERTION_LBN 1915004#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_VLAN_INSERTION_WIDTH 115005#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_VLAN_STRIPPING_OFST 015006#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_VLAN_STRIPPING_LBN 2015007#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_VLAN_STRIPPING_WIDTH 115008#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_OFST 015009#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_LBN 2115010#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_WIDTH 115011#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PREFIX_LEN_0_OFST 015012#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PREFIX_LEN_0_LBN 2215013#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PREFIX_LEN_0_WIDTH 115014#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PREFIX_LEN_14_OFST 015015#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PREFIX_LEN_14_LBN 2315016#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PREFIX_LEN_14_WIDTH 115017#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_TIMESTAMP_OFST 015018#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_TIMESTAMP_LBN 2415019#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_TIMESTAMP_WIDTH 115020#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_BATCHING_OFST 015021#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_BATCHING_LBN 2515022#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_BATCHING_WIDTH 115023#define MC_CMD_GET_CAPABILITIES_V4_OUT_MCAST_FILTER_CHAINING_OFST 015024#define MC_CMD_GET_CAPABILITIES_V4_OUT_MCAST_FILTER_CHAINING_LBN 2615025#define MC_CMD_GET_CAPABILITIES_V4_OUT_MCAST_FILTER_CHAINING_WIDTH 115026#define MC_CMD_GET_CAPABILITIES_V4_OUT_PM_AND_RXDP_COUNTERS_OFST 015027#define MC_CMD_GET_CAPABILITIES_V4_OUT_PM_AND_RXDP_COUNTERS_LBN 2715028#define MC_CMD_GET_CAPABILITIES_V4_OUT_PM_AND_RXDP_COUNTERS_WIDTH 115029#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_DISABLE_SCATTER_OFST 015030#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_DISABLE_SCATTER_LBN 2815031#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_DISABLE_SCATTER_WIDTH 115032#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MCAST_UDP_LOOPBACK_OFST 015033#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MCAST_UDP_LOOPBACK_LBN 2915034#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 115035#define MC_CMD_GET_CAPABILITIES_V4_OUT_EVB_OFST 015036#define MC_CMD_GET_CAPABILITIES_V4_OUT_EVB_LBN 3015037#define MC_CMD_GET_CAPABILITIES_V4_OUT_EVB_WIDTH 115038#define MC_CMD_GET_CAPABILITIES_V4_OUT_VXLAN_NVGRE_OFST 015039#define MC_CMD_GET_CAPABILITIES_V4_OUT_VXLAN_NVGRE_LBN 3115040#define MC_CMD_GET_CAPABILITIES_V4_OUT_VXLAN_NVGRE_WIDTH 115041/* RxDPCPU firmware id. */15042#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_DPCPU_FW_ID_OFST 415043#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_DPCPU_FW_ID_LEN 215044/* enum: Standard RXDP firmware */15045#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP 0x015046/* enum: Low latency RXDP firmware */15047#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_LOW_LATENCY 0x115048/* enum: Packed stream RXDP firmware */15049#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_PACKED_STREAM 0x215050/* enum: Rules engine RXDP firmware */15051#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_RULES_ENGINE 0x515052/* enum: DPDK RXDP firmware */15053#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_DPDK 0x615054/* enum: BIST RXDP firmware */15055#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_BIST 0x10a15056/* enum: RXDP Test firmware image 1 */15057#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x10115058/* enum: RXDP Test firmware image 2 */15059#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x10215060/* enum: RXDP Test firmware image 3 */15061#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x10315062/* enum: RXDP Test firmware image 4 */15063#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x10415064/* enum: RXDP Test firmware image 5 */15065#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_BACKPRESSURE 0x10515066/* enum: RXDP Test firmware image 6 */15067#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_PACKET_EDITS 0x10615068/* enum: RXDP Test firmware image 7 */15069#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x10715070/* enum: RXDP Test firmware image 8 */15071#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_DISABLE_DL 0x10815072/* enum: RXDP Test firmware image 9 */15073#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b15074/* enum: RXDP Test firmware image 10 */15075#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_SLOW 0x10c15076/* TxDPCPU firmware id. */15077#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_DPCPU_FW_ID_OFST 615078#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_DPCPU_FW_ID_LEN 215079/* enum: Standard TXDP firmware */15080#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP 0x015081/* enum: Low latency TXDP firmware */15082#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_LOW_LATENCY 0x115083/* enum: High packet rate TXDP firmware */15084#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_HIGH_PACKET_RATE 0x315085/* enum: Rules engine TXDP firmware */15086#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_RULES_ENGINE 0x515087/* enum: DPDK TXDP firmware */15088#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_DPDK 0x615089/* enum: BIST TXDP firmware */15090#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_BIST 0x12d15091/* enum: TXDP Test firmware image 1 */15092#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_TEST_FW_TSO_EDIT 0x10115093/* enum: TXDP Test firmware image 2 */15094#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_TEST_FW_PACKET_EDITS 0x10215095/* enum: TXDP CSR bus test firmware */15096#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_TEST_FW_CSR 0x10315097#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_OFST 815098#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_LEN 215099#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_REV_OFST 815100#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_REV_LBN 015101#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_REV_WIDTH 1215102#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_TYPE_OFST 815103#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_TYPE_LBN 1215104#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_TYPE_WIDTH 415105/* enum: reserved value - do not use (may indicate alternative interpretation15106 * of REV field in future)15107 */15108#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_RESERVED 0x015109/* enum: Trivial RX PD firmware for early Huntington development (Huntington15110 * development only)15111 */15112#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_FIRST_PKT 0x115113/* enum: RX PD firmware for telemetry prototyping (Medford2 development only)15114 */15115#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x115116/* enum: RX PD firmware with approximately Siena-compatible behaviour15117 * (Huntington development only)15118 */15119#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x215120/* enum: Full featured RX PD production firmware */15121#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x315122/* enum: (deprecated original name for the FULL_FEATURED variant) */15123#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_VSWITCH 0x315124/* enum: siena_compat variant RX PD firmware using PM rather than MAC15125 * (Huntington development only)15126 */15127#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x415128/* enum: Low latency RX PD production firmware */15129#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x515130/* enum: Packed stream RX PD production firmware */15131#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x615132/* enum: RX PD firmware handling layer 2 only for high packet rate performance15133 * tests (Medford development only)15134 */15135#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x715136/* enum: Rules engine RX PD production firmware */15137#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x815138/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */15139#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_L3XUDP 0x915140/* enum: DPDK RX PD production firmware */15141#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_DPDK 0xa15142/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */15143#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe15144/* enum: RX PD firmware parsing but not filtering network overlay tunnel15145 * encapsulations (Medford development only)15146 */15147#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf15148#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_OFST 1015149#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_LEN 215150#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_REV_OFST 1015151#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_REV_LBN 015152#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_REV_WIDTH 1215153#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_TYPE_OFST 1015154#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_TYPE_LBN 1215155#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_TYPE_WIDTH 415156/* enum: reserved value - do not use (may indicate alternative interpretation15157 * of REV field in future)15158 */15159#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_RESERVED 0x015160/* enum: Trivial TX PD firmware for early Huntington development (Huntington15161 * development only)15162 */15163#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_FIRST_PKT 0x115164/* enum: TX PD firmware for telemetry prototyping (Medford2 development only)15165 */15166#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x115167/* enum: TX PD firmware with approximately Siena-compatible behaviour15168 * (Huntington development only)15169 */15170#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x215171/* enum: Full featured TX PD production firmware */15172#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x315173/* enum: (deprecated original name for the FULL_FEATURED variant) */15174#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_VSWITCH 0x315175/* enum: siena_compat variant TX PD firmware using PM rather than MAC15176 * (Huntington development only)15177 */15178#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x415179#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */15180/* enum: TX PD firmware handling layer 2 only for high packet rate performance15181 * tests (Medford development only)15182 */15183#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x715184/* enum: Rules engine TX PD production firmware */15185#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x815186/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */15187#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_L3XUDP 0x915188/* enum: DPDK TX PD production firmware */15189#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_DPDK 0xa15190/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */15191#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe15192/* Hardware capabilities of NIC */15193#define MC_CMD_GET_CAPABILITIES_V4_OUT_HW_CAPABILITIES_OFST 1215194#define MC_CMD_GET_CAPABILITIES_V4_OUT_HW_CAPABILITIES_LEN 415195/* Licensed capabilities */15196#define MC_CMD_GET_CAPABILITIES_V4_OUT_LICENSE_CAPABILITIES_OFST 1615197#define MC_CMD_GET_CAPABILITIES_V4_OUT_LICENSE_CAPABILITIES_LEN 415198/* Second word of flags. Not present on older firmware (check the length). */15199#define MC_CMD_GET_CAPABILITIES_V4_OUT_FLAGS2_OFST 2015200#define MC_CMD_GET_CAPABILITIES_V4_OUT_FLAGS2_LEN 415201#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_OFST 2015202#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_LBN 015203#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_WIDTH 115204#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_ENCAP_OFST 2015205#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_ENCAP_LBN 115206#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_ENCAP_WIDTH 115207#define MC_CMD_GET_CAPABILITIES_V4_OUT_EVQ_TIMER_CTRL_OFST 2015208#define MC_CMD_GET_CAPABILITIES_V4_OUT_EVQ_TIMER_CTRL_LBN 215209#define MC_CMD_GET_CAPABILITIES_V4_OUT_EVQ_TIMER_CTRL_WIDTH 115210#define MC_CMD_GET_CAPABILITIES_V4_OUT_EVENT_CUT_THROUGH_OFST 2015211#define MC_CMD_GET_CAPABILITIES_V4_OUT_EVENT_CUT_THROUGH_LBN 315212#define MC_CMD_GET_CAPABILITIES_V4_OUT_EVENT_CUT_THROUGH_WIDTH 115213#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_CUT_THROUGH_OFST 2015214#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_CUT_THROUGH_LBN 415215#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_CUT_THROUGH_WIDTH 115216#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_VFIFO_ULL_MODE_OFST 2015217#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_VFIFO_ULL_MODE_LBN 515218#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_VFIFO_ULL_MODE_WIDTH 115219#define MC_CMD_GET_CAPABILITIES_V4_OUT_MAC_STATS_40G_TX_SIZE_BINS_OFST 2015220#define MC_CMD_GET_CAPABILITIES_V4_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 615221#define MC_CMD_GET_CAPABILITIES_V4_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 115222#define MC_CMD_GET_CAPABILITIES_V4_OUT_INIT_EVQ_TYPE_SUPPORTED_OFST 2015223#define MC_CMD_GET_CAPABILITIES_V4_OUT_INIT_EVQ_TYPE_SUPPORTED_LBN 715224#define MC_CMD_GET_CAPABILITIES_V4_OUT_INIT_EVQ_TYPE_SUPPORTED_WIDTH 115225#define MC_CMD_GET_CAPABILITIES_V4_OUT_INIT_EVQ_V2_OFST 2015226#define MC_CMD_GET_CAPABILITIES_V4_OUT_INIT_EVQ_V2_LBN 715227#define MC_CMD_GET_CAPABILITIES_V4_OUT_INIT_EVQ_V2_WIDTH 115228#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MAC_TIMESTAMPING_OFST 2015229#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MAC_TIMESTAMPING_LBN 815230#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MAC_TIMESTAMPING_WIDTH 115231#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TIMESTAMP_OFST 2015232#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TIMESTAMP_LBN 915233#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TIMESTAMP_WIDTH 115234#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_SNIFF_OFST 2015235#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_SNIFF_LBN 1015236#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_SNIFF_WIDTH 115237#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_SNIFF_OFST 2015238#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_SNIFF_LBN 1115239#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_SNIFF_WIDTH 115240#define MC_CMD_GET_CAPABILITIES_V4_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_OFST 2015241#define MC_CMD_GET_CAPABILITIES_V4_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_LBN 1215242#define MC_CMD_GET_CAPABILITIES_V4_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 115243#define MC_CMD_GET_CAPABILITIES_V4_OUT_MCDI_BACKGROUND_OFST 2015244#define MC_CMD_GET_CAPABILITIES_V4_OUT_MCDI_BACKGROUND_LBN 1315245#define MC_CMD_GET_CAPABILITIES_V4_OUT_MCDI_BACKGROUND_WIDTH 115246#define MC_CMD_GET_CAPABILITIES_V4_OUT_MCDI_DB_RETURN_OFST 2015247#define MC_CMD_GET_CAPABILITIES_V4_OUT_MCDI_DB_RETURN_LBN 1415248#define MC_CMD_GET_CAPABILITIES_V4_OUT_MCDI_DB_RETURN_WIDTH 115249#define MC_CMD_GET_CAPABILITIES_V4_OUT_CTPIO_OFST 2015250#define MC_CMD_GET_CAPABILITIES_V4_OUT_CTPIO_LBN 1515251#define MC_CMD_GET_CAPABILITIES_V4_OUT_CTPIO_WIDTH 115252#define MC_CMD_GET_CAPABILITIES_V4_OUT_TSA_SUPPORT_OFST 2015253#define MC_CMD_GET_CAPABILITIES_V4_OUT_TSA_SUPPORT_LBN 1615254#define MC_CMD_GET_CAPABILITIES_V4_OUT_TSA_SUPPORT_WIDTH 115255#define MC_CMD_GET_CAPABILITIES_V4_OUT_TSA_BOUND_OFST 2015256#define MC_CMD_GET_CAPABILITIES_V4_OUT_TSA_BOUND_LBN 1715257#define MC_CMD_GET_CAPABILITIES_V4_OUT_TSA_BOUND_WIDTH 115258#define MC_CMD_GET_CAPABILITIES_V4_OUT_SF_ADAPTER_AUTHENTICATION_OFST 2015259#define MC_CMD_GET_CAPABILITIES_V4_OUT_SF_ADAPTER_AUTHENTICATION_LBN 1815260#define MC_CMD_GET_CAPABILITIES_V4_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 115261#define MC_CMD_GET_CAPABILITIES_V4_OUT_FILTER_ACTION_FLAG_OFST 2015262#define MC_CMD_GET_CAPABILITIES_V4_OUT_FILTER_ACTION_FLAG_LBN 1915263#define MC_CMD_GET_CAPABILITIES_V4_OUT_FILTER_ACTION_FLAG_WIDTH 115264#define MC_CMD_GET_CAPABILITIES_V4_OUT_FILTER_ACTION_MARK_OFST 2015265#define MC_CMD_GET_CAPABILITIES_V4_OUT_FILTER_ACTION_MARK_LBN 2015266#define MC_CMD_GET_CAPABILITIES_V4_OUT_FILTER_ACTION_MARK_WIDTH 115267#define MC_CMD_GET_CAPABILITIES_V4_OUT_EQUAL_STRIDE_SUPER_BUFFER_OFST 2015268#define MC_CMD_GET_CAPABILITIES_V4_OUT_EQUAL_STRIDE_SUPER_BUFFER_LBN 2115269#define MC_CMD_GET_CAPABILITIES_V4_OUT_EQUAL_STRIDE_SUPER_BUFFER_WIDTH 115270#define MC_CMD_GET_CAPABILITIES_V4_OUT_EQUAL_STRIDE_PACKED_STREAM_OFST 2015271#define MC_CMD_GET_CAPABILITIES_V4_OUT_EQUAL_STRIDE_PACKED_STREAM_LBN 2115272#define MC_CMD_GET_CAPABILITIES_V4_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 115273#define MC_CMD_GET_CAPABILITIES_V4_OUT_L3XUDP_SUPPORT_OFST 2015274#define MC_CMD_GET_CAPABILITIES_V4_OUT_L3XUDP_SUPPORT_LBN 2215275#define MC_CMD_GET_CAPABILITIES_V4_OUT_L3XUDP_SUPPORT_WIDTH 115276#define MC_CMD_GET_CAPABILITIES_V4_OUT_FW_SUBVARIANT_NO_TX_CSUM_OFST 2015277#define MC_CMD_GET_CAPABILITIES_V4_OUT_FW_SUBVARIANT_NO_TX_CSUM_LBN 2315278#define MC_CMD_GET_CAPABILITIES_V4_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 115279#define MC_CMD_GET_CAPABILITIES_V4_OUT_VI_SPREADING_OFST 2015280#define MC_CMD_GET_CAPABILITIES_V4_OUT_VI_SPREADING_LBN 2415281#define MC_CMD_GET_CAPABILITIES_V4_OUT_VI_SPREADING_WIDTH 115282#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_HLB_IDLE_OFST 2015283#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_HLB_IDLE_LBN 2515284#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_HLB_IDLE_WIDTH 115285#define MC_CMD_GET_CAPABILITIES_V4_OUT_INIT_RXQ_NO_CONT_EV_OFST 2015286#define MC_CMD_GET_CAPABILITIES_V4_OUT_INIT_RXQ_NO_CONT_EV_LBN 2615287#define MC_CMD_GET_CAPABILITIES_V4_OUT_INIT_RXQ_NO_CONT_EV_WIDTH 115288#define MC_CMD_GET_CAPABILITIES_V4_OUT_INIT_RXQ_WITH_BUFFER_SIZE_OFST 2015289#define MC_CMD_GET_CAPABILITIES_V4_OUT_INIT_RXQ_WITH_BUFFER_SIZE_LBN 2715290#define MC_CMD_GET_CAPABILITIES_V4_OUT_INIT_RXQ_WITH_BUFFER_SIZE_WIDTH 115291#define MC_CMD_GET_CAPABILITIES_V4_OUT_BUNDLE_UPDATE_OFST 2015292#define MC_CMD_GET_CAPABILITIES_V4_OUT_BUNDLE_UPDATE_LBN 2815293#define MC_CMD_GET_CAPABILITIES_V4_OUT_BUNDLE_UPDATE_WIDTH 115294#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V3_OFST 2015295#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V3_LBN 2915296#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V3_WIDTH 115297#define MC_CMD_GET_CAPABILITIES_V4_OUT_DYNAMIC_SENSORS_OFST 2015298#define MC_CMD_GET_CAPABILITIES_V4_OUT_DYNAMIC_SENSORS_LBN 3015299#define MC_CMD_GET_CAPABILITIES_V4_OUT_DYNAMIC_SENSORS_WIDTH 115300#define MC_CMD_GET_CAPABILITIES_V4_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_OFST 2015301#define MC_CMD_GET_CAPABILITIES_V4_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_LBN 3115302#define MC_CMD_GET_CAPABILITIES_V4_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_WIDTH 115303/* Number of FATSOv2 contexts per datapath supported by this NIC (when15304 * TX_TSO_V2 == 1). Not present on older firmware (check the length).15305 */15306#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_N_CONTEXTS_OFST 2415307#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_N_CONTEXTS_LEN 215308/* One byte per PF containing the number of the external port assigned to this15309 * PF, indexed by PF number. Special values indicate that a PF is either not15310 * present or not assigned.15311 */15312#define MC_CMD_GET_CAPABILITIES_V4_OUT_PFS_TO_PORTS_ASSIGNMENT_OFST 2615313#define MC_CMD_GET_CAPABILITIES_V4_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 115314#define MC_CMD_GET_CAPABILITIES_V4_OUT_PFS_TO_PORTS_ASSIGNMENT_NUM 1615315/* enum: The caller is not permitted to access information on this PF. */15316#define MC_CMD_GET_CAPABILITIES_V4_OUT_ACCESS_NOT_PERMITTED 0xff15317/* enum: PF does not exist. */15318#define MC_CMD_GET_CAPABILITIES_V4_OUT_PF_NOT_PRESENT 0xfe15319/* enum: PF does exist but is not assigned to any external port. */15320#define MC_CMD_GET_CAPABILITIES_V4_OUT_PF_NOT_ASSIGNED 0xfd15321/* enum: This value indicates that PF is assigned, but it cannot be expressed15322 * in this field. It is intended for a possible future situation where a more15323 * complex scheme of PFs to ports mapping is being used. The future driver15324 * should look for a new field supporting the new scheme. The current/old15325 * driver should treat this value as PF_NOT_ASSIGNED.15326 */15327#define MC_CMD_GET_CAPABILITIES_V4_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc15328/* One byte per PF containing the number of its VFs, indexed by PF number. A15329 * special value indicates that a PF is not present.15330 */15331#define MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_VFS_PER_PF_OFST 4215332#define MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_VFS_PER_PF_LEN 115333#define MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_VFS_PER_PF_NUM 1615334/* enum: The caller is not permitted to access information on this PF. */15335/* MC_CMD_GET_CAPABILITIES_V4_OUT_ACCESS_NOT_PERMITTED 0xff */15336/* enum: PF does not exist. */15337/* MC_CMD_GET_CAPABILITIES_V4_OUT_PF_NOT_PRESENT 0xfe */15338/* Number of VIs available for each external port */15339#define MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_VIS_PER_PORT_OFST 5815340#define MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_VIS_PER_PORT_LEN 215341#define MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_VIS_PER_PORT_NUM 415342/* Size of RX descriptor cache expressed as binary logarithm The actual size15343 * equals (2 ^ RX_DESC_CACHE_SIZE)15344 */15345#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_DESC_CACHE_SIZE_OFST 6615346#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_DESC_CACHE_SIZE_LEN 115347/* Size of TX descriptor cache expressed as binary logarithm The actual size15348 * equals (2 ^ TX_DESC_CACHE_SIZE)15349 */15350#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_DESC_CACHE_SIZE_OFST 6715351#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_DESC_CACHE_SIZE_LEN 115352/* Total number of available PIO buffers */15353#define MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_PIO_BUFFS_OFST 6815354#define MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_PIO_BUFFS_LEN 215355/* Size of a single PIO buffer */15356#define MC_CMD_GET_CAPABILITIES_V4_OUT_SIZE_PIO_BUFF_OFST 7015357#define MC_CMD_GET_CAPABILITIES_V4_OUT_SIZE_PIO_BUFF_LEN 215358/* On chips later than Medford the amount of address space assigned to each VI15359 * is configurable. This is a global setting that the driver must query to15360 * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available15361 * with 8k VI windows.15362 */15363#define MC_CMD_GET_CAPABILITIES_V4_OUT_VI_WINDOW_MODE_OFST 7215364#define MC_CMD_GET_CAPABILITIES_V4_OUT_VI_WINDOW_MODE_LEN 115365/* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k.15366 * CTPIO is not mapped.15367 */15368#define MC_CMD_GET_CAPABILITIES_V4_OUT_VI_WINDOW_MODE_8K 0x015369/* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */15370#define MC_CMD_GET_CAPABILITIES_V4_OUT_VI_WINDOW_MODE_16K 0x115371/* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */15372#define MC_CMD_GET_CAPABILITIES_V4_OUT_VI_WINDOW_MODE_64K 0x215373/* Number of vFIFOs per adapter that can be used for VFIFO Stuffing15374 * (SF-115995-SW) in the present configuration of firmware and port mode.15375 */15376#define MC_CMD_GET_CAPABILITIES_V4_OUT_VFIFO_STUFFING_NUM_VFIFOS_OFST 7315377#define MC_CMD_GET_CAPABILITIES_V4_OUT_VFIFO_STUFFING_NUM_VFIFOS_LEN 115378/* Number of buffers per adapter that can be used for VFIFO Stuffing15379 * (SF-115995-SW) in the present configuration of firmware and port mode.15380 */15381#define MC_CMD_GET_CAPABILITIES_V4_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_OFST 7415382#define MC_CMD_GET_CAPABILITIES_V4_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_LEN 215383/* Entry count in the MAC stats array, including the final GENERATION_END15384 * entry. For MAC stats DMA, drivers should allocate a buffer large enough to15385 * hold at least this many 64-bit stats values, if they wish to receive all15386 * available stats. If the buffer is shorter than MAC_STATS_NUM_STATS * 8, the15387 * stats array returned will be truncated.15388 */15389#define MC_CMD_GET_CAPABILITIES_V4_OUT_MAC_STATS_NUM_STATS_OFST 7615390#define MC_CMD_GET_CAPABILITIES_V4_OUT_MAC_STATS_NUM_STATS_LEN 215391 15392/* MC_CMD_GET_CAPABILITIES_V5_OUT msgresponse */15393#define MC_CMD_GET_CAPABILITIES_V5_OUT_LEN 8415394/* First word of flags. */15395#define MC_CMD_GET_CAPABILITIES_V5_OUT_FLAGS1_OFST 015396#define MC_CMD_GET_CAPABILITIES_V5_OUT_FLAGS1_LEN 415397#define MC_CMD_GET_CAPABILITIES_V5_OUT_VPORT_RECONFIGURE_OFST 015398#define MC_CMD_GET_CAPABILITIES_V5_OUT_VPORT_RECONFIGURE_LBN 315399#define MC_CMD_GET_CAPABILITIES_V5_OUT_VPORT_RECONFIGURE_WIDTH 115400#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_STRIPING_OFST 015401#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_STRIPING_LBN 415402#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_STRIPING_WIDTH 115403#define MC_CMD_GET_CAPABILITIES_V5_OUT_VADAPTOR_QUERY_OFST 015404#define MC_CMD_GET_CAPABILITIES_V5_OUT_VADAPTOR_QUERY_LBN 515405#define MC_CMD_GET_CAPABILITIES_V5_OUT_VADAPTOR_QUERY_WIDTH 115406#define MC_CMD_GET_CAPABILITIES_V5_OUT_EVB_PORT_VLAN_RESTRICT_OFST 015407#define MC_CMD_GET_CAPABILITIES_V5_OUT_EVB_PORT_VLAN_RESTRICT_LBN 615408#define MC_CMD_GET_CAPABILITIES_V5_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 115409#define MC_CMD_GET_CAPABILITIES_V5_OUT_DRV_ATTACH_PREBOOT_OFST 015410#define MC_CMD_GET_CAPABILITIES_V5_OUT_DRV_ATTACH_PREBOOT_LBN 715411#define MC_CMD_GET_CAPABILITIES_V5_OUT_DRV_ATTACH_PREBOOT_WIDTH 115412#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_FORCE_EVENT_MERGING_OFST 015413#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_FORCE_EVENT_MERGING_LBN 815414#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_FORCE_EVENT_MERGING_WIDTH 115415#define MC_CMD_GET_CAPABILITIES_V5_OUT_SET_MAC_ENHANCED_OFST 015416#define MC_CMD_GET_CAPABILITIES_V5_OUT_SET_MAC_ENHANCED_LBN 915417#define MC_CMD_GET_CAPABILITIES_V5_OUT_SET_MAC_ENHANCED_WIDTH 115418#define MC_CMD_GET_CAPABILITIES_V5_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 015419#define MC_CMD_GET_CAPABILITIES_V5_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 1015420#define MC_CMD_GET_CAPABILITIES_V5_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 115421#define MC_CMD_GET_CAPABILITIES_V5_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 015422#define MC_CMD_GET_CAPABILITIES_V5_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 1115423#define MC_CMD_GET_CAPABILITIES_V5_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 115424#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_MAC_SECURITY_FILTERING_OFST 015425#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_MAC_SECURITY_FILTERING_LBN 1215426#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 115427#define MC_CMD_GET_CAPABILITIES_V5_OUT_ADDITIONAL_RSS_MODES_OFST 015428#define MC_CMD_GET_CAPABILITIES_V5_OUT_ADDITIONAL_RSS_MODES_LBN 1315429#define MC_CMD_GET_CAPABILITIES_V5_OUT_ADDITIONAL_RSS_MODES_WIDTH 115430#define MC_CMD_GET_CAPABILITIES_V5_OUT_QBB_OFST 015431#define MC_CMD_GET_CAPABILITIES_V5_OUT_QBB_LBN 1415432#define MC_CMD_GET_CAPABILITIES_V5_OUT_QBB_WIDTH 115433#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 015434#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 1515435#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 115436#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_RSS_LIMITED_OFST 015437#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_RSS_LIMITED_LBN 1615438#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_RSS_LIMITED_WIDTH 115439#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PACKED_STREAM_OFST 015440#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PACKED_STREAM_LBN 1715441#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PACKED_STREAM_WIDTH 115442#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_INCLUDE_FCS_OFST 015443#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_INCLUDE_FCS_LBN 1815444#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_INCLUDE_FCS_WIDTH 115445#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_VLAN_INSERTION_OFST 015446#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_VLAN_INSERTION_LBN 1915447#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_VLAN_INSERTION_WIDTH 115448#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_VLAN_STRIPPING_OFST 015449#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_VLAN_STRIPPING_LBN 2015450#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_VLAN_STRIPPING_WIDTH 115451#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_OFST 015452#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_LBN 2115453#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_WIDTH 115454#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PREFIX_LEN_0_OFST 015455#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PREFIX_LEN_0_LBN 2215456#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PREFIX_LEN_0_WIDTH 115457#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PREFIX_LEN_14_OFST 015458#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PREFIX_LEN_14_LBN 2315459#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PREFIX_LEN_14_WIDTH 115460#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_TIMESTAMP_OFST 015461#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_TIMESTAMP_LBN 2415462#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_TIMESTAMP_WIDTH 115463#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_BATCHING_OFST 015464#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_BATCHING_LBN 2515465#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_BATCHING_WIDTH 115466#define MC_CMD_GET_CAPABILITIES_V5_OUT_MCAST_FILTER_CHAINING_OFST 015467#define MC_CMD_GET_CAPABILITIES_V5_OUT_MCAST_FILTER_CHAINING_LBN 2615468#define MC_CMD_GET_CAPABILITIES_V5_OUT_MCAST_FILTER_CHAINING_WIDTH 115469#define MC_CMD_GET_CAPABILITIES_V5_OUT_PM_AND_RXDP_COUNTERS_OFST 015470#define MC_CMD_GET_CAPABILITIES_V5_OUT_PM_AND_RXDP_COUNTERS_LBN 2715471#define MC_CMD_GET_CAPABILITIES_V5_OUT_PM_AND_RXDP_COUNTERS_WIDTH 115472#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_DISABLE_SCATTER_OFST 015473#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_DISABLE_SCATTER_LBN 2815474#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_DISABLE_SCATTER_WIDTH 115475#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_MCAST_UDP_LOOPBACK_OFST 015476#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_MCAST_UDP_LOOPBACK_LBN 2915477#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 115478#define MC_CMD_GET_CAPABILITIES_V5_OUT_EVB_OFST 015479#define MC_CMD_GET_CAPABILITIES_V5_OUT_EVB_LBN 3015480#define MC_CMD_GET_CAPABILITIES_V5_OUT_EVB_WIDTH 115481#define MC_CMD_GET_CAPABILITIES_V5_OUT_VXLAN_NVGRE_OFST 015482#define MC_CMD_GET_CAPABILITIES_V5_OUT_VXLAN_NVGRE_LBN 3115483#define MC_CMD_GET_CAPABILITIES_V5_OUT_VXLAN_NVGRE_WIDTH 115484/* RxDPCPU firmware id. */15485#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_DPCPU_FW_ID_OFST 415486#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_DPCPU_FW_ID_LEN 215487/* enum: Standard RXDP firmware */15488#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP 0x015489/* enum: Low latency RXDP firmware */15490#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_LOW_LATENCY 0x115491/* enum: Packed stream RXDP firmware */15492#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_PACKED_STREAM 0x215493/* enum: Rules engine RXDP firmware */15494#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_RULES_ENGINE 0x515495/* enum: DPDK RXDP firmware */15496#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_DPDK 0x615497/* enum: BIST RXDP firmware */15498#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_BIST 0x10a15499/* enum: RXDP Test firmware image 1 */15500#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x10115501/* enum: RXDP Test firmware image 2 */15502#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x10215503/* enum: RXDP Test firmware image 3 */15504#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x10315505/* enum: RXDP Test firmware image 4 */15506#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x10415507/* enum: RXDP Test firmware image 5 */15508#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_BACKPRESSURE 0x10515509/* enum: RXDP Test firmware image 6 */15510#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_PACKET_EDITS 0x10615511/* enum: RXDP Test firmware image 7 */15512#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x10715513/* enum: RXDP Test firmware image 8 */15514#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_DISABLE_DL 0x10815515/* enum: RXDP Test firmware image 9 */15516#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b15517/* enum: RXDP Test firmware image 10 */15518#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_SLOW 0x10c15519/* TxDPCPU firmware id. */15520#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_DPCPU_FW_ID_OFST 615521#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_DPCPU_FW_ID_LEN 215522/* enum: Standard TXDP firmware */15523#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP 0x015524/* enum: Low latency TXDP firmware */15525#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_LOW_LATENCY 0x115526/* enum: High packet rate TXDP firmware */15527#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_HIGH_PACKET_RATE 0x315528/* enum: Rules engine TXDP firmware */15529#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_RULES_ENGINE 0x515530/* enum: DPDK TXDP firmware */15531#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_DPDK 0x615532/* enum: BIST TXDP firmware */15533#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_BIST 0x12d15534/* enum: TXDP Test firmware image 1 */15535#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_TEST_FW_TSO_EDIT 0x10115536/* enum: TXDP Test firmware image 2 */15537#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_TEST_FW_PACKET_EDITS 0x10215538/* enum: TXDP CSR bus test firmware */15539#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_TEST_FW_CSR 0x10315540#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_VERSION_OFST 815541#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_VERSION_LEN 215542#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_VERSION_REV_OFST 815543#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_VERSION_REV_LBN 015544#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_VERSION_REV_WIDTH 1215545#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_VERSION_TYPE_OFST 815546#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_VERSION_TYPE_LBN 1215547#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_VERSION_TYPE_WIDTH 415548/* enum: reserved value - do not use (may indicate alternative interpretation15549 * of REV field in future)15550 */15551#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_RESERVED 0x015552/* enum: Trivial RX PD firmware for early Huntington development (Huntington15553 * development only)15554 */15555#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_FIRST_PKT 0x115556/* enum: RX PD firmware for telemetry prototyping (Medford2 development only)15557 */15558#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x115559/* enum: RX PD firmware with approximately Siena-compatible behaviour15560 * (Huntington development only)15561 */15562#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x215563/* enum: Full featured RX PD production firmware */15564#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x315565/* enum: (deprecated original name for the FULL_FEATURED variant) */15566#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_VSWITCH 0x315567/* enum: siena_compat variant RX PD firmware using PM rather than MAC15568 * (Huntington development only)15569 */15570#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x415571/* enum: Low latency RX PD production firmware */15572#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x515573/* enum: Packed stream RX PD production firmware */15574#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x615575/* enum: RX PD firmware handling layer 2 only for high packet rate performance15576 * tests (Medford development only)15577 */15578#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x715579/* enum: Rules engine RX PD production firmware */15580#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x815581/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */15582#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_L3XUDP 0x915583/* enum: DPDK RX PD production firmware */15584#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_DPDK 0xa15585/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */15586#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe15587/* enum: RX PD firmware parsing but not filtering network overlay tunnel15588 * encapsulations (Medford development only)15589 */15590#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf15591#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_VERSION_OFST 1015592#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_VERSION_LEN 215593#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_VERSION_REV_OFST 1015594#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_VERSION_REV_LBN 015595#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_VERSION_REV_WIDTH 1215596#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_VERSION_TYPE_OFST 1015597#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_VERSION_TYPE_LBN 1215598#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_VERSION_TYPE_WIDTH 415599/* enum: reserved value - do not use (may indicate alternative interpretation15600 * of REV field in future)15601 */15602#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_RESERVED 0x015603/* enum: Trivial TX PD firmware for early Huntington development (Huntington15604 * development only)15605 */15606#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_FIRST_PKT 0x115607/* enum: TX PD firmware for telemetry prototyping (Medford2 development only)15608 */15609#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x115610/* enum: TX PD firmware with approximately Siena-compatible behaviour15611 * (Huntington development only)15612 */15613#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x215614/* enum: Full featured TX PD production firmware */15615#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x315616/* enum: (deprecated original name for the FULL_FEATURED variant) */15617#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_VSWITCH 0x315618/* enum: siena_compat variant TX PD firmware using PM rather than MAC15619 * (Huntington development only)15620 */15621#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x415622#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */15623/* enum: TX PD firmware handling layer 2 only for high packet rate performance15624 * tests (Medford development only)15625 */15626#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x715627/* enum: Rules engine TX PD production firmware */15628#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x815629/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */15630#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_L3XUDP 0x915631/* enum: DPDK TX PD production firmware */15632#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_DPDK 0xa15633/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */15634#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe15635/* Hardware capabilities of NIC */15636#define MC_CMD_GET_CAPABILITIES_V5_OUT_HW_CAPABILITIES_OFST 1215637#define MC_CMD_GET_CAPABILITIES_V5_OUT_HW_CAPABILITIES_LEN 415638/* Licensed capabilities */15639#define MC_CMD_GET_CAPABILITIES_V5_OUT_LICENSE_CAPABILITIES_OFST 1615640#define MC_CMD_GET_CAPABILITIES_V5_OUT_LICENSE_CAPABILITIES_LEN 415641/* Second word of flags. Not present on older firmware (check the length). */15642#define MC_CMD_GET_CAPABILITIES_V5_OUT_FLAGS2_OFST 2015643#define MC_CMD_GET_CAPABILITIES_V5_OUT_FLAGS2_LEN 415644#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V2_OFST 2015645#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V2_LBN 015646#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V2_WIDTH 115647#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V2_ENCAP_OFST 2015648#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V2_ENCAP_LBN 115649#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V2_ENCAP_WIDTH 115650#define MC_CMD_GET_CAPABILITIES_V5_OUT_EVQ_TIMER_CTRL_OFST 2015651#define MC_CMD_GET_CAPABILITIES_V5_OUT_EVQ_TIMER_CTRL_LBN 215652#define MC_CMD_GET_CAPABILITIES_V5_OUT_EVQ_TIMER_CTRL_WIDTH 115653#define MC_CMD_GET_CAPABILITIES_V5_OUT_EVENT_CUT_THROUGH_OFST 2015654#define MC_CMD_GET_CAPABILITIES_V5_OUT_EVENT_CUT_THROUGH_LBN 315655#define MC_CMD_GET_CAPABILITIES_V5_OUT_EVENT_CUT_THROUGH_WIDTH 115656#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_CUT_THROUGH_OFST 2015657#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_CUT_THROUGH_LBN 415658#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_CUT_THROUGH_WIDTH 115659#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_VFIFO_ULL_MODE_OFST 2015660#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_VFIFO_ULL_MODE_LBN 515661#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_VFIFO_ULL_MODE_WIDTH 115662#define MC_CMD_GET_CAPABILITIES_V5_OUT_MAC_STATS_40G_TX_SIZE_BINS_OFST 2015663#define MC_CMD_GET_CAPABILITIES_V5_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 615664#define MC_CMD_GET_CAPABILITIES_V5_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 115665#define MC_CMD_GET_CAPABILITIES_V5_OUT_INIT_EVQ_TYPE_SUPPORTED_OFST 2015666#define MC_CMD_GET_CAPABILITIES_V5_OUT_INIT_EVQ_TYPE_SUPPORTED_LBN 715667#define MC_CMD_GET_CAPABILITIES_V5_OUT_INIT_EVQ_TYPE_SUPPORTED_WIDTH 115668#define MC_CMD_GET_CAPABILITIES_V5_OUT_INIT_EVQ_V2_OFST 2015669#define MC_CMD_GET_CAPABILITIES_V5_OUT_INIT_EVQ_V2_LBN 715670#define MC_CMD_GET_CAPABILITIES_V5_OUT_INIT_EVQ_V2_WIDTH 115671#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_MAC_TIMESTAMPING_OFST 2015672#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_MAC_TIMESTAMPING_LBN 815673#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_MAC_TIMESTAMPING_WIDTH 115674#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TIMESTAMP_OFST 2015675#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TIMESTAMP_LBN 915676#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TIMESTAMP_WIDTH 115677#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_SNIFF_OFST 2015678#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_SNIFF_LBN 1015679#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_SNIFF_WIDTH 115680#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_SNIFF_OFST 2015681#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_SNIFF_LBN 1115682#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_SNIFF_WIDTH 115683#define MC_CMD_GET_CAPABILITIES_V5_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_OFST 2015684#define MC_CMD_GET_CAPABILITIES_V5_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_LBN 1215685#define MC_CMD_GET_CAPABILITIES_V5_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 115686#define MC_CMD_GET_CAPABILITIES_V5_OUT_MCDI_BACKGROUND_OFST 2015687#define MC_CMD_GET_CAPABILITIES_V5_OUT_MCDI_BACKGROUND_LBN 1315688#define MC_CMD_GET_CAPABILITIES_V5_OUT_MCDI_BACKGROUND_WIDTH 115689#define MC_CMD_GET_CAPABILITIES_V5_OUT_MCDI_DB_RETURN_OFST 2015690#define MC_CMD_GET_CAPABILITIES_V5_OUT_MCDI_DB_RETURN_LBN 1415691#define MC_CMD_GET_CAPABILITIES_V5_OUT_MCDI_DB_RETURN_WIDTH 115692#define MC_CMD_GET_CAPABILITIES_V5_OUT_CTPIO_OFST 2015693#define MC_CMD_GET_CAPABILITIES_V5_OUT_CTPIO_LBN 1515694#define MC_CMD_GET_CAPABILITIES_V5_OUT_CTPIO_WIDTH 115695#define MC_CMD_GET_CAPABILITIES_V5_OUT_TSA_SUPPORT_OFST 2015696#define MC_CMD_GET_CAPABILITIES_V5_OUT_TSA_SUPPORT_LBN 1615697#define MC_CMD_GET_CAPABILITIES_V5_OUT_TSA_SUPPORT_WIDTH 115698#define MC_CMD_GET_CAPABILITIES_V5_OUT_TSA_BOUND_OFST 2015699#define MC_CMD_GET_CAPABILITIES_V5_OUT_TSA_BOUND_LBN 1715700#define MC_CMD_GET_CAPABILITIES_V5_OUT_TSA_BOUND_WIDTH 115701#define MC_CMD_GET_CAPABILITIES_V5_OUT_SF_ADAPTER_AUTHENTICATION_OFST 2015702#define MC_CMD_GET_CAPABILITIES_V5_OUT_SF_ADAPTER_AUTHENTICATION_LBN 1815703#define MC_CMD_GET_CAPABILITIES_V5_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 115704#define MC_CMD_GET_CAPABILITIES_V5_OUT_FILTER_ACTION_FLAG_OFST 2015705#define MC_CMD_GET_CAPABILITIES_V5_OUT_FILTER_ACTION_FLAG_LBN 1915706#define MC_CMD_GET_CAPABILITIES_V5_OUT_FILTER_ACTION_FLAG_WIDTH 115707#define MC_CMD_GET_CAPABILITIES_V5_OUT_FILTER_ACTION_MARK_OFST 2015708#define MC_CMD_GET_CAPABILITIES_V5_OUT_FILTER_ACTION_MARK_LBN 2015709#define MC_CMD_GET_CAPABILITIES_V5_OUT_FILTER_ACTION_MARK_WIDTH 115710#define MC_CMD_GET_CAPABILITIES_V5_OUT_EQUAL_STRIDE_SUPER_BUFFER_OFST 2015711#define MC_CMD_GET_CAPABILITIES_V5_OUT_EQUAL_STRIDE_SUPER_BUFFER_LBN 2115712#define MC_CMD_GET_CAPABILITIES_V5_OUT_EQUAL_STRIDE_SUPER_BUFFER_WIDTH 115713#define MC_CMD_GET_CAPABILITIES_V5_OUT_EQUAL_STRIDE_PACKED_STREAM_OFST 2015714#define MC_CMD_GET_CAPABILITIES_V5_OUT_EQUAL_STRIDE_PACKED_STREAM_LBN 2115715#define MC_CMD_GET_CAPABILITIES_V5_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 115716#define MC_CMD_GET_CAPABILITIES_V5_OUT_L3XUDP_SUPPORT_OFST 2015717#define MC_CMD_GET_CAPABILITIES_V5_OUT_L3XUDP_SUPPORT_LBN 2215718#define MC_CMD_GET_CAPABILITIES_V5_OUT_L3XUDP_SUPPORT_WIDTH 115719#define MC_CMD_GET_CAPABILITIES_V5_OUT_FW_SUBVARIANT_NO_TX_CSUM_OFST 2015720#define MC_CMD_GET_CAPABILITIES_V5_OUT_FW_SUBVARIANT_NO_TX_CSUM_LBN 2315721#define MC_CMD_GET_CAPABILITIES_V5_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 115722#define MC_CMD_GET_CAPABILITIES_V5_OUT_VI_SPREADING_OFST 2015723#define MC_CMD_GET_CAPABILITIES_V5_OUT_VI_SPREADING_LBN 2415724#define MC_CMD_GET_CAPABILITIES_V5_OUT_VI_SPREADING_WIDTH 115725#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_HLB_IDLE_OFST 2015726#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_HLB_IDLE_LBN 2515727#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_HLB_IDLE_WIDTH 115728#define MC_CMD_GET_CAPABILITIES_V5_OUT_INIT_RXQ_NO_CONT_EV_OFST 2015729#define MC_CMD_GET_CAPABILITIES_V5_OUT_INIT_RXQ_NO_CONT_EV_LBN 2615730#define MC_CMD_GET_CAPABILITIES_V5_OUT_INIT_RXQ_NO_CONT_EV_WIDTH 115731#define MC_CMD_GET_CAPABILITIES_V5_OUT_INIT_RXQ_WITH_BUFFER_SIZE_OFST 2015732#define MC_CMD_GET_CAPABILITIES_V5_OUT_INIT_RXQ_WITH_BUFFER_SIZE_LBN 2715733#define MC_CMD_GET_CAPABILITIES_V5_OUT_INIT_RXQ_WITH_BUFFER_SIZE_WIDTH 115734#define MC_CMD_GET_CAPABILITIES_V5_OUT_BUNDLE_UPDATE_OFST 2015735#define MC_CMD_GET_CAPABILITIES_V5_OUT_BUNDLE_UPDATE_LBN 2815736#define MC_CMD_GET_CAPABILITIES_V5_OUT_BUNDLE_UPDATE_WIDTH 115737#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V3_OFST 2015738#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V3_LBN 2915739#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V3_WIDTH 115740#define MC_CMD_GET_CAPABILITIES_V5_OUT_DYNAMIC_SENSORS_OFST 2015741#define MC_CMD_GET_CAPABILITIES_V5_OUT_DYNAMIC_SENSORS_LBN 3015742#define MC_CMD_GET_CAPABILITIES_V5_OUT_DYNAMIC_SENSORS_WIDTH 115743#define MC_CMD_GET_CAPABILITIES_V5_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_OFST 2015744#define MC_CMD_GET_CAPABILITIES_V5_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_LBN 3115745#define MC_CMD_GET_CAPABILITIES_V5_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_WIDTH 115746/* Number of FATSOv2 contexts per datapath supported by this NIC (when15747 * TX_TSO_V2 == 1). Not present on older firmware (check the length).15748 */15749#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V2_N_CONTEXTS_OFST 2415750#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V2_N_CONTEXTS_LEN 215751/* One byte per PF containing the number of the external port assigned to this15752 * PF, indexed by PF number. Special values indicate that a PF is either not15753 * present or not assigned.15754 */15755#define MC_CMD_GET_CAPABILITIES_V5_OUT_PFS_TO_PORTS_ASSIGNMENT_OFST 2615756#define MC_CMD_GET_CAPABILITIES_V5_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 115757#define MC_CMD_GET_CAPABILITIES_V5_OUT_PFS_TO_PORTS_ASSIGNMENT_NUM 1615758/* enum: The caller is not permitted to access information on this PF. */15759#define MC_CMD_GET_CAPABILITIES_V5_OUT_ACCESS_NOT_PERMITTED 0xff15760/* enum: PF does not exist. */15761#define MC_CMD_GET_CAPABILITIES_V5_OUT_PF_NOT_PRESENT 0xfe15762/* enum: PF does exist but is not assigned to any external port. */15763#define MC_CMD_GET_CAPABILITIES_V5_OUT_PF_NOT_ASSIGNED 0xfd15764/* enum: This value indicates that PF is assigned, but it cannot be expressed15765 * in this field. It is intended for a possible future situation where a more15766 * complex scheme of PFs to ports mapping is being used. The future driver15767 * should look for a new field supporting the new scheme. The current/old15768 * driver should treat this value as PF_NOT_ASSIGNED.15769 */15770#define MC_CMD_GET_CAPABILITIES_V5_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc15771/* One byte per PF containing the number of its VFs, indexed by PF number. A15772 * special value indicates that a PF is not present.15773 */15774#define MC_CMD_GET_CAPABILITIES_V5_OUT_NUM_VFS_PER_PF_OFST 4215775#define MC_CMD_GET_CAPABILITIES_V5_OUT_NUM_VFS_PER_PF_LEN 115776#define MC_CMD_GET_CAPABILITIES_V5_OUT_NUM_VFS_PER_PF_NUM 1615777/* enum: The caller is not permitted to access information on this PF. */15778/* MC_CMD_GET_CAPABILITIES_V5_OUT_ACCESS_NOT_PERMITTED 0xff */15779/* enum: PF does not exist. */15780/* MC_CMD_GET_CAPABILITIES_V5_OUT_PF_NOT_PRESENT 0xfe */15781/* Number of VIs available for each external port */15782#define MC_CMD_GET_CAPABILITIES_V5_OUT_NUM_VIS_PER_PORT_OFST 5815783#define MC_CMD_GET_CAPABILITIES_V5_OUT_NUM_VIS_PER_PORT_LEN 215784#define MC_CMD_GET_CAPABILITIES_V5_OUT_NUM_VIS_PER_PORT_NUM 415785/* Size of RX descriptor cache expressed as binary logarithm The actual size15786 * equals (2 ^ RX_DESC_CACHE_SIZE)15787 */15788#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_DESC_CACHE_SIZE_OFST 6615789#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_DESC_CACHE_SIZE_LEN 115790/* Size of TX descriptor cache expressed as binary logarithm The actual size15791 * equals (2 ^ TX_DESC_CACHE_SIZE)15792 */15793#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_DESC_CACHE_SIZE_OFST 6715794#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_DESC_CACHE_SIZE_LEN 115795/* Total number of available PIO buffers */15796#define MC_CMD_GET_CAPABILITIES_V5_OUT_NUM_PIO_BUFFS_OFST 6815797#define MC_CMD_GET_CAPABILITIES_V5_OUT_NUM_PIO_BUFFS_LEN 215798/* Size of a single PIO buffer */15799#define MC_CMD_GET_CAPABILITIES_V5_OUT_SIZE_PIO_BUFF_OFST 7015800#define MC_CMD_GET_CAPABILITIES_V5_OUT_SIZE_PIO_BUFF_LEN 215801/* On chips later than Medford the amount of address space assigned to each VI15802 * is configurable. This is a global setting that the driver must query to15803 * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available15804 * with 8k VI windows.15805 */15806#define MC_CMD_GET_CAPABILITIES_V5_OUT_VI_WINDOW_MODE_OFST 7215807#define MC_CMD_GET_CAPABILITIES_V5_OUT_VI_WINDOW_MODE_LEN 115808/* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k.15809 * CTPIO is not mapped.15810 */15811#define MC_CMD_GET_CAPABILITIES_V5_OUT_VI_WINDOW_MODE_8K 0x015812/* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */15813#define MC_CMD_GET_CAPABILITIES_V5_OUT_VI_WINDOW_MODE_16K 0x115814/* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */15815#define MC_CMD_GET_CAPABILITIES_V5_OUT_VI_WINDOW_MODE_64K 0x215816/* Number of vFIFOs per adapter that can be used for VFIFO Stuffing15817 * (SF-115995-SW) in the present configuration of firmware and port mode.15818 */15819#define MC_CMD_GET_CAPABILITIES_V5_OUT_VFIFO_STUFFING_NUM_VFIFOS_OFST 7315820#define MC_CMD_GET_CAPABILITIES_V5_OUT_VFIFO_STUFFING_NUM_VFIFOS_LEN 115821/* Number of buffers per adapter that can be used for VFIFO Stuffing15822 * (SF-115995-SW) in the present configuration of firmware and port mode.15823 */15824#define MC_CMD_GET_CAPABILITIES_V5_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_OFST 7415825#define MC_CMD_GET_CAPABILITIES_V5_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_LEN 215826/* Entry count in the MAC stats array, including the final GENERATION_END15827 * entry. For MAC stats DMA, drivers should allocate a buffer large enough to15828 * hold at least this many 64-bit stats values, if they wish to receive all15829 * available stats. If the buffer is shorter than MAC_STATS_NUM_STATS * 8, the15830 * stats array returned will be truncated.15831 */15832#define MC_CMD_GET_CAPABILITIES_V5_OUT_MAC_STATS_NUM_STATS_OFST 7615833#define MC_CMD_GET_CAPABILITIES_V5_OUT_MAC_STATS_NUM_STATS_LEN 215834/* Maximum supported value for MC_CMD_FILTER_OP_V3/MATCH_MARK_VALUE. This field15835 * will only be non-zero if MC_CMD_GET_CAPABILITIES/FILTER_ACTION_MARK is set.15836 */15837#define MC_CMD_GET_CAPABILITIES_V5_OUT_FILTER_ACTION_MARK_MAX_OFST 8015838#define MC_CMD_GET_CAPABILITIES_V5_OUT_FILTER_ACTION_MARK_MAX_LEN 415839 15840/* MC_CMD_GET_CAPABILITIES_V6_OUT msgresponse */15841#define MC_CMD_GET_CAPABILITIES_V6_OUT_LEN 14815842/* First word of flags. */15843#define MC_CMD_GET_CAPABILITIES_V6_OUT_FLAGS1_OFST 015844#define MC_CMD_GET_CAPABILITIES_V6_OUT_FLAGS1_LEN 415845#define MC_CMD_GET_CAPABILITIES_V6_OUT_VPORT_RECONFIGURE_OFST 015846#define MC_CMD_GET_CAPABILITIES_V6_OUT_VPORT_RECONFIGURE_LBN 315847#define MC_CMD_GET_CAPABILITIES_V6_OUT_VPORT_RECONFIGURE_WIDTH 115848#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_STRIPING_OFST 015849#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_STRIPING_LBN 415850#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_STRIPING_WIDTH 115851#define MC_CMD_GET_CAPABILITIES_V6_OUT_VADAPTOR_QUERY_OFST 015852#define MC_CMD_GET_CAPABILITIES_V6_OUT_VADAPTOR_QUERY_LBN 515853#define MC_CMD_GET_CAPABILITIES_V6_OUT_VADAPTOR_QUERY_WIDTH 115854#define MC_CMD_GET_CAPABILITIES_V6_OUT_EVB_PORT_VLAN_RESTRICT_OFST 015855#define MC_CMD_GET_CAPABILITIES_V6_OUT_EVB_PORT_VLAN_RESTRICT_LBN 615856#define MC_CMD_GET_CAPABILITIES_V6_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 115857#define MC_CMD_GET_CAPABILITIES_V6_OUT_DRV_ATTACH_PREBOOT_OFST 015858#define MC_CMD_GET_CAPABILITIES_V6_OUT_DRV_ATTACH_PREBOOT_LBN 715859#define MC_CMD_GET_CAPABILITIES_V6_OUT_DRV_ATTACH_PREBOOT_WIDTH 115860#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_FORCE_EVENT_MERGING_OFST 015861#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_FORCE_EVENT_MERGING_LBN 815862#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_FORCE_EVENT_MERGING_WIDTH 115863#define MC_CMD_GET_CAPABILITIES_V6_OUT_SET_MAC_ENHANCED_OFST 015864#define MC_CMD_GET_CAPABILITIES_V6_OUT_SET_MAC_ENHANCED_LBN 915865#define MC_CMD_GET_CAPABILITIES_V6_OUT_SET_MAC_ENHANCED_WIDTH 115866#define MC_CMD_GET_CAPABILITIES_V6_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 015867#define MC_CMD_GET_CAPABILITIES_V6_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 1015868#define MC_CMD_GET_CAPABILITIES_V6_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 115869#define MC_CMD_GET_CAPABILITIES_V6_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 015870#define MC_CMD_GET_CAPABILITIES_V6_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 1115871#define MC_CMD_GET_CAPABILITIES_V6_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 115872#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_MAC_SECURITY_FILTERING_OFST 015873#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_MAC_SECURITY_FILTERING_LBN 1215874#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 115875#define MC_CMD_GET_CAPABILITIES_V6_OUT_ADDITIONAL_RSS_MODES_OFST 015876#define MC_CMD_GET_CAPABILITIES_V6_OUT_ADDITIONAL_RSS_MODES_LBN 1315877#define MC_CMD_GET_CAPABILITIES_V6_OUT_ADDITIONAL_RSS_MODES_WIDTH 115878#define MC_CMD_GET_CAPABILITIES_V6_OUT_QBB_OFST 015879#define MC_CMD_GET_CAPABILITIES_V6_OUT_QBB_LBN 1415880#define MC_CMD_GET_CAPABILITIES_V6_OUT_QBB_WIDTH 115881#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 015882#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 1515883#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 115884#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_RSS_LIMITED_OFST 015885#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_RSS_LIMITED_LBN 1615886#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_RSS_LIMITED_WIDTH 115887#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PACKED_STREAM_OFST 015888#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PACKED_STREAM_LBN 1715889#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PACKED_STREAM_WIDTH 115890#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_INCLUDE_FCS_OFST 015891#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_INCLUDE_FCS_LBN 1815892#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_INCLUDE_FCS_WIDTH 115893#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_VLAN_INSERTION_OFST 015894#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_VLAN_INSERTION_LBN 1915895#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_VLAN_INSERTION_WIDTH 115896#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_VLAN_STRIPPING_OFST 015897#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_VLAN_STRIPPING_LBN 2015898#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_VLAN_STRIPPING_WIDTH 115899#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_OFST 015900#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_LBN 2115901#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_WIDTH 115902#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PREFIX_LEN_0_OFST 015903#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PREFIX_LEN_0_LBN 2215904#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PREFIX_LEN_0_WIDTH 115905#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PREFIX_LEN_14_OFST 015906#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PREFIX_LEN_14_LBN 2315907#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PREFIX_LEN_14_WIDTH 115908#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_TIMESTAMP_OFST 015909#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_TIMESTAMP_LBN 2415910#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_TIMESTAMP_WIDTH 115911#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_BATCHING_OFST 015912#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_BATCHING_LBN 2515913#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_BATCHING_WIDTH 115914#define MC_CMD_GET_CAPABILITIES_V6_OUT_MCAST_FILTER_CHAINING_OFST 015915#define MC_CMD_GET_CAPABILITIES_V6_OUT_MCAST_FILTER_CHAINING_LBN 2615916#define MC_CMD_GET_CAPABILITIES_V6_OUT_MCAST_FILTER_CHAINING_WIDTH 115917#define MC_CMD_GET_CAPABILITIES_V6_OUT_PM_AND_RXDP_COUNTERS_OFST 015918#define MC_CMD_GET_CAPABILITIES_V6_OUT_PM_AND_RXDP_COUNTERS_LBN 2715919#define MC_CMD_GET_CAPABILITIES_V6_OUT_PM_AND_RXDP_COUNTERS_WIDTH 115920#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_DISABLE_SCATTER_OFST 015921#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_DISABLE_SCATTER_LBN 2815922#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_DISABLE_SCATTER_WIDTH 115923#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_MCAST_UDP_LOOPBACK_OFST 015924#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_MCAST_UDP_LOOPBACK_LBN 2915925#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 115926#define MC_CMD_GET_CAPABILITIES_V6_OUT_EVB_OFST 015927#define MC_CMD_GET_CAPABILITIES_V6_OUT_EVB_LBN 3015928#define MC_CMD_GET_CAPABILITIES_V6_OUT_EVB_WIDTH 115929#define MC_CMD_GET_CAPABILITIES_V6_OUT_VXLAN_NVGRE_OFST 015930#define MC_CMD_GET_CAPABILITIES_V6_OUT_VXLAN_NVGRE_LBN 3115931#define MC_CMD_GET_CAPABILITIES_V6_OUT_VXLAN_NVGRE_WIDTH 115932/* RxDPCPU firmware id. */15933#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_DPCPU_FW_ID_OFST 415934#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_DPCPU_FW_ID_LEN 215935/* enum: Standard RXDP firmware */15936#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP 0x015937/* enum: Low latency RXDP firmware */15938#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_LOW_LATENCY 0x115939/* enum: Packed stream RXDP firmware */15940#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_PACKED_STREAM 0x215941/* enum: Rules engine RXDP firmware */15942#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_RULES_ENGINE 0x515943/* enum: DPDK RXDP firmware */15944#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_DPDK 0x615945/* enum: BIST RXDP firmware */15946#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_BIST 0x10a15947/* enum: RXDP Test firmware image 1 */15948#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x10115949/* enum: RXDP Test firmware image 2 */15950#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x10215951/* enum: RXDP Test firmware image 3 */15952#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x10315953/* enum: RXDP Test firmware image 4 */15954#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x10415955/* enum: RXDP Test firmware image 5 */15956#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_BACKPRESSURE 0x10515957/* enum: RXDP Test firmware image 6 */15958#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_FW_PACKET_EDITS 0x10615959/* enum: RXDP Test firmware image 7 */15960#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x10715961/* enum: RXDP Test firmware image 8 */15962#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_FW_DISABLE_DL 0x10815963/* enum: RXDP Test firmware image 9 */15964#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b15965/* enum: RXDP Test firmware image 10 */15966#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_FW_SLOW 0x10c15967/* TxDPCPU firmware id. */15968#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_DPCPU_FW_ID_OFST 615969#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_DPCPU_FW_ID_LEN 215970/* enum: Standard TXDP firmware */15971#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXDP 0x015972/* enum: Low latency TXDP firmware */15973#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXDP_LOW_LATENCY 0x115974/* enum: High packet rate TXDP firmware */15975#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXDP_HIGH_PACKET_RATE 0x315976/* enum: Rules engine TXDP firmware */15977#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXDP_RULES_ENGINE 0x515978/* enum: DPDK TXDP firmware */15979#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXDP_DPDK 0x615980/* enum: BIST TXDP firmware */15981#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXDP_BIST 0x12d15982/* enum: TXDP Test firmware image 1 */15983#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXDP_TEST_FW_TSO_EDIT 0x10115984/* enum: TXDP Test firmware image 2 */15985#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXDP_TEST_FW_PACKET_EDITS 0x10215986/* enum: TXDP CSR bus test firmware */15987#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXDP_TEST_FW_CSR 0x10315988#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_VERSION_OFST 815989#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_VERSION_LEN 215990#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_VERSION_REV_OFST 815991#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_VERSION_REV_LBN 015992#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_VERSION_REV_WIDTH 1215993#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_VERSION_TYPE_OFST 815994#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_VERSION_TYPE_LBN 1215995#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_VERSION_TYPE_WIDTH 415996/* enum: reserved value - do not use (may indicate alternative interpretation15997 * of REV field in future)15998 */15999#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_RESERVED 0x016000/* enum: Trivial RX PD firmware for early Huntington development (Huntington16001 * development only)16002 */16003#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_FIRST_PKT 0x116004/* enum: RX PD firmware for telemetry prototyping (Medford2 development only)16005 */16006#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x116007/* enum: RX PD firmware with approximately Siena-compatible behaviour16008 * (Huntington development only)16009 */16010#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x216011/* enum: Full featured RX PD production firmware */16012#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x316013/* enum: (deprecated original name for the FULL_FEATURED variant) */16014#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_VSWITCH 0x316015/* enum: siena_compat variant RX PD firmware using PM rather than MAC16016 * (Huntington development only)16017 */16018#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x416019/* enum: Low latency RX PD production firmware */16020#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x516021/* enum: Packed stream RX PD production firmware */16022#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x616023/* enum: RX PD firmware handling layer 2 only for high packet rate performance16024 * tests (Medford development only)16025 */16026#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x716027/* enum: Rules engine RX PD production firmware */16028#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x816029/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */16030#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_L3XUDP 0x916031/* enum: DPDK RX PD production firmware */16032#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_DPDK 0xa16033/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */16034#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe16035/* enum: RX PD firmware parsing but not filtering network overlay tunnel16036 * encapsulations (Medford development only)16037 */16038#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf16039#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_VERSION_OFST 1016040#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_VERSION_LEN 216041#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_VERSION_REV_OFST 1016042#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_VERSION_REV_LBN 016043#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_VERSION_REV_WIDTH 1216044#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_VERSION_TYPE_OFST 1016045#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_VERSION_TYPE_LBN 1216046#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_VERSION_TYPE_WIDTH 416047/* enum: reserved value - do not use (may indicate alternative interpretation16048 * of REV field in future)16049 */16050#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_RESERVED 0x016051/* enum: Trivial TX PD firmware for early Huntington development (Huntington16052 * development only)16053 */16054#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_FIRST_PKT 0x116055/* enum: TX PD firmware for telemetry prototyping (Medford2 development only)16056 */16057#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x116058/* enum: TX PD firmware with approximately Siena-compatible behaviour16059 * (Huntington development only)16060 */16061#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x216062/* enum: Full featured TX PD production firmware */16063#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x316064/* enum: (deprecated original name for the FULL_FEATURED variant) */16065#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_VSWITCH 0x316066/* enum: siena_compat variant TX PD firmware using PM rather than MAC16067 * (Huntington development only)16068 */16069#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x416070#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */16071/* enum: TX PD firmware handling layer 2 only for high packet rate performance16072 * tests (Medford development only)16073 */16074#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x716075/* enum: Rules engine TX PD production firmware */16076#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x816077/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */16078#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_L3XUDP 0x916079/* enum: DPDK TX PD production firmware */16080#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_DPDK 0xa16081/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */16082#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe16083/* Hardware capabilities of NIC */16084#define MC_CMD_GET_CAPABILITIES_V6_OUT_HW_CAPABILITIES_OFST 1216085#define MC_CMD_GET_CAPABILITIES_V6_OUT_HW_CAPABILITIES_LEN 416086/* Licensed capabilities */16087#define MC_CMD_GET_CAPABILITIES_V6_OUT_LICENSE_CAPABILITIES_OFST 1616088#define MC_CMD_GET_CAPABILITIES_V6_OUT_LICENSE_CAPABILITIES_LEN 416089/* Second word of flags. Not present on older firmware (check the length). */16090#define MC_CMD_GET_CAPABILITIES_V6_OUT_FLAGS2_OFST 2016091#define MC_CMD_GET_CAPABILITIES_V6_OUT_FLAGS2_LEN 416092#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_V2_OFST 2016093#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_V2_LBN 016094#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_V2_WIDTH 116095#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_V2_ENCAP_OFST 2016096#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_V2_ENCAP_LBN 116097#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_V2_ENCAP_WIDTH 116098#define MC_CMD_GET_CAPABILITIES_V6_OUT_EVQ_TIMER_CTRL_OFST 2016099#define MC_CMD_GET_CAPABILITIES_V6_OUT_EVQ_TIMER_CTRL_LBN 216100#define MC_CMD_GET_CAPABILITIES_V6_OUT_EVQ_TIMER_CTRL_WIDTH 116101#define MC_CMD_GET_CAPABILITIES_V6_OUT_EVENT_CUT_THROUGH_OFST 2016102#define MC_CMD_GET_CAPABILITIES_V6_OUT_EVENT_CUT_THROUGH_LBN 316103#define MC_CMD_GET_CAPABILITIES_V6_OUT_EVENT_CUT_THROUGH_WIDTH 116104#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_CUT_THROUGH_OFST 2016105#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_CUT_THROUGH_LBN 416106#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_CUT_THROUGH_WIDTH 116107#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_VFIFO_ULL_MODE_OFST 2016108#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_VFIFO_ULL_MODE_LBN 516109#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_VFIFO_ULL_MODE_WIDTH 116110#define MC_CMD_GET_CAPABILITIES_V6_OUT_MAC_STATS_40G_TX_SIZE_BINS_OFST 2016111#define MC_CMD_GET_CAPABILITIES_V6_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 616112#define MC_CMD_GET_CAPABILITIES_V6_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 116113#define MC_CMD_GET_CAPABILITIES_V6_OUT_INIT_EVQ_TYPE_SUPPORTED_OFST 2016114#define MC_CMD_GET_CAPABILITIES_V6_OUT_INIT_EVQ_TYPE_SUPPORTED_LBN 716115#define MC_CMD_GET_CAPABILITIES_V6_OUT_INIT_EVQ_TYPE_SUPPORTED_WIDTH 116116#define MC_CMD_GET_CAPABILITIES_V6_OUT_INIT_EVQ_V2_OFST 2016117#define MC_CMD_GET_CAPABILITIES_V6_OUT_INIT_EVQ_V2_LBN 716118#define MC_CMD_GET_CAPABILITIES_V6_OUT_INIT_EVQ_V2_WIDTH 116119#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_MAC_TIMESTAMPING_OFST 2016120#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_MAC_TIMESTAMPING_LBN 816121#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_MAC_TIMESTAMPING_WIDTH 116122#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TIMESTAMP_OFST 2016123#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TIMESTAMP_LBN 916124#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TIMESTAMP_WIDTH 116125#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_SNIFF_OFST 2016126#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_SNIFF_LBN 1016127#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_SNIFF_WIDTH 116128#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_SNIFF_OFST 2016129#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_SNIFF_LBN 1116130#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_SNIFF_WIDTH 116131#define MC_CMD_GET_CAPABILITIES_V6_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_OFST 2016132#define MC_CMD_GET_CAPABILITIES_V6_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_LBN 1216133#define MC_CMD_GET_CAPABILITIES_V6_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 116134#define MC_CMD_GET_CAPABILITIES_V6_OUT_MCDI_BACKGROUND_OFST 2016135#define MC_CMD_GET_CAPABILITIES_V6_OUT_MCDI_BACKGROUND_LBN 1316136#define MC_CMD_GET_CAPABILITIES_V6_OUT_MCDI_BACKGROUND_WIDTH 116137#define MC_CMD_GET_CAPABILITIES_V6_OUT_MCDI_DB_RETURN_OFST 2016138#define MC_CMD_GET_CAPABILITIES_V6_OUT_MCDI_DB_RETURN_LBN 1416139#define MC_CMD_GET_CAPABILITIES_V6_OUT_MCDI_DB_RETURN_WIDTH 116140#define MC_CMD_GET_CAPABILITIES_V6_OUT_CTPIO_OFST 2016141#define MC_CMD_GET_CAPABILITIES_V6_OUT_CTPIO_LBN 1516142#define MC_CMD_GET_CAPABILITIES_V6_OUT_CTPIO_WIDTH 116143#define MC_CMD_GET_CAPABILITIES_V6_OUT_TSA_SUPPORT_OFST 2016144#define MC_CMD_GET_CAPABILITIES_V6_OUT_TSA_SUPPORT_LBN 1616145#define MC_CMD_GET_CAPABILITIES_V6_OUT_TSA_SUPPORT_WIDTH 116146#define MC_CMD_GET_CAPABILITIES_V6_OUT_TSA_BOUND_OFST 2016147#define MC_CMD_GET_CAPABILITIES_V6_OUT_TSA_BOUND_LBN 1716148#define MC_CMD_GET_CAPABILITIES_V6_OUT_TSA_BOUND_WIDTH 116149#define MC_CMD_GET_CAPABILITIES_V6_OUT_SF_ADAPTER_AUTHENTICATION_OFST 2016150#define MC_CMD_GET_CAPABILITIES_V6_OUT_SF_ADAPTER_AUTHENTICATION_LBN 1816151#define MC_CMD_GET_CAPABILITIES_V6_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 116152#define MC_CMD_GET_CAPABILITIES_V6_OUT_FILTER_ACTION_FLAG_OFST 2016153#define MC_CMD_GET_CAPABILITIES_V6_OUT_FILTER_ACTION_FLAG_LBN 1916154#define MC_CMD_GET_CAPABILITIES_V6_OUT_FILTER_ACTION_FLAG_WIDTH 116155#define MC_CMD_GET_CAPABILITIES_V6_OUT_FILTER_ACTION_MARK_OFST 2016156#define MC_CMD_GET_CAPABILITIES_V6_OUT_FILTER_ACTION_MARK_LBN 2016157#define MC_CMD_GET_CAPABILITIES_V6_OUT_FILTER_ACTION_MARK_WIDTH 116158#define MC_CMD_GET_CAPABILITIES_V6_OUT_EQUAL_STRIDE_SUPER_BUFFER_OFST 2016159#define MC_CMD_GET_CAPABILITIES_V6_OUT_EQUAL_STRIDE_SUPER_BUFFER_LBN 2116160#define MC_CMD_GET_CAPABILITIES_V6_OUT_EQUAL_STRIDE_SUPER_BUFFER_WIDTH 116161#define MC_CMD_GET_CAPABILITIES_V6_OUT_EQUAL_STRIDE_PACKED_STREAM_OFST 2016162#define MC_CMD_GET_CAPABILITIES_V6_OUT_EQUAL_STRIDE_PACKED_STREAM_LBN 2116163#define MC_CMD_GET_CAPABILITIES_V6_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 116164#define MC_CMD_GET_CAPABILITIES_V6_OUT_L3XUDP_SUPPORT_OFST 2016165#define MC_CMD_GET_CAPABILITIES_V6_OUT_L3XUDP_SUPPORT_LBN 2216166#define MC_CMD_GET_CAPABILITIES_V6_OUT_L3XUDP_SUPPORT_WIDTH 116167#define MC_CMD_GET_CAPABILITIES_V6_OUT_FW_SUBVARIANT_NO_TX_CSUM_OFST 2016168#define MC_CMD_GET_CAPABILITIES_V6_OUT_FW_SUBVARIANT_NO_TX_CSUM_LBN 2316169#define MC_CMD_GET_CAPABILITIES_V6_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 116170#define MC_CMD_GET_CAPABILITIES_V6_OUT_VI_SPREADING_OFST 2016171#define MC_CMD_GET_CAPABILITIES_V6_OUT_VI_SPREADING_LBN 2416172#define MC_CMD_GET_CAPABILITIES_V6_OUT_VI_SPREADING_WIDTH 116173#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_HLB_IDLE_OFST 2016174#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_HLB_IDLE_LBN 2516175#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_HLB_IDLE_WIDTH 116176#define MC_CMD_GET_CAPABILITIES_V6_OUT_INIT_RXQ_NO_CONT_EV_OFST 2016177#define MC_CMD_GET_CAPABILITIES_V6_OUT_INIT_RXQ_NO_CONT_EV_LBN 2616178#define MC_CMD_GET_CAPABILITIES_V6_OUT_INIT_RXQ_NO_CONT_EV_WIDTH 116179#define MC_CMD_GET_CAPABILITIES_V6_OUT_INIT_RXQ_WITH_BUFFER_SIZE_OFST 2016180#define MC_CMD_GET_CAPABILITIES_V6_OUT_INIT_RXQ_WITH_BUFFER_SIZE_LBN 2716181#define MC_CMD_GET_CAPABILITIES_V6_OUT_INIT_RXQ_WITH_BUFFER_SIZE_WIDTH 116182#define MC_CMD_GET_CAPABILITIES_V6_OUT_BUNDLE_UPDATE_OFST 2016183#define MC_CMD_GET_CAPABILITIES_V6_OUT_BUNDLE_UPDATE_LBN 2816184#define MC_CMD_GET_CAPABILITIES_V6_OUT_BUNDLE_UPDATE_WIDTH 116185#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_V3_OFST 2016186#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_V3_LBN 2916187#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_V3_WIDTH 116188#define MC_CMD_GET_CAPABILITIES_V6_OUT_DYNAMIC_SENSORS_OFST 2016189#define MC_CMD_GET_CAPABILITIES_V6_OUT_DYNAMIC_SENSORS_LBN 3016190#define MC_CMD_GET_CAPABILITIES_V6_OUT_DYNAMIC_SENSORS_WIDTH 116191#define MC_CMD_GET_CAPABILITIES_V6_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_OFST 2016192#define MC_CMD_GET_CAPABILITIES_V6_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_LBN 3116193#define MC_CMD_GET_CAPABILITIES_V6_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_WIDTH 116194/* Number of FATSOv2 contexts per datapath supported by this NIC (when16195 * TX_TSO_V2 == 1). Not present on older firmware (check the length).16196 */16197#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_V2_N_CONTEXTS_OFST 2416198#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_V2_N_CONTEXTS_LEN 216199/* One byte per PF containing the number of the external port assigned to this16200 * PF, indexed by PF number. Special values indicate that a PF is either not16201 * present or not assigned.16202 */16203#define MC_CMD_GET_CAPABILITIES_V6_OUT_PFS_TO_PORTS_ASSIGNMENT_OFST 2616204#define MC_CMD_GET_CAPABILITIES_V6_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 116205#define MC_CMD_GET_CAPABILITIES_V6_OUT_PFS_TO_PORTS_ASSIGNMENT_NUM 1616206/* enum: The caller is not permitted to access information on this PF. */16207#define MC_CMD_GET_CAPABILITIES_V6_OUT_ACCESS_NOT_PERMITTED 0xff16208/* enum: PF does not exist. */16209#define MC_CMD_GET_CAPABILITIES_V6_OUT_PF_NOT_PRESENT 0xfe16210/* enum: PF does exist but is not assigned to any external port. */16211#define MC_CMD_GET_CAPABILITIES_V6_OUT_PF_NOT_ASSIGNED 0xfd16212/* enum: This value indicates that PF is assigned, but it cannot be expressed16213 * in this field. It is intended for a possible future situation where a more16214 * complex scheme of PFs to ports mapping is being used. The future driver16215 * should look for a new field supporting the new scheme. The current/old16216 * driver should treat this value as PF_NOT_ASSIGNED.16217 */16218#define MC_CMD_GET_CAPABILITIES_V6_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc16219/* One byte per PF containing the number of its VFs, indexed by PF number. A16220 * special value indicates that a PF is not present.16221 */16222#define MC_CMD_GET_CAPABILITIES_V6_OUT_NUM_VFS_PER_PF_OFST 4216223#define MC_CMD_GET_CAPABILITIES_V6_OUT_NUM_VFS_PER_PF_LEN 116224#define MC_CMD_GET_CAPABILITIES_V6_OUT_NUM_VFS_PER_PF_NUM 1616225/* enum: The caller is not permitted to access information on this PF. */16226/* MC_CMD_GET_CAPABILITIES_V6_OUT_ACCESS_NOT_PERMITTED 0xff */16227/* enum: PF does not exist. */16228/* MC_CMD_GET_CAPABILITIES_V6_OUT_PF_NOT_PRESENT 0xfe */16229/* Number of VIs available for each external port */16230#define MC_CMD_GET_CAPABILITIES_V6_OUT_NUM_VIS_PER_PORT_OFST 5816231#define MC_CMD_GET_CAPABILITIES_V6_OUT_NUM_VIS_PER_PORT_LEN 216232#define MC_CMD_GET_CAPABILITIES_V6_OUT_NUM_VIS_PER_PORT_NUM 416233/* Size of RX descriptor cache expressed as binary logarithm The actual size16234 * equals (2 ^ RX_DESC_CACHE_SIZE)16235 */16236#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_DESC_CACHE_SIZE_OFST 6616237#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_DESC_CACHE_SIZE_LEN 116238/* Size of TX descriptor cache expressed as binary logarithm The actual size16239 * equals (2 ^ TX_DESC_CACHE_SIZE)16240 */16241#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_DESC_CACHE_SIZE_OFST 6716242#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_DESC_CACHE_SIZE_LEN 116243/* Total number of available PIO buffers */16244#define MC_CMD_GET_CAPABILITIES_V6_OUT_NUM_PIO_BUFFS_OFST 6816245#define MC_CMD_GET_CAPABILITIES_V6_OUT_NUM_PIO_BUFFS_LEN 216246/* Size of a single PIO buffer */16247#define MC_CMD_GET_CAPABILITIES_V6_OUT_SIZE_PIO_BUFF_OFST 7016248#define MC_CMD_GET_CAPABILITIES_V6_OUT_SIZE_PIO_BUFF_LEN 216249/* On chips later than Medford the amount of address space assigned to each VI16250 * is configurable. This is a global setting that the driver must query to16251 * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available16252 * with 8k VI windows.16253 */16254#define MC_CMD_GET_CAPABILITIES_V6_OUT_VI_WINDOW_MODE_OFST 7216255#define MC_CMD_GET_CAPABILITIES_V6_OUT_VI_WINDOW_MODE_LEN 116256/* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k.16257 * CTPIO is not mapped.16258 */16259#define MC_CMD_GET_CAPABILITIES_V6_OUT_VI_WINDOW_MODE_8K 0x016260/* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */16261#define MC_CMD_GET_CAPABILITIES_V6_OUT_VI_WINDOW_MODE_16K 0x116262/* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */16263#define MC_CMD_GET_CAPABILITIES_V6_OUT_VI_WINDOW_MODE_64K 0x216264/* Number of vFIFOs per adapter that can be used for VFIFO Stuffing16265 * (SF-115995-SW) in the present configuration of firmware and port mode.16266 */16267#define MC_CMD_GET_CAPABILITIES_V6_OUT_VFIFO_STUFFING_NUM_VFIFOS_OFST 7316268#define MC_CMD_GET_CAPABILITIES_V6_OUT_VFIFO_STUFFING_NUM_VFIFOS_LEN 116269/* Number of buffers per adapter that can be used for VFIFO Stuffing16270 * (SF-115995-SW) in the present configuration of firmware and port mode.16271 */16272#define MC_CMD_GET_CAPABILITIES_V6_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_OFST 7416273#define MC_CMD_GET_CAPABILITIES_V6_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_LEN 216274/* Entry count in the MAC stats array, including the final GENERATION_END16275 * entry. For MAC stats DMA, drivers should allocate a buffer large enough to16276 * hold at least this many 64-bit stats values, if they wish to receive all16277 * available stats. If the buffer is shorter than MAC_STATS_NUM_STATS * 8, the16278 * stats array returned will be truncated.16279 */16280#define MC_CMD_GET_CAPABILITIES_V6_OUT_MAC_STATS_NUM_STATS_OFST 7616281#define MC_CMD_GET_CAPABILITIES_V6_OUT_MAC_STATS_NUM_STATS_LEN 216282/* Maximum supported value for MC_CMD_FILTER_OP_V3/MATCH_MARK_VALUE. This field16283 * will only be non-zero if MC_CMD_GET_CAPABILITIES/FILTER_ACTION_MARK is set.16284 */16285#define MC_CMD_GET_CAPABILITIES_V6_OUT_FILTER_ACTION_MARK_MAX_OFST 8016286#define MC_CMD_GET_CAPABILITIES_V6_OUT_FILTER_ACTION_MARK_MAX_LEN 416287/* On devices where the INIT_RXQ_WITH_BUFFER_SIZE flag (in16288 * GET_CAPABILITIES_OUT_V2) is set, drivers have to specify a buffer size when16289 * they create an RX queue. Due to hardware limitations, only a small number of16290 * different buffer sizes may be available concurrently. Nonzero entries in16291 * this array are the sizes of buffers which the system guarantees will be16292 * available for use. If the list is empty, there are no limitations on16293 * concurrent buffer sizes.16294 */16295#define MC_CMD_GET_CAPABILITIES_V6_OUT_GUARANTEED_RX_BUFFER_SIZES_OFST 8416296#define MC_CMD_GET_CAPABILITIES_V6_OUT_GUARANTEED_RX_BUFFER_SIZES_LEN 416297#define MC_CMD_GET_CAPABILITIES_V6_OUT_GUARANTEED_RX_BUFFER_SIZES_NUM 1616298 16299/* MC_CMD_GET_CAPABILITIES_V7_OUT msgresponse */16300#define MC_CMD_GET_CAPABILITIES_V7_OUT_LEN 15216301/* First word of flags. */16302#define MC_CMD_GET_CAPABILITIES_V7_OUT_FLAGS1_OFST 016303#define MC_CMD_GET_CAPABILITIES_V7_OUT_FLAGS1_LEN 416304#define MC_CMD_GET_CAPABILITIES_V7_OUT_VPORT_RECONFIGURE_OFST 016305#define MC_CMD_GET_CAPABILITIES_V7_OUT_VPORT_RECONFIGURE_LBN 316306#define MC_CMD_GET_CAPABILITIES_V7_OUT_VPORT_RECONFIGURE_WIDTH 116307#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_STRIPING_OFST 016308#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_STRIPING_LBN 416309#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_STRIPING_WIDTH 116310#define MC_CMD_GET_CAPABILITIES_V7_OUT_VADAPTOR_QUERY_OFST 016311#define MC_CMD_GET_CAPABILITIES_V7_OUT_VADAPTOR_QUERY_LBN 516312#define MC_CMD_GET_CAPABILITIES_V7_OUT_VADAPTOR_QUERY_WIDTH 116313#define MC_CMD_GET_CAPABILITIES_V7_OUT_EVB_PORT_VLAN_RESTRICT_OFST 016314#define MC_CMD_GET_CAPABILITIES_V7_OUT_EVB_PORT_VLAN_RESTRICT_LBN 616315#define MC_CMD_GET_CAPABILITIES_V7_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 116316#define MC_CMD_GET_CAPABILITIES_V7_OUT_DRV_ATTACH_PREBOOT_OFST 016317#define MC_CMD_GET_CAPABILITIES_V7_OUT_DRV_ATTACH_PREBOOT_LBN 716318#define MC_CMD_GET_CAPABILITIES_V7_OUT_DRV_ATTACH_PREBOOT_WIDTH 116319#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_FORCE_EVENT_MERGING_OFST 016320#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_FORCE_EVENT_MERGING_LBN 816321#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_FORCE_EVENT_MERGING_WIDTH 116322#define MC_CMD_GET_CAPABILITIES_V7_OUT_SET_MAC_ENHANCED_OFST 016323#define MC_CMD_GET_CAPABILITIES_V7_OUT_SET_MAC_ENHANCED_LBN 916324#define MC_CMD_GET_CAPABILITIES_V7_OUT_SET_MAC_ENHANCED_WIDTH 116325#define MC_CMD_GET_CAPABILITIES_V7_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 016326#define MC_CMD_GET_CAPABILITIES_V7_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 1016327#define MC_CMD_GET_CAPABILITIES_V7_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 116328#define MC_CMD_GET_CAPABILITIES_V7_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 016329#define MC_CMD_GET_CAPABILITIES_V7_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 1116330#define MC_CMD_GET_CAPABILITIES_V7_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 116331#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_MAC_SECURITY_FILTERING_OFST 016332#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_MAC_SECURITY_FILTERING_LBN 1216333#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 116334#define MC_CMD_GET_CAPABILITIES_V7_OUT_ADDITIONAL_RSS_MODES_OFST 016335#define MC_CMD_GET_CAPABILITIES_V7_OUT_ADDITIONAL_RSS_MODES_LBN 1316336#define MC_CMD_GET_CAPABILITIES_V7_OUT_ADDITIONAL_RSS_MODES_WIDTH 116337#define MC_CMD_GET_CAPABILITIES_V7_OUT_QBB_OFST 016338#define MC_CMD_GET_CAPABILITIES_V7_OUT_QBB_LBN 1416339#define MC_CMD_GET_CAPABILITIES_V7_OUT_QBB_WIDTH 116340#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 016341#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 1516342#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 116343#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_RSS_LIMITED_OFST 016344#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_RSS_LIMITED_LBN 1616345#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_RSS_LIMITED_WIDTH 116346#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_PACKED_STREAM_OFST 016347#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_PACKED_STREAM_LBN 1716348#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_PACKED_STREAM_WIDTH 116349#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_INCLUDE_FCS_OFST 016350#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_INCLUDE_FCS_LBN 1816351#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_INCLUDE_FCS_WIDTH 116352#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_VLAN_INSERTION_OFST 016353#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_VLAN_INSERTION_LBN 1916354#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_VLAN_INSERTION_WIDTH 116355#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_VLAN_STRIPPING_OFST 016356#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_VLAN_STRIPPING_LBN 2016357#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_VLAN_STRIPPING_WIDTH 116358#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_OFST 016359#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_LBN 2116360#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_WIDTH 116361#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_PREFIX_LEN_0_OFST 016362#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_PREFIX_LEN_0_LBN 2216363#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_PREFIX_LEN_0_WIDTH 116364#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_PREFIX_LEN_14_OFST 016365#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_PREFIX_LEN_14_LBN 2316366#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_PREFIX_LEN_14_WIDTH 116367#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_TIMESTAMP_OFST 016368#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_TIMESTAMP_LBN 2416369#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_TIMESTAMP_WIDTH 116370#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_BATCHING_OFST 016371#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_BATCHING_LBN 2516372#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_BATCHING_WIDTH 116373#define MC_CMD_GET_CAPABILITIES_V7_OUT_MCAST_FILTER_CHAINING_OFST 016374#define MC_CMD_GET_CAPABILITIES_V7_OUT_MCAST_FILTER_CHAINING_LBN 2616375#define MC_CMD_GET_CAPABILITIES_V7_OUT_MCAST_FILTER_CHAINING_WIDTH 116376#define MC_CMD_GET_CAPABILITIES_V7_OUT_PM_AND_RXDP_COUNTERS_OFST 016377#define MC_CMD_GET_CAPABILITIES_V7_OUT_PM_AND_RXDP_COUNTERS_LBN 2716378#define MC_CMD_GET_CAPABILITIES_V7_OUT_PM_AND_RXDP_COUNTERS_WIDTH 116379#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_DISABLE_SCATTER_OFST 016380#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_DISABLE_SCATTER_LBN 2816381#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_DISABLE_SCATTER_WIDTH 116382#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_MCAST_UDP_LOOPBACK_OFST 016383#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_MCAST_UDP_LOOPBACK_LBN 2916384#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 116385#define MC_CMD_GET_CAPABILITIES_V7_OUT_EVB_OFST 016386#define MC_CMD_GET_CAPABILITIES_V7_OUT_EVB_LBN 3016387#define MC_CMD_GET_CAPABILITIES_V7_OUT_EVB_WIDTH 116388#define MC_CMD_GET_CAPABILITIES_V7_OUT_VXLAN_NVGRE_OFST 016389#define MC_CMD_GET_CAPABILITIES_V7_OUT_VXLAN_NVGRE_LBN 3116390#define MC_CMD_GET_CAPABILITIES_V7_OUT_VXLAN_NVGRE_WIDTH 116391/* RxDPCPU firmware id. */16392#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_DPCPU_FW_ID_OFST 416393#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_DPCPU_FW_ID_LEN 216394/* enum: Standard RXDP firmware */16395#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP 0x016396/* enum: Low latency RXDP firmware */16397#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_LOW_LATENCY 0x116398/* enum: Packed stream RXDP firmware */16399#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_PACKED_STREAM 0x216400/* enum: Rules engine RXDP firmware */16401#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_RULES_ENGINE 0x516402/* enum: DPDK RXDP firmware */16403#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_DPDK 0x616404/* enum: BIST RXDP firmware */16405#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_BIST 0x10a16406/* enum: RXDP Test firmware image 1 */16407#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x10116408/* enum: RXDP Test firmware image 2 */16409#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x10216410/* enum: RXDP Test firmware image 3 */16411#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x10316412/* enum: RXDP Test firmware image 4 */16413#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x10416414/* enum: RXDP Test firmware image 5 */16415#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_BACKPRESSURE 0x10516416/* enum: RXDP Test firmware image 6 */16417#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_FW_PACKET_EDITS 0x10616418/* enum: RXDP Test firmware image 7 */16419#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x10716420/* enum: RXDP Test firmware image 8 */16421#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_FW_DISABLE_DL 0x10816422/* enum: RXDP Test firmware image 9 */16423#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b16424/* enum: RXDP Test firmware image 10 */16425#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_FW_SLOW 0x10c16426/* TxDPCPU firmware id. */16427#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_DPCPU_FW_ID_OFST 616428#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_DPCPU_FW_ID_LEN 216429/* enum: Standard TXDP firmware */16430#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXDP 0x016431/* enum: Low latency TXDP firmware */16432#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXDP_LOW_LATENCY 0x116433/* enum: High packet rate TXDP firmware */16434#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXDP_HIGH_PACKET_RATE 0x316435/* enum: Rules engine TXDP firmware */16436#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXDP_RULES_ENGINE 0x516437/* enum: DPDK TXDP firmware */16438#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXDP_DPDK 0x616439/* enum: BIST TXDP firmware */16440#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXDP_BIST 0x12d16441/* enum: TXDP Test firmware image 1 */16442#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXDP_TEST_FW_TSO_EDIT 0x10116443/* enum: TXDP Test firmware image 2 */16444#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXDP_TEST_FW_PACKET_EDITS 0x10216445/* enum: TXDP CSR bus test firmware */16446#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXDP_TEST_FW_CSR 0x10316447#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_VERSION_OFST 816448#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_VERSION_LEN 216449#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_VERSION_REV_OFST 816450#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_VERSION_REV_LBN 016451#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_VERSION_REV_WIDTH 1216452#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_VERSION_TYPE_OFST 816453#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_VERSION_TYPE_LBN 1216454#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_VERSION_TYPE_WIDTH 416455/* enum: reserved value - do not use (may indicate alternative interpretation16456 * of REV field in future)16457 */16458#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_RESERVED 0x016459/* enum: Trivial RX PD firmware for early Huntington development (Huntington16460 * development only)16461 */16462#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_FIRST_PKT 0x116463/* enum: RX PD firmware for telemetry prototyping (Medford2 development only)16464 */16465#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x116466/* enum: RX PD firmware with approximately Siena-compatible behaviour16467 * (Huntington development only)16468 */16469#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x216470/* enum: Full featured RX PD production firmware */16471#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x316472/* enum: (deprecated original name for the FULL_FEATURED variant) */16473#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_VSWITCH 0x316474/* enum: siena_compat variant RX PD firmware using PM rather than MAC16475 * (Huntington development only)16476 */16477#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x416478/* enum: Low latency RX PD production firmware */16479#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x516480/* enum: Packed stream RX PD production firmware */16481#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x616482/* enum: RX PD firmware handling layer 2 only for high packet rate performance16483 * tests (Medford development only)16484 */16485#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x716486/* enum: Rules engine RX PD production firmware */16487#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x816488/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */16489#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_L3XUDP 0x916490/* enum: DPDK RX PD production firmware */16491#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_DPDK 0xa16492/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */16493#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe16494/* enum: RX PD firmware parsing but not filtering network overlay tunnel16495 * encapsulations (Medford development only)16496 */16497#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf16498#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_VERSION_OFST 1016499#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_VERSION_LEN 216500#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_VERSION_REV_OFST 1016501#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_VERSION_REV_LBN 016502#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_VERSION_REV_WIDTH 1216503#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_VERSION_TYPE_OFST 1016504#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_VERSION_TYPE_LBN 1216505#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_VERSION_TYPE_WIDTH 416506/* enum: reserved value - do not use (may indicate alternative interpretation16507 * of REV field in future)16508 */16509#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_RESERVED 0x016510/* enum: Trivial TX PD firmware for early Huntington development (Huntington16511 * development only)16512 */16513#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_FIRST_PKT 0x116514/* enum: TX PD firmware for telemetry prototyping (Medford2 development only)16515 */16516#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x116517/* enum: TX PD firmware with approximately Siena-compatible behaviour16518 * (Huntington development only)16519 */16520#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x216521/* enum: Full featured TX PD production firmware */16522#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x316523/* enum: (deprecated original name for the FULL_FEATURED variant) */16524#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_VSWITCH 0x316525/* enum: siena_compat variant TX PD firmware using PM rather than MAC16526 * (Huntington development only)16527 */16528#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x416529#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */16530/* enum: TX PD firmware handling layer 2 only for high packet rate performance16531 * tests (Medford development only)16532 */16533#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x716534/* enum: Rules engine TX PD production firmware */16535#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x816536/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */16537#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_L3XUDP 0x916538/* enum: DPDK TX PD production firmware */16539#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_DPDK 0xa16540/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */16541#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe16542/* Hardware capabilities of NIC */16543#define MC_CMD_GET_CAPABILITIES_V7_OUT_HW_CAPABILITIES_OFST 1216544#define MC_CMD_GET_CAPABILITIES_V7_OUT_HW_CAPABILITIES_LEN 416545/* Licensed capabilities */16546#define MC_CMD_GET_CAPABILITIES_V7_OUT_LICENSE_CAPABILITIES_OFST 1616547#define MC_CMD_GET_CAPABILITIES_V7_OUT_LICENSE_CAPABILITIES_LEN 416548/* Second word of flags. Not present on older firmware (check the length). */16549#define MC_CMD_GET_CAPABILITIES_V7_OUT_FLAGS2_OFST 2016550#define MC_CMD_GET_CAPABILITIES_V7_OUT_FLAGS2_LEN 416551#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_V2_OFST 2016552#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_V2_LBN 016553#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_V2_WIDTH 116554#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_V2_ENCAP_OFST 2016555#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_V2_ENCAP_LBN 116556#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_V2_ENCAP_WIDTH 116557#define MC_CMD_GET_CAPABILITIES_V7_OUT_EVQ_TIMER_CTRL_OFST 2016558#define MC_CMD_GET_CAPABILITIES_V7_OUT_EVQ_TIMER_CTRL_LBN 216559#define MC_CMD_GET_CAPABILITIES_V7_OUT_EVQ_TIMER_CTRL_WIDTH 116560#define MC_CMD_GET_CAPABILITIES_V7_OUT_EVENT_CUT_THROUGH_OFST 2016561#define MC_CMD_GET_CAPABILITIES_V7_OUT_EVENT_CUT_THROUGH_LBN 316562#define MC_CMD_GET_CAPABILITIES_V7_OUT_EVENT_CUT_THROUGH_WIDTH 116563#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_CUT_THROUGH_OFST 2016564#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_CUT_THROUGH_LBN 416565#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_CUT_THROUGH_WIDTH 116566#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_VFIFO_ULL_MODE_OFST 2016567#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_VFIFO_ULL_MODE_LBN 516568#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_VFIFO_ULL_MODE_WIDTH 116569#define MC_CMD_GET_CAPABILITIES_V7_OUT_MAC_STATS_40G_TX_SIZE_BINS_OFST 2016570#define MC_CMD_GET_CAPABILITIES_V7_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 616571#define MC_CMD_GET_CAPABILITIES_V7_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 116572#define MC_CMD_GET_CAPABILITIES_V7_OUT_INIT_EVQ_TYPE_SUPPORTED_OFST 2016573#define MC_CMD_GET_CAPABILITIES_V7_OUT_INIT_EVQ_TYPE_SUPPORTED_LBN 716574#define MC_CMD_GET_CAPABILITIES_V7_OUT_INIT_EVQ_TYPE_SUPPORTED_WIDTH 116575#define MC_CMD_GET_CAPABILITIES_V7_OUT_INIT_EVQ_V2_OFST 2016576#define MC_CMD_GET_CAPABILITIES_V7_OUT_INIT_EVQ_V2_LBN 716577#define MC_CMD_GET_CAPABILITIES_V7_OUT_INIT_EVQ_V2_WIDTH 116578#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_MAC_TIMESTAMPING_OFST 2016579#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_MAC_TIMESTAMPING_LBN 816580#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_MAC_TIMESTAMPING_WIDTH 116581#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TIMESTAMP_OFST 2016582#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TIMESTAMP_LBN 916583#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TIMESTAMP_WIDTH 116584#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_SNIFF_OFST 2016585#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_SNIFF_LBN 1016586#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_SNIFF_WIDTH 116587#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_SNIFF_OFST 2016588#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_SNIFF_LBN 1116589#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_SNIFF_WIDTH 116590#define MC_CMD_GET_CAPABILITIES_V7_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_OFST 2016591#define MC_CMD_GET_CAPABILITIES_V7_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_LBN 1216592#define MC_CMD_GET_CAPABILITIES_V7_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 116593#define MC_CMD_GET_CAPABILITIES_V7_OUT_MCDI_BACKGROUND_OFST 2016594#define MC_CMD_GET_CAPABILITIES_V7_OUT_MCDI_BACKGROUND_LBN 1316595#define MC_CMD_GET_CAPABILITIES_V7_OUT_MCDI_BACKGROUND_WIDTH 116596#define MC_CMD_GET_CAPABILITIES_V7_OUT_MCDI_DB_RETURN_OFST 2016597#define MC_CMD_GET_CAPABILITIES_V7_OUT_MCDI_DB_RETURN_LBN 1416598#define MC_CMD_GET_CAPABILITIES_V7_OUT_MCDI_DB_RETURN_WIDTH 116599#define MC_CMD_GET_CAPABILITIES_V7_OUT_CTPIO_OFST 2016600#define MC_CMD_GET_CAPABILITIES_V7_OUT_CTPIO_LBN 1516601#define MC_CMD_GET_CAPABILITIES_V7_OUT_CTPIO_WIDTH 116602#define MC_CMD_GET_CAPABILITIES_V7_OUT_TSA_SUPPORT_OFST 2016603#define MC_CMD_GET_CAPABILITIES_V7_OUT_TSA_SUPPORT_LBN 1616604#define MC_CMD_GET_CAPABILITIES_V7_OUT_TSA_SUPPORT_WIDTH 116605#define MC_CMD_GET_CAPABILITIES_V7_OUT_TSA_BOUND_OFST 2016606#define MC_CMD_GET_CAPABILITIES_V7_OUT_TSA_BOUND_LBN 1716607#define MC_CMD_GET_CAPABILITIES_V7_OUT_TSA_BOUND_WIDTH 116608#define MC_CMD_GET_CAPABILITIES_V7_OUT_SF_ADAPTER_AUTHENTICATION_OFST 2016609#define MC_CMD_GET_CAPABILITIES_V7_OUT_SF_ADAPTER_AUTHENTICATION_LBN 1816610#define MC_CMD_GET_CAPABILITIES_V7_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 116611#define MC_CMD_GET_CAPABILITIES_V7_OUT_FILTER_ACTION_FLAG_OFST 2016612#define MC_CMD_GET_CAPABILITIES_V7_OUT_FILTER_ACTION_FLAG_LBN 1916613#define MC_CMD_GET_CAPABILITIES_V7_OUT_FILTER_ACTION_FLAG_WIDTH 116614#define MC_CMD_GET_CAPABILITIES_V7_OUT_FILTER_ACTION_MARK_OFST 2016615#define MC_CMD_GET_CAPABILITIES_V7_OUT_FILTER_ACTION_MARK_LBN 2016616#define MC_CMD_GET_CAPABILITIES_V7_OUT_FILTER_ACTION_MARK_WIDTH 116617#define MC_CMD_GET_CAPABILITIES_V7_OUT_EQUAL_STRIDE_SUPER_BUFFER_OFST 2016618#define MC_CMD_GET_CAPABILITIES_V7_OUT_EQUAL_STRIDE_SUPER_BUFFER_LBN 2116619#define MC_CMD_GET_CAPABILITIES_V7_OUT_EQUAL_STRIDE_SUPER_BUFFER_WIDTH 116620#define MC_CMD_GET_CAPABILITIES_V7_OUT_EQUAL_STRIDE_PACKED_STREAM_OFST 2016621#define MC_CMD_GET_CAPABILITIES_V7_OUT_EQUAL_STRIDE_PACKED_STREAM_LBN 2116622#define MC_CMD_GET_CAPABILITIES_V7_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 116623#define MC_CMD_GET_CAPABILITIES_V7_OUT_L3XUDP_SUPPORT_OFST 2016624#define MC_CMD_GET_CAPABILITIES_V7_OUT_L3XUDP_SUPPORT_LBN 2216625#define MC_CMD_GET_CAPABILITIES_V7_OUT_L3XUDP_SUPPORT_WIDTH 116626#define MC_CMD_GET_CAPABILITIES_V7_OUT_FW_SUBVARIANT_NO_TX_CSUM_OFST 2016627#define MC_CMD_GET_CAPABILITIES_V7_OUT_FW_SUBVARIANT_NO_TX_CSUM_LBN 2316628#define MC_CMD_GET_CAPABILITIES_V7_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 116629#define MC_CMD_GET_CAPABILITIES_V7_OUT_VI_SPREADING_OFST 2016630#define MC_CMD_GET_CAPABILITIES_V7_OUT_VI_SPREADING_LBN 2416631#define MC_CMD_GET_CAPABILITIES_V7_OUT_VI_SPREADING_WIDTH 116632#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_HLB_IDLE_OFST 2016633#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_HLB_IDLE_LBN 2516634#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_HLB_IDLE_WIDTH 116635#define MC_CMD_GET_CAPABILITIES_V7_OUT_INIT_RXQ_NO_CONT_EV_OFST 2016636#define MC_CMD_GET_CAPABILITIES_V7_OUT_INIT_RXQ_NO_CONT_EV_LBN 2616637#define MC_CMD_GET_CAPABILITIES_V7_OUT_INIT_RXQ_NO_CONT_EV_WIDTH 116638#define MC_CMD_GET_CAPABILITIES_V7_OUT_INIT_RXQ_WITH_BUFFER_SIZE_OFST 2016639#define MC_CMD_GET_CAPABILITIES_V7_OUT_INIT_RXQ_WITH_BUFFER_SIZE_LBN 2716640#define MC_CMD_GET_CAPABILITIES_V7_OUT_INIT_RXQ_WITH_BUFFER_SIZE_WIDTH 116641#define MC_CMD_GET_CAPABILITIES_V7_OUT_BUNDLE_UPDATE_OFST 2016642#define MC_CMD_GET_CAPABILITIES_V7_OUT_BUNDLE_UPDATE_LBN 2816643#define MC_CMD_GET_CAPABILITIES_V7_OUT_BUNDLE_UPDATE_WIDTH 116644#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_V3_OFST 2016645#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_V3_LBN 2916646#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_V3_WIDTH 116647#define MC_CMD_GET_CAPABILITIES_V7_OUT_DYNAMIC_SENSORS_OFST 2016648#define MC_CMD_GET_CAPABILITIES_V7_OUT_DYNAMIC_SENSORS_LBN 3016649#define MC_CMD_GET_CAPABILITIES_V7_OUT_DYNAMIC_SENSORS_WIDTH 116650#define MC_CMD_GET_CAPABILITIES_V7_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_OFST 2016651#define MC_CMD_GET_CAPABILITIES_V7_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_LBN 3116652#define MC_CMD_GET_CAPABILITIES_V7_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_WIDTH 116653/* Number of FATSOv2 contexts per datapath supported by this NIC (when16654 * TX_TSO_V2 == 1). Not present on older firmware (check the length).16655 */16656#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_V2_N_CONTEXTS_OFST 2416657#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_V2_N_CONTEXTS_LEN 216658/* One byte per PF containing the number of the external port assigned to this16659 * PF, indexed by PF number. Special values indicate that a PF is either not16660 * present or not assigned.16661 */16662#define MC_CMD_GET_CAPABILITIES_V7_OUT_PFS_TO_PORTS_ASSIGNMENT_OFST 2616663#define MC_CMD_GET_CAPABILITIES_V7_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 116664#define MC_CMD_GET_CAPABILITIES_V7_OUT_PFS_TO_PORTS_ASSIGNMENT_NUM 1616665/* enum: The caller is not permitted to access information on this PF. */16666#define MC_CMD_GET_CAPABILITIES_V7_OUT_ACCESS_NOT_PERMITTED 0xff16667/* enum: PF does not exist. */16668#define MC_CMD_GET_CAPABILITIES_V7_OUT_PF_NOT_PRESENT 0xfe16669/* enum: PF does exist but is not assigned to any external port. */16670#define MC_CMD_GET_CAPABILITIES_V7_OUT_PF_NOT_ASSIGNED 0xfd16671/* enum: This value indicates that PF is assigned, but it cannot be expressed16672 * in this field. It is intended for a possible future situation where a more16673 * complex scheme of PFs to ports mapping is being used. The future driver16674 * should look for a new field supporting the new scheme. The current/old16675 * driver should treat this value as PF_NOT_ASSIGNED.16676 */16677#define MC_CMD_GET_CAPABILITIES_V7_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc16678/* One byte per PF containing the number of its VFs, indexed by PF number. A16679 * special value indicates that a PF is not present.16680 */16681#define MC_CMD_GET_CAPABILITIES_V7_OUT_NUM_VFS_PER_PF_OFST 4216682#define MC_CMD_GET_CAPABILITIES_V7_OUT_NUM_VFS_PER_PF_LEN 116683#define MC_CMD_GET_CAPABILITIES_V7_OUT_NUM_VFS_PER_PF_NUM 1616684/* enum: The caller is not permitted to access information on this PF. */16685/* MC_CMD_GET_CAPABILITIES_V7_OUT_ACCESS_NOT_PERMITTED 0xff */16686/* enum: PF does not exist. */16687/* MC_CMD_GET_CAPABILITIES_V7_OUT_PF_NOT_PRESENT 0xfe */16688/* Number of VIs available for each external port */16689#define MC_CMD_GET_CAPABILITIES_V7_OUT_NUM_VIS_PER_PORT_OFST 5816690#define MC_CMD_GET_CAPABILITIES_V7_OUT_NUM_VIS_PER_PORT_LEN 216691#define MC_CMD_GET_CAPABILITIES_V7_OUT_NUM_VIS_PER_PORT_NUM 416692/* Size of RX descriptor cache expressed as binary logarithm The actual size16693 * equals (2 ^ RX_DESC_CACHE_SIZE)16694 */16695#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_DESC_CACHE_SIZE_OFST 6616696#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_DESC_CACHE_SIZE_LEN 116697/* Size of TX descriptor cache expressed as binary logarithm The actual size16698 * equals (2 ^ TX_DESC_CACHE_SIZE)16699 */16700#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_DESC_CACHE_SIZE_OFST 6716701#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_DESC_CACHE_SIZE_LEN 116702/* Total number of available PIO buffers */16703#define MC_CMD_GET_CAPABILITIES_V7_OUT_NUM_PIO_BUFFS_OFST 6816704#define MC_CMD_GET_CAPABILITIES_V7_OUT_NUM_PIO_BUFFS_LEN 216705/* Size of a single PIO buffer */16706#define MC_CMD_GET_CAPABILITIES_V7_OUT_SIZE_PIO_BUFF_OFST 7016707#define MC_CMD_GET_CAPABILITIES_V7_OUT_SIZE_PIO_BUFF_LEN 216708/* On chips later than Medford the amount of address space assigned to each VI16709 * is configurable. This is a global setting that the driver must query to16710 * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available16711 * with 8k VI windows.16712 */16713#define MC_CMD_GET_CAPABILITIES_V7_OUT_VI_WINDOW_MODE_OFST 7216714#define MC_CMD_GET_CAPABILITIES_V7_OUT_VI_WINDOW_MODE_LEN 116715/* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k.16716 * CTPIO is not mapped.16717 */16718#define MC_CMD_GET_CAPABILITIES_V7_OUT_VI_WINDOW_MODE_8K 0x016719/* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */16720#define MC_CMD_GET_CAPABILITIES_V7_OUT_VI_WINDOW_MODE_16K 0x116721/* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */16722#define MC_CMD_GET_CAPABILITIES_V7_OUT_VI_WINDOW_MODE_64K 0x216723/* Number of vFIFOs per adapter that can be used for VFIFO Stuffing16724 * (SF-115995-SW) in the present configuration of firmware and port mode.16725 */16726#define MC_CMD_GET_CAPABILITIES_V7_OUT_VFIFO_STUFFING_NUM_VFIFOS_OFST 7316727#define MC_CMD_GET_CAPABILITIES_V7_OUT_VFIFO_STUFFING_NUM_VFIFOS_LEN 116728/* Number of buffers per adapter that can be used for VFIFO Stuffing16729 * (SF-115995-SW) in the present configuration of firmware and port mode.16730 */16731#define MC_CMD_GET_CAPABILITIES_V7_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_OFST 7416732#define MC_CMD_GET_CAPABILITIES_V7_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_LEN 216733/* Entry count in the MAC stats array, including the final GENERATION_END16734 * entry. For MAC stats DMA, drivers should allocate a buffer large enough to16735 * hold at least this many 64-bit stats values, if they wish to receive all16736 * available stats. If the buffer is shorter than MAC_STATS_NUM_STATS * 8, the16737 * stats array returned will be truncated.16738 */16739#define MC_CMD_GET_CAPABILITIES_V7_OUT_MAC_STATS_NUM_STATS_OFST 7616740#define MC_CMD_GET_CAPABILITIES_V7_OUT_MAC_STATS_NUM_STATS_LEN 216741/* Maximum supported value for MC_CMD_FILTER_OP_V3/MATCH_MARK_VALUE. This field16742 * will only be non-zero if MC_CMD_GET_CAPABILITIES/FILTER_ACTION_MARK is set.16743 */16744#define MC_CMD_GET_CAPABILITIES_V7_OUT_FILTER_ACTION_MARK_MAX_OFST 8016745#define MC_CMD_GET_CAPABILITIES_V7_OUT_FILTER_ACTION_MARK_MAX_LEN 416746/* On devices where the INIT_RXQ_WITH_BUFFER_SIZE flag (in16747 * GET_CAPABILITIES_OUT_V2) is set, drivers have to specify a buffer size when16748 * they create an RX queue. Due to hardware limitations, only a small number of16749 * different buffer sizes may be available concurrently. Nonzero entries in16750 * this array are the sizes of buffers which the system guarantees will be16751 * available for use. If the list is empty, there are no limitations on16752 * concurrent buffer sizes.16753 */16754#define MC_CMD_GET_CAPABILITIES_V7_OUT_GUARANTEED_RX_BUFFER_SIZES_OFST 8416755#define MC_CMD_GET_CAPABILITIES_V7_OUT_GUARANTEED_RX_BUFFER_SIZES_LEN 416756#define MC_CMD_GET_CAPABILITIES_V7_OUT_GUARANTEED_RX_BUFFER_SIZES_NUM 1616757/* Third word of flags. Not present on older firmware (check the length). */16758#define MC_CMD_GET_CAPABILITIES_V7_OUT_FLAGS3_OFST 14816759#define MC_CMD_GET_CAPABILITIES_V7_OUT_FLAGS3_LEN 416760#define MC_CMD_GET_CAPABILITIES_V7_OUT_WOL_ETHERWAKE_OFST 14816761#define MC_CMD_GET_CAPABILITIES_V7_OUT_WOL_ETHERWAKE_LBN 016762#define MC_CMD_GET_CAPABILITIES_V7_OUT_WOL_ETHERWAKE_WIDTH 116763#define MC_CMD_GET_CAPABILITIES_V7_OUT_RSS_EVEN_SPREADING_OFST 14816764#define MC_CMD_GET_CAPABILITIES_V7_OUT_RSS_EVEN_SPREADING_LBN 116765#define MC_CMD_GET_CAPABILITIES_V7_OUT_RSS_EVEN_SPREADING_WIDTH 116766#define MC_CMD_GET_CAPABILITIES_V7_OUT_RSS_SELECTABLE_TABLE_SIZE_OFST 14816767#define MC_CMD_GET_CAPABILITIES_V7_OUT_RSS_SELECTABLE_TABLE_SIZE_LBN 216768#define MC_CMD_GET_CAPABILITIES_V7_OUT_RSS_SELECTABLE_TABLE_SIZE_WIDTH 116769#define MC_CMD_GET_CAPABILITIES_V7_OUT_MAE_SUPPORTED_OFST 14816770#define MC_CMD_GET_CAPABILITIES_V7_OUT_MAE_SUPPORTED_LBN 316771#define MC_CMD_GET_CAPABILITIES_V7_OUT_MAE_SUPPORTED_WIDTH 116772#define MC_CMD_GET_CAPABILITIES_V7_OUT_VDPA_SUPPORTED_OFST 14816773#define MC_CMD_GET_CAPABILITIES_V7_OUT_VDPA_SUPPORTED_LBN 416774#define MC_CMD_GET_CAPABILITIES_V7_OUT_VDPA_SUPPORTED_WIDTH 116775#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_OFST 14816776#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_LBN 516777#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_WIDTH 116778#define MC_CMD_GET_CAPABILITIES_V7_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_OFST 14816779#define MC_CMD_GET_CAPABILITIES_V7_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_LBN 616780#define MC_CMD_GET_CAPABILITIES_V7_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_WIDTH 116781#define MC_CMD_GET_CAPABILITIES_V7_OUT_UNSOL_EV_CREDIT_SUPPORTED_OFST 14816782#define MC_CMD_GET_CAPABILITIES_V7_OUT_UNSOL_EV_CREDIT_SUPPORTED_LBN 716783#define MC_CMD_GET_CAPABILITIES_V7_OUT_UNSOL_EV_CREDIT_SUPPORTED_WIDTH 116784#define MC_CMD_GET_CAPABILITIES_V7_OUT_ENCAPSULATED_MCDI_SUPPORTED_OFST 14816785#define MC_CMD_GET_CAPABILITIES_V7_OUT_ENCAPSULATED_MCDI_SUPPORTED_LBN 816786#define MC_CMD_GET_CAPABILITIES_V7_OUT_ENCAPSULATED_MCDI_SUPPORTED_WIDTH 116787#define MC_CMD_GET_CAPABILITIES_V7_OUT_EXTERNAL_MAE_SUPPORTED_OFST 14816788#define MC_CMD_GET_CAPABILITIES_V7_OUT_EXTERNAL_MAE_SUPPORTED_LBN 916789#define MC_CMD_GET_CAPABILITIES_V7_OUT_EXTERNAL_MAE_SUPPORTED_WIDTH 116790#define MC_CMD_GET_CAPABILITIES_V7_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_OFST 14816791#define MC_CMD_GET_CAPABILITIES_V7_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_LBN 1016792#define MC_CMD_GET_CAPABILITIES_V7_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_WIDTH 116793#define MC_CMD_GET_CAPABILITIES_V7_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_OFST 14816794#define MC_CMD_GET_CAPABILITIES_V7_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_LBN 1116795#define MC_CMD_GET_CAPABILITIES_V7_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_WIDTH 116796#define MC_CMD_GET_CAPABILITIES_V7_OUT_RSS_STEER_ON_OUTER_SUPPORTED_OFST 14816797#define MC_CMD_GET_CAPABILITIES_V7_OUT_RSS_STEER_ON_OUTER_SUPPORTED_LBN 1216798#define MC_CMD_GET_CAPABILITIES_V7_OUT_RSS_STEER_ON_OUTER_SUPPORTED_WIDTH 116799#define MC_CMD_GET_CAPABILITIES_V7_OUT_DYNAMIC_MPORT_JOURNAL_OFST 14816800#define MC_CMD_GET_CAPABILITIES_V7_OUT_DYNAMIC_MPORT_JOURNAL_LBN 1416801#define MC_CMD_GET_CAPABILITIES_V7_OUT_DYNAMIC_MPORT_JOURNAL_WIDTH 116802 16803/* MC_CMD_GET_CAPABILITIES_V8_OUT msgresponse */16804#define MC_CMD_GET_CAPABILITIES_V8_OUT_LEN 16016805/* First word of flags. */16806#define MC_CMD_GET_CAPABILITIES_V8_OUT_FLAGS1_OFST 016807#define MC_CMD_GET_CAPABILITIES_V8_OUT_FLAGS1_LEN 416808#define MC_CMD_GET_CAPABILITIES_V8_OUT_VPORT_RECONFIGURE_OFST 016809#define MC_CMD_GET_CAPABILITIES_V8_OUT_VPORT_RECONFIGURE_LBN 316810#define MC_CMD_GET_CAPABILITIES_V8_OUT_VPORT_RECONFIGURE_WIDTH 116811#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_STRIPING_OFST 016812#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_STRIPING_LBN 416813#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_STRIPING_WIDTH 116814#define MC_CMD_GET_CAPABILITIES_V8_OUT_VADAPTOR_QUERY_OFST 016815#define MC_CMD_GET_CAPABILITIES_V8_OUT_VADAPTOR_QUERY_LBN 516816#define MC_CMD_GET_CAPABILITIES_V8_OUT_VADAPTOR_QUERY_WIDTH 116817#define MC_CMD_GET_CAPABILITIES_V8_OUT_EVB_PORT_VLAN_RESTRICT_OFST 016818#define MC_CMD_GET_CAPABILITIES_V8_OUT_EVB_PORT_VLAN_RESTRICT_LBN 616819#define MC_CMD_GET_CAPABILITIES_V8_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 116820#define MC_CMD_GET_CAPABILITIES_V8_OUT_DRV_ATTACH_PREBOOT_OFST 016821#define MC_CMD_GET_CAPABILITIES_V8_OUT_DRV_ATTACH_PREBOOT_LBN 716822#define MC_CMD_GET_CAPABILITIES_V8_OUT_DRV_ATTACH_PREBOOT_WIDTH 116823#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_FORCE_EVENT_MERGING_OFST 016824#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_FORCE_EVENT_MERGING_LBN 816825#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_FORCE_EVENT_MERGING_WIDTH 116826#define MC_CMD_GET_CAPABILITIES_V8_OUT_SET_MAC_ENHANCED_OFST 016827#define MC_CMD_GET_CAPABILITIES_V8_OUT_SET_MAC_ENHANCED_LBN 916828#define MC_CMD_GET_CAPABILITIES_V8_OUT_SET_MAC_ENHANCED_WIDTH 116829#define MC_CMD_GET_CAPABILITIES_V8_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 016830#define MC_CMD_GET_CAPABILITIES_V8_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 1016831#define MC_CMD_GET_CAPABILITIES_V8_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 116832#define MC_CMD_GET_CAPABILITIES_V8_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 016833#define MC_CMD_GET_CAPABILITIES_V8_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 1116834#define MC_CMD_GET_CAPABILITIES_V8_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 116835#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_MAC_SECURITY_FILTERING_OFST 016836#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_MAC_SECURITY_FILTERING_LBN 1216837#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 116838#define MC_CMD_GET_CAPABILITIES_V8_OUT_ADDITIONAL_RSS_MODES_OFST 016839#define MC_CMD_GET_CAPABILITIES_V8_OUT_ADDITIONAL_RSS_MODES_LBN 1316840#define MC_CMD_GET_CAPABILITIES_V8_OUT_ADDITIONAL_RSS_MODES_WIDTH 116841#define MC_CMD_GET_CAPABILITIES_V8_OUT_QBB_OFST 016842#define MC_CMD_GET_CAPABILITIES_V8_OUT_QBB_LBN 1416843#define MC_CMD_GET_CAPABILITIES_V8_OUT_QBB_WIDTH 116844#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 016845#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 1516846#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 116847#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_RSS_LIMITED_OFST 016848#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_RSS_LIMITED_LBN 1616849#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_RSS_LIMITED_WIDTH 116850#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_PACKED_STREAM_OFST 016851#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_PACKED_STREAM_LBN 1716852#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_PACKED_STREAM_WIDTH 116853#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_INCLUDE_FCS_OFST 016854#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_INCLUDE_FCS_LBN 1816855#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_INCLUDE_FCS_WIDTH 116856#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_VLAN_INSERTION_OFST 016857#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_VLAN_INSERTION_LBN 1916858#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_VLAN_INSERTION_WIDTH 116859#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_VLAN_STRIPPING_OFST 016860#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_VLAN_STRIPPING_LBN 2016861#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_VLAN_STRIPPING_WIDTH 116862#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_OFST 016863#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_LBN 2116864#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_WIDTH 116865#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_PREFIX_LEN_0_OFST 016866#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_PREFIX_LEN_0_LBN 2216867#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_PREFIX_LEN_0_WIDTH 116868#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_PREFIX_LEN_14_OFST 016869#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_PREFIX_LEN_14_LBN 2316870#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_PREFIX_LEN_14_WIDTH 116871#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_TIMESTAMP_OFST 016872#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_TIMESTAMP_LBN 2416873#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_TIMESTAMP_WIDTH 116874#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_BATCHING_OFST 016875#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_BATCHING_LBN 2516876#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_BATCHING_WIDTH 116877#define MC_CMD_GET_CAPABILITIES_V8_OUT_MCAST_FILTER_CHAINING_OFST 016878#define MC_CMD_GET_CAPABILITIES_V8_OUT_MCAST_FILTER_CHAINING_LBN 2616879#define MC_CMD_GET_CAPABILITIES_V8_OUT_MCAST_FILTER_CHAINING_WIDTH 116880#define MC_CMD_GET_CAPABILITIES_V8_OUT_PM_AND_RXDP_COUNTERS_OFST 016881#define MC_CMD_GET_CAPABILITIES_V8_OUT_PM_AND_RXDP_COUNTERS_LBN 2716882#define MC_CMD_GET_CAPABILITIES_V8_OUT_PM_AND_RXDP_COUNTERS_WIDTH 116883#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_DISABLE_SCATTER_OFST 016884#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_DISABLE_SCATTER_LBN 2816885#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_DISABLE_SCATTER_WIDTH 116886#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_MCAST_UDP_LOOPBACK_OFST 016887#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_MCAST_UDP_LOOPBACK_LBN 2916888#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 116889#define MC_CMD_GET_CAPABILITIES_V8_OUT_EVB_OFST 016890#define MC_CMD_GET_CAPABILITIES_V8_OUT_EVB_LBN 3016891#define MC_CMD_GET_CAPABILITIES_V8_OUT_EVB_WIDTH 116892#define MC_CMD_GET_CAPABILITIES_V8_OUT_VXLAN_NVGRE_OFST 016893#define MC_CMD_GET_CAPABILITIES_V8_OUT_VXLAN_NVGRE_LBN 3116894#define MC_CMD_GET_CAPABILITIES_V8_OUT_VXLAN_NVGRE_WIDTH 116895/* RxDPCPU firmware id. */16896#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_DPCPU_FW_ID_OFST 416897#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_DPCPU_FW_ID_LEN 216898/* enum: Standard RXDP firmware */16899#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP 0x016900/* enum: Low latency RXDP firmware */16901#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_LOW_LATENCY 0x116902/* enum: Packed stream RXDP firmware */16903#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_PACKED_STREAM 0x216904/* enum: Rules engine RXDP firmware */16905#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_RULES_ENGINE 0x516906/* enum: DPDK RXDP firmware */16907#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_DPDK 0x616908/* enum: BIST RXDP firmware */16909#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_BIST 0x10a16910/* enum: RXDP Test firmware image 1 */16911#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x10116912/* enum: RXDP Test firmware image 2 */16913#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x10216914/* enum: RXDP Test firmware image 3 */16915#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x10316916/* enum: RXDP Test firmware image 4 */16917#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x10416918/* enum: RXDP Test firmware image 5 */16919#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_BACKPRESSURE 0x10516920/* enum: RXDP Test firmware image 6 */16921#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_FW_PACKET_EDITS 0x10616922/* enum: RXDP Test firmware image 7 */16923#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x10716924/* enum: RXDP Test firmware image 8 */16925#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_FW_DISABLE_DL 0x10816926/* enum: RXDP Test firmware image 9 */16927#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b16928/* enum: RXDP Test firmware image 10 */16929#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_FW_SLOW 0x10c16930/* TxDPCPU firmware id. */16931#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_DPCPU_FW_ID_OFST 616932#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_DPCPU_FW_ID_LEN 216933/* enum: Standard TXDP firmware */16934#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXDP 0x016935/* enum: Low latency TXDP firmware */16936#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXDP_LOW_LATENCY 0x116937/* enum: High packet rate TXDP firmware */16938#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXDP_HIGH_PACKET_RATE 0x316939/* enum: Rules engine TXDP firmware */16940#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXDP_RULES_ENGINE 0x516941/* enum: DPDK TXDP firmware */16942#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXDP_DPDK 0x616943/* enum: BIST TXDP firmware */16944#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXDP_BIST 0x12d16945/* enum: TXDP Test firmware image 1 */16946#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXDP_TEST_FW_TSO_EDIT 0x10116947/* enum: TXDP Test firmware image 2 */16948#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXDP_TEST_FW_PACKET_EDITS 0x10216949/* enum: TXDP CSR bus test firmware */16950#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXDP_TEST_FW_CSR 0x10316951#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_VERSION_OFST 816952#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_VERSION_LEN 216953#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_VERSION_REV_OFST 816954#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_VERSION_REV_LBN 016955#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_VERSION_REV_WIDTH 1216956#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_VERSION_TYPE_OFST 816957#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_VERSION_TYPE_LBN 1216958#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_VERSION_TYPE_WIDTH 416959/* enum: reserved value - do not use (may indicate alternative interpretation16960 * of REV field in future)16961 */16962#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_RESERVED 0x016963/* enum: Trivial RX PD firmware for early Huntington development (Huntington16964 * development only)16965 */16966#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_FIRST_PKT 0x116967/* enum: RX PD firmware for telemetry prototyping (Medford2 development only)16968 */16969#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x116970/* enum: RX PD firmware with approximately Siena-compatible behaviour16971 * (Huntington development only)16972 */16973#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x216974/* enum: Full featured RX PD production firmware */16975#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x316976/* enum: (deprecated original name for the FULL_FEATURED variant) */16977#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_VSWITCH 0x316978/* enum: siena_compat variant RX PD firmware using PM rather than MAC16979 * (Huntington development only)16980 */16981#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x416982/* enum: Low latency RX PD production firmware */16983#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x516984/* enum: Packed stream RX PD production firmware */16985#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x616986/* enum: RX PD firmware handling layer 2 only for high packet rate performance16987 * tests (Medford development only)16988 */16989#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x716990/* enum: Rules engine RX PD production firmware */16991#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x816992/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */16993#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_L3XUDP 0x916994/* enum: DPDK RX PD production firmware */16995#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_DPDK 0xa16996/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */16997#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe16998/* enum: RX PD firmware parsing but not filtering network overlay tunnel16999 * encapsulations (Medford development only)17000 */17001#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf17002#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_VERSION_OFST 1017003#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_VERSION_LEN 217004#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_VERSION_REV_OFST 1017005#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_VERSION_REV_LBN 017006#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_VERSION_REV_WIDTH 1217007#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_VERSION_TYPE_OFST 1017008#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_VERSION_TYPE_LBN 1217009#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_VERSION_TYPE_WIDTH 417010/* enum: reserved value - do not use (may indicate alternative interpretation17011 * of REV field in future)17012 */17013#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_RESERVED 0x017014/* enum: Trivial TX PD firmware for early Huntington development (Huntington17015 * development only)17016 */17017#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_FIRST_PKT 0x117018/* enum: TX PD firmware for telemetry prototyping (Medford2 development only)17019 */17020#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x117021/* enum: TX PD firmware with approximately Siena-compatible behaviour17022 * (Huntington development only)17023 */17024#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x217025/* enum: Full featured TX PD production firmware */17026#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x317027/* enum: (deprecated original name for the FULL_FEATURED variant) */17028#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_VSWITCH 0x317029/* enum: siena_compat variant TX PD firmware using PM rather than MAC17030 * (Huntington development only)17031 */17032#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x417033#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */17034/* enum: TX PD firmware handling layer 2 only for high packet rate performance17035 * tests (Medford development only)17036 */17037#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x717038/* enum: Rules engine TX PD production firmware */17039#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x817040/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */17041#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_L3XUDP 0x917042/* enum: DPDK TX PD production firmware */17043#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_DPDK 0xa17044/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */17045#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe17046/* Hardware capabilities of NIC */17047#define MC_CMD_GET_CAPABILITIES_V8_OUT_HW_CAPABILITIES_OFST 1217048#define MC_CMD_GET_CAPABILITIES_V8_OUT_HW_CAPABILITIES_LEN 417049/* Licensed capabilities */17050#define MC_CMD_GET_CAPABILITIES_V8_OUT_LICENSE_CAPABILITIES_OFST 1617051#define MC_CMD_GET_CAPABILITIES_V8_OUT_LICENSE_CAPABILITIES_LEN 417052/* Second word of flags. Not present on older firmware (check the length). */17053#define MC_CMD_GET_CAPABILITIES_V8_OUT_FLAGS2_OFST 2017054#define MC_CMD_GET_CAPABILITIES_V8_OUT_FLAGS2_LEN 417055#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_V2_OFST 2017056#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_V2_LBN 017057#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_V2_WIDTH 117058#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_V2_ENCAP_OFST 2017059#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_V2_ENCAP_LBN 117060#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_V2_ENCAP_WIDTH 117061#define MC_CMD_GET_CAPABILITIES_V8_OUT_EVQ_TIMER_CTRL_OFST 2017062#define MC_CMD_GET_CAPABILITIES_V8_OUT_EVQ_TIMER_CTRL_LBN 217063#define MC_CMD_GET_CAPABILITIES_V8_OUT_EVQ_TIMER_CTRL_WIDTH 117064#define MC_CMD_GET_CAPABILITIES_V8_OUT_EVENT_CUT_THROUGH_OFST 2017065#define MC_CMD_GET_CAPABILITIES_V8_OUT_EVENT_CUT_THROUGH_LBN 317066#define MC_CMD_GET_CAPABILITIES_V8_OUT_EVENT_CUT_THROUGH_WIDTH 117067#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_CUT_THROUGH_OFST 2017068#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_CUT_THROUGH_LBN 417069#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_CUT_THROUGH_WIDTH 117070#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_VFIFO_ULL_MODE_OFST 2017071#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_VFIFO_ULL_MODE_LBN 517072#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_VFIFO_ULL_MODE_WIDTH 117073#define MC_CMD_GET_CAPABILITIES_V8_OUT_MAC_STATS_40G_TX_SIZE_BINS_OFST 2017074#define MC_CMD_GET_CAPABILITIES_V8_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 617075#define MC_CMD_GET_CAPABILITIES_V8_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 117076#define MC_CMD_GET_CAPABILITIES_V8_OUT_INIT_EVQ_TYPE_SUPPORTED_OFST 2017077#define MC_CMD_GET_CAPABILITIES_V8_OUT_INIT_EVQ_TYPE_SUPPORTED_LBN 717078#define MC_CMD_GET_CAPABILITIES_V8_OUT_INIT_EVQ_TYPE_SUPPORTED_WIDTH 117079#define MC_CMD_GET_CAPABILITIES_V8_OUT_INIT_EVQ_V2_OFST 2017080#define MC_CMD_GET_CAPABILITIES_V8_OUT_INIT_EVQ_V2_LBN 717081#define MC_CMD_GET_CAPABILITIES_V8_OUT_INIT_EVQ_V2_WIDTH 117082#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_MAC_TIMESTAMPING_OFST 2017083#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_MAC_TIMESTAMPING_LBN 817084#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_MAC_TIMESTAMPING_WIDTH 117085#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TIMESTAMP_OFST 2017086#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TIMESTAMP_LBN 917087#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TIMESTAMP_WIDTH 117088#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_SNIFF_OFST 2017089#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_SNIFF_LBN 1017090#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_SNIFF_WIDTH 117091#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_SNIFF_OFST 2017092#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_SNIFF_LBN 1117093#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_SNIFF_WIDTH 117094#define MC_CMD_GET_CAPABILITIES_V8_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_OFST 2017095#define MC_CMD_GET_CAPABILITIES_V8_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_LBN 1217096#define MC_CMD_GET_CAPABILITIES_V8_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 117097#define MC_CMD_GET_CAPABILITIES_V8_OUT_MCDI_BACKGROUND_OFST 2017098#define MC_CMD_GET_CAPABILITIES_V8_OUT_MCDI_BACKGROUND_LBN 1317099#define MC_CMD_GET_CAPABILITIES_V8_OUT_MCDI_BACKGROUND_WIDTH 117100#define MC_CMD_GET_CAPABILITIES_V8_OUT_MCDI_DB_RETURN_OFST 2017101#define MC_CMD_GET_CAPABILITIES_V8_OUT_MCDI_DB_RETURN_LBN 1417102#define MC_CMD_GET_CAPABILITIES_V8_OUT_MCDI_DB_RETURN_WIDTH 117103#define MC_CMD_GET_CAPABILITIES_V8_OUT_CTPIO_OFST 2017104#define MC_CMD_GET_CAPABILITIES_V8_OUT_CTPIO_LBN 1517105#define MC_CMD_GET_CAPABILITIES_V8_OUT_CTPIO_WIDTH 117106#define MC_CMD_GET_CAPABILITIES_V8_OUT_TSA_SUPPORT_OFST 2017107#define MC_CMD_GET_CAPABILITIES_V8_OUT_TSA_SUPPORT_LBN 1617108#define MC_CMD_GET_CAPABILITIES_V8_OUT_TSA_SUPPORT_WIDTH 117109#define MC_CMD_GET_CAPABILITIES_V8_OUT_TSA_BOUND_OFST 2017110#define MC_CMD_GET_CAPABILITIES_V8_OUT_TSA_BOUND_LBN 1717111#define MC_CMD_GET_CAPABILITIES_V8_OUT_TSA_BOUND_WIDTH 117112#define MC_CMD_GET_CAPABILITIES_V8_OUT_SF_ADAPTER_AUTHENTICATION_OFST 2017113#define MC_CMD_GET_CAPABILITIES_V8_OUT_SF_ADAPTER_AUTHENTICATION_LBN 1817114#define MC_CMD_GET_CAPABILITIES_V8_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 117115#define MC_CMD_GET_CAPABILITIES_V8_OUT_FILTER_ACTION_FLAG_OFST 2017116#define MC_CMD_GET_CAPABILITIES_V8_OUT_FILTER_ACTION_FLAG_LBN 1917117#define MC_CMD_GET_CAPABILITIES_V8_OUT_FILTER_ACTION_FLAG_WIDTH 117118#define MC_CMD_GET_CAPABILITIES_V8_OUT_FILTER_ACTION_MARK_OFST 2017119#define MC_CMD_GET_CAPABILITIES_V8_OUT_FILTER_ACTION_MARK_LBN 2017120#define MC_CMD_GET_CAPABILITIES_V8_OUT_FILTER_ACTION_MARK_WIDTH 117121#define MC_CMD_GET_CAPABILITIES_V8_OUT_EQUAL_STRIDE_SUPER_BUFFER_OFST 2017122#define MC_CMD_GET_CAPABILITIES_V8_OUT_EQUAL_STRIDE_SUPER_BUFFER_LBN 2117123#define MC_CMD_GET_CAPABILITIES_V8_OUT_EQUAL_STRIDE_SUPER_BUFFER_WIDTH 117124#define MC_CMD_GET_CAPABILITIES_V8_OUT_EQUAL_STRIDE_PACKED_STREAM_OFST 2017125#define MC_CMD_GET_CAPABILITIES_V8_OUT_EQUAL_STRIDE_PACKED_STREAM_LBN 2117126#define MC_CMD_GET_CAPABILITIES_V8_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 117127#define MC_CMD_GET_CAPABILITIES_V8_OUT_L3XUDP_SUPPORT_OFST 2017128#define MC_CMD_GET_CAPABILITIES_V8_OUT_L3XUDP_SUPPORT_LBN 2217129#define MC_CMD_GET_CAPABILITIES_V8_OUT_L3XUDP_SUPPORT_WIDTH 117130#define MC_CMD_GET_CAPABILITIES_V8_OUT_FW_SUBVARIANT_NO_TX_CSUM_OFST 2017131#define MC_CMD_GET_CAPABILITIES_V8_OUT_FW_SUBVARIANT_NO_TX_CSUM_LBN 2317132#define MC_CMD_GET_CAPABILITIES_V8_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 117133#define MC_CMD_GET_CAPABILITIES_V8_OUT_VI_SPREADING_OFST 2017134#define MC_CMD_GET_CAPABILITIES_V8_OUT_VI_SPREADING_LBN 2417135#define MC_CMD_GET_CAPABILITIES_V8_OUT_VI_SPREADING_WIDTH 117136#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_HLB_IDLE_OFST 2017137#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_HLB_IDLE_LBN 2517138#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_HLB_IDLE_WIDTH 117139#define MC_CMD_GET_CAPABILITIES_V8_OUT_INIT_RXQ_NO_CONT_EV_OFST 2017140#define MC_CMD_GET_CAPABILITIES_V8_OUT_INIT_RXQ_NO_CONT_EV_LBN 2617141#define MC_CMD_GET_CAPABILITIES_V8_OUT_INIT_RXQ_NO_CONT_EV_WIDTH 117142#define MC_CMD_GET_CAPABILITIES_V8_OUT_INIT_RXQ_WITH_BUFFER_SIZE_OFST 2017143#define MC_CMD_GET_CAPABILITIES_V8_OUT_INIT_RXQ_WITH_BUFFER_SIZE_LBN 2717144#define MC_CMD_GET_CAPABILITIES_V8_OUT_INIT_RXQ_WITH_BUFFER_SIZE_WIDTH 117145#define MC_CMD_GET_CAPABILITIES_V8_OUT_BUNDLE_UPDATE_OFST 2017146#define MC_CMD_GET_CAPABILITIES_V8_OUT_BUNDLE_UPDATE_LBN 2817147#define MC_CMD_GET_CAPABILITIES_V8_OUT_BUNDLE_UPDATE_WIDTH 117148#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_V3_OFST 2017149#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_V3_LBN 2917150#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_V3_WIDTH 117151#define MC_CMD_GET_CAPABILITIES_V8_OUT_DYNAMIC_SENSORS_OFST 2017152#define MC_CMD_GET_CAPABILITIES_V8_OUT_DYNAMIC_SENSORS_LBN 3017153#define MC_CMD_GET_CAPABILITIES_V8_OUT_DYNAMIC_SENSORS_WIDTH 117154#define MC_CMD_GET_CAPABILITIES_V8_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_OFST 2017155#define MC_CMD_GET_CAPABILITIES_V8_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_LBN 3117156#define MC_CMD_GET_CAPABILITIES_V8_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_WIDTH 117157/* Number of FATSOv2 contexts per datapath supported by this NIC (when17158 * TX_TSO_V2 == 1). Not present on older firmware (check the length).17159 */17160#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_V2_N_CONTEXTS_OFST 2417161#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_V2_N_CONTEXTS_LEN 217162/* One byte per PF containing the number of the external port assigned to this17163 * PF, indexed by PF number. Special values indicate that a PF is either not17164 * present or not assigned.17165 */17166#define MC_CMD_GET_CAPABILITIES_V8_OUT_PFS_TO_PORTS_ASSIGNMENT_OFST 2617167#define MC_CMD_GET_CAPABILITIES_V8_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 117168#define MC_CMD_GET_CAPABILITIES_V8_OUT_PFS_TO_PORTS_ASSIGNMENT_NUM 1617169/* enum: The caller is not permitted to access information on this PF. */17170#define MC_CMD_GET_CAPABILITIES_V8_OUT_ACCESS_NOT_PERMITTED 0xff17171/* enum: PF does not exist. */17172#define MC_CMD_GET_CAPABILITIES_V8_OUT_PF_NOT_PRESENT 0xfe17173/* enum: PF does exist but is not assigned to any external port. */17174#define MC_CMD_GET_CAPABILITIES_V8_OUT_PF_NOT_ASSIGNED 0xfd17175/* enum: This value indicates that PF is assigned, but it cannot be expressed17176 * in this field. It is intended for a possible future situation where a more17177 * complex scheme of PFs to ports mapping is being used. The future driver17178 * should look for a new field supporting the new scheme. The current/old17179 * driver should treat this value as PF_NOT_ASSIGNED.17180 */17181#define MC_CMD_GET_CAPABILITIES_V8_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc17182/* One byte per PF containing the number of its VFs, indexed by PF number. A17183 * special value indicates that a PF is not present.17184 */17185#define MC_CMD_GET_CAPABILITIES_V8_OUT_NUM_VFS_PER_PF_OFST 4217186#define MC_CMD_GET_CAPABILITIES_V8_OUT_NUM_VFS_PER_PF_LEN 117187#define MC_CMD_GET_CAPABILITIES_V8_OUT_NUM_VFS_PER_PF_NUM 1617188/* enum: The caller is not permitted to access information on this PF. */17189/* MC_CMD_GET_CAPABILITIES_V8_OUT_ACCESS_NOT_PERMITTED 0xff */17190/* enum: PF does not exist. */17191/* MC_CMD_GET_CAPABILITIES_V8_OUT_PF_NOT_PRESENT 0xfe */17192/* Number of VIs available for each external port */17193#define MC_CMD_GET_CAPABILITIES_V8_OUT_NUM_VIS_PER_PORT_OFST 5817194#define MC_CMD_GET_CAPABILITIES_V8_OUT_NUM_VIS_PER_PORT_LEN 217195#define MC_CMD_GET_CAPABILITIES_V8_OUT_NUM_VIS_PER_PORT_NUM 417196/* Size of RX descriptor cache expressed as binary logarithm The actual size17197 * equals (2 ^ RX_DESC_CACHE_SIZE)17198 */17199#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_DESC_CACHE_SIZE_OFST 6617200#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_DESC_CACHE_SIZE_LEN 117201/* Size of TX descriptor cache expressed as binary logarithm The actual size17202 * equals (2 ^ TX_DESC_CACHE_SIZE)17203 */17204#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_DESC_CACHE_SIZE_OFST 6717205#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_DESC_CACHE_SIZE_LEN 117206/* Total number of available PIO buffers */17207#define MC_CMD_GET_CAPABILITIES_V8_OUT_NUM_PIO_BUFFS_OFST 6817208#define MC_CMD_GET_CAPABILITIES_V8_OUT_NUM_PIO_BUFFS_LEN 217209/* Size of a single PIO buffer */17210#define MC_CMD_GET_CAPABILITIES_V8_OUT_SIZE_PIO_BUFF_OFST 7017211#define MC_CMD_GET_CAPABILITIES_V8_OUT_SIZE_PIO_BUFF_LEN 217212/* On chips later than Medford the amount of address space assigned to each VI17213 * is configurable. This is a global setting that the driver must query to17214 * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available17215 * with 8k VI windows.17216 */17217#define MC_CMD_GET_CAPABILITIES_V8_OUT_VI_WINDOW_MODE_OFST 7217218#define MC_CMD_GET_CAPABILITIES_V8_OUT_VI_WINDOW_MODE_LEN 117219/* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k.17220 * CTPIO is not mapped.17221 */17222#define MC_CMD_GET_CAPABILITIES_V8_OUT_VI_WINDOW_MODE_8K 0x017223/* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */17224#define MC_CMD_GET_CAPABILITIES_V8_OUT_VI_WINDOW_MODE_16K 0x117225/* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */17226#define MC_CMD_GET_CAPABILITIES_V8_OUT_VI_WINDOW_MODE_64K 0x217227/* Number of vFIFOs per adapter that can be used for VFIFO Stuffing17228 * (SF-115995-SW) in the present configuration of firmware and port mode.17229 */17230#define MC_CMD_GET_CAPABILITIES_V8_OUT_VFIFO_STUFFING_NUM_VFIFOS_OFST 7317231#define MC_CMD_GET_CAPABILITIES_V8_OUT_VFIFO_STUFFING_NUM_VFIFOS_LEN 117232/* Number of buffers per adapter that can be used for VFIFO Stuffing17233 * (SF-115995-SW) in the present configuration of firmware and port mode.17234 */17235#define MC_CMD_GET_CAPABILITIES_V8_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_OFST 7417236#define MC_CMD_GET_CAPABILITIES_V8_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_LEN 217237/* Entry count in the MAC stats array, including the final GENERATION_END17238 * entry. For MAC stats DMA, drivers should allocate a buffer large enough to17239 * hold at least this many 64-bit stats values, if they wish to receive all17240 * available stats. If the buffer is shorter than MAC_STATS_NUM_STATS * 8, the17241 * stats array returned will be truncated.17242 */17243#define MC_CMD_GET_CAPABILITIES_V8_OUT_MAC_STATS_NUM_STATS_OFST 7617244#define MC_CMD_GET_CAPABILITIES_V8_OUT_MAC_STATS_NUM_STATS_LEN 217245/* Maximum supported value for MC_CMD_FILTER_OP_V3/MATCH_MARK_VALUE. This field17246 * will only be non-zero if MC_CMD_GET_CAPABILITIES/FILTER_ACTION_MARK is set.17247 */17248#define MC_CMD_GET_CAPABILITIES_V8_OUT_FILTER_ACTION_MARK_MAX_OFST 8017249#define MC_CMD_GET_CAPABILITIES_V8_OUT_FILTER_ACTION_MARK_MAX_LEN 417250/* On devices where the INIT_RXQ_WITH_BUFFER_SIZE flag (in17251 * GET_CAPABILITIES_OUT_V2) is set, drivers have to specify a buffer size when17252 * they create an RX queue. Due to hardware limitations, only a small number of17253 * different buffer sizes may be available concurrently. Nonzero entries in17254 * this array are the sizes of buffers which the system guarantees will be17255 * available for use. If the list is empty, there are no limitations on17256 * concurrent buffer sizes.17257 */17258#define MC_CMD_GET_CAPABILITIES_V8_OUT_GUARANTEED_RX_BUFFER_SIZES_OFST 8417259#define MC_CMD_GET_CAPABILITIES_V8_OUT_GUARANTEED_RX_BUFFER_SIZES_LEN 417260#define MC_CMD_GET_CAPABILITIES_V8_OUT_GUARANTEED_RX_BUFFER_SIZES_NUM 1617261/* Third word of flags. Not present on older firmware (check the length). */17262#define MC_CMD_GET_CAPABILITIES_V8_OUT_FLAGS3_OFST 14817263#define MC_CMD_GET_CAPABILITIES_V8_OUT_FLAGS3_LEN 417264#define MC_CMD_GET_CAPABILITIES_V8_OUT_WOL_ETHERWAKE_OFST 14817265#define MC_CMD_GET_CAPABILITIES_V8_OUT_WOL_ETHERWAKE_LBN 017266#define MC_CMD_GET_CAPABILITIES_V8_OUT_WOL_ETHERWAKE_WIDTH 117267#define MC_CMD_GET_CAPABILITIES_V8_OUT_RSS_EVEN_SPREADING_OFST 14817268#define MC_CMD_GET_CAPABILITIES_V8_OUT_RSS_EVEN_SPREADING_LBN 117269#define MC_CMD_GET_CAPABILITIES_V8_OUT_RSS_EVEN_SPREADING_WIDTH 117270#define MC_CMD_GET_CAPABILITIES_V8_OUT_RSS_SELECTABLE_TABLE_SIZE_OFST 14817271#define MC_CMD_GET_CAPABILITIES_V8_OUT_RSS_SELECTABLE_TABLE_SIZE_LBN 217272#define MC_CMD_GET_CAPABILITIES_V8_OUT_RSS_SELECTABLE_TABLE_SIZE_WIDTH 117273#define MC_CMD_GET_CAPABILITIES_V8_OUT_MAE_SUPPORTED_OFST 14817274#define MC_CMD_GET_CAPABILITIES_V8_OUT_MAE_SUPPORTED_LBN 317275#define MC_CMD_GET_CAPABILITIES_V8_OUT_MAE_SUPPORTED_WIDTH 117276#define MC_CMD_GET_CAPABILITIES_V8_OUT_VDPA_SUPPORTED_OFST 14817277#define MC_CMD_GET_CAPABILITIES_V8_OUT_VDPA_SUPPORTED_LBN 417278#define MC_CMD_GET_CAPABILITIES_V8_OUT_VDPA_SUPPORTED_WIDTH 117279#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_OFST 14817280#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_LBN 517281#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_WIDTH 117282#define MC_CMD_GET_CAPABILITIES_V8_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_OFST 14817283#define MC_CMD_GET_CAPABILITIES_V8_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_LBN 617284#define MC_CMD_GET_CAPABILITIES_V8_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_WIDTH 117285#define MC_CMD_GET_CAPABILITIES_V8_OUT_UNSOL_EV_CREDIT_SUPPORTED_OFST 14817286#define MC_CMD_GET_CAPABILITIES_V8_OUT_UNSOL_EV_CREDIT_SUPPORTED_LBN 717287#define MC_CMD_GET_CAPABILITIES_V8_OUT_UNSOL_EV_CREDIT_SUPPORTED_WIDTH 117288#define MC_CMD_GET_CAPABILITIES_V8_OUT_ENCAPSULATED_MCDI_SUPPORTED_OFST 14817289#define MC_CMD_GET_CAPABILITIES_V8_OUT_ENCAPSULATED_MCDI_SUPPORTED_LBN 817290#define MC_CMD_GET_CAPABILITIES_V8_OUT_ENCAPSULATED_MCDI_SUPPORTED_WIDTH 117291#define MC_CMD_GET_CAPABILITIES_V8_OUT_EXTERNAL_MAE_SUPPORTED_OFST 14817292#define MC_CMD_GET_CAPABILITIES_V8_OUT_EXTERNAL_MAE_SUPPORTED_LBN 917293#define MC_CMD_GET_CAPABILITIES_V8_OUT_EXTERNAL_MAE_SUPPORTED_WIDTH 117294#define MC_CMD_GET_CAPABILITIES_V8_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_OFST 14817295#define MC_CMD_GET_CAPABILITIES_V8_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_LBN 1017296#define MC_CMD_GET_CAPABILITIES_V8_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_WIDTH 117297#define MC_CMD_GET_CAPABILITIES_V8_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_OFST 14817298#define MC_CMD_GET_CAPABILITIES_V8_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_LBN 1117299#define MC_CMD_GET_CAPABILITIES_V8_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_WIDTH 117300#define MC_CMD_GET_CAPABILITIES_V8_OUT_RSS_STEER_ON_OUTER_SUPPORTED_OFST 14817301#define MC_CMD_GET_CAPABILITIES_V8_OUT_RSS_STEER_ON_OUTER_SUPPORTED_LBN 1217302#define MC_CMD_GET_CAPABILITIES_V8_OUT_RSS_STEER_ON_OUTER_SUPPORTED_WIDTH 117303#define MC_CMD_GET_CAPABILITIES_V8_OUT_DYNAMIC_MPORT_JOURNAL_OFST 14817304#define MC_CMD_GET_CAPABILITIES_V8_OUT_DYNAMIC_MPORT_JOURNAL_LBN 1417305#define MC_CMD_GET_CAPABILITIES_V8_OUT_DYNAMIC_MPORT_JOURNAL_WIDTH 117306/* These bits are reserved for communicating test-specific capabilities to17307 * host-side test software. All production drivers should treat this field as17308 * opaque.17309 */17310#define MC_CMD_GET_CAPABILITIES_V8_OUT_TEST_RESERVED_OFST 15217311#define MC_CMD_GET_CAPABILITIES_V8_OUT_TEST_RESERVED_LEN 817312#define MC_CMD_GET_CAPABILITIES_V8_OUT_TEST_RESERVED_LO_OFST 15217313#define MC_CMD_GET_CAPABILITIES_V8_OUT_TEST_RESERVED_LO_LEN 417314#define MC_CMD_GET_CAPABILITIES_V8_OUT_TEST_RESERVED_LO_LBN 121617315#define MC_CMD_GET_CAPABILITIES_V8_OUT_TEST_RESERVED_LO_WIDTH 3217316#define MC_CMD_GET_CAPABILITIES_V8_OUT_TEST_RESERVED_HI_OFST 15617317#define MC_CMD_GET_CAPABILITIES_V8_OUT_TEST_RESERVED_HI_LEN 417318#define MC_CMD_GET_CAPABILITIES_V8_OUT_TEST_RESERVED_HI_LBN 124817319#define MC_CMD_GET_CAPABILITIES_V8_OUT_TEST_RESERVED_HI_WIDTH 3217320 17321/* MC_CMD_GET_CAPABILITIES_V9_OUT msgresponse */17322#define MC_CMD_GET_CAPABILITIES_V9_OUT_LEN 18417323/* First word of flags. */17324#define MC_CMD_GET_CAPABILITIES_V9_OUT_FLAGS1_OFST 017325#define MC_CMD_GET_CAPABILITIES_V9_OUT_FLAGS1_LEN 417326#define MC_CMD_GET_CAPABILITIES_V9_OUT_VPORT_RECONFIGURE_OFST 017327#define MC_CMD_GET_CAPABILITIES_V9_OUT_VPORT_RECONFIGURE_LBN 317328#define MC_CMD_GET_CAPABILITIES_V9_OUT_VPORT_RECONFIGURE_WIDTH 117329#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_STRIPING_OFST 017330#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_STRIPING_LBN 417331#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_STRIPING_WIDTH 117332#define MC_CMD_GET_CAPABILITIES_V9_OUT_VADAPTOR_QUERY_OFST 017333#define MC_CMD_GET_CAPABILITIES_V9_OUT_VADAPTOR_QUERY_LBN 517334#define MC_CMD_GET_CAPABILITIES_V9_OUT_VADAPTOR_QUERY_WIDTH 117335#define MC_CMD_GET_CAPABILITIES_V9_OUT_EVB_PORT_VLAN_RESTRICT_OFST 017336#define MC_CMD_GET_CAPABILITIES_V9_OUT_EVB_PORT_VLAN_RESTRICT_LBN 617337#define MC_CMD_GET_CAPABILITIES_V9_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 117338#define MC_CMD_GET_CAPABILITIES_V9_OUT_DRV_ATTACH_PREBOOT_OFST 017339#define MC_CMD_GET_CAPABILITIES_V9_OUT_DRV_ATTACH_PREBOOT_LBN 717340#define MC_CMD_GET_CAPABILITIES_V9_OUT_DRV_ATTACH_PREBOOT_WIDTH 117341#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_FORCE_EVENT_MERGING_OFST 017342#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_FORCE_EVENT_MERGING_LBN 817343#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_FORCE_EVENT_MERGING_WIDTH 117344#define MC_CMD_GET_CAPABILITIES_V9_OUT_SET_MAC_ENHANCED_OFST 017345#define MC_CMD_GET_CAPABILITIES_V9_OUT_SET_MAC_ENHANCED_LBN 917346#define MC_CMD_GET_CAPABILITIES_V9_OUT_SET_MAC_ENHANCED_WIDTH 117347#define MC_CMD_GET_CAPABILITIES_V9_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 017348#define MC_CMD_GET_CAPABILITIES_V9_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 1017349#define MC_CMD_GET_CAPABILITIES_V9_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 117350#define MC_CMD_GET_CAPABILITIES_V9_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 017351#define MC_CMD_GET_CAPABILITIES_V9_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 1117352#define MC_CMD_GET_CAPABILITIES_V9_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 117353#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_MAC_SECURITY_FILTERING_OFST 017354#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_MAC_SECURITY_FILTERING_LBN 1217355#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 117356#define MC_CMD_GET_CAPABILITIES_V9_OUT_ADDITIONAL_RSS_MODES_OFST 017357#define MC_CMD_GET_CAPABILITIES_V9_OUT_ADDITIONAL_RSS_MODES_LBN 1317358#define MC_CMD_GET_CAPABILITIES_V9_OUT_ADDITIONAL_RSS_MODES_WIDTH 117359#define MC_CMD_GET_CAPABILITIES_V9_OUT_QBB_OFST 017360#define MC_CMD_GET_CAPABILITIES_V9_OUT_QBB_LBN 1417361#define MC_CMD_GET_CAPABILITIES_V9_OUT_QBB_WIDTH 117362#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 017363#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 1517364#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 117365#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_RSS_LIMITED_OFST 017366#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_RSS_LIMITED_LBN 1617367#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_RSS_LIMITED_WIDTH 117368#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_PACKED_STREAM_OFST 017369#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_PACKED_STREAM_LBN 1717370#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_PACKED_STREAM_WIDTH 117371#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_INCLUDE_FCS_OFST 017372#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_INCLUDE_FCS_LBN 1817373#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_INCLUDE_FCS_WIDTH 117374#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_VLAN_INSERTION_OFST 017375#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_VLAN_INSERTION_LBN 1917376#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_VLAN_INSERTION_WIDTH 117377#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_VLAN_STRIPPING_OFST 017378#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_VLAN_STRIPPING_LBN 2017379#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_VLAN_STRIPPING_WIDTH 117380#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_OFST 017381#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_LBN 2117382#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_WIDTH 117383#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_PREFIX_LEN_0_OFST 017384#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_PREFIX_LEN_0_LBN 2217385#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_PREFIX_LEN_0_WIDTH 117386#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_PREFIX_LEN_14_OFST 017387#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_PREFIX_LEN_14_LBN 2317388#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_PREFIX_LEN_14_WIDTH 117389#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_TIMESTAMP_OFST 017390#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_TIMESTAMP_LBN 2417391#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_TIMESTAMP_WIDTH 117392#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_BATCHING_OFST 017393#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_BATCHING_LBN 2517394#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_BATCHING_WIDTH 117395#define MC_CMD_GET_CAPABILITIES_V9_OUT_MCAST_FILTER_CHAINING_OFST 017396#define MC_CMD_GET_CAPABILITIES_V9_OUT_MCAST_FILTER_CHAINING_LBN 2617397#define MC_CMD_GET_CAPABILITIES_V9_OUT_MCAST_FILTER_CHAINING_WIDTH 117398#define MC_CMD_GET_CAPABILITIES_V9_OUT_PM_AND_RXDP_COUNTERS_OFST 017399#define MC_CMD_GET_CAPABILITIES_V9_OUT_PM_AND_RXDP_COUNTERS_LBN 2717400#define MC_CMD_GET_CAPABILITIES_V9_OUT_PM_AND_RXDP_COUNTERS_WIDTH 117401#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_DISABLE_SCATTER_OFST 017402#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_DISABLE_SCATTER_LBN 2817403#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_DISABLE_SCATTER_WIDTH 117404#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_MCAST_UDP_LOOPBACK_OFST 017405#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_MCAST_UDP_LOOPBACK_LBN 2917406#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 117407#define MC_CMD_GET_CAPABILITIES_V9_OUT_EVB_OFST 017408#define MC_CMD_GET_CAPABILITIES_V9_OUT_EVB_LBN 3017409#define MC_CMD_GET_CAPABILITIES_V9_OUT_EVB_WIDTH 117410#define MC_CMD_GET_CAPABILITIES_V9_OUT_VXLAN_NVGRE_OFST 017411#define MC_CMD_GET_CAPABILITIES_V9_OUT_VXLAN_NVGRE_LBN 3117412#define MC_CMD_GET_CAPABILITIES_V9_OUT_VXLAN_NVGRE_WIDTH 117413/* RxDPCPU firmware id. */17414#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_DPCPU_FW_ID_OFST 417415#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_DPCPU_FW_ID_LEN 217416/* enum: Standard RXDP firmware */17417#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP 0x017418/* enum: Low latency RXDP firmware */17419#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_LOW_LATENCY 0x117420/* enum: Packed stream RXDP firmware */17421#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_PACKED_STREAM 0x217422/* enum: Rules engine RXDP firmware */17423#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_RULES_ENGINE 0x517424/* enum: DPDK RXDP firmware */17425#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_DPDK 0x617426/* enum: BIST RXDP firmware */17427#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_BIST 0x10a17428/* enum: RXDP Test firmware image 1 */17429#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x10117430/* enum: RXDP Test firmware image 2 */17431#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x10217432/* enum: RXDP Test firmware image 3 */17433#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x10317434/* enum: RXDP Test firmware image 4 */17435#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x10417436/* enum: RXDP Test firmware image 5 */17437#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_BACKPRESSURE 0x10517438/* enum: RXDP Test firmware image 6 */17439#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_FW_PACKET_EDITS 0x10617440/* enum: RXDP Test firmware image 7 */17441#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x10717442/* enum: RXDP Test firmware image 8 */17443#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_FW_DISABLE_DL 0x10817444/* enum: RXDP Test firmware image 9 */17445#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b17446/* enum: RXDP Test firmware image 10 */17447#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_FW_SLOW 0x10c17448/* TxDPCPU firmware id. */17449#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_DPCPU_FW_ID_OFST 617450#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_DPCPU_FW_ID_LEN 217451/* enum: Standard TXDP firmware */17452#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXDP 0x017453/* enum: Low latency TXDP firmware */17454#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXDP_LOW_LATENCY 0x117455/* enum: High packet rate TXDP firmware */17456#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXDP_HIGH_PACKET_RATE 0x317457/* enum: Rules engine TXDP firmware */17458#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXDP_RULES_ENGINE 0x517459/* enum: DPDK TXDP firmware */17460#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXDP_DPDK 0x617461/* enum: BIST TXDP firmware */17462#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXDP_BIST 0x12d17463/* enum: TXDP Test firmware image 1 */17464#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXDP_TEST_FW_TSO_EDIT 0x10117465/* enum: TXDP Test firmware image 2 */17466#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXDP_TEST_FW_PACKET_EDITS 0x10217467/* enum: TXDP CSR bus test firmware */17468#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXDP_TEST_FW_CSR 0x10317469#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_VERSION_OFST 817470#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_VERSION_LEN 217471#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_VERSION_REV_OFST 817472#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_VERSION_REV_LBN 017473#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_VERSION_REV_WIDTH 1217474#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_VERSION_TYPE_OFST 817475#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_VERSION_TYPE_LBN 1217476#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_VERSION_TYPE_WIDTH 417477/* enum: reserved value - do not use (may indicate alternative interpretation17478 * of REV field in future)17479 */17480#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_RESERVED 0x017481/* enum: Trivial RX PD firmware for early Huntington development (Huntington17482 * development only)17483 */17484#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_FIRST_PKT 0x117485/* enum: RX PD firmware for telemetry prototyping (Medford2 development only)17486 */17487#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x117488/* enum: RX PD firmware with approximately Siena-compatible behaviour17489 * (Huntington development only)17490 */17491#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x217492/* enum: Full featured RX PD production firmware */17493#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x317494/* enum: (deprecated original name for the FULL_FEATURED variant) */17495#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_VSWITCH 0x317496/* enum: siena_compat variant RX PD firmware using PM rather than MAC17497 * (Huntington development only)17498 */17499#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x417500/* enum: Low latency RX PD production firmware */17501#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x517502/* enum: Packed stream RX PD production firmware */17503#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x617504/* enum: RX PD firmware handling layer 2 only for high packet rate performance17505 * tests (Medford development only)17506 */17507#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x717508/* enum: Rules engine RX PD production firmware */17509#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x817510/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */17511#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_L3XUDP 0x917512/* enum: DPDK RX PD production firmware */17513#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_DPDK 0xa17514/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */17515#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe17516/* enum: RX PD firmware parsing but not filtering network overlay tunnel17517 * encapsulations (Medford development only)17518 */17519#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf17520#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_VERSION_OFST 1017521#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_VERSION_LEN 217522#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_VERSION_REV_OFST 1017523#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_VERSION_REV_LBN 017524#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_VERSION_REV_WIDTH 1217525#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_VERSION_TYPE_OFST 1017526#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_VERSION_TYPE_LBN 1217527#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_VERSION_TYPE_WIDTH 417528/* enum: reserved value - do not use (may indicate alternative interpretation17529 * of REV field in future)17530 */17531#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_RESERVED 0x017532/* enum: Trivial TX PD firmware for early Huntington development (Huntington17533 * development only)17534 */17535#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_FIRST_PKT 0x117536/* enum: TX PD firmware for telemetry prototyping (Medford2 development only)17537 */17538#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x117539/* enum: TX PD firmware with approximately Siena-compatible behaviour17540 * (Huntington development only)17541 */17542#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x217543/* enum: Full featured TX PD production firmware */17544#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x317545/* enum: (deprecated original name for the FULL_FEATURED variant) */17546#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_VSWITCH 0x317547/* enum: siena_compat variant TX PD firmware using PM rather than MAC17548 * (Huntington development only)17549 */17550#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x417551#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */17552/* enum: TX PD firmware handling layer 2 only for high packet rate performance17553 * tests (Medford development only)17554 */17555#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x717556/* enum: Rules engine TX PD production firmware */17557#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x817558/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */17559#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_L3XUDP 0x917560/* enum: DPDK TX PD production firmware */17561#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_DPDK 0xa17562/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */17563#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe17564/* Hardware capabilities of NIC */17565#define MC_CMD_GET_CAPABILITIES_V9_OUT_HW_CAPABILITIES_OFST 1217566#define MC_CMD_GET_CAPABILITIES_V9_OUT_HW_CAPABILITIES_LEN 417567/* Licensed capabilities */17568#define MC_CMD_GET_CAPABILITIES_V9_OUT_LICENSE_CAPABILITIES_OFST 1617569#define MC_CMD_GET_CAPABILITIES_V9_OUT_LICENSE_CAPABILITIES_LEN 417570/* Second word of flags. Not present on older firmware (check the length). */17571#define MC_CMD_GET_CAPABILITIES_V9_OUT_FLAGS2_OFST 2017572#define MC_CMD_GET_CAPABILITIES_V9_OUT_FLAGS2_LEN 417573#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_V2_OFST 2017574#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_V2_LBN 017575#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_V2_WIDTH 117576#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_V2_ENCAP_OFST 2017577#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_V2_ENCAP_LBN 117578#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_V2_ENCAP_WIDTH 117579#define MC_CMD_GET_CAPABILITIES_V9_OUT_EVQ_TIMER_CTRL_OFST 2017580#define MC_CMD_GET_CAPABILITIES_V9_OUT_EVQ_TIMER_CTRL_LBN 217581#define MC_CMD_GET_CAPABILITIES_V9_OUT_EVQ_TIMER_CTRL_WIDTH 117582#define MC_CMD_GET_CAPABILITIES_V9_OUT_EVENT_CUT_THROUGH_OFST 2017583#define MC_CMD_GET_CAPABILITIES_V9_OUT_EVENT_CUT_THROUGH_LBN 317584#define MC_CMD_GET_CAPABILITIES_V9_OUT_EVENT_CUT_THROUGH_WIDTH 117585#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_CUT_THROUGH_OFST 2017586#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_CUT_THROUGH_LBN 417587#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_CUT_THROUGH_WIDTH 117588#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_VFIFO_ULL_MODE_OFST 2017589#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_VFIFO_ULL_MODE_LBN 517590#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_VFIFO_ULL_MODE_WIDTH 117591#define MC_CMD_GET_CAPABILITIES_V9_OUT_MAC_STATS_40G_TX_SIZE_BINS_OFST 2017592#define MC_CMD_GET_CAPABILITIES_V9_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 617593#define MC_CMD_GET_CAPABILITIES_V9_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 117594#define MC_CMD_GET_CAPABILITIES_V9_OUT_INIT_EVQ_TYPE_SUPPORTED_OFST 2017595#define MC_CMD_GET_CAPABILITIES_V9_OUT_INIT_EVQ_TYPE_SUPPORTED_LBN 717596#define MC_CMD_GET_CAPABILITIES_V9_OUT_INIT_EVQ_TYPE_SUPPORTED_WIDTH 117597#define MC_CMD_GET_CAPABILITIES_V9_OUT_INIT_EVQ_V2_OFST 2017598#define MC_CMD_GET_CAPABILITIES_V9_OUT_INIT_EVQ_V2_LBN 717599#define MC_CMD_GET_CAPABILITIES_V9_OUT_INIT_EVQ_V2_WIDTH 117600#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_MAC_TIMESTAMPING_OFST 2017601#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_MAC_TIMESTAMPING_LBN 817602#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_MAC_TIMESTAMPING_WIDTH 117603#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TIMESTAMP_OFST 2017604#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TIMESTAMP_LBN 917605#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TIMESTAMP_WIDTH 117606#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_SNIFF_OFST 2017607#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_SNIFF_LBN 1017608#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_SNIFF_WIDTH 117609#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_SNIFF_OFST 2017610#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_SNIFF_LBN 1117611#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_SNIFF_WIDTH 117612#define MC_CMD_GET_CAPABILITIES_V9_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_OFST 2017613#define MC_CMD_GET_CAPABILITIES_V9_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_LBN 1217614#define MC_CMD_GET_CAPABILITIES_V9_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 117615#define MC_CMD_GET_CAPABILITIES_V9_OUT_MCDI_BACKGROUND_OFST 2017616#define MC_CMD_GET_CAPABILITIES_V9_OUT_MCDI_BACKGROUND_LBN 1317617#define MC_CMD_GET_CAPABILITIES_V9_OUT_MCDI_BACKGROUND_WIDTH 117618#define MC_CMD_GET_CAPABILITIES_V9_OUT_MCDI_DB_RETURN_OFST 2017619#define MC_CMD_GET_CAPABILITIES_V9_OUT_MCDI_DB_RETURN_LBN 1417620#define MC_CMD_GET_CAPABILITIES_V9_OUT_MCDI_DB_RETURN_WIDTH 117621#define MC_CMD_GET_CAPABILITIES_V9_OUT_CTPIO_OFST 2017622#define MC_CMD_GET_CAPABILITIES_V9_OUT_CTPIO_LBN 1517623#define MC_CMD_GET_CAPABILITIES_V9_OUT_CTPIO_WIDTH 117624#define MC_CMD_GET_CAPABILITIES_V9_OUT_TSA_SUPPORT_OFST 2017625#define MC_CMD_GET_CAPABILITIES_V9_OUT_TSA_SUPPORT_LBN 1617626#define MC_CMD_GET_CAPABILITIES_V9_OUT_TSA_SUPPORT_WIDTH 117627#define MC_CMD_GET_CAPABILITIES_V9_OUT_TSA_BOUND_OFST 2017628#define MC_CMD_GET_CAPABILITIES_V9_OUT_TSA_BOUND_LBN 1717629#define MC_CMD_GET_CAPABILITIES_V9_OUT_TSA_BOUND_WIDTH 117630#define MC_CMD_GET_CAPABILITIES_V9_OUT_SF_ADAPTER_AUTHENTICATION_OFST 2017631#define MC_CMD_GET_CAPABILITIES_V9_OUT_SF_ADAPTER_AUTHENTICATION_LBN 1817632#define MC_CMD_GET_CAPABILITIES_V9_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 117633#define MC_CMD_GET_CAPABILITIES_V9_OUT_FILTER_ACTION_FLAG_OFST 2017634#define MC_CMD_GET_CAPABILITIES_V9_OUT_FILTER_ACTION_FLAG_LBN 1917635#define MC_CMD_GET_CAPABILITIES_V9_OUT_FILTER_ACTION_FLAG_WIDTH 117636#define MC_CMD_GET_CAPABILITIES_V9_OUT_FILTER_ACTION_MARK_OFST 2017637#define MC_CMD_GET_CAPABILITIES_V9_OUT_FILTER_ACTION_MARK_LBN 2017638#define MC_CMD_GET_CAPABILITIES_V9_OUT_FILTER_ACTION_MARK_WIDTH 117639#define MC_CMD_GET_CAPABILITIES_V9_OUT_EQUAL_STRIDE_SUPER_BUFFER_OFST 2017640#define MC_CMD_GET_CAPABILITIES_V9_OUT_EQUAL_STRIDE_SUPER_BUFFER_LBN 2117641#define MC_CMD_GET_CAPABILITIES_V9_OUT_EQUAL_STRIDE_SUPER_BUFFER_WIDTH 117642#define MC_CMD_GET_CAPABILITIES_V9_OUT_EQUAL_STRIDE_PACKED_STREAM_OFST 2017643#define MC_CMD_GET_CAPABILITIES_V9_OUT_EQUAL_STRIDE_PACKED_STREAM_LBN 2117644#define MC_CMD_GET_CAPABILITIES_V9_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 117645#define MC_CMD_GET_CAPABILITIES_V9_OUT_L3XUDP_SUPPORT_OFST 2017646#define MC_CMD_GET_CAPABILITIES_V9_OUT_L3XUDP_SUPPORT_LBN 2217647#define MC_CMD_GET_CAPABILITIES_V9_OUT_L3XUDP_SUPPORT_WIDTH 117648#define MC_CMD_GET_CAPABILITIES_V9_OUT_FW_SUBVARIANT_NO_TX_CSUM_OFST 2017649#define MC_CMD_GET_CAPABILITIES_V9_OUT_FW_SUBVARIANT_NO_TX_CSUM_LBN 2317650#define MC_CMD_GET_CAPABILITIES_V9_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 117651#define MC_CMD_GET_CAPABILITIES_V9_OUT_VI_SPREADING_OFST 2017652#define MC_CMD_GET_CAPABILITIES_V9_OUT_VI_SPREADING_LBN 2417653#define MC_CMD_GET_CAPABILITIES_V9_OUT_VI_SPREADING_WIDTH 117654#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_HLB_IDLE_OFST 2017655#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_HLB_IDLE_LBN 2517656#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_HLB_IDLE_WIDTH 117657#define MC_CMD_GET_CAPABILITIES_V9_OUT_INIT_RXQ_NO_CONT_EV_OFST 2017658#define MC_CMD_GET_CAPABILITIES_V9_OUT_INIT_RXQ_NO_CONT_EV_LBN 2617659#define MC_CMD_GET_CAPABILITIES_V9_OUT_INIT_RXQ_NO_CONT_EV_WIDTH 117660#define MC_CMD_GET_CAPABILITIES_V9_OUT_INIT_RXQ_WITH_BUFFER_SIZE_OFST 2017661#define MC_CMD_GET_CAPABILITIES_V9_OUT_INIT_RXQ_WITH_BUFFER_SIZE_LBN 2717662#define MC_CMD_GET_CAPABILITIES_V9_OUT_INIT_RXQ_WITH_BUFFER_SIZE_WIDTH 117663#define MC_CMD_GET_CAPABILITIES_V9_OUT_BUNDLE_UPDATE_OFST 2017664#define MC_CMD_GET_CAPABILITIES_V9_OUT_BUNDLE_UPDATE_LBN 2817665#define MC_CMD_GET_CAPABILITIES_V9_OUT_BUNDLE_UPDATE_WIDTH 117666#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_V3_OFST 2017667#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_V3_LBN 2917668#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_V3_WIDTH 117669#define MC_CMD_GET_CAPABILITIES_V9_OUT_DYNAMIC_SENSORS_OFST 2017670#define MC_CMD_GET_CAPABILITIES_V9_OUT_DYNAMIC_SENSORS_LBN 3017671#define MC_CMD_GET_CAPABILITIES_V9_OUT_DYNAMIC_SENSORS_WIDTH 117672#define MC_CMD_GET_CAPABILITIES_V9_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_OFST 2017673#define MC_CMD_GET_CAPABILITIES_V9_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_LBN 3117674#define MC_CMD_GET_CAPABILITIES_V9_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_WIDTH 117675/* Number of FATSOv2 contexts per datapath supported by this NIC (when17676 * TX_TSO_V2 == 1). Not present on older firmware (check the length).17677 */17678#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_V2_N_CONTEXTS_OFST 2417679#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_V2_N_CONTEXTS_LEN 217680/* One byte per PF containing the number of the external port assigned to this17681 * PF, indexed by PF number. Special values indicate that a PF is either not17682 * present or not assigned.17683 */17684#define MC_CMD_GET_CAPABILITIES_V9_OUT_PFS_TO_PORTS_ASSIGNMENT_OFST 2617685#define MC_CMD_GET_CAPABILITIES_V9_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 117686#define MC_CMD_GET_CAPABILITIES_V9_OUT_PFS_TO_PORTS_ASSIGNMENT_NUM 1617687/* enum: The caller is not permitted to access information on this PF. */17688#define MC_CMD_GET_CAPABILITIES_V9_OUT_ACCESS_NOT_PERMITTED 0xff17689/* enum: PF does not exist. */17690#define MC_CMD_GET_CAPABILITIES_V9_OUT_PF_NOT_PRESENT 0xfe17691/* enum: PF does exist but is not assigned to any external port. */17692#define MC_CMD_GET_CAPABILITIES_V9_OUT_PF_NOT_ASSIGNED 0xfd17693/* enum: This value indicates that PF is assigned, but it cannot be expressed17694 * in this field. It is intended for a possible future situation where a more17695 * complex scheme of PFs to ports mapping is being used. The future driver17696 * should look for a new field supporting the new scheme. The current/old17697 * driver should treat this value as PF_NOT_ASSIGNED.17698 */17699#define MC_CMD_GET_CAPABILITIES_V9_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc17700/* One byte per PF containing the number of its VFs, indexed by PF number. A17701 * special value indicates that a PF is not present.17702 */17703#define MC_CMD_GET_CAPABILITIES_V9_OUT_NUM_VFS_PER_PF_OFST 4217704#define MC_CMD_GET_CAPABILITIES_V9_OUT_NUM_VFS_PER_PF_LEN 117705#define MC_CMD_GET_CAPABILITIES_V9_OUT_NUM_VFS_PER_PF_NUM 1617706/* enum: The caller is not permitted to access information on this PF. */17707/* MC_CMD_GET_CAPABILITIES_V9_OUT_ACCESS_NOT_PERMITTED 0xff */17708/* enum: PF does not exist. */17709/* MC_CMD_GET_CAPABILITIES_V9_OUT_PF_NOT_PRESENT 0xfe */17710/* Number of VIs available for each external port */17711#define MC_CMD_GET_CAPABILITIES_V9_OUT_NUM_VIS_PER_PORT_OFST 5817712#define MC_CMD_GET_CAPABILITIES_V9_OUT_NUM_VIS_PER_PORT_LEN 217713#define MC_CMD_GET_CAPABILITIES_V9_OUT_NUM_VIS_PER_PORT_NUM 417714/* Size of RX descriptor cache expressed as binary logarithm The actual size17715 * equals (2 ^ RX_DESC_CACHE_SIZE)17716 */17717#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_DESC_CACHE_SIZE_OFST 6617718#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_DESC_CACHE_SIZE_LEN 117719/* Size of TX descriptor cache expressed as binary logarithm The actual size17720 * equals (2 ^ TX_DESC_CACHE_SIZE)17721 */17722#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_DESC_CACHE_SIZE_OFST 6717723#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_DESC_CACHE_SIZE_LEN 117724/* Total number of available PIO buffers */17725#define MC_CMD_GET_CAPABILITIES_V9_OUT_NUM_PIO_BUFFS_OFST 6817726#define MC_CMD_GET_CAPABILITIES_V9_OUT_NUM_PIO_BUFFS_LEN 217727/* Size of a single PIO buffer */17728#define MC_CMD_GET_CAPABILITIES_V9_OUT_SIZE_PIO_BUFF_OFST 7017729#define MC_CMD_GET_CAPABILITIES_V9_OUT_SIZE_PIO_BUFF_LEN 217730/* On chips later than Medford the amount of address space assigned to each VI17731 * is configurable. This is a global setting that the driver must query to17732 * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available17733 * with 8k VI windows.17734 */17735#define MC_CMD_GET_CAPABILITIES_V9_OUT_VI_WINDOW_MODE_OFST 7217736#define MC_CMD_GET_CAPABILITIES_V9_OUT_VI_WINDOW_MODE_LEN 117737/* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k.17738 * CTPIO is not mapped.17739 */17740#define MC_CMD_GET_CAPABILITIES_V9_OUT_VI_WINDOW_MODE_8K 0x017741/* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */17742#define MC_CMD_GET_CAPABILITIES_V9_OUT_VI_WINDOW_MODE_16K 0x117743/* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */17744#define MC_CMD_GET_CAPABILITIES_V9_OUT_VI_WINDOW_MODE_64K 0x217745/* Number of vFIFOs per adapter that can be used for VFIFO Stuffing17746 * (SF-115995-SW) in the present configuration of firmware and port mode.17747 */17748#define MC_CMD_GET_CAPABILITIES_V9_OUT_VFIFO_STUFFING_NUM_VFIFOS_OFST 7317749#define MC_CMD_GET_CAPABILITIES_V9_OUT_VFIFO_STUFFING_NUM_VFIFOS_LEN 117750/* Number of buffers per adapter that can be used for VFIFO Stuffing17751 * (SF-115995-SW) in the present configuration of firmware and port mode.17752 */17753#define MC_CMD_GET_CAPABILITIES_V9_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_OFST 7417754#define MC_CMD_GET_CAPABILITIES_V9_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_LEN 217755/* Entry count in the MAC stats array, including the final GENERATION_END17756 * entry. For MAC stats DMA, drivers should allocate a buffer large enough to17757 * hold at least this many 64-bit stats values, if they wish to receive all17758 * available stats. If the buffer is shorter than MAC_STATS_NUM_STATS * 8, the17759 * stats array returned will be truncated.17760 */17761#define MC_CMD_GET_CAPABILITIES_V9_OUT_MAC_STATS_NUM_STATS_OFST 7617762#define MC_CMD_GET_CAPABILITIES_V9_OUT_MAC_STATS_NUM_STATS_LEN 217763/* Maximum supported value for MC_CMD_FILTER_OP_V3/MATCH_MARK_VALUE. This field17764 * will only be non-zero if MC_CMD_GET_CAPABILITIES/FILTER_ACTION_MARK is set.17765 */17766#define MC_CMD_GET_CAPABILITIES_V9_OUT_FILTER_ACTION_MARK_MAX_OFST 8017767#define MC_CMD_GET_CAPABILITIES_V9_OUT_FILTER_ACTION_MARK_MAX_LEN 417768/* On devices where the INIT_RXQ_WITH_BUFFER_SIZE flag (in17769 * GET_CAPABILITIES_OUT_V2) is set, drivers have to specify a buffer size when17770 * they create an RX queue. Due to hardware limitations, only a small number of17771 * different buffer sizes may be available concurrently. Nonzero entries in17772 * this array are the sizes of buffers which the system guarantees will be17773 * available for use. If the list is empty, there are no limitations on17774 * concurrent buffer sizes.17775 */17776#define MC_CMD_GET_CAPABILITIES_V9_OUT_GUARANTEED_RX_BUFFER_SIZES_OFST 8417777#define MC_CMD_GET_CAPABILITIES_V9_OUT_GUARANTEED_RX_BUFFER_SIZES_LEN 417778#define MC_CMD_GET_CAPABILITIES_V9_OUT_GUARANTEED_RX_BUFFER_SIZES_NUM 1617779/* Third word of flags. Not present on older firmware (check the length). */17780#define MC_CMD_GET_CAPABILITIES_V9_OUT_FLAGS3_OFST 14817781#define MC_CMD_GET_CAPABILITIES_V9_OUT_FLAGS3_LEN 417782#define MC_CMD_GET_CAPABILITIES_V9_OUT_WOL_ETHERWAKE_OFST 14817783#define MC_CMD_GET_CAPABILITIES_V9_OUT_WOL_ETHERWAKE_LBN 017784#define MC_CMD_GET_CAPABILITIES_V9_OUT_WOL_ETHERWAKE_WIDTH 117785#define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_EVEN_SPREADING_OFST 14817786#define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_EVEN_SPREADING_LBN 117787#define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_EVEN_SPREADING_WIDTH 117788#define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_SELECTABLE_TABLE_SIZE_OFST 14817789#define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_SELECTABLE_TABLE_SIZE_LBN 217790#define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_SELECTABLE_TABLE_SIZE_WIDTH 117791#define MC_CMD_GET_CAPABILITIES_V9_OUT_MAE_SUPPORTED_OFST 14817792#define MC_CMD_GET_CAPABILITIES_V9_OUT_MAE_SUPPORTED_LBN 317793#define MC_CMD_GET_CAPABILITIES_V9_OUT_MAE_SUPPORTED_WIDTH 117794#define MC_CMD_GET_CAPABILITIES_V9_OUT_VDPA_SUPPORTED_OFST 14817795#define MC_CMD_GET_CAPABILITIES_V9_OUT_VDPA_SUPPORTED_LBN 417796#define MC_CMD_GET_CAPABILITIES_V9_OUT_VDPA_SUPPORTED_WIDTH 117797#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_OFST 14817798#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_LBN 517799#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_WIDTH 117800#define MC_CMD_GET_CAPABILITIES_V9_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_OFST 14817801#define MC_CMD_GET_CAPABILITIES_V9_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_LBN 617802#define MC_CMD_GET_CAPABILITIES_V9_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_WIDTH 117803#define MC_CMD_GET_CAPABILITIES_V9_OUT_UNSOL_EV_CREDIT_SUPPORTED_OFST 14817804#define MC_CMD_GET_CAPABILITIES_V9_OUT_UNSOL_EV_CREDIT_SUPPORTED_LBN 717805#define MC_CMD_GET_CAPABILITIES_V9_OUT_UNSOL_EV_CREDIT_SUPPORTED_WIDTH 117806#define MC_CMD_GET_CAPABILITIES_V9_OUT_ENCAPSULATED_MCDI_SUPPORTED_OFST 14817807#define MC_CMD_GET_CAPABILITIES_V9_OUT_ENCAPSULATED_MCDI_SUPPORTED_LBN 817808#define MC_CMD_GET_CAPABILITIES_V9_OUT_ENCAPSULATED_MCDI_SUPPORTED_WIDTH 117809#define MC_CMD_GET_CAPABILITIES_V9_OUT_EXTERNAL_MAE_SUPPORTED_OFST 14817810#define MC_CMD_GET_CAPABILITIES_V9_OUT_EXTERNAL_MAE_SUPPORTED_LBN 917811#define MC_CMD_GET_CAPABILITIES_V9_OUT_EXTERNAL_MAE_SUPPORTED_WIDTH 117812#define MC_CMD_GET_CAPABILITIES_V9_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_OFST 14817813#define MC_CMD_GET_CAPABILITIES_V9_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_LBN 1017814#define MC_CMD_GET_CAPABILITIES_V9_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_WIDTH 117815#define MC_CMD_GET_CAPABILITIES_V9_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_OFST 14817816#define MC_CMD_GET_CAPABILITIES_V9_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_LBN 1117817#define MC_CMD_GET_CAPABILITIES_V9_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_WIDTH 117818#define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_STEER_ON_OUTER_SUPPORTED_OFST 14817819#define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_STEER_ON_OUTER_SUPPORTED_LBN 1217820#define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_STEER_ON_OUTER_SUPPORTED_WIDTH 117821#define MC_CMD_GET_CAPABILITIES_V9_OUT_DYNAMIC_MPORT_JOURNAL_OFST 14817822#define MC_CMD_GET_CAPABILITIES_V9_OUT_DYNAMIC_MPORT_JOURNAL_LBN 1417823#define MC_CMD_GET_CAPABILITIES_V9_OUT_DYNAMIC_MPORT_JOURNAL_WIDTH 117824/* These bits are reserved for communicating test-specific capabilities to17825 * host-side test software. All production drivers should treat this field as17826 * opaque.17827 */17828#define MC_CMD_GET_CAPABILITIES_V9_OUT_TEST_RESERVED_OFST 15217829#define MC_CMD_GET_CAPABILITIES_V9_OUT_TEST_RESERVED_LEN 817830#define MC_CMD_GET_CAPABILITIES_V9_OUT_TEST_RESERVED_LO_OFST 15217831#define MC_CMD_GET_CAPABILITIES_V9_OUT_TEST_RESERVED_LO_LEN 417832#define MC_CMD_GET_CAPABILITIES_V9_OUT_TEST_RESERVED_LO_LBN 121617833#define MC_CMD_GET_CAPABILITIES_V9_OUT_TEST_RESERVED_LO_WIDTH 3217834#define MC_CMD_GET_CAPABILITIES_V9_OUT_TEST_RESERVED_HI_OFST 15617835#define MC_CMD_GET_CAPABILITIES_V9_OUT_TEST_RESERVED_HI_LEN 417836#define MC_CMD_GET_CAPABILITIES_V9_OUT_TEST_RESERVED_HI_LBN 124817837#define MC_CMD_GET_CAPABILITIES_V9_OUT_TEST_RESERVED_HI_WIDTH 3217838/* The minimum size (in table entries) of indirection table to be allocated17839 * from the pool for an RSS context. Note that the table size used must be a17840 * power of 2.17841 */17842#define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_MIN_INDIRECTION_TABLE_SIZE_OFST 16017843#define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_MIN_INDIRECTION_TABLE_SIZE_LEN 417844/* The maximum size (in table entries) of indirection table to be allocated17845 * from the pool for an RSS context. Note that the table size used must be a17846 * power of 2.17847 */17848#define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_MAX_INDIRECTION_TABLE_SIZE_OFST 16417849#define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_MAX_INDIRECTION_TABLE_SIZE_LEN 417850/* The maximum number of queues that can be used by an RSS context in exclusive17851 * mode. In exclusive mode the context has a configurable indirection table and17852 * a configurable RSS key.17853 */17854#define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_MAX_INDIRECTION_QUEUES_OFST 16817855#define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_MAX_INDIRECTION_QUEUES_LEN 417856/* The maximum number of queues that can be used by an RSS context in even-17857 * spreading mode. In even-spreading mode the context has no indirection table17858 * but it does have a configurable RSS key.17859 */17860#define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_MAX_EVEN_SPREADING_QUEUES_OFST 17217861#define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_MAX_EVEN_SPREADING_QUEUES_LEN 417862/* The total number of RSS contexts supported. Note that the number of17863 * available contexts using indirection tables is also limited by the17864 * availability of indirection table space allocated from a common pool.17865 */17866#define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_NUM_CONTEXTS_OFST 17617867#define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_NUM_CONTEXTS_LEN 417868/* The total amount of indirection table space that can be shared between RSS17869 * contexts.17870 */17871#define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_TABLE_POOL_SIZE_OFST 18017872#define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_TABLE_POOL_SIZE_LEN 417873 17874/* MC_CMD_GET_CAPABILITIES_V10_OUT msgresponse */17875#define MC_CMD_GET_CAPABILITIES_V10_OUT_LEN 19217876/* First word of flags. */17877#define MC_CMD_GET_CAPABILITIES_V10_OUT_FLAGS1_OFST 017878#define MC_CMD_GET_CAPABILITIES_V10_OUT_FLAGS1_LEN 417879#define MC_CMD_GET_CAPABILITIES_V10_OUT_VPORT_RECONFIGURE_OFST 017880#define MC_CMD_GET_CAPABILITIES_V10_OUT_VPORT_RECONFIGURE_LBN 317881#define MC_CMD_GET_CAPABILITIES_V10_OUT_VPORT_RECONFIGURE_WIDTH 117882#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_STRIPING_OFST 017883#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_STRIPING_LBN 417884#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_STRIPING_WIDTH 117885#define MC_CMD_GET_CAPABILITIES_V10_OUT_VADAPTOR_QUERY_OFST 017886#define MC_CMD_GET_CAPABILITIES_V10_OUT_VADAPTOR_QUERY_LBN 517887#define MC_CMD_GET_CAPABILITIES_V10_OUT_VADAPTOR_QUERY_WIDTH 117888#define MC_CMD_GET_CAPABILITIES_V10_OUT_EVB_PORT_VLAN_RESTRICT_OFST 017889#define MC_CMD_GET_CAPABILITIES_V10_OUT_EVB_PORT_VLAN_RESTRICT_LBN 617890#define MC_CMD_GET_CAPABILITIES_V10_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 117891#define MC_CMD_GET_CAPABILITIES_V10_OUT_DRV_ATTACH_PREBOOT_OFST 017892#define MC_CMD_GET_CAPABILITIES_V10_OUT_DRV_ATTACH_PREBOOT_LBN 717893#define MC_CMD_GET_CAPABILITIES_V10_OUT_DRV_ATTACH_PREBOOT_WIDTH 117894#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_FORCE_EVENT_MERGING_OFST 017895#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_FORCE_EVENT_MERGING_LBN 817896#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_FORCE_EVENT_MERGING_WIDTH 117897#define MC_CMD_GET_CAPABILITIES_V10_OUT_SET_MAC_ENHANCED_OFST 017898#define MC_CMD_GET_CAPABILITIES_V10_OUT_SET_MAC_ENHANCED_LBN 917899#define MC_CMD_GET_CAPABILITIES_V10_OUT_SET_MAC_ENHANCED_WIDTH 117900#define MC_CMD_GET_CAPABILITIES_V10_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 017901#define MC_CMD_GET_CAPABILITIES_V10_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 1017902#define MC_CMD_GET_CAPABILITIES_V10_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 117903#define MC_CMD_GET_CAPABILITIES_V10_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 017904#define MC_CMD_GET_CAPABILITIES_V10_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 1117905#define MC_CMD_GET_CAPABILITIES_V10_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 117906#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_MAC_SECURITY_FILTERING_OFST 017907#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_MAC_SECURITY_FILTERING_LBN 1217908#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 117909#define MC_CMD_GET_CAPABILITIES_V10_OUT_ADDITIONAL_RSS_MODES_OFST 017910#define MC_CMD_GET_CAPABILITIES_V10_OUT_ADDITIONAL_RSS_MODES_LBN 1317911#define MC_CMD_GET_CAPABILITIES_V10_OUT_ADDITIONAL_RSS_MODES_WIDTH 117912#define MC_CMD_GET_CAPABILITIES_V10_OUT_QBB_OFST 017913#define MC_CMD_GET_CAPABILITIES_V10_OUT_QBB_LBN 1417914#define MC_CMD_GET_CAPABILITIES_V10_OUT_QBB_WIDTH 117915#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 017916#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 1517917#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 117918#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_RSS_LIMITED_OFST 017919#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_RSS_LIMITED_LBN 1617920#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_RSS_LIMITED_WIDTH 117921#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_PACKED_STREAM_OFST 017922#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_PACKED_STREAM_LBN 1717923#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_PACKED_STREAM_WIDTH 117924#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_INCLUDE_FCS_OFST 017925#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_INCLUDE_FCS_LBN 1817926#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_INCLUDE_FCS_WIDTH 117927#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_VLAN_INSERTION_OFST 017928#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_VLAN_INSERTION_LBN 1917929#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_VLAN_INSERTION_WIDTH 117930#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_VLAN_STRIPPING_OFST 017931#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_VLAN_STRIPPING_LBN 2017932#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_VLAN_STRIPPING_WIDTH 117933#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_TSO_OFST 017934#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_TSO_LBN 2117935#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_TSO_WIDTH 117936#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_PREFIX_LEN_0_OFST 017937#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_PREFIX_LEN_0_LBN 2217938#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_PREFIX_LEN_0_WIDTH 117939#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_PREFIX_LEN_14_OFST 017940#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_PREFIX_LEN_14_LBN 2317941#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_PREFIX_LEN_14_WIDTH 117942#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_TIMESTAMP_OFST 017943#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_TIMESTAMP_LBN 2417944#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_TIMESTAMP_WIDTH 117945#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_BATCHING_OFST 017946#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_BATCHING_LBN 2517947#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_BATCHING_WIDTH 117948#define MC_CMD_GET_CAPABILITIES_V10_OUT_MCAST_FILTER_CHAINING_OFST 017949#define MC_CMD_GET_CAPABILITIES_V10_OUT_MCAST_FILTER_CHAINING_LBN 2617950#define MC_CMD_GET_CAPABILITIES_V10_OUT_MCAST_FILTER_CHAINING_WIDTH 117951#define MC_CMD_GET_CAPABILITIES_V10_OUT_PM_AND_RXDP_COUNTERS_OFST 017952#define MC_CMD_GET_CAPABILITIES_V10_OUT_PM_AND_RXDP_COUNTERS_LBN 2717953#define MC_CMD_GET_CAPABILITIES_V10_OUT_PM_AND_RXDP_COUNTERS_WIDTH 117954#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_DISABLE_SCATTER_OFST 017955#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_DISABLE_SCATTER_LBN 2817956#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_DISABLE_SCATTER_WIDTH 117957#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_MCAST_UDP_LOOPBACK_OFST 017958#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_MCAST_UDP_LOOPBACK_LBN 2917959#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 117960#define MC_CMD_GET_CAPABILITIES_V10_OUT_EVB_OFST 017961#define MC_CMD_GET_CAPABILITIES_V10_OUT_EVB_LBN 3017962#define MC_CMD_GET_CAPABILITIES_V10_OUT_EVB_WIDTH 117963#define MC_CMD_GET_CAPABILITIES_V10_OUT_VXLAN_NVGRE_OFST 017964#define MC_CMD_GET_CAPABILITIES_V10_OUT_VXLAN_NVGRE_LBN 3117965#define MC_CMD_GET_CAPABILITIES_V10_OUT_VXLAN_NVGRE_WIDTH 117966/* RxDPCPU firmware id. */17967#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_DPCPU_FW_ID_OFST 417968#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_DPCPU_FW_ID_LEN 217969/* enum: Standard RXDP firmware */17970#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXDP 0x017971/* enum: Low latency RXDP firmware */17972#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_LOW_LATENCY 0x117973/* enum: Packed stream RXDP firmware */17974#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_PACKED_STREAM 0x217975/* enum: Rules engine RXDP firmware */17976#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_RULES_ENGINE 0x517977/* enum: DPDK RXDP firmware */17978#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_DPDK 0x617979/* enum: BIST RXDP firmware */17980#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_BIST 0x10a17981/* enum: RXDP Test firmware image 1 */17982#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x10117983/* enum: RXDP Test firmware image 2 */17984#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x10217985/* enum: RXDP Test firmware image 3 */17986#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x10317987/* enum: RXDP Test firmware image 4 */17988#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x10417989/* enum: RXDP Test firmware image 5 */17990#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_TEST_BACKPRESSURE 0x10517991/* enum: RXDP Test firmware image 6 */17992#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_TEST_FW_PACKET_EDITS 0x10617993/* enum: RXDP Test firmware image 7 */17994#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x10717995/* enum: RXDP Test firmware image 8 */17996#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_TEST_FW_DISABLE_DL 0x10817997/* enum: RXDP Test firmware image 9 */17998#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b17999/* enum: RXDP Test firmware image 10 */18000#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_TEST_FW_SLOW 0x10c18001/* TxDPCPU firmware id. */18002#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_DPCPU_FW_ID_OFST 618003#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_DPCPU_FW_ID_LEN 218004/* enum: Standard TXDP firmware */18005#define MC_CMD_GET_CAPABILITIES_V10_OUT_TXDP 0x018006/* enum: Low latency TXDP firmware */18007#define MC_CMD_GET_CAPABILITIES_V10_OUT_TXDP_LOW_LATENCY 0x118008/* enum: High packet rate TXDP firmware */18009#define MC_CMD_GET_CAPABILITIES_V10_OUT_TXDP_HIGH_PACKET_RATE 0x318010/* enum: Rules engine TXDP firmware */18011#define MC_CMD_GET_CAPABILITIES_V10_OUT_TXDP_RULES_ENGINE 0x518012/* enum: DPDK TXDP firmware */18013#define MC_CMD_GET_CAPABILITIES_V10_OUT_TXDP_DPDK 0x618014/* enum: BIST TXDP firmware */18015#define MC_CMD_GET_CAPABILITIES_V10_OUT_TXDP_BIST 0x12d18016/* enum: TXDP Test firmware image 1 */18017#define MC_CMD_GET_CAPABILITIES_V10_OUT_TXDP_TEST_FW_TSO_EDIT 0x10118018/* enum: TXDP Test firmware image 2 */18019#define MC_CMD_GET_CAPABILITIES_V10_OUT_TXDP_TEST_FW_PACKET_EDITS 0x10218020/* enum: TXDP CSR bus test firmware */18021#define MC_CMD_GET_CAPABILITIES_V10_OUT_TXDP_TEST_FW_CSR 0x10318022#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_VERSION_OFST 818023#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_VERSION_LEN 218024#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_VERSION_REV_OFST 818025#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_VERSION_REV_LBN 018026#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_VERSION_REV_WIDTH 1218027#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_VERSION_TYPE_OFST 818028#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_VERSION_TYPE_LBN 1218029#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_VERSION_TYPE_WIDTH 418030/* enum: reserved value - do not use (may indicate alternative interpretation18031 * of REV field in future)18032 */18033#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_TYPE_RESERVED 0x018034/* enum: Trivial RX PD firmware for early Huntington development (Huntington18035 * development only)18036 */18037#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_TYPE_FIRST_PKT 0x118038/* enum: RX PD firmware for telemetry prototyping (Medford2 development only)18039 */18040#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x118041/* enum: RX PD firmware with approximately Siena-compatible behaviour18042 * (Huntington development only)18043 */18044#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x218045/* enum: Full featured RX PD production firmware */18046#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x318047/* enum: (deprecated original name for the FULL_FEATURED variant) */18048#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_TYPE_VSWITCH 0x318049/* enum: siena_compat variant RX PD firmware using PM rather than MAC18050 * (Huntington development only)18051 */18052#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x418053/* enum: Low latency RX PD production firmware */18054#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x518055/* enum: Packed stream RX PD production firmware */18056#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x618057/* enum: RX PD firmware handling layer 2 only for high packet rate performance18058 * tests (Medford development only)18059 */18060#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x718061/* enum: Rules engine RX PD production firmware */18062#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x818063/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */18064#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_TYPE_L3XUDP 0x918065/* enum: DPDK RX PD production firmware */18066#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_TYPE_DPDK 0xa18067/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */18068#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe18069/* enum: RX PD firmware parsing but not filtering network overlay tunnel18070 * encapsulations (Medford development only)18071 */18072#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf18073#define MC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_VERSION_OFST 1018074#define MC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_VERSION_LEN 218075#define MC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_VERSION_REV_OFST 1018076#define MC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_VERSION_REV_LBN 018077#define MC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_VERSION_REV_WIDTH 1218078#define MC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_VERSION_TYPE_OFST 1018079#define MC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_VERSION_TYPE_LBN 1218080#define MC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_VERSION_TYPE_WIDTH 418081/* enum: reserved value - do not use (may indicate alternative interpretation18082 * of REV field in future)18083 */18084#define MC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_TYPE_RESERVED 0x018085/* enum: Trivial TX PD firmware for early Huntington development (Huntington18086 * development only)18087 */18088#define MC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_TYPE_FIRST_PKT 0x118089/* enum: TX PD firmware for telemetry prototyping (Medford2 development only)18090 */18091#define MC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x118092/* enum: TX PD firmware with approximately Siena-compatible behaviour18093 * (Huntington development only)18094 */18095#define MC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x218096/* enum: Full featured TX PD production firmware */18097#define MC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x318098/* enum: (deprecated original name for the FULL_FEATURED variant) */18099#define MC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_TYPE_VSWITCH 0x318100/* enum: siena_compat variant TX PD firmware using PM rather than MAC18101 * (Huntington development only)18102 */18103#define MC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x418104#define MC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */18105/* enum: TX PD firmware handling layer 2 only for high packet rate performance18106 * tests (Medford development only)18107 */18108#define MC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x718109/* enum: Rules engine TX PD production firmware */18110#define MC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x818111/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */18112#define MC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_TYPE_L3XUDP 0x918113/* enum: DPDK TX PD production firmware */18114#define MC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_TYPE_DPDK 0xa18115/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */18116#define MC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe18117/* Hardware capabilities of NIC */18118#define MC_CMD_GET_CAPABILITIES_V10_OUT_HW_CAPABILITIES_OFST 1218119#define MC_CMD_GET_CAPABILITIES_V10_OUT_HW_CAPABILITIES_LEN 418120/* Licensed capabilities */18121#define MC_CMD_GET_CAPABILITIES_V10_OUT_LICENSE_CAPABILITIES_OFST 1618122#define MC_CMD_GET_CAPABILITIES_V10_OUT_LICENSE_CAPABILITIES_LEN 418123/* Second word of flags. Not present on older firmware (check the length). */18124#define MC_CMD_GET_CAPABILITIES_V10_OUT_FLAGS2_OFST 2018125#define MC_CMD_GET_CAPABILITIES_V10_OUT_FLAGS2_LEN 418126#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_TSO_V2_OFST 2018127#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_TSO_V2_LBN 018128#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_TSO_V2_WIDTH 118129#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_TSO_V2_ENCAP_OFST 2018130#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_TSO_V2_ENCAP_LBN 118131#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_TSO_V2_ENCAP_WIDTH 118132#define MC_CMD_GET_CAPABILITIES_V10_OUT_EVQ_TIMER_CTRL_OFST 2018133#define MC_CMD_GET_CAPABILITIES_V10_OUT_EVQ_TIMER_CTRL_LBN 218134#define MC_CMD_GET_CAPABILITIES_V10_OUT_EVQ_TIMER_CTRL_WIDTH 118135#define MC_CMD_GET_CAPABILITIES_V10_OUT_EVENT_CUT_THROUGH_OFST 2018136#define MC_CMD_GET_CAPABILITIES_V10_OUT_EVENT_CUT_THROUGH_LBN 318137#define MC_CMD_GET_CAPABILITIES_V10_OUT_EVENT_CUT_THROUGH_WIDTH 118138#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_CUT_THROUGH_OFST 2018139#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_CUT_THROUGH_LBN 418140#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_CUT_THROUGH_WIDTH 118141#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_VFIFO_ULL_MODE_OFST 2018142#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_VFIFO_ULL_MODE_LBN 518143#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_VFIFO_ULL_MODE_WIDTH 118144#define MC_CMD_GET_CAPABILITIES_V10_OUT_MAC_STATS_40G_TX_SIZE_BINS_OFST 2018145#define MC_CMD_GET_CAPABILITIES_V10_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 618146#define MC_CMD_GET_CAPABILITIES_V10_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 118147#define MC_CMD_GET_CAPABILITIES_V10_OUT_INIT_EVQ_TYPE_SUPPORTED_OFST 2018148#define MC_CMD_GET_CAPABILITIES_V10_OUT_INIT_EVQ_TYPE_SUPPORTED_LBN 718149#define MC_CMD_GET_CAPABILITIES_V10_OUT_INIT_EVQ_TYPE_SUPPORTED_WIDTH 118150#define MC_CMD_GET_CAPABILITIES_V10_OUT_INIT_EVQ_V2_OFST 2018151#define MC_CMD_GET_CAPABILITIES_V10_OUT_INIT_EVQ_V2_LBN 718152#define MC_CMD_GET_CAPABILITIES_V10_OUT_INIT_EVQ_V2_WIDTH 118153#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_MAC_TIMESTAMPING_OFST 2018154#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_MAC_TIMESTAMPING_LBN 818155#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_MAC_TIMESTAMPING_WIDTH 118156#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_TIMESTAMP_OFST 2018157#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_TIMESTAMP_LBN 918158#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_TIMESTAMP_WIDTH 118159#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_SNIFF_OFST 2018160#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_SNIFF_LBN 1018161#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_SNIFF_WIDTH 118162#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_SNIFF_OFST 2018163#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_SNIFF_LBN 1118164#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_SNIFF_WIDTH 118165#define MC_CMD_GET_CAPABILITIES_V10_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_OFST 2018166#define MC_CMD_GET_CAPABILITIES_V10_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_LBN 1218167#define MC_CMD_GET_CAPABILITIES_V10_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 118168#define MC_CMD_GET_CAPABILITIES_V10_OUT_MCDI_BACKGROUND_OFST 2018169#define MC_CMD_GET_CAPABILITIES_V10_OUT_MCDI_BACKGROUND_LBN 1318170#define MC_CMD_GET_CAPABILITIES_V10_OUT_MCDI_BACKGROUND_WIDTH 118171#define MC_CMD_GET_CAPABILITIES_V10_OUT_MCDI_DB_RETURN_OFST 2018172#define MC_CMD_GET_CAPABILITIES_V10_OUT_MCDI_DB_RETURN_LBN 1418173#define MC_CMD_GET_CAPABILITIES_V10_OUT_MCDI_DB_RETURN_WIDTH 118174#define MC_CMD_GET_CAPABILITIES_V10_OUT_CTPIO_OFST 2018175#define MC_CMD_GET_CAPABILITIES_V10_OUT_CTPIO_LBN 1518176#define MC_CMD_GET_CAPABILITIES_V10_OUT_CTPIO_WIDTH 118177#define MC_CMD_GET_CAPABILITIES_V10_OUT_TSA_SUPPORT_OFST 2018178#define MC_CMD_GET_CAPABILITIES_V10_OUT_TSA_SUPPORT_LBN 1618179#define MC_CMD_GET_CAPABILITIES_V10_OUT_TSA_SUPPORT_WIDTH 118180#define MC_CMD_GET_CAPABILITIES_V10_OUT_TSA_BOUND_OFST 2018181#define MC_CMD_GET_CAPABILITIES_V10_OUT_TSA_BOUND_LBN 1718182#define MC_CMD_GET_CAPABILITIES_V10_OUT_TSA_BOUND_WIDTH 118183#define MC_CMD_GET_CAPABILITIES_V10_OUT_SF_ADAPTER_AUTHENTICATION_OFST 2018184#define MC_CMD_GET_CAPABILITIES_V10_OUT_SF_ADAPTER_AUTHENTICATION_LBN 1818185#define MC_CMD_GET_CAPABILITIES_V10_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 118186#define MC_CMD_GET_CAPABILITIES_V10_OUT_FILTER_ACTION_FLAG_OFST 2018187#define MC_CMD_GET_CAPABILITIES_V10_OUT_FILTER_ACTION_FLAG_LBN 1918188#define MC_CMD_GET_CAPABILITIES_V10_OUT_FILTER_ACTION_FLAG_WIDTH 118189#define MC_CMD_GET_CAPABILITIES_V10_OUT_FILTER_ACTION_MARK_OFST 2018190#define MC_CMD_GET_CAPABILITIES_V10_OUT_FILTER_ACTION_MARK_LBN 2018191#define MC_CMD_GET_CAPABILITIES_V10_OUT_FILTER_ACTION_MARK_WIDTH 118192#define MC_CMD_GET_CAPABILITIES_V10_OUT_EQUAL_STRIDE_SUPER_BUFFER_OFST 2018193#define MC_CMD_GET_CAPABILITIES_V10_OUT_EQUAL_STRIDE_SUPER_BUFFER_LBN 2118194#define MC_CMD_GET_CAPABILITIES_V10_OUT_EQUAL_STRIDE_SUPER_BUFFER_WIDTH 118195#define MC_CMD_GET_CAPABILITIES_V10_OUT_EQUAL_STRIDE_PACKED_STREAM_OFST 2018196#define MC_CMD_GET_CAPABILITIES_V10_OUT_EQUAL_STRIDE_PACKED_STREAM_LBN 2118197#define MC_CMD_GET_CAPABILITIES_V10_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 118198#define MC_CMD_GET_CAPABILITIES_V10_OUT_L3XUDP_SUPPORT_OFST 2018199#define MC_CMD_GET_CAPABILITIES_V10_OUT_L3XUDP_SUPPORT_LBN 2218200#define MC_CMD_GET_CAPABILITIES_V10_OUT_L3XUDP_SUPPORT_WIDTH 118201#define MC_CMD_GET_CAPABILITIES_V10_OUT_FW_SUBVARIANT_NO_TX_CSUM_OFST 2018202#define MC_CMD_GET_CAPABILITIES_V10_OUT_FW_SUBVARIANT_NO_TX_CSUM_LBN 2318203#define MC_CMD_GET_CAPABILITIES_V10_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 118204#define MC_CMD_GET_CAPABILITIES_V10_OUT_VI_SPREADING_OFST 2018205#define MC_CMD_GET_CAPABILITIES_V10_OUT_VI_SPREADING_LBN 2418206#define MC_CMD_GET_CAPABILITIES_V10_OUT_VI_SPREADING_WIDTH 118207#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_HLB_IDLE_OFST 2018208#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_HLB_IDLE_LBN 2518209#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_HLB_IDLE_WIDTH 118210#define MC_CMD_GET_CAPABILITIES_V10_OUT_INIT_RXQ_NO_CONT_EV_OFST 2018211#define MC_CMD_GET_CAPABILITIES_V10_OUT_INIT_RXQ_NO_CONT_EV_LBN 2618212#define MC_CMD_GET_CAPABILITIES_V10_OUT_INIT_RXQ_NO_CONT_EV_WIDTH 118213#define MC_CMD_GET_CAPABILITIES_V10_OUT_INIT_RXQ_WITH_BUFFER_SIZE_OFST 2018214#define MC_CMD_GET_CAPABILITIES_V10_OUT_INIT_RXQ_WITH_BUFFER_SIZE_LBN 2718215#define MC_CMD_GET_CAPABILITIES_V10_OUT_INIT_RXQ_WITH_BUFFER_SIZE_WIDTH 118216#define MC_CMD_GET_CAPABILITIES_V10_OUT_BUNDLE_UPDATE_OFST 2018217#define MC_CMD_GET_CAPABILITIES_V10_OUT_BUNDLE_UPDATE_LBN 2818218#define MC_CMD_GET_CAPABILITIES_V10_OUT_BUNDLE_UPDATE_WIDTH 118219#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_TSO_V3_OFST 2018220#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_TSO_V3_LBN 2918221#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_TSO_V3_WIDTH 118222#define MC_CMD_GET_CAPABILITIES_V10_OUT_DYNAMIC_SENSORS_OFST 2018223#define MC_CMD_GET_CAPABILITIES_V10_OUT_DYNAMIC_SENSORS_LBN 3018224#define MC_CMD_GET_CAPABILITIES_V10_OUT_DYNAMIC_SENSORS_WIDTH 118225#define MC_CMD_GET_CAPABILITIES_V10_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_OFST 2018226#define MC_CMD_GET_CAPABILITIES_V10_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_LBN 3118227#define MC_CMD_GET_CAPABILITIES_V10_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_WIDTH 118228/* Number of FATSOv2 contexts per datapath supported by this NIC (when18229 * TX_TSO_V2 == 1). Not present on older firmware (check the length).18230 */18231#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_TSO_V2_N_CONTEXTS_OFST 2418232#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_TSO_V2_N_CONTEXTS_LEN 218233/* One byte per PF containing the number of the external port assigned to this18234 * PF, indexed by PF number. Special values indicate that a PF is either not18235 * present or not assigned.18236 */18237#define MC_CMD_GET_CAPABILITIES_V10_OUT_PFS_TO_PORTS_ASSIGNMENT_OFST 2618238#define MC_CMD_GET_CAPABILITIES_V10_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 118239#define MC_CMD_GET_CAPABILITIES_V10_OUT_PFS_TO_PORTS_ASSIGNMENT_NUM 1618240/* enum: The caller is not permitted to access information on this PF. */18241#define MC_CMD_GET_CAPABILITIES_V10_OUT_ACCESS_NOT_PERMITTED 0xff18242/* enum: PF does not exist. */18243#define MC_CMD_GET_CAPABILITIES_V10_OUT_PF_NOT_PRESENT 0xfe18244/* enum: PF does exist but is not assigned to any external port. */18245#define MC_CMD_GET_CAPABILITIES_V10_OUT_PF_NOT_ASSIGNED 0xfd18246/* enum: This value indicates that PF is assigned, but it cannot be expressed18247 * in this field. It is intended for a possible future situation where a more18248 * complex scheme of PFs to ports mapping is being used. The future driver18249 * should look for a new field supporting the new scheme. The current/old18250 * driver should treat this value as PF_NOT_ASSIGNED.18251 */18252#define MC_CMD_GET_CAPABILITIES_V10_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc18253/* One byte per PF containing the number of its VFs, indexed by PF number. A18254 * special value indicates that a PF is not present.18255 */18256#define MC_CMD_GET_CAPABILITIES_V10_OUT_NUM_VFS_PER_PF_OFST 4218257#define MC_CMD_GET_CAPABILITIES_V10_OUT_NUM_VFS_PER_PF_LEN 118258#define MC_CMD_GET_CAPABILITIES_V10_OUT_NUM_VFS_PER_PF_NUM 1618259/* enum: The caller is not permitted to access information on this PF. */18260/* MC_CMD_GET_CAPABILITIES_V10_OUT_ACCESS_NOT_PERMITTED 0xff */18261/* enum: PF does not exist. */18262/* MC_CMD_GET_CAPABILITIES_V10_OUT_PF_NOT_PRESENT 0xfe */18263/* Number of VIs available for each external port */18264#define MC_CMD_GET_CAPABILITIES_V10_OUT_NUM_VIS_PER_PORT_OFST 5818265#define MC_CMD_GET_CAPABILITIES_V10_OUT_NUM_VIS_PER_PORT_LEN 218266#define MC_CMD_GET_CAPABILITIES_V10_OUT_NUM_VIS_PER_PORT_NUM 418267/* Size of RX descriptor cache expressed as binary logarithm The actual size18268 * equals (2 ^ RX_DESC_CACHE_SIZE)18269 */18270#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_DESC_CACHE_SIZE_OFST 6618271#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_DESC_CACHE_SIZE_LEN 118272/* Size of TX descriptor cache expressed as binary logarithm The actual size18273 * equals (2 ^ TX_DESC_CACHE_SIZE)18274 */18275#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_DESC_CACHE_SIZE_OFST 6718276#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_DESC_CACHE_SIZE_LEN 118277/* Total number of available PIO buffers */18278#define MC_CMD_GET_CAPABILITIES_V10_OUT_NUM_PIO_BUFFS_OFST 6818279#define MC_CMD_GET_CAPABILITIES_V10_OUT_NUM_PIO_BUFFS_LEN 218280/* Size of a single PIO buffer */18281#define MC_CMD_GET_CAPABILITIES_V10_OUT_SIZE_PIO_BUFF_OFST 7018282#define MC_CMD_GET_CAPABILITIES_V10_OUT_SIZE_PIO_BUFF_LEN 218283/* On chips later than Medford the amount of address space assigned to each VI18284 * is configurable. This is a global setting that the driver must query to18285 * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available18286 * with 8k VI windows.18287 */18288#define MC_CMD_GET_CAPABILITIES_V10_OUT_VI_WINDOW_MODE_OFST 7218289#define MC_CMD_GET_CAPABILITIES_V10_OUT_VI_WINDOW_MODE_LEN 118290/* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k.18291 * CTPIO is not mapped.18292 */18293#define MC_CMD_GET_CAPABILITIES_V10_OUT_VI_WINDOW_MODE_8K 0x018294/* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */18295#define MC_CMD_GET_CAPABILITIES_V10_OUT_VI_WINDOW_MODE_16K 0x118296/* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */18297#define MC_CMD_GET_CAPABILITIES_V10_OUT_VI_WINDOW_MODE_64K 0x218298/* Number of vFIFOs per adapter that can be used for VFIFO Stuffing18299 * (SF-115995-SW) in the present configuration of firmware and port mode.18300 */18301#define MC_CMD_GET_CAPABILITIES_V10_OUT_VFIFO_STUFFING_NUM_VFIFOS_OFST 7318302#define MC_CMD_GET_CAPABILITIES_V10_OUT_VFIFO_STUFFING_NUM_VFIFOS_LEN 118303/* Number of buffers per adapter that can be used for VFIFO Stuffing18304 * (SF-115995-SW) in the present configuration of firmware and port mode.18305 */18306#define MC_CMD_GET_CAPABILITIES_V10_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_OFST 7418307#define MC_CMD_GET_CAPABILITIES_V10_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_LEN 218308/* Entry count in the MAC stats array, including the final GENERATION_END18309 * entry. For MAC stats DMA, drivers should allocate a buffer large enough to18310 * hold at least this many 64-bit stats values, if they wish to receive all18311 * available stats. If the buffer is shorter than MAC_STATS_NUM_STATS * 8, the18312 * stats array returned will be truncated.18313 */18314#define MC_CMD_GET_CAPABILITIES_V10_OUT_MAC_STATS_NUM_STATS_OFST 7618315#define MC_CMD_GET_CAPABILITIES_V10_OUT_MAC_STATS_NUM_STATS_LEN 218316/* Maximum supported value for MC_CMD_FILTER_OP_V3/MATCH_MARK_VALUE. This field18317 * will only be non-zero if MC_CMD_GET_CAPABILITIES/FILTER_ACTION_MARK is set.18318 */18319#define MC_CMD_GET_CAPABILITIES_V10_OUT_FILTER_ACTION_MARK_MAX_OFST 8018320#define MC_CMD_GET_CAPABILITIES_V10_OUT_FILTER_ACTION_MARK_MAX_LEN 418321/* On devices where the INIT_RXQ_WITH_BUFFER_SIZE flag (in18322 * GET_CAPABILITIES_OUT_V2) is set, drivers have to specify a buffer size when18323 * they create an RX queue. Due to hardware limitations, only a small number of18324 * different buffer sizes may be available concurrently. Nonzero entries in18325 * this array are the sizes of buffers which the system guarantees will be18326 * available for use. If the list is empty, there are no limitations on18327 * concurrent buffer sizes.18328 */18329#define MC_CMD_GET_CAPABILITIES_V10_OUT_GUARANTEED_RX_BUFFER_SIZES_OFST 8418330#define MC_CMD_GET_CAPABILITIES_V10_OUT_GUARANTEED_RX_BUFFER_SIZES_LEN 418331#define MC_CMD_GET_CAPABILITIES_V10_OUT_GUARANTEED_RX_BUFFER_SIZES_NUM 1618332/* Third word of flags. Not present on older firmware (check the length). */18333#define MC_CMD_GET_CAPABILITIES_V10_OUT_FLAGS3_OFST 14818334#define MC_CMD_GET_CAPABILITIES_V10_OUT_FLAGS3_LEN 418335#define MC_CMD_GET_CAPABILITIES_V10_OUT_WOL_ETHERWAKE_OFST 14818336#define MC_CMD_GET_CAPABILITIES_V10_OUT_WOL_ETHERWAKE_LBN 018337#define MC_CMD_GET_CAPABILITIES_V10_OUT_WOL_ETHERWAKE_WIDTH 118338#define MC_CMD_GET_CAPABILITIES_V10_OUT_RSS_EVEN_SPREADING_OFST 14818339#define MC_CMD_GET_CAPABILITIES_V10_OUT_RSS_EVEN_SPREADING_LBN 118340#define MC_CMD_GET_CAPABILITIES_V10_OUT_RSS_EVEN_SPREADING_WIDTH 118341#define MC_CMD_GET_CAPABILITIES_V10_OUT_RSS_SELECTABLE_TABLE_SIZE_OFST 14818342#define MC_CMD_GET_CAPABILITIES_V10_OUT_RSS_SELECTABLE_TABLE_SIZE_LBN 218343#define MC_CMD_GET_CAPABILITIES_V10_OUT_RSS_SELECTABLE_TABLE_SIZE_WIDTH 118344#define MC_CMD_GET_CAPABILITIES_V10_OUT_MAE_SUPPORTED_OFST 14818345#define MC_CMD_GET_CAPABILITIES_V10_OUT_MAE_SUPPORTED_LBN 318346#define MC_CMD_GET_CAPABILITIES_V10_OUT_MAE_SUPPORTED_WIDTH 118347#define MC_CMD_GET_CAPABILITIES_V10_OUT_VDPA_SUPPORTED_OFST 14818348#define MC_CMD_GET_CAPABILITIES_V10_OUT_VDPA_SUPPORTED_LBN 418349#define MC_CMD_GET_CAPABILITIES_V10_OUT_VDPA_SUPPORTED_WIDTH 118350#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_OFST 14818351#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_LBN 518352#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_WIDTH 118353#define MC_CMD_GET_CAPABILITIES_V10_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_OFST 14818354#define MC_CMD_GET_CAPABILITIES_V10_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_LBN 618355#define MC_CMD_GET_CAPABILITIES_V10_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_WIDTH 118356#define MC_CMD_GET_CAPABILITIES_V10_OUT_UNSOL_EV_CREDIT_SUPPORTED_OFST 14818357#define MC_CMD_GET_CAPABILITIES_V10_OUT_UNSOL_EV_CREDIT_SUPPORTED_LBN 718358#define MC_CMD_GET_CAPABILITIES_V10_OUT_UNSOL_EV_CREDIT_SUPPORTED_WIDTH 118359#define MC_CMD_GET_CAPABILITIES_V10_OUT_ENCAPSULATED_MCDI_SUPPORTED_OFST 14818360#define MC_CMD_GET_CAPABILITIES_V10_OUT_ENCAPSULATED_MCDI_SUPPORTED_LBN 818361#define MC_CMD_GET_CAPABILITIES_V10_OUT_ENCAPSULATED_MCDI_SUPPORTED_WIDTH 118362#define MC_CMD_GET_CAPABILITIES_V10_OUT_EXTERNAL_MAE_SUPPORTED_OFST 14818363#define MC_CMD_GET_CAPABILITIES_V10_OUT_EXTERNAL_MAE_SUPPORTED_LBN 918364#define MC_CMD_GET_CAPABILITIES_V10_OUT_EXTERNAL_MAE_SUPPORTED_WIDTH 118365#define MC_CMD_GET_CAPABILITIES_V10_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_OFST 14818366#define MC_CMD_GET_CAPABILITIES_V10_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_LBN 1018367#define MC_CMD_GET_CAPABILITIES_V10_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_WIDTH 118368#define MC_CMD_GET_CAPABILITIES_V10_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_OFST 14818369#define MC_CMD_GET_CAPABILITIES_V10_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_LBN 1118370#define MC_CMD_GET_CAPABILITIES_V10_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_WIDTH 118371#define MC_CMD_GET_CAPABILITIES_V10_OUT_RSS_STEER_ON_OUTER_SUPPORTED_OFST 14818372#define MC_CMD_GET_CAPABILITIES_V10_OUT_RSS_STEER_ON_OUTER_SUPPORTED_LBN 1218373#define MC_CMD_GET_CAPABILITIES_V10_OUT_RSS_STEER_ON_OUTER_SUPPORTED_WIDTH 118374#define MC_CMD_GET_CAPABILITIES_V10_OUT_DYNAMIC_MPORT_JOURNAL_OFST 14818375#define MC_CMD_GET_CAPABILITIES_V10_OUT_DYNAMIC_MPORT_JOURNAL_LBN 1418376#define MC_CMD_GET_CAPABILITIES_V10_OUT_DYNAMIC_MPORT_JOURNAL_WIDTH 118377/* These bits are reserved for communicating test-specific capabilities to18378 * host-side test software. All production drivers should treat this field as18379 * opaque.18380 */18381#define MC_CMD_GET_CAPABILITIES_V10_OUT_TEST_RESERVED_OFST 15218382#define MC_CMD_GET_CAPABILITIES_V10_OUT_TEST_RESERVED_LEN 818383#define MC_CMD_GET_CAPABILITIES_V10_OUT_TEST_RESERVED_LO_OFST 15218384#define MC_CMD_GET_CAPABILITIES_V10_OUT_TEST_RESERVED_LO_LEN 418385#define MC_CMD_GET_CAPABILITIES_V10_OUT_TEST_RESERVED_LO_LBN 121618386#define MC_CMD_GET_CAPABILITIES_V10_OUT_TEST_RESERVED_LO_WIDTH 3218387#define MC_CMD_GET_CAPABILITIES_V10_OUT_TEST_RESERVED_HI_OFST 15618388#define MC_CMD_GET_CAPABILITIES_V10_OUT_TEST_RESERVED_HI_LEN 418389#define MC_CMD_GET_CAPABILITIES_V10_OUT_TEST_RESERVED_HI_LBN 124818390#define MC_CMD_GET_CAPABILITIES_V10_OUT_TEST_RESERVED_HI_WIDTH 3218391/* The minimum size (in table entries) of indirection table to be allocated18392 * from the pool for an RSS context. Note that the table size used must be a18393 * power of 2.18394 */18395#define MC_CMD_GET_CAPABILITIES_V10_OUT_RSS_MIN_INDIRECTION_TABLE_SIZE_OFST 16018396#define MC_CMD_GET_CAPABILITIES_V10_OUT_RSS_MIN_INDIRECTION_TABLE_SIZE_LEN 418397/* The maximum size (in table entries) of indirection table to be allocated18398 * from the pool for an RSS context. Note that the table size used must be a18399 * power of 2.18400 */18401#define MC_CMD_GET_CAPABILITIES_V10_OUT_RSS_MAX_INDIRECTION_TABLE_SIZE_OFST 16418402#define MC_CMD_GET_CAPABILITIES_V10_OUT_RSS_MAX_INDIRECTION_TABLE_SIZE_LEN 418403/* The maximum number of queues that can be used by an RSS context in exclusive18404 * mode. In exclusive mode the context has a configurable indirection table and18405 * a configurable RSS key.18406 */18407#define MC_CMD_GET_CAPABILITIES_V10_OUT_RSS_MAX_INDIRECTION_QUEUES_OFST 16818408#define MC_CMD_GET_CAPABILITIES_V10_OUT_RSS_MAX_INDIRECTION_QUEUES_LEN 418409/* The maximum number of queues that can be used by an RSS context in even-18410 * spreading mode. In even-spreading mode the context has no indirection table18411 * but it does have a configurable RSS key.18412 */18413#define MC_CMD_GET_CAPABILITIES_V10_OUT_RSS_MAX_EVEN_SPREADING_QUEUES_OFST 17218414#define MC_CMD_GET_CAPABILITIES_V10_OUT_RSS_MAX_EVEN_SPREADING_QUEUES_LEN 418415/* The total number of RSS contexts supported. Note that the number of18416 * available contexts using indirection tables is also limited by the18417 * availability of indirection table space allocated from a common pool.18418 */18419#define MC_CMD_GET_CAPABILITIES_V10_OUT_RSS_NUM_CONTEXTS_OFST 17618420#define MC_CMD_GET_CAPABILITIES_V10_OUT_RSS_NUM_CONTEXTS_LEN 418421/* The total amount of indirection table space that can be shared between RSS18422 * contexts.18423 */18424#define MC_CMD_GET_CAPABILITIES_V10_OUT_RSS_TABLE_POOL_SIZE_OFST 18018425#define MC_CMD_GET_CAPABILITIES_V10_OUT_RSS_TABLE_POOL_SIZE_LEN 418426/* A bitmap of the queue sizes the device can provide, where bit N being set18427 * indicates that 2**N is a valid size. The device may be limited in the number18428 * of different queue sizes that can exist simultaneously, so a bit being set18429 * here does not guarantee that an attempt to create a queue of that size will18430 * succeed.18431 */18432#define MC_CMD_GET_CAPABILITIES_V10_OUT_SUPPORTED_QUEUE_SIZES_OFST 18418433#define MC_CMD_GET_CAPABILITIES_V10_OUT_SUPPORTED_QUEUE_SIZES_LEN 418434/* A bitmap of queue sizes that are always available, in the same format as18435 * SUPPORTED_QUEUE_SIZES. Attempting to create a queue with one of these sizes18436 * will never fail due to unavailability of the requested size.18437 */18438#define MC_CMD_GET_CAPABILITIES_V10_OUT_GUARANTEED_QUEUE_SIZES_OFST 18818439#define MC_CMD_GET_CAPABILITIES_V10_OUT_GUARANTEED_QUEUE_SIZES_LEN 418440 18441 18442/***********************************/18443/* MC_CMD_V2_EXTN18444 * Encapsulation for a v2 extended command18445 */18446#define MC_CMD_V2_EXTN 0x7f18447 18448/* MC_CMD_V2_EXTN_IN msgrequest */18449#define MC_CMD_V2_EXTN_IN_LEN 418450/* the extended command number */18451#define MC_CMD_V2_EXTN_IN_EXTENDED_CMD_LBN 018452#define MC_CMD_V2_EXTN_IN_EXTENDED_CMD_WIDTH 1518453#define MC_CMD_V2_EXTN_IN_UNUSED_LBN 1518454#define MC_CMD_V2_EXTN_IN_UNUSED_WIDTH 118455/* the actual length of the encapsulated command (which is not in the v118456 * header)18457 */18458#define MC_CMD_V2_EXTN_IN_ACTUAL_LEN_LBN 1618459#define MC_CMD_V2_EXTN_IN_ACTUAL_LEN_WIDTH 1018460#define MC_CMD_V2_EXTN_IN_UNUSED2_LBN 2618461#define MC_CMD_V2_EXTN_IN_UNUSED2_WIDTH 218462/* Type of command/response */18463#define MC_CMD_V2_EXTN_IN_MESSAGE_TYPE_LBN 2818464#define MC_CMD_V2_EXTN_IN_MESSAGE_TYPE_WIDTH 418465/* enum: MCDI command directed to or response originating from the MC. */18466#define MC_CMD_V2_EXTN_IN_MCDI_MESSAGE_TYPE_MC 0x018467/* enum: MCDI command directed to a TSA controller. MCDI responses of this type18468 * are not defined.18469 */18470#define MC_CMD_V2_EXTN_IN_MCDI_MESSAGE_TYPE_TSA 0x118471 18472 18473/***********************************/18474/* MC_CMD_TCM_BUCKET_ALLOC18475 * Allocate a pacer bucket (for qau rp or a snapper test)18476 */18477#define MC_CMD_TCM_BUCKET_ALLOC 0xb218478#undef MC_CMD_0xb2_PRIVILEGE_CTG18479 18480#define MC_CMD_0xb2_PRIVILEGE_CTG SRIOV_CTG_GENERAL18481 18482/* MC_CMD_TCM_BUCKET_ALLOC_IN msgrequest */18483#define MC_CMD_TCM_BUCKET_ALLOC_IN_LEN 018484 18485/* MC_CMD_TCM_BUCKET_ALLOC_OUT msgresponse */18486#define MC_CMD_TCM_BUCKET_ALLOC_OUT_LEN 418487/* the bucket id */18488#define MC_CMD_TCM_BUCKET_ALLOC_OUT_BUCKET_OFST 018489#define MC_CMD_TCM_BUCKET_ALLOC_OUT_BUCKET_LEN 418490 18491 18492/***********************************/18493/* MC_CMD_TCM_BUCKET_FREE18494 * Free a pacer bucket18495 */18496#define MC_CMD_TCM_BUCKET_FREE 0xb318497#undef MC_CMD_0xb3_PRIVILEGE_CTG18498 18499#define MC_CMD_0xb3_PRIVILEGE_CTG SRIOV_CTG_GENERAL18500 18501/* MC_CMD_TCM_BUCKET_FREE_IN msgrequest */18502#define MC_CMD_TCM_BUCKET_FREE_IN_LEN 418503/* the bucket id */18504#define MC_CMD_TCM_BUCKET_FREE_IN_BUCKET_OFST 018505#define MC_CMD_TCM_BUCKET_FREE_IN_BUCKET_LEN 418506 18507/* MC_CMD_TCM_BUCKET_FREE_OUT msgresponse */18508#define MC_CMD_TCM_BUCKET_FREE_OUT_LEN 018509 18510 18511/***********************************/18512/* MC_CMD_TCM_BUCKET_INIT18513 * Initialise pacer bucket with a given rate18514 */18515#define MC_CMD_TCM_BUCKET_INIT 0xb418516#undef MC_CMD_0xb4_PRIVILEGE_CTG18517 18518#define MC_CMD_0xb4_PRIVILEGE_CTG SRIOV_CTG_GENERAL18519 18520/* MC_CMD_TCM_BUCKET_INIT_IN msgrequest */18521#define MC_CMD_TCM_BUCKET_INIT_IN_LEN 818522/* the bucket id */18523#define MC_CMD_TCM_BUCKET_INIT_IN_BUCKET_OFST 018524#define MC_CMD_TCM_BUCKET_INIT_IN_BUCKET_LEN 418525/* the rate in mbps */18526#define MC_CMD_TCM_BUCKET_INIT_IN_RATE_OFST 418527#define MC_CMD_TCM_BUCKET_INIT_IN_RATE_LEN 418528 18529/* MC_CMD_TCM_BUCKET_INIT_EXT_IN msgrequest */18530#define MC_CMD_TCM_BUCKET_INIT_EXT_IN_LEN 1218531/* the bucket id */18532#define MC_CMD_TCM_BUCKET_INIT_EXT_IN_BUCKET_OFST 018533#define MC_CMD_TCM_BUCKET_INIT_EXT_IN_BUCKET_LEN 418534/* the rate in mbps */18535#define MC_CMD_TCM_BUCKET_INIT_EXT_IN_RATE_OFST 418536#define MC_CMD_TCM_BUCKET_INIT_EXT_IN_RATE_LEN 418537/* the desired maximum fill level */18538#define MC_CMD_TCM_BUCKET_INIT_EXT_IN_MAX_FILL_OFST 818539#define MC_CMD_TCM_BUCKET_INIT_EXT_IN_MAX_FILL_LEN 418540 18541/* MC_CMD_TCM_BUCKET_INIT_OUT msgresponse */18542#define MC_CMD_TCM_BUCKET_INIT_OUT_LEN 018543 18544 18545/***********************************/18546/* MC_CMD_TCM_TXQ_INIT18547 * Initialise txq in pacer with given options or set options18548 */18549#define MC_CMD_TCM_TXQ_INIT 0xb518550#undef MC_CMD_0xb5_PRIVILEGE_CTG18551 18552#define MC_CMD_0xb5_PRIVILEGE_CTG SRIOV_CTG_GENERAL18553 18554/* MC_CMD_TCM_TXQ_INIT_IN msgrequest */18555#define MC_CMD_TCM_TXQ_INIT_IN_LEN 2818556/* the txq id */18557#define MC_CMD_TCM_TXQ_INIT_IN_QID_OFST 018558#define MC_CMD_TCM_TXQ_INIT_IN_QID_LEN 418559/* the static priority associated with the txq */18560#define MC_CMD_TCM_TXQ_INIT_IN_LABEL_OFST 418561#define MC_CMD_TCM_TXQ_INIT_IN_LABEL_LEN 418562/* bitmask of the priority queues this txq is inserted into when inserted. */18563#define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAGS_OFST 818564#define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAGS_LEN 418565#define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_GUARANTEED_OFST 818566#define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_GUARANTEED_LBN 018567#define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_GUARANTEED_WIDTH 118568#define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_NORMAL_OFST 818569#define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_NORMAL_LBN 118570#define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_NORMAL_WIDTH 118571#define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_LOW_OFST 818572#define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_LOW_LBN 218573#define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_LOW_WIDTH 118574/* the reaction point (RP) bucket */18575#define MC_CMD_TCM_TXQ_INIT_IN_RP_BKT_OFST 1218576#define MC_CMD_TCM_TXQ_INIT_IN_RP_BKT_LEN 418577/* an already reserved bucket (typically set to bucket associated with outer18578 * vswitch)18579 */18580#define MC_CMD_TCM_TXQ_INIT_IN_MAX_BKT1_OFST 1618581#define MC_CMD_TCM_TXQ_INIT_IN_MAX_BKT1_LEN 418582/* an already reserved bucket (typically set to bucket associated with inner18583 * vswitch)18584 */18585#define MC_CMD_TCM_TXQ_INIT_IN_MAX_BKT2_OFST 2018586#define MC_CMD_TCM_TXQ_INIT_IN_MAX_BKT2_LEN 418587/* the min bucket (typically for ETS/minimum bandwidth) */18588#define MC_CMD_TCM_TXQ_INIT_IN_MIN_BKT_OFST 2418589#define MC_CMD_TCM_TXQ_INIT_IN_MIN_BKT_LEN 418590 18591/* MC_CMD_TCM_TXQ_INIT_EXT_IN msgrequest */18592#define MC_CMD_TCM_TXQ_INIT_EXT_IN_LEN 3218593/* the txq id */18594#define MC_CMD_TCM_TXQ_INIT_EXT_IN_QID_OFST 018595#define MC_CMD_TCM_TXQ_INIT_EXT_IN_QID_LEN 418596/* the static priority associated with the txq */18597#define MC_CMD_TCM_TXQ_INIT_EXT_IN_LABEL_NORMAL_OFST 418598#define MC_CMD_TCM_TXQ_INIT_EXT_IN_LABEL_NORMAL_LEN 418599/* bitmask of the priority queues this txq is inserted into when inserted. */18600#define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAGS_OFST 818601#define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAGS_LEN 418602#define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_GUARANTEED_OFST 818603#define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_GUARANTEED_LBN 018604#define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_GUARANTEED_WIDTH 118605#define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_NORMAL_OFST 818606#define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_NORMAL_LBN 118607#define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_NORMAL_WIDTH 118608#define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_LOW_OFST 818609#define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_LOW_LBN 218610#define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_LOW_WIDTH 118611/* the reaction point (RP) bucket */18612#define MC_CMD_TCM_TXQ_INIT_EXT_IN_RP_BKT_OFST 1218613#define MC_CMD_TCM_TXQ_INIT_EXT_IN_RP_BKT_LEN 418614/* an already reserved bucket (typically set to bucket associated with outer18615 * vswitch)18616 */18617#define MC_CMD_TCM_TXQ_INIT_EXT_IN_MAX_BKT1_OFST 1618618#define MC_CMD_TCM_TXQ_INIT_EXT_IN_MAX_BKT1_LEN 418619/* an already reserved bucket (typically set to bucket associated with inner18620 * vswitch)18621 */18622#define MC_CMD_TCM_TXQ_INIT_EXT_IN_MAX_BKT2_OFST 2018623#define MC_CMD_TCM_TXQ_INIT_EXT_IN_MAX_BKT2_LEN 418624/* the min bucket (typically for ETS/minimum bandwidth) */18625#define MC_CMD_TCM_TXQ_INIT_EXT_IN_MIN_BKT_OFST 2418626#define MC_CMD_TCM_TXQ_INIT_EXT_IN_MIN_BKT_LEN 418627/* the static priority associated with the txq */18628#define MC_CMD_TCM_TXQ_INIT_EXT_IN_LABEL_GUARANTEED_OFST 2818629#define MC_CMD_TCM_TXQ_INIT_EXT_IN_LABEL_GUARANTEED_LEN 418630 18631/* MC_CMD_TCM_TXQ_INIT_OUT msgresponse */18632#define MC_CMD_TCM_TXQ_INIT_OUT_LEN 018633 18634 18635/***********************************/18636/* MC_CMD_LINK_PIOBUF18637 * Link a push I/O buffer to a TxQ18638 */18639#define MC_CMD_LINK_PIOBUF 0x9218640#undef MC_CMD_0x92_PRIVILEGE_CTG18641 18642#define MC_CMD_0x92_PRIVILEGE_CTG SRIOV_CTG_ONLOAD18643 18644/* MC_CMD_LINK_PIOBUF_IN msgrequest */18645#define MC_CMD_LINK_PIOBUF_IN_LEN 818646/* Handle for allocated push I/O buffer. */18647#define MC_CMD_LINK_PIOBUF_IN_PIOBUF_HANDLE_OFST 018648#define MC_CMD_LINK_PIOBUF_IN_PIOBUF_HANDLE_LEN 418649/* Function Local Instance (VI) number which has a TxQ allocated to it. */18650#define MC_CMD_LINK_PIOBUF_IN_TXQ_INSTANCE_OFST 418651#define MC_CMD_LINK_PIOBUF_IN_TXQ_INSTANCE_LEN 418652 18653/* MC_CMD_LINK_PIOBUF_OUT msgresponse */18654#define MC_CMD_LINK_PIOBUF_OUT_LEN 018655 18656 18657/***********************************/18658/* MC_CMD_UNLINK_PIOBUF18659 * Unlink a push I/O buffer from a TxQ18660 */18661#define MC_CMD_UNLINK_PIOBUF 0x9318662#undef MC_CMD_0x93_PRIVILEGE_CTG18663 18664#define MC_CMD_0x93_PRIVILEGE_CTG SRIOV_CTG_ONLOAD18665 18666/* MC_CMD_UNLINK_PIOBUF_IN msgrequest */18667#define MC_CMD_UNLINK_PIOBUF_IN_LEN 418668/* Function Local Instance (VI) number. */18669#define MC_CMD_UNLINK_PIOBUF_IN_TXQ_INSTANCE_OFST 018670#define MC_CMD_UNLINK_PIOBUF_IN_TXQ_INSTANCE_LEN 418671 18672/* MC_CMD_UNLINK_PIOBUF_OUT msgresponse */18673#define MC_CMD_UNLINK_PIOBUF_OUT_LEN 018674 18675 18676/***********************************/18677/* MC_CMD_VSWITCH_ALLOC18678 * allocate and initialise a v-switch.18679 */18680#define MC_CMD_VSWITCH_ALLOC 0x9418681#undef MC_CMD_0x94_PRIVILEGE_CTG18682 18683#define MC_CMD_0x94_PRIVILEGE_CTG SRIOV_CTG_GENERAL18684 18685/* MC_CMD_VSWITCH_ALLOC_IN msgrequest */18686#define MC_CMD_VSWITCH_ALLOC_IN_LEN 1618687/* The port to connect to the v-switch's upstream port. */18688#define MC_CMD_VSWITCH_ALLOC_IN_UPSTREAM_PORT_ID_OFST 018689#define MC_CMD_VSWITCH_ALLOC_IN_UPSTREAM_PORT_ID_LEN 418690/* The type of v-switch to create. */18691#define MC_CMD_VSWITCH_ALLOC_IN_TYPE_OFST 418692#define MC_CMD_VSWITCH_ALLOC_IN_TYPE_LEN 418693/* enum: VLAN */18694#define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VLAN 0x118695/* enum: VEB */18696#define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VEB 0x218697/* enum: VEPA (obsolete) */18698#define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VEPA 0x318699/* enum: MUX */18700#define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_MUX 0x418701/* enum: Snapper specific; semantics TBD */18702#define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_TEST 0x518703/* Flags controlling v-port creation */18704#define MC_CMD_VSWITCH_ALLOC_IN_FLAGS_OFST 818705#define MC_CMD_VSWITCH_ALLOC_IN_FLAGS_LEN 418706#define MC_CMD_VSWITCH_ALLOC_IN_FLAG_AUTO_PORT_OFST 818707#define MC_CMD_VSWITCH_ALLOC_IN_FLAG_AUTO_PORT_LBN 018708#define MC_CMD_VSWITCH_ALLOC_IN_FLAG_AUTO_PORT_WIDTH 118709/* The number of VLAN tags to allow for attached v-ports. For VLAN aggregators,18710 * this must be one or greated, and the attached v-ports must have exactly this18711 * number of tags. For other v-switch types, this must be zero of greater, and18712 * is an upper limit on the number of VLAN tags for attached v-ports. An error18713 * will be returned if existing configuration means we can't support attached18714 * v-ports with this number of tags.18715 */18716#define MC_CMD_VSWITCH_ALLOC_IN_NUM_VLAN_TAGS_OFST 1218717#define MC_CMD_VSWITCH_ALLOC_IN_NUM_VLAN_TAGS_LEN 418718 18719/* MC_CMD_VSWITCH_ALLOC_OUT msgresponse */18720#define MC_CMD_VSWITCH_ALLOC_OUT_LEN 018721 18722 18723/***********************************/18724/* MC_CMD_VSWITCH_FREE18725 * de-allocate a v-switch.18726 */18727#define MC_CMD_VSWITCH_FREE 0x9518728#undef MC_CMD_0x95_PRIVILEGE_CTG18729 18730#define MC_CMD_0x95_PRIVILEGE_CTG SRIOV_CTG_GENERAL18731 18732/* MC_CMD_VSWITCH_FREE_IN msgrequest */18733#define MC_CMD_VSWITCH_FREE_IN_LEN 418734/* The port to which the v-switch is connected. */18735#define MC_CMD_VSWITCH_FREE_IN_UPSTREAM_PORT_ID_OFST 018736#define MC_CMD_VSWITCH_FREE_IN_UPSTREAM_PORT_ID_LEN 418737 18738/* MC_CMD_VSWITCH_FREE_OUT msgresponse */18739#define MC_CMD_VSWITCH_FREE_OUT_LEN 018740 18741 18742/***********************************/18743/* MC_CMD_VSWITCH_QUERY18744 * read some config of v-switch. For now this command is an empty placeholder.18745 * It may be used to check if a v-switch is connected to a given EVB port (if18746 * not, then the command returns ENOENT).18747 */18748#define MC_CMD_VSWITCH_QUERY 0x6318749#undef MC_CMD_0x63_PRIVILEGE_CTG18750 18751#define MC_CMD_0x63_PRIVILEGE_CTG SRIOV_CTG_GENERAL18752 18753/* MC_CMD_VSWITCH_QUERY_IN msgrequest */18754#define MC_CMD_VSWITCH_QUERY_IN_LEN 418755/* The port to which the v-switch is connected. */18756#define MC_CMD_VSWITCH_QUERY_IN_UPSTREAM_PORT_ID_OFST 018757#define MC_CMD_VSWITCH_QUERY_IN_UPSTREAM_PORT_ID_LEN 418758 18759/* MC_CMD_VSWITCH_QUERY_OUT msgresponse */18760#define MC_CMD_VSWITCH_QUERY_OUT_LEN 018761 18762 18763/***********************************/18764/* MC_CMD_VPORT_ALLOC18765 * allocate a v-port.18766 */18767#define MC_CMD_VPORT_ALLOC 0x9618768#undef MC_CMD_0x96_PRIVILEGE_CTG18769 18770#define MC_CMD_0x96_PRIVILEGE_CTG SRIOV_CTG_GENERAL18771 18772/* MC_CMD_VPORT_ALLOC_IN msgrequest */18773#define MC_CMD_VPORT_ALLOC_IN_LEN 2018774/* The port to which the v-switch is connected. */18775#define MC_CMD_VPORT_ALLOC_IN_UPSTREAM_PORT_ID_OFST 018776#define MC_CMD_VPORT_ALLOC_IN_UPSTREAM_PORT_ID_LEN 418777/* The type of the new v-port. */18778#define MC_CMD_VPORT_ALLOC_IN_TYPE_OFST 418779#define MC_CMD_VPORT_ALLOC_IN_TYPE_LEN 418780/* enum: VLAN (obsolete) */18781#define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VLAN 0x118782/* enum: VEB (obsolete) */18783#define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VEB 0x218784/* enum: VEPA (obsolete) */18785#define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VEPA 0x318786/* enum: A normal v-port receives packets which match a specified MAC and/or18787 * VLAN.18788 */18789#define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_NORMAL 0x418790/* enum: An expansion v-port packets traffic which don't match any other18791 * v-port.18792 */18793#define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_EXPANSION 0x518794/* enum: An test v-port receives packets which match any filters installed by18795 * its downstream components.18796 */18797#define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_TEST 0x618798/* Flags controlling v-port creation */18799#define MC_CMD_VPORT_ALLOC_IN_FLAGS_OFST 818800#define MC_CMD_VPORT_ALLOC_IN_FLAGS_LEN 418801#define MC_CMD_VPORT_ALLOC_IN_FLAG_AUTO_PORT_OFST 818802#define MC_CMD_VPORT_ALLOC_IN_FLAG_AUTO_PORT_LBN 018803#define MC_CMD_VPORT_ALLOC_IN_FLAG_AUTO_PORT_WIDTH 118804#define MC_CMD_VPORT_ALLOC_IN_FLAG_VLAN_RESTRICT_OFST 818805#define MC_CMD_VPORT_ALLOC_IN_FLAG_VLAN_RESTRICT_LBN 118806#define MC_CMD_VPORT_ALLOC_IN_FLAG_VLAN_RESTRICT_WIDTH 118807/* The number of VLAN tags to insert/remove. An error will be returned if18808 * incompatible with the number of VLAN tags specified for the upstream18809 * v-switch.18810 */18811#define MC_CMD_VPORT_ALLOC_IN_NUM_VLAN_TAGS_OFST 1218812#define MC_CMD_VPORT_ALLOC_IN_NUM_VLAN_TAGS_LEN 418813/* The actual VLAN tags to insert/remove */18814#define MC_CMD_VPORT_ALLOC_IN_VLAN_TAGS_OFST 1618815#define MC_CMD_VPORT_ALLOC_IN_VLAN_TAGS_LEN 418816#define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_0_OFST 1618817#define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_0_LBN 018818#define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_0_WIDTH 1618819#define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_1_OFST 1618820#define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_1_LBN 1618821#define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_1_WIDTH 1618822 18823/* MC_CMD_VPORT_ALLOC_OUT msgresponse */18824#define MC_CMD_VPORT_ALLOC_OUT_LEN 418825/* The handle of the new v-port */18826#define MC_CMD_VPORT_ALLOC_OUT_VPORT_ID_OFST 018827#define MC_CMD_VPORT_ALLOC_OUT_VPORT_ID_LEN 418828 18829 18830/***********************************/18831/* MC_CMD_VPORT_FREE18832 * de-allocate a v-port.18833 */18834#define MC_CMD_VPORT_FREE 0x9718835#undef MC_CMD_0x97_PRIVILEGE_CTG18836 18837#define MC_CMD_0x97_PRIVILEGE_CTG SRIOV_CTG_GENERAL18838 18839/* MC_CMD_VPORT_FREE_IN msgrequest */18840#define MC_CMD_VPORT_FREE_IN_LEN 418841/* The handle of the v-port */18842#define MC_CMD_VPORT_FREE_IN_VPORT_ID_OFST 018843#define MC_CMD_VPORT_FREE_IN_VPORT_ID_LEN 418844 18845/* MC_CMD_VPORT_FREE_OUT msgresponse */18846#define MC_CMD_VPORT_FREE_OUT_LEN 018847 18848 18849/***********************************/18850/* MC_CMD_VADAPTOR_ALLOC18851 * allocate a v-adaptor.18852 */18853#define MC_CMD_VADAPTOR_ALLOC 0x9818854#undef MC_CMD_0x98_PRIVILEGE_CTG18855 18856#define MC_CMD_0x98_PRIVILEGE_CTG SRIOV_CTG_GENERAL18857 18858/* MC_CMD_VADAPTOR_ALLOC_IN msgrequest */18859#define MC_CMD_VADAPTOR_ALLOC_IN_LEN 3018860/* The port to connect to the v-adaptor's port. */18861#define MC_CMD_VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID_OFST 018862#define MC_CMD_VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID_LEN 418863/* Flags controlling v-adaptor creation */18864#define MC_CMD_VADAPTOR_ALLOC_IN_FLAGS_OFST 818865#define MC_CMD_VADAPTOR_ALLOC_IN_FLAGS_LEN 418866#define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_AUTO_VADAPTOR_OFST 818867#define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_AUTO_VADAPTOR_LBN 018868#define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_AUTO_VADAPTOR_WIDTH 118869#define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 818870#define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 118871#define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 118872/* The number of VLAN tags to strip on receive */18873#define MC_CMD_VADAPTOR_ALLOC_IN_NUM_VLANS_OFST 1218874#define MC_CMD_VADAPTOR_ALLOC_IN_NUM_VLANS_LEN 418875/* The number of VLAN tags to transparently insert/remove. */18876#define MC_CMD_VADAPTOR_ALLOC_IN_NUM_VLAN_TAGS_OFST 1618877#define MC_CMD_VADAPTOR_ALLOC_IN_NUM_VLAN_TAGS_LEN 418878/* The actual VLAN tags to insert/remove */18879#define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAGS_OFST 2018880#define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAGS_LEN 418881#define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_0_OFST 2018882#define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_0_LBN 018883#define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_0_WIDTH 1618884#define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_1_OFST 2018885#define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_1_LBN 1618886#define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_1_WIDTH 1618887/* The MAC address to assign to this v-adaptor */18888#define MC_CMD_VADAPTOR_ALLOC_IN_MACADDR_OFST 2418889#define MC_CMD_VADAPTOR_ALLOC_IN_MACADDR_LEN 618890/* enum: Derive the MAC address from the upstream port */18891#define MC_CMD_VADAPTOR_ALLOC_IN_AUTO_MAC 0x018892 18893/* MC_CMD_VADAPTOR_ALLOC_OUT msgresponse */18894#define MC_CMD_VADAPTOR_ALLOC_OUT_LEN 018895 18896 18897/***********************************/18898/* MC_CMD_VADAPTOR_FREE18899 * de-allocate a v-adaptor.18900 */18901#define MC_CMD_VADAPTOR_FREE 0x9918902#undef MC_CMD_0x99_PRIVILEGE_CTG18903 18904#define MC_CMD_0x99_PRIVILEGE_CTG SRIOV_CTG_GENERAL18905 18906/* MC_CMD_VADAPTOR_FREE_IN msgrequest */18907#define MC_CMD_VADAPTOR_FREE_IN_LEN 418908/* The port to which the v-adaptor is connected. */18909#define MC_CMD_VADAPTOR_FREE_IN_UPSTREAM_PORT_ID_OFST 018910#define MC_CMD_VADAPTOR_FREE_IN_UPSTREAM_PORT_ID_LEN 418911 18912/* MC_CMD_VADAPTOR_FREE_OUT msgresponse */18913#define MC_CMD_VADAPTOR_FREE_OUT_LEN 018914 18915 18916/***********************************/18917/* MC_CMD_VADAPTOR_SET_MAC18918 * assign a new MAC address to a v-adaptor.18919 */18920#define MC_CMD_VADAPTOR_SET_MAC 0x5d18921#undef MC_CMD_0x5d_PRIVILEGE_CTG18922 18923#define MC_CMD_0x5d_PRIVILEGE_CTG SRIOV_CTG_GENERAL18924 18925/* MC_CMD_VADAPTOR_SET_MAC_IN msgrequest */18926#define MC_CMD_VADAPTOR_SET_MAC_IN_LEN 1018927/* The port to which the v-adaptor is connected. */18928#define MC_CMD_VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID_OFST 018929#define MC_CMD_VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID_LEN 418930/* The new MAC address to assign to this v-adaptor */18931#define MC_CMD_VADAPTOR_SET_MAC_IN_MACADDR_OFST 418932#define MC_CMD_VADAPTOR_SET_MAC_IN_MACADDR_LEN 618933 18934/* MC_CMD_VADAPTOR_SET_MAC_OUT msgresponse */18935#define MC_CMD_VADAPTOR_SET_MAC_OUT_LEN 018936 18937 18938/***********************************/18939/* MC_CMD_VADAPTOR_GET_MAC18940 * read the MAC address assigned to a v-adaptor.18941 */18942#define MC_CMD_VADAPTOR_GET_MAC 0x5e18943#undef MC_CMD_0x5e_PRIVILEGE_CTG18944 18945#define MC_CMD_0x5e_PRIVILEGE_CTG SRIOV_CTG_GENERAL18946 18947/* MC_CMD_VADAPTOR_GET_MAC_IN msgrequest */18948#define MC_CMD_VADAPTOR_GET_MAC_IN_LEN 418949/* The port to which the v-adaptor is connected. */18950#define MC_CMD_VADAPTOR_GET_MAC_IN_UPSTREAM_PORT_ID_OFST 018951#define MC_CMD_VADAPTOR_GET_MAC_IN_UPSTREAM_PORT_ID_LEN 418952 18953/* MC_CMD_VADAPTOR_GET_MAC_OUT msgresponse */18954#define MC_CMD_VADAPTOR_GET_MAC_OUT_LEN 618955/* The MAC address assigned to this v-adaptor */18956#define MC_CMD_VADAPTOR_GET_MAC_OUT_MACADDR_OFST 018957#define MC_CMD_VADAPTOR_GET_MAC_OUT_MACADDR_LEN 618958 18959 18960/***********************************/18961/* MC_CMD_VADAPTOR_QUERY18962 * read some config of v-adaptor.18963 */18964#define MC_CMD_VADAPTOR_QUERY 0x6118965#undef MC_CMD_0x61_PRIVILEGE_CTG18966 18967#define MC_CMD_0x61_PRIVILEGE_CTG SRIOV_CTG_GENERAL18968 18969/* MC_CMD_VADAPTOR_QUERY_IN msgrequest */18970#define MC_CMD_VADAPTOR_QUERY_IN_LEN 418971/* The port to which the v-adaptor is connected. */18972#define MC_CMD_VADAPTOR_QUERY_IN_UPSTREAM_PORT_ID_OFST 018973#define MC_CMD_VADAPTOR_QUERY_IN_UPSTREAM_PORT_ID_LEN 418974 18975/* MC_CMD_VADAPTOR_QUERY_OUT msgresponse */18976#define MC_CMD_VADAPTOR_QUERY_OUT_LEN 1218977/* The EVB port flags as defined at MC_CMD_VPORT_ALLOC. */18978#define MC_CMD_VADAPTOR_QUERY_OUT_PORT_FLAGS_OFST 018979#define MC_CMD_VADAPTOR_QUERY_OUT_PORT_FLAGS_LEN 418980/* The v-adaptor flags as defined at MC_CMD_VADAPTOR_ALLOC. */18981#define MC_CMD_VADAPTOR_QUERY_OUT_VADAPTOR_FLAGS_OFST 418982#define MC_CMD_VADAPTOR_QUERY_OUT_VADAPTOR_FLAGS_LEN 418983/* The number of VLAN tags that may still be added */18984#define MC_CMD_VADAPTOR_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS_OFST 818985#define MC_CMD_VADAPTOR_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS_LEN 418986 18987 18988/***********************************/18989/* MC_CMD_EVB_PORT_ASSIGN18990 * assign a port to a PCI function.18991 */18992#define MC_CMD_EVB_PORT_ASSIGN 0x9a18993#undef MC_CMD_0x9a_PRIVILEGE_CTG18994 18995#define MC_CMD_0x9a_PRIVILEGE_CTG SRIOV_CTG_GENERAL18996 18997/* MC_CMD_EVB_PORT_ASSIGN_IN msgrequest */18998#define MC_CMD_EVB_PORT_ASSIGN_IN_LEN 818999/* The port to assign. */19000#define MC_CMD_EVB_PORT_ASSIGN_IN_PORT_ID_OFST 019001#define MC_CMD_EVB_PORT_ASSIGN_IN_PORT_ID_LEN 419002/* The target function to modify. */19003#define MC_CMD_EVB_PORT_ASSIGN_IN_FUNCTION_OFST 419004#define MC_CMD_EVB_PORT_ASSIGN_IN_FUNCTION_LEN 419005#define MC_CMD_EVB_PORT_ASSIGN_IN_PF_OFST 419006#define MC_CMD_EVB_PORT_ASSIGN_IN_PF_LBN 019007#define MC_CMD_EVB_PORT_ASSIGN_IN_PF_WIDTH 1619008#define MC_CMD_EVB_PORT_ASSIGN_IN_VF_OFST 419009#define MC_CMD_EVB_PORT_ASSIGN_IN_VF_LBN 1619010#define MC_CMD_EVB_PORT_ASSIGN_IN_VF_WIDTH 1619011 19012/* MC_CMD_EVB_PORT_ASSIGN_OUT msgresponse */19013#define MC_CMD_EVB_PORT_ASSIGN_OUT_LEN 019014 19015 19016/***********************************/19017/* MC_CMD_RDWR_A64_REGIONS19018 * Assign the 64 bit region addresses.19019 */19020#define MC_CMD_RDWR_A64_REGIONS 0x9b19021#undef MC_CMD_0x9b_PRIVILEGE_CTG19022 19023#define MC_CMD_0x9b_PRIVILEGE_CTG SRIOV_CTG_ADMIN19024 19025/* MC_CMD_RDWR_A64_REGIONS_IN msgrequest */19026#define MC_CMD_RDWR_A64_REGIONS_IN_LEN 1719027#define MC_CMD_RDWR_A64_REGIONS_IN_REGION0_OFST 019028#define MC_CMD_RDWR_A64_REGIONS_IN_REGION0_LEN 419029#define MC_CMD_RDWR_A64_REGIONS_IN_REGION1_OFST 419030#define MC_CMD_RDWR_A64_REGIONS_IN_REGION1_LEN 419031#define MC_CMD_RDWR_A64_REGIONS_IN_REGION2_OFST 819032#define MC_CMD_RDWR_A64_REGIONS_IN_REGION2_LEN 419033#define MC_CMD_RDWR_A64_REGIONS_IN_REGION3_OFST 1219034#define MC_CMD_RDWR_A64_REGIONS_IN_REGION3_LEN 419035/* Write enable bits 0-3, set to write, clear to read. */19036#define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_LBN 12819037#define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_WIDTH 419038#define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_BYTE_OFST 1619039#define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_BYTE_LEN 119040 19041/* MC_CMD_RDWR_A64_REGIONS_OUT msgresponse: This data always included19042 * regardless of state of write bits in the request.19043 */19044#define MC_CMD_RDWR_A64_REGIONS_OUT_LEN 1619045#define MC_CMD_RDWR_A64_REGIONS_OUT_REGION0_OFST 019046#define MC_CMD_RDWR_A64_REGIONS_OUT_REGION0_LEN 419047#define MC_CMD_RDWR_A64_REGIONS_OUT_REGION1_OFST 419048#define MC_CMD_RDWR_A64_REGIONS_OUT_REGION1_LEN 419049#define MC_CMD_RDWR_A64_REGIONS_OUT_REGION2_OFST 819050#define MC_CMD_RDWR_A64_REGIONS_OUT_REGION2_LEN 419051#define MC_CMD_RDWR_A64_REGIONS_OUT_REGION3_OFST 1219052#define MC_CMD_RDWR_A64_REGIONS_OUT_REGION3_LEN 419053 19054 19055/***********************************/19056/* MC_CMD_ONLOAD_STACK_ALLOC19057 * Allocate an Onload stack ID.19058 */19059#define MC_CMD_ONLOAD_STACK_ALLOC 0x9c19060#undef MC_CMD_0x9c_PRIVILEGE_CTG19061 19062#define MC_CMD_0x9c_PRIVILEGE_CTG SRIOV_CTG_ONLOAD19063 19064/* MC_CMD_ONLOAD_STACK_ALLOC_IN msgrequest */19065#define MC_CMD_ONLOAD_STACK_ALLOC_IN_LEN 419066/* The handle of the owning upstream port */19067#define MC_CMD_ONLOAD_STACK_ALLOC_IN_UPSTREAM_PORT_ID_OFST 019068#define MC_CMD_ONLOAD_STACK_ALLOC_IN_UPSTREAM_PORT_ID_LEN 419069 19070/* MC_CMD_ONLOAD_STACK_ALLOC_OUT msgresponse */19071#define MC_CMD_ONLOAD_STACK_ALLOC_OUT_LEN 419072/* The handle of the new Onload stack */19073#define MC_CMD_ONLOAD_STACK_ALLOC_OUT_ONLOAD_STACK_ID_OFST 019074#define MC_CMD_ONLOAD_STACK_ALLOC_OUT_ONLOAD_STACK_ID_LEN 419075 19076 19077/***********************************/19078/* MC_CMD_ONLOAD_STACK_FREE19079 * Free an Onload stack ID.19080 */19081#define MC_CMD_ONLOAD_STACK_FREE 0x9d19082#undef MC_CMD_0x9d_PRIVILEGE_CTG19083 19084#define MC_CMD_0x9d_PRIVILEGE_CTG SRIOV_CTG_ONLOAD19085 19086/* MC_CMD_ONLOAD_STACK_FREE_IN msgrequest */19087#define MC_CMD_ONLOAD_STACK_FREE_IN_LEN 419088/* The handle of the Onload stack */19089#define MC_CMD_ONLOAD_STACK_FREE_IN_ONLOAD_STACK_ID_OFST 019090#define MC_CMD_ONLOAD_STACK_FREE_IN_ONLOAD_STACK_ID_LEN 419091 19092/* MC_CMD_ONLOAD_STACK_FREE_OUT msgresponse */19093#define MC_CMD_ONLOAD_STACK_FREE_OUT_LEN 019094 19095 19096/***********************************/19097/* MC_CMD_RSS_CONTEXT_ALLOC19098 * Allocate an RSS context.19099 */19100#define MC_CMD_RSS_CONTEXT_ALLOC 0x9e19101#undef MC_CMD_0x9e_PRIVILEGE_CTG19102 19103#define MC_CMD_0x9e_PRIVILEGE_CTG SRIOV_CTG_GENERAL19104 19105/* MC_CMD_RSS_CONTEXT_ALLOC_IN msgrequest */19106#define MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN 1219107/* The handle of the owning upstream port */19108#define MC_CMD_RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID_OFST 019109#define MC_CMD_RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID_LEN 419110/* The type of context to allocate */19111#define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_OFST 419112#define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_LEN 419113/* enum: Allocate a context for exclusive use. The key and indirection table19114 * must be explicitly configured.19115 */19116#define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE 0x019117/* enum: Allocate a context for shared use; this will spread across a range of19118 * queues, but the key and indirection table are pre-configured and may not be19119 * changed. For this mode, NUM_QUEUES must 2, 4, 8, 16, 32 or 64.19120 */19121#define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_SHARED 0x119122/* enum: Allocate a context to spread evenly across an arbitrary number of19123 * queues. No indirection table space is allocated for this context. (EF100 and19124 * later)19125 */19126#define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EVEN_SPREADING 0x219127/* Number of queues spanned by this context. For exclusive contexts this must19128 * be in the range 1 to RSS_MAX_INDIRECTION_QUEUES, where19129 * RSS_MAX_INDIRECTION_QUEUES is queried from MC_CMD_GET_CAPABILITIES_V9 or if19130 * V9 is not supported then RSS_MAX_INDIRECTION_QUEUES is 64. Valid entries in19131 * the indirection table will be in the range 0 to NUM_QUEUES-1. For even-19132 * spreading contexts this must be in the range 1 to19133 * RSS_MAX_EVEN_SPREADING_QUEUES as queried from MC_CMD_GET_CAPABILITIES. Note19134 * that specifying NUM_QUEUES = 1 will not perform any spreading but may still19135 * be useful as a way of obtaining the Toeplitz hash.19136 */19137#define MC_CMD_RSS_CONTEXT_ALLOC_IN_NUM_QUEUES_OFST 819138#define MC_CMD_RSS_CONTEXT_ALLOC_IN_NUM_QUEUES_LEN 419139 19140/* MC_CMD_RSS_CONTEXT_ALLOC_V2_IN msgrequest */19141#define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_LEN 1619142/* The handle of the owning upstream port */19143#define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_UPSTREAM_PORT_ID_OFST 019144#define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_UPSTREAM_PORT_ID_LEN 419145/* The type of context to allocate */19146#define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_TYPE_OFST 419147#define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_TYPE_LEN 419148/* enum: Allocate a context for exclusive use. The key and indirection table19149 * must be explicitly configured.19150 */19151#define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_TYPE_EXCLUSIVE 0x019152/* enum: Allocate a context for shared use; this will spread across a range of19153 * queues, but the key and indirection table are pre-configured and may not be19154 * changed. For this mode, NUM_QUEUES must 2, 4, 8, 16, 32 or 64.19155 */19156#define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_TYPE_SHARED 0x119157/* enum: Allocate a context to spread evenly across an arbitrary number of19158 * queues. No indirection table space is allocated for this context. (EF100 and19159 * later)19160 */19161#define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_TYPE_EVEN_SPREADING 0x219162/* Number of queues spanned by this context. For exclusive contexts this must19163 * be in the range 1 to RSS_MAX_INDIRECTION_QUEUES, where19164 * RSS_MAX_INDIRECTION_QUEUES is queried from MC_CMD_GET_CAPABILITIES_V9 or if19165 * V9 is not supported then RSS_MAX_INDIRECTION_QUEUES is 64. Valid entries in19166 * the indirection table will be in the range 0 to NUM_QUEUES-1. For even-19167 * spreading contexts this must be in the range 1 to19168 * RSS_MAX_EVEN_SPREADING_QUEUES as queried from MC_CMD_GET_CAPABILITIES. Note19169 * that specifying NUM_QUEUES = 1 will not perform any spreading but may still19170 * be useful as a way of obtaining the Toeplitz hash.19171 */19172#define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_NUM_QUEUES_OFST 819173#define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_NUM_QUEUES_LEN 419174/* Size of indirection table to be allocated to this context from the pool.19175 * Must be a power of 2. The minimum and maximum table size can be queried19176 * using MC_CMD_GET_CAPABILITIES_V9. If there is not enough space remaining in19177 * the common pool to allocate the requested table size, due to allocating19178 * table space to other RSS contexts, then the command will fail with19179 * MC_CMD_ERR_ENOSPC.19180 */19181#define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_INDIRECTION_TABLE_SIZE_OFST 1219182#define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_INDIRECTION_TABLE_SIZE_LEN 419183 19184/* MC_CMD_RSS_CONTEXT_ALLOC_OUT msgresponse */19185#define MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN 419186/* The handle of the new RSS context. This should be considered opaque to the19187 * host, although a value of 0xFFFFFFFF is guaranteed never to be a valid19188 * handle.19189 */19190#define MC_CMD_RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID_OFST 019191#define MC_CMD_RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID_LEN 419192/* enum: guaranteed invalid RSS context handle value */19193#define MC_CMD_RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID_INVALID 0xffffffff19194 19195 19196/***********************************/19197/* MC_CMD_RSS_CONTEXT_FREE19198 * Free an RSS context.19199 */19200#define MC_CMD_RSS_CONTEXT_FREE 0x9f19201#undef MC_CMD_0x9f_PRIVILEGE_CTG19202 19203#define MC_CMD_0x9f_PRIVILEGE_CTG SRIOV_CTG_GENERAL19204 19205/* MC_CMD_RSS_CONTEXT_FREE_IN msgrequest */19206#define MC_CMD_RSS_CONTEXT_FREE_IN_LEN 419207/* The handle of the RSS context */19208#define MC_CMD_RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID_OFST 019209#define MC_CMD_RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID_LEN 419210 19211/* MC_CMD_RSS_CONTEXT_FREE_OUT msgresponse */19212#define MC_CMD_RSS_CONTEXT_FREE_OUT_LEN 019213 19214 19215/***********************************/19216/* MC_CMD_RSS_CONTEXT_SET_KEY19217 * Set the Toeplitz hash key for an RSS context.19218 */19219#define MC_CMD_RSS_CONTEXT_SET_KEY 0xa019220#undef MC_CMD_0xa0_PRIVILEGE_CTG19221 19222#define MC_CMD_0xa0_PRIVILEGE_CTG SRIOV_CTG_GENERAL19223 19224/* MC_CMD_RSS_CONTEXT_SET_KEY_IN msgrequest */19225#define MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN 4419226/* The handle of the RSS context */19227#define MC_CMD_RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID_OFST 019228#define MC_CMD_RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID_LEN 419229/* The 40-byte Toeplitz hash key (TBD endianness issues?) */19230#define MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_OFST 419231#define MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN 4019232 19233/* MC_CMD_RSS_CONTEXT_SET_KEY_OUT msgresponse */19234#define MC_CMD_RSS_CONTEXT_SET_KEY_OUT_LEN 019235 19236 19237/***********************************/19238/* MC_CMD_RSS_CONTEXT_GET_KEY19239 * Get the Toeplitz hash key for an RSS context.19240 */19241#define MC_CMD_RSS_CONTEXT_GET_KEY 0xa119242#undef MC_CMD_0xa1_PRIVILEGE_CTG19243 19244#define MC_CMD_0xa1_PRIVILEGE_CTG SRIOV_CTG_GENERAL19245 19246/* MC_CMD_RSS_CONTEXT_GET_KEY_IN msgrequest */19247#define MC_CMD_RSS_CONTEXT_GET_KEY_IN_LEN 419248/* The handle of the RSS context */19249#define MC_CMD_RSS_CONTEXT_GET_KEY_IN_RSS_CONTEXT_ID_OFST 019250#define MC_CMD_RSS_CONTEXT_GET_KEY_IN_RSS_CONTEXT_ID_LEN 419251 19252/* MC_CMD_RSS_CONTEXT_GET_KEY_OUT msgresponse */19253#define MC_CMD_RSS_CONTEXT_GET_KEY_OUT_LEN 4419254/* The 40-byte Toeplitz hash key (TBD endianness issues?) */19255#define MC_CMD_RSS_CONTEXT_GET_KEY_OUT_TOEPLITZ_KEY_OFST 419256#define MC_CMD_RSS_CONTEXT_GET_KEY_OUT_TOEPLITZ_KEY_LEN 4019257 19258 19259/***********************************/19260/* MC_CMD_RSS_CONTEXT_SET_TABLE19261 * Set the indirection table for an RSS context. This command should only be19262 * used with indirection tables containing 128 entries, which is the default19263 * when the RSS context is allocated without specifying a table size.19264 */19265#define MC_CMD_RSS_CONTEXT_SET_TABLE 0xa219266#undef MC_CMD_0xa2_PRIVILEGE_CTG19267 19268#define MC_CMD_0xa2_PRIVILEGE_CTG SRIOV_CTG_GENERAL19269 19270/* MC_CMD_RSS_CONTEXT_SET_TABLE_IN msgrequest */19271#define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN 13219272/* The handle of the RSS context */19273#define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID_OFST 019274#define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID_LEN 419275/* The 128-byte indirection table (1 byte per entry) */19276#define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_OFST 419277#define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_LEN 12819278 19279/* MC_CMD_RSS_CONTEXT_SET_TABLE_OUT msgresponse */19280#define MC_CMD_RSS_CONTEXT_SET_TABLE_OUT_LEN 019281 19282 19283/***********************************/19284/* MC_CMD_RSS_CONTEXT_GET_TABLE19285 * Get the indirection table for an RSS context. This command should only be19286 * used with indirection tables containing 128 entries, which is the default19287 * when the RSS context is allocated without specifying a table size.19288 */19289#define MC_CMD_RSS_CONTEXT_GET_TABLE 0xa319290#undef MC_CMD_0xa3_PRIVILEGE_CTG19291 19292#define MC_CMD_0xa3_PRIVILEGE_CTG SRIOV_CTG_GENERAL19293 19294/* MC_CMD_RSS_CONTEXT_GET_TABLE_IN msgrequest */19295#define MC_CMD_RSS_CONTEXT_GET_TABLE_IN_LEN 419296/* The handle of the RSS context */19297#define MC_CMD_RSS_CONTEXT_GET_TABLE_IN_RSS_CONTEXT_ID_OFST 019298#define MC_CMD_RSS_CONTEXT_GET_TABLE_IN_RSS_CONTEXT_ID_LEN 419299 19300/* MC_CMD_RSS_CONTEXT_GET_TABLE_OUT msgresponse */19301#define MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_LEN 13219302/* The 128-byte indirection table (1 byte per entry) */19303#define MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_INDIRECTION_TABLE_OFST 419304#define MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_INDIRECTION_TABLE_LEN 12819305 19306 19307/***********************************/19308/* MC_CMD_RSS_CONTEXT_WRITE_TABLE19309 * Write a portion of a selectable-size indirection table for an RSS context.19310 * This command must be used instead of MC_CMD_RSS_CONTEXT_SET_TABLE if the19311 * RSS_SELECTABLE_TABLE_SIZE bit is set in MC_CMD_GET_CAPABILITIES.19312 */19313#define MC_CMD_RSS_CONTEXT_WRITE_TABLE 0x13e19314#undef MC_CMD_0x13e_PRIVILEGE_CTG19315 19316#define MC_CMD_0x13e_PRIVILEGE_CTG SRIOV_CTG_GENERAL19317 19318/* MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN msgrequest */19319#define MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_LENMIN 819320#define MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_LENMAX 25219321#define MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_LENMAX_MCDI2 102019322#define MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_LEN(num) (4+4*(num))19323#define MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_ENTRIES_NUM(len) (((len)-4)/4)19324/* The handle of the RSS context */19325#define MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_RSS_CONTEXT_ID_OFST 019326#define MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_RSS_CONTEXT_ID_LEN 419327/* An array of index-value pairs to be written to the table. Structure is19328 * MC_CMD_RSS_CONTEXT_WRITE_TABLE_ENTRY.19329 */19330#define MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_ENTRIES_OFST 419331#define MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_ENTRIES_LEN 419332#define MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_ENTRIES_MINNUM 119333#define MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_ENTRIES_MAXNUM 6219334#define MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_ENTRIES_MAXNUM_MCDI2 25419335 19336/* MC_CMD_RSS_CONTEXT_WRITE_TABLE_OUT msgresponse */19337#define MC_CMD_RSS_CONTEXT_WRITE_TABLE_OUT_LEN 019338 19339/* MC_CMD_RSS_CONTEXT_WRITE_TABLE_ENTRY structuredef */19340#define MC_CMD_RSS_CONTEXT_WRITE_TABLE_ENTRY_LEN 419341/* The index of the table entry to be written. */19342#define MC_CMD_RSS_CONTEXT_WRITE_TABLE_ENTRY_INDEX_OFST 019343#define MC_CMD_RSS_CONTEXT_WRITE_TABLE_ENTRY_INDEX_LEN 219344#define MC_CMD_RSS_CONTEXT_WRITE_TABLE_ENTRY_INDEX_LBN 019345#define MC_CMD_RSS_CONTEXT_WRITE_TABLE_ENTRY_INDEX_WIDTH 1619346/* The value to write into the table entry. */19347#define MC_CMD_RSS_CONTEXT_WRITE_TABLE_ENTRY_VALUE_OFST 219348#define MC_CMD_RSS_CONTEXT_WRITE_TABLE_ENTRY_VALUE_LEN 219349#define MC_CMD_RSS_CONTEXT_WRITE_TABLE_ENTRY_VALUE_LBN 1619350#define MC_CMD_RSS_CONTEXT_WRITE_TABLE_ENTRY_VALUE_WIDTH 1619351 19352 19353/***********************************/19354/* MC_CMD_RSS_CONTEXT_READ_TABLE19355 * Read a portion of a selectable-size indirection table for an RSS context.19356 * This command must be used instead of MC_CMD_RSS_CONTEXT_GET_TABLE if the19357 * RSS_SELECTABLE_TABLE_SIZE bit is set in MC_CMD_GET_CAPABILITIES.19358 */19359#define MC_CMD_RSS_CONTEXT_READ_TABLE 0x13f19360#undef MC_CMD_0x13f_PRIVILEGE_CTG19361 19362#define MC_CMD_0x13f_PRIVILEGE_CTG SRIOV_CTG_GENERAL19363 19364/* MC_CMD_RSS_CONTEXT_READ_TABLE_IN msgrequest */19365#define MC_CMD_RSS_CONTEXT_READ_TABLE_IN_LENMIN 619366#define MC_CMD_RSS_CONTEXT_READ_TABLE_IN_LENMAX 25219367#define MC_CMD_RSS_CONTEXT_READ_TABLE_IN_LENMAX_MCDI2 102019368#define MC_CMD_RSS_CONTEXT_READ_TABLE_IN_LEN(num) (4+2*(num))19369#define MC_CMD_RSS_CONTEXT_READ_TABLE_IN_INDICES_NUM(len) (((len)-4)/2)19370/* The handle of the RSS context */19371#define MC_CMD_RSS_CONTEXT_READ_TABLE_IN_RSS_CONTEXT_ID_OFST 019372#define MC_CMD_RSS_CONTEXT_READ_TABLE_IN_RSS_CONTEXT_ID_LEN 419373/* An array containing the indices of the entries to be read. */19374#define MC_CMD_RSS_CONTEXT_READ_TABLE_IN_INDICES_OFST 419375#define MC_CMD_RSS_CONTEXT_READ_TABLE_IN_INDICES_LEN 219376#define MC_CMD_RSS_CONTEXT_READ_TABLE_IN_INDICES_MINNUM 119377#define MC_CMD_RSS_CONTEXT_READ_TABLE_IN_INDICES_MAXNUM 12419378#define MC_CMD_RSS_CONTEXT_READ_TABLE_IN_INDICES_MAXNUM_MCDI2 50819379 19380/* MC_CMD_RSS_CONTEXT_READ_TABLE_OUT msgresponse */19381#define MC_CMD_RSS_CONTEXT_READ_TABLE_OUT_LENMIN 219382#define MC_CMD_RSS_CONTEXT_READ_TABLE_OUT_LENMAX 25219383#define MC_CMD_RSS_CONTEXT_READ_TABLE_OUT_LENMAX_MCDI2 102019384#define MC_CMD_RSS_CONTEXT_READ_TABLE_OUT_LEN(num) (0+2*(num))19385#define MC_CMD_RSS_CONTEXT_READ_TABLE_OUT_DATA_NUM(len) (((len)-0)/2)19386/* A buffer containing the requested entries read from the table. */19387#define MC_CMD_RSS_CONTEXT_READ_TABLE_OUT_DATA_OFST 019388#define MC_CMD_RSS_CONTEXT_READ_TABLE_OUT_DATA_LEN 219389#define MC_CMD_RSS_CONTEXT_READ_TABLE_OUT_DATA_MINNUM 119390#define MC_CMD_RSS_CONTEXT_READ_TABLE_OUT_DATA_MAXNUM 12619391#define MC_CMD_RSS_CONTEXT_READ_TABLE_OUT_DATA_MAXNUM_MCDI2 51019392 19393 19394/***********************************/19395/* MC_CMD_RSS_CONTEXT_SET_FLAGS19396 * Set various control flags for an RSS context.19397 */19398#define MC_CMD_RSS_CONTEXT_SET_FLAGS 0xe119399#undef MC_CMD_0xe1_PRIVILEGE_CTG19400 19401#define MC_CMD_0xe1_PRIVILEGE_CTG SRIOV_CTG_GENERAL19402 19403/* MC_CMD_RSS_CONTEXT_SET_FLAGS_IN msgrequest */19404#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_LEN 819405/* The handle of the RSS context */19406#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RSS_CONTEXT_ID_OFST 019407#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RSS_CONTEXT_ID_LEN 419408/* Hash control flags. The _EN bits are always supported, but new modes are19409 * available when ADDITIONAL_RSS_MODES is reported by MC_CMD_GET_CAPABILITIES:19410 * in this case, the MODE fields may be set to non-zero values, and will take19411 * effect regardless of the settings of the _EN flags. See the RSS_MODE19412 * structure for the meaning of the mode bits. Drivers must check the19413 * capability before trying to set any _MODE fields, as older firmware will19414 * reject any attempt to set the FLAGS field to a value > 0xff with EINVAL. In19415 * the case where all the _MODE flags are zero, the _EN flags take effect,19416 * providing backward compatibility for existing drivers. (Setting all _MODE19417 * *and* all _EN flags to zero is valid, to disable RSS spreading for that19418 * particular packet type.)19419 */19420#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_FLAGS_OFST 419421#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_FLAGS_LEN 419422#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV4_EN_OFST 419423#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV4_EN_LBN 019424#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV4_EN_WIDTH 119425#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV4_EN_OFST 419426#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV4_EN_LBN 119427#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV4_EN_WIDTH 119428#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV6_EN_OFST 419429#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV6_EN_LBN 219430#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV6_EN_WIDTH 119431#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV6_EN_OFST 419432#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV6_EN_LBN 319433#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV6_EN_WIDTH 119434#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RESERVED_OFST 419435#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RESERVED_LBN 419436#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RESERVED_WIDTH 419437#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV4_RSS_MODE_OFST 419438#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV4_RSS_MODE_LBN 819439#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV4_RSS_MODE_WIDTH 419440#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV4_RSS_MODE_OFST 419441#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV4_RSS_MODE_LBN 1219442#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV4_RSS_MODE_WIDTH 419443#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV4_RSS_MODE_OFST 419444#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV4_RSS_MODE_LBN 1619445#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV4_RSS_MODE_WIDTH 419446#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV6_RSS_MODE_OFST 419447#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV6_RSS_MODE_LBN 2019448#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV6_RSS_MODE_WIDTH 419449#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV6_RSS_MODE_OFST 419450#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV6_RSS_MODE_LBN 2419451#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV6_RSS_MODE_WIDTH 419452#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV6_RSS_MODE_OFST File truncated to the first 1 MiB.