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1// SPDX-License-Identifier: GPL-2.0-only2/****************************************************************************3 * Driver for Solarflare network controllers and boards4 * Copyright 2005-2006 Fen Systems Ltd.5 * Copyright 2006-2013 Solarflare Communications Inc.6 */7 8#include <linux/bitops.h>9#include <linux/delay.h>10#include <linux/interrupt.h>11#include <linux/pci.h>12#include <linux/module.h>13#include <linux/seq_file.h>14#include <linux/cpu_rmap.h>15#include "net_driver.h"16#include "bitfield.h"17#include "efx.h"18#include "nic.h"19#include "ef10_regs.h"20#include "io.h"21#include "workarounds.h"22#include "mcdi_pcol.h"23 24/**************************************************************************25 *26 * Generic buffer handling27 * These buffers are used for interrupt status, MAC stats, etc.28 *29 **************************************************************************/30 31int efx_nic_alloc_buffer(struct efx_nic *efx, struct efx_buffer *buffer,32 unsigned int len, gfp_t gfp_flags)33{34 buffer->addr = dma_alloc_coherent(&efx->pci_dev->dev, len,35 &buffer->dma_addr, gfp_flags);36 if (!buffer->addr)37 return -ENOMEM;38 buffer->len = len;39 return 0;40}41 42void efx_nic_free_buffer(struct efx_nic *efx, struct efx_buffer *buffer)43{44 if (buffer->addr) {45 dma_free_coherent(&efx->pci_dev->dev, buffer->len,46 buffer->addr, buffer->dma_addr);47 buffer->addr = NULL;48 }49}50 51/* Check whether an event is present in the eventq at the current52 * read pointer. Only useful for self-test.53 */54bool efx_nic_event_present(struct efx_channel *channel)55{56 return efx_event_present(efx_event(channel, channel->eventq_read_ptr));57}58 59void efx_nic_event_test_start(struct efx_channel *channel)60{61 channel->event_test_cpu = -1;62 smp_wmb();63 channel->efx->type->ev_test_generate(channel);64}65 66int efx_nic_irq_test_start(struct efx_nic *efx)67{68 efx->last_irq_cpu = -1;69 smp_wmb();70 return efx->type->irq_test_generate(efx);71}72 73/* Hook interrupt handler(s)74 * Try MSI and then legacy interrupts.75 */76int efx_nic_init_interrupt(struct efx_nic *efx)77{78 struct efx_channel *channel;79 unsigned int n_irqs;80 int rc;81 82 if (!EFX_INT_MODE_USE_MSI(efx)) {83 rc = request_irq(efx->legacy_irq,84 efx->type->irq_handle_legacy, IRQF_SHARED,85 efx->name, efx);86 if (rc) {87 netif_err(efx, drv, efx->net_dev,88 "failed to hook legacy IRQ %d\n",89 efx->pci_dev->irq);90 goto fail1;91 }92 efx->irqs_hooked = true;93 return 0;94 }95 96#ifdef CONFIG_RFS_ACCEL97 if (efx->interrupt_mode == EFX_INT_MODE_MSIX) {98 efx->net_dev->rx_cpu_rmap =99 alloc_irq_cpu_rmap(efx->n_rx_channels);100 if (!efx->net_dev->rx_cpu_rmap) {101 rc = -ENOMEM;102 goto fail1;103 }104 }105#endif106 107 /* Hook MSI or MSI-X interrupt */108 n_irqs = 0;109 efx_for_each_channel(channel, efx) {110 rc = request_irq(channel->irq, efx->type->irq_handle_msi,111 IRQF_PROBE_SHARED, /* Not shared */112 efx->msi_context[channel->channel].name,113 &efx->msi_context[channel->channel]);114 if (rc) {115 netif_err(efx, drv, efx->net_dev,116 "failed to hook IRQ %d\n", channel->irq);117 goto fail2;118 }119 ++n_irqs;120 121#ifdef CONFIG_RFS_ACCEL122 if (efx->interrupt_mode == EFX_INT_MODE_MSIX &&123 channel->channel < efx->n_rx_channels) {124 rc = irq_cpu_rmap_add(efx->net_dev->rx_cpu_rmap,125 channel->irq);126 if (rc)127 goto fail2;128 }129#endif130 }131 132 efx->irqs_hooked = true;133 return 0;134 135 fail2:136#ifdef CONFIG_RFS_ACCEL137 free_irq_cpu_rmap(efx->net_dev->rx_cpu_rmap);138 efx->net_dev->rx_cpu_rmap = NULL;139#endif140 efx_for_each_channel(channel, efx) {141 if (n_irqs-- == 0)142 break;143 free_irq(channel->irq, &efx->msi_context[channel->channel]);144 }145 fail1:146 return rc;147}148 149void efx_nic_fini_interrupt(struct efx_nic *efx)150{151 struct efx_channel *channel;152 153#ifdef CONFIG_RFS_ACCEL154 free_irq_cpu_rmap(efx->net_dev->rx_cpu_rmap);155 efx->net_dev->rx_cpu_rmap = NULL;156#endif157 158 if (!efx->irqs_hooked)159 return;160 if (EFX_INT_MODE_USE_MSI(efx)) {161 /* Disable MSI/MSI-X interrupts */162 efx_for_each_channel(channel, efx)163 free_irq(channel->irq,164 &efx->msi_context[channel->channel]);165 } else {166 /* Disable legacy interrupt */167 free_irq(efx->legacy_irq, efx);168 }169 efx->irqs_hooked = false;170}171 172/* Register dump */173 174#define REGISTER_REVISION_ED 4175#define REGISTER_REVISION_EZ 4 /* latest EF10 revision */176 177struct efx_nic_reg {178 u32 offset:24;179 u32 min_revision:3, max_revision:3;180};181 182#define REGISTER(name, arch, min_rev, max_rev) { \183 arch ## R_ ## min_rev ## max_rev ## _ ## name, \184 REGISTER_REVISION_ ## arch ## min_rev, \185 REGISTER_REVISION_ ## arch ## max_rev \186}187#define REGISTER_DZ(name) REGISTER(name, E, D, Z)188 189static const struct efx_nic_reg efx_nic_regs[] = {190 /* XX_PRBS_CTL, XX_PRBS_CHK and XX_PRBS_ERR are not used */191 /* XX_CORE_STAT is partly RC */192 REGISTER_DZ(BIU_HW_REV_ID),193 REGISTER_DZ(MC_DB_LWRD),194 REGISTER_DZ(MC_DB_HWRD),195};196 197struct efx_nic_reg_table {198 u32 offset:24;199 u32 min_revision:3, max_revision:3;200 u32 step:6, rows:21;201};202 203#define REGISTER_TABLE_DIMENSIONS(_, offset, arch, min_rev, max_rev, step, rows) { \204 offset, \205 REGISTER_REVISION_ ## arch ## min_rev, \206 REGISTER_REVISION_ ## arch ## max_rev, \207 step, rows \208}209#define REGISTER_TABLE(name, arch, min_rev, max_rev) \210 REGISTER_TABLE_DIMENSIONS( \211 name, arch ## R_ ## min_rev ## max_rev ## _ ## name, \212 arch, min_rev, max_rev, \213 arch ## R_ ## min_rev ## max_rev ## _ ## name ## _STEP, \214 arch ## R_ ## min_rev ## max_rev ## _ ## name ## _ROWS)215#define REGISTER_TABLE_DZ(name) REGISTER_TABLE(name, E, D, Z)216 217static const struct efx_nic_reg_table efx_nic_reg_tables[] = {218 REGISTER_TABLE_DZ(BIU_MC_SFT_STATUS),219};220 221size_t efx_nic_get_regs_len(struct efx_nic *efx)222{223 const struct efx_nic_reg *reg;224 const struct efx_nic_reg_table *table;225 size_t len = 0;226 227 for (reg = efx_nic_regs;228 reg < efx_nic_regs + ARRAY_SIZE(efx_nic_regs);229 reg++)230 if (efx->type->revision >= reg->min_revision &&231 efx->type->revision <= reg->max_revision)232 len += sizeof(efx_oword_t);233 234 for (table = efx_nic_reg_tables;235 table < efx_nic_reg_tables + ARRAY_SIZE(efx_nic_reg_tables);236 table++)237 if (efx->type->revision >= table->min_revision &&238 efx->type->revision <= table->max_revision)239 len += table->rows * min_t(size_t, table->step, 16);240 241 return len;242}243 244void efx_nic_get_regs(struct efx_nic *efx, void *buf)245{246 const struct efx_nic_reg *reg;247 const struct efx_nic_reg_table *table;248 249 for (reg = efx_nic_regs;250 reg < efx_nic_regs + ARRAY_SIZE(efx_nic_regs);251 reg++) {252 if (efx->type->revision >= reg->min_revision &&253 efx->type->revision <= reg->max_revision) {254 efx_reado(efx, (efx_oword_t *)buf, reg->offset);255 buf += sizeof(efx_oword_t);256 }257 }258 259 for (table = efx_nic_reg_tables;260 table < efx_nic_reg_tables + ARRAY_SIZE(efx_nic_reg_tables);261 table++) {262 size_t size, i;263 264 if (!(efx->type->revision >= table->min_revision &&265 efx->type->revision <= table->max_revision))266 continue;267 268 size = min_t(size_t, table->step, 16);269 270 for (i = 0; i < table->rows; i++) {271 switch (table->step) {272 case 4: /* 32-bit SRAM */273 efx_readd(efx, buf, table->offset + 4 * i);274 break;275 case 16: /* 128-bit-readable register */276 efx_reado_table(efx, buf, table->offset, i);277 break;278 case 32: /* 128-bit register, interleaved */279 efx_reado_table(efx, buf, table->offset, 2 * i);280 break;281 default:282 WARN_ON(1);283 return;284 }285 buf += size;286 }287 }288}289 290/**291 * efx_nic_describe_stats - Describe supported statistics for ethtool292 * @desc: Array of &struct efx_hw_stat_desc describing the statistics293 * @count: Length of the @desc array294 * @mask: Bitmask of which elements of @desc are enabled295 * @names: Buffer to copy names to, or %NULL. The names are copied296 * starting at intervals of %ETH_GSTRING_LEN bytes.297 *298 * Returns the number of visible statistics, i.e. the number of set299 * bits in the first @count bits of @mask for which a name is defined.300 */301size_t efx_nic_describe_stats(const struct efx_hw_stat_desc *desc, size_t count,302 const unsigned long *mask, u8 *names)303{304 size_t visible = 0;305 size_t index;306 307 for_each_set_bit(index, mask, count) {308 if (desc[index].name) {309 if (names) {310 strscpy(names, desc[index].name,311 ETH_GSTRING_LEN);312 names += ETH_GSTRING_LEN;313 }314 ++visible;315 }316 }317 318 return visible;319}320 321/**322 * efx_nic_copy_stats - Copy stats from the DMA buffer in to an323 * intermediate buffer. This is used to get a consistent324 * set of stats while the DMA buffer can be written at any time325 * by the NIC.326 * @efx: The associated NIC.327 * @dest: Destination buffer. Must be the same size as the DMA buffer.328 */329int efx_nic_copy_stats(struct efx_nic *efx, __le64 *dest)330{331 __le64 *dma_stats = efx->stats_buffer.addr;332 __le64 generation_start, generation_end;333 int rc = 0, retry;334 335 if (!dest)336 return 0;337 338 if (!dma_stats)339 goto return_zeroes;340 341 /* If we're unlucky enough to read statistics during the DMA, wait342 * up to 10ms for it to finish (typically takes <500us)343 */344 for (retry = 0; retry < 100; ++retry) {345 generation_end = dma_stats[efx->num_mac_stats - 1];346 if (generation_end == EFX_MC_STATS_GENERATION_INVALID)347 goto return_zeroes;348 rmb();349 memcpy(dest, dma_stats, efx->num_mac_stats * sizeof(__le64));350 rmb();351 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];352 if (generation_end == generation_start)353 return 0; /* return good data */354 udelay(100);355 }356 357 rc = -EIO;358 359return_zeroes:360 memset(dest, 0, efx->num_mac_stats * sizeof(u64));361 return rc;362}363 364/**365 * efx_nic_update_stats - Convert statistics DMA buffer to array of u64366 * @desc: Array of &struct efx_hw_stat_desc describing the DMA buffer367 * layout. DMA widths of 0, 16, 32 and 64 are supported; where368 * the width is specified as 0 the corresponding element of369 * @stats is not updated.370 * @count: Length of the @desc array371 * @mask: Bitmask of which elements of @desc are enabled372 * @stats: Buffer to update with the converted statistics. The length373 * of this array must be at least @count.374 * @dma_buf: DMA buffer containing hardware statistics375 * @accumulate: If set, the converted values will be added rather than376 * directly stored to the corresponding elements of @stats377 */378void efx_nic_update_stats(const struct efx_hw_stat_desc *desc, size_t count,379 const unsigned long *mask,380 u64 *stats, const void *dma_buf, bool accumulate)381{382 size_t index;383 384 for_each_set_bit(index, mask, count) {385 if (desc[index].dma_width) {386 const void *addr = dma_buf + desc[index].offset;387 u64 val;388 389 switch (desc[index].dma_width) {390 case 16:391 val = le16_to_cpup((__le16 *)addr);392 break;393 case 32:394 val = le32_to_cpup((__le32 *)addr);395 break;396 case 64:397 val = le64_to_cpup((__le64 *)addr);398 break;399 default:400 WARN_ON(1);401 val = 0;402 break;403 }404 405 if (accumulate)406 stats[index] += val;407 else408 stats[index] = val;409 }410 }411}412 413void efx_nic_fix_nodesc_drop_stat(struct efx_nic *efx, u64 *rx_nodesc_drops)414{415 /* if down, or this is the first update after coming up */416 if (!(efx->net_dev->flags & IFF_UP) || !efx->rx_nodesc_drops_prev_state)417 efx->rx_nodesc_drops_while_down +=418 *rx_nodesc_drops - efx->rx_nodesc_drops_total;419 efx->rx_nodesc_drops_total = *rx_nodesc_drops;420 efx->rx_nodesc_drops_prev_state = !!(efx->net_dev->flags & IFF_UP);421 *rx_nodesc_drops -= efx->rx_nodesc_drops_while_down;422}423