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1/* SPDX-License-Identifier: GPL-2.0-only */2/****************************************************************************3 * Driver for Solarflare network controllers and boards4 * Copyright 2005-2006 Fen Systems Ltd.5 * Copyright 2006-2013 Solarflare Communications Inc.6 */7 8#ifndef EFX_IO_H9#define EFX_IO_H10 11#include <linux/io.h>12#include <linux/spinlock.h>13 14/**************************************************************************15 *16 * NIC register I/O17 *18 **************************************************************************19 *20 * Notes on locking strategy for the Falcon architecture:21 *22 * Many CSRs are very wide and cannot be read or written atomically.23 * Writes from the host are buffered by the Bus Interface Unit (BIU)24 * up to 128 bits. Whenever the host writes part of such a register,25 * the BIU collects the written value and does not write to the26 * underlying register until all 4 dwords have been written. A27 * similar buffering scheme applies to host access to the NIC's 64-bit28 * SRAM.29 *30 * Writes to different CSRs and 64-bit SRAM words must be serialised,31 * since interleaved access can result in lost writes. We use32 * efx_nic::biu_lock for this.33 *34 * We also serialise reads from 128-bit CSRs and SRAM with the same35 * spinlock. This may not be necessary, but it doesn't really matter36 * as there are no such reads on the fast path.37 *38 * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are39 * 128-bit but are special-cased in the BIU to avoid the need for40 * locking in the host:41 *42 * - They are write-only.43 * - The semantics of writing to these registers are such that44 * replacing the low 96 bits with zero does not affect functionality.45 * - If the host writes to the last dword address of such a register46 * (i.e. the high 32 bits) the underlying register will always be47 * written. If the collector and the current write together do not48 * provide values for all 128 bits of the register, the low 96 bits49 * will be written as zero.50 * - If the host writes to the address of any other part of such a51 * register while the collector already holds values for some other52 * register, the write is discarded and the collector maintains its53 * current state.54 *55 * The EF10 architecture exposes very few registers to the host and56 * most of them are only 32 bits wide. The only exceptions are the MC57 * doorbell register pair, which has its own latching, and58 * TX_DESC_UPD, which works in a similar way to the Falcon59 * architecture.60 */61 62#if BITS_PER_LONG == 6463#define EFX_USE_QWORD_IO 164#endif65 66/* Hardware issue requires that only 64-bit naturally aligned writes67 * are seen by hardware. Its not strictly necessary to restrict to68 * x86_64 arch, but done for safety since unusual write combining behaviour69 * can break PIO.70 */71#ifdef CONFIG_X86_6472/* PIO is a win only if write-combining is possible */73#ifdef ioremap_wc74#define EFX_USE_PIO 175#endif76#endif77 78static inline u32 efx_reg(struct efx_nic *efx, unsigned int reg)79{80 return efx->reg_base + reg;81}82 83#ifdef EFX_USE_QWORD_IO84static inline void _efx_writeq(struct efx_nic *efx, __le64 value,85 unsigned int reg)86{87 __raw_writeq((__force u64)value, efx->membase + reg);88}89static inline __le64 _efx_readq(struct efx_nic *efx, unsigned int reg)90{91 return (__force __le64)__raw_readq(efx->membase + reg);92}93#endif94 95static inline void _efx_writed(struct efx_nic *efx, __le32 value,96 unsigned int reg)97{98 __raw_writel((__force u32)value, efx->membase + reg);99}100static inline __le32 _efx_readd(struct efx_nic *efx, unsigned int reg)101{102 return (__force __le32)__raw_readl(efx->membase + reg);103}104 105/* Write a normal 128-bit CSR, locking as appropriate. */106static inline void efx_writeo(struct efx_nic *efx, const efx_oword_t *value,107 unsigned int reg)108{109 unsigned long flags __attribute__ ((unused));110 111 netif_vdbg(efx, hw, efx->net_dev,112 "writing register %x with " EFX_OWORD_FMT "\n", reg,113 EFX_OWORD_VAL(*value));114 115 spin_lock_irqsave(&efx->biu_lock, flags);116#ifdef EFX_USE_QWORD_IO117 _efx_writeq(efx, value->u64[0], reg + 0);118 _efx_writeq(efx, value->u64[1], reg + 8);119#else120 _efx_writed(efx, value->u32[0], reg + 0);121 _efx_writed(efx, value->u32[1], reg + 4);122 _efx_writed(efx, value->u32[2], reg + 8);123 _efx_writed(efx, value->u32[3], reg + 12);124#endif125 spin_unlock_irqrestore(&efx->biu_lock, flags);126}127 128/* Write 64-bit SRAM through the supplied mapping, locking as appropriate. */129static inline void efx_sram_writeq(struct efx_nic *efx, void __iomem *membase,130 const efx_qword_t *value, unsigned int index)131{132 unsigned int addr = index * sizeof(*value);133 unsigned long flags __attribute__ ((unused));134 135 netif_vdbg(efx, hw, efx->net_dev,136 "writing SRAM address %x with " EFX_QWORD_FMT "\n",137 addr, EFX_QWORD_VAL(*value));138 139 spin_lock_irqsave(&efx->biu_lock, flags);140#ifdef EFX_USE_QWORD_IO141 __raw_writeq((__force u64)value->u64[0], membase + addr);142#else143 __raw_writel((__force u32)value->u32[0], membase + addr);144 __raw_writel((__force u32)value->u32[1], membase + addr + 4);145#endif146 spin_unlock_irqrestore(&efx->biu_lock, flags);147}148 149/* Write a 32-bit CSR or the last dword of a special 128-bit CSR */150static inline void efx_writed(struct efx_nic *efx, const efx_dword_t *value,151 unsigned int reg)152{153 netif_vdbg(efx, hw, efx->net_dev,154 "writing register %x with "EFX_DWORD_FMT"\n",155 reg, EFX_DWORD_VAL(*value));156 157 /* No lock required */158 _efx_writed(efx, value->u32[0], reg);159}160 161/* Read a 128-bit CSR, locking as appropriate. */162static inline void efx_reado(struct efx_nic *efx, efx_oword_t *value,163 unsigned int reg)164{165 unsigned long flags __attribute__ ((unused));166 167 spin_lock_irqsave(&efx->biu_lock, flags);168 value->u32[0] = _efx_readd(efx, reg + 0);169 value->u32[1] = _efx_readd(efx, reg + 4);170 value->u32[2] = _efx_readd(efx, reg + 8);171 value->u32[3] = _efx_readd(efx, reg + 12);172 spin_unlock_irqrestore(&efx->biu_lock, flags);173 174 netif_vdbg(efx, hw, efx->net_dev,175 "read from register %x, got " EFX_OWORD_FMT "\n", reg,176 EFX_OWORD_VAL(*value));177}178 179/* Read 64-bit SRAM through the supplied mapping, locking as appropriate. */180static inline void efx_sram_readq(struct efx_nic *efx, void __iomem *membase,181 efx_qword_t *value, unsigned int index)182{183 unsigned int addr = index * sizeof(*value);184 unsigned long flags __attribute__ ((unused));185 186 spin_lock_irqsave(&efx->biu_lock, flags);187#ifdef EFX_USE_QWORD_IO188 value->u64[0] = (__force __le64)__raw_readq(membase + addr);189#else190 value->u32[0] = (__force __le32)__raw_readl(membase + addr);191 value->u32[1] = (__force __le32)__raw_readl(membase + addr + 4);192#endif193 spin_unlock_irqrestore(&efx->biu_lock, flags);194 195 netif_vdbg(efx, hw, efx->net_dev,196 "read from SRAM address %x, got "EFX_QWORD_FMT"\n",197 addr, EFX_QWORD_VAL(*value));198}199 200/* Read a 32-bit CSR or SRAM */201static inline void efx_readd(struct efx_nic *efx, efx_dword_t *value,202 unsigned int reg)203{204 value->u32[0] = _efx_readd(efx, reg);205 netif_vdbg(efx, hw, efx->net_dev,206 "read from register %x, got "EFX_DWORD_FMT"\n",207 reg, EFX_DWORD_VAL(*value));208}209 210/* Write a 128-bit CSR forming part of a table */211static inline void212efx_writeo_table(struct efx_nic *efx, const efx_oword_t *value,213 unsigned int reg, unsigned int index)214{215 efx_writeo(efx, value, reg + index * sizeof(efx_oword_t));216}217 218/* Read a 128-bit CSR forming part of a table */219static inline void efx_reado_table(struct efx_nic *efx, efx_oword_t *value,220 unsigned int reg, unsigned int index)221{222 efx_reado(efx, value, reg + index * sizeof(efx_oword_t));223}224 225/* default VI stride (step between per-VI registers) is 8K on EF10 and226 * 64K on EF100227 */228#define EFX_DEFAULT_VI_STRIDE 0x2000229#define EF100_DEFAULT_VI_STRIDE 0x10000230 231/* Calculate offset to page-mapped register */232static inline unsigned int efx_paged_reg(struct efx_nic *efx, unsigned int page,233 unsigned int reg)234{235 return page * efx->vi_stride + reg;236}237 238/* Write the whole of RX_DESC_UPD or TX_DESC_UPD */239static inline void _efx_writeo_page(struct efx_nic *efx, efx_oword_t *value,240 unsigned int reg, unsigned int page)241{242 reg = efx_paged_reg(efx, page, reg);243 244 netif_vdbg(efx, hw, efx->net_dev,245 "writing register %x with " EFX_OWORD_FMT "\n", reg,246 EFX_OWORD_VAL(*value));247 248#ifdef EFX_USE_QWORD_IO249 _efx_writeq(efx, value->u64[0], reg + 0);250 _efx_writeq(efx, value->u64[1], reg + 8);251#else252 _efx_writed(efx, value->u32[0], reg + 0);253 _efx_writed(efx, value->u32[1], reg + 4);254 _efx_writed(efx, value->u32[2], reg + 8);255 _efx_writed(efx, value->u32[3], reg + 12);256#endif257}258#define efx_writeo_page(efx, value, reg, page) \259 _efx_writeo_page(efx, value, \260 reg + \261 BUILD_BUG_ON_ZERO((reg) != 0x830 && (reg) != 0xa10), \262 page)263 264/* Write a page-mapped 32-bit CSR (EVQ_RPTR, EVQ_TMR (EF10), or the265 * high bits of RX_DESC_UPD or TX_DESC_UPD)266 */267static inline void268_efx_writed_page(struct efx_nic *efx, const efx_dword_t *value,269 unsigned int reg, unsigned int page)270{271 efx_writed(efx, value, efx_paged_reg(efx, page, reg));272}273#define efx_writed_page(efx, value, reg, page) \274 _efx_writed_page(efx, value, \275 reg + \276 BUILD_BUG_ON_ZERO((reg) != 0x180 && \277 (reg) != 0x200 && \278 (reg) != 0x400 && \279 (reg) != 0x420 && \280 (reg) != 0x830 && \281 (reg) != 0x83c && \282 (reg) != 0xa18 && \283 (reg) != 0xa1c), \284 page)285 286/* Write TIMER_COMMAND. This is a page-mapped 32-bit CSR, but a bug287 * in the BIU means that writes to TIMER_COMMAND[0] invalidate the288 * collector register.289 */290static inline void _efx_writed_page_locked(struct efx_nic *efx,291 const efx_dword_t *value,292 unsigned int reg,293 unsigned int page)294{295 unsigned long flags __attribute__ ((unused));296 297 if (page == 0) {298 spin_lock_irqsave(&efx->biu_lock, flags);299 efx_writed(efx, value, efx_paged_reg(efx, page, reg));300 spin_unlock_irqrestore(&efx->biu_lock, flags);301 } else {302 efx_writed(efx, value, efx_paged_reg(efx, page, reg));303 }304}305#define efx_writed_page_locked(efx, value, reg, page) \306 _efx_writed_page_locked(efx, value, \307 reg + BUILD_BUG_ON_ZERO((reg) != 0x420), \308 page)309 310#endif /* EFX_IO_H */311