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1/* SPDX-License-Identifier: GPL-2.0-only */2/****************************************************************************3 * Driver for Solarflare network controllers and boards4 * Copyright 2009-2018 Solarflare Communications Inc.5 * Copyright 2019-2020 Xilinx Inc.6 */7 8 9#ifndef MCDI_PCOL_H10#define MCDI_PCOL_H11 12/* Values to be written into FMCR_CZ_RESET_STATE_REG to control boot. */13/* Power-on reset state */14#define MC_FW_STATE_POR (1)15/* If this is set in MC_RESET_STATE_REG then it should be16 * possible to jump into IMEM without loading code from flash. */17#define MC_FW_WARM_BOOT_OK (2)18/* The MC main image has started to boot. */19#define MC_FW_STATE_BOOTING (4)20/* The Scheduler has started. */21#define MC_FW_STATE_SCHED (8)22/* If this is set in MC_RESET_STATE_REG then it should be23 * possible to jump into IMEM without loading code from flash.24 * Unlike a warm boot, assume DMEM has been reloaded, so that25 * the MC persistent data must be reinitialised. */26#define MC_FW_TEPID_BOOT_OK (16)27/* We have entered the main firmware via recovery mode. This28 * means that MC persistent data must be reinitialised, but that29 * we shouldn't touch PCIe config. */30#define MC_FW_RECOVERY_MODE_PCIE_INIT_OK (32)31/* BIST state has been initialized */32#define MC_FW_BIST_INIT_OK (128)33 34/* Siena MC shared memmory offsets */35/* The 'doorbell' addresses are hard-wired to alert the MC when written */36#define MC_SMEM_P0_DOORBELL_OFST 0x00037#define MC_SMEM_P1_DOORBELL_OFST 0x00438/* The rest of these are firmware-defined */39#define MC_SMEM_P0_PDU_OFST 0x00840#define MC_SMEM_P1_PDU_OFST 0x10841#define MC_SMEM_PDU_LEN 0x10042#define MC_SMEM_P0_PTP_TIME_OFST 0x7f043#define MC_SMEM_P0_STATUS_OFST 0x7f844#define MC_SMEM_P1_STATUS_OFST 0x7fc45 46/* Values to be written to the per-port status dword in shared47 * memory on reboot and assert */48#define MC_STATUS_DWORD_REBOOT (0xb007b007)49#define MC_STATUS_DWORD_ASSERT (0xdeaddead)50 51/* Check whether an mcfw version (in host order) belongs to a bootloader */52#define MC_FW_VERSION_IS_BOOTLOADER(_v) (((_v) >> 16) == 0xb007)53 54/* The current version of the MCDI protocol.55 *56 * Note that the ROM burnt into the card only talks V0, so at the very57 * least every driver must support version 0 and MCDI_PCOL_VERSION58 */59#define MCDI_PCOL_VERSION 260 61/* Unused commands: 0x23, 0x27, 0x30, 0x31 */62 63/* MCDI version 164 *65 * Each MCDI request starts with an MCDI_HEADER, which is a 32bit66 * structure, filled in by the client.67 *68 * 0 7 8 16 20 22 23 24 3169 * | CODE | R | LEN | SEQ | Rsvd | E | R | XFLAGS |70 * | | |71 * | | \--- Response72 * | \------- Error73 * \------------------------------ Resync (always set)74 *75 * The client writes it's request into MC shared memory, and rings the76 * doorbell. Each request is completed by either by the MC writing77 * back into shared memory, or by writing out an event.78 *79 * All MCDI commands support completion by shared memory response. Each80 * request may also contain additional data (accounted for by HEADER.LEN),81 * and some response's may also contain additional data (again, accounted82 * for by HEADER.LEN).83 *84 * Some MCDI commands support completion by event, in which any associated85 * response data is included in the event.86 *87 * The protocol requires one response to be delivered for every request, a88 * request should not be sent unless the response for the previous request89 * has been received (either by polling shared memory, or by receiving90 * an event).91 */92 93/** Request/Response structure */94#define MCDI_HEADER_OFST 095#define MCDI_HEADER_CODE_LBN 096#define MCDI_HEADER_CODE_WIDTH 797#define MCDI_HEADER_RESYNC_LBN 798#define MCDI_HEADER_RESYNC_WIDTH 199#define MCDI_HEADER_DATALEN_LBN 8100#define MCDI_HEADER_DATALEN_WIDTH 8101#define MCDI_HEADER_SEQ_LBN 16102#define MCDI_HEADER_SEQ_WIDTH 4103#define MCDI_HEADER_RSVD_LBN 20104#define MCDI_HEADER_RSVD_WIDTH 1105#define MCDI_HEADER_NOT_EPOCH_LBN 21106#define MCDI_HEADER_NOT_EPOCH_WIDTH 1107#define MCDI_HEADER_ERROR_LBN 22108#define MCDI_HEADER_ERROR_WIDTH 1109#define MCDI_HEADER_RESPONSE_LBN 23110#define MCDI_HEADER_RESPONSE_WIDTH 1111#define MCDI_HEADER_XFLAGS_LBN 24112#define MCDI_HEADER_XFLAGS_WIDTH 8113/* Request response using event */114#define MCDI_HEADER_XFLAGS_EVREQ 0x01115/* Request (and signal) early doorbell return */116#define MCDI_HEADER_XFLAGS_DBRET 0x02117 118/* Maximum number of payload bytes */119#define MCDI_CTL_SDU_LEN_MAX_V1 0xfc120#define MCDI_CTL_SDU_LEN_MAX_V2 0x400121 122#define MCDI_CTL_SDU_LEN_MAX MCDI_CTL_SDU_LEN_MAX_V2123 124 125/* The MC can generate events for two reasons:126 * - To advance a shared memory request if XFLAGS_EVREQ was set127 * - As a notification (link state, i2c event), controlled128 * via MC_CMD_LOG_CTRL129 *130 * Both events share a common structure:131 *132 * 0 32 33 36 44 52 60133 * | Data | Cont | Level | Src | Code | Rsvd |134 * |135 * \ There is another event pending in this notification136 *137 * If Code==CMDDONE, then the fields are further interpreted as:138 *139 * - LEVEL==INFO Command succeeded140 * - LEVEL==ERR Command failed141 *142 * 0 8 16 24 32143 * | Seq | Datalen | Errno | Rsvd |144 *145 * These fields are taken directly out of the standard MCDI header, i.e.,146 * LEVEL==ERR, Datalen == 0 => Reboot147 *148 * Events can be squirted out of the UART (using LOG_CTRL) without a149 * MCDI header. An event can be distinguished from a MCDI response by150 * examining the first byte which is 0xc0. This corresponds to the151 * non-existent MCDI command MC_CMD_DEBUG_LOG.152 *153 * 0 7 8154 * | command | Resync | = 0xc0155 *156 * Since the event is written in big-endian byte order, this works157 * providing bits 56-63 of the event are 0xc0.158 *159 * 56 60 63160 * | Rsvd | Code | = 0xc0161 *162 * Which means for convenience the event code is 0xc for all MC163 * generated events.164 */165#define FSE_AZ_EV_CODE_MCDI_EVRESPONSE 0xc166 167 168/* Operation not permitted. */169#define MC_CMD_ERR_EPERM 1170/* Non-existent command target */171#define MC_CMD_ERR_ENOENT 2172/* assert() has killed the MC */173#define MC_CMD_ERR_EINTR 4174/* I/O failure */175#define MC_CMD_ERR_EIO 5176/* Already exists */177#define MC_CMD_ERR_EEXIST 6178/* Try again */179#define MC_CMD_ERR_EAGAIN 11180/* Out of memory */181#define MC_CMD_ERR_ENOMEM 12182/* Caller does not hold required locks */183#define MC_CMD_ERR_EACCES 13184/* Resource is currently unavailable (e.g. lock contention) */185#define MC_CMD_ERR_EBUSY 16186/* No such device */187#define MC_CMD_ERR_ENODEV 19188/* Invalid argument to target */189#define MC_CMD_ERR_EINVAL 22190/* Broken pipe */191#define MC_CMD_ERR_EPIPE 32192/* Read-only */193#define MC_CMD_ERR_EROFS 30194/* Out of range */195#define MC_CMD_ERR_ERANGE 34196/* Non-recursive resource is already acquired */197#define MC_CMD_ERR_EDEADLK 35198/* Operation not implemented */199#define MC_CMD_ERR_ENOSYS 38200/* Operation timed out */201#define MC_CMD_ERR_ETIME 62202/* Link has been severed */203#define MC_CMD_ERR_ENOLINK 67204/* Protocol error */205#define MC_CMD_ERR_EPROTO 71206/* Operation not supported */207#define MC_CMD_ERR_ENOTSUP 95208/* Address not available */209#define MC_CMD_ERR_EADDRNOTAVAIL 99210/* Not connected */211#define MC_CMD_ERR_ENOTCONN 107212/* Operation already in progress */213#define MC_CMD_ERR_EALREADY 114214 215/* Resource allocation failed. */216#define MC_CMD_ERR_ALLOC_FAIL 0x1000217/* V-adaptor not found. */218#define MC_CMD_ERR_NO_VADAPTOR 0x1001219/* EVB port not found. */220#define MC_CMD_ERR_NO_EVB_PORT 0x1002221/* V-switch not found. */222#define MC_CMD_ERR_NO_VSWITCH 0x1003223/* Too many VLAN tags. */224#define MC_CMD_ERR_VLAN_LIMIT 0x1004225/* Bad PCI function number. */226#define MC_CMD_ERR_BAD_PCI_FUNC 0x1005227/* Invalid VLAN mode. */228#define MC_CMD_ERR_BAD_VLAN_MODE 0x1006229/* Invalid v-switch type. */230#define MC_CMD_ERR_BAD_VSWITCH_TYPE 0x1007231/* Invalid v-port type. */232#define MC_CMD_ERR_BAD_VPORT_TYPE 0x1008233/* MAC address exists. */234#define MC_CMD_ERR_MAC_EXIST 0x1009235/* Slave core not present */236#define MC_CMD_ERR_SLAVE_NOT_PRESENT 0x100a237/* The datapath is disabled. */238#define MC_CMD_ERR_DATAPATH_DISABLED 0x100b239/* The requesting client is not a function */240#define MC_CMD_ERR_CLIENT_NOT_FN 0x100c241/* The requested operation might require the242 command to be passed between MCs, and the243 transport doesn't support that. Should244 only ever been seen over the UART. */245#define MC_CMD_ERR_TRANSPORT_NOPROXY 0x100d246/* VLAN tag(s) exists */247#define MC_CMD_ERR_VLAN_EXIST 0x100e248/* No MAC address assigned to an EVB port */249#define MC_CMD_ERR_NO_MAC_ADDR 0x100f250/* Notifies the driver that the request has been relayed251 * to an admin function for authorization. The driver should252 * wait for a PROXY_RESPONSE event and then resend its request.253 * This error code is followed by a 32-bit handle that254 * helps matching it with the respective PROXY_RESPONSE event. */255#define MC_CMD_ERR_PROXY_PENDING 0x1010256#define MC_CMD_ERR_PROXY_PENDING_HANDLE_OFST 4257/* The request cannot be passed for authorization because258 * another request from the same function is currently being259 * authorized. The drvier should try again later. */260#define MC_CMD_ERR_PROXY_INPROGRESS 0x1011261/* Returned by MC_CMD_PROXY_COMPLETE if the caller is not the function262 * that has enabled proxying or BLOCK_INDEX points to a function that263 * doesn't await an authorization. */264#define MC_CMD_ERR_PROXY_UNEXPECTED 0x1012265/* This code is currently only used internally in FW. Its meaning is that266 * an operation failed due to lack of SR-IOV privilege.267 * Normally it is translated to EPERM by send_cmd_err(),268 * but it may also be used to trigger some special mechanism269 * for handling such case, e.g. to relay the failed request270 * to a designated admin function for authorization. */271#define MC_CMD_ERR_NO_PRIVILEGE 0x1013272/* Workaround 26807 could not be turned on/off because some functions273 * have already installed filters. See the comment at274 * MC_CMD_WORKAROUND_BUG26807.275 * May also returned for other operations such as sub-variant switching. */276#define MC_CMD_ERR_FILTERS_PRESENT 0x1014277/* The clock whose frequency you've attempted to set278 * doesn't exist on this NIC */279#define MC_CMD_ERR_NO_CLOCK 0x1015280/* Returned by MC_CMD_TESTASSERT if the action that should281 * have caused an assertion failed to do so. */282#define MC_CMD_ERR_UNREACHABLE 0x1016283/* This command needs to be processed in the background but there were no284 * resources to do so. Send it again after a command has completed. */285#define MC_CMD_ERR_QUEUE_FULL 0x1017286/* The operation could not be completed because the PCIe link has gone287 * away. This error code is never expected to be returned over the TLP288 * transport. */289#define MC_CMD_ERR_NO_PCIE 0x1018290/* The operation could not be completed because the datapath has gone291 * away. This is distinct from MC_CMD_ERR_DATAPATH_DISABLED in that the292 * datapath absence may be temporary*/293#define MC_CMD_ERR_NO_DATAPATH 0x1019294/* The operation could not complete because some VIs are allocated */295#define MC_CMD_ERR_VIS_PRESENT 0x101a296/* The operation could not complete because some PIO buffers are allocated */297#define MC_CMD_ERR_PIOBUFS_PRESENT 0x101b298 299#define MC_CMD_ERR_CODE_OFST 0300 301/* We define 8 "escape" commands to allow302 for command number space extension */303 304#define MC_CMD_CMD_SPACE_ESCAPE_0 0x78305#define MC_CMD_CMD_SPACE_ESCAPE_1 0x79306#define MC_CMD_CMD_SPACE_ESCAPE_2 0x7A307#define MC_CMD_CMD_SPACE_ESCAPE_3 0x7B308#define MC_CMD_CMD_SPACE_ESCAPE_4 0x7C309#define MC_CMD_CMD_SPACE_ESCAPE_5 0x7D310#define MC_CMD_CMD_SPACE_ESCAPE_6 0x7E311#define MC_CMD_CMD_SPACE_ESCAPE_7 0x7F312 313/* Vectors in the boot ROM */314/* Point to the copycode entry point. */315#define SIENA_MC_BOOTROM_COPYCODE_VEC (0x800 - 3 * 0x4)316#define HUNT_MC_BOOTROM_COPYCODE_VEC (0x8000 - 3 * 0x4)317#define MEDFORD_MC_BOOTROM_COPYCODE_VEC (0x10000 - 3 * 0x4)318/* Points to the recovery mode entry point. Misnamed but kept for compatibility. */319#define SIENA_MC_BOOTROM_NOFLASH_VEC (0x800 - 2 * 0x4)320#define HUNT_MC_BOOTROM_NOFLASH_VEC (0x8000 - 2 * 0x4)321#define MEDFORD_MC_BOOTROM_NOFLASH_VEC (0x10000 - 2 * 0x4)322/* Points to the recovery mode entry point. Same as above, but the right name. */323#define SIENA_MC_BOOTROM_RECOVERY_VEC (0x800 - 2 * 0x4)324#define HUNT_MC_BOOTROM_RECOVERY_VEC (0x8000 - 2 * 0x4)325#define MEDFORD_MC_BOOTROM_RECOVERY_VEC (0x10000 - 2 * 0x4)326 327/* Points to noflash mode entry point. */328#define MEDFORD_MC_BOOTROM_REAL_NOFLASH_VEC (0x10000 - 4 * 0x4)329 330/* The command set exported by the boot ROM (MCDI v0) */331#define MC_CMD_GET_VERSION_V0_SUPPORTED_FUNCS { \332 (1 << MC_CMD_READ32) | \333 (1 << MC_CMD_WRITE32) | \334 (1 << MC_CMD_COPYCODE) | \335 (1 << MC_CMD_GET_VERSION), \336 0, 0, 0 }337 338#define MC_CMD_SENSOR_INFO_OUT_OFFSET_OFST(_x) \339 (MC_CMD_SENSOR_ENTRY_OFST + (_x))340 341#define MC_CMD_DBI_WRITE_IN_ADDRESS_OFST(n) \342 (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST + \343 MC_CMD_DBIWROP_TYPEDEF_ADDRESS_OFST + \344 (n) * MC_CMD_DBIWROP_TYPEDEF_LEN)345 346#define MC_CMD_DBI_WRITE_IN_BYTE_MASK_OFST(n) \347 (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST + \348 MC_CMD_DBIWROP_TYPEDEF_BYTE_MASK_OFST + \349 (n) * MC_CMD_DBIWROP_TYPEDEF_LEN)350 351#define MC_CMD_DBI_WRITE_IN_VALUE_OFST(n) \352 (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST + \353 MC_CMD_DBIWROP_TYPEDEF_VALUE_OFST + \354 (n) * MC_CMD_DBIWROP_TYPEDEF_LEN)355 356/* This may be ORed with an EVB_PORT_ID_xxx constant to pass a non-default357 * stack ID (which must be in the range 1-255) along with an EVB port ID.358 */359#define EVB_STACK_ID(n) (((n) & 0xff) << 16)360 361 362/* Version 2 adds an optional argument to error returns: the errno value363 * may be followed by the (0-based) number of the first argument that364 * could not be processed.365 */366#define MC_CMD_ERR_ARG_OFST 4367 368/* No space */369#define MC_CMD_ERR_ENOSPC 28370 371/* MCDI_EVENT structuredef */372#define MCDI_EVENT_LEN 8373#define MCDI_EVENT_CONT_LBN 32374#define MCDI_EVENT_CONT_WIDTH 1375#define MCDI_EVENT_LEVEL_LBN 33376#define MCDI_EVENT_LEVEL_WIDTH 3377/* enum: Info. */378#define MCDI_EVENT_LEVEL_INFO 0x0379/* enum: Warning. */380#define MCDI_EVENT_LEVEL_WARN 0x1381/* enum: Error. */382#define MCDI_EVENT_LEVEL_ERR 0x2383/* enum: Fatal. */384#define MCDI_EVENT_LEVEL_FATAL 0x3385#define MCDI_EVENT_DATA_OFST 0386#define MCDI_EVENT_DATA_LEN 4387#define MCDI_EVENT_CMDDONE_SEQ_OFST 0388#define MCDI_EVENT_CMDDONE_SEQ_LBN 0389#define MCDI_EVENT_CMDDONE_SEQ_WIDTH 8390#define MCDI_EVENT_CMDDONE_DATALEN_OFST 0391#define MCDI_EVENT_CMDDONE_DATALEN_LBN 8392#define MCDI_EVENT_CMDDONE_DATALEN_WIDTH 8393#define MCDI_EVENT_CMDDONE_ERRNO_OFST 0394#define MCDI_EVENT_CMDDONE_ERRNO_LBN 16395#define MCDI_EVENT_CMDDONE_ERRNO_WIDTH 8396#define MCDI_EVENT_LINKCHANGE_LP_CAP_OFST 0397#define MCDI_EVENT_LINKCHANGE_LP_CAP_LBN 0398#define MCDI_EVENT_LINKCHANGE_LP_CAP_WIDTH 16399#define MCDI_EVENT_LINKCHANGE_SPEED_OFST 0400#define MCDI_EVENT_LINKCHANGE_SPEED_LBN 16401#define MCDI_EVENT_LINKCHANGE_SPEED_WIDTH 4402/* enum: Link is down or link speed could not be determined */403#define MCDI_EVENT_LINKCHANGE_SPEED_UNKNOWN 0x0404/* enum: 100Mbs */405#define MCDI_EVENT_LINKCHANGE_SPEED_100M 0x1406/* enum: 1Gbs */407#define MCDI_EVENT_LINKCHANGE_SPEED_1G 0x2408/* enum: 10Gbs */409#define MCDI_EVENT_LINKCHANGE_SPEED_10G 0x3410/* enum: 40Gbs */411#define MCDI_EVENT_LINKCHANGE_SPEED_40G 0x4412/* enum: 25Gbs */413#define MCDI_EVENT_LINKCHANGE_SPEED_25G 0x5414/* enum: 50Gbs */415#define MCDI_EVENT_LINKCHANGE_SPEED_50G 0x6416/* enum: 100Gbs */417#define MCDI_EVENT_LINKCHANGE_SPEED_100G 0x7418#define MCDI_EVENT_LINKCHANGE_FCNTL_OFST 0419#define MCDI_EVENT_LINKCHANGE_FCNTL_LBN 20420#define MCDI_EVENT_LINKCHANGE_FCNTL_WIDTH 4421#define MCDI_EVENT_LINKCHANGE_LINK_FLAGS_OFST 0422#define MCDI_EVENT_LINKCHANGE_LINK_FLAGS_LBN 24423#define MCDI_EVENT_LINKCHANGE_LINK_FLAGS_WIDTH 8424#define MCDI_EVENT_SENSOREVT_MONITOR_OFST 0425#define MCDI_EVENT_SENSOREVT_MONITOR_LBN 0426#define MCDI_EVENT_SENSOREVT_MONITOR_WIDTH 8427#define MCDI_EVENT_SENSOREVT_STATE_OFST 0428#define MCDI_EVENT_SENSOREVT_STATE_LBN 8429#define MCDI_EVENT_SENSOREVT_STATE_WIDTH 8430#define MCDI_EVENT_SENSOREVT_VALUE_OFST 0431#define MCDI_EVENT_SENSOREVT_VALUE_LBN 16432#define MCDI_EVENT_SENSOREVT_VALUE_WIDTH 16433#define MCDI_EVENT_FWALERT_DATA_OFST 0434#define MCDI_EVENT_FWALERT_DATA_LBN 8435#define MCDI_EVENT_FWALERT_DATA_WIDTH 24436#define MCDI_EVENT_FWALERT_REASON_OFST 0437#define MCDI_EVENT_FWALERT_REASON_LBN 0438#define MCDI_EVENT_FWALERT_REASON_WIDTH 8439/* enum: SRAM Access. */440#define MCDI_EVENT_FWALERT_REASON_SRAM_ACCESS 0x1441#define MCDI_EVENT_FLR_VF_OFST 0442#define MCDI_EVENT_FLR_VF_LBN 0443#define MCDI_EVENT_FLR_VF_WIDTH 8444#define MCDI_EVENT_TX_ERR_TXQ_OFST 0445#define MCDI_EVENT_TX_ERR_TXQ_LBN 0446#define MCDI_EVENT_TX_ERR_TXQ_WIDTH 12447#define MCDI_EVENT_TX_ERR_TYPE_OFST 0448#define MCDI_EVENT_TX_ERR_TYPE_LBN 12449#define MCDI_EVENT_TX_ERR_TYPE_WIDTH 4450/* enum: Descriptor loader reported failure */451#define MCDI_EVENT_TX_ERR_DL_FAIL 0x1452/* enum: Descriptor ring empty and no EOP seen for packet */453#define MCDI_EVENT_TX_ERR_NO_EOP 0x2454/* enum: Overlength packet */455#define MCDI_EVENT_TX_ERR_2BIG 0x3456/* enum: Malformed option descriptor */457#define MCDI_EVENT_TX_BAD_OPTDESC 0x5458/* enum: Option descriptor part way through a packet */459#define MCDI_EVENT_TX_OPT_IN_PKT 0x8460/* enum: DMA or PIO data access error */461#define MCDI_EVENT_TX_ERR_BAD_DMA_OR_PIO 0x9462#define MCDI_EVENT_TX_ERR_INFO_OFST 0463#define MCDI_EVENT_TX_ERR_INFO_LBN 16464#define MCDI_EVENT_TX_ERR_INFO_WIDTH 16465#define MCDI_EVENT_TX_FLUSH_TO_DRIVER_OFST 0466#define MCDI_EVENT_TX_FLUSH_TO_DRIVER_LBN 12467#define MCDI_EVENT_TX_FLUSH_TO_DRIVER_WIDTH 1468#define MCDI_EVENT_TX_FLUSH_TXQ_OFST 0469#define MCDI_EVENT_TX_FLUSH_TXQ_LBN 0470#define MCDI_EVENT_TX_FLUSH_TXQ_WIDTH 12471#define MCDI_EVENT_PTP_ERR_TYPE_OFST 0472#define MCDI_EVENT_PTP_ERR_TYPE_LBN 0473#define MCDI_EVENT_PTP_ERR_TYPE_WIDTH 8474/* enum: PLL lost lock */475#define MCDI_EVENT_PTP_ERR_PLL_LOST 0x1476/* enum: Filter overflow (PDMA) */477#define MCDI_EVENT_PTP_ERR_FILTER 0x2478/* enum: FIFO overflow (FPGA) */479#define MCDI_EVENT_PTP_ERR_FIFO 0x3480/* enum: Merge queue overflow */481#define MCDI_EVENT_PTP_ERR_QUEUE 0x4482#define MCDI_EVENT_AOE_ERR_TYPE_OFST 0483#define MCDI_EVENT_AOE_ERR_TYPE_LBN 0484#define MCDI_EVENT_AOE_ERR_TYPE_WIDTH 8485/* enum: AOE failed to load - no valid image? */486#define MCDI_EVENT_AOE_NO_LOAD 0x1487/* enum: AOE FC reported an exception */488#define MCDI_EVENT_AOE_FC_ASSERT 0x2489/* enum: AOE FC watchdogged */490#define MCDI_EVENT_AOE_FC_WATCHDOG 0x3491/* enum: AOE FC failed to start */492#define MCDI_EVENT_AOE_FC_NO_START 0x4493/* enum: Generic AOE fault - likely to have been reported via other means too494 * but intended for use by aoex driver.495 */496#define MCDI_EVENT_AOE_FAULT 0x5497/* enum: Results of reprogramming the CPLD (status in AOE_ERR_DATA) */498#define MCDI_EVENT_AOE_CPLD_REPROGRAMMED 0x6499/* enum: AOE loaded successfully */500#define MCDI_EVENT_AOE_LOAD 0x7501/* enum: AOE DMA operation completed (LSB of HOST_HANDLE in AOE_ERR_DATA) */502#define MCDI_EVENT_AOE_DMA 0x8503/* enum: AOE byteblaster connected/disconnected (Connection status in504 * AOE_ERR_DATA)505 */506#define MCDI_EVENT_AOE_BYTEBLASTER 0x9507/* enum: DDR ECC status update */508#define MCDI_EVENT_AOE_DDR_ECC_STATUS 0xa509/* enum: PTP status update */510#define MCDI_EVENT_AOE_PTP_STATUS 0xb511/* enum: FPGA header incorrect */512#define MCDI_EVENT_AOE_FPGA_LOAD_HEADER_ERR 0xc513/* enum: FPGA Powered Off due to error in powering up FPGA */514#define MCDI_EVENT_AOE_FPGA_POWER_OFF 0xd515/* enum: AOE FPGA load failed due to MC to MUM communication failure */516#define MCDI_EVENT_AOE_FPGA_LOAD_FAILED 0xe517/* enum: Notify that invalid flash type detected */518#define MCDI_EVENT_AOE_INVALID_FPGA_FLASH_TYPE 0xf519/* enum: Notify that the attempt to run FPGA Controller firmware timedout */520#define MCDI_EVENT_AOE_FC_RUN_TIMEDOUT 0x10521/* enum: Failure to probe one or more FPGA boot flash chips */522#define MCDI_EVENT_AOE_FPGA_BOOT_FLASH_INVALID 0x11523/* enum: FPGA boot-flash contains an invalid image header */524#define MCDI_EVENT_AOE_FPGA_BOOT_FLASH_HDR_INVALID 0x12525/* enum: Failed to program clocks required by the FPGA */526#define MCDI_EVENT_AOE_FPGA_CLOCKS_PROGRAM_FAILED 0x13527/* enum: Notify that FPGA Controller is alive to serve MCDI requests */528#define MCDI_EVENT_AOE_FC_RUNNING 0x14529#define MCDI_EVENT_AOE_ERR_DATA_OFST 0530#define MCDI_EVENT_AOE_ERR_DATA_LBN 8531#define MCDI_EVENT_AOE_ERR_DATA_WIDTH 8532#define MCDI_EVENT_AOE_ERR_FC_ASSERT_INFO_OFST 0533#define MCDI_EVENT_AOE_ERR_FC_ASSERT_INFO_LBN 8534#define MCDI_EVENT_AOE_ERR_FC_ASSERT_INFO_WIDTH 8535/* enum: FC Assert happened, but the register information is not available */536#define MCDI_EVENT_AOE_ERR_FC_ASSERT_SEEN 0x0537/* enum: The register information for FC Assert is ready for readinng by driver538 */539#define MCDI_EVENT_AOE_ERR_FC_ASSERT_DATA_READY 0x1540#define MCDI_EVENT_AOE_ERR_CODE_FPGA_HEADER_VERIFY_FAILED_OFST 0541#define MCDI_EVENT_AOE_ERR_CODE_FPGA_HEADER_VERIFY_FAILED_LBN 8542#define MCDI_EVENT_AOE_ERR_CODE_FPGA_HEADER_VERIFY_FAILED_WIDTH 8543/* enum: Reading from NV failed */544#define MCDI_EVENT_AOE_ERR_FPGA_HEADER_NV_READ_FAIL 0x0545/* enum: Invalid Magic Number if FPGA header */546#define MCDI_EVENT_AOE_ERR_FPGA_HEADER_MAGIC_FAIL 0x1547/* enum: Invalid Silicon type detected in header */548#define MCDI_EVENT_AOE_ERR_FPGA_HEADER_SILICON_TYPE 0x2549/* enum: Unsupported VRatio */550#define MCDI_EVENT_AOE_ERR_FPGA_HEADER_VRATIO 0x3551/* enum: Unsupported DDR Type */552#define MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_TYPE 0x4553/* enum: DDR Voltage out of supported range */554#define MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_VOLTAGE 0x5555/* enum: Unsupported DDR speed */556#define MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_SPEED 0x6557/* enum: Unsupported DDR size */558#define MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_SIZE 0x7559/* enum: Unsupported DDR rank */560#define MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_RANK 0x8561#define MCDI_EVENT_AOE_ERR_CODE_INVALID_FPGA_FLASH_TYPE_INFO_OFST 0562#define MCDI_EVENT_AOE_ERR_CODE_INVALID_FPGA_FLASH_TYPE_INFO_LBN 8563#define MCDI_EVENT_AOE_ERR_CODE_INVALID_FPGA_FLASH_TYPE_INFO_WIDTH 8564/* enum: Primary boot flash */565#define MCDI_EVENT_AOE_FLASH_TYPE_BOOT_PRIMARY 0x0566/* enum: Secondary boot flash */567#define MCDI_EVENT_AOE_FLASH_TYPE_BOOT_SECONDARY 0x1568#define MCDI_EVENT_AOE_ERR_CODE_FPGA_POWER_OFF_OFST 0569#define MCDI_EVENT_AOE_ERR_CODE_FPGA_POWER_OFF_LBN 8570#define MCDI_EVENT_AOE_ERR_CODE_FPGA_POWER_OFF_WIDTH 8571#define MCDI_EVENT_AOE_ERR_CODE_FPGA_LOAD_FAILED_OFST 0572#define MCDI_EVENT_AOE_ERR_CODE_FPGA_LOAD_FAILED_LBN 8573#define MCDI_EVENT_AOE_ERR_CODE_FPGA_LOAD_FAILED_WIDTH 8574#define MCDI_EVENT_RX_ERR_RXQ_OFST 0575#define MCDI_EVENT_RX_ERR_RXQ_LBN 0576#define MCDI_EVENT_RX_ERR_RXQ_WIDTH 12577#define MCDI_EVENT_RX_ERR_TYPE_OFST 0578#define MCDI_EVENT_RX_ERR_TYPE_LBN 12579#define MCDI_EVENT_RX_ERR_TYPE_WIDTH 4580#define MCDI_EVENT_RX_ERR_INFO_OFST 0581#define MCDI_EVENT_RX_ERR_INFO_LBN 16582#define MCDI_EVENT_RX_ERR_INFO_WIDTH 16583#define MCDI_EVENT_RX_FLUSH_TO_DRIVER_OFST 0584#define MCDI_EVENT_RX_FLUSH_TO_DRIVER_LBN 12585#define MCDI_EVENT_RX_FLUSH_TO_DRIVER_WIDTH 1586#define MCDI_EVENT_RX_FLUSH_RXQ_OFST 0587#define MCDI_EVENT_RX_FLUSH_RXQ_LBN 0588#define MCDI_EVENT_RX_FLUSH_RXQ_WIDTH 12589#define MCDI_EVENT_MC_REBOOT_COUNT_OFST 0590#define MCDI_EVENT_MC_REBOOT_COUNT_LBN 0591#define MCDI_EVENT_MC_REBOOT_COUNT_WIDTH 16592#define MCDI_EVENT_MUM_ERR_TYPE_OFST 0593#define MCDI_EVENT_MUM_ERR_TYPE_LBN 0594#define MCDI_EVENT_MUM_ERR_TYPE_WIDTH 8595/* enum: MUM failed to load - no valid image? */596#define MCDI_EVENT_MUM_NO_LOAD 0x1597/* enum: MUM f/w reported an exception */598#define MCDI_EVENT_MUM_ASSERT 0x2599/* enum: MUM not kicking watchdog */600#define MCDI_EVENT_MUM_WATCHDOG 0x3601#define MCDI_EVENT_MUM_ERR_DATA_OFST 0602#define MCDI_EVENT_MUM_ERR_DATA_LBN 8603#define MCDI_EVENT_MUM_ERR_DATA_WIDTH 8604#define MCDI_EVENT_DBRET_SEQ_OFST 0605#define MCDI_EVENT_DBRET_SEQ_LBN 0606#define MCDI_EVENT_DBRET_SEQ_WIDTH 8607#define MCDI_EVENT_SUC_ERR_TYPE_OFST 0608#define MCDI_EVENT_SUC_ERR_TYPE_LBN 0609#define MCDI_EVENT_SUC_ERR_TYPE_WIDTH 8610/* enum: Corrupted or bad SUC application. */611#define MCDI_EVENT_SUC_BAD_APP 0x1612/* enum: SUC application reported an assert. */613#define MCDI_EVENT_SUC_ASSERT 0x2614/* enum: SUC application reported an exception. */615#define MCDI_EVENT_SUC_EXCEPTION 0x3616/* enum: SUC watchdog timer expired. */617#define MCDI_EVENT_SUC_WATCHDOG 0x4618#define MCDI_EVENT_SUC_ERR_ADDRESS_OFST 0619#define MCDI_EVENT_SUC_ERR_ADDRESS_LBN 8620#define MCDI_EVENT_SUC_ERR_ADDRESS_WIDTH 24621#define MCDI_EVENT_SUC_ERR_DATA_OFST 0622#define MCDI_EVENT_SUC_ERR_DATA_LBN 8623#define MCDI_EVENT_SUC_ERR_DATA_WIDTH 24624#define MCDI_EVENT_LINKCHANGE_V2_LP_CAP_OFST 0625#define MCDI_EVENT_LINKCHANGE_V2_LP_CAP_LBN 0626#define MCDI_EVENT_LINKCHANGE_V2_LP_CAP_WIDTH 24627#define MCDI_EVENT_LINKCHANGE_V2_SPEED_OFST 0628#define MCDI_EVENT_LINKCHANGE_V2_SPEED_LBN 24629#define MCDI_EVENT_LINKCHANGE_V2_SPEED_WIDTH 4630/* Enum values, see field(s): */631/* MCDI_EVENT/LINKCHANGE_SPEED */632#define MCDI_EVENT_LINKCHANGE_V2_FLAGS_LINK_UP_OFST 0633#define MCDI_EVENT_LINKCHANGE_V2_FLAGS_LINK_UP_LBN 28634#define MCDI_EVENT_LINKCHANGE_V2_FLAGS_LINK_UP_WIDTH 1635#define MCDI_EVENT_LINKCHANGE_V2_FCNTL_OFST 0636#define MCDI_EVENT_LINKCHANGE_V2_FCNTL_LBN 29637#define MCDI_EVENT_LINKCHANGE_V2_FCNTL_WIDTH 3638/* Enum values, see field(s): */639/* MC_CMD_SET_MAC/MC_CMD_SET_MAC_IN/FCNTL */640#define MCDI_EVENT_MODULECHANGE_LD_CAP_OFST 0641#define MCDI_EVENT_MODULECHANGE_LD_CAP_LBN 0642#define MCDI_EVENT_MODULECHANGE_LD_CAP_WIDTH 30643#define MCDI_EVENT_MODULECHANGE_SEQ_OFST 0644#define MCDI_EVENT_MODULECHANGE_SEQ_LBN 30645#define MCDI_EVENT_MODULECHANGE_SEQ_WIDTH 2646#define MCDI_EVENT_DATA_LBN 0647#define MCDI_EVENT_DATA_WIDTH 32648/* Alias for PTP_DATA. */649#define MCDI_EVENT_SRC_LBN 36650#define MCDI_EVENT_SRC_WIDTH 8651/* Data associated with PTP events which doesn't fit into the main DATA field652 */653#define MCDI_EVENT_PTP_DATA_LBN 36654#define MCDI_EVENT_PTP_DATA_WIDTH 8655/* EF100 specific. Defined by QDMA. The phase bit, changes each time round the656 * event ring657 */658#define MCDI_EVENT_EV_EVQ_PHASE_LBN 59659#define MCDI_EVENT_EV_EVQ_PHASE_WIDTH 1660#define MCDI_EVENT_EV_CODE_LBN 60661#define MCDI_EVENT_EV_CODE_WIDTH 4662#define MCDI_EVENT_CODE_LBN 44663#define MCDI_EVENT_CODE_WIDTH 8664/* enum: Event generated by host software */665#define MCDI_EVENT_SW_EVENT 0x0666/* enum: Bad assert. */667#define MCDI_EVENT_CODE_BADSSERT 0x1668/* enum: PM Notice. */669#define MCDI_EVENT_CODE_PMNOTICE 0x2670/* enum: Command done. */671#define MCDI_EVENT_CODE_CMDDONE 0x3672/* enum: Link change. */673#define MCDI_EVENT_CODE_LINKCHANGE 0x4674/* enum: Sensor Event. */675#define MCDI_EVENT_CODE_SENSOREVT 0x5676/* enum: Schedule error. */677#define MCDI_EVENT_CODE_SCHEDERR 0x6678/* enum: Reboot. */679#define MCDI_EVENT_CODE_REBOOT 0x7680/* enum: Mac stats DMA. */681#define MCDI_EVENT_CODE_MAC_STATS_DMA 0x8682/* enum: Firmware alert. */683#define MCDI_EVENT_CODE_FWALERT 0x9684/* enum: Function level reset. */685#define MCDI_EVENT_CODE_FLR 0xa686/* enum: Transmit error */687#define MCDI_EVENT_CODE_TX_ERR 0xb688/* enum: Tx flush has completed */689#define MCDI_EVENT_CODE_TX_FLUSH 0xc690/* enum: PTP packet received timestamp */691#define MCDI_EVENT_CODE_PTP_RX 0xd692/* enum: PTP NIC failure */693#define MCDI_EVENT_CODE_PTP_FAULT 0xe694/* enum: PTP PPS event */695#define MCDI_EVENT_CODE_PTP_PPS 0xf696/* enum: Rx flush has completed */697#define MCDI_EVENT_CODE_RX_FLUSH 0x10698/* enum: Receive error */699#define MCDI_EVENT_CODE_RX_ERR 0x11700/* enum: AOE fault */701#define MCDI_EVENT_CODE_AOE 0x12702/* enum: Network port calibration failed (VCAL). */703#define MCDI_EVENT_CODE_VCAL_FAIL 0x13704/* enum: HW PPS event */705#define MCDI_EVENT_CODE_HW_PPS 0x14706/* enum: The MC has rebooted (huntington and later, siena uses CODE_REBOOT and707 * a different format)708 */709#define MCDI_EVENT_CODE_MC_REBOOT 0x15710/* enum: the MC has detected a parity error */711#define MCDI_EVENT_CODE_PAR_ERR 0x16712/* enum: the MC has detected a correctable error */713#define MCDI_EVENT_CODE_ECC_CORR_ERR 0x17714/* enum: the MC has detected an uncorrectable error */715#define MCDI_EVENT_CODE_ECC_FATAL_ERR 0x18716/* enum: The MC has entered offline BIST mode */717#define MCDI_EVENT_CODE_MC_BIST 0x19718/* enum: PTP tick event providing current NIC time */719#define MCDI_EVENT_CODE_PTP_TIME 0x1a720/* enum: MUM fault */721#define MCDI_EVENT_CODE_MUM 0x1b722/* enum: notify the designated PF of a new authorization request */723#define MCDI_EVENT_CODE_PROXY_REQUEST 0x1c724/* enum: notify a function that awaits an authorization that its request has725 * been processed and it may now resend the command726 */727#define MCDI_EVENT_CODE_PROXY_RESPONSE 0x1d728/* enum: MCDI command accepted. New commands can be issued but this command is729 * not done yet.730 */731#define MCDI_EVENT_CODE_DBRET 0x1e732/* enum: The MC has detected a fault on the SUC */733#define MCDI_EVENT_CODE_SUC 0x1f734/* enum: Link change. This event is sent instead of LINKCHANGE if735 * WANT_V2_LINKCHANGES was set on driver attach.736 */737#define MCDI_EVENT_CODE_LINKCHANGE_V2 0x20738/* enum: This event is sent if WANT_V2_LINKCHANGES was set on driver attach739 * when the local device capabilities changes. This will usually correspond to740 * a module change.741 */742#define MCDI_EVENT_CODE_MODULECHANGE 0x21743/* enum: Notification that the sensors have been added and/or removed from the744 * sensor table. This event includes the new sensor table generation count, if745 * this does not match the driver's local copy it is expected to call746 * DYNAMIC_SENSORS_LIST to refresh it.747 */748#define MCDI_EVENT_CODE_DYNAMIC_SENSORS_CHANGE 0x22749/* enum: Notification that a sensor has changed state as a result of a reading750 * crossing a threshold. This is sent as two events, the first event contains751 * the handle and the sensor's state (in the SRC field), and the second752 * contains the value.753 */754#define MCDI_EVENT_CODE_DYNAMIC_SENSORS_STATE_CHANGE 0x23755/* enum: Notification that a descriptor proxy function configuration has been756 * pushed to "live" status (visible to host). SRC field contains the handle of757 * the affected descriptor proxy function. DATA field contains the generation758 * count of configuration set applied. See MC_CMD_DESC_PROXY_FUNC_CONFIG_SET /759 * MC_CMD_DESC_PROXY_FUNC_CONFIG_COMMIT and SF-122927-TC for details.760 */761#define MCDI_EVENT_CODE_DESC_PROXY_FUNC_CONFIG_COMMITTED 0x24762/* enum: Notification that a descriptor proxy function has been reset. SRC763 * field contains the handle of the affected descriptor proxy function. See764 * SF-122927-TC for details.765 */766#define MCDI_EVENT_CODE_DESC_PROXY_FUNC_RESET 0x25767/* enum: Notification that a driver attached to a descriptor proxy function.768 * SRC field contains the handle of the affected descriptor proxy function. For769 * Virtio proxy functions this message consists of two MCDI events, where the770 * first event's (CONT=1) DATA field carries negotiated virtio feature bits 0771 * to 31 and the second (CONT=0) carries bits 32 to 63. For EF100 proxy772 * functions event length and meaning of DATA field is not yet defined. See773 * SF-122927-TC for details.774 */775#define MCDI_EVENT_CODE_DESC_PROXY_FUNC_DRIVER_ATTACH 0x26776/* enum: Artificial event generated by host and posted via MC for test777 * purposes.778 */779#define MCDI_EVENT_CODE_TESTGEN 0xfa780#define MCDI_EVENT_CMDDONE_DATA_OFST 0781#define MCDI_EVENT_CMDDONE_DATA_LEN 4782#define MCDI_EVENT_CMDDONE_DATA_LBN 0783#define MCDI_EVENT_CMDDONE_DATA_WIDTH 32784#define MCDI_EVENT_LINKCHANGE_DATA_OFST 0785#define MCDI_EVENT_LINKCHANGE_DATA_LEN 4786#define MCDI_EVENT_LINKCHANGE_DATA_LBN 0787#define MCDI_EVENT_LINKCHANGE_DATA_WIDTH 32788#define MCDI_EVENT_SENSOREVT_DATA_OFST 0789#define MCDI_EVENT_SENSOREVT_DATA_LEN 4790#define MCDI_EVENT_SENSOREVT_DATA_LBN 0791#define MCDI_EVENT_SENSOREVT_DATA_WIDTH 32792#define MCDI_EVENT_MAC_STATS_DMA_GENERATION_OFST 0793#define MCDI_EVENT_MAC_STATS_DMA_GENERATION_LEN 4794#define MCDI_EVENT_MAC_STATS_DMA_GENERATION_LBN 0795#define MCDI_EVENT_MAC_STATS_DMA_GENERATION_WIDTH 32796#define MCDI_EVENT_TX_ERR_DATA_OFST 0797#define MCDI_EVENT_TX_ERR_DATA_LEN 4798#define MCDI_EVENT_TX_ERR_DATA_LBN 0799#define MCDI_EVENT_TX_ERR_DATA_WIDTH 32800/* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the seconds field of801 * timestamp802 */803#define MCDI_EVENT_PTP_SECONDS_OFST 0804#define MCDI_EVENT_PTP_SECONDS_LEN 4805#define MCDI_EVENT_PTP_SECONDS_LBN 0806#define MCDI_EVENT_PTP_SECONDS_WIDTH 32807/* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the major field of808 * timestamp809 */810#define MCDI_EVENT_PTP_MAJOR_OFST 0811#define MCDI_EVENT_PTP_MAJOR_LEN 4812#define MCDI_EVENT_PTP_MAJOR_LBN 0813#define MCDI_EVENT_PTP_MAJOR_WIDTH 32814/* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the nanoseconds field815 * of timestamp816 */817#define MCDI_EVENT_PTP_NANOSECONDS_OFST 0818#define MCDI_EVENT_PTP_NANOSECONDS_LEN 4819#define MCDI_EVENT_PTP_NANOSECONDS_LBN 0820#define MCDI_EVENT_PTP_NANOSECONDS_WIDTH 32821/* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the minor field of822 * timestamp823 */824#define MCDI_EVENT_PTP_MINOR_OFST 0825#define MCDI_EVENT_PTP_MINOR_LEN 4826#define MCDI_EVENT_PTP_MINOR_LBN 0827#define MCDI_EVENT_PTP_MINOR_WIDTH 32828/* For CODE_PTP_RX events, the lowest four bytes of sourceUUID from PTP packet829 */830#define MCDI_EVENT_PTP_UUID_OFST 0831#define MCDI_EVENT_PTP_UUID_LEN 4832#define MCDI_EVENT_PTP_UUID_LBN 0833#define MCDI_EVENT_PTP_UUID_WIDTH 32834#define MCDI_EVENT_RX_ERR_DATA_OFST 0835#define MCDI_EVENT_RX_ERR_DATA_LEN 4836#define MCDI_EVENT_RX_ERR_DATA_LBN 0837#define MCDI_EVENT_RX_ERR_DATA_WIDTH 32838#define MCDI_EVENT_PAR_ERR_DATA_OFST 0839#define MCDI_EVENT_PAR_ERR_DATA_LEN 4840#define MCDI_EVENT_PAR_ERR_DATA_LBN 0841#define MCDI_EVENT_PAR_ERR_DATA_WIDTH 32842#define MCDI_EVENT_ECC_CORR_ERR_DATA_OFST 0843#define MCDI_EVENT_ECC_CORR_ERR_DATA_LEN 4844#define MCDI_EVENT_ECC_CORR_ERR_DATA_LBN 0845#define MCDI_EVENT_ECC_CORR_ERR_DATA_WIDTH 32846#define MCDI_EVENT_ECC_FATAL_ERR_DATA_OFST 0847#define MCDI_EVENT_ECC_FATAL_ERR_DATA_LEN 4848#define MCDI_EVENT_ECC_FATAL_ERR_DATA_LBN 0849#define MCDI_EVENT_ECC_FATAL_ERR_DATA_WIDTH 32850/* For CODE_PTP_TIME events, the major value of the PTP clock */851#define MCDI_EVENT_PTP_TIME_MAJOR_OFST 0852#define MCDI_EVENT_PTP_TIME_MAJOR_LEN 4853#define MCDI_EVENT_PTP_TIME_MAJOR_LBN 0854#define MCDI_EVENT_PTP_TIME_MAJOR_WIDTH 32855/* For CODE_PTP_TIME events, bits 19-26 of the minor value of the PTP clock */856#define MCDI_EVENT_PTP_TIME_MINOR_26_19_LBN 36857#define MCDI_EVENT_PTP_TIME_MINOR_26_19_WIDTH 8858/* For CODE_PTP_TIME events, most significant bits of the minor value of the859 * PTP clock. This is a more generic equivalent of PTP_TIME_MINOR_26_19.860 */861#define MCDI_EVENT_PTP_TIME_MINOR_MS_8BITS_LBN 36862#define MCDI_EVENT_PTP_TIME_MINOR_MS_8BITS_WIDTH 8863/* For CODE_PTP_TIME events where report sync status is enabled, indicates864 * whether the NIC clock has ever been set865 */866#define MCDI_EVENT_PTP_TIME_NIC_CLOCK_VALID_LBN 36867#define MCDI_EVENT_PTP_TIME_NIC_CLOCK_VALID_WIDTH 1868/* For CODE_PTP_TIME events where report sync status is enabled, indicates869 * whether the NIC and System clocks are in sync870 */871#define MCDI_EVENT_PTP_TIME_HOST_NIC_IN_SYNC_LBN 37872#define MCDI_EVENT_PTP_TIME_HOST_NIC_IN_SYNC_WIDTH 1873/* For CODE_PTP_TIME events where report sync status is enabled, bits 21-26 of874 * the minor value of the PTP clock875 */876#define MCDI_EVENT_PTP_TIME_MINOR_26_21_LBN 38877#define MCDI_EVENT_PTP_TIME_MINOR_26_21_WIDTH 6878/* For CODE_PTP_TIME events, most significant bits of the minor value of the879 * PTP clock. This is a more generic equivalent of PTP_TIME_MINOR_26_21.880 */881#define MCDI_EVENT_PTP_TIME_MINOR_MS_6BITS_LBN 38882#define MCDI_EVENT_PTP_TIME_MINOR_MS_6BITS_WIDTH 6883#define MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_OFST 0884#define MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_LEN 4885#define MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_LBN 0886#define MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_WIDTH 32887#define MCDI_EVENT_PROXY_RESPONSE_HANDLE_OFST 0888#define MCDI_EVENT_PROXY_RESPONSE_HANDLE_LEN 4889#define MCDI_EVENT_PROXY_RESPONSE_HANDLE_LBN 0890#define MCDI_EVENT_PROXY_RESPONSE_HANDLE_WIDTH 32891/* Zero means that the request has been completed or authorized, and the driver892 * should resend it. A non-zero value means that the authorization has been893 * denied, and gives the reason. Typically it will be EPERM.894 */895#define MCDI_EVENT_PROXY_RESPONSE_RC_LBN 36896#define MCDI_EVENT_PROXY_RESPONSE_RC_WIDTH 8897#define MCDI_EVENT_DBRET_DATA_OFST 0898#define MCDI_EVENT_DBRET_DATA_LEN 4899#define MCDI_EVENT_DBRET_DATA_LBN 0900#define MCDI_EVENT_DBRET_DATA_WIDTH 32901#define MCDI_EVENT_LINKCHANGE_V2_DATA_OFST 0902#define MCDI_EVENT_LINKCHANGE_V2_DATA_LEN 4903#define MCDI_EVENT_LINKCHANGE_V2_DATA_LBN 0904#define MCDI_EVENT_LINKCHANGE_V2_DATA_WIDTH 32905#define MCDI_EVENT_MODULECHANGE_DATA_OFST 0906#define MCDI_EVENT_MODULECHANGE_DATA_LEN 4907#define MCDI_EVENT_MODULECHANGE_DATA_LBN 0908#define MCDI_EVENT_MODULECHANGE_DATA_WIDTH 32909/* The new generation count after a sensor has been added or deleted. */910#define MCDI_EVENT_DYNAMIC_SENSORS_GENERATION_OFST 0911#define MCDI_EVENT_DYNAMIC_SENSORS_GENERATION_LEN 4912#define MCDI_EVENT_DYNAMIC_SENSORS_GENERATION_LBN 0913#define MCDI_EVENT_DYNAMIC_SENSORS_GENERATION_WIDTH 32914/* The handle of a dynamic sensor. */915#define MCDI_EVENT_DYNAMIC_SENSORS_HANDLE_OFST 0916#define MCDI_EVENT_DYNAMIC_SENSORS_HANDLE_LEN 4917#define MCDI_EVENT_DYNAMIC_SENSORS_HANDLE_LBN 0918#define MCDI_EVENT_DYNAMIC_SENSORS_HANDLE_WIDTH 32919/* The current values of a sensor. */920#define MCDI_EVENT_DYNAMIC_SENSORS_VALUE_OFST 0921#define MCDI_EVENT_DYNAMIC_SENSORS_VALUE_LEN 4922#define MCDI_EVENT_DYNAMIC_SENSORS_VALUE_LBN 0923#define MCDI_EVENT_DYNAMIC_SENSORS_VALUE_WIDTH 32924/* The current state of a sensor. */925#define MCDI_EVENT_DYNAMIC_SENSORS_STATE_LBN 36926#define MCDI_EVENT_DYNAMIC_SENSORS_STATE_WIDTH 8927#define MCDI_EVENT_DESC_PROXY_DATA_OFST 0928#define MCDI_EVENT_DESC_PROXY_DATA_LEN 4929#define MCDI_EVENT_DESC_PROXY_DATA_LBN 0930#define MCDI_EVENT_DESC_PROXY_DATA_WIDTH 32931/* Generation count of applied configuration set */932#define MCDI_EVENT_DESC_PROXY_GENERATION_OFST 0933#define MCDI_EVENT_DESC_PROXY_GENERATION_LEN 4934#define MCDI_EVENT_DESC_PROXY_GENERATION_LBN 0935#define MCDI_EVENT_DESC_PROXY_GENERATION_WIDTH 32936/* Virtio features negotiated with the host driver. First event (CONT=1)937 * carries bits 0 to 31. Second event (CONT=0) carries bits 32 to 63.938 */939#define MCDI_EVENT_DESC_PROXY_VIRTIO_FEATURES_OFST 0940#define MCDI_EVENT_DESC_PROXY_VIRTIO_FEATURES_LEN 4941#define MCDI_EVENT_DESC_PROXY_VIRTIO_FEATURES_LBN 0942#define MCDI_EVENT_DESC_PROXY_VIRTIO_FEATURES_WIDTH 32943 944/* FCDI_EVENT structuredef */945#define FCDI_EVENT_LEN 8946#define FCDI_EVENT_CONT_LBN 32947#define FCDI_EVENT_CONT_WIDTH 1948#define FCDI_EVENT_LEVEL_LBN 33949#define FCDI_EVENT_LEVEL_WIDTH 3950/* enum: Info. */951#define FCDI_EVENT_LEVEL_INFO 0x0952/* enum: Warning. */953#define FCDI_EVENT_LEVEL_WARN 0x1954/* enum: Error. */955#define FCDI_EVENT_LEVEL_ERR 0x2956/* enum: Fatal. */957#define FCDI_EVENT_LEVEL_FATAL 0x3958#define FCDI_EVENT_DATA_OFST 0959#define FCDI_EVENT_DATA_LEN 4960#define FCDI_EVENT_LINK_STATE_STATUS_OFST 0961#define FCDI_EVENT_LINK_STATE_STATUS_LBN 0962#define FCDI_EVENT_LINK_STATE_STATUS_WIDTH 1963#define FCDI_EVENT_LINK_DOWN 0x0 /* enum */964#define FCDI_EVENT_LINK_UP 0x1 /* enum */965#define FCDI_EVENT_DATA_LBN 0966#define FCDI_EVENT_DATA_WIDTH 32967#define FCDI_EVENT_SRC_LBN 36968#define FCDI_EVENT_SRC_WIDTH 8969#define FCDI_EVENT_EV_CODE_LBN 60970#define FCDI_EVENT_EV_CODE_WIDTH 4971#define FCDI_EVENT_CODE_LBN 44972#define FCDI_EVENT_CODE_WIDTH 8973/* enum: The FC was rebooted. */974#define FCDI_EVENT_CODE_REBOOT 0x1975/* enum: Bad assert. */976#define FCDI_EVENT_CODE_ASSERT 0x2977/* enum: DDR3 test result. */978#define FCDI_EVENT_CODE_DDR_TEST_RESULT 0x3979/* enum: Link status. */980#define FCDI_EVENT_CODE_LINK_STATE 0x4981/* enum: A timed read is ready to be serviced. */982#define FCDI_EVENT_CODE_TIMED_READ 0x5983/* enum: One or more PPS IN events */984#define FCDI_EVENT_CODE_PPS_IN 0x6985/* enum: Tick event from PTP clock */986#define FCDI_EVENT_CODE_PTP_TICK 0x7987/* enum: ECC error counters */988#define FCDI_EVENT_CODE_DDR_ECC_STATUS 0x8989/* enum: Current status of PTP */990#define FCDI_EVENT_CODE_PTP_STATUS 0x9991/* enum: Port id config to map MC-FC port idx */992#define FCDI_EVENT_CODE_PORT_CONFIG 0xa993/* enum: Boot result or error code */994#define FCDI_EVENT_CODE_BOOT_RESULT 0xb995#define FCDI_EVENT_REBOOT_SRC_LBN 36996#define FCDI_EVENT_REBOOT_SRC_WIDTH 8997#define FCDI_EVENT_REBOOT_FC_FW 0x0 /* enum */998#define FCDI_EVENT_REBOOT_FC_BOOTLOADER 0x1 /* enum */999#define FCDI_EVENT_ASSERT_INSTR_ADDRESS_OFST 01000#define FCDI_EVENT_ASSERT_INSTR_ADDRESS_LEN 41001#define FCDI_EVENT_ASSERT_INSTR_ADDRESS_LBN 01002#define FCDI_EVENT_ASSERT_INSTR_ADDRESS_WIDTH 321003#define FCDI_EVENT_ASSERT_TYPE_LBN 361004#define FCDI_EVENT_ASSERT_TYPE_WIDTH 81005#define FCDI_EVENT_DDR_TEST_RESULT_STATUS_CODE_LBN 361006#define FCDI_EVENT_DDR_TEST_RESULT_STATUS_CODE_WIDTH 81007#define FCDI_EVENT_DDR_TEST_RESULT_RESULT_OFST 01008#define FCDI_EVENT_DDR_TEST_RESULT_RESULT_LEN 41009#define FCDI_EVENT_DDR_TEST_RESULT_RESULT_LBN 01010#define FCDI_EVENT_DDR_TEST_RESULT_RESULT_WIDTH 321011#define FCDI_EVENT_LINK_STATE_DATA_OFST 01012#define FCDI_EVENT_LINK_STATE_DATA_LEN 41013#define FCDI_EVENT_LINK_STATE_DATA_LBN 01014#define FCDI_EVENT_LINK_STATE_DATA_WIDTH 321015#define FCDI_EVENT_PTP_STATE_OFST 01016#define FCDI_EVENT_PTP_STATE_LEN 41017#define FCDI_EVENT_PTP_UNDEFINED 0x0 /* enum */1018#define FCDI_EVENT_PTP_SETUP_FAILED 0x1 /* enum */1019#define FCDI_EVENT_PTP_OPERATIONAL 0x2 /* enum */1020#define FCDI_EVENT_PTP_STATE_LBN 01021#define FCDI_EVENT_PTP_STATE_WIDTH 321022#define FCDI_EVENT_DDR_ECC_STATUS_BANK_ID_LBN 361023#define FCDI_EVENT_DDR_ECC_STATUS_BANK_ID_WIDTH 81024#define FCDI_EVENT_DDR_ECC_STATUS_STATUS_OFST 01025#define FCDI_EVENT_DDR_ECC_STATUS_STATUS_LEN 41026#define FCDI_EVENT_DDR_ECC_STATUS_STATUS_LBN 01027#define FCDI_EVENT_DDR_ECC_STATUS_STATUS_WIDTH 321028/* Index of MC port being referred to */1029#define FCDI_EVENT_PORT_CONFIG_SRC_LBN 361030#define FCDI_EVENT_PORT_CONFIG_SRC_WIDTH 81031/* FC Port index that matches the MC port index in SRC */1032#define FCDI_EVENT_PORT_CONFIG_DATA_OFST 01033#define FCDI_EVENT_PORT_CONFIG_DATA_LEN 41034#define FCDI_EVENT_PORT_CONFIG_DATA_LBN 01035#define FCDI_EVENT_PORT_CONFIG_DATA_WIDTH 321036#define FCDI_EVENT_BOOT_RESULT_OFST 01037#define FCDI_EVENT_BOOT_RESULT_LEN 41038/* Enum values, see field(s): */1039/* MC_CMD_AOE/MC_CMD_AOE_OUT_INFO/FC_BOOT_RESULT */1040#define FCDI_EVENT_BOOT_RESULT_LBN 01041#define FCDI_EVENT_BOOT_RESULT_WIDTH 321042 1043/* FCDI_EXTENDED_EVENT_PPS structuredef: Extended FCDI event to send PPS events1044 * to the MC. Note that this structure | is overlayed over a normal FCDI event1045 * such that bits 32-63 containing | event code, level, source etc remain the1046 * same. In this case the data | field of the header is defined to be the1047 * number of timestamps1048 */1049#define FCDI_EXTENDED_EVENT_PPS_LENMIN 161050#define FCDI_EXTENDED_EVENT_PPS_LENMAX 2481051#define FCDI_EXTENDED_EVENT_PPS_LENMAX_MCDI2 10161052#define FCDI_EXTENDED_EVENT_PPS_LEN(num) (8+8*(num))1053#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_NUM(len) (((len)-8)/8)1054/* Number of timestamps following */1055#define FCDI_EXTENDED_EVENT_PPS_COUNT_OFST 01056#define FCDI_EXTENDED_EVENT_PPS_COUNT_LEN 41057#define FCDI_EXTENDED_EVENT_PPS_COUNT_LBN 01058#define FCDI_EXTENDED_EVENT_PPS_COUNT_WIDTH 321059/* Seconds field of a timestamp record */1060#define FCDI_EXTENDED_EVENT_PPS_SECONDS_OFST 81061#define FCDI_EXTENDED_EVENT_PPS_SECONDS_LEN 41062#define FCDI_EXTENDED_EVENT_PPS_SECONDS_LBN 641063#define FCDI_EXTENDED_EVENT_PPS_SECONDS_WIDTH 321064/* Nanoseconds field of a timestamp record */1065#define FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_OFST 121066#define FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_LEN 41067#define FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_LBN 961068#define FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_WIDTH 321069/* Timestamp records comprising the event */1070#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_OFST 81071#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LEN 81072#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LO_OFST 81073#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_HI_OFST 121074#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_MINNUM 11075#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_MAXNUM 301076#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_MAXNUM_MCDI2 1261077#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LBN 641078#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_WIDTH 641079 1080/* MUM_EVENT structuredef */1081#define MUM_EVENT_LEN 81082#define MUM_EVENT_CONT_LBN 321083#define MUM_EVENT_CONT_WIDTH 11084#define MUM_EVENT_LEVEL_LBN 331085#define MUM_EVENT_LEVEL_WIDTH 31086/* enum: Info. */1087#define MUM_EVENT_LEVEL_INFO 0x01088/* enum: Warning. */1089#define MUM_EVENT_LEVEL_WARN 0x11090/* enum: Error. */1091#define MUM_EVENT_LEVEL_ERR 0x21092/* enum: Fatal. */1093#define MUM_EVENT_LEVEL_FATAL 0x31094#define MUM_EVENT_DATA_OFST 01095#define MUM_EVENT_DATA_LEN 41096#define MUM_EVENT_SENSOR_ID_OFST 01097#define MUM_EVENT_SENSOR_ID_LBN 01098#define MUM_EVENT_SENSOR_ID_WIDTH 81099/* Enum values, see field(s): */1100/* MC_CMD_SENSOR_INFO/MC_CMD_SENSOR_INFO_OUT/MASK */1101#define MUM_EVENT_SENSOR_STATE_OFST 01102#define MUM_EVENT_SENSOR_STATE_LBN 81103#define MUM_EVENT_SENSOR_STATE_WIDTH 81104#define MUM_EVENT_PORT_PHY_READY_OFST 01105#define MUM_EVENT_PORT_PHY_READY_LBN 01106#define MUM_EVENT_PORT_PHY_READY_WIDTH 11107#define MUM_EVENT_PORT_PHY_LINK_UP_OFST 01108#define MUM_EVENT_PORT_PHY_LINK_UP_LBN 11109#define MUM_EVENT_PORT_PHY_LINK_UP_WIDTH 11110#define MUM_EVENT_PORT_PHY_TX_LOL_OFST 01111#define MUM_EVENT_PORT_PHY_TX_LOL_LBN 21112#define MUM_EVENT_PORT_PHY_TX_LOL_WIDTH 11113#define MUM_EVENT_PORT_PHY_RX_LOL_OFST 01114#define MUM_EVENT_PORT_PHY_RX_LOL_LBN 31115#define MUM_EVENT_PORT_PHY_RX_LOL_WIDTH 11116#define MUM_EVENT_PORT_PHY_TX_LOS_OFST 01117#define MUM_EVENT_PORT_PHY_TX_LOS_LBN 41118#define MUM_EVENT_PORT_PHY_TX_LOS_WIDTH 11119#define MUM_EVENT_PORT_PHY_RX_LOS_OFST 01120#define MUM_EVENT_PORT_PHY_RX_LOS_LBN 51121#define MUM_EVENT_PORT_PHY_RX_LOS_WIDTH 11122#define MUM_EVENT_PORT_PHY_TX_FAULT_OFST 01123#define MUM_EVENT_PORT_PHY_TX_FAULT_LBN 61124#define MUM_EVENT_PORT_PHY_TX_FAULT_WIDTH 11125#define MUM_EVENT_DATA_LBN 01126#define MUM_EVENT_DATA_WIDTH 321127#define MUM_EVENT_SRC_LBN 361128#define MUM_EVENT_SRC_WIDTH 81129#define MUM_EVENT_EV_CODE_LBN 601130#define MUM_EVENT_EV_CODE_WIDTH 41131#define MUM_EVENT_CODE_LBN 441132#define MUM_EVENT_CODE_WIDTH 81133/* enum: The MUM was rebooted. */1134#define MUM_EVENT_CODE_REBOOT 0x11135/* enum: Bad assert. */1136#define MUM_EVENT_CODE_ASSERT 0x21137/* enum: Sensor failure. */1138#define MUM_EVENT_CODE_SENSOR 0x31139/* enum: Link fault has been asserted, or has cleared. */1140#define MUM_EVENT_CODE_QSFP_LASI_INTERRUPT 0x41141#define MUM_EVENT_SENSOR_DATA_OFST 01142#define MUM_EVENT_SENSOR_DATA_LEN 41143#define MUM_EVENT_SENSOR_DATA_LBN 01144#define MUM_EVENT_SENSOR_DATA_WIDTH 321145#define MUM_EVENT_PORT_PHY_FLAGS_OFST 01146#define MUM_EVENT_PORT_PHY_FLAGS_LEN 41147#define MUM_EVENT_PORT_PHY_FLAGS_LBN 01148#define MUM_EVENT_PORT_PHY_FLAGS_WIDTH 321149#define MUM_EVENT_PORT_PHY_COPPER_LEN_OFST 01150#define MUM_EVENT_PORT_PHY_COPPER_LEN_LEN 41151#define MUM_EVENT_PORT_PHY_COPPER_LEN_LBN 01152#define MUM_EVENT_PORT_PHY_COPPER_LEN_WIDTH 321153#define MUM_EVENT_PORT_PHY_CAPS_OFST 01154#define MUM_EVENT_PORT_PHY_CAPS_LEN 41155#define MUM_EVENT_PORT_PHY_CAPS_LBN 01156#define MUM_EVENT_PORT_PHY_CAPS_WIDTH 321157#define MUM_EVENT_PORT_PHY_TECH_OFST 01158#define MUM_EVENT_PORT_PHY_TECH_LEN 41159#define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_UNKNOWN 0x0 /* enum */1160#define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_OPTICAL 0x1 /* enum */1161#define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_PASSIVE 0x2 /* enum */1162#define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_PASSIVE_EQUALIZED 0x3 /* enum */1163#define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_ACTIVE_LIMITING 0x4 /* enum */1164#define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_ACTIVE_LINEAR 0x5 /* enum */1165#define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_BASE_T 0x6 /* enum */1166#define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_LOOPBACK_PASSIVE 0x7 /* enum */1167#define MUM_EVENT_PORT_PHY_TECH_LBN 01168#define MUM_EVENT_PORT_PHY_TECH_WIDTH 321169#define MUM_EVENT_PORT_PHY_SRC_DATA_ID_LBN 361170#define MUM_EVENT_PORT_PHY_SRC_DATA_ID_WIDTH 41171#define MUM_EVENT_PORT_PHY_SRC_DATA_ID_FLAGS 0x0 /* enum */1172#define MUM_EVENT_PORT_PHY_SRC_DATA_ID_COPPER_LEN 0x1 /* enum */1173#define MUM_EVENT_PORT_PHY_SRC_DATA_ID_CAPS 0x2 /* enum */1174#define MUM_EVENT_PORT_PHY_SRC_DATA_ID_TECH 0x3 /* enum */1175#define MUM_EVENT_PORT_PHY_SRC_DATA_ID_MAX 0x4 /* enum */1176#define MUM_EVENT_PORT_PHY_SRC_PORT_NO_LBN 401177#define MUM_EVENT_PORT_PHY_SRC_PORT_NO_WIDTH 41178 1179 1180/***********************************/1181/* MC_CMD_READ321182 * Read multiple 32byte words from MC memory. Note - this command really1183 * belongs to INSECURE category but is required by shmboot. The command handler1184 * has additional checks to reject insecure calls.1185 */1186#define MC_CMD_READ32 0x11187#undef MC_CMD_0x1_PRIVILEGE_CTG1188 1189#define MC_CMD_0x1_PRIVILEGE_CTG SRIOV_CTG_ADMIN1190 1191/* MC_CMD_READ32_IN msgrequest */1192#define MC_CMD_READ32_IN_LEN 81193#define MC_CMD_READ32_IN_ADDR_OFST 01194#define MC_CMD_READ32_IN_ADDR_LEN 41195#define MC_CMD_READ32_IN_NUMWORDS_OFST 41196#define MC_CMD_READ32_IN_NUMWORDS_LEN 41197 1198/* MC_CMD_READ32_OUT msgresponse */1199#define MC_CMD_READ32_OUT_LENMIN 41200#define MC_CMD_READ32_OUT_LENMAX 2521201#define MC_CMD_READ32_OUT_LENMAX_MCDI2 10201202#define MC_CMD_READ32_OUT_LEN(num) (0+4*(num))1203#define MC_CMD_READ32_OUT_BUFFER_NUM(len) (((len)-0)/4)1204#define MC_CMD_READ32_OUT_BUFFER_OFST 01205#define MC_CMD_READ32_OUT_BUFFER_LEN 41206#define MC_CMD_READ32_OUT_BUFFER_MINNUM 11207#define MC_CMD_READ32_OUT_BUFFER_MAXNUM 631208#define MC_CMD_READ32_OUT_BUFFER_MAXNUM_MCDI2 2551209 1210 1211/***********************************/1212/* MC_CMD_WRITE321213 * Write multiple 32byte words to MC memory.1214 */1215#define MC_CMD_WRITE32 0x21216#undef MC_CMD_0x2_PRIVILEGE_CTG1217 1218#define MC_CMD_0x2_PRIVILEGE_CTG SRIOV_CTG_INSECURE1219 1220/* MC_CMD_WRITE32_IN msgrequest */1221#define MC_CMD_WRITE32_IN_LENMIN 81222#define MC_CMD_WRITE32_IN_LENMAX 2521223#define MC_CMD_WRITE32_IN_LENMAX_MCDI2 10201224#define MC_CMD_WRITE32_IN_LEN(num) (4+4*(num))1225#define MC_CMD_WRITE32_IN_BUFFER_NUM(len) (((len)-4)/4)1226#define MC_CMD_WRITE32_IN_ADDR_OFST 01227#define MC_CMD_WRITE32_IN_ADDR_LEN 41228#define MC_CMD_WRITE32_IN_BUFFER_OFST 41229#define MC_CMD_WRITE32_IN_BUFFER_LEN 41230#define MC_CMD_WRITE32_IN_BUFFER_MINNUM 11231#define MC_CMD_WRITE32_IN_BUFFER_MAXNUM 621232#define MC_CMD_WRITE32_IN_BUFFER_MAXNUM_MCDI2 2541233 1234/* MC_CMD_WRITE32_OUT msgresponse */1235#define MC_CMD_WRITE32_OUT_LEN 01236 1237 1238/***********************************/1239/* MC_CMD_COPYCODE1240 * Copy MC code between two locations and jump. Note - this command really1241 * belongs to INSECURE category but is required by shmboot. The command handler1242 * has additional checks to reject insecure calls.1243 */1244#define MC_CMD_COPYCODE 0x31245#undef MC_CMD_0x3_PRIVILEGE_CTG1246 1247#define MC_CMD_0x3_PRIVILEGE_CTG SRIOV_CTG_ADMIN1248 1249/* MC_CMD_COPYCODE_IN msgrequest */1250#define MC_CMD_COPYCODE_IN_LEN 161251/* Source address1252 *1253 * The main image should be entered via a copy of a single word from and to a1254 * magic address, which controls various aspects of the boot. The magic address1255 * is a bitfield, with each bit as documented below.1256 */1257#define MC_CMD_COPYCODE_IN_SRC_ADDR_OFST 01258#define MC_CMD_COPYCODE_IN_SRC_ADDR_LEN 41259/* enum: Deprecated; equivalent to setting BOOT_MAGIC_PRESENT (see below) */1260#define MC_CMD_COPYCODE_HUNT_NO_MAGIC_ADDR 0x100001261/* enum: Deprecated; equivalent to setting BOOT_MAGIC_PRESENT and1262 * BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED (see below)1263 */1264#define MC_CMD_COPYCODE_HUNT_NO_DATAPATH_MAGIC_ADDR 0x1d0d01265/* enum: Deprecated; equivalent to setting BOOT_MAGIC_PRESENT,1266 * BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED and BOOT_MAGIC_IGNORE_CONFIG (see1267 * below)1268 */1269#define MC_CMD_COPYCODE_HUNT_IGNORE_CONFIG_MAGIC_ADDR 0x1badc1270#define MC_CMD_COPYCODE_IN_BOOT_MAGIC_PRESENT_OFST 01271#define MC_CMD_COPYCODE_IN_BOOT_MAGIC_PRESENT_LBN 171272#define MC_CMD_COPYCODE_IN_BOOT_MAGIC_PRESENT_WIDTH 11273#define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED_OFST 01274#define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED_LBN 21275#define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED_WIDTH 11276#define MC_CMD_COPYCODE_IN_BOOT_MAGIC_IGNORE_CONFIG_OFST 01277#define MC_CMD_COPYCODE_IN_BOOT_MAGIC_IGNORE_CONFIG_LBN 31278#define MC_CMD_COPYCODE_IN_BOOT_MAGIC_IGNORE_CONFIG_WIDTH 11279#define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SKIP_BOOT_ICORE_SYNC_OFST 01280#define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SKIP_BOOT_ICORE_SYNC_LBN 41281#define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SKIP_BOOT_ICORE_SYNC_WIDTH 11282#define MC_CMD_COPYCODE_IN_BOOT_MAGIC_FORCE_STANDALONE_OFST 01283#define MC_CMD_COPYCODE_IN_BOOT_MAGIC_FORCE_STANDALONE_LBN 51284#define MC_CMD_COPYCODE_IN_BOOT_MAGIC_FORCE_STANDALONE_WIDTH 11285#define MC_CMD_COPYCODE_IN_BOOT_MAGIC_DISABLE_XIP_OFST 01286#define MC_CMD_COPYCODE_IN_BOOT_MAGIC_DISABLE_XIP_LBN 61287#define MC_CMD_COPYCODE_IN_BOOT_MAGIC_DISABLE_XIP_WIDTH 11288/* Destination address */1289#define MC_CMD_COPYCODE_IN_DEST_ADDR_OFST 41290#define MC_CMD_COPYCODE_IN_DEST_ADDR_LEN 41291#define MC_CMD_COPYCODE_IN_NUMWORDS_OFST 81292#define MC_CMD_COPYCODE_IN_NUMWORDS_LEN 41293/* Address of where to jump after copy. */1294#define MC_CMD_COPYCODE_IN_JUMP_OFST 121295#define MC_CMD_COPYCODE_IN_JUMP_LEN 41296/* enum: Control should return to the caller rather than jumping */1297#define MC_CMD_COPYCODE_JUMP_NONE 0x11298 1299/* MC_CMD_COPYCODE_OUT msgresponse */1300#define MC_CMD_COPYCODE_OUT_LEN 01301 1302 1303/***********************************/1304/* MC_CMD_SET_FUNC1305 * Select function for function-specific commands.1306 */1307#define MC_CMD_SET_FUNC 0x41308#undef MC_CMD_0x4_PRIVILEGE_CTG1309 1310#define MC_CMD_0x4_PRIVILEGE_CTG SRIOV_CTG_INSECURE1311 1312/* MC_CMD_SET_FUNC_IN msgrequest */1313#define MC_CMD_SET_FUNC_IN_LEN 41314/* Set function */1315#define MC_CMD_SET_FUNC_IN_FUNC_OFST 01316#define MC_CMD_SET_FUNC_IN_FUNC_LEN 41317 1318/* MC_CMD_SET_FUNC_OUT msgresponse */1319#define MC_CMD_SET_FUNC_OUT_LEN 01320 1321 1322/***********************************/1323/* MC_CMD_GET_BOOT_STATUS1324 * Get the instruction address from which the MC booted.1325 */1326#define MC_CMD_GET_BOOT_STATUS 0x51327#undef MC_CMD_0x5_PRIVILEGE_CTG1328 1329#define MC_CMD_0x5_PRIVILEGE_CTG SRIOV_CTG_GENERAL1330 1331/* MC_CMD_GET_BOOT_STATUS_IN msgrequest */1332#define MC_CMD_GET_BOOT_STATUS_IN_LEN 01333 1334/* MC_CMD_GET_BOOT_STATUS_OUT msgresponse */1335#define MC_CMD_GET_BOOT_STATUS_OUT_LEN 81336/* ?? */1337#define MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_OFST 01338#define MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_LEN 41339/* enum: indicates that the MC wasn't flash booted */1340#define MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_NULL 0xdeadbeef1341#define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_OFST 41342#define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_LEN 41343#define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_WATCHDOG_OFST 41344#define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_WATCHDOG_LBN 01345#define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_WATCHDOG_WIDTH 11346#define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_PRIMARY_OFST 41347#define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_PRIMARY_LBN 11348#define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_PRIMARY_WIDTH 11349#define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_BACKUP_OFST 41350#define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_BACKUP_LBN 21351#define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_BACKUP_WIDTH 11352 1353 1354/***********************************/1355/* MC_CMD_GET_ASSERTS1356 * Get (and optionally clear) the current assertion status. Only1357 * OUT.GLOBAL_FLAGS is guaranteed to exist in the completion payload. The other1358 * fields will only be present if OUT.GLOBAL_FLAGS != NO_FAILS1359 */1360#define MC_CMD_GET_ASSERTS 0x61361#undef MC_CMD_0x6_PRIVILEGE_CTG1362 1363#define MC_CMD_0x6_PRIVILEGE_CTG SRIOV_CTG_ADMIN1364 1365/* MC_CMD_GET_ASSERTS_IN msgrequest */1366#define MC_CMD_GET_ASSERTS_IN_LEN 41367/* Set to clear assertion */1368#define MC_CMD_GET_ASSERTS_IN_CLEAR_OFST 01369#define MC_CMD_GET_ASSERTS_IN_CLEAR_LEN 41370 1371/* MC_CMD_GET_ASSERTS_OUT msgresponse */1372#define MC_CMD_GET_ASSERTS_OUT_LEN 1401373/* Assertion status flag. */1374#define MC_CMD_GET_ASSERTS_OUT_GLOBAL_FLAGS_OFST 01375#define MC_CMD_GET_ASSERTS_OUT_GLOBAL_FLAGS_LEN 41376/* enum: No assertions have failed. */1377#define MC_CMD_GET_ASSERTS_FLAGS_NO_FAILS 0x11378/* enum: A system-level assertion has failed. */1379#define MC_CMD_GET_ASSERTS_FLAGS_SYS_FAIL 0x21380/* enum: A thread-level assertion has failed. */1381#define MC_CMD_GET_ASSERTS_FLAGS_THR_FAIL 0x31382/* enum: The system was reset by the watchdog. */1383#define MC_CMD_GET_ASSERTS_FLAGS_WDOG_FIRED 0x41384/* enum: An illegal address trap stopped the system (huntington and later) */1385#define MC_CMD_GET_ASSERTS_FLAGS_ADDR_TRAP 0x51386/* Failing PC value */1387#define MC_CMD_GET_ASSERTS_OUT_SAVED_PC_OFFS_OFST 41388#define MC_CMD_GET_ASSERTS_OUT_SAVED_PC_OFFS_LEN 41389/* Saved GP regs */1390#define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_OFST 81391#define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_LEN 41392#define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_NUM 311393/* enum: A magic value hinting that the value in this register at the time of1394 * the failure has likely been lost.1395 */1396#define MC_CMD_GET_ASSERTS_REG_NO_DATA 0xda7a10571397/* Failing thread address */1398#define MC_CMD_GET_ASSERTS_OUT_THREAD_OFFS_OFST 1321399#define MC_CMD_GET_ASSERTS_OUT_THREAD_OFFS_LEN 41400#define MC_CMD_GET_ASSERTS_OUT_RESERVED_OFST 1361401#define MC_CMD_GET_ASSERTS_OUT_RESERVED_LEN 41402 1403/* MC_CMD_GET_ASSERTS_OUT_V2 msgresponse: Extended response for MicroBlaze CPUs1404 * found on Riverhead designs1405 */1406#define MC_CMD_GET_ASSERTS_OUT_V2_LEN 2401407/* Assertion status flag. */1408#define MC_CMD_GET_ASSERTS_OUT_V2_GLOBAL_FLAGS_OFST 01409#define MC_CMD_GET_ASSERTS_OUT_V2_GLOBAL_FLAGS_LEN 41410/* enum: No assertions have failed. */1411/* MC_CMD_GET_ASSERTS_FLAGS_NO_FAILS 0x1 */1412/* enum: A system-level assertion has failed. */1413/* MC_CMD_GET_ASSERTS_FLAGS_SYS_FAIL 0x2 */1414/* enum: A thread-level assertion has failed. */1415/* MC_CMD_GET_ASSERTS_FLAGS_THR_FAIL 0x3 */1416/* enum: The system was reset by the watchdog. */1417/* MC_CMD_GET_ASSERTS_FLAGS_WDOG_FIRED 0x4 */1418/* enum: An illegal address trap stopped the system (huntington and later) */1419/* MC_CMD_GET_ASSERTS_FLAGS_ADDR_TRAP 0x5 */1420/* Failing PC value */1421#define MC_CMD_GET_ASSERTS_OUT_V2_SAVED_PC_OFFS_OFST 41422#define MC_CMD_GET_ASSERTS_OUT_V2_SAVED_PC_OFFS_LEN 41423/* Saved GP regs */1424#define MC_CMD_GET_ASSERTS_OUT_V2_GP_REGS_OFFS_OFST 81425#define MC_CMD_GET_ASSERTS_OUT_V2_GP_REGS_OFFS_LEN 41426#define MC_CMD_GET_ASSERTS_OUT_V2_GP_REGS_OFFS_NUM 311427/* enum: A magic value hinting that the value in this register at the time of1428 * the failure has likely been lost.1429 */1430/* MC_CMD_GET_ASSERTS_REG_NO_DATA 0xda7a1057 */1431/* Failing thread address */1432#define MC_CMD_GET_ASSERTS_OUT_V2_THREAD_OFFS_OFST 1321433#define MC_CMD_GET_ASSERTS_OUT_V2_THREAD_OFFS_LEN 41434#define MC_CMD_GET_ASSERTS_OUT_V2_RESERVED_OFST 1361435#define MC_CMD_GET_ASSERTS_OUT_V2_RESERVED_LEN 41436/* Saved Special Function Registers */1437#define MC_CMD_GET_ASSERTS_OUT_V2_SF_REGS_OFFS_OFST 1361438#define MC_CMD_GET_ASSERTS_OUT_V2_SF_REGS_OFFS_LEN 41439#define MC_CMD_GET_ASSERTS_OUT_V2_SF_REGS_OFFS_NUM 261440 1441/* MC_CMD_GET_ASSERTS_OUT_V3 msgresponse: Extended response with asserted1442 * firmware version information1443 */1444#define MC_CMD_GET_ASSERTS_OUT_V3_LEN 3601445/* Assertion status flag. */1446#define MC_CMD_GET_ASSERTS_OUT_V3_GLOBAL_FLAGS_OFST 01447#define MC_CMD_GET_ASSERTS_OUT_V3_GLOBAL_FLAGS_LEN 41448/* enum: No assertions have failed. */1449/* MC_CMD_GET_ASSERTS_FLAGS_NO_FAILS 0x1 */1450/* enum: A system-level assertion has failed. */1451/* MC_CMD_GET_ASSERTS_FLAGS_SYS_FAIL 0x2 */1452/* enum: A thread-level assertion has failed. */1453/* MC_CMD_GET_ASSERTS_FLAGS_THR_FAIL 0x3 */1454/* enum: The system was reset by the watchdog. */1455/* MC_CMD_GET_ASSERTS_FLAGS_WDOG_FIRED 0x4 */1456/* enum: An illegal address trap stopped the system (huntington and later) */1457/* MC_CMD_GET_ASSERTS_FLAGS_ADDR_TRAP 0x5 */1458/* Failing PC value */1459#define MC_CMD_GET_ASSERTS_OUT_V3_SAVED_PC_OFFS_OFST 41460#define MC_CMD_GET_ASSERTS_OUT_V3_SAVED_PC_OFFS_LEN 41461/* Saved GP regs */1462#define MC_CMD_GET_ASSERTS_OUT_V3_GP_REGS_OFFS_OFST 81463#define MC_CMD_GET_ASSERTS_OUT_V3_GP_REGS_OFFS_LEN 41464#define MC_CMD_GET_ASSERTS_OUT_V3_GP_REGS_OFFS_NUM 311465/* enum: A magic value hinting that the value in this register at the time of1466 * the failure has likely been lost.1467 */1468/* MC_CMD_GET_ASSERTS_REG_NO_DATA 0xda7a1057 */1469/* Failing thread address */1470#define MC_CMD_GET_ASSERTS_OUT_V3_THREAD_OFFS_OFST 1321471#define MC_CMD_GET_ASSERTS_OUT_V3_THREAD_OFFS_LEN 41472#define MC_CMD_GET_ASSERTS_OUT_V3_RESERVED_OFST 1361473#define MC_CMD_GET_ASSERTS_OUT_V3_RESERVED_LEN 41474/* Saved Special Function Registers */1475#define MC_CMD_GET_ASSERTS_OUT_V3_SF_REGS_OFFS_OFST 1361476#define MC_CMD_GET_ASSERTS_OUT_V3_SF_REGS_OFFS_LEN 41477#define MC_CMD_GET_ASSERTS_OUT_V3_SF_REGS_OFFS_NUM 261478/* MC firmware unique build ID (as binary SHA-1 value) */1479#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_ID_OFST 2401480#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_ID_LEN 201481/* MC firmware build date (as Unix timestamp) */1482#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_TIMESTAMP_OFST 2601483#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_TIMESTAMP_LEN 81484#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_TIMESTAMP_LO_OFST 2601485#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_TIMESTAMP_HI_OFST 2641486/* MC firmware version number */1487#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_VERSION_OFST 2681488#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_VERSION_LEN 81489#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_VERSION_LO_OFST 2681490#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_VERSION_HI_OFST 2721491/* MC firmware security level */1492#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_SECURITY_LEVEL_OFST 2761493#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_SECURITY_LEVEL_LEN 41494/* MC firmware extra version info (as null-terminated US-ASCII string) */1495#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_EXTRA_INFO_OFST 2801496#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_EXTRA_INFO_LEN 161497/* MC firmware build name (as null-terminated US-ASCII string) */1498#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_NAME_OFST 2961499#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_NAME_LEN 641500 1501 1502/***********************************/1503/* MC_CMD_LOG_CTRL1504 * Configure the output stream for log events such as link state changes,1505 * sensor notifications and MCDI completions1506 */1507#define MC_CMD_LOG_CTRL 0x71508#undef MC_CMD_0x7_PRIVILEGE_CTG1509 1510#define MC_CMD_0x7_PRIVILEGE_CTG SRIOV_CTG_GENERAL1511 1512/* MC_CMD_LOG_CTRL_IN msgrequest */1513#define MC_CMD_LOG_CTRL_IN_LEN 81514/* Log destination */1515#define MC_CMD_LOG_CTRL_IN_LOG_DEST_OFST 01516#define MC_CMD_LOG_CTRL_IN_LOG_DEST_LEN 41517/* enum: UART. */1518#define MC_CMD_LOG_CTRL_IN_LOG_DEST_UART 0x11519/* enum: Event queue. */1520#define MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ 0x21521/* Legacy argument. Must be zero. */1522#define MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ_OFST 41523#define MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ_LEN 41524 1525/* MC_CMD_LOG_CTRL_OUT msgresponse */1526#define MC_CMD_LOG_CTRL_OUT_LEN 01527 1528 1529/***********************************/1530/* MC_CMD_GET_VERSION1531 * Get version information about adapter components.1532 */1533#define MC_CMD_GET_VERSION 0x81534#undef MC_CMD_0x8_PRIVILEGE_CTG1535 1536#define MC_CMD_0x8_PRIVILEGE_CTG SRIOV_CTG_GENERAL1537 1538/* MC_CMD_GET_VERSION_IN msgrequest */1539#define MC_CMD_GET_VERSION_IN_LEN 01540 1541/* MC_CMD_GET_VERSION_EXT_IN msgrequest: Asks for the extended version */1542#define MC_CMD_GET_VERSION_EXT_IN_LEN 41543/* placeholder, set to 0 */1544#define MC_CMD_GET_VERSION_EXT_IN_EXT_FLAGS_OFST 01545#define MC_CMD_GET_VERSION_EXT_IN_EXT_FLAGS_LEN 41546 1547/* MC_CMD_GET_VERSION_V0_OUT msgresponse: deprecated version format */1548#define MC_CMD_GET_VERSION_V0_OUT_LEN 41549#define MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 01550#define MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 41551/* enum: Reserved version number to indicate "any" version. */1552#define MC_CMD_GET_VERSION_OUT_FIRMWARE_ANY 0xffffffff1553/* enum: Bootrom version value for Siena. */1554#define MC_CMD_GET_VERSION_OUT_FIRMWARE_SIENA_BOOTROM 0xb00700001555/* enum: Bootrom version value for Huntington. */1556#define MC_CMD_GET_VERSION_OUT_FIRMWARE_HUNT_BOOTROM 0xb00700011557/* enum: Bootrom version value for Medford2. */1558#define MC_CMD_GET_VERSION_OUT_FIRMWARE_MEDFORD2_BOOTROM 0xb00700021559 1560/* MC_CMD_GET_VERSION_OUT msgresponse */1561#define MC_CMD_GET_VERSION_OUT_LEN 321562/* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */1563/* MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4 */1564/* Enum values, see field(s): */1565/* MC_CMD_GET_VERSION_V0_OUT/MC_CMD_GET_VERSION_OUT_FIRMWARE */1566#define MC_CMD_GET_VERSION_OUT_PCOL_OFST 41567#define MC_CMD_GET_VERSION_OUT_PCOL_LEN 41568/* 128bit mask of functions supported by the current firmware */1569#define MC_CMD_GET_VERSION_OUT_SUPPORTED_FUNCS_OFST 81570#define MC_CMD_GET_VERSION_OUT_SUPPORTED_FUNCS_LEN 161571#define MC_CMD_GET_VERSION_OUT_VERSION_OFST 241572#define MC_CMD_GET_VERSION_OUT_VERSION_LEN 81573#define MC_CMD_GET_VERSION_OUT_VERSION_LO_OFST 241574#define MC_CMD_GET_VERSION_OUT_VERSION_HI_OFST 281575 1576/* MC_CMD_GET_VERSION_EXT_OUT msgresponse */1577#define MC_CMD_GET_VERSION_EXT_OUT_LEN 481578/* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */1579/* MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4 */1580/* Enum values, see field(s): */1581/* MC_CMD_GET_VERSION_V0_OUT/MC_CMD_GET_VERSION_OUT_FIRMWARE */1582#define MC_CMD_GET_VERSION_EXT_OUT_PCOL_OFST 41583#define MC_CMD_GET_VERSION_EXT_OUT_PCOL_LEN 41584/* 128bit mask of functions supported by the current firmware */1585#define MC_CMD_GET_VERSION_EXT_OUT_SUPPORTED_FUNCS_OFST 81586#define MC_CMD_GET_VERSION_EXT_OUT_SUPPORTED_FUNCS_LEN 161587#define MC_CMD_GET_VERSION_EXT_OUT_VERSION_OFST 241588#define MC_CMD_GET_VERSION_EXT_OUT_VERSION_LEN 81589#define MC_CMD_GET_VERSION_EXT_OUT_VERSION_LO_OFST 241590#define MC_CMD_GET_VERSION_EXT_OUT_VERSION_HI_OFST 281591/* extra info */1592#define MC_CMD_GET_VERSION_EXT_OUT_EXTRA_OFST 321593#define MC_CMD_GET_VERSION_EXT_OUT_EXTRA_LEN 161594 1595/* MC_CMD_GET_VERSION_V2_OUT msgresponse: Extended response providing version1596 * information for all adapter components. For Riverhead based designs, base MC1597 * firmware version fields refer to NMC firmware, while CMC firmware data is in1598 * dedicated CMC fields. Flags indicate which data is present in the response1599 * (depending on which components exist on a particular adapter)1600 */1601#define MC_CMD_GET_VERSION_V2_OUT_LEN 3041602/* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */1603/* MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4 */1604/* Enum values, see field(s): */1605/* MC_CMD_GET_VERSION_V0_OUT/MC_CMD_GET_VERSION_OUT_FIRMWARE */1606#define MC_CMD_GET_VERSION_V2_OUT_PCOL_OFST 41607#define MC_CMD_GET_VERSION_V2_OUT_PCOL_LEN 41608/* 128bit mask of functions supported by the current firmware */1609#define MC_CMD_GET_VERSION_V2_OUT_SUPPORTED_FUNCS_OFST 81610#define MC_CMD_GET_VERSION_V2_OUT_SUPPORTED_FUNCS_LEN 161611#define MC_CMD_GET_VERSION_V2_OUT_VERSION_OFST 241612#define MC_CMD_GET_VERSION_V2_OUT_VERSION_LEN 81613#define MC_CMD_GET_VERSION_V2_OUT_VERSION_LO_OFST 241614#define MC_CMD_GET_VERSION_V2_OUT_VERSION_HI_OFST 281615/* extra info */1616#define MC_CMD_GET_VERSION_V2_OUT_EXTRA_OFST 321617#define MC_CMD_GET_VERSION_V2_OUT_EXTRA_LEN 161618/* Flags indicating which extended fields are valid */1619#define MC_CMD_GET_VERSION_V2_OUT_FLAGS_OFST 481620#define MC_CMD_GET_VERSION_V2_OUT_FLAGS_LEN 41621#define MC_CMD_GET_VERSION_V2_OUT_MCFW_EXT_INFO_PRESENT_OFST 481622#define MC_CMD_GET_VERSION_V2_OUT_MCFW_EXT_INFO_PRESENT_LBN 01623#define MC_CMD_GET_VERSION_V2_OUT_MCFW_EXT_INFO_PRESENT_WIDTH 11624#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_EXT_INFO_PRESENT_OFST 481625#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_EXT_INFO_PRESENT_LBN 11626#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_EXT_INFO_PRESENT_WIDTH 11627#define MC_CMD_GET_VERSION_V2_OUT_CMC_EXT_INFO_PRESENT_OFST 481628#define MC_CMD_GET_VERSION_V2_OUT_CMC_EXT_INFO_PRESENT_LBN 21629#define MC_CMD_GET_VERSION_V2_OUT_CMC_EXT_INFO_PRESENT_WIDTH 11630#define MC_CMD_GET_VERSION_V2_OUT_FPGA_EXT_INFO_PRESENT_OFST 481631#define MC_CMD_GET_VERSION_V2_OUT_FPGA_EXT_INFO_PRESENT_LBN 31632#define MC_CMD_GET_VERSION_V2_OUT_FPGA_EXT_INFO_PRESENT_WIDTH 11633#define MC_CMD_GET_VERSION_V2_OUT_BOARD_EXT_INFO_PRESENT_OFST 481634#define MC_CMD_GET_VERSION_V2_OUT_BOARD_EXT_INFO_PRESENT_LBN 41635#define MC_CMD_GET_VERSION_V2_OUT_BOARD_EXT_INFO_PRESENT_WIDTH 11636/* MC firmware unique build ID (as binary SHA-1 value) */1637#define MC_CMD_GET_VERSION_V2_OUT_MCFW_BUILD_ID_OFST 521638#define MC_CMD_GET_VERSION_V2_OUT_MCFW_BUILD_ID_LEN 201639/* MC firmware security level */1640#define MC_CMD_GET_VERSION_V2_OUT_MCFW_SECURITY_LEVEL_OFST 721641#define MC_CMD_GET_VERSION_V2_OUT_MCFW_SECURITY_LEVEL_LEN 41642/* MC firmware build name (as null-terminated US-ASCII string) */1643#define MC_CMD_GET_VERSION_V2_OUT_MCFW_BUILD_NAME_OFST 761644#define MC_CMD_GET_VERSION_V2_OUT_MCFW_BUILD_NAME_LEN 641645/* The SUC firmware version as four numbers - a.b.c.d */1646#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_VERSION_OFST 1401647#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_VERSION_LEN 41648#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_VERSION_NUM 41649/* SUC firmware build date (as 64-bit Unix timestamp) */1650#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_BUILD_DATE_OFST 1561651#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_BUILD_DATE_LEN 81652#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_BUILD_DATE_LO_OFST 1561653#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_BUILD_DATE_HI_OFST 1601654/* The ID of the SUC chip. This is specific to the platform but typically1655 * indicates family, memory sizes etc. See SF-116728-SW for further details.1656 */1657#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_CHIP_ID_OFST 1641658#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_CHIP_ID_LEN 41659/* The CMC firmware version as four numbers - a.b.c.d */1660#define MC_CMD_GET_VERSION_V2_OUT_CMCFW_VERSION_OFST 1681661#define MC_CMD_GET_VERSION_V2_OUT_CMCFW_VERSION_LEN 41662#define MC_CMD_GET_VERSION_V2_OUT_CMCFW_VERSION_NUM 41663/* CMC firmware build date (as 64-bit Unix timestamp) */1664#define MC_CMD_GET_VERSION_V2_OUT_CMCFW_BUILD_DATE_OFST 1841665#define MC_CMD_GET_VERSION_V2_OUT_CMCFW_BUILD_DATE_LEN 81666#define MC_CMD_GET_VERSION_V2_OUT_CMCFW_BUILD_DATE_LO_OFST 1841667#define MC_CMD_GET_VERSION_V2_OUT_CMCFW_BUILD_DATE_HI_OFST 1881668/* FPGA version as three numbers. On Riverhead based systems this field uses1669 * the same encoding as hardware version ID registers (MC_FPGA_BUILD_HWRD_REG):1670 * FPGA_VERSION[0]: x => Image H{x} FPGA_VERSION[1]: Revision letter (0 => A, 11671 * => B, ...) FPGA_VERSION[2]: Sub-revision number1672 */1673#define MC_CMD_GET_VERSION_V2_OUT_FPGA_VERSION_OFST 1921674#define MC_CMD_GET_VERSION_V2_OUT_FPGA_VERSION_LEN 41675#define MC_CMD_GET_VERSION_V2_OUT_FPGA_VERSION_NUM 31676/* Extra FPGA revision information (as null-terminated US-ASCII string) */1677#define MC_CMD_GET_VERSION_V2_OUT_FPGA_EXTRA_OFST 2041678#define MC_CMD_GET_VERSION_V2_OUT_FPGA_EXTRA_LEN 161679/* Board name / adapter model (as null-terminated US-ASCII string) */1680#define MC_CMD_GET_VERSION_V2_OUT_BOARD_NAME_OFST 2201681#define MC_CMD_GET_VERSION_V2_OUT_BOARD_NAME_LEN 161682/* Board revision number */1683#define MC_CMD_GET_VERSION_V2_OUT_BOARD_REVISION_OFST 2361684#define MC_CMD_GET_VERSION_V2_OUT_BOARD_REVISION_LEN 41685/* Board serial number (as null-terminated US-ASCII string) */1686#define MC_CMD_GET_VERSION_V2_OUT_BOARD_SERIAL_OFST 2401687#define MC_CMD_GET_VERSION_V2_OUT_BOARD_SERIAL_LEN 641688 1689 1690/***********************************/1691/* MC_CMD_PTP1692 * Perform PTP operation1693 */1694#define MC_CMD_PTP 0xb1695#undef MC_CMD_0xb_PRIVILEGE_CTG1696 1697#define MC_CMD_0xb_PRIVILEGE_CTG SRIOV_CTG_GENERAL1698 1699/* MC_CMD_PTP_IN msgrequest */1700#define MC_CMD_PTP_IN_LEN 11701/* PTP operation code */1702#define MC_CMD_PTP_IN_OP_OFST 01703#define MC_CMD_PTP_IN_OP_LEN 11704/* enum: Enable PTP packet timestamping operation. */1705#define MC_CMD_PTP_OP_ENABLE 0x11706/* enum: Disable PTP packet timestamping operation. */1707#define MC_CMD_PTP_OP_DISABLE 0x21708/* enum: Send a PTP packet. This operation is used on Siena and Huntington.1709 * From Medford onwards it is not supported: on those platforms PTP transmit1710 * timestamping is done using the fast path.1711 */1712#define MC_CMD_PTP_OP_TRANSMIT 0x31713/* enum: Read the current NIC time. */1714#define MC_CMD_PTP_OP_READ_NIC_TIME 0x41715/* enum: Get the current PTP status. Note that the clock frequency returned (in1716 * Hz) is rounded to the nearest MHz (e.g. 666000000 for 666666666).1717 */1718#define MC_CMD_PTP_OP_STATUS 0x51719/* enum: Adjust the PTP NIC's time. */1720#define MC_CMD_PTP_OP_ADJUST 0x61721/* enum: Synchronize host and NIC time. */1722#define MC_CMD_PTP_OP_SYNCHRONIZE 0x71723/* enum: Basic manufacturing tests. Siena PTP adapters only. */1724#define MC_CMD_PTP_OP_MANFTEST_BASIC 0x81725/* enum: Packet based manufacturing tests. Siena PTP adapters only. */1726#define MC_CMD_PTP_OP_MANFTEST_PACKET 0x91727/* enum: Reset some of the PTP related statistics */1728#define MC_CMD_PTP_OP_RESET_STATS 0xa1729/* enum: Debug operations to MC. */1730#define MC_CMD_PTP_OP_DEBUG 0xb1731/* enum: Read an FPGA register. Siena PTP adapters only. */1732#define MC_CMD_PTP_OP_FPGAREAD 0xc1733/* enum: Write an FPGA register. Siena PTP adapters only. */1734#define MC_CMD_PTP_OP_FPGAWRITE 0xd1735/* enum: Apply an offset to the NIC clock */1736#define MC_CMD_PTP_OP_CLOCK_OFFSET_ADJUST 0xe1737/* enum: Change the frequency correction applied to the NIC clock */1738#define MC_CMD_PTP_OP_CLOCK_FREQ_ADJUST 0xf1739/* enum: Set the MC packet filter VLAN tags for received PTP packets.1740 * Deprecated for Huntington onwards.1741 */1742#define MC_CMD_PTP_OP_RX_SET_VLAN_FILTER 0x101743/* enum: Set the MC packet filter UUID for received PTP packets. Deprecated for1744 * Huntington onwards.1745 */1746#define MC_CMD_PTP_OP_RX_SET_UUID_FILTER 0x111747/* enum: Set the MC packet filter Domain for received PTP packets. Deprecated1748 * for Huntington onwards.1749 */1750#define MC_CMD_PTP_OP_RX_SET_DOMAIN_FILTER 0x121751/* enum: Set the clock source. Required for snapper tests on Huntington and1752 * Medford. Not implemented for Siena or Medford2.1753 */1754#define MC_CMD_PTP_OP_SET_CLK_SRC 0x131755/* enum: Reset value of Timer Reg. Not implemented. */1756#define MC_CMD_PTP_OP_RST_CLK 0x141757/* enum: Enable the forwarding of PPS events to the host */1758#define MC_CMD_PTP_OP_PPS_ENABLE 0x151759/* enum: Get the time format used by this NIC for PTP operations */1760#define MC_CMD_PTP_OP_GET_TIME_FORMAT 0x161761/* enum: Get the clock attributes. NOTE- extended version of1762 * MC_CMD_PTP_OP_GET_TIME_FORMAT1763 */1764#define MC_CMD_PTP_OP_GET_ATTRIBUTES 0x161765/* enum: Get corrections that should be applied to the various different1766 * timestamps1767 */1768#define MC_CMD_PTP_OP_GET_TIMESTAMP_CORRECTIONS 0x171769/* enum: Subscribe to receive periodic time events indicating the current NIC1770 * time1771 */1772#define MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE 0x181773/* enum: Unsubscribe to stop receiving time events */1774#define MC_CMD_PTP_OP_TIME_EVENT_UNSUBSCRIBE 0x191775/* enum: PPS based manfacturing tests. Requires PPS output to be looped to PPS1776 * input on the same NIC. Siena PTP adapters only.1777 */1778#define MC_CMD_PTP_OP_MANFTEST_PPS 0x1a1779/* enum: Set the PTP sync status. Status is used by firmware to report to event1780 * subscribers.1781 */1782#define MC_CMD_PTP_OP_SET_SYNC_STATUS 0x1b1783/* enum: Above this for future use. */1784#define MC_CMD_PTP_OP_MAX 0x1c1785 1786/* MC_CMD_PTP_IN_ENABLE msgrequest */1787#define MC_CMD_PTP_IN_ENABLE_LEN 161788#define MC_CMD_PTP_IN_CMD_OFST 01789#define MC_CMD_PTP_IN_CMD_LEN 41790#define MC_CMD_PTP_IN_PERIPH_ID_OFST 41791#define MC_CMD_PTP_IN_PERIPH_ID_LEN 41792/* Not used. Events are always sent to function relative queue 0. */1793#define MC_CMD_PTP_IN_ENABLE_QUEUE_OFST 81794#define MC_CMD_PTP_IN_ENABLE_QUEUE_LEN 41795/* PTP timestamping mode. Not used from Huntington onwards. */1796#define MC_CMD_PTP_IN_ENABLE_MODE_OFST 121797#define MC_CMD_PTP_IN_ENABLE_MODE_LEN 41798/* enum: PTP, version 1 */1799#define MC_CMD_PTP_MODE_V1 0x01800/* enum: PTP, version 1, with VLAN headers - deprecated */1801#define MC_CMD_PTP_MODE_V1_VLAN 0x11802/* enum: PTP, version 2 */1803#define MC_CMD_PTP_MODE_V2 0x21804/* enum: PTP, version 2, with VLAN headers - deprecated */1805#define MC_CMD_PTP_MODE_V2_VLAN 0x31806/* enum: PTP, version 2, with improved UUID filtering */1807#define MC_CMD_PTP_MODE_V2_ENHANCED 0x41808/* enum: FCoE (seconds and microseconds) */1809#define MC_CMD_PTP_MODE_FCOE 0x51810 1811/* MC_CMD_PTP_IN_DISABLE msgrequest */1812#define MC_CMD_PTP_IN_DISABLE_LEN 81813/* MC_CMD_PTP_IN_CMD_OFST 0 */1814/* MC_CMD_PTP_IN_CMD_LEN 4 */1815/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */1816/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */1817 1818/* MC_CMD_PTP_IN_TRANSMIT msgrequest */1819#define MC_CMD_PTP_IN_TRANSMIT_LENMIN 131820#define MC_CMD_PTP_IN_TRANSMIT_LENMAX 2521821#define MC_CMD_PTP_IN_TRANSMIT_LENMAX_MCDI2 10201822#define MC_CMD_PTP_IN_TRANSMIT_LEN(num) (12+1*(num))1823#define MC_CMD_PTP_IN_TRANSMIT_PACKET_NUM(len) (((len)-12)/1)1824/* MC_CMD_PTP_IN_CMD_OFST 0 */1825/* MC_CMD_PTP_IN_CMD_LEN 4 */1826/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */1827/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */1828/* Transmit packet length */1829#define MC_CMD_PTP_IN_TRANSMIT_LENGTH_OFST 81830#define MC_CMD_PTP_IN_TRANSMIT_LENGTH_LEN 41831/* Transmit packet data */1832#define MC_CMD_PTP_IN_TRANSMIT_PACKET_OFST 121833#define MC_CMD_PTP_IN_TRANSMIT_PACKET_LEN 11834#define MC_CMD_PTP_IN_TRANSMIT_PACKET_MINNUM 11835#define MC_CMD_PTP_IN_TRANSMIT_PACKET_MAXNUM 2401836#define MC_CMD_PTP_IN_TRANSMIT_PACKET_MAXNUM_MCDI2 10081837 1838/* MC_CMD_PTP_IN_READ_NIC_TIME msgrequest */1839#define MC_CMD_PTP_IN_READ_NIC_TIME_LEN 81840/* MC_CMD_PTP_IN_CMD_OFST 0 */1841/* MC_CMD_PTP_IN_CMD_LEN 4 */1842/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */1843/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */1844 1845/* MC_CMD_PTP_IN_READ_NIC_TIME_V2 msgrequest */1846#define MC_CMD_PTP_IN_READ_NIC_TIME_V2_LEN 81847/* MC_CMD_PTP_IN_CMD_OFST 0 */1848/* MC_CMD_PTP_IN_CMD_LEN 4 */1849/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */1850/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */1851 1852/* MC_CMD_PTP_IN_STATUS msgrequest */1853#define MC_CMD_PTP_IN_STATUS_LEN 81854/* MC_CMD_PTP_IN_CMD_OFST 0 */1855/* MC_CMD_PTP_IN_CMD_LEN 4 */1856/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */1857/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */1858 1859/* MC_CMD_PTP_IN_ADJUST msgrequest */1860#define MC_CMD_PTP_IN_ADJUST_LEN 241861/* MC_CMD_PTP_IN_CMD_OFST 0 */1862/* MC_CMD_PTP_IN_CMD_LEN 4 */1863/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */1864/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */1865/* Frequency adjustment 40 bit fixed point ns */1866#define MC_CMD_PTP_IN_ADJUST_FREQ_OFST 81867#define MC_CMD_PTP_IN_ADJUST_FREQ_LEN 81868#define MC_CMD_PTP_IN_ADJUST_FREQ_LO_OFST 81869#define MC_CMD_PTP_IN_ADJUST_FREQ_HI_OFST 121870/* enum: Number of fractional bits in frequency adjustment */1871#define MC_CMD_PTP_IN_ADJUST_BITS 0x281872/* enum: Number of fractional bits in frequency adjustment when FP44_FREQ_ADJ1873 * is indicated in the MC_CMD_PTP_OUT_GET_ATTRIBUTES command CAPABILITIES1874 * field.1875 */1876#define MC_CMD_PTP_IN_ADJUST_BITS_FP44 0x2c1877/* Time adjustment in seconds */1878#define MC_CMD_PTP_IN_ADJUST_SECONDS_OFST 161879#define MC_CMD_PTP_IN_ADJUST_SECONDS_LEN 41880/* Time adjustment major value */1881#define MC_CMD_PTP_IN_ADJUST_MAJOR_OFST 161882#define MC_CMD_PTP_IN_ADJUST_MAJOR_LEN 41883/* Time adjustment in nanoseconds */1884#define MC_CMD_PTP_IN_ADJUST_NANOSECONDS_OFST 201885#define MC_CMD_PTP_IN_ADJUST_NANOSECONDS_LEN 41886/* Time adjustment minor value */1887#define MC_CMD_PTP_IN_ADJUST_MINOR_OFST 201888#define MC_CMD_PTP_IN_ADJUST_MINOR_LEN 41889 1890/* MC_CMD_PTP_IN_ADJUST_V2 msgrequest */1891#define MC_CMD_PTP_IN_ADJUST_V2_LEN 281892/* MC_CMD_PTP_IN_CMD_OFST 0 */1893/* MC_CMD_PTP_IN_CMD_LEN 4 */1894/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */1895/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */1896/* Frequency adjustment 40 bit fixed point ns */1897#define MC_CMD_PTP_IN_ADJUST_V2_FREQ_OFST 81898#define MC_CMD_PTP_IN_ADJUST_V2_FREQ_LEN 81899#define MC_CMD_PTP_IN_ADJUST_V2_FREQ_LO_OFST 81900#define MC_CMD_PTP_IN_ADJUST_V2_FREQ_HI_OFST 121901/* enum: Number of fractional bits in frequency adjustment */1902/* MC_CMD_PTP_IN_ADJUST_BITS 0x28 */1903/* enum: Number of fractional bits in frequency adjustment when FP44_FREQ_ADJ1904 * is indicated in the MC_CMD_PTP_OUT_GET_ATTRIBUTES command CAPABILITIES1905 * field.1906 */1907/* MC_CMD_PTP_IN_ADJUST_BITS_FP44 0x2c */1908/* Time adjustment in seconds */1909#define MC_CMD_PTP_IN_ADJUST_V2_SECONDS_OFST 161910#define MC_CMD_PTP_IN_ADJUST_V2_SECONDS_LEN 41911/* Time adjustment major value */1912#define MC_CMD_PTP_IN_ADJUST_V2_MAJOR_OFST 161913#define MC_CMD_PTP_IN_ADJUST_V2_MAJOR_LEN 41914/* Time adjustment in nanoseconds */1915#define MC_CMD_PTP_IN_ADJUST_V2_NANOSECONDS_OFST 201916#define MC_CMD_PTP_IN_ADJUST_V2_NANOSECONDS_LEN 41917/* Time adjustment minor value */1918#define MC_CMD_PTP_IN_ADJUST_V2_MINOR_OFST 201919#define MC_CMD_PTP_IN_ADJUST_V2_MINOR_LEN 41920/* Upper 32bits of major time offset adjustment */1921#define MC_CMD_PTP_IN_ADJUST_V2_MAJOR_HI_OFST 241922#define MC_CMD_PTP_IN_ADJUST_V2_MAJOR_HI_LEN 41923 1924/* MC_CMD_PTP_IN_SYNCHRONIZE msgrequest */1925#define MC_CMD_PTP_IN_SYNCHRONIZE_LEN 201926/* MC_CMD_PTP_IN_CMD_OFST 0 */1927/* MC_CMD_PTP_IN_CMD_LEN 4 */1928/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */1929/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */1930/* Number of time readings to capture */1931#define MC_CMD_PTP_IN_SYNCHRONIZE_NUMTIMESETS_OFST 81932#define MC_CMD_PTP_IN_SYNCHRONIZE_NUMTIMESETS_LEN 41933/* Host address in which to write "synchronization started" indication (641934 * bits)1935 */1936#define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_OFST 121937#define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LEN 81938#define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LO_OFST 121939#define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_HI_OFST 161940 1941/* MC_CMD_PTP_IN_MANFTEST_BASIC msgrequest */1942#define MC_CMD_PTP_IN_MANFTEST_BASIC_LEN 81943/* MC_CMD_PTP_IN_CMD_OFST 0 */1944/* MC_CMD_PTP_IN_CMD_LEN 4 */1945/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */1946/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */1947 1948/* MC_CMD_PTP_IN_MANFTEST_PACKET msgrequest */1949#define MC_CMD_PTP_IN_MANFTEST_PACKET_LEN 121950/* MC_CMD_PTP_IN_CMD_OFST 0 */1951/* MC_CMD_PTP_IN_CMD_LEN 4 */1952/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */1953/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */1954/* Enable or disable packet testing */1955#define MC_CMD_PTP_IN_MANFTEST_PACKET_TEST_ENABLE_OFST 81956#define MC_CMD_PTP_IN_MANFTEST_PACKET_TEST_ENABLE_LEN 41957 1958/* MC_CMD_PTP_IN_RESET_STATS msgrequest: Reset PTP statistics */1959#define MC_CMD_PTP_IN_RESET_STATS_LEN 81960/* MC_CMD_PTP_IN_CMD_OFST 0 */1961/* MC_CMD_PTP_IN_CMD_LEN 4 */1962/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */1963/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */1964 1965/* MC_CMD_PTP_IN_DEBUG msgrequest */1966#define MC_CMD_PTP_IN_DEBUG_LEN 121967/* MC_CMD_PTP_IN_CMD_OFST 0 */1968/* MC_CMD_PTP_IN_CMD_LEN 4 */1969/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */1970/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */1971/* Debug operations */1972#define MC_CMD_PTP_IN_DEBUG_DEBUG_PARAM_OFST 81973#define MC_CMD_PTP_IN_DEBUG_DEBUG_PARAM_LEN 41974 1975/* MC_CMD_PTP_IN_FPGAREAD msgrequest */1976#define MC_CMD_PTP_IN_FPGAREAD_LEN 161977/* MC_CMD_PTP_IN_CMD_OFST 0 */1978/* MC_CMD_PTP_IN_CMD_LEN 4 */1979/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */1980/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */1981#define MC_CMD_PTP_IN_FPGAREAD_ADDR_OFST 81982#define MC_CMD_PTP_IN_FPGAREAD_ADDR_LEN 41983#define MC_CMD_PTP_IN_FPGAREAD_NUMBYTES_OFST 121984#define MC_CMD_PTP_IN_FPGAREAD_NUMBYTES_LEN 41985 1986/* MC_CMD_PTP_IN_FPGAWRITE msgrequest */1987#define MC_CMD_PTP_IN_FPGAWRITE_LENMIN 131988#define MC_CMD_PTP_IN_FPGAWRITE_LENMAX 2521989#define MC_CMD_PTP_IN_FPGAWRITE_LENMAX_MCDI2 10201990#define MC_CMD_PTP_IN_FPGAWRITE_LEN(num) (12+1*(num))1991#define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_NUM(len) (((len)-12)/1)1992/* MC_CMD_PTP_IN_CMD_OFST 0 */1993/* MC_CMD_PTP_IN_CMD_LEN 4 */1994/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */1995/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */1996#define MC_CMD_PTP_IN_FPGAWRITE_ADDR_OFST 81997#define MC_CMD_PTP_IN_FPGAWRITE_ADDR_LEN 41998#define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_OFST 121999#define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_LEN 12000#define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_MINNUM 12001#define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_MAXNUM 2402002#define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_MAXNUM_MCDI2 10082003 2004/* MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST msgrequest */2005#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_LEN 162006/* MC_CMD_PTP_IN_CMD_OFST 0 */2007/* MC_CMD_PTP_IN_CMD_LEN 4 */2008/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */2009/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */2010/* Time adjustment in seconds */2011#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_SECONDS_OFST 82012#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_SECONDS_LEN 42013/* Time adjustment major value */2014#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_MAJOR_OFST 82015#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_MAJOR_LEN 42016/* Time adjustment in nanoseconds */2017#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_NANOSECONDS_OFST 122018#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_NANOSECONDS_LEN 42019/* Time adjustment minor value */2020#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_MINOR_OFST 122021#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_MINOR_LEN 42022 2023/* MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2 msgrequest */2024#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_LEN 202025/* MC_CMD_PTP_IN_CMD_OFST 0 */2026/* MC_CMD_PTP_IN_CMD_LEN 4 */2027/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */2028/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */2029/* Time adjustment in seconds */2030#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_SECONDS_OFST 82031#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_SECONDS_LEN 42032/* Time adjustment major value */2033#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_MAJOR_OFST 82034#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_MAJOR_LEN 42035/* Time adjustment in nanoseconds */2036#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_NANOSECONDS_OFST 122037#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_NANOSECONDS_LEN 42038/* Time adjustment minor value */2039#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_MINOR_OFST 122040#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_MINOR_LEN 42041/* Upper 32bits of major time offset adjustment */2042#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_MAJOR_HI_OFST 162043#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_MAJOR_HI_LEN 42044 2045/* MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST msgrequest */2046#define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_LEN 162047/* MC_CMD_PTP_IN_CMD_OFST 0 */2048/* MC_CMD_PTP_IN_CMD_LEN 4 */2049/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */2050/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */2051/* Frequency adjustment 40 bit fixed point ns */2052#define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_OFST 82053#define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_LEN 82054#define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_LO_OFST 82055#define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_HI_OFST 122056/* Enum values, see field(s): */2057/* MC_CMD_PTP/MC_CMD_PTP_IN_ADJUST/FREQ */2058 2059/* MC_CMD_PTP_IN_RX_SET_VLAN_FILTER msgrequest */2060#define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_LEN 242061/* MC_CMD_PTP_IN_CMD_OFST 0 */2062/* MC_CMD_PTP_IN_CMD_LEN 4 */2063/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */2064/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */2065/* Number of VLAN tags, 0 if not VLAN */2066#define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_NUM_VLAN_TAGS_OFST 82067#define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_NUM_VLAN_TAGS_LEN 42068/* Set of VLAN tags to filter against */2069#define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_OFST 122070#define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_LEN 42071#define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_NUM 32072 2073/* MC_CMD_PTP_IN_RX_SET_UUID_FILTER msgrequest */2074#define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_LEN 202075/* MC_CMD_PTP_IN_CMD_OFST 0 */2076/* MC_CMD_PTP_IN_CMD_LEN 4 */2077/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */2078/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */2079/* 1 to enable UUID filtering, 0 to disable */2080#define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_ENABLE_OFST 82081#define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_ENABLE_LEN 42082/* UUID to filter against */2083#define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_OFST 122084#define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_LEN 82085#define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_LO_OFST 122086#define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_HI_OFST 162087 2088/* MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER msgrequest */2089#define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_LEN 162090/* MC_CMD_PTP_IN_CMD_OFST 0 */2091/* MC_CMD_PTP_IN_CMD_LEN 4 */2092/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */2093/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */2094/* 1 to enable Domain filtering, 0 to disable */2095#define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_ENABLE_OFST 82096#define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_ENABLE_LEN 42097/* Domain number to filter against */2098#define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_DOMAIN_OFST 122099#define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_DOMAIN_LEN 42100 2101/* MC_CMD_PTP_IN_SET_CLK_SRC msgrequest */2102#define MC_CMD_PTP_IN_SET_CLK_SRC_LEN 122103/* MC_CMD_PTP_IN_CMD_OFST 0 */2104/* MC_CMD_PTP_IN_CMD_LEN 4 */2105/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */2106/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */2107/* Set the clock source. */2108#define MC_CMD_PTP_IN_SET_CLK_SRC_CLK_OFST 82109#define MC_CMD_PTP_IN_SET_CLK_SRC_CLK_LEN 42110/* enum: Internal. */2111#define MC_CMD_PTP_CLK_SRC_INTERNAL 0x02112/* enum: External. */2113#define MC_CMD_PTP_CLK_SRC_EXTERNAL 0x12114 2115/* MC_CMD_PTP_IN_RST_CLK msgrequest: Reset value of Timer Reg. */2116#define MC_CMD_PTP_IN_RST_CLK_LEN 82117/* MC_CMD_PTP_IN_CMD_OFST 0 */2118/* MC_CMD_PTP_IN_CMD_LEN 4 */2119/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */2120/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */2121 2122/* MC_CMD_PTP_IN_PPS_ENABLE msgrequest */2123#define MC_CMD_PTP_IN_PPS_ENABLE_LEN 122124/* MC_CMD_PTP_IN_CMD_OFST 0 */2125/* MC_CMD_PTP_IN_CMD_LEN 4 */2126/* Enable or disable */2127#define MC_CMD_PTP_IN_PPS_ENABLE_OP_OFST 42128#define MC_CMD_PTP_IN_PPS_ENABLE_OP_LEN 42129/* enum: Enable */2130#define MC_CMD_PTP_ENABLE_PPS 0x02131/* enum: Disable */2132#define MC_CMD_PTP_DISABLE_PPS 0x12133/* Not used. Events are always sent to function relative queue 0. */2134#define MC_CMD_PTP_IN_PPS_ENABLE_QUEUE_ID_OFST 82135#define MC_CMD_PTP_IN_PPS_ENABLE_QUEUE_ID_LEN 42136 2137/* MC_CMD_PTP_IN_GET_TIME_FORMAT msgrequest */2138#define MC_CMD_PTP_IN_GET_TIME_FORMAT_LEN 82139/* MC_CMD_PTP_IN_CMD_OFST 0 */2140/* MC_CMD_PTP_IN_CMD_LEN 4 */2141/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */2142/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */2143 2144/* MC_CMD_PTP_IN_GET_ATTRIBUTES msgrequest */2145#define MC_CMD_PTP_IN_GET_ATTRIBUTES_LEN 82146/* MC_CMD_PTP_IN_CMD_OFST 0 */2147/* MC_CMD_PTP_IN_CMD_LEN 4 */2148/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */2149/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */2150 2151/* MC_CMD_PTP_IN_GET_TIMESTAMP_CORRECTIONS msgrequest */2152#define MC_CMD_PTP_IN_GET_TIMESTAMP_CORRECTIONS_LEN 82153/* MC_CMD_PTP_IN_CMD_OFST 0 */2154/* MC_CMD_PTP_IN_CMD_LEN 4 */2155/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */2156/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */2157 2158/* MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE msgrequest */2159#define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_LEN 122160/* MC_CMD_PTP_IN_CMD_OFST 0 */2161/* MC_CMD_PTP_IN_CMD_LEN 4 */2162/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */2163/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */2164/* Original field containing queue ID. Now extended to include flags. */2165#define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_OFST 82166#define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_LEN 42167#define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_ID_OFST 82168#define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_ID_LBN 02169#define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_ID_WIDTH 162170#define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_REPORT_SYNC_STATUS_OFST 82171#define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_REPORT_SYNC_STATUS_LBN 312172#define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_REPORT_SYNC_STATUS_WIDTH 12173 2174/* MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE msgrequest */2175#define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_LEN 162176/* MC_CMD_PTP_IN_CMD_OFST 0 */2177/* MC_CMD_PTP_IN_CMD_LEN 4 */2178/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */2179/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */2180/* Unsubscribe options */2181#define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL_OFST 82182#define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL_LEN 42183/* enum: Unsubscribe a single queue */2184#define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_SINGLE 0x02185/* enum: Unsubscribe all queues */2186#define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_ALL 0x12187/* Event queue ID */2188#define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE_OFST 122189#define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE_LEN 42190 2191/* MC_CMD_PTP_IN_MANFTEST_PPS msgrequest */2192#define MC_CMD_PTP_IN_MANFTEST_PPS_LEN 122193/* MC_CMD_PTP_IN_CMD_OFST 0 */2194/* MC_CMD_PTP_IN_CMD_LEN 4 */2195/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */2196/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */2197/* 1 to enable PPS test mode, 0 to disable and return result. */2198#define MC_CMD_PTP_IN_MANFTEST_PPS_TEST_ENABLE_OFST 82199#define MC_CMD_PTP_IN_MANFTEST_PPS_TEST_ENABLE_LEN 42200 2201/* MC_CMD_PTP_IN_SET_SYNC_STATUS msgrequest */2202#define MC_CMD_PTP_IN_SET_SYNC_STATUS_LEN 242203/* MC_CMD_PTP_IN_CMD_OFST 0 */2204/* MC_CMD_PTP_IN_CMD_LEN 4 */2205/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */2206/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */2207/* NIC - Host System Clock Synchronization status */2208#define MC_CMD_PTP_IN_SET_SYNC_STATUS_STATUS_OFST 82209#define MC_CMD_PTP_IN_SET_SYNC_STATUS_STATUS_LEN 42210/* enum: Host System clock and NIC clock are not in sync */2211#define MC_CMD_PTP_IN_SET_SYNC_STATUS_NOT_IN_SYNC 0x02212/* enum: Host System clock and NIC clock are synchronized */2213#define MC_CMD_PTP_IN_SET_SYNC_STATUS_IN_SYNC 0x12214/* If synchronized, number of seconds until clocks should be considered to be2215 * no longer in sync.2216 */2217#define MC_CMD_PTP_IN_SET_SYNC_STATUS_TIMEOUT_OFST 122218#define MC_CMD_PTP_IN_SET_SYNC_STATUS_TIMEOUT_LEN 42219#define MC_CMD_PTP_IN_SET_SYNC_STATUS_RESERVED0_OFST 162220#define MC_CMD_PTP_IN_SET_SYNC_STATUS_RESERVED0_LEN 42221#define MC_CMD_PTP_IN_SET_SYNC_STATUS_RESERVED1_OFST 202222#define MC_CMD_PTP_IN_SET_SYNC_STATUS_RESERVED1_LEN 42223 2224/* MC_CMD_PTP_OUT msgresponse */2225#define MC_CMD_PTP_OUT_LEN 02226 2227/* MC_CMD_PTP_OUT_TRANSMIT msgresponse */2228#define MC_CMD_PTP_OUT_TRANSMIT_LEN 82229/* Value of seconds timestamp */2230#define MC_CMD_PTP_OUT_TRANSMIT_SECONDS_OFST 02231#define MC_CMD_PTP_OUT_TRANSMIT_SECONDS_LEN 42232/* Timestamp major value */2233#define MC_CMD_PTP_OUT_TRANSMIT_MAJOR_OFST 02234#define MC_CMD_PTP_OUT_TRANSMIT_MAJOR_LEN 42235/* Value of nanoseconds timestamp */2236#define MC_CMD_PTP_OUT_TRANSMIT_NANOSECONDS_OFST 42237#define MC_CMD_PTP_OUT_TRANSMIT_NANOSECONDS_LEN 42238/* Timestamp minor value */2239#define MC_CMD_PTP_OUT_TRANSMIT_MINOR_OFST 42240#define MC_CMD_PTP_OUT_TRANSMIT_MINOR_LEN 42241 2242/* MC_CMD_PTP_OUT_TIME_EVENT_SUBSCRIBE msgresponse */2243#define MC_CMD_PTP_OUT_TIME_EVENT_SUBSCRIBE_LEN 02244 2245/* MC_CMD_PTP_OUT_TIME_EVENT_UNSUBSCRIBE msgresponse */2246#define MC_CMD_PTP_OUT_TIME_EVENT_UNSUBSCRIBE_LEN 02247 2248/* MC_CMD_PTP_OUT_READ_NIC_TIME msgresponse */2249#define MC_CMD_PTP_OUT_READ_NIC_TIME_LEN 82250/* Value of seconds timestamp */2251#define MC_CMD_PTP_OUT_READ_NIC_TIME_SECONDS_OFST 02252#define MC_CMD_PTP_OUT_READ_NIC_TIME_SECONDS_LEN 42253/* Timestamp major value */2254#define MC_CMD_PTP_OUT_READ_NIC_TIME_MAJOR_OFST 02255#define MC_CMD_PTP_OUT_READ_NIC_TIME_MAJOR_LEN 42256/* Value of nanoseconds timestamp */2257#define MC_CMD_PTP_OUT_READ_NIC_TIME_NANOSECONDS_OFST 42258#define MC_CMD_PTP_OUT_READ_NIC_TIME_NANOSECONDS_LEN 42259/* Timestamp minor value */2260#define MC_CMD_PTP_OUT_READ_NIC_TIME_MINOR_OFST 42261#define MC_CMD_PTP_OUT_READ_NIC_TIME_MINOR_LEN 42262 2263/* MC_CMD_PTP_OUT_READ_NIC_TIME_V2 msgresponse */2264#define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_LEN 122265/* Value of seconds timestamp */2266#define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_SECONDS_OFST 02267#define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_SECONDS_LEN 42268/* Timestamp major value */2269#define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MAJOR_OFST 02270#define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MAJOR_LEN 42271/* Value of nanoseconds timestamp */2272#define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_NANOSECONDS_OFST 42273#define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_NANOSECONDS_LEN 42274/* Timestamp minor value */2275#define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MINOR_OFST 42276#define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MINOR_LEN 42277/* Upper 32bits of major timestamp value */2278#define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MAJOR_HI_OFST 82279#define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MAJOR_HI_LEN 42280 2281/* MC_CMD_PTP_OUT_STATUS msgresponse */2282#define MC_CMD_PTP_OUT_STATUS_LEN 642283/* Frequency of NIC's hardware clock */2284#define MC_CMD_PTP_OUT_STATUS_CLOCK_FREQ_OFST 02285#define MC_CMD_PTP_OUT_STATUS_CLOCK_FREQ_LEN 42286/* Number of packets transmitted and timestamped */2287#define MC_CMD_PTP_OUT_STATUS_STATS_TX_OFST 42288#define MC_CMD_PTP_OUT_STATUS_STATS_TX_LEN 42289/* Number of packets received and timestamped */2290#define MC_CMD_PTP_OUT_STATUS_STATS_RX_OFST 82291#define MC_CMD_PTP_OUT_STATUS_STATS_RX_LEN 42292/* Number of packets timestamped by the FPGA */2293#define MC_CMD_PTP_OUT_STATUS_STATS_TS_OFST 122294#define MC_CMD_PTP_OUT_STATUS_STATS_TS_LEN 42295/* Number of packets filter matched */2296#define MC_CMD_PTP_OUT_STATUS_STATS_FM_OFST 162297#define MC_CMD_PTP_OUT_STATUS_STATS_FM_LEN 42298/* Number of packets not filter matched */2299#define MC_CMD_PTP_OUT_STATUS_STATS_NFM_OFST 202300#define MC_CMD_PTP_OUT_STATUS_STATS_NFM_LEN 42301/* Number of PPS overflows (noise on input?) */2302#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFLOW_OFST 242303#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFLOW_LEN 42304/* Number of PPS bad periods */2305#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_BAD_OFST 282306#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_BAD_LEN 42307/* Minimum period of PPS pulse in nanoseconds */2308#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MIN_OFST 322309#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MIN_LEN 42310/* Maximum period of PPS pulse in nanoseconds */2311#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MAX_OFST 362312#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MAX_LEN 42313/* Last period of PPS pulse in nanoseconds */2314#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_LAST_OFST 402315#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_LAST_LEN 42316/* Mean period of PPS pulse in nanoseconds */2317#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MEAN_OFST 442318#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MEAN_LEN 42319/* Minimum offset of PPS pulse in nanoseconds (signed) */2320#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MIN_OFST 482321#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MIN_LEN 42322/* Maximum offset of PPS pulse in nanoseconds (signed) */2323#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MAX_OFST 522324#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MAX_LEN 42325/* Last offset of PPS pulse in nanoseconds (signed) */2326#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_LAST_OFST 562327#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_LAST_LEN 42328/* Mean offset of PPS pulse in nanoseconds (signed) */2329#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MEAN_OFST 602330#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MEAN_LEN 42331 2332/* MC_CMD_PTP_OUT_SYNCHRONIZE msgresponse */2333#define MC_CMD_PTP_OUT_SYNCHRONIZE_LENMIN 202334#define MC_CMD_PTP_OUT_SYNCHRONIZE_LENMAX 2402335#define MC_CMD_PTP_OUT_SYNCHRONIZE_LENMAX_MCDI2 10202336#define MC_CMD_PTP_OUT_SYNCHRONIZE_LEN(num) (0+20*(num))2337#define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_NUM(len) (((len)-0)/20)2338/* A set of host and NIC times */2339#define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_OFST 02340#define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_LEN 202341#define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_MINNUM 12342#define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_MAXNUM 122343#define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_MAXNUM_MCDI2 512344/* Host time immediately before NIC's hardware clock read */2345#define MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTSTART_OFST 02346#define MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTSTART_LEN 42347/* Value of seconds timestamp */2348#define MC_CMD_PTP_OUT_SYNCHRONIZE_SECONDS_OFST 42349#define MC_CMD_PTP_OUT_SYNCHRONIZE_SECONDS_LEN 42350/* Timestamp major value */2351#define MC_CMD_PTP_OUT_SYNCHRONIZE_MAJOR_OFST 42352#define MC_CMD_PTP_OUT_SYNCHRONIZE_MAJOR_LEN 42353/* Value of nanoseconds timestamp */2354#define MC_CMD_PTP_OUT_SYNCHRONIZE_NANOSECONDS_OFST 82355#define MC_CMD_PTP_OUT_SYNCHRONIZE_NANOSECONDS_LEN 42356/* Timestamp minor value */2357#define MC_CMD_PTP_OUT_SYNCHRONIZE_MINOR_OFST 82358#define MC_CMD_PTP_OUT_SYNCHRONIZE_MINOR_LEN 42359/* Host time immediately after NIC's hardware clock read */2360#define MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTEND_OFST 122361#define MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTEND_LEN 42362/* Number of nanoseconds waited after reading NIC's hardware clock */2363#define MC_CMD_PTP_OUT_SYNCHRONIZE_WAITNS_OFST 162364#define MC_CMD_PTP_OUT_SYNCHRONIZE_WAITNS_LEN 42365 2366/* MC_CMD_PTP_OUT_MANFTEST_BASIC msgresponse */2367#define MC_CMD_PTP_OUT_MANFTEST_BASIC_LEN 82368/* Results of testing */2369#define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_RESULT_OFST 02370#define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_RESULT_LEN 42371/* enum: Successful test */2372#define MC_CMD_PTP_MANF_SUCCESS 0x02373/* enum: FPGA load failed */2374#define MC_CMD_PTP_MANF_FPGA_LOAD 0x12375/* enum: FPGA version invalid */2376#define MC_CMD_PTP_MANF_FPGA_VERSION 0x22377/* enum: FPGA registers incorrect */2378#define MC_CMD_PTP_MANF_FPGA_REGISTERS 0x32379/* enum: Oscillator possibly not working? */2380#define MC_CMD_PTP_MANF_OSCILLATOR 0x42381/* enum: Timestamps not increasing */2382#define MC_CMD_PTP_MANF_TIMESTAMPS 0x52383/* enum: Mismatched packet count */2384#define MC_CMD_PTP_MANF_PACKET_COUNT 0x62385/* enum: Mismatched packet count (Siena filter and FPGA) */2386#define MC_CMD_PTP_MANF_FILTER_COUNT 0x72387/* enum: Not enough packets to perform timestamp check */2388#define MC_CMD_PTP_MANF_PACKET_ENOUGH 0x82389/* enum: Timestamp trigger GPIO not working */2390#define MC_CMD_PTP_MANF_GPIO_TRIGGER 0x92391/* enum: Insufficient PPS events to perform checks */2392#define MC_CMD_PTP_MANF_PPS_ENOUGH 0xa2393/* enum: PPS time event period not sufficiently close to 1s. */2394#define MC_CMD_PTP_MANF_PPS_PERIOD 0xb2395/* enum: PPS time event nS reading not sufficiently close to zero. */2396#define MC_CMD_PTP_MANF_PPS_NS 0xc2397/* enum: PTP peripheral registers incorrect */2398#define MC_CMD_PTP_MANF_REGISTERS 0xd2399/* enum: Failed to read time from PTP peripheral */2400#define MC_CMD_PTP_MANF_CLOCK_READ 0xe2401/* Presence of external oscillator */2402#define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_EXTOSC_OFST 42403#define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_EXTOSC_LEN 42404 2405/* MC_CMD_PTP_OUT_MANFTEST_PACKET msgresponse */2406#define MC_CMD_PTP_OUT_MANFTEST_PACKET_LEN 122407/* Results of testing */2408#define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_RESULT_OFST 02409#define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_RESULT_LEN 42410/* Number of packets received by FPGA */2411#define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FPGACOUNT_OFST 42412#define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FPGACOUNT_LEN 42413/* Number of packets received by Siena filters */2414#define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FILTERCOUNT_OFST 82415#define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FILTERCOUNT_LEN 42416 2417/* MC_CMD_PTP_OUT_FPGAREAD msgresponse */2418#define MC_CMD_PTP_OUT_FPGAREAD_LENMIN 12419#define MC_CMD_PTP_OUT_FPGAREAD_LENMAX 2522420#define MC_CMD_PTP_OUT_FPGAREAD_LENMAX_MCDI2 10202421#define MC_CMD_PTP_OUT_FPGAREAD_LEN(num) (0+1*(num))2422#define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_NUM(len) (((len)-0)/1)2423#define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_OFST 02424#define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_LEN 12425#define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_MINNUM 12426#define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_MAXNUM 2522427#define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_MAXNUM_MCDI2 10202428 2429/* MC_CMD_PTP_OUT_GET_TIME_FORMAT msgresponse */2430#define MC_CMD_PTP_OUT_GET_TIME_FORMAT_LEN 42431/* Time format required/used by for this NIC. Applies to all PTP MCDI2432 * operations that pass times between the host and firmware. If this operation2433 * is not supported (older firmware) a format of seconds and nanoseconds should2434 * be assumed. Note this enum is deprecated. Do not add to it- use the2435 * TIME_FORMAT field in MC_CMD_PTP_OUT_GET_ATTRIBUTES instead.2436 */2437#define MC_CMD_PTP_OUT_GET_TIME_FORMAT_FORMAT_OFST 02438#define MC_CMD_PTP_OUT_GET_TIME_FORMAT_FORMAT_LEN 42439/* enum: Times are in seconds and nanoseconds */2440#define MC_CMD_PTP_OUT_GET_TIME_FORMAT_SECONDS_NANOSECONDS 0x02441/* enum: Major register has units of 16 second per tick, minor 8 ns per tick */2442#define MC_CMD_PTP_OUT_GET_TIME_FORMAT_16SECONDS_8NANOSECONDS 0x12443/* enum: Major register has units of seconds, minor 2^-27s per tick */2444#define MC_CMD_PTP_OUT_GET_TIME_FORMAT_SECONDS_27FRACTION 0x22445 2446/* MC_CMD_PTP_OUT_GET_ATTRIBUTES msgresponse */2447#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_LEN 242448/* Time format required/used by for this NIC. Applies to all PTP MCDI2449 * operations that pass times between the host and firmware. If this operation2450 * is not supported (older firmware) a format of seconds and nanoseconds should2451 * be assumed.2452 */2453#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_TIME_FORMAT_OFST 02454#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_TIME_FORMAT_LEN 42455/* enum: Times are in seconds and nanoseconds */2456#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SECONDS_NANOSECONDS 0x02457/* enum: Major register has units of 16 second per tick, minor 8 ns per tick */2458#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_16SECONDS_8NANOSECONDS 0x12459/* enum: Major register has units of seconds, minor 2^-27s per tick */2460#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SECONDS_27FRACTION 0x22461/* enum: Major register units are seconds, minor units are quarter nanoseconds2462 */2463#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SECONDS_QTR_NANOSECONDS 0x32464/* Minimum acceptable value for a corrected synchronization timeset. When2465 * comparing host and NIC clock times, the MC returns a set of samples that2466 * contain the host start and end time, the MC time when the host start was2467 * detected and the time the MC waited between reading the time and detecting2468 * the host end. The corrected sync window is the difference between the host2469 * end and start times minus the time that the MC waited for host end.2470 */2471#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SYNC_WINDOW_MIN_OFST 42472#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SYNC_WINDOW_MIN_LEN 42473/* Various PTP capabilities */2474#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_CAPABILITIES_OFST 82475#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_CAPABILITIES_LEN 42476#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_REPORT_SYNC_STATUS_OFST 82477#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_REPORT_SYNC_STATUS_LBN 02478#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_REPORT_SYNC_STATUS_WIDTH 12479#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RX_TSTAMP_OOB_OFST 82480#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RX_TSTAMP_OOB_LBN 12481#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RX_TSTAMP_OOB_WIDTH 12482#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_64BIT_SECONDS_OFST 82483#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_64BIT_SECONDS_LBN 22484#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_64BIT_SECONDS_WIDTH 12485#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_FP44_FREQ_ADJ_OFST 82486#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_FP44_FREQ_ADJ_LBN 32487#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_FP44_FREQ_ADJ_WIDTH 12488#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED0_OFST 122489#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED0_LEN 42490#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED1_OFST 162491#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED1_LEN 42492#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED2_OFST 202493#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED2_LEN 42494 2495/* MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS msgresponse */2496#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_LEN 162497/* Uncorrected error on PTP transmit timestamps in NIC clock format */2498#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_TRANSMIT_OFST 02499#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_TRANSMIT_LEN 42500/* Uncorrected error on PTP receive timestamps in NIC clock format */2501#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_RECEIVE_OFST 42502#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_RECEIVE_LEN 42503/* Uncorrected error on PPS output in NIC clock format */2504#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_OUT_OFST 82505#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_OUT_LEN 42506/* Uncorrected error on PPS input in NIC clock format */2507#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_IN_OFST 122508#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_IN_LEN 42509 2510/* MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2 msgresponse */2511#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_LEN 242512/* Uncorrected error on PTP transmit timestamps in NIC clock format */2513#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PTP_TX_OFST 02514#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PTP_TX_LEN 42515/* Uncorrected error on PTP receive timestamps in NIC clock format */2516#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PTP_RX_OFST 42517#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PTP_RX_LEN 42518/* Uncorrected error on PPS output in NIC clock format */2519#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PPS_OUT_OFST 82520#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PPS_OUT_LEN 42521/* Uncorrected error on PPS input in NIC clock format */2522#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PPS_IN_OFST 122523#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PPS_IN_LEN 42524/* Uncorrected error on non-PTP transmit timestamps in NIC clock format */2525#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_GENERAL_TX_OFST 162526#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_GENERAL_TX_LEN 42527/* Uncorrected error on non-PTP receive timestamps in NIC clock format */2528#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_GENERAL_RX_OFST 202529#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_GENERAL_RX_LEN 42530 2531/* MC_CMD_PTP_OUT_MANFTEST_PPS msgresponse */2532#define MC_CMD_PTP_OUT_MANFTEST_PPS_LEN 42533/* Results of testing */2534#define MC_CMD_PTP_OUT_MANFTEST_PPS_TEST_RESULT_OFST 02535#define MC_CMD_PTP_OUT_MANFTEST_PPS_TEST_RESULT_LEN 42536/* Enum values, see field(s): */2537/* MC_CMD_PTP_OUT_MANFTEST_BASIC/TEST_RESULT */2538 2539/* MC_CMD_PTP_OUT_SET_SYNC_STATUS msgresponse */2540#define MC_CMD_PTP_OUT_SET_SYNC_STATUS_LEN 02541 2542 2543/***********************************/2544/* MC_CMD_CSR_READ322545 * Read 32bit words from the indirect memory map.2546 */2547#define MC_CMD_CSR_READ32 0xc2548#undef MC_CMD_0xc_PRIVILEGE_CTG2549 2550#define MC_CMD_0xc_PRIVILEGE_CTG SRIOV_CTG_INSECURE2551 2552/* MC_CMD_CSR_READ32_IN msgrequest */2553#define MC_CMD_CSR_READ32_IN_LEN 122554/* Address */2555#define MC_CMD_CSR_READ32_IN_ADDR_OFST 02556#define MC_CMD_CSR_READ32_IN_ADDR_LEN 42557#define MC_CMD_CSR_READ32_IN_STEP_OFST 42558#define MC_CMD_CSR_READ32_IN_STEP_LEN 42559#define MC_CMD_CSR_READ32_IN_NUMWORDS_OFST 82560#define MC_CMD_CSR_READ32_IN_NUMWORDS_LEN 42561 2562/* MC_CMD_CSR_READ32_OUT msgresponse */2563#define MC_CMD_CSR_READ32_OUT_LENMIN 42564#define MC_CMD_CSR_READ32_OUT_LENMAX 2522565#define MC_CMD_CSR_READ32_OUT_LENMAX_MCDI2 10202566#define MC_CMD_CSR_READ32_OUT_LEN(num) (0+4*(num))2567#define MC_CMD_CSR_READ32_OUT_BUFFER_NUM(len) (((len)-0)/4)2568/* The last dword is the status, not a value read */2569#define MC_CMD_CSR_READ32_OUT_BUFFER_OFST 02570#define MC_CMD_CSR_READ32_OUT_BUFFER_LEN 42571#define MC_CMD_CSR_READ32_OUT_BUFFER_MINNUM 12572#define MC_CMD_CSR_READ32_OUT_BUFFER_MAXNUM 632573#define MC_CMD_CSR_READ32_OUT_BUFFER_MAXNUM_MCDI2 2552574 2575 2576/***********************************/2577/* MC_CMD_CSR_WRITE322578 * Write 32bit dwords to the indirect memory map.2579 */2580#define MC_CMD_CSR_WRITE32 0xd2581#undef MC_CMD_0xd_PRIVILEGE_CTG2582 2583#define MC_CMD_0xd_PRIVILEGE_CTG SRIOV_CTG_INSECURE2584 2585/* MC_CMD_CSR_WRITE32_IN msgrequest */2586#define MC_CMD_CSR_WRITE32_IN_LENMIN 122587#define MC_CMD_CSR_WRITE32_IN_LENMAX 2522588#define MC_CMD_CSR_WRITE32_IN_LENMAX_MCDI2 10202589#define MC_CMD_CSR_WRITE32_IN_LEN(num) (8+4*(num))2590#define MC_CMD_CSR_WRITE32_IN_BUFFER_NUM(len) (((len)-8)/4)2591/* Address */2592#define MC_CMD_CSR_WRITE32_IN_ADDR_OFST 02593#define MC_CMD_CSR_WRITE32_IN_ADDR_LEN 42594#define MC_CMD_CSR_WRITE32_IN_STEP_OFST 42595#define MC_CMD_CSR_WRITE32_IN_STEP_LEN 42596#define MC_CMD_CSR_WRITE32_IN_BUFFER_OFST 82597#define MC_CMD_CSR_WRITE32_IN_BUFFER_LEN 42598#define MC_CMD_CSR_WRITE32_IN_BUFFER_MINNUM 12599#define MC_CMD_CSR_WRITE32_IN_BUFFER_MAXNUM 612600#define MC_CMD_CSR_WRITE32_IN_BUFFER_MAXNUM_MCDI2 2532601 2602/* MC_CMD_CSR_WRITE32_OUT msgresponse */2603#define MC_CMD_CSR_WRITE32_OUT_LEN 42604#define MC_CMD_CSR_WRITE32_OUT_STATUS_OFST 02605#define MC_CMD_CSR_WRITE32_OUT_STATUS_LEN 42606 2607 2608/***********************************/2609/* MC_CMD_HP2610 * These commands are used for HP related features. They are grouped under one2611 * MCDI command to avoid creating too many MCDI commands.2612 */2613#define MC_CMD_HP 0x542614#undef MC_CMD_0x54_PRIVILEGE_CTG2615 2616#define MC_CMD_0x54_PRIVILEGE_CTG SRIOV_CTG_ADMIN2617 2618/* MC_CMD_HP_IN msgrequest */2619#define MC_CMD_HP_IN_LEN 162620/* HP OCSD sub-command. When address is not NULL, request activation of OCSD at2621 * the specified address with the specified interval.When address is NULL,2622 * INTERVAL is interpreted as a command: 0: stop OCSD / 1: Report OCSD current2623 * state / 2: (debug) Show temperature reported by one of the supported2624 * sensors.2625 */2626#define MC_CMD_HP_IN_SUBCMD_OFST 02627#define MC_CMD_HP_IN_SUBCMD_LEN 42628/* enum: OCSD (Option Card Sensor Data) sub-command. */2629#define MC_CMD_HP_IN_OCSD_SUBCMD 0x02630/* enum: Last known valid HP sub-command. */2631#define MC_CMD_HP_IN_LAST_SUBCMD 0x02632/* The address to the array of sensor fields. (Or NULL to use a sub-command.)2633 */2634#define MC_CMD_HP_IN_OCSD_ADDR_OFST 42635#define MC_CMD_HP_IN_OCSD_ADDR_LEN 82636#define MC_CMD_HP_IN_OCSD_ADDR_LO_OFST 42637#define MC_CMD_HP_IN_OCSD_ADDR_HI_OFST 82638/* The requested update interval, in seconds. (Or the sub-command if ADDR is2639 * NULL.)2640 */2641#define MC_CMD_HP_IN_OCSD_INTERVAL_OFST 122642#define MC_CMD_HP_IN_OCSD_INTERVAL_LEN 42643 2644/* MC_CMD_HP_OUT msgresponse */2645#define MC_CMD_HP_OUT_LEN 42646#define MC_CMD_HP_OUT_OCSD_STATUS_OFST 02647#define MC_CMD_HP_OUT_OCSD_STATUS_LEN 42648/* enum: OCSD stopped for this card. */2649#define MC_CMD_HP_OUT_OCSD_STOPPED 0x12650/* enum: OCSD was successfully started with the address provided. */2651#define MC_CMD_HP_OUT_OCSD_STARTED 0x22652/* enum: OCSD was already started for this card. */2653#define MC_CMD_HP_OUT_OCSD_ALREADY_STARTED 0x32654 2655 2656/***********************************/2657/* MC_CMD_STACKINFO2658 * Get stack information.2659 */2660#define MC_CMD_STACKINFO 0xf2661#undef MC_CMD_0xf_PRIVILEGE_CTG2662 2663#define MC_CMD_0xf_PRIVILEGE_CTG SRIOV_CTG_ADMIN2664 2665/* MC_CMD_STACKINFO_IN msgrequest */2666#define MC_CMD_STACKINFO_IN_LEN 02667 2668/* MC_CMD_STACKINFO_OUT msgresponse */2669#define MC_CMD_STACKINFO_OUT_LENMIN 122670#define MC_CMD_STACKINFO_OUT_LENMAX 2522671#define MC_CMD_STACKINFO_OUT_LENMAX_MCDI2 10202672#define MC_CMD_STACKINFO_OUT_LEN(num) (0+12*(num))2673#define MC_CMD_STACKINFO_OUT_THREAD_INFO_NUM(len) (((len)-0)/12)2674/* (thread ptr, stack size, free space) for each thread in system */2675#define MC_CMD_STACKINFO_OUT_THREAD_INFO_OFST 02676#define MC_CMD_STACKINFO_OUT_THREAD_INFO_LEN 122677#define MC_CMD_STACKINFO_OUT_THREAD_INFO_MINNUM 12678#define MC_CMD_STACKINFO_OUT_THREAD_INFO_MAXNUM 212679#define MC_CMD_STACKINFO_OUT_THREAD_INFO_MAXNUM_MCDI2 852680 2681 2682/***********************************/2683/* MC_CMD_MDIO_READ2684 * MDIO register read.2685 */2686#define MC_CMD_MDIO_READ 0x102687#undef MC_CMD_0x10_PRIVILEGE_CTG2688 2689#define MC_CMD_0x10_PRIVILEGE_CTG SRIOV_CTG_GENERAL2690 2691/* MC_CMD_MDIO_READ_IN msgrequest */2692#define MC_CMD_MDIO_READ_IN_LEN 162693/* Bus number; there are two MDIO buses: one for the internal PHY, and one for2694 * external devices.2695 */2696#define MC_CMD_MDIO_READ_IN_BUS_OFST 02697#define MC_CMD_MDIO_READ_IN_BUS_LEN 42698/* enum: Internal. */2699#define MC_CMD_MDIO_BUS_INTERNAL 0x02700/* enum: External. */2701#define MC_CMD_MDIO_BUS_EXTERNAL 0x12702/* Port address */2703#define MC_CMD_MDIO_READ_IN_PRTAD_OFST 42704#define MC_CMD_MDIO_READ_IN_PRTAD_LEN 42705/* Device Address or clause 22. */2706#define MC_CMD_MDIO_READ_IN_DEVAD_OFST 82707#define MC_CMD_MDIO_READ_IN_DEVAD_LEN 42708/* enum: By default all the MCDI MDIO operations perform clause45 mode. If you2709 * want to use clause22 then set DEVAD = MC_CMD_MDIO_CLAUSE22.2710 */2711#define MC_CMD_MDIO_CLAUSE22 0x202712/* Address */2713#define MC_CMD_MDIO_READ_IN_ADDR_OFST 122714#define MC_CMD_MDIO_READ_IN_ADDR_LEN 42715 2716/* MC_CMD_MDIO_READ_OUT msgresponse */2717#define MC_CMD_MDIO_READ_OUT_LEN 82718/* Value */2719#define MC_CMD_MDIO_READ_OUT_VALUE_OFST 02720#define MC_CMD_MDIO_READ_OUT_VALUE_LEN 42721/* Status the MDIO commands return the raw status bits from the MDIO block. A2722 * "good" transaction should have the DONE bit set and all other bits clear.2723 */2724#define MC_CMD_MDIO_READ_OUT_STATUS_OFST 42725#define MC_CMD_MDIO_READ_OUT_STATUS_LEN 42726/* enum: Good. */2727#define MC_CMD_MDIO_STATUS_GOOD 0x82728 2729 2730/***********************************/2731/* MC_CMD_MDIO_WRITE2732 * MDIO register write.2733 */2734#define MC_CMD_MDIO_WRITE 0x112735#undef MC_CMD_0x11_PRIVILEGE_CTG2736 2737#define MC_CMD_0x11_PRIVILEGE_CTG SRIOV_CTG_ADMIN2738 2739/* MC_CMD_MDIO_WRITE_IN msgrequest */2740#define MC_CMD_MDIO_WRITE_IN_LEN 202741/* Bus number; there are two MDIO buses: one for the internal PHY, and one for2742 * external devices.2743 */2744#define MC_CMD_MDIO_WRITE_IN_BUS_OFST 02745#define MC_CMD_MDIO_WRITE_IN_BUS_LEN 42746/* enum: Internal. */2747/* MC_CMD_MDIO_BUS_INTERNAL 0x0 */2748/* enum: External. */2749/* MC_CMD_MDIO_BUS_EXTERNAL 0x1 */2750/* Port address */2751#define MC_CMD_MDIO_WRITE_IN_PRTAD_OFST 42752#define MC_CMD_MDIO_WRITE_IN_PRTAD_LEN 42753/* Device Address or clause 22. */2754#define MC_CMD_MDIO_WRITE_IN_DEVAD_OFST 82755#define MC_CMD_MDIO_WRITE_IN_DEVAD_LEN 42756/* enum: By default all the MCDI MDIO operations perform clause45 mode. If you2757 * want to use clause22 then set DEVAD = MC_CMD_MDIO_CLAUSE22.2758 */2759/* MC_CMD_MDIO_CLAUSE22 0x20 */2760/* Address */2761#define MC_CMD_MDIO_WRITE_IN_ADDR_OFST 122762#define MC_CMD_MDIO_WRITE_IN_ADDR_LEN 42763/* Value */2764#define MC_CMD_MDIO_WRITE_IN_VALUE_OFST 162765#define MC_CMD_MDIO_WRITE_IN_VALUE_LEN 42766 2767/* MC_CMD_MDIO_WRITE_OUT msgresponse */2768#define MC_CMD_MDIO_WRITE_OUT_LEN 42769/* Status; the MDIO commands return the raw status bits from the MDIO block. A2770 * "good" transaction should have the DONE bit set and all other bits clear.2771 */2772#define MC_CMD_MDIO_WRITE_OUT_STATUS_OFST 02773#define MC_CMD_MDIO_WRITE_OUT_STATUS_LEN 42774/* enum: Good. */2775/* MC_CMD_MDIO_STATUS_GOOD 0x8 */2776 2777 2778/***********************************/2779/* MC_CMD_DBI_WRITE2780 * Write DBI register(s).2781 */2782#define MC_CMD_DBI_WRITE 0x122783#undef MC_CMD_0x12_PRIVILEGE_CTG2784 2785#define MC_CMD_0x12_PRIVILEGE_CTG SRIOV_CTG_INSECURE2786 2787/* MC_CMD_DBI_WRITE_IN msgrequest */2788#define MC_CMD_DBI_WRITE_IN_LENMIN 122789#define MC_CMD_DBI_WRITE_IN_LENMAX 2522790#define MC_CMD_DBI_WRITE_IN_LENMAX_MCDI2 10202791#define MC_CMD_DBI_WRITE_IN_LEN(num) (0+12*(num))2792#define MC_CMD_DBI_WRITE_IN_DBIWROP_NUM(len) (((len)-0)/12)2793/* Each write op consists of an address (offset 0), byte enable/VF/CS2 (offset2794 * 32) and value (offset 64). See MC_CMD_DBIWROP_TYPEDEF.2795 */2796#define MC_CMD_DBI_WRITE_IN_DBIWROP_OFST 02797#define MC_CMD_DBI_WRITE_IN_DBIWROP_LEN 122798#define MC_CMD_DBI_WRITE_IN_DBIWROP_MINNUM 12799#define MC_CMD_DBI_WRITE_IN_DBIWROP_MAXNUM 212800#define MC_CMD_DBI_WRITE_IN_DBIWROP_MAXNUM_MCDI2 852801 2802/* MC_CMD_DBI_WRITE_OUT msgresponse */2803#define MC_CMD_DBI_WRITE_OUT_LEN 02804 2805/* MC_CMD_DBIWROP_TYPEDEF structuredef */2806#define MC_CMD_DBIWROP_TYPEDEF_LEN 122807#define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_OFST 02808#define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_LEN 42809#define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_LBN 02810#define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_WIDTH 322811#define MC_CMD_DBIWROP_TYPEDEF_PARMS_OFST 42812#define MC_CMD_DBIWROP_TYPEDEF_PARMS_LEN 42813#define MC_CMD_DBIWROP_TYPEDEF_VF_NUM_OFST 42814#define MC_CMD_DBIWROP_TYPEDEF_VF_NUM_LBN 162815#define MC_CMD_DBIWROP_TYPEDEF_VF_NUM_WIDTH 162816#define MC_CMD_DBIWROP_TYPEDEF_VF_ACTIVE_OFST 42817#define MC_CMD_DBIWROP_TYPEDEF_VF_ACTIVE_LBN 152818#define MC_CMD_DBIWROP_TYPEDEF_VF_ACTIVE_WIDTH 12819#define MC_CMD_DBIWROP_TYPEDEF_CS2_OFST 42820#define MC_CMD_DBIWROP_TYPEDEF_CS2_LBN 142821#define MC_CMD_DBIWROP_TYPEDEF_CS2_WIDTH 12822#define MC_CMD_DBIWROP_TYPEDEF_PARMS_LBN 322823#define MC_CMD_DBIWROP_TYPEDEF_PARMS_WIDTH 322824#define MC_CMD_DBIWROP_TYPEDEF_VALUE_OFST 82825#define MC_CMD_DBIWROP_TYPEDEF_VALUE_LEN 42826#define MC_CMD_DBIWROP_TYPEDEF_VALUE_LBN 642827#define MC_CMD_DBIWROP_TYPEDEF_VALUE_WIDTH 322828 2829 2830/***********************************/2831/* MC_CMD_PORT_READ322832 * Read a 32-bit register from the indirect port register map. The port to2833 * access is implied by the Shared memory channel used.2834 */2835#define MC_CMD_PORT_READ32 0x142836 2837/* MC_CMD_PORT_READ32_IN msgrequest */2838#define MC_CMD_PORT_READ32_IN_LEN 42839/* Address */2840#define MC_CMD_PORT_READ32_IN_ADDR_OFST 02841#define MC_CMD_PORT_READ32_IN_ADDR_LEN 42842 2843/* MC_CMD_PORT_READ32_OUT msgresponse */2844#define MC_CMD_PORT_READ32_OUT_LEN 82845/* Value */2846#define MC_CMD_PORT_READ32_OUT_VALUE_OFST 02847#define MC_CMD_PORT_READ32_OUT_VALUE_LEN 42848/* Status */2849#define MC_CMD_PORT_READ32_OUT_STATUS_OFST 42850#define MC_CMD_PORT_READ32_OUT_STATUS_LEN 42851 2852 2853/***********************************/2854/* MC_CMD_PORT_WRITE322855 * Write a 32-bit register to the indirect port register map. The port to2856 * access is implied by the Shared memory channel used.2857 */2858#define MC_CMD_PORT_WRITE32 0x152859 2860/* MC_CMD_PORT_WRITE32_IN msgrequest */2861#define MC_CMD_PORT_WRITE32_IN_LEN 82862/* Address */2863#define MC_CMD_PORT_WRITE32_IN_ADDR_OFST 02864#define MC_CMD_PORT_WRITE32_IN_ADDR_LEN 42865/* Value */2866#define MC_CMD_PORT_WRITE32_IN_VALUE_OFST 42867#define MC_CMD_PORT_WRITE32_IN_VALUE_LEN 42868 2869/* MC_CMD_PORT_WRITE32_OUT msgresponse */2870#define MC_CMD_PORT_WRITE32_OUT_LEN 42871/* Status */2872#define MC_CMD_PORT_WRITE32_OUT_STATUS_OFST 02873#define MC_CMD_PORT_WRITE32_OUT_STATUS_LEN 42874 2875 2876/***********************************/2877/* MC_CMD_PORT_READ1282878 * Read a 128-bit register from the indirect port register map. The port to2879 * access is implied by the Shared memory channel used.2880 */2881#define MC_CMD_PORT_READ128 0x162882 2883/* MC_CMD_PORT_READ128_IN msgrequest */2884#define MC_CMD_PORT_READ128_IN_LEN 42885/* Address */2886#define MC_CMD_PORT_READ128_IN_ADDR_OFST 02887#define MC_CMD_PORT_READ128_IN_ADDR_LEN 42888 2889/* MC_CMD_PORT_READ128_OUT msgresponse */2890#define MC_CMD_PORT_READ128_OUT_LEN 202891/* Value */2892#define MC_CMD_PORT_READ128_OUT_VALUE_OFST 02893#define MC_CMD_PORT_READ128_OUT_VALUE_LEN 162894/* Status */2895#define MC_CMD_PORT_READ128_OUT_STATUS_OFST 162896#define MC_CMD_PORT_READ128_OUT_STATUS_LEN 42897 2898 2899/***********************************/2900/* MC_CMD_PORT_WRITE1282901 * Write a 128-bit register to the indirect port register map. The port to2902 * access is implied by the Shared memory channel used.2903 */2904#define MC_CMD_PORT_WRITE128 0x172905 2906/* MC_CMD_PORT_WRITE128_IN msgrequest */2907#define MC_CMD_PORT_WRITE128_IN_LEN 202908/* Address */2909#define MC_CMD_PORT_WRITE128_IN_ADDR_OFST 02910#define MC_CMD_PORT_WRITE128_IN_ADDR_LEN 42911/* Value */2912#define MC_CMD_PORT_WRITE128_IN_VALUE_OFST 42913#define MC_CMD_PORT_WRITE128_IN_VALUE_LEN 162914 2915/* MC_CMD_PORT_WRITE128_OUT msgresponse */2916#define MC_CMD_PORT_WRITE128_OUT_LEN 42917/* Status */2918#define MC_CMD_PORT_WRITE128_OUT_STATUS_OFST 02919#define MC_CMD_PORT_WRITE128_OUT_STATUS_LEN 42920 2921/* MC_CMD_CAPABILITIES structuredef */2922#define MC_CMD_CAPABILITIES_LEN 42923/* Small buf table. */2924#define MC_CMD_CAPABILITIES_SMALL_BUF_TBL_LBN 02925#define MC_CMD_CAPABILITIES_SMALL_BUF_TBL_WIDTH 12926/* Turbo mode (for Maranello). */2927#define MC_CMD_CAPABILITIES_TURBO_LBN 12928#define MC_CMD_CAPABILITIES_TURBO_WIDTH 12929/* Turbo mode active (for Maranello). */2930#define MC_CMD_CAPABILITIES_TURBO_ACTIVE_LBN 22931#define MC_CMD_CAPABILITIES_TURBO_ACTIVE_WIDTH 12932/* PTP offload. */2933#define MC_CMD_CAPABILITIES_PTP_LBN 32934#define MC_CMD_CAPABILITIES_PTP_WIDTH 12935/* AOE mode. */2936#define MC_CMD_CAPABILITIES_AOE_LBN 42937#define MC_CMD_CAPABILITIES_AOE_WIDTH 12938/* AOE mode active. */2939#define MC_CMD_CAPABILITIES_AOE_ACTIVE_LBN 52940#define MC_CMD_CAPABILITIES_AOE_ACTIVE_WIDTH 12941/* AOE mode active. */2942#define MC_CMD_CAPABILITIES_FC_ACTIVE_LBN 62943#define MC_CMD_CAPABILITIES_FC_ACTIVE_WIDTH 12944#define MC_CMD_CAPABILITIES_RESERVED_LBN 72945#define MC_CMD_CAPABILITIES_RESERVED_WIDTH 252946 2947 2948/***********************************/2949/* MC_CMD_GET_BOARD_CFG2950 * Returns the MC firmware configuration structure.2951 */2952#define MC_CMD_GET_BOARD_CFG 0x182953#undef MC_CMD_0x18_PRIVILEGE_CTG2954 2955#define MC_CMD_0x18_PRIVILEGE_CTG SRIOV_CTG_GENERAL2956 2957/* MC_CMD_GET_BOARD_CFG_IN msgrequest */2958#define MC_CMD_GET_BOARD_CFG_IN_LEN 02959 2960/* MC_CMD_GET_BOARD_CFG_OUT msgresponse */2961#define MC_CMD_GET_BOARD_CFG_OUT_LENMIN 962962#define MC_CMD_GET_BOARD_CFG_OUT_LENMAX 1362963#define MC_CMD_GET_BOARD_CFG_OUT_LENMAX_MCDI2 1362964#define MC_CMD_GET_BOARD_CFG_OUT_LEN(num) (72+2*(num))2965#define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_NUM(len) (((len)-72)/2)2966#define MC_CMD_GET_BOARD_CFG_OUT_BOARD_TYPE_OFST 02967#define MC_CMD_GET_BOARD_CFG_OUT_BOARD_TYPE_LEN 42968#define MC_CMD_GET_BOARD_CFG_OUT_BOARD_NAME_OFST 42969#define MC_CMD_GET_BOARD_CFG_OUT_BOARD_NAME_LEN 322970/* Capabilities for Siena Port0 (see struct MC_CMD_CAPABILITIES). Unused on2971 * EF10 and later (use MC_CMD_GET_CAPABILITIES).2972 */2973#define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT0_OFST 362974#define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT0_LEN 42975/* Capabilities for Siena Port1 (see struct MC_CMD_CAPABILITIES). Unused on2976 * EF10 and later (use MC_CMD_GET_CAPABILITIES).2977 */2978#define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT1_OFST 402979#define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT1_LEN 42980/* Base MAC address for Siena Port0. Unused on EF10 and later (use2981 * MC_CMD_GET_MAC_ADDRESSES).2982 */2983#define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0_OFST 442984#define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0_LEN 62985/* Base MAC address for Siena Port1. Unused on EF10 and later (use2986 * MC_CMD_GET_MAC_ADDRESSES).2987 */2988#define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1_OFST 502989#define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1_LEN 62990/* Size of MAC address pool for Siena Port0. Unused on EF10 and later (use2991 * MC_CMD_GET_MAC_ADDRESSES).2992 */2993#define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT0_OFST 562994#define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT0_LEN 42995/* Size of MAC address pool for Siena Port1. Unused on EF10 and later (use2996 * MC_CMD_GET_MAC_ADDRESSES).2997 */2998#define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT1_OFST 602999#define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT1_LEN 43000/* Increment between addresses in MAC address pool for Siena Port0. Unused on3001 * EF10 and later (use MC_CMD_GET_MAC_ADDRESSES).3002 */3003#define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT0_OFST 643004#define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT0_LEN 43005/* Increment between addresses in MAC address pool for Siena Port1. Unused on3006 * EF10 and later (use MC_CMD_GET_MAC_ADDRESSES).3007 */3008#define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT1_OFST 683009#define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT1_LEN 43010/* Siena only. This field contains a 16-bit value for each of the types of3011 * NVRAM area. The values are defined in the firmware/mc/platform/.c file for a3012 * specific board type, but otherwise have no meaning to the MC; they are used3013 * by the driver to manage selection of appropriate firmware updates. Unused on3014 * EF10 and later (use MC_CMD_NVRAM_METADATA).3015 */3016#define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_OFST 723017#define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_LEN 23018#define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MINNUM 123019#define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MAXNUM 323020#define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MAXNUM_MCDI2 323021 3022 3023/***********************************/3024/* MC_CMD_DBI_READX3025 * Read DBI register(s) -- extended functionality3026 */3027#define MC_CMD_DBI_READX 0x193028#undef MC_CMD_0x19_PRIVILEGE_CTG3029 3030#define MC_CMD_0x19_PRIVILEGE_CTG SRIOV_CTG_INSECURE3031 3032/* MC_CMD_DBI_READX_IN msgrequest */3033#define MC_CMD_DBI_READX_IN_LENMIN 83034#define MC_CMD_DBI_READX_IN_LENMAX 2483035#define MC_CMD_DBI_READX_IN_LENMAX_MCDI2 10163036#define MC_CMD_DBI_READX_IN_LEN(num) (0+8*(num))3037#define MC_CMD_DBI_READX_IN_DBIRDOP_NUM(len) (((len)-0)/8)3038/* Each Read op consists of an address (offset 0), VF/CS2) */3039#define MC_CMD_DBI_READX_IN_DBIRDOP_OFST 03040#define MC_CMD_DBI_READX_IN_DBIRDOP_LEN 83041#define MC_CMD_DBI_READX_IN_DBIRDOP_LO_OFST 03042#define MC_CMD_DBI_READX_IN_DBIRDOP_HI_OFST 43043#define MC_CMD_DBI_READX_IN_DBIRDOP_MINNUM 13044#define MC_CMD_DBI_READX_IN_DBIRDOP_MAXNUM 313045#define MC_CMD_DBI_READX_IN_DBIRDOP_MAXNUM_MCDI2 1273046 3047/* MC_CMD_DBI_READX_OUT msgresponse */3048#define MC_CMD_DBI_READX_OUT_LENMIN 43049#define MC_CMD_DBI_READX_OUT_LENMAX 2523050#define MC_CMD_DBI_READX_OUT_LENMAX_MCDI2 10203051#define MC_CMD_DBI_READX_OUT_LEN(num) (0+4*(num))3052#define MC_CMD_DBI_READX_OUT_VALUE_NUM(len) (((len)-0)/4)3053/* Value */3054#define MC_CMD_DBI_READX_OUT_VALUE_OFST 03055#define MC_CMD_DBI_READX_OUT_VALUE_LEN 43056#define MC_CMD_DBI_READX_OUT_VALUE_MINNUM 13057#define MC_CMD_DBI_READX_OUT_VALUE_MAXNUM 633058#define MC_CMD_DBI_READX_OUT_VALUE_MAXNUM_MCDI2 2553059 3060/* MC_CMD_DBIRDOP_TYPEDEF structuredef */3061#define MC_CMD_DBIRDOP_TYPEDEF_LEN 83062#define MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_OFST 03063#define MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_LEN 43064#define MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_LBN 03065#define MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_WIDTH 323066#define MC_CMD_DBIRDOP_TYPEDEF_PARMS_OFST 43067#define MC_CMD_DBIRDOP_TYPEDEF_PARMS_LEN 43068#define MC_CMD_DBIRDOP_TYPEDEF_VF_NUM_OFST 43069#define MC_CMD_DBIRDOP_TYPEDEF_VF_NUM_LBN 163070#define MC_CMD_DBIRDOP_TYPEDEF_VF_NUM_WIDTH 163071#define MC_CMD_DBIRDOP_TYPEDEF_VF_ACTIVE_OFST 43072#define MC_CMD_DBIRDOP_TYPEDEF_VF_ACTIVE_LBN 153073#define MC_CMD_DBIRDOP_TYPEDEF_VF_ACTIVE_WIDTH 13074#define MC_CMD_DBIRDOP_TYPEDEF_CS2_OFST 43075#define MC_CMD_DBIRDOP_TYPEDEF_CS2_LBN 143076#define MC_CMD_DBIRDOP_TYPEDEF_CS2_WIDTH 13077#define MC_CMD_DBIRDOP_TYPEDEF_PARMS_LBN 323078#define MC_CMD_DBIRDOP_TYPEDEF_PARMS_WIDTH 323079 3080 3081/***********************************/3082/* MC_CMD_SET_RAND_SEED3083 * Set the 16byte seed for the MC pseudo-random generator.3084 */3085#define MC_CMD_SET_RAND_SEED 0x1a3086#undef MC_CMD_0x1a_PRIVILEGE_CTG3087 3088#define MC_CMD_0x1a_PRIVILEGE_CTG SRIOV_CTG_INSECURE3089 3090/* MC_CMD_SET_RAND_SEED_IN msgrequest */3091#define MC_CMD_SET_RAND_SEED_IN_LEN 163092/* Seed value. */3093#define MC_CMD_SET_RAND_SEED_IN_SEED_OFST 03094#define MC_CMD_SET_RAND_SEED_IN_SEED_LEN 163095 3096/* MC_CMD_SET_RAND_SEED_OUT msgresponse */3097#define MC_CMD_SET_RAND_SEED_OUT_LEN 03098 3099 3100/***********************************/3101/* MC_CMD_LTSSM_HIST3102 * Retrieve the history of the LTSSM, if the build supports it.3103 */3104#define MC_CMD_LTSSM_HIST 0x1b3105 3106/* MC_CMD_LTSSM_HIST_IN msgrequest */3107#define MC_CMD_LTSSM_HIST_IN_LEN 03108 3109/* MC_CMD_LTSSM_HIST_OUT msgresponse */3110#define MC_CMD_LTSSM_HIST_OUT_LENMIN 03111#define MC_CMD_LTSSM_HIST_OUT_LENMAX 2523112#define MC_CMD_LTSSM_HIST_OUT_LENMAX_MCDI2 10203113#define MC_CMD_LTSSM_HIST_OUT_LEN(num) (0+4*(num))3114#define MC_CMD_LTSSM_HIST_OUT_DATA_NUM(len) (((len)-0)/4)3115/* variable number of LTSSM values, as bytes. The history is read-to-clear. */3116#define MC_CMD_LTSSM_HIST_OUT_DATA_OFST 03117#define MC_CMD_LTSSM_HIST_OUT_DATA_LEN 43118#define MC_CMD_LTSSM_HIST_OUT_DATA_MINNUM 03119#define MC_CMD_LTSSM_HIST_OUT_DATA_MAXNUM 633120#define MC_CMD_LTSSM_HIST_OUT_DATA_MAXNUM_MCDI2 2553121 3122 3123/***********************************/3124/* MC_CMD_DRV_ATTACH3125 * Inform MCPU that this port is managed on the host (i.e. driver active). For3126 * Huntington, also request the preferred datapath firmware to use if possible3127 * (it may not be possible for this request to be fulfilled; the driver must3128 * issue a subsequent MC_CMD_GET_CAPABILITIES command to determine which3129 * features are actually available). The FIRMWARE_ID field is ignored by older3130 * platforms.3131 */3132#define MC_CMD_DRV_ATTACH 0x1c3133#undef MC_CMD_0x1c_PRIVILEGE_CTG3134 3135#define MC_CMD_0x1c_PRIVILEGE_CTG SRIOV_CTG_GENERAL3136 3137/* MC_CMD_DRV_ATTACH_IN msgrequest */3138#define MC_CMD_DRV_ATTACH_IN_LEN 123139/* new state to set if UPDATE=1 */3140#define MC_CMD_DRV_ATTACH_IN_NEW_STATE_OFST 03141#define MC_CMD_DRV_ATTACH_IN_NEW_STATE_LEN 43142#define MC_CMD_DRV_ATTACH_OFST 03143#define MC_CMD_DRV_ATTACH_LBN 03144#define MC_CMD_DRV_ATTACH_WIDTH 13145#define MC_CMD_DRV_ATTACH_IN_ATTACH_OFST 03146#define MC_CMD_DRV_ATTACH_IN_ATTACH_LBN 03147#define MC_CMD_DRV_ATTACH_IN_ATTACH_WIDTH 13148#define MC_CMD_DRV_PREBOOT_OFST 03149#define MC_CMD_DRV_PREBOOT_LBN 13150#define MC_CMD_DRV_PREBOOT_WIDTH 13151#define MC_CMD_DRV_ATTACH_IN_PREBOOT_OFST 03152#define MC_CMD_DRV_ATTACH_IN_PREBOOT_LBN 13153#define MC_CMD_DRV_ATTACH_IN_PREBOOT_WIDTH 13154#define MC_CMD_DRV_ATTACH_IN_SUBVARIANT_AWARE_OFST 03155#define MC_CMD_DRV_ATTACH_IN_SUBVARIANT_AWARE_LBN 23156#define MC_CMD_DRV_ATTACH_IN_SUBVARIANT_AWARE_WIDTH 13157#define MC_CMD_DRV_ATTACH_IN_WANT_VI_SPREADING_OFST 03158#define MC_CMD_DRV_ATTACH_IN_WANT_VI_SPREADING_LBN 33159#define MC_CMD_DRV_ATTACH_IN_WANT_VI_SPREADING_WIDTH 13160#define MC_CMD_DRV_ATTACH_IN_WANT_V2_LINKCHANGES_OFST 03161#define MC_CMD_DRV_ATTACH_IN_WANT_V2_LINKCHANGES_LBN 43162#define MC_CMD_DRV_ATTACH_IN_WANT_V2_LINKCHANGES_WIDTH 13163#define MC_CMD_DRV_ATTACH_IN_WANT_RX_VI_SPREADING_INHIBIT_OFST 03164#define MC_CMD_DRV_ATTACH_IN_WANT_RX_VI_SPREADING_INHIBIT_LBN 53165#define MC_CMD_DRV_ATTACH_IN_WANT_RX_VI_SPREADING_INHIBIT_WIDTH 13166#define MC_CMD_DRV_ATTACH_IN_WANT_TX_ONLY_SPREADING_OFST 03167#define MC_CMD_DRV_ATTACH_IN_WANT_TX_ONLY_SPREADING_LBN 53168#define MC_CMD_DRV_ATTACH_IN_WANT_TX_ONLY_SPREADING_WIDTH 13169/* 1 to set new state, or 0 to just report the existing state */3170#define MC_CMD_DRV_ATTACH_IN_UPDATE_OFST 43171#define MC_CMD_DRV_ATTACH_IN_UPDATE_LEN 43172/* preferred datapath firmware (for Huntington; ignored for Siena) */3173#define MC_CMD_DRV_ATTACH_IN_FIRMWARE_ID_OFST 83174#define MC_CMD_DRV_ATTACH_IN_FIRMWARE_ID_LEN 43175/* enum: Prefer to use full featured firmware */3176#define MC_CMD_FW_FULL_FEATURED 0x03177/* enum: Prefer to use firmware with fewer features but lower latency */3178#define MC_CMD_FW_LOW_LATENCY 0x13179/* enum: Prefer to use firmware for SolarCapture packed stream mode */3180#define MC_CMD_FW_PACKED_STREAM 0x23181/* enum: Prefer to use firmware with fewer features and simpler TX event3182 * batching but higher TX packet rate3183 */3184#define MC_CMD_FW_HIGH_TX_RATE 0x33185/* enum: Reserved value */3186#define MC_CMD_FW_PACKED_STREAM_HASH_MODE_1 0x43187/* enum: Prefer to use firmware with additional "rules engine" filtering3188 * support3189 */3190#define MC_CMD_FW_RULES_ENGINE 0x53191/* enum: Prefer to use firmware with additional DPDK support */3192#define MC_CMD_FW_DPDK 0x63193/* enum: Prefer to use "l3xudp" custom datapath firmware (see SF-119495-PD and3194 * bug69716)3195 */3196#define MC_CMD_FW_L3XUDP 0x73197/* enum: Requests that the MC keep whatever datapath firmware is currently3198 * running. It's used for test purposes, where we want to be able to shmboot3199 * special test firmware variants. This option is only recognised in eftest3200 * (i.e. non-production) builds.3201 */3202#define MC_CMD_FW_KEEP_CURRENT_EFTEST_ONLY 0xfffffffe3203/* enum: Only this option is allowed for non-admin functions */3204#define MC_CMD_FW_DONT_CARE 0xffffffff3205 3206/* MC_CMD_DRV_ATTACH_IN_V2 msgrequest: Updated DRV_ATTACH to include driver3207 * version3208 */3209#define MC_CMD_DRV_ATTACH_IN_V2_LEN 323210/* new state to set if UPDATE=1 */3211#define MC_CMD_DRV_ATTACH_IN_V2_NEW_STATE_OFST 03212#define MC_CMD_DRV_ATTACH_IN_V2_NEW_STATE_LEN 43213/* MC_CMD_DRV_ATTACH_OFST 0 */3214/* MC_CMD_DRV_ATTACH_LBN 0 */3215/* MC_CMD_DRV_ATTACH_WIDTH 1 */3216#define MC_CMD_DRV_ATTACH_IN_V2_ATTACH_OFST 03217#define MC_CMD_DRV_ATTACH_IN_V2_ATTACH_LBN 03218#define MC_CMD_DRV_ATTACH_IN_V2_ATTACH_WIDTH 13219/* MC_CMD_DRV_PREBOOT_OFST 0 */3220/* MC_CMD_DRV_PREBOOT_LBN 1 */3221/* MC_CMD_DRV_PREBOOT_WIDTH 1 */3222#define MC_CMD_DRV_ATTACH_IN_V2_PREBOOT_OFST 03223#define MC_CMD_DRV_ATTACH_IN_V2_PREBOOT_LBN 13224#define MC_CMD_DRV_ATTACH_IN_V2_PREBOOT_WIDTH 13225#define MC_CMD_DRV_ATTACH_IN_V2_SUBVARIANT_AWARE_OFST 03226#define MC_CMD_DRV_ATTACH_IN_V2_SUBVARIANT_AWARE_LBN 23227#define MC_CMD_DRV_ATTACH_IN_V2_SUBVARIANT_AWARE_WIDTH 13228#define MC_CMD_DRV_ATTACH_IN_V2_WANT_VI_SPREADING_OFST 03229#define MC_CMD_DRV_ATTACH_IN_V2_WANT_VI_SPREADING_LBN 33230#define MC_CMD_DRV_ATTACH_IN_V2_WANT_VI_SPREADING_WIDTH 13231#define MC_CMD_DRV_ATTACH_IN_V2_WANT_V2_LINKCHANGES_OFST 03232#define MC_CMD_DRV_ATTACH_IN_V2_WANT_V2_LINKCHANGES_LBN 43233#define MC_CMD_DRV_ATTACH_IN_V2_WANT_V2_LINKCHANGES_WIDTH 13234#define MC_CMD_DRV_ATTACH_IN_V2_WANT_RX_VI_SPREADING_INHIBIT_OFST 03235#define MC_CMD_DRV_ATTACH_IN_V2_WANT_RX_VI_SPREADING_INHIBIT_LBN 53236#define MC_CMD_DRV_ATTACH_IN_V2_WANT_RX_VI_SPREADING_INHIBIT_WIDTH 13237#define MC_CMD_DRV_ATTACH_IN_V2_WANT_TX_ONLY_SPREADING_OFST 03238#define MC_CMD_DRV_ATTACH_IN_V2_WANT_TX_ONLY_SPREADING_LBN 53239#define MC_CMD_DRV_ATTACH_IN_V2_WANT_TX_ONLY_SPREADING_WIDTH 13240/* 1 to set new state, or 0 to just report the existing state */3241#define MC_CMD_DRV_ATTACH_IN_V2_UPDATE_OFST 43242#define MC_CMD_DRV_ATTACH_IN_V2_UPDATE_LEN 43243/* preferred datapath firmware (for Huntington; ignored for Siena) */3244#define MC_CMD_DRV_ATTACH_IN_V2_FIRMWARE_ID_OFST 83245#define MC_CMD_DRV_ATTACH_IN_V2_FIRMWARE_ID_LEN 43246/* enum: Prefer to use full featured firmware */3247/* MC_CMD_FW_FULL_FEATURED 0x0 */3248/* enum: Prefer to use firmware with fewer features but lower latency */3249/* MC_CMD_FW_LOW_LATENCY 0x1 */3250/* enum: Prefer to use firmware for SolarCapture packed stream mode */3251/* MC_CMD_FW_PACKED_STREAM 0x2 */3252/* enum: Prefer to use firmware with fewer features and simpler TX event3253 * batching but higher TX packet rate3254 */3255/* MC_CMD_FW_HIGH_TX_RATE 0x3 */3256/* enum: Reserved value */3257/* MC_CMD_FW_PACKED_STREAM_HASH_MODE_1 0x4 */3258/* enum: Prefer to use firmware with additional "rules engine" filtering3259 * support3260 */3261/* MC_CMD_FW_RULES_ENGINE 0x5 */3262/* enum: Prefer to use firmware with additional DPDK support */3263/* MC_CMD_FW_DPDK 0x6 */3264/* enum: Prefer to use "l3xudp" custom datapath firmware (see SF-119495-PD and3265 * bug69716)3266 */3267/* MC_CMD_FW_L3XUDP 0x7 */3268/* enum: Requests that the MC keep whatever datapath firmware is currently3269 * running. It's used for test purposes, where we want to be able to shmboot3270 * special test firmware variants. This option is only recognised in eftest3271 * (i.e. non-production) builds.3272 */3273/* MC_CMD_FW_KEEP_CURRENT_EFTEST_ONLY 0xfffffffe */3274/* enum: Only this option is allowed for non-admin functions */3275/* MC_CMD_FW_DONT_CARE 0xffffffff */3276/* Version of the driver to be reported by management protocols (e.g. NC-SI)3277 * handled by the NIC. This is a zero-terminated ASCII string.3278 */3279#define MC_CMD_DRV_ATTACH_IN_V2_DRIVER_VERSION_OFST 123280#define MC_CMD_DRV_ATTACH_IN_V2_DRIVER_VERSION_LEN 203281 3282/* MC_CMD_DRV_ATTACH_OUT msgresponse */3283#define MC_CMD_DRV_ATTACH_OUT_LEN 43284/* previous or existing state, see the bitmask at NEW_STATE */3285#define MC_CMD_DRV_ATTACH_OUT_OLD_STATE_OFST 03286#define MC_CMD_DRV_ATTACH_OUT_OLD_STATE_LEN 43287 3288/* MC_CMD_DRV_ATTACH_EXT_OUT msgresponse */3289#define MC_CMD_DRV_ATTACH_EXT_OUT_LEN 83290/* previous or existing state, see the bitmask at NEW_STATE */3291#define MC_CMD_DRV_ATTACH_EXT_OUT_OLD_STATE_OFST 03292#define MC_CMD_DRV_ATTACH_EXT_OUT_OLD_STATE_LEN 43293/* Flags associated with this function */3294#define MC_CMD_DRV_ATTACH_EXT_OUT_FUNC_FLAGS_OFST 43295#define MC_CMD_DRV_ATTACH_EXT_OUT_FUNC_FLAGS_LEN 43296/* enum: Labels the lowest-numbered function visible to the OS */3297#define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_PRIMARY 0x03298/* enum: The function can control the link state of the physical port it is3299 * bound to.3300 */3301#define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL 0x13302/* enum: The function can perform privileged operations */3303#define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_TRUSTED 0x23304/* enum: The function does not have an active port associated with it. The port3305 * refers to the Sorrento external FPGA port.3306 */3307#define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_NO_ACTIVE_PORT 0x33308/* enum: If set, indicates that VI spreading is currently enabled. Will always3309 * indicate the current state, regardless of the value in the WANT_VI_SPREADING3310 * input.3311 */3312#define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_VI_SPREADING_ENABLED 0x43313/* enum: Used during development only. Should no longer be used. */3314#define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_RX_VI_SPREADING_INHIBITED 0x53315/* enum: If set, indicates that TX only spreading is enabled. Even-numbered3316 * TXQs will use one engine, and odd-numbered TXQs will use the other. This3317 * also has the effect that only even-numbered RXQs will receive traffic.3318 */3319#define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_TX_ONLY_VI_SPREADING_ENABLED 0x53320 3321 3322/***********************************/3323/* MC_CMD_SHMUART3324 * Route UART output to circular buffer in shared memory instead.3325 */3326#define MC_CMD_SHMUART 0x1f3327 3328/* MC_CMD_SHMUART_IN msgrequest */3329#define MC_CMD_SHMUART_IN_LEN 43330/* ??? */3331#define MC_CMD_SHMUART_IN_FLAG_OFST 03332#define MC_CMD_SHMUART_IN_FLAG_LEN 43333 3334/* MC_CMD_SHMUART_OUT msgresponse */3335#define MC_CMD_SHMUART_OUT_LEN 03336 3337 3338/***********************************/3339/* MC_CMD_PORT_RESET3340 * Generic per-port reset. There is no equivalent for per-board reset. Locks3341 * required: None; Return code: 0, ETIME. NOTE: This command is deprecated -3342 * use MC_CMD_ENTITY_RESET instead.3343 */3344#define MC_CMD_PORT_RESET 0x203345#undef MC_CMD_0x20_PRIVILEGE_CTG3346 3347#define MC_CMD_0x20_PRIVILEGE_CTG SRIOV_CTG_GENERAL3348 3349/* MC_CMD_PORT_RESET_IN msgrequest */3350#define MC_CMD_PORT_RESET_IN_LEN 03351 3352/* MC_CMD_PORT_RESET_OUT msgresponse */3353#define MC_CMD_PORT_RESET_OUT_LEN 03354 3355 3356/***********************************/3357/* MC_CMD_ENTITY_RESET3358 * Generic per-resource reset. There is no equivalent for per-board reset.3359 * Locks required: None; Return code: 0, ETIME. NOTE: This command is an3360 * extended version of the deprecated MC_CMD_PORT_RESET with added fields.3361 */3362#define MC_CMD_ENTITY_RESET 0x203363/* MC_CMD_0x20_PRIVILEGE_CTG SRIOV_CTG_GENERAL */3364 3365/* MC_CMD_ENTITY_RESET_IN msgrequest */3366#define MC_CMD_ENTITY_RESET_IN_LEN 43367/* Optional flags field. Omitting this will perform a "legacy" reset action3368 * (TBD).3369 */3370#define MC_CMD_ENTITY_RESET_IN_FLAG_OFST 03371#define MC_CMD_ENTITY_RESET_IN_FLAG_LEN 43372#define MC_CMD_ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET_OFST 03373#define MC_CMD_ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET_LBN 03374#define MC_CMD_ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET_WIDTH 13375 3376/* MC_CMD_ENTITY_RESET_OUT msgresponse */3377#define MC_CMD_ENTITY_RESET_OUT_LEN 03378 3379 3380/***********************************/3381/* MC_CMD_PCIE_CREDITS3382 * Read instantaneous and minimum flow control thresholds.3383 */3384#define MC_CMD_PCIE_CREDITS 0x213385 3386/* MC_CMD_PCIE_CREDITS_IN msgrequest */3387#define MC_CMD_PCIE_CREDITS_IN_LEN 83388/* poll period. 0 is disabled */3389#define MC_CMD_PCIE_CREDITS_IN_POLL_PERIOD_OFST 03390#define MC_CMD_PCIE_CREDITS_IN_POLL_PERIOD_LEN 43391/* wipe statistics */3392#define MC_CMD_PCIE_CREDITS_IN_WIPE_OFST 43393#define MC_CMD_PCIE_CREDITS_IN_WIPE_LEN 43394 3395/* MC_CMD_PCIE_CREDITS_OUT msgresponse */3396#define MC_CMD_PCIE_CREDITS_OUT_LEN 163397#define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_HDR_OFST 03398#define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_HDR_LEN 23399#define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_DATA_OFST 23400#define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_DATA_LEN 23401#define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_HDR_OFST 43402#define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_HDR_LEN 23403#define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_DATA_OFST 63404#define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_DATA_LEN 23405#define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_HDR_OFST 83406#define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_HDR_LEN 23407#define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_DATA_OFST 103408#define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_DATA_LEN 23409#define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_HDR_OFST 123410#define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_HDR_LEN 23411#define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_DATA_OFST 143412#define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_DATA_LEN 23413 3414 3415/***********************************/3416/* MC_CMD_RXD_MONITOR3417 * Get histogram of RX queue fill level.3418 */3419#define MC_CMD_RXD_MONITOR 0x223420 3421/* MC_CMD_RXD_MONITOR_IN msgrequest */3422#define MC_CMD_RXD_MONITOR_IN_LEN 123423#define MC_CMD_RXD_MONITOR_IN_QID_OFST 03424#define MC_CMD_RXD_MONITOR_IN_QID_LEN 43425#define MC_CMD_RXD_MONITOR_IN_POLL_PERIOD_OFST 43426#define MC_CMD_RXD_MONITOR_IN_POLL_PERIOD_LEN 43427#define MC_CMD_RXD_MONITOR_IN_WIPE_OFST 83428#define MC_CMD_RXD_MONITOR_IN_WIPE_LEN 43429 3430/* MC_CMD_RXD_MONITOR_OUT msgresponse */3431#define MC_CMD_RXD_MONITOR_OUT_LEN 803432#define MC_CMD_RXD_MONITOR_OUT_QID_OFST 03433#define MC_CMD_RXD_MONITOR_OUT_QID_LEN 43434#define MC_CMD_RXD_MONITOR_OUT_RING_FILL_OFST 43435#define MC_CMD_RXD_MONITOR_OUT_RING_FILL_LEN 43436#define MC_CMD_RXD_MONITOR_OUT_CACHE_FILL_OFST 83437#define MC_CMD_RXD_MONITOR_OUT_CACHE_FILL_LEN 43438#define MC_CMD_RXD_MONITOR_OUT_RING_LT_1_OFST 123439#define MC_CMD_RXD_MONITOR_OUT_RING_LT_1_LEN 43440#define MC_CMD_RXD_MONITOR_OUT_RING_LT_2_OFST 163441#define MC_CMD_RXD_MONITOR_OUT_RING_LT_2_LEN 43442#define MC_CMD_RXD_MONITOR_OUT_RING_LT_4_OFST 203443#define MC_CMD_RXD_MONITOR_OUT_RING_LT_4_LEN 43444#define MC_CMD_RXD_MONITOR_OUT_RING_LT_8_OFST 243445#define MC_CMD_RXD_MONITOR_OUT_RING_LT_8_LEN 43446#define MC_CMD_RXD_MONITOR_OUT_RING_LT_16_OFST 283447#define MC_CMD_RXD_MONITOR_OUT_RING_LT_16_LEN 43448#define MC_CMD_RXD_MONITOR_OUT_RING_LT_32_OFST 323449#define MC_CMD_RXD_MONITOR_OUT_RING_LT_32_LEN 43450#define MC_CMD_RXD_MONITOR_OUT_RING_LT_64_OFST 363451#define MC_CMD_RXD_MONITOR_OUT_RING_LT_64_LEN 43452#define MC_CMD_RXD_MONITOR_OUT_RING_LT_128_OFST 403453#define MC_CMD_RXD_MONITOR_OUT_RING_LT_128_LEN 43454#define MC_CMD_RXD_MONITOR_OUT_RING_LT_256_OFST 443455#define MC_CMD_RXD_MONITOR_OUT_RING_LT_256_LEN 43456#define MC_CMD_RXD_MONITOR_OUT_RING_GE_256_OFST 483457#define MC_CMD_RXD_MONITOR_OUT_RING_GE_256_LEN 43458#define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_1_OFST 523459#define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_1_LEN 43460#define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_2_OFST 563461#define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_2_LEN 43462#define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_4_OFST 603463#define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_4_LEN 43464#define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_8_OFST 643465#define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_8_LEN 43466#define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_16_OFST 683467#define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_16_LEN 43468#define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_32_OFST 723469#define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_32_LEN 43470#define MC_CMD_RXD_MONITOR_OUT_CACHE_GE_32_OFST 763471#define MC_CMD_RXD_MONITOR_OUT_CACHE_GE_32_LEN 43472 3473 3474/***********************************/3475/* MC_CMD_PUTS3476 * Copy the given ASCII string out onto UART and/or out of the network port.3477 */3478#define MC_CMD_PUTS 0x233479#undef MC_CMD_0x23_PRIVILEGE_CTG3480 3481#define MC_CMD_0x23_PRIVILEGE_CTG SRIOV_CTG_INSECURE3482 3483/* MC_CMD_PUTS_IN msgrequest */3484#define MC_CMD_PUTS_IN_LENMIN 133485#define MC_CMD_PUTS_IN_LENMAX 2523486#define MC_CMD_PUTS_IN_LENMAX_MCDI2 10203487#define MC_CMD_PUTS_IN_LEN(num) (12+1*(num))3488#define MC_CMD_PUTS_IN_STRING_NUM(len) (((len)-12)/1)3489#define MC_CMD_PUTS_IN_DEST_OFST 03490#define MC_CMD_PUTS_IN_DEST_LEN 43491#define MC_CMD_PUTS_IN_UART_OFST 03492#define MC_CMD_PUTS_IN_UART_LBN 03493#define MC_CMD_PUTS_IN_UART_WIDTH 13494#define MC_CMD_PUTS_IN_PORT_OFST 03495#define MC_CMD_PUTS_IN_PORT_LBN 13496#define MC_CMD_PUTS_IN_PORT_WIDTH 13497#define MC_CMD_PUTS_IN_DHOST_OFST 43498#define MC_CMD_PUTS_IN_DHOST_LEN 63499#define MC_CMD_PUTS_IN_STRING_OFST 123500#define MC_CMD_PUTS_IN_STRING_LEN 13501#define MC_CMD_PUTS_IN_STRING_MINNUM 13502#define MC_CMD_PUTS_IN_STRING_MAXNUM 2403503#define MC_CMD_PUTS_IN_STRING_MAXNUM_MCDI2 10083504 3505/* MC_CMD_PUTS_OUT msgresponse */3506#define MC_CMD_PUTS_OUT_LEN 03507 3508 3509/***********************************/3510/* MC_CMD_GET_PHY_CFG3511 * Report PHY configuration. This guarantees to succeed even if the PHY is in a3512 * 'zombie' state. Locks required: None3513 */3514#define MC_CMD_GET_PHY_CFG 0x243515#undef MC_CMD_0x24_PRIVILEGE_CTG3516 3517#define MC_CMD_0x24_PRIVILEGE_CTG SRIOV_CTG_GENERAL3518 3519/* MC_CMD_GET_PHY_CFG_IN msgrequest */3520#define MC_CMD_GET_PHY_CFG_IN_LEN 03521 3522/* MC_CMD_GET_PHY_CFG_OUT msgresponse */3523#define MC_CMD_GET_PHY_CFG_OUT_LEN 723524/* flags */3525#define MC_CMD_GET_PHY_CFG_OUT_FLAGS_OFST 03526#define MC_CMD_GET_PHY_CFG_OUT_FLAGS_LEN 43527#define MC_CMD_GET_PHY_CFG_OUT_PRESENT_OFST 03528#define MC_CMD_GET_PHY_CFG_OUT_PRESENT_LBN 03529#define MC_CMD_GET_PHY_CFG_OUT_PRESENT_WIDTH 13530#define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_SHORT_OFST 03531#define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_SHORT_LBN 13532#define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_SHORT_WIDTH 13533#define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_LONG_OFST 03534#define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_LONG_LBN 23535#define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_LONG_WIDTH 13536#define MC_CMD_GET_PHY_CFG_OUT_LOWPOWER_OFST 03537#define MC_CMD_GET_PHY_CFG_OUT_LOWPOWER_LBN 33538#define MC_CMD_GET_PHY_CFG_OUT_LOWPOWER_WIDTH 13539#define MC_CMD_GET_PHY_CFG_OUT_POWEROFF_OFST 03540#define MC_CMD_GET_PHY_CFG_OUT_POWEROFF_LBN 43541#define MC_CMD_GET_PHY_CFG_OUT_POWEROFF_WIDTH 13542#define MC_CMD_GET_PHY_CFG_OUT_TXDIS_OFST 03543#define MC_CMD_GET_PHY_CFG_OUT_TXDIS_LBN 53544#define MC_CMD_GET_PHY_CFG_OUT_TXDIS_WIDTH 13545#define MC_CMD_GET_PHY_CFG_OUT_BIST_OFST 03546#define MC_CMD_GET_PHY_CFG_OUT_BIST_LBN 63547#define MC_CMD_GET_PHY_CFG_OUT_BIST_WIDTH 13548/* ?? */3549#define MC_CMD_GET_PHY_CFG_OUT_TYPE_OFST 43550#define MC_CMD_GET_PHY_CFG_OUT_TYPE_LEN 43551/* Bitmask of supported capabilities */3552#define MC_CMD_GET_PHY_CFG_OUT_SUPPORTED_CAP_OFST 83553#define MC_CMD_GET_PHY_CFG_OUT_SUPPORTED_CAP_LEN 43554#define MC_CMD_PHY_CAP_10HDX_OFST 83555#define MC_CMD_PHY_CAP_10HDX_LBN 13556#define MC_CMD_PHY_CAP_10HDX_WIDTH 13557#define MC_CMD_PHY_CAP_10FDX_OFST 83558#define MC_CMD_PHY_CAP_10FDX_LBN 23559#define MC_CMD_PHY_CAP_10FDX_WIDTH 13560#define MC_CMD_PHY_CAP_100HDX_OFST 83561#define MC_CMD_PHY_CAP_100HDX_LBN 33562#define MC_CMD_PHY_CAP_100HDX_WIDTH 13563#define MC_CMD_PHY_CAP_100FDX_OFST 83564#define MC_CMD_PHY_CAP_100FDX_LBN 43565#define MC_CMD_PHY_CAP_100FDX_WIDTH 13566#define MC_CMD_PHY_CAP_1000HDX_OFST 83567#define MC_CMD_PHY_CAP_1000HDX_LBN 53568#define MC_CMD_PHY_CAP_1000HDX_WIDTH 13569#define MC_CMD_PHY_CAP_1000FDX_OFST 83570#define MC_CMD_PHY_CAP_1000FDX_LBN 63571#define MC_CMD_PHY_CAP_1000FDX_WIDTH 13572#define MC_CMD_PHY_CAP_10000FDX_OFST 83573#define MC_CMD_PHY_CAP_10000FDX_LBN 73574#define MC_CMD_PHY_CAP_10000FDX_WIDTH 13575#define MC_CMD_PHY_CAP_PAUSE_OFST 83576#define MC_CMD_PHY_CAP_PAUSE_LBN 83577#define MC_CMD_PHY_CAP_PAUSE_WIDTH 13578#define MC_CMD_PHY_CAP_ASYM_OFST 83579#define MC_CMD_PHY_CAP_ASYM_LBN 93580#define MC_CMD_PHY_CAP_ASYM_WIDTH 13581#define MC_CMD_PHY_CAP_AN_OFST 83582#define MC_CMD_PHY_CAP_AN_LBN 103583#define MC_CMD_PHY_CAP_AN_WIDTH 13584#define MC_CMD_PHY_CAP_40000FDX_OFST 83585#define MC_CMD_PHY_CAP_40000FDX_LBN 113586#define MC_CMD_PHY_CAP_40000FDX_WIDTH 13587#define MC_CMD_PHY_CAP_DDM_OFST 83588#define MC_CMD_PHY_CAP_DDM_LBN 123589#define MC_CMD_PHY_CAP_DDM_WIDTH 13590#define MC_CMD_PHY_CAP_100000FDX_OFST 83591#define MC_CMD_PHY_CAP_100000FDX_LBN 133592#define MC_CMD_PHY_CAP_100000FDX_WIDTH 13593#define MC_CMD_PHY_CAP_25000FDX_OFST 83594#define MC_CMD_PHY_CAP_25000FDX_LBN 143595#define MC_CMD_PHY_CAP_25000FDX_WIDTH 13596#define MC_CMD_PHY_CAP_50000FDX_OFST 83597#define MC_CMD_PHY_CAP_50000FDX_LBN 153598#define MC_CMD_PHY_CAP_50000FDX_WIDTH 13599#define MC_CMD_PHY_CAP_BASER_FEC_OFST 83600#define MC_CMD_PHY_CAP_BASER_FEC_LBN 163601#define MC_CMD_PHY_CAP_BASER_FEC_WIDTH 13602#define MC_CMD_PHY_CAP_BASER_FEC_REQUESTED_OFST 83603#define MC_CMD_PHY_CAP_BASER_FEC_REQUESTED_LBN 173604#define MC_CMD_PHY_CAP_BASER_FEC_REQUESTED_WIDTH 13605#define MC_CMD_PHY_CAP_RS_FEC_OFST 83606#define MC_CMD_PHY_CAP_RS_FEC_LBN 183607#define MC_CMD_PHY_CAP_RS_FEC_WIDTH 13608#define MC_CMD_PHY_CAP_RS_FEC_REQUESTED_OFST 83609#define MC_CMD_PHY_CAP_RS_FEC_REQUESTED_LBN 193610#define MC_CMD_PHY_CAP_RS_FEC_REQUESTED_WIDTH 13611#define MC_CMD_PHY_CAP_25G_BASER_FEC_OFST 83612#define MC_CMD_PHY_CAP_25G_BASER_FEC_LBN 203613#define MC_CMD_PHY_CAP_25G_BASER_FEC_WIDTH 13614#define MC_CMD_PHY_CAP_25G_BASER_FEC_REQUESTED_OFST 83615#define MC_CMD_PHY_CAP_25G_BASER_FEC_REQUESTED_LBN 213616#define MC_CMD_PHY_CAP_25G_BASER_FEC_REQUESTED_WIDTH 13617/* ?? */3618#define MC_CMD_GET_PHY_CFG_OUT_CHANNEL_OFST 123619#define MC_CMD_GET_PHY_CFG_OUT_CHANNEL_LEN 43620/* ?? */3621#define MC_CMD_GET_PHY_CFG_OUT_PRT_OFST 163622#define MC_CMD_GET_PHY_CFG_OUT_PRT_LEN 43623/* ?? */3624#define MC_CMD_GET_PHY_CFG_OUT_STATS_MASK_OFST 203625#define MC_CMD_GET_PHY_CFG_OUT_STATS_MASK_LEN 43626/* ?? */3627#define MC_CMD_GET_PHY_CFG_OUT_NAME_OFST 243628#define MC_CMD_GET_PHY_CFG_OUT_NAME_LEN 203629/* ?? */3630#define MC_CMD_GET_PHY_CFG_OUT_MEDIA_TYPE_OFST 443631#define MC_CMD_GET_PHY_CFG_OUT_MEDIA_TYPE_LEN 43632/* enum: Xaui. */3633#define MC_CMD_MEDIA_XAUI 0x13634/* enum: CX4. */3635#define MC_CMD_MEDIA_CX4 0x23636/* enum: KX4. */3637#define MC_CMD_MEDIA_KX4 0x33638/* enum: XFP Far. */3639#define MC_CMD_MEDIA_XFP 0x43640/* enum: SFP+. */3641#define MC_CMD_MEDIA_SFP_PLUS 0x53642/* enum: 10GBaseT. */3643#define MC_CMD_MEDIA_BASE_T 0x63644/* enum: QSFP+. */3645#define MC_CMD_MEDIA_QSFP_PLUS 0x73646#define MC_CMD_GET_PHY_CFG_OUT_MMD_MASK_OFST 483647#define MC_CMD_GET_PHY_CFG_OUT_MMD_MASK_LEN 43648/* enum: Native clause 22 */3649#define MC_CMD_MMD_CLAUSE22 0x03650#define MC_CMD_MMD_CLAUSE45_PMAPMD 0x1 /* enum */3651#define MC_CMD_MMD_CLAUSE45_WIS 0x2 /* enum */3652#define MC_CMD_MMD_CLAUSE45_PCS 0x3 /* enum */3653#define MC_CMD_MMD_CLAUSE45_PHYXS 0x4 /* enum */3654#define MC_CMD_MMD_CLAUSE45_DTEXS 0x5 /* enum */3655#define MC_CMD_MMD_CLAUSE45_TC 0x6 /* enum */3656#define MC_CMD_MMD_CLAUSE45_AN 0x7 /* enum */3657/* enum: Clause22 proxied over clause45 by PHY. */3658#define MC_CMD_MMD_CLAUSE45_C22EXT 0x1d3659#define MC_CMD_MMD_CLAUSE45_VEND1 0x1e /* enum */3660#define MC_CMD_MMD_CLAUSE45_VEND2 0x1f /* enum */3661#define MC_CMD_GET_PHY_CFG_OUT_REVISION_OFST 523662#define MC_CMD_GET_PHY_CFG_OUT_REVISION_LEN 203663 3664 3665/***********************************/3666/* MC_CMD_START_BIST3667 * Start a BIST test on the PHY. Locks required: PHY_LOCK if doing a PHY BIST3668 * Return code: 0, EINVAL, EACCES (if PHY_LOCK is not held)3669 */3670#define MC_CMD_START_BIST 0x253671#undef MC_CMD_0x25_PRIVILEGE_CTG3672 3673#define MC_CMD_0x25_PRIVILEGE_CTG SRIOV_CTG_ADMIN3674 3675/* MC_CMD_START_BIST_IN msgrequest */3676#define MC_CMD_START_BIST_IN_LEN 43677/* Type of test. */3678#define MC_CMD_START_BIST_IN_TYPE_OFST 03679#define MC_CMD_START_BIST_IN_TYPE_LEN 43680/* enum: Run the PHY's short cable BIST. */3681#define MC_CMD_PHY_BIST_CABLE_SHORT 0x13682/* enum: Run the PHY's long cable BIST. */3683#define MC_CMD_PHY_BIST_CABLE_LONG 0x23684/* enum: Run BIST on the currently selected BPX Serdes (XAUI or XFI) . */3685#define MC_CMD_BPX_SERDES_BIST 0x33686/* enum: Run the MC loopback tests. */3687#define MC_CMD_MC_LOOPBACK_BIST 0x43688/* enum: Run the PHY's standard BIST. */3689#define MC_CMD_PHY_BIST 0x53690/* enum: Run MC RAM test. */3691#define MC_CMD_MC_MEM_BIST 0x63692/* enum: Run Port RAM test. */3693#define MC_CMD_PORT_MEM_BIST 0x73694/* enum: Run register test. */3695#define MC_CMD_REG_BIST 0x83696 3697/* MC_CMD_START_BIST_OUT msgresponse */3698#define MC_CMD_START_BIST_OUT_LEN 03699 3700 3701/***********************************/3702/* MC_CMD_POLL_BIST3703 * Poll for BIST completion. Returns a single status code, and optionally some3704 * PHY specific bist output. The driver should only consume the BIST output3705 * after validating OUTLEN and MC_CMD_GET_PHY_CFG.TYPE. If a driver can't3706 * successfully parse the BIST output, it should still respect the pass/Fail in3707 * OUT.RESULT. Locks required: PHY_LOCK if doing a PHY BIST. Return code: 0,3708 * EACCES (if PHY_LOCK is not held).3709 */3710#define MC_CMD_POLL_BIST 0x263711#undef MC_CMD_0x26_PRIVILEGE_CTG3712 3713#define MC_CMD_0x26_PRIVILEGE_CTG SRIOV_CTG_ADMIN3714 3715/* MC_CMD_POLL_BIST_IN msgrequest */3716#define MC_CMD_POLL_BIST_IN_LEN 03717 3718/* MC_CMD_POLL_BIST_OUT msgresponse */3719#define MC_CMD_POLL_BIST_OUT_LEN 83720/* result */3721#define MC_CMD_POLL_BIST_OUT_RESULT_OFST 03722#define MC_CMD_POLL_BIST_OUT_RESULT_LEN 43723/* enum: Running. */3724#define MC_CMD_POLL_BIST_RUNNING 0x13725/* enum: Passed. */3726#define MC_CMD_POLL_BIST_PASSED 0x23727/* enum: Failed. */3728#define MC_CMD_POLL_BIST_FAILED 0x33729/* enum: Timed-out. */3730#define MC_CMD_POLL_BIST_TIMEOUT 0x43731#define MC_CMD_POLL_BIST_OUT_PRIVATE_OFST 43732#define MC_CMD_POLL_BIST_OUT_PRIVATE_LEN 43733 3734/* MC_CMD_POLL_BIST_OUT_SFT9001 msgresponse */3735#define MC_CMD_POLL_BIST_OUT_SFT9001_LEN 363736/* result */3737/* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */3738/* MC_CMD_POLL_BIST_OUT_RESULT_LEN 4 */3739/* Enum values, see field(s): */3740/* MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */3741#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_A_OFST 43742#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_A_LEN 43743#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_B_OFST 83744#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_B_LEN 43745#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_C_OFST 123746#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_C_LEN 43747#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_D_OFST 163748#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_D_LEN 43749/* Status of each channel A */3750#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_A_OFST 203751#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_A_LEN 43752/* enum: Ok. */3753#define MC_CMD_POLL_BIST_SFT9001_PAIR_OK 0x13754/* enum: Open. */3755#define MC_CMD_POLL_BIST_SFT9001_PAIR_OPEN 0x23756/* enum: Intra-pair short. */3757#define MC_CMD_POLL_BIST_SFT9001_INTRA_PAIR_SHORT 0x33758/* enum: Inter-pair short. */3759#define MC_CMD_POLL_BIST_SFT9001_INTER_PAIR_SHORT 0x43760/* enum: Busy. */3761#define MC_CMD_POLL_BIST_SFT9001_PAIR_BUSY 0x93762/* Status of each channel B */3763#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_B_OFST 243764#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_B_LEN 43765/* Enum values, see field(s): */3766/* CABLE_STATUS_A */3767/* Status of each channel C */3768#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_C_OFST 283769#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_C_LEN 43770/* Enum values, see field(s): */3771/* CABLE_STATUS_A */3772/* Status of each channel D */3773#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_D_OFST 323774#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_D_LEN 43775/* Enum values, see field(s): */3776/* CABLE_STATUS_A */3777 3778/* MC_CMD_POLL_BIST_OUT_MRSFP msgresponse */3779#define MC_CMD_POLL_BIST_OUT_MRSFP_LEN 83780/* result */3781/* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */3782/* MC_CMD_POLL_BIST_OUT_RESULT_LEN 4 */3783/* Enum values, see field(s): */3784/* MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */3785#define MC_CMD_POLL_BIST_OUT_MRSFP_TEST_OFST 43786#define MC_CMD_POLL_BIST_OUT_MRSFP_TEST_LEN 43787/* enum: Complete. */3788#define MC_CMD_POLL_BIST_MRSFP_TEST_COMPLETE 0x03789/* enum: Bus switch off I2C write. */3790#define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_WRITE 0x13791/* enum: Bus switch off I2C no access IO exp. */3792#define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_NO_ACCESS_IO_EXP 0x23793/* enum: Bus switch off I2C no access module. */3794#define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_NO_ACCESS_MODULE 0x33795/* enum: IO exp I2C configure. */3796#define MC_CMD_POLL_BIST_MRSFP_TEST_IO_EXP_I2C_CONFIGURE 0x43797/* enum: Bus switch I2C no cross talk. */3798#define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_I2C_NO_CROSSTALK 0x53799/* enum: Module presence. */3800#define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_PRESENCE 0x63801/* enum: Module ID I2C access. */3802#define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_ID_I2C_ACCESS 0x73803/* enum: Module ID sane value. */3804#define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_ID_SANE_VALUE 0x83805 3806/* MC_CMD_POLL_BIST_OUT_MEM msgresponse */3807#define MC_CMD_POLL_BIST_OUT_MEM_LEN 363808/* result */3809/* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */3810/* MC_CMD_POLL_BIST_OUT_RESULT_LEN 4 */3811/* Enum values, see field(s): */3812/* MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */3813#define MC_CMD_POLL_BIST_OUT_MEM_TEST_OFST 43814#define MC_CMD_POLL_BIST_OUT_MEM_TEST_LEN 43815/* enum: Test has completed. */3816#define MC_CMD_POLL_BIST_MEM_COMPLETE 0x03817/* enum: RAM test - walk ones. */3818#define MC_CMD_POLL_BIST_MEM_MEM_WALK_ONES 0x13819/* enum: RAM test - walk zeros. */3820#define MC_CMD_POLL_BIST_MEM_MEM_WALK_ZEROS 0x23821/* enum: RAM test - walking inversions zeros/ones. */3822#define MC_CMD_POLL_BIST_MEM_MEM_INV_ZERO_ONE 0x33823/* enum: RAM test - walking inversions checkerboard. */3824#define MC_CMD_POLL_BIST_MEM_MEM_INV_CHKBOARD 0x43825/* enum: Register test - set / clear individual bits. */3826#define MC_CMD_POLL_BIST_MEM_REG 0x53827/* enum: ECC error detected. */3828#define MC_CMD_POLL_BIST_MEM_ECC 0x63829/* Failure address, only valid if result is POLL_BIST_FAILED */3830#define MC_CMD_POLL_BIST_OUT_MEM_ADDR_OFST 83831#define MC_CMD_POLL_BIST_OUT_MEM_ADDR_LEN 43832/* Bus or address space to which the failure address corresponds */3833#define MC_CMD_POLL_BIST_OUT_MEM_BUS_OFST 123834#define MC_CMD_POLL_BIST_OUT_MEM_BUS_LEN 43835/* enum: MC MIPS bus. */3836#define MC_CMD_POLL_BIST_MEM_BUS_MC 0x03837/* enum: CSR IREG bus. */3838#define MC_CMD_POLL_BIST_MEM_BUS_CSR 0x13839/* enum: RX0 DPCPU bus. */3840#define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_RX 0x23841/* enum: TX0 DPCPU bus. */3842#define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_TX0 0x33843/* enum: TX1 DPCPU bus. */3844#define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_TX1 0x43845/* enum: RX0 DICPU bus. */3846#define MC_CMD_POLL_BIST_MEM_BUS_DICPU_RX 0x53847/* enum: TX DICPU bus. */3848#define MC_CMD_POLL_BIST_MEM_BUS_DICPU_TX 0x63849/* enum: RX1 DPCPU bus. */3850#define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_RX1 0x73851/* enum: RX1 DICPU bus. */3852#define MC_CMD_POLL_BIST_MEM_BUS_DICPU_RX1 0x83853/* Pattern written to RAM / register */3854#define MC_CMD_POLL_BIST_OUT_MEM_EXPECT_OFST 163855#define MC_CMD_POLL_BIST_OUT_MEM_EXPECT_LEN 43856/* Actual value read from RAM / register */3857#define MC_CMD_POLL_BIST_OUT_MEM_ACTUAL_OFST 203858#define MC_CMD_POLL_BIST_OUT_MEM_ACTUAL_LEN 43859/* ECC error mask */3860#define MC_CMD_POLL_BIST_OUT_MEM_ECC_OFST 243861#define MC_CMD_POLL_BIST_OUT_MEM_ECC_LEN 43862/* ECC parity error mask */3863#define MC_CMD_POLL_BIST_OUT_MEM_ECC_PARITY_OFST 283864#define MC_CMD_POLL_BIST_OUT_MEM_ECC_PARITY_LEN 43865/* ECC fatal error mask */3866#define MC_CMD_POLL_BIST_OUT_MEM_ECC_FATAL_OFST 323867#define MC_CMD_POLL_BIST_OUT_MEM_ECC_FATAL_LEN 43868 3869 3870/***********************************/3871/* MC_CMD_FLUSH_RX_QUEUES3872 * Flush receive queue(s). If SRIOV is enabled (via MC_CMD_SRIOV), then RXQ3873 * flushes should be initiated via this MCDI operation, rather than via3874 * directly writing FLUSH_CMD.3875 *3876 * The flush is completed (either done/fail) asynchronously (after this command3877 * returns). The driver must still wait for flush done/failure events as usual.3878 */3879#define MC_CMD_FLUSH_RX_QUEUES 0x273880 3881/* MC_CMD_FLUSH_RX_QUEUES_IN msgrequest */3882#define MC_CMD_FLUSH_RX_QUEUES_IN_LENMIN 43883#define MC_CMD_FLUSH_RX_QUEUES_IN_LENMAX 2523884#define MC_CMD_FLUSH_RX_QUEUES_IN_LENMAX_MCDI2 10203885#define MC_CMD_FLUSH_RX_QUEUES_IN_LEN(num) (0+4*(num))3886#define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_NUM(len) (((len)-0)/4)3887#define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_OFST 03888#define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_LEN 43889#define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_MINNUM 13890#define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_MAXNUM 633891#define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_MAXNUM_MCDI2 2553892 3893/* MC_CMD_FLUSH_RX_QUEUES_OUT msgresponse */3894#define MC_CMD_FLUSH_RX_QUEUES_OUT_LEN 03895 3896 3897/***********************************/3898/* MC_CMD_GET_LOOPBACK_MODES3899 * Returns a bitmask of loopback modes available at each speed.3900 */3901#define MC_CMD_GET_LOOPBACK_MODES 0x283902#undef MC_CMD_0x28_PRIVILEGE_CTG3903 3904#define MC_CMD_0x28_PRIVILEGE_CTG SRIOV_CTG_GENERAL3905 3906/* MC_CMD_GET_LOOPBACK_MODES_IN msgrequest */3907#define MC_CMD_GET_LOOPBACK_MODES_IN_LEN 03908 3909/* MC_CMD_GET_LOOPBACK_MODES_OUT msgresponse */3910#define MC_CMD_GET_LOOPBACK_MODES_OUT_LEN 403911/* Supported loopbacks. */3912#define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_OFST 03913#define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LEN 83914#define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LO_OFST 03915#define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_HI_OFST 43916/* enum: None. */3917#define MC_CMD_LOOPBACK_NONE 0x03918/* enum: Data. */3919#define MC_CMD_LOOPBACK_DATA 0x13920/* enum: GMAC. */3921#define MC_CMD_LOOPBACK_GMAC 0x23922/* enum: XGMII. */3923#define MC_CMD_LOOPBACK_XGMII 0x33924/* enum: XGXS. */3925#define MC_CMD_LOOPBACK_XGXS 0x43926/* enum: XAUI. */3927#define MC_CMD_LOOPBACK_XAUI 0x53928/* enum: GMII. */3929#define MC_CMD_LOOPBACK_GMII 0x63930/* enum: SGMII. */3931#define MC_CMD_LOOPBACK_SGMII 0x73932/* enum: XGBR. */3933#define MC_CMD_LOOPBACK_XGBR 0x83934/* enum: XFI. */3935#define MC_CMD_LOOPBACK_XFI 0x93936/* enum: XAUI Far. */3937#define MC_CMD_LOOPBACK_XAUI_FAR 0xa3938/* enum: GMII Far. */3939#define MC_CMD_LOOPBACK_GMII_FAR 0xb3940/* enum: SGMII Far. */3941#define MC_CMD_LOOPBACK_SGMII_FAR 0xc3942/* enum: XFI Far. */3943#define MC_CMD_LOOPBACK_XFI_FAR 0xd3944/* enum: GPhy. */3945#define MC_CMD_LOOPBACK_GPHY 0xe3946/* enum: PhyXS. */3947#define MC_CMD_LOOPBACK_PHYXS 0xf3948/* enum: PCS. */3949#define MC_CMD_LOOPBACK_PCS 0x103950/* enum: PMA-PMD. */3951#define MC_CMD_LOOPBACK_PMAPMD 0x113952/* enum: Cross-Port. */3953#define MC_CMD_LOOPBACK_XPORT 0x123954/* enum: XGMII-Wireside. */3955#define MC_CMD_LOOPBACK_XGMII_WS 0x133956/* enum: XAUI Wireside. */3957#define MC_CMD_LOOPBACK_XAUI_WS 0x143958/* enum: XAUI Wireside Far. */3959#define MC_CMD_LOOPBACK_XAUI_WS_FAR 0x153960/* enum: XAUI Wireside near. */3961#define MC_CMD_LOOPBACK_XAUI_WS_NEAR 0x163962/* enum: GMII Wireside. */3963#define MC_CMD_LOOPBACK_GMII_WS 0x173964/* enum: XFI Wireside. */3965#define MC_CMD_LOOPBACK_XFI_WS 0x183966/* enum: XFI Wireside Far. */3967#define MC_CMD_LOOPBACK_XFI_WS_FAR 0x193968/* enum: PhyXS Wireside. */3969#define MC_CMD_LOOPBACK_PHYXS_WS 0x1a3970/* enum: PMA lanes MAC-Serdes. */3971#define MC_CMD_LOOPBACK_PMA_INT 0x1b3972/* enum: KR Serdes Parallel (Encoder). */3973#define MC_CMD_LOOPBACK_SD_NEAR 0x1c3974/* enum: KR Serdes Serial. */3975#define MC_CMD_LOOPBACK_SD_FAR 0x1d3976/* enum: PMA lanes MAC-Serdes Wireside. */3977#define MC_CMD_LOOPBACK_PMA_INT_WS 0x1e3978/* enum: KR Serdes Parallel Wireside (Full PCS). */3979#define MC_CMD_LOOPBACK_SD_FEP2_WS 0x1f3980/* enum: KR Serdes Parallel Wireside (Sym Aligner to TX). */3981#define MC_CMD_LOOPBACK_SD_FEP1_5_WS 0x203982/* enum: KR Serdes Parallel Wireside (Deserializer to Serializer). */3983#define MC_CMD_LOOPBACK_SD_FEP_WS 0x213984/* enum: KR Serdes Serial Wireside. */3985#define MC_CMD_LOOPBACK_SD_FES_WS 0x223986/* enum: Near side of AOE Siena side port */3987#define MC_CMD_LOOPBACK_AOE_INT_NEAR 0x233988/* enum: Medford Wireside datapath loopback */3989#define MC_CMD_LOOPBACK_DATA_WS 0x243990/* enum: Force link up without setting up any physical loopback (snapper use3991 * only)3992 */3993#define MC_CMD_LOOPBACK_FORCE_EXT_LINK 0x253994/* Supported loopbacks. */3995#define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_OFST 83996#define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_LEN 83997#define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_LO_OFST 83998#define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_HI_OFST 123999/* Enum values, see field(s): */4000/* 100M */4001/* Supported loopbacks. */4002#define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_OFST 164003#define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_LEN 84004#define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_LO_OFST 164005#define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_HI_OFST 204006/* Enum values, see field(s): */4007/* 100M */4008/* Supported loopbacks. */4009#define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_OFST 244010#define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LEN 84011#define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LO_OFST 244012#define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_HI_OFST 284013/* Enum values, see field(s): */4014/* 100M */4015/* Supported loopbacks. */4016#define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_OFST 324017#define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LEN 84018#define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LO_OFST 324019#define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_HI_OFST 364020/* Enum values, see field(s): */4021/* 100M */4022 4023/* MC_CMD_GET_LOOPBACK_MODES_OUT_V2 msgresponse: Supported loopback modes for4024 * newer NICs with 25G/50G/100G support4025 */4026#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_LEN 644027/* Supported loopbacks. */4028#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_OFST 04029#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_LEN 84030#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_LO_OFST 04031#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_HI_OFST 44032/* enum: None. */4033/* MC_CMD_LOOPBACK_NONE 0x0 */4034/* enum: Data. */4035/* MC_CMD_LOOPBACK_DATA 0x1 */4036/* enum: GMAC. */4037/* MC_CMD_LOOPBACK_GMAC 0x2 */4038/* enum: XGMII. */4039/* MC_CMD_LOOPBACK_XGMII 0x3 */4040/* enum: XGXS. */4041/* MC_CMD_LOOPBACK_XGXS 0x4 */4042/* enum: XAUI. */4043/* MC_CMD_LOOPBACK_XAUI 0x5 */4044/* enum: GMII. */4045/* MC_CMD_LOOPBACK_GMII 0x6 */4046/* enum: SGMII. */4047/* MC_CMD_LOOPBACK_SGMII 0x7 */4048/* enum: XGBR. */4049/* MC_CMD_LOOPBACK_XGBR 0x8 */4050/* enum: XFI. */4051/* MC_CMD_LOOPBACK_XFI 0x9 */4052/* enum: XAUI Far. */4053/* MC_CMD_LOOPBACK_XAUI_FAR 0xa */4054/* enum: GMII Far. */4055/* MC_CMD_LOOPBACK_GMII_FAR 0xb */4056/* enum: SGMII Far. */4057/* MC_CMD_LOOPBACK_SGMII_FAR 0xc */4058/* enum: XFI Far. */4059/* MC_CMD_LOOPBACK_XFI_FAR 0xd */4060/* enum: GPhy. */4061/* MC_CMD_LOOPBACK_GPHY 0xe */4062/* enum: PhyXS. */4063/* MC_CMD_LOOPBACK_PHYXS 0xf */4064/* enum: PCS. */4065/* MC_CMD_LOOPBACK_PCS 0x10 */4066/* enum: PMA-PMD. */4067/* MC_CMD_LOOPBACK_PMAPMD 0x11 */4068/* enum: Cross-Port. */4069/* MC_CMD_LOOPBACK_XPORT 0x12 */4070/* enum: XGMII-Wireside. */4071/* MC_CMD_LOOPBACK_XGMII_WS 0x13 */4072/* enum: XAUI Wireside. */4073/* MC_CMD_LOOPBACK_XAUI_WS 0x14 */4074/* enum: XAUI Wireside Far. */4075/* MC_CMD_LOOPBACK_XAUI_WS_FAR 0x15 */4076/* enum: XAUI Wireside near. */4077/* MC_CMD_LOOPBACK_XAUI_WS_NEAR 0x16 */4078/* enum: GMII Wireside. */4079/* MC_CMD_LOOPBACK_GMII_WS 0x17 */4080/* enum: XFI Wireside. */4081/* MC_CMD_LOOPBACK_XFI_WS 0x18 */4082/* enum: XFI Wireside Far. */4083/* MC_CMD_LOOPBACK_XFI_WS_FAR 0x19 */4084/* enum: PhyXS Wireside. */4085/* MC_CMD_LOOPBACK_PHYXS_WS 0x1a */4086/* enum: PMA lanes MAC-Serdes. */4087/* MC_CMD_LOOPBACK_PMA_INT 0x1b */4088/* enum: KR Serdes Parallel (Encoder). */4089/* MC_CMD_LOOPBACK_SD_NEAR 0x1c */4090/* enum: KR Serdes Serial. */4091/* MC_CMD_LOOPBACK_SD_FAR 0x1d */4092/* enum: PMA lanes MAC-Serdes Wireside. */4093/* MC_CMD_LOOPBACK_PMA_INT_WS 0x1e */4094/* enum: KR Serdes Parallel Wireside (Full PCS). */4095/* MC_CMD_LOOPBACK_SD_FEP2_WS 0x1f */4096/* enum: KR Serdes Parallel Wireside (Sym Aligner to TX). */4097/* MC_CMD_LOOPBACK_SD_FEP1_5_WS 0x20 */4098/* enum: KR Serdes Parallel Wireside (Deserializer to Serializer). */4099/* MC_CMD_LOOPBACK_SD_FEP_WS 0x21 */4100/* enum: KR Serdes Serial Wireside. */4101/* MC_CMD_LOOPBACK_SD_FES_WS 0x22 */4102/* enum: Near side of AOE Siena side port */4103/* MC_CMD_LOOPBACK_AOE_INT_NEAR 0x23 */4104/* enum: Medford Wireside datapath loopback */4105/* MC_CMD_LOOPBACK_DATA_WS 0x24 */4106/* enum: Force link up without setting up any physical loopback (snapper use4107 * only)4108 */4109/* MC_CMD_LOOPBACK_FORCE_EXT_LINK 0x25 */4110/* Supported loopbacks. */4111#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_OFST 84112#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_LEN 84113#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_LO_OFST 84114#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_HI_OFST 124115/* Enum values, see field(s): */4116/* 100M */4117/* Supported loopbacks. */4118#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_OFST 164119#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_LEN 84120#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_LO_OFST 164121#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_HI_OFST 204122/* Enum values, see field(s): */4123/* 100M */4124/* Supported loopbacks. */4125#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_OFST 244126#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_LEN 84127#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_LO_OFST 244128#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_HI_OFST 284129/* Enum values, see field(s): */4130/* 100M */4131/* Supported loopbacks. */4132#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_OFST 324133#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_LEN 84134#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_LO_OFST 324135#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_HI_OFST 364136/* Enum values, see field(s): */4137/* 100M */4138/* Supported 25G loopbacks. */4139#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_OFST 404140#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_LEN 84141#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_LO_OFST 404142#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_HI_OFST 444143/* Enum values, see field(s): */4144/* 100M */4145/* Supported 50 loopbacks. */4146#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_OFST 484147#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_LEN 84148#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_LO_OFST 484149#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_HI_OFST 524150/* Enum values, see field(s): */4151/* 100M */4152/* Supported 100G loopbacks. */4153#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_OFST 564154#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_LEN 84155#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_LO_OFST 564156#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_HI_OFST 604157/* Enum values, see field(s): */4158/* 100M */4159 4160/* AN_TYPE structuredef: Auto-negotiation types defined in IEEE802.3 */4161#define AN_TYPE_LEN 44162#define AN_TYPE_TYPE_OFST 04163#define AN_TYPE_TYPE_LEN 44164/* enum: None, AN disabled or not supported */4165#define MC_CMD_AN_NONE 0x04166/* enum: Clause 28 - BASE-T */4167#define MC_CMD_AN_CLAUSE28 0x14168/* enum: Clause 37 - BASE-X */4169#define MC_CMD_AN_CLAUSE37 0x24170/* enum: Clause 73 - BASE-R startup protocol for backplane and copper cable4171 * assemblies. Includes Clause 72/Clause 92 link-training.4172 */4173#define MC_CMD_AN_CLAUSE73 0x34174#define AN_TYPE_TYPE_LBN 04175#define AN_TYPE_TYPE_WIDTH 324176 4177/* FEC_TYPE structuredef: Forward error correction types defined in IEEE802.34178 */4179#define FEC_TYPE_LEN 44180#define FEC_TYPE_TYPE_OFST 04181#define FEC_TYPE_TYPE_LEN 44182/* enum: No FEC */4183#define MC_CMD_FEC_NONE 0x04184/* enum: Clause 74 BASE-R FEC (a.k.a Firecode) */4185#define MC_CMD_FEC_BASER 0x14186/* enum: Clause 91/Clause 108 Reed-Solomon FEC */4187#define MC_CMD_FEC_RS 0x24188#define FEC_TYPE_TYPE_LBN 04189#define FEC_TYPE_TYPE_WIDTH 324190 4191 4192/***********************************/4193/* MC_CMD_GET_LINK4194 * Read the unified MAC/PHY link state. Locks required: None Return code: 0,4195 * ETIME.4196 */4197#define MC_CMD_GET_LINK 0x294198#undef MC_CMD_0x29_PRIVILEGE_CTG4199 4200#define MC_CMD_0x29_PRIVILEGE_CTG SRIOV_CTG_GENERAL4201 4202/* MC_CMD_GET_LINK_IN msgrequest */4203#define MC_CMD_GET_LINK_IN_LEN 04204 4205/* MC_CMD_GET_LINK_OUT msgresponse */4206#define MC_CMD_GET_LINK_OUT_LEN 284207/* Near-side advertised capabilities. Refer to4208 * MC_CMD_GET_PHY_CFG_OUT/SUPPORTED_CAP for bit definitions.4209 */4210#define MC_CMD_GET_LINK_OUT_CAP_OFST 04211#define MC_CMD_GET_LINK_OUT_CAP_LEN 44212/* Link-partner advertised capabilities. Refer to4213 * MC_CMD_GET_PHY_CFG_OUT/SUPPORTED_CAP for bit definitions.4214 */4215#define MC_CMD_GET_LINK_OUT_LP_CAP_OFST 44216#define MC_CMD_GET_LINK_OUT_LP_CAP_LEN 44217/* Autonegotiated speed in mbit/s. The link may still be down even if this4218 * reads non-zero.4219 */4220#define MC_CMD_GET_LINK_OUT_LINK_SPEED_OFST 84221#define MC_CMD_GET_LINK_OUT_LINK_SPEED_LEN 44222/* Current loopback setting. */4223#define MC_CMD_GET_LINK_OUT_LOOPBACK_MODE_OFST 124224#define MC_CMD_GET_LINK_OUT_LOOPBACK_MODE_LEN 44225/* Enum values, see field(s): */4226/* MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */4227#define MC_CMD_GET_LINK_OUT_FLAGS_OFST 164228#define MC_CMD_GET_LINK_OUT_FLAGS_LEN 44229#define MC_CMD_GET_LINK_OUT_LINK_UP_OFST 164230#define MC_CMD_GET_LINK_OUT_LINK_UP_LBN 04231#define MC_CMD_GET_LINK_OUT_LINK_UP_WIDTH 14232#define MC_CMD_GET_LINK_OUT_FULL_DUPLEX_OFST 164233#define MC_CMD_GET_LINK_OUT_FULL_DUPLEX_LBN 14234#define MC_CMD_GET_LINK_OUT_FULL_DUPLEX_WIDTH 14235#define MC_CMD_GET_LINK_OUT_BPX_LINK_OFST 164236#define MC_CMD_GET_LINK_OUT_BPX_LINK_LBN 24237#define MC_CMD_GET_LINK_OUT_BPX_LINK_WIDTH 14238#define MC_CMD_GET_LINK_OUT_PHY_LINK_OFST 164239#define MC_CMD_GET_LINK_OUT_PHY_LINK_LBN 34240#define MC_CMD_GET_LINK_OUT_PHY_LINK_WIDTH 14241#define MC_CMD_GET_LINK_OUT_LINK_FAULT_RX_OFST 164242#define MC_CMD_GET_LINK_OUT_LINK_FAULT_RX_LBN 64243#define MC_CMD_GET_LINK_OUT_LINK_FAULT_RX_WIDTH 14244#define MC_CMD_GET_LINK_OUT_LINK_FAULT_TX_OFST 164245#define MC_CMD_GET_LINK_OUT_LINK_FAULT_TX_LBN 74246#define MC_CMD_GET_LINK_OUT_LINK_FAULT_TX_WIDTH 14247#define MC_CMD_GET_LINK_OUT_MODULE_UP_VALID_OFST 164248#define MC_CMD_GET_LINK_OUT_MODULE_UP_VALID_LBN 84249#define MC_CMD_GET_LINK_OUT_MODULE_UP_VALID_WIDTH 14250#define MC_CMD_GET_LINK_OUT_MODULE_UP_OFST 164251#define MC_CMD_GET_LINK_OUT_MODULE_UP_LBN 94252#define MC_CMD_GET_LINK_OUT_MODULE_UP_WIDTH 14253/* This returns the negotiated flow control value. */4254#define MC_CMD_GET_LINK_OUT_FCNTL_OFST 204255#define MC_CMD_GET_LINK_OUT_FCNTL_LEN 44256/* Enum values, see field(s): */4257/* MC_CMD_SET_MAC/MC_CMD_SET_MAC_IN/FCNTL */4258#define MC_CMD_GET_LINK_OUT_MAC_FAULT_OFST 244259#define MC_CMD_GET_LINK_OUT_MAC_FAULT_LEN 44260#define MC_CMD_MAC_FAULT_XGMII_LOCAL_OFST 244261#define MC_CMD_MAC_FAULT_XGMII_LOCAL_LBN 04262#define MC_CMD_MAC_FAULT_XGMII_LOCAL_WIDTH 14263#define MC_CMD_MAC_FAULT_XGMII_REMOTE_OFST 244264#define MC_CMD_MAC_FAULT_XGMII_REMOTE_LBN 14265#define MC_CMD_MAC_FAULT_XGMII_REMOTE_WIDTH 14266#define MC_CMD_MAC_FAULT_SGMII_REMOTE_OFST 244267#define MC_CMD_MAC_FAULT_SGMII_REMOTE_LBN 24268#define MC_CMD_MAC_FAULT_SGMII_REMOTE_WIDTH 14269#define MC_CMD_MAC_FAULT_PENDING_RECONFIG_OFST 244270#define MC_CMD_MAC_FAULT_PENDING_RECONFIG_LBN 34271#define MC_CMD_MAC_FAULT_PENDING_RECONFIG_WIDTH 14272 4273/* MC_CMD_GET_LINK_OUT_V2 msgresponse: Extended link state information */4274#define MC_CMD_GET_LINK_OUT_V2_LEN 444275/* Near-side advertised capabilities. Refer to4276 * MC_CMD_GET_PHY_CFG_OUT/SUPPORTED_CAP for bit definitions.4277 */4278#define MC_CMD_GET_LINK_OUT_V2_CAP_OFST 04279#define MC_CMD_GET_LINK_OUT_V2_CAP_LEN 44280/* Link-partner advertised capabilities. Refer to4281 * MC_CMD_GET_PHY_CFG_OUT/SUPPORTED_CAP for bit definitions.4282 */4283#define MC_CMD_GET_LINK_OUT_V2_LP_CAP_OFST 44284#define MC_CMD_GET_LINK_OUT_V2_LP_CAP_LEN 44285/* Autonegotiated speed in mbit/s. The link may still be down even if this4286 * reads non-zero.4287 */4288#define MC_CMD_GET_LINK_OUT_V2_LINK_SPEED_OFST 84289#define MC_CMD_GET_LINK_OUT_V2_LINK_SPEED_LEN 44290/* Current loopback setting. */4291#define MC_CMD_GET_LINK_OUT_V2_LOOPBACK_MODE_OFST 124292#define MC_CMD_GET_LINK_OUT_V2_LOOPBACK_MODE_LEN 44293/* Enum values, see field(s): */4294/* MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */4295#define MC_CMD_GET_LINK_OUT_V2_FLAGS_OFST 164296#define MC_CMD_GET_LINK_OUT_V2_FLAGS_LEN 44297#define MC_CMD_GET_LINK_OUT_V2_LINK_UP_OFST 164298#define MC_CMD_GET_LINK_OUT_V2_LINK_UP_LBN 04299#define MC_CMD_GET_LINK_OUT_V2_LINK_UP_WIDTH 14300#define MC_CMD_GET_LINK_OUT_V2_FULL_DUPLEX_OFST 164301#define MC_CMD_GET_LINK_OUT_V2_FULL_DUPLEX_LBN 14302#define MC_CMD_GET_LINK_OUT_V2_FULL_DUPLEX_WIDTH 14303#define MC_CMD_GET_LINK_OUT_V2_BPX_LINK_OFST 164304#define MC_CMD_GET_LINK_OUT_V2_BPX_LINK_LBN 24305#define MC_CMD_GET_LINK_OUT_V2_BPX_LINK_WIDTH 14306#define MC_CMD_GET_LINK_OUT_V2_PHY_LINK_OFST 164307#define MC_CMD_GET_LINK_OUT_V2_PHY_LINK_LBN 34308#define MC_CMD_GET_LINK_OUT_V2_PHY_LINK_WIDTH 14309#define MC_CMD_GET_LINK_OUT_V2_LINK_FAULT_RX_OFST 164310#define MC_CMD_GET_LINK_OUT_V2_LINK_FAULT_RX_LBN 64311#define MC_CMD_GET_LINK_OUT_V2_LINK_FAULT_RX_WIDTH 14312#define MC_CMD_GET_LINK_OUT_V2_LINK_FAULT_TX_OFST 164313#define MC_CMD_GET_LINK_OUT_V2_LINK_FAULT_TX_LBN 74314#define MC_CMD_GET_LINK_OUT_V2_LINK_FAULT_TX_WIDTH 14315#define MC_CMD_GET_LINK_OUT_V2_MODULE_UP_VALID_OFST 164316#define MC_CMD_GET_LINK_OUT_V2_MODULE_UP_VALID_LBN 84317#define MC_CMD_GET_LINK_OUT_V2_MODULE_UP_VALID_WIDTH 14318#define MC_CMD_GET_LINK_OUT_V2_MODULE_UP_OFST 164319#define MC_CMD_GET_LINK_OUT_V2_MODULE_UP_LBN 94320#define MC_CMD_GET_LINK_OUT_V2_MODULE_UP_WIDTH 14321/* This returns the negotiated flow control value. */4322#define MC_CMD_GET_LINK_OUT_V2_FCNTL_OFST 204323#define MC_CMD_GET_LINK_OUT_V2_FCNTL_LEN 44324/* Enum values, see field(s): */4325/* MC_CMD_SET_MAC/MC_CMD_SET_MAC_IN/FCNTL */4326#define MC_CMD_GET_LINK_OUT_V2_MAC_FAULT_OFST 244327#define MC_CMD_GET_LINK_OUT_V2_MAC_FAULT_LEN 44328/* MC_CMD_MAC_FAULT_XGMII_LOCAL_OFST 24 */4329/* MC_CMD_MAC_FAULT_XGMII_LOCAL_LBN 0 */4330/* MC_CMD_MAC_FAULT_XGMII_LOCAL_WIDTH 1 */4331/* MC_CMD_MAC_FAULT_XGMII_REMOTE_OFST 24 */4332/* MC_CMD_MAC_FAULT_XGMII_REMOTE_LBN 1 */4333/* MC_CMD_MAC_FAULT_XGMII_REMOTE_WIDTH 1 */4334/* MC_CMD_MAC_FAULT_SGMII_REMOTE_OFST 24 */4335/* MC_CMD_MAC_FAULT_SGMII_REMOTE_LBN 2 */4336/* MC_CMD_MAC_FAULT_SGMII_REMOTE_WIDTH 1 */4337/* MC_CMD_MAC_FAULT_PENDING_RECONFIG_OFST 24 */4338/* MC_CMD_MAC_FAULT_PENDING_RECONFIG_LBN 3 */4339/* MC_CMD_MAC_FAULT_PENDING_RECONFIG_WIDTH 1 */4340/* True local device capabilities (taking into account currently used PMD/MDI,4341 * e.g. plugged-in module). In general, subset of4342 * MC_CMD_GET_PHY_CFG_OUT/SUPPORTED_CAP, but may include extra _FEC_REQUEST4343 * bits, if the PMD requires FEC. 0 if unknown (e.g. module unplugged). Equal4344 * to SUPPORTED_CAP for non-pluggable PMDs. Refer to4345 * MC_CMD_GET_PHY_CFG_OUT/SUPPORTED_CAP for bit definitions.4346 */4347#define MC_CMD_GET_LINK_OUT_V2_LD_CAP_OFST 284348#define MC_CMD_GET_LINK_OUT_V2_LD_CAP_LEN 44349/* Auto-negotiation type used on the link */4350#define MC_CMD_GET_LINK_OUT_V2_AN_TYPE_OFST 324351#define MC_CMD_GET_LINK_OUT_V2_AN_TYPE_LEN 44352/* Enum values, see field(s): */4353/* AN_TYPE/TYPE */4354/* Forward error correction used on the link */4355#define MC_CMD_GET_LINK_OUT_V2_FEC_TYPE_OFST 364356#define MC_CMD_GET_LINK_OUT_V2_FEC_TYPE_LEN 44357/* Enum values, see field(s): */4358/* FEC_TYPE/TYPE */4359#define MC_CMD_GET_LINK_OUT_V2_EXT_FLAGS_OFST 404360#define MC_CMD_GET_LINK_OUT_V2_EXT_FLAGS_LEN 44361#define MC_CMD_GET_LINK_OUT_V2_PMD_MDI_CONNECTED_OFST 404362#define MC_CMD_GET_LINK_OUT_V2_PMD_MDI_CONNECTED_LBN 04363#define MC_CMD_GET_LINK_OUT_V2_PMD_MDI_CONNECTED_WIDTH 14364#define MC_CMD_GET_LINK_OUT_V2_PMD_READY_OFST 404365#define MC_CMD_GET_LINK_OUT_V2_PMD_READY_LBN 14366#define MC_CMD_GET_LINK_OUT_V2_PMD_READY_WIDTH 14367#define MC_CMD_GET_LINK_OUT_V2_PMD_LINK_UP_OFST 404368#define MC_CMD_GET_LINK_OUT_V2_PMD_LINK_UP_LBN 24369#define MC_CMD_GET_LINK_OUT_V2_PMD_LINK_UP_WIDTH 14370#define MC_CMD_GET_LINK_OUT_V2_PMA_LINK_UP_OFST 404371#define MC_CMD_GET_LINK_OUT_V2_PMA_LINK_UP_LBN 34372#define MC_CMD_GET_LINK_OUT_V2_PMA_LINK_UP_WIDTH 14373#define MC_CMD_GET_LINK_OUT_V2_PCS_LOCK_OFST 404374#define MC_CMD_GET_LINK_OUT_V2_PCS_LOCK_LBN 44375#define MC_CMD_GET_LINK_OUT_V2_PCS_LOCK_WIDTH 14376#define MC_CMD_GET_LINK_OUT_V2_ALIGN_LOCK_OFST 404377#define MC_CMD_GET_LINK_OUT_V2_ALIGN_LOCK_LBN 54378#define MC_CMD_GET_LINK_OUT_V2_ALIGN_LOCK_WIDTH 14379#define MC_CMD_GET_LINK_OUT_V2_HI_BER_OFST 404380#define MC_CMD_GET_LINK_OUT_V2_HI_BER_LBN 64381#define MC_CMD_GET_LINK_OUT_V2_HI_BER_WIDTH 14382#define MC_CMD_GET_LINK_OUT_V2_FEC_LOCK_OFST 404383#define MC_CMD_GET_LINK_OUT_V2_FEC_LOCK_LBN 74384#define MC_CMD_GET_LINK_OUT_V2_FEC_LOCK_WIDTH 14385#define MC_CMD_GET_LINK_OUT_V2_AN_DONE_OFST 404386#define MC_CMD_GET_LINK_OUT_V2_AN_DONE_LBN 84387#define MC_CMD_GET_LINK_OUT_V2_AN_DONE_WIDTH 14388#define MC_CMD_GET_LINK_OUT_V2_PORT_SHUTDOWN_OFST 404389#define MC_CMD_GET_LINK_OUT_V2_PORT_SHUTDOWN_LBN 94390#define MC_CMD_GET_LINK_OUT_V2_PORT_SHUTDOWN_WIDTH 14391 4392 4393/***********************************/4394/* MC_CMD_SET_LINK4395 * Write the unified MAC/PHY link configuration. Locks required: None. Return4396 * code: 0, EINVAL, ETIME, EAGAIN4397 */4398#define MC_CMD_SET_LINK 0x2a4399#undef MC_CMD_0x2a_PRIVILEGE_CTG4400 4401#define MC_CMD_0x2a_PRIVILEGE_CTG SRIOV_CTG_LINK4402 4403/* MC_CMD_SET_LINK_IN msgrequest */4404#define MC_CMD_SET_LINK_IN_LEN 164405/* Near-side advertised capabilities. Refer to4406 * MC_CMD_GET_PHY_CFG_OUT/SUPPORTED_CAP for bit definitions.4407 */4408#define MC_CMD_SET_LINK_IN_CAP_OFST 04409#define MC_CMD_SET_LINK_IN_CAP_LEN 44410/* Flags */4411#define MC_CMD_SET_LINK_IN_FLAGS_OFST 44412#define MC_CMD_SET_LINK_IN_FLAGS_LEN 44413#define MC_CMD_SET_LINK_IN_LOWPOWER_OFST 44414#define MC_CMD_SET_LINK_IN_LOWPOWER_LBN 04415#define MC_CMD_SET_LINK_IN_LOWPOWER_WIDTH 14416#define MC_CMD_SET_LINK_IN_POWEROFF_OFST 44417#define MC_CMD_SET_LINK_IN_POWEROFF_LBN 14418#define MC_CMD_SET_LINK_IN_POWEROFF_WIDTH 14419#define MC_CMD_SET_LINK_IN_TXDIS_OFST 44420#define MC_CMD_SET_LINK_IN_TXDIS_LBN 24421#define MC_CMD_SET_LINK_IN_TXDIS_WIDTH 14422#define MC_CMD_SET_LINK_IN_LINKDOWN_OFST 44423#define MC_CMD_SET_LINK_IN_LINKDOWN_LBN 34424#define MC_CMD_SET_LINK_IN_LINKDOWN_WIDTH 14425/* Loopback mode. */4426#define MC_CMD_SET_LINK_IN_LOOPBACK_MODE_OFST 84427#define MC_CMD_SET_LINK_IN_LOOPBACK_MODE_LEN 44428/* Enum values, see field(s): */4429/* MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */4430/* A loopback speed of "0" is supported, and means (choose any available4431 * speed).4432 */4433#define MC_CMD_SET_LINK_IN_LOOPBACK_SPEED_OFST 124434#define MC_CMD_SET_LINK_IN_LOOPBACK_SPEED_LEN 44435 4436/* MC_CMD_SET_LINK_IN_V2 msgrequest: Updated SET_LINK to include sequence4437 * number to ensure this SET_LINK command corresponds to the latest4438 * MODULECHANGE event.4439 */4440#define MC_CMD_SET_LINK_IN_V2_LEN 174441/* Near-side advertised capabilities. Refer to4442 * MC_CMD_GET_PHY_CFG_OUT/SUPPORTED_CAP for bit definitions.4443 */4444#define MC_CMD_SET_LINK_IN_V2_CAP_OFST 04445#define MC_CMD_SET_LINK_IN_V2_CAP_LEN 44446/* Flags */4447#define MC_CMD_SET_LINK_IN_V2_FLAGS_OFST 44448#define MC_CMD_SET_LINK_IN_V2_FLAGS_LEN 44449#define MC_CMD_SET_LINK_IN_V2_LOWPOWER_OFST 44450#define MC_CMD_SET_LINK_IN_V2_LOWPOWER_LBN 04451#define MC_CMD_SET_LINK_IN_V2_LOWPOWER_WIDTH 14452#define MC_CMD_SET_LINK_IN_V2_POWEROFF_OFST 44453#define MC_CMD_SET_LINK_IN_V2_POWEROFF_LBN 14454#define MC_CMD_SET_LINK_IN_V2_POWEROFF_WIDTH 14455#define MC_CMD_SET_LINK_IN_V2_TXDIS_OFST 44456#define MC_CMD_SET_LINK_IN_V2_TXDIS_LBN 24457#define MC_CMD_SET_LINK_IN_V2_TXDIS_WIDTH 14458#define MC_CMD_SET_LINK_IN_V2_LINKDOWN_OFST 44459#define MC_CMD_SET_LINK_IN_V2_LINKDOWN_LBN 34460#define MC_CMD_SET_LINK_IN_V2_LINKDOWN_WIDTH 14461/* Loopback mode. */4462#define MC_CMD_SET_LINK_IN_V2_LOOPBACK_MODE_OFST 84463#define MC_CMD_SET_LINK_IN_V2_LOOPBACK_MODE_LEN 44464/* Enum values, see field(s): */4465/* MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */4466/* A loopback speed of "0" is supported, and means (choose any available4467 * speed).4468 */4469#define MC_CMD_SET_LINK_IN_V2_LOOPBACK_SPEED_OFST 124470#define MC_CMD_SET_LINK_IN_V2_LOOPBACK_SPEED_LEN 44471#define MC_CMD_SET_LINK_IN_V2_MODULE_SEQ_OFST 164472#define MC_CMD_SET_LINK_IN_V2_MODULE_SEQ_LEN 14473#define MC_CMD_SET_LINK_IN_V2_MODULE_SEQ_NUMBER_OFST 164474#define MC_CMD_SET_LINK_IN_V2_MODULE_SEQ_NUMBER_LBN 04475#define MC_CMD_SET_LINK_IN_V2_MODULE_SEQ_NUMBER_WIDTH 74476#define MC_CMD_SET_LINK_IN_V2_MODULE_SEQ_IGNORE_OFST 164477#define MC_CMD_SET_LINK_IN_V2_MODULE_SEQ_IGNORE_LBN 74478#define MC_CMD_SET_LINK_IN_V2_MODULE_SEQ_IGNORE_WIDTH 14479 4480/* MC_CMD_SET_LINK_OUT msgresponse */4481#define MC_CMD_SET_LINK_OUT_LEN 04482 4483 4484/***********************************/4485/* MC_CMD_SET_ID_LED4486 * Set identification LED state. Locks required: None. Return code: 0, EINVAL4487 */4488#define MC_CMD_SET_ID_LED 0x2b4489#undef MC_CMD_0x2b_PRIVILEGE_CTG4490 4491#define MC_CMD_0x2b_PRIVILEGE_CTG SRIOV_CTG_LINK4492 4493/* MC_CMD_SET_ID_LED_IN msgrequest */4494#define MC_CMD_SET_ID_LED_IN_LEN 44495/* Set LED state. */4496#define MC_CMD_SET_ID_LED_IN_STATE_OFST 04497#define MC_CMD_SET_ID_LED_IN_STATE_LEN 44498#define MC_CMD_LED_OFF 0x0 /* enum */4499#define MC_CMD_LED_ON 0x1 /* enum */4500#define MC_CMD_LED_DEFAULT 0x2 /* enum */4501 4502/* MC_CMD_SET_ID_LED_OUT msgresponse */4503#define MC_CMD_SET_ID_LED_OUT_LEN 04504 4505 4506/***********************************/4507/* MC_CMD_SET_MAC4508 * Set MAC configuration. Locks required: None. Return code: 0, EINVAL4509 */4510#define MC_CMD_SET_MAC 0x2c4511#undef MC_CMD_0x2c_PRIVILEGE_CTG4512 4513#define MC_CMD_0x2c_PRIVILEGE_CTG SRIOV_CTG_GENERAL4514 4515/* MC_CMD_SET_MAC_IN msgrequest */4516#define MC_CMD_SET_MAC_IN_LEN 284517/* The MTU is the MTU programmed directly into the XMAC/GMAC (inclusive of4518 * EtherII, VLAN, bug16011 padding).4519 */4520#define MC_CMD_SET_MAC_IN_MTU_OFST 04521#define MC_CMD_SET_MAC_IN_MTU_LEN 44522#define MC_CMD_SET_MAC_IN_DRAIN_OFST 44523#define MC_CMD_SET_MAC_IN_DRAIN_LEN 44524#define MC_CMD_SET_MAC_IN_ADDR_OFST 84525#define MC_CMD_SET_MAC_IN_ADDR_LEN 84526#define MC_CMD_SET_MAC_IN_ADDR_LO_OFST 84527#define MC_CMD_SET_MAC_IN_ADDR_HI_OFST 124528#define MC_CMD_SET_MAC_IN_REJECT_OFST 164529#define MC_CMD_SET_MAC_IN_REJECT_LEN 44530#define MC_CMD_SET_MAC_IN_REJECT_UNCST_OFST 164531#define MC_CMD_SET_MAC_IN_REJECT_UNCST_LBN 04532#define MC_CMD_SET_MAC_IN_REJECT_UNCST_WIDTH 14533#define MC_CMD_SET_MAC_IN_REJECT_BRDCST_OFST 164534#define MC_CMD_SET_MAC_IN_REJECT_BRDCST_LBN 14535#define MC_CMD_SET_MAC_IN_REJECT_BRDCST_WIDTH 14536#define MC_CMD_SET_MAC_IN_FCNTL_OFST 204537#define MC_CMD_SET_MAC_IN_FCNTL_LEN 44538/* enum: Flow control is off. */4539#define MC_CMD_FCNTL_OFF 0x04540/* enum: Respond to flow control. */4541#define MC_CMD_FCNTL_RESPOND 0x14542/* enum: Respond to and Issue flow control. */4543#define MC_CMD_FCNTL_BIDIR 0x24544/* enum: Auto neg flow control. */4545#define MC_CMD_FCNTL_AUTO 0x34546/* enum: Priority flow control (eftest builds only). */4547#define MC_CMD_FCNTL_QBB 0x44548/* enum: Issue flow control. */4549#define MC_CMD_FCNTL_GENERATE 0x54550#define MC_CMD_SET_MAC_IN_FLAGS_OFST 244551#define MC_CMD_SET_MAC_IN_FLAGS_LEN 44552#define MC_CMD_SET_MAC_IN_FLAG_INCLUDE_FCS_OFST 244553#define MC_CMD_SET_MAC_IN_FLAG_INCLUDE_FCS_LBN 04554#define MC_CMD_SET_MAC_IN_FLAG_INCLUDE_FCS_WIDTH 14555 4556/* MC_CMD_SET_MAC_EXT_IN msgrequest */4557#define MC_CMD_SET_MAC_EXT_IN_LEN 324558/* The MTU is the MTU programmed directly into the XMAC/GMAC (inclusive of4559 * EtherII, VLAN, bug16011 padding).4560 */4561#define MC_CMD_SET_MAC_EXT_IN_MTU_OFST 04562#define MC_CMD_SET_MAC_EXT_IN_MTU_LEN 44563#define MC_CMD_SET_MAC_EXT_IN_DRAIN_OFST 44564#define MC_CMD_SET_MAC_EXT_IN_DRAIN_LEN 44565#define MC_CMD_SET_MAC_EXT_IN_ADDR_OFST 84566#define MC_CMD_SET_MAC_EXT_IN_ADDR_LEN 84567#define MC_CMD_SET_MAC_EXT_IN_ADDR_LO_OFST 84568#define MC_CMD_SET_MAC_EXT_IN_ADDR_HI_OFST 124569#define MC_CMD_SET_MAC_EXT_IN_REJECT_OFST 164570#define MC_CMD_SET_MAC_EXT_IN_REJECT_LEN 44571#define MC_CMD_SET_MAC_EXT_IN_REJECT_UNCST_OFST 164572#define MC_CMD_SET_MAC_EXT_IN_REJECT_UNCST_LBN 04573#define MC_CMD_SET_MAC_EXT_IN_REJECT_UNCST_WIDTH 14574#define MC_CMD_SET_MAC_EXT_IN_REJECT_BRDCST_OFST 164575#define MC_CMD_SET_MAC_EXT_IN_REJECT_BRDCST_LBN 14576#define MC_CMD_SET_MAC_EXT_IN_REJECT_BRDCST_WIDTH 14577#define MC_CMD_SET_MAC_EXT_IN_FCNTL_OFST 204578#define MC_CMD_SET_MAC_EXT_IN_FCNTL_LEN 44579/* enum: Flow control is off. */4580/* MC_CMD_FCNTL_OFF 0x0 */4581/* enum: Respond to flow control. */4582/* MC_CMD_FCNTL_RESPOND 0x1 */4583/* enum: Respond to and Issue flow control. */4584/* MC_CMD_FCNTL_BIDIR 0x2 */4585/* enum: Auto neg flow control. */4586/* MC_CMD_FCNTL_AUTO 0x3 */4587/* enum: Priority flow control (eftest builds only). */4588/* MC_CMD_FCNTL_QBB 0x4 */4589/* enum: Issue flow control. */4590/* MC_CMD_FCNTL_GENERATE 0x5 */4591#define MC_CMD_SET_MAC_EXT_IN_FLAGS_OFST 244592#define MC_CMD_SET_MAC_EXT_IN_FLAGS_LEN 44593#define MC_CMD_SET_MAC_EXT_IN_FLAG_INCLUDE_FCS_OFST 244594#define MC_CMD_SET_MAC_EXT_IN_FLAG_INCLUDE_FCS_LBN 04595#define MC_CMD_SET_MAC_EXT_IN_FLAG_INCLUDE_FCS_WIDTH 14596/* Select which parameters to configure. A parameter will only be modified if4597 * the corresponding control flag is set. If SET_MAC_ENHANCED is not set in4598 * capabilities then this field is ignored (and all flags are assumed to be4599 * set).4600 */4601#define MC_CMD_SET_MAC_EXT_IN_CONTROL_OFST 284602#define MC_CMD_SET_MAC_EXT_IN_CONTROL_LEN 44603#define MC_CMD_SET_MAC_EXT_IN_CFG_MTU_OFST 284604#define MC_CMD_SET_MAC_EXT_IN_CFG_MTU_LBN 04605#define MC_CMD_SET_MAC_EXT_IN_CFG_MTU_WIDTH 14606#define MC_CMD_SET_MAC_EXT_IN_CFG_DRAIN_OFST 284607#define MC_CMD_SET_MAC_EXT_IN_CFG_DRAIN_LBN 14608#define MC_CMD_SET_MAC_EXT_IN_CFG_DRAIN_WIDTH 14609#define MC_CMD_SET_MAC_EXT_IN_CFG_REJECT_OFST 284610#define MC_CMD_SET_MAC_EXT_IN_CFG_REJECT_LBN 24611#define MC_CMD_SET_MAC_EXT_IN_CFG_REJECT_WIDTH 14612#define MC_CMD_SET_MAC_EXT_IN_CFG_FCNTL_OFST 284613#define MC_CMD_SET_MAC_EXT_IN_CFG_FCNTL_LBN 34614#define MC_CMD_SET_MAC_EXT_IN_CFG_FCNTL_WIDTH 14615#define MC_CMD_SET_MAC_EXT_IN_CFG_FCS_OFST 284616#define MC_CMD_SET_MAC_EXT_IN_CFG_FCS_LBN 44617#define MC_CMD_SET_MAC_EXT_IN_CFG_FCS_WIDTH 14618 4619/* MC_CMD_SET_MAC_OUT msgresponse */4620#define MC_CMD_SET_MAC_OUT_LEN 04621 4622/* MC_CMD_SET_MAC_V2_OUT msgresponse */4623#define MC_CMD_SET_MAC_V2_OUT_LEN 44624/* MTU as configured after processing the request. See comment at4625 * MC_CMD_SET_MAC_IN/MTU. To query MTU without doing any changes, set CONTROL4626 * to 0.4627 */4628#define MC_CMD_SET_MAC_V2_OUT_MTU_OFST 04629#define MC_CMD_SET_MAC_V2_OUT_MTU_LEN 44630 4631 4632/***********************************/4633/* MC_CMD_PHY_STATS4634 * Get generic PHY statistics. This call returns the statistics for a generic4635 * PHY in a sparse array (indexed by the enumerate). Each value is represented4636 * by a 32bit number. If the DMA_ADDR is 0, then no DMA is performed, and the4637 * statistics may be read from the message response. If DMA_ADDR != 0, then the4638 * statistics are dmad to that (page-aligned location). Locks required: None.4639 * Returns: 0, ETIME4640 */4641#define MC_CMD_PHY_STATS 0x2d4642#undef MC_CMD_0x2d_PRIVILEGE_CTG4643 4644#define MC_CMD_0x2d_PRIVILEGE_CTG SRIOV_CTG_LINK4645 4646/* MC_CMD_PHY_STATS_IN msgrequest */4647#define MC_CMD_PHY_STATS_IN_LEN 84648/* ??? */4649#define MC_CMD_PHY_STATS_IN_DMA_ADDR_OFST 04650#define MC_CMD_PHY_STATS_IN_DMA_ADDR_LEN 84651#define MC_CMD_PHY_STATS_IN_DMA_ADDR_LO_OFST 04652#define MC_CMD_PHY_STATS_IN_DMA_ADDR_HI_OFST 44653 4654/* MC_CMD_PHY_STATS_OUT_DMA msgresponse */4655#define MC_CMD_PHY_STATS_OUT_DMA_LEN 04656 4657/* MC_CMD_PHY_STATS_OUT_NO_DMA msgresponse */4658#define MC_CMD_PHY_STATS_OUT_NO_DMA_LEN (((MC_CMD_PHY_NSTATS*32))>>3)4659#define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_OFST 04660#define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_LEN 44661#define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_NUM MC_CMD_PHY_NSTATS4662/* enum: OUI. */4663#define MC_CMD_OUI 0x04664/* enum: PMA-PMD Link Up. */4665#define MC_CMD_PMA_PMD_LINK_UP 0x14666/* enum: PMA-PMD RX Fault. */4667#define MC_CMD_PMA_PMD_RX_FAULT 0x24668/* enum: PMA-PMD TX Fault. */4669#define MC_CMD_PMA_PMD_TX_FAULT 0x34670/* enum: PMA-PMD Signal */4671#define MC_CMD_PMA_PMD_SIGNAL 0x44672/* enum: PMA-PMD SNR A. */4673#define MC_CMD_PMA_PMD_SNR_A 0x54674/* enum: PMA-PMD SNR B. */4675#define MC_CMD_PMA_PMD_SNR_B 0x64676/* enum: PMA-PMD SNR C. */4677#define MC_CMD_PMA_PMD_SNR_C 0x74678/* enum: PMA-PMD SNR D. */4679#define MC_CMD_PMA_PMD_SNR_D 0x84680/* enum: PCS Link Up. */4681#define MC_CMD_PCS_LINK_UP 0x94682/* enum: PCS RX Fault. */4683#define MC_CMD_PCS_RX_FAULT 0xa4684/* enum: PCS TX Fault. */4685#define MC_CMD_PCS_TX_FAULT 0xb4686/* enum: PCS BER. */4687#define MC_CMD_PCS_BER 0xc4688/* enum: PCS Block Errors. */4689#define MC_CMD_PCS_BLOCK_ERRORS 0xd4690/* enum: PhyXS Link Up. */4691#define MC_CMD_PHYXS_LINK_UP 0xe4692/* enum: PhyXS RX Fault. */4693#define MC_CMD_PHYXS_RX_FAULT 0xf4694/* enum: PhyXS TX Fault. */4695#define MC_CMD_PHYXS_TX_FAULT 0x104696/* enum: PhyXS Align. */4697#define MC_CMD_PHYXS_ALIGN 0x114698/* enum: PhyXS Sync. */4699#define MC_CMD_PHYXS_SYNC 0x124700/* enum: AN link-up. */4701#define MC_CMD_AN_LINK_UP 0x134702/* enum: AN Complete. */4703#define MC_CMD_AN_COMPLETE 0x144704/* enum: AN 10GBaseT Status. */4705#define MC_CMD_AN_10GBT_STATUS 0x154706/* enum: Clause 22 Link-Up. */4707#define MC_CMD_CL22_LINK_UP 0x164708/* enum: (Last entry) */4709#define MC_CMD_PHY_NSTATS 0x174710 4711 4712/***********************************/4713/* MC_CMD_MAC_STATS4714 * Get generic MAC statistics. This call returns unified statistics maintained4715 * by the MC as it switches between the GMAC and XMAC. The MC will write out4716 * all supported stats. The driver should zero initialise the buffer to4717 * guarantee consistent results. If the DMA_ADDR is 0, then no DMA is4718 * performed, and the statistics may be read from the message response. If4719 * DMA_ADDR != 0, then the statistics are dmad to that (page-aligned location).4720 * Locks required: None. The PERIODIC_CLEAR option is not used and now has no4721 * effect. Returns: 0, ETIME4722 */4723#define MC_CMD_MAC_STATS 0x2e4724#undef MC_CMD_0x2e_PRIVILEGE_CTG4725 4726#define MC_CMD_0x2e_PRIVILEGE_CTG SRIOV_CTG_GENERAL4727 4728/* MC_CMD_MAC_STATS_IN msgrequest */4729#define MC_CMD_MAC_STATS_IN_LEN 204730/* ??? */4731#define MC_CMD_MAC_STATS_IN_DMA_ADDR_OFST 04732#define MC_CMD_MAC_STATS_IN_DMA_ADDR_LEN 84733#define MC_CMD_MAC_STATS_IN_DMA_ADDR_LO_OFST 04734#define MC_CMD_MAC_STATS_IN_DMA_ADDR_HI_OFST 44735#define MC_CMD_MAC_STATS_IN_CMD_OFST 84736#define MC_CMD_MAC_STATS_IN_CMD_LEN 44737#define MC_CMD_MAC_STATS_IN_DMA_OFST 84738#define MC_CMD_MAC_STATS_IN_DMA_LBN 04739#define MC_CMD_MAC_STATS_IN_DMA_WIDTH 14740#define MC_CMD_MAC_STATS_IN_CLEAR_OFST 84741#define MC_CMD_MAC_STATS_IN_CLEAR_LBN 14742#define MC_CMD_MAC_STATS_IN_CLEAR_WIDTH 14743#define MC_CMD_MAC_STATS_IN_PERIODIC_CHANGE_OFST 84744#define MC_CMD_MAC_STATS_IN_PERIODIC_CHANGE_LBN 24745#define MC_CMD_MAC_STATS_IN_PERIODIC_CHANGE_WIDTH 14746#define MC_CMD_MAC_STATS_IN_PERIODIC_ENABLE_OFST 84747#define MC_CMD_MAC_STATS_IN_PERIODIC_ENABLE_LBN 34748#define MC_CMD_MAC_STATS_IN_PERIODIC_ENABLE_WIDTH 14749#define MC_CMD_MAC_STATS_IN_PERIODIC_CLEAR_OFST 84750#define MC_CMD_MAC_STATS_IN_PERIODIC_CLEAR_LBN 44751#define MC_CMD_MAC_STATS_IN_PERIODIC_CLEAR_WIDTH 14752#define MC_CMD_MAC_STATS_IN_PERIODIC_NOEVENT_OFST 84753#define MC_CMD_MAC_STATS_IN_PERIODIC_NOEVENT_LBN 54754#define MC_CMD_MAC_STATS_IN_PERIODIC_NOEVENT_WIDTH 14755#define MC_CMD_MAC_STATS_IN_PERIOD_MS_OFST 84756#define MC_CMD_MAC_STATS_IN_PERIOD_MS_LBN 164757#define MC_CMD_MAC_STATS_IN_PERIOD_MS_WIDTH 164758/* DMA length. Should be set to MAC_STATS_NUM_STATS * sizeof(uint64_t), as4759 * returned by MC_CMD_GET_CAPABILITIES_V4_OUT. For legacy firmware not4760 * supporting MC_CMD_GET_CAPABILITIES_V4_OUT, DMA_LEN should be set to4761 * MC_CMD_MAC_NSTATS * sizeof(uint64_t)4762 */4763#define MC_CMD_MAC_STATS_IN_DMA_LEN_OFST 124764#define MC_CMD_MAC_STATS_IN_DMA_LEN_LEN 44765/* port id so vadapter stats can be provided */4766#define MC_CMD_MAC_STATS_IN_PORT_ID_OFST 164767#define MC_CMD_MAC_STATS_IN_PORT_ID_LEN 44768 4769/* MC_CMD_MAC_STATS_OUT_DMA msgresponse */4770#define MC_CMD_MAC_STATS_OUT_DMA_LEN 04771 4772/* MC_CMD_MAC_STATS_OUT_NO_DMA msgresponse */4773#define MC_CMD_MAC_STATS_OUT_NO_DMA_LEN (((MC_CMD_MAC_NSTATS*64))>>3)4774#define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_OFST 04775#define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LEN 84776#define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LO_OFST 04777#define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_HI_OFST 44778#define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS4779#define MC_CMD_MAC_GENERATION_START 0x0 /* enum */4780#define MC_CMD_MAC_DMABUF_START 0x1 /* enum */4781#define MC_CMD_MAC_TX_PKTS 0x1 /* enum */4782#define MC_CMD_MAC_TX_PAUSE_PKTS 0x2 /* enum */4783#define MC_CMD_MAC_TX_CONTROL_PKTS 0x3 /* enum */4784#define MC_CMD_MAC_TX_UNICAST_PKTS 0x4 /* enum */4785#define MC_CMD_MAC_TX_MULTICAST_PKTS 0x5 /* enum */4786#define MC_CMD_MAC_TX_BROADCAST_PKTS 0x6 /* enum */4787#define MC_CMD_MAC_TX_BYTES 0x7 /* enum */4788#define MC_CMD_MAC_TX_BAD_BYTES 0x8 /* enum */4789#define MC_CMD_MAC_TX_LT64_PKTS 0x9 /* enum */4790#define MC_CMD_MAC_TX_64_PKTS 0xa /* enum */4791#define MC_CMD_MAC_TX_65_TO_127_PKTS 0xb /* enum */4792#define MC_CMD_MAC_TX_128_TO_255_PKTS 0xc /* enum */4793#define MC_CMD_MAC_TX_256_TO_511_PKTS 0xd /* enum */4794#define MC_CMD_MAC_TX_512_TO_1023_PKTS 0xe /* enum */4795#define MC_CMD_MAC_TX_1024_TO_15XX_PKTS 0xf /* enum */4796#define MC_CMD_MAC_TX_15XX_TO_JUMBO_PKTS 0x10 /* enum */4797#define MC_CMD_MAC_TX_GTJUMBO_PKTS 0x11 /* enum */4798#define MC_CMD_MAC_TX_BAD_FCS_PKTS 0x12 /* enum */4799#define MC_CMD_MAC_TX_SINGLE_COLLISION_PKTS 0x13 /* enum */4800#define MC_CMD_MAC_TX_MULTIPLE_COLLISION_PKTS 0x14 /* enum */4801#define MC_CMD_MAC_TX_EXCESSIVE_COLLISION_PKTS 0x15 /* enum */4802#define MC_CMD_MAC_TX_LATE_COLLISION_PKTS 0x16 /* enum */4803#define MC_CMD_MAC_TX_DEFERRED_PKTS 0x17 /* enum */4804#define MC_CMD_MAC_TX_EXCESSIVE_DEFERRED_PKTS 0x18 /* enum */4805#define MC_CMD_MAC_TX_NON_TCPUDP_PKTS 0x19 /* enum */4806#define MC_CMD_MAC_TX_MAC_SRC_ERR_PKTS 0x1a /* enum */4807#define MC_CMD_MAC_TX_IP_SRC_ERR_PKTS 0x1b /* enum */4808#define MC_CMD_MAC_RX_PKTS 0x1c /* enum */4809#define MC_CMD_MAC_RX_PAUSE_PKTS 0x1d /* enum */4810#define MC_CMD_MAC_RX_GOOD_PKTS 0x1e /* enum */4811#define MC_CMD_MAC_RX_CONTROL_PKTS 0x1f /* enum */4812#define MC_CMD_MAC_RX_UNICAST_PKTS 0x20 /* enum */4813#define MC_CMD_MAC_RX_MULTICAST_PKTS 0x21 /* enum */4814#define MC_CMD_MAC_RX_BROADCAST_PKTS 0x22 /* enum */4815#define MC_CMD_MAC_RX_BYTES 0x23 /* enum */4816#define MC_CMD_MAC_RX_BAD_BYTES 0x24 /* enum */4817#define MC_CMD_MAC_RX_64_PKTS 0x25 /* enum */4818#define MC_CMD_MAC_RX_65_TO_127_PKTS 0x26 /* enum */4819#define MC_CMD_MAC_RX_128_TO_255_PKTS 0x27 /* enum */4820#define MC_CMD_MAC_RX_256_TO_511_PKTS 0x28 /* enum */4821#define MC_CMD_MAC_RX_512_TO_1023_PKTS 0x29 /* enum */4822#define MC_CMD_MAC_RX_1024_TO_15XX_PKTS 0x2a /* enum */4823#define MC_CMD_MAC_RX_15XX_TO_JUMBO_PKTS 0x2b /* enum */4824#define MC_CMD_MAC_RX_GTJUMBO_PKTS 0x2c /* enum */4825#define MC_CMD_MAC_RX_UNDERSIZE_PKTS 0x2d /* enum */4826#define MC_CMD_MAC_RX_BAD_FCS_PKTS 0x2e /* enum */4827#define MC_CMD_MAC_RX_OVERFLOW_PKTS 0x2f /* enum */4828#define MC_CMD_MAC_RX_FALSE_CARRIER_PKTS 0x30 /* enum */4829#define MC_CMD_MAC_RX_SYMBOL_ERROR_PKTS 0x31 /* enum */4830#define MC_CMD_MAC_RX_ALIGN_ERROR_PKTS 0x32 /* enum */4831#define MC_CMD_MAC_RX_LENGTH_ERROR_PKTS 0x33 /* enum */4832#define MC_CMD_MAC_RX_INTERNAL_ERROR_PKTS 0x34 /* enum */4833#define MC_CMD_MAC_RX_JABBER_PKTS 0x35 /* enum */4834#define MC_CMD_MAC_RX_NODESC_DROPS 0x36 /* enum */4835#define MC_CMD_MAC_RX_LANES01_CHAR_ERR 0x37 /* enum */4836#define MC_CMD_MAC_RX_LANES23_CHAR_ERR 0x38 /* enum */4837#define MC_CMD_MAC_RX_LANES01_DISP_ERR 0x39 /* enum */4838#define MC_CMD_MAC_RX_LANES23_DISP_ERR 0x3a /* enum */4839#define MC_CMD_MAC_RX_MATCH_FAULT 0x3b /* enum */4840/* enum: PM trunc_bb_overflow counter. Valid for EF10 with PM_AND_RXDP_COUNTERS4841 * capability only.4842 */4843#define MC_CMD_MAC_PM_TRUNC_BB_OVERFLOW 0x3c4844/* enum: PM discard_bb_overflow counter. Valid for EF10 with4845 * PM_AND_RXDP_COUNTERS capability only.4846 */4847#define MC_CMD_MAC_PM_DISCARD_BB_OVERFLOW 0x3d4848/* enum: PM trunc_vfifo_full counter. Valid for EF10 with PM_AND_RXDP_COUNTERS4849 * capability only.4850 */4851#define MC_CMD_MAC_PM_TRUNC_VFIFO_FULL 0x3e4852/* enum: PM discard_vfifo_full counter. Valid for EF10 with4853 * PM_AND_RXDP_COUNTERS capability only.4854 */4855#define MC_CMD_MAC_PM_DISCARD_VFIFO_FULL 0x3f4856/* enum: PM trunc_qbb counter. Valid for EF10 with PM_AND_RXDP_COUNTERS4857 * capability only.4858 */4859#define MC_CMD_MAC_PM_TRUNC_QBB 0x404860/* enum: PM discard_qbb counter. Valid for EF10 with PM_AND_RXDP_COUNTERS4861 * capability only.4862 */4863#define MC_CMD_MAC_PM_DISCARD_QBB 0x414864/* enum: PM discard_mapping counter. Valid for EF10 with PM_AND_RXDP_COUNTERS4865 * capability only.4866 */4867#define MC_CMD_MAC_PM_DISCARD_MAPPING 0x424868/* enum: RXDP counter: Number of packets dropped due to the queue being4869 * disabled. Valid for EF10 with PM_AND_RXDP_COUNTERS capability only.4870 */4871#define MC_CMD_MAC_RXDP_Q_DISABLED_PKTS 0x434872/* enum: RXDP counter: Number of packets dropped by the DICPU. Valid for EF104873 * with PM_AND_RXDP_COUNTERS capability only.4874 */4875#define MC_CMD_MAC_RXDP_DI_DROPPED_PKTS 0x454876/* enum: RXDP counter: Number of non-host packets. Valid for EF10 with4877 * PM_AND_RXDP_COUNTERS capability only.4878 */4879#define MC_CMD_MAC_RXDP_STREAMING_PKTS 0x464880/* enum: RXDP counter: Number of times an hlb descriptor fetch was performed.4881 * Valid for EF10 with PM_AND_RXDP_COUNTERS capability only.4882 */4883#define MC_CMD_MAC_RXDP_HLB_FETCH_CONDITIONS 0x474884/* enum: RXDP counter: Number of times the DPCPU waited for an existing4885 * descriptor fetch. Valid for EF10 with PM_AND_RXDP_COUNTERS capability only.4886 */4887#define MC_CMD_MAC_RXDP_HLB_WAIT_CONDITIONS 0x484888#define MC_CMD_MAC_VADAPTER_RX_DMABUF_START 0x4c /* enum */4889#define MC_CMD_MAC_VADAPTER_RX_UNICAST_PACKETS 0x4c /* enum */4890#define MC_CMD_MAC_VADAPTER_RX_UNICAST_BYTES 0x4d /* enum */4891#define MC_CMD_MAC_VADAPTER_RX_MULTICAST_PACKETS 0x4e /* enum */4892#define MC_CMD_MAC_VADAPTER_RX_MULTICAST_BYTES 0x4f /* enum */4893#define MC_CMD_MAC_VADAPTER_RX_BROADCAST_PACKETS 0x50 /* enum */4894#define MC_CMD_MAC_VADAPTER_RX_BROADCAST_BYTES 0x51 /* enum */4895#define MC_CMD_MAC_VADAPTER_RX_BAD_PACKETS 0x52 /* enum */4896#define MC_CMD_MAC_VADAPTER_RX_BAD_BYTES 0x53 /* enum */4897#define MC_CMD_MAC_VADAPTER_RX_OVERFLOW 0x54 /* enum */4898#define MC_CMD_MAC_VADAPTER_TX_DMABUF_START 0x57 /* enum */4899#define MC_CMD_MAC_VADAPTER_TX_UNICAST_PACKETS 0x57 /* enum */4900#define MC_CMD_MAC_VADAPTER_TX_UNICAST_BYTES 0x58 /* enum */4901#define MC_CMD_MAC_VADAPTER_TX_MULTICAST_PACKETS 0x59 /* enum */4902#define MC_CMD_MAC_VADAPTER_TX_MULTICAST_BYTES 0x5a /* enum */4903#define MC_CMD_MAC_VADAPTER_TX_BROADCAST_PACKETS 0x5b /* enum */4904#define MC_CMD_MAC_VADAPTER_TX_BROADCAST_BYTES 0x5c /* enum */4905#define MC_CMD_MAC_VADAPTER_TX_BAD_PACKETS 0x5d /* enum */4906#define MC_CMD_MAC_VADAPTER_TX_BAD_BYTES 0x5e /* enum */4907#define MC_CMD_MAC_VADAPTER_TX_OVERFLOW 0x5f /* enum */4908/* enum: Start of GMAC stats buffer space, for Siena only. */4909#define MC_CMD_GMAC_DMABUF_START 0x404910/* enum: End of GMAC stats buffer space, for Siena only. */4911#define MC_CMD_GMAC_DMABUF_END 0x5f4912/* enum: GENERATION_END value, used together with GENERATION_START to verify4913 * consistency of DMAd data. For legacy firmware / drivers without extended4914 * stats (more precisely, when DMA_LEN == MC_CMD_MAC_NSTATS *4915 * sizeof(uint64_t)), this entry holds the GENERATION_END value. Otherwise,4916 * this value is invalid/ reserved and GENERATION_END is written as the last4917 * 64-bit word of the DMA buffer (at DMA_LEN - sizeof(uint64_t)). Note that4918 * this is consistent with the legacy behaviour, in the sense that entry 96 is4919 * the last 64-bit word in the buffer when DMA_LEN == MC_CMD_MAC_NSTATS *4920 * sizeof(uint64_t). See SF-109306-TC, Section 9.2 for details.4921 */4922#define MC_CMD_MAC_GENERATION_END 0x604923#define MC_CMD_MAC_NSTATS 0x61 /* enum */4924 4925/* MC_CMD_MAC_STATS_V2_OUT_DMA msgresponse */4926#define MC_CMD_MAC_STATS_V2_OUT_DMA_LEN 04927 4928/* MC_CMD_MAC_STATS_V2_OUT_NO_DMA msgresponse */4929#define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_LEN (((MC_CMD_MAC_NSTATS_V2*64))>>3)4930#define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_OFST 04931#define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_LEN 84932#define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_LO_OFST 04933#define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_HI_OFST 44934#define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS_V24935/* enum: Start of FEC stats buffer space, Medford2 and up */4936#define MC_CMD_MAC_FEC_DMABUF_START 0x614937/* enum: Number of uncorrected FEC codewords on link (RS-FEC only for Medford2)4938 */4939#define MC_CMD_MAC_FEC_UNCORRECTED_ERRORS 0x614940/* enum: Number of corrected FEC codewords on link (RS-FEC only for Medford2)4941 */4942#define MC_CMD_MAC_FEC_CORRECTED_ERRORS 0x624943/* enum: Number of corrected 10-bit symbol errors, lane 0 (RS-FEC only) */4944#define MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE0 0x634945/* enum: Number of corrected 10-bit symbol errors, lane 1 (RS-FEC only) */4946#define MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE1 0x644947/* enum: Number of corrected 10-bit symbol errors, lane 2 (RS-FEC only) */4948#define MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE2 0x654949/* enum: Number of corrected 10-bit symbol errors, lane 3 (RS-FEC only) */4950#define MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE3 0x664951/* enum: This includes the space at offset 103 which is the final4952 * GENERATION_END in a MAC_STATS_V2 response and otherwise unused.4953 */4954#define MC_CMD_MAC_NSTATS_V2 0x684955/* Other enum values, see field(s): */4956/* MC_CMD_MAC_STATS_OUT_NO_DMA/STATISTICS */4957 4958/* MC_CMD_MAC_STATS_V3_OUT_DMA msgresponse */4959#define MC_CMD_MAC_STATS_V3_OUT_DMA_LEN 04960 4961/* MC_CMD_MAC_STATS_V3_OUT_NO_DMA msgresponse */4962#define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_LEN (((MC_CMD_MAC_NSTATS_V3*64))>>3)4963#define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_OFST 04964#define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_LEN 84965#define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_LO_OFST 04966#define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_HI_OFST 44967#define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS_V34968/* enum: Start of CTPIO stats buffer space, Medford2 and up */4969#define MC_CMD_MAC_CTPIO_DMABUF_START 0x684970/* enum: Number of CTPIO fallbacks because a DMA packet was in progress on the4971 * target VI4972 */4973#define MC_CMD_MAC_CTPIO_VI_BUSY_FALLBACK 0x684974/* enum: Number of times a CTPIO send wrote beyond frame end (informational4975 * only)4976 */4977#define MC_CMD_MAC_CTPIO_LONG_WRITE_SUCCESS 0x694978/* enum: Number of CTPIO failures because the TX doorbell was written before4979 * the end of the frame data4980 */4981#define MC_CMD_MAC_CTPIO_MISSING_DBELL_FAIL 0x6a4982/* enum: Number of CTPIO failures because the internal FIFO overflowed */4983#define MC_CMD_MAC_CTPIO_OVERFLOW_FAIL 0x6b4984/* enum: Number of CTPIO failures because the host did not deliver data fast4985 * enough to avoid MAC underflow4986 */4987#define MC_CMD_MAC_CTPIO_UNDERFLOW_FAIL 0x6c4988/* enum: Number of CTPIO failures because the host did not deliver all the4989 * frame data within the timeout4990 */4991#define MC_CMD_MAC_CTPIO_TIMEOUT_FAIL 0x6d4992/* enum: Number of CTPIO failures because the frame data arrived out of order4993 * or with gaps4994 */4995#define MC_CMD_MAC_CTPIO_NONCONTIG_WR_FAIL 0x6e4996/* enum: Number of CTPIO failures because the host started a new frame before4997 * completing the previous one4998 */4999#define MC_CMD_MAC_CTPIO_FRM_CLOBBER_FAIL 0x6f5000/* enum: Number of CTPIO failures because a write was not a multiple of 32 bits5001 * or not 32-bit aligned5002 */5003#define MC_CMD_MAC_CTPIO_INVALID_WR_FAIL 0x705004/* enum: Number of CTPIO fallbacks because another VI on the same port was5005 * sending a CTPIO frame5006 */5007#define MC_CMD_MAC_CTPIO_VI_CLOBBER_FALLBACK 0x715008/* enum: Number of CTPIO fallbacks because target VI did not have CTPIO enabled5009 */5010#define MC_CMD_MAC_CTPIO_UNQUALIFIED_FALLBACK 0x725011/* enum: Number of CTPIO fallbacks because length in header was less than 295012 * bytes5013 */5014#define MC_CMD_MAC_CTPIO_RUNT_FALLBACK 0x735015/* enum: Total number of successful CTPIO sends on this port */5016#define MC_CMD_MAC_CTPIO_SUCCESS 0x745017/* enum: Total number of CTPIO fallbacks on this port */5018#define MC_CMD_MAC_CTPIO_FALLBACK 0x755019/* enum: Total number of CTPIO poisoned frames on this port, whether erased or5020 * not5021 */5022#define MC_CMD_MAC_CTPIO_POISON 0x765023/* enum: Total number of CTPIO erased frames on this port */5024#define MC_CMD_MAC_CTPIO_ERASE 0x775025/* enum: This includes the space at offset 120 which is the final5026 * GENERATION_END in a MAC_STATS_V3 response and otherwise unused.5027 */5028#define MC_CMD_MAC_NSTATS_V3 0x795029/* Other enum values, see field(s): */5030/* MC_CMD_MAC_STATS_V2_OUT_NO_DMA/STATISTICS */5031 5032/* MC_CMD_MAC_STATS_V4_OUT_DMA msgresponse */5033#define MC_CMD_MAC_STATS_V4_OUT_DMA_LEN 05034 5035/* MC_CMD_MAC_STATS_V4_OUT_NO_DMA msgresponse */5036#define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_LEN (((MC_CMD_MAC_NSTATS_V4*64))>>3)5037#define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_OFST 05038#define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_LEN 85039#define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_LO_OFST 05040#define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_HI_OFST 45041#define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS_V45042/* enum: Start of V4 stats buffer space */5043#define MC_CMD_MAC_V4_DMABUF_START 0x795044/* enum: RXDP counter: Number of packets truncated because scattering was5045 * disabled.5046 */5047#define MC_CMD_MAC_RXDP_SCATTER_DISABLED_TRUNC 0x795048/* enum: RXDP counter: Number of times the RXDP head of line blocked waiting5049 * for descriptors. Will be zero unless RXDP_HLB_IDLE capability is set.5050 */5051#define MC_CMD_MAC_RXDP_HLB_IDLE 0x7a5052/* enum: RXDP counter: Number of times the RXDP timed out while head of line5053 * blocking. Will be zero unless RXDP_HLB_IDLE capability is set.5054 */5055#define MC_CMD_MAC_RXDP_HLB_TIMEOUT 0x7b5056/* enum: This includes the space at offset 124 which is the final5057 * GENERATION_END in a MAC_STATS_V4 response and otherwise unused.5058 */5059#define MC_CMD_MAC_NSTATS_V4 0x7d5060/* Other enum values, see field(s): */5061/* MC_CMD_MAC_STATS_V3_OUT_NO_DMA/STATISTICS */5062 5063 5064/***********************************/5065/* MC_CMD_SRIOV5066 * to be documented5067 */5068#define MC_CMD_SRIOV 0x305069 5070/* MC_CMD_SRIOV_IN msgrequest */5071#define MC_CMD_SRIOV_IN_LEN 125072#define MC_CMD_SRIOV_IN_ENABLE_OFST 05073#define MC_CMD_SRIOV_IN_ENABLE_LEN 45074#define MC_CMD_SRIOV_IN_VI_BASE_OFST 45075#define MC_CMD_SRIOV_IN_VI_BASE_LEN 45076#define MC_CMD_SRIOV_IN_VF_COUNT_OFST 85077#define MC_CMD_SRIOV_IN_VF_COUNT_LEN 45078 5079/* MC_CMD_SRIOV_OUT msgresponse */5080#define MC_CMD_SRIOV_OUT_LEN 85081#define MC_CMD_SRIOV_OUT_VI_SCALE_OFST 05082#define MC_CMD_SRIOV_OUT_VI_SCALE_LEN 45083#define MC_CMD_SRIOV_OUT_VF_TOTAL_OFST 45084#define MC_CMD_SRIOV_OUT_VF_TOTAL_LEN 45085 5086/* MC_CMD_MEMCPY_RECORD_TYPEDEF structuredef */5087#define MC_CMD_MEMCPY_RECORD_TYPEDEF_LEN 325088/* this is only used for the first record */5089#define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_OFST 05090#define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_LEN 45091#define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_LBN 05092#define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_WIDTH 325093#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_OFST 45094#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_LEN 45095#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_LBN 325096#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_WIDTH 325097#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_OFST 85098#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LEN 85099#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LO_OFST 85100#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_HI_OFST 125101#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LBN 645102#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_WIDTH 645103#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_OFST 165104#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_LEN 45105#define MC_CMD_MEMCPY_RECORD_TYPEDEF_RID_INLINE 0x100 /* enum */5106#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_LBN 1285107#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_WIDTH 325108#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_OFST 205109#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LEN 85110#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LO_OFST 205111#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_HI_OFST 245112#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LBN 1605113#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_WIDTH 645114#define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_OFST 285115#define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_LEN 45116#define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_LBN 2245117#define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_WIDTH 325118 5119 5120/***********************************/5121/* MC_CMD_MEMCPY5122 * DMA write data into (Rid,Addr), either by dma reading (Rid,Addr), or by data5123 * embedded directly in the command.5124 *5125 * A common pattern is for a client to use generation counts to signal a dma5126 * update of a datastructure. To facilitate this, this MCDI operation can5127 * contain multiple requests which are executed in strict order. Requests take5128 * the form of duplicating the entire MCDI request continuously (including the5129 * requests record, which is ignored in all but the first structure)5130 *5131 * The source data can either come from a DMA from the host, or it can be5132 * embedded within the request directly, thereby eliminating a DMA read. To5133 * indicate this, the client sets FROM_RID=%RID_INLINE, ADDR_HI=0, and5134 * ADDR_LO=offset, and inserts the data at %offset from the start of the5135 * payload. It's the callers responsibility to ensure that the embedded data5136 * doesn't overlap the records.5137 *5138 * Returns: 0, EINVAL (invalid RID)5139 */5140#define MC_CMD_MEMCPY 0x315141 5142/* MC_CMD_MEMCPY_IN msgrequest */5143#define MC_CMD_MEMCPY_IN_LENMIN 325144#define MC_CMD_MEMCPY_IN_LENMAX 2245145#define MC_CMD_MEMCPY_IN_LENMAX_MCDI2 9925146#define MC_CMD_MEMCPY_IN_LEN(num) (0+32*(num))5147#define MC_CMD_MEMCPY_IN_RECORD_NUM(len) (((len)-0)/32)5148/* see MC_CMD_MEMCPY_RECORD_TYPEDEF */5149#define MC_CMD_MEMCPY_IN_RECORD_OFST 05150#define MC_CMD_MEMCPY_IN_RECORD_LEN 325151#define MC_CMD_MEMCPY_IN_RECORD_MINNUM 15152#define MC_CMD_MEMCPY_IN_RECORD_MAXNUM 75153#define MC_CMD_MEMCPY_IN_RECORD_MAXNUM_MCDI2 315154 5155/* MC_CMD_MEMCPY_OUT msgresponse */5156#define MC_CMD_MEMCPY_OUT_LEN 05157 5158 5159/***********************************/5160/* MC_CMD_WOL_FILTER_SET5161 * Set a WoL filter.5162 */5163#define MC_CMD_WOL_FILTER_SET 0x325164#undef MC_CMD_0x32_PRIVILEGE_CTG5165 5166#define MC_CMD_0x32_PRIVILEGE_CTG SRIOV_CTG_LINK5167 5168/* MC_CMD_WOL_FILTER_SET_IN msgrequest */5169#define MC_CMD_WOL_FILTER_SET_IN_LEN 1925170#define MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 05171#define MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 45172#define MC_CMD_FILTER_MODE_SIMPLE 0x0 /* enum */5173#define MC_CMD_FILTER_MODE_STRUCTURED 0xffffffff /* enum */5174/* A type value of 1 is unused. */5175#define MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 45176#define MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 45177/* enum: Magic */5178#define MC_CMD_WOL_TYPE_MAGIC 0x05179/* enum: MS Windows Magic */5180#define MC_CMD_WOL_TYPE_WIN_MAGIC 0x25181/* enum: IPv4 Syn */5182#define MC_CMD_WOL_TYPE_IPV4_SYN 0x35183/* enum: IPv6 Syn */5184#define MC_CMD_WOL_TYPE_IPV6_SYN 0x45185/* enum: Bitmap */5186#define MC_CMD_WOL_TYPE_BITMAP 0x55187/* enum: Link */5188#define MC_CMD_WOL_TYPE_LINK 0x65189/* enum: (Above this for future use) */5190#define MC_CMD_WOL_TYPE_MAX 0x75191#define MC_CMD_WOL_FILTER_SET_IN_DATA_OFST 85192#define MC_CMD_WOL_FILTER_SET_IN_DATA_LEN 45193#define MC_CMD_WOL_FILTER_SET_IN_DATA_NUM 465194 5195/* MC_CMD_WOL_FILTER_SET_IN_MAGIC msgrequest */5196#define MC_CMD_WOL_FILTER_SET_IN_MAGIC_LEN 165197/* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */5198/* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4 */5199/* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */5200/* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4 */5201#define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_OFST 85202#define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LEN 85203#define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LO_OFST 85204#define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_HI_OFST 125205 5206/* MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN msgrequest */5207#define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_LEN 205208/* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */5209/* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4 */5210/* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */5211/* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4 */5212#define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_IP_OFST 85213#define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_IP_LEN 45214#define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_IP_OFST 125215#define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_IP_LEN 45216#define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_PORT_OFST 165217#define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_PORT_LEN 25218#define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_PORT_OFST 185219#define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_PORT_LEN 25220 5221/* MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN msgrequest */5222#define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_LEN 445223/* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */5224/* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4 */5225/* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */5226/* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4 */5227#define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_IP_OFST 85228#define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_IP_LEN 165229#define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_IP_OFST 245230#define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_IP_LEN 165231#define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_PORT_OFST 405232#define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_PORT_LEN 25233#define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_PORT_OFST 425234#define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_PORT_LEN 25235 5236/* MC_CMD_WOL_FILTER_SET_IN_BITMAP msgrequest */5237#define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN 1875238/* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */5239/* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4 */5240/* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */5241/* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4 */5242#define MC_CMD_WOL_FILTER_SET_IN_BITMAP_MASK_OFST 85243#define MC_CMD_WOL_FILTER_SET_IN_BITMAP_MASK_LEN 485244#define MC_CMD_WOL_FILTER_SET_IN_BITMAP_BITMAP_OFST 565245#define MC_CMD_WOL_FILTER_SET_IN_BITMAP_BITMAP_LEN 1285246#define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN_OFST 1845247#define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN_LEN 15248#define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER3_OFST 1855249#define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER3_LEN 15250#define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER4_OFST 1865251#define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER4_LEN 15252 5253/* MC_CMD_WOL_FILTER_SET_IN_LINK msgrequest */5254#define MC_CMD_WOL_FILTER_SET_IN_LINK_LEN 125255/* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */5256/* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4 */5257/* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */5258/* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4 */5259#define MC_CMD_WOL_FILTER_SET_IN_LINK_MASK_OFST 85260#define MC_CMD_WOL_FILTER_SET_IN_LINK_MASK_LEN 45261#define MC_CMD_WOL_FILTER_SET_IN_LINK_UP_OFST 85262#define MC_CMD_WOL_FILTER_SET_IN_LINK_UP_LBN 05263#define MC_CMD_WOL_FILTER_SET_IN_LINK_UP_WIDTH 15264#define MC_CMD_WOL_FILTER_SET_IN_LINK_DOWN_OFST 85265#define MC_CMD_WOL_FILTER_SET_IN_LINK_DOWN_LBN 15266#define MC_CMD_WOL_FILTER_SET_IN_LINK_DOWN_WIDTH 15267 5268/* MC_CMD_WOL_FILTER_SET_OUT msgresponse */5269#define MC_CMD_WOL_FILTER_SET_OUT_LEN 45270#define MC_CMD_WOL_FILTER_SET_OUT_FILTER_ID_OFST 05271#define MC_CMD_WOL_FILTER_SET_OUT_FILTER_ID_LEN 45272 5273 5274/***********************************/5275/* MC_CMD_WOL_FILTER_REMOVE5276 * Remove a WoL filter. Locks required: None. Returns: 0, EINVAL, ENOSYS5277 */5278#define MC_CMD_WOL_FILTER_REMOVE 0x335279#undef MC_CMD_0x33_PRIVILEGE_CTG5280 5281#define MC_CMD_0x33_PRIVILEGE_CTG SRIOV_CTG_LINK5282 5283/* MC_CMD_WOL_FILTER_REMOVE_IN msgrequest */5284#define MC_CMD_WOL_FILTER_REMOVE_IN_LEN 45285#define MC_CMD_WOL_FILTER_REMOVE_IN_FILTER_ID_OFST 05286#define MC_CMD_WOL_FILTER_REMOVE_IN_FILTER_ID_LEN 45287 5288/* MC_CMD_WOL_FILTER_REMOVE_OUT msgresponse */5289#define MC_CMD_WOL_FILTER_REMOVE_OUT_LEN 05290 5291 5292/***********************************/5293/* MC_CMD_WOL_FILTER_RESET5294 * Reset (i.e. remove all) WoL filters. Locks required: None. Returns: 0,5295 * ENOSYS5296 */5297#define MC_CMD_WOL_FILTER_RESET 0x345298#undef MC_CMD_0x34_PRIVILEGE_CTG5299 5300#define MC_CMD_0x34_PRIVILEGE_CTG SRIOV_CTG_LINK5301 5302/* MC_CMD_WOL_FILTER_RESET_IN msgrequest */5303#define MC_CMD_WOL_FILTER_RESET_IN_LEN 45304#define MC_CMD_WOL_FILTER_RESET_IN_MASK_OFST 05305#define MC_CMD_WOL_FILTER_RESET_IN_MASK_LEN 45306#define MC_CMD_WOL_FILTER_RESET_IN_WAKE_FILTERS 0x1 /* enum */5307#define MC_CMD_WOL_FILTER_RESET_IN_LIGHTSOUT_OFFLOADS 0x2 /* enum */5308 5309/* MC_CMD_WOL_FILTER_RESET_OUT msgresponse */5310#define MC_CMD_WOL_FILTER_RESET_OUT_LEN 05311 5312 5313/***********************************/5314/* MC_CMD_SET_MCAST_HASH5315 * Set the MCAST hash value without otherwise reconfiguring the MAC5316 */5317#define MC_CMD_SET_MCAST_HASH 0x355318 5319/* MC_CMD_SET_MCAST_HASH_IN msgrequest */5320#define MC_CMD_SET_MCAST_HASH_IN_LEN 325321#define MC_CMD_SET_MCAST_HASH_IN_HASH0_OFST 05322#define MC_CMD_SET_MCAST_HASH_IN_HASH0_LEN 165323#define MC_CMD_SET_MCAST_HASH_IN_HASH1_OFST 165324#define MC_CMD_SET_MCAST_HASH_IN_HASH1_LEN 165325 5326/* MC_CMD_SET_MCAST_HASH_OUT msgresponse */5327#define MC_CMD_SET_MCAST_HASH_OUT_LEN 05328 5329 5330/***********************************/5331/* MC_CMD_NVRAM_TYPES5332 * Return bitfield indicating available types of virtual NVRAM partitions.5333 * Locks required: none. Returns: 05334 */5335#define MC_CMD_NVRAM_TYPES 0x365336#undef MC_CMD_0x36_PRIVILEGE_CTG5337 5338#define MC_CMD_0x36_PRIVILEGE_CTG SRIOV_CTG_ADMIN5339 5340/* MC_CMD_NVRAM_TYPES_IN msgrequest */5341#define MC_CMD_NVRAM_TYPES_IN_LEN 05342 5343/* MC_CMD_NVRAM_TYPES_OUT msgresponse */5344#define MC_CMD_NVRAM_TYPES_OUT_LEN 45345/* Bit mask of supported types. */5346#define MC_CMD_NVRAM_TYPES_OUT_TYPES_OFST 05347#define MC_CMD_NVRAM_TYPES_OUT_TYPES_LEN 45348/* enum: Disabled callisto. */5349#define MC_CMD_NVRAM_TYPE_DISABLED_CALLISTO 0x05350/* enum: MC firmware. */5351#define MC_CMD_NVRAM_TYPE_MC_FW 0x15352/* enum: MC backup firmware. */5353#define MC_CMD_NVRAM_TYPE_MC_FW_BACKUP 0x25354/* enum: Static configuration Port0. */5355#define MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT0 0x35356/* enum: Static configuration Port1. */5357#define MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT1 0x45358/* enum: Dynamic configuration Port0. */5359#define MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT0 0x55360/* enum: Dynamic configuration Port1. */5361#define MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT1 0x65362/* enum: Expansion Rom. */5363#define MC_CMD_NVRAM_TYPE_EXP_ROM 0x75364/* enum: Expansion Rom Configuration Port0. */5365#define MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT0 0x85366/* enum: Expansion Rom Configuration Port1. */5367#define MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT1 0x95368/* enum: Phy Configuration Port0. */5369#define MC_CMD_NVRAM_TYPE_PHY_PORT0 0xa5370/* enum: Phy Configuration Port1. */5371#define MC_CMD_NVRAM_TYPE_PHY_PORT1 0xb5372/* enum: Log. */5373#define MC_CMD_NVRAM_TYPE_LOG 0xc5374/* enum: FPGA image. */5375#define MC_CMD_NVRAM_TYPE_FPGA 0xd5376/* enum: FPGA backup image */5377#define MC_CMD_NVRAM_TYPE_FPGA_BACKUP 0xe5378/* enum: FC firmware. */5379#define MC_CMD_NVRAM_TYPE_FC_FW 0xf5380/* enum: FC backup firmware. */5381#define MC_CMD_NVRAM_TYPE_FC_FW_BACKUP 0x105382/* enum: CPLD image. */5383#define MC_CMD_NVRAM_TYPE_CPLD 0x115384/* enum: Licensing information. */5385#define MC_CMD_NVRAM_TYPE_LICENSE 0x125386/* enum: FC Log. */5387#define MC_CMD_NVRAM_TYPE_FC_LOG 0x135388/* enum: Additional flash on FPGA. */5389#define MC_CMD_NVRAM_TYPE_FC_EXTRA 0x145390 5391 5392/***********************************/5393/* MC_CMD_NVRAM_INFO5394 * Read info about a virtual NVRAM partition. Locks required: none. Returns: 0,5395 * EINVAL (bad type).5396 */5397#define MC_CMD_NVRAM_INFO 0x375398#undef MC_CMD_0x37_PRIVILEGE_CTG5399 5400#define MC_CMD_0x37_PRIVILEGE_CTG SRIOV_CTG_ADMIN5401 5402/* MC_CMD_NVRAM_INFO_IN msgrequest */5403#define MC_CMD_NVRAM_INFO_IN_LEN 45404#define MC_CMD_NVRAM_INFO_IN_TYPE_OFST 05405#define MC_CMD_NVRAM_INFO_IN_TYPE_LEN 45406/* Enum values, see field(s): */5407/* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */5408 5409/* MC_CMD_NVRAM_INFO_OUT msgresponse */5410#define MC_CMD_NVRAM_INFO_OUT_LEN 245411#define MC_CMD_NVRAM_INFO_OUT_TYPE_OFST 05412#define MC_CMD_NVRAM_INFO_OUT_TYPE_LEN 45413/* Enum values, see field(s): */5414/* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */5415#define MC_CMD_NVRAM_INFO_OUT_SIZE_OFST 45416#define MC_CMD_NVRAM_INFO_OUT_SIZE_LEN 45417#define MC_CMD_NVRAM_INFO_OUT_ERASESIZE_OFST 85418#define MC_CMD_NVRAM_INFO_OUT_ERASESIZE_LEN 45419#define MC_CMD_NVRAM_INFO_OUT_FLAGS_OFST 125420#define MC_CMD_NVRAM_INFO_OUT_FLAGS_LEN 45421#define MC_CMD_NVRAM_INFO_OUT_PROTECTED_OFST 125422#define MC_CMD_NVRAM_INFO_OUT_PROTECTED_LBN 05423#define MC_CMD_NVRAM_INFO_OUT_PROTECTED_WIDTH 15424#define MC_CMD_NVRAM_INFO_OUT_TLV_OFST 125425#define MC_CMD_NVRAM_INFO_OUT_TLV_LBN 15426#define MC_CMD_NVRAM_INFO_OUT_TLV_WIDTH 15427#define MC_CMD_NVRAM_INFO_OUT_READ_ONLY_IF_TSA_BOUND_OFST 125428#define MC_CMD_NVRAM_INFO_OUT_READ_ONLY_IF_TSA_BOUND_LBN 25429#define MC_CMD_NVRAM_INFO_OUT_READ_ONLY_IF_TSA_BOUND_WIDTH 15430#define MC_CMD_NVRAM_INFO_OUT_CRC_OFST 125431#define MC_CMD_NVRAM_INFO_OUT_CRC_LBN 35432#define MC_CMD_NVRAM_INFO_OUT_CRC_WIDTH 15433#define MC_CMD_NVRAM_INFO_OUT_READ_ONLY_OFST 125434#define MC_CMD_NVRAM_INFO_OUT_READ_ONLY_LBN 55435#define MC_CMD_NVRAM_INFO_OUT_READ_ONLY_WIDTH 15436#define MC_CMD_NVRAM_INFO_OUT_CMAC_OFST 125437#define MC_CMD_NVRAM_INFO_OUT_CMAC_LBN 65438#define MC_CMD_NVRAM_INFO_OUT_CMAC_WIDTH 15439#define MC_CMD_NVRAM_INFO_OUT_A_B_OFST 125440#define MC_CMD_NVRAM_INFO_OUT_A_B_LBN 75441#define MC_CMD_NVRAM_INFO_OUT_A_B_WIDTH 15442#define MC_CMD_NVRAM_INFO_OUT_PHYSDEV_OFST 165443#define MC_CMD_NVRAM_INFO_OUT_PHYSDEV_LEN 45444#define MC_CMD_NVRAM_INFO_OUT_PHYSADDR_OFST 205445#define MC_CMD_NVRAM_INFO_OUT_PHYSADDR_LEN 45446 5447/* MC_CMD_NVRAM_INFO_V2_OUT msgresponse */5448#define MC_CMD_NVRAM_INFO_V2_OUT_LEN 285449#define MC_CMD_NVRAM_INFO_V2_OUT_TYPE_OFST 05450#define MC_CMD_NVRAM_INFO_V2_OUT_TYPE_LEN 45451/* Enum values, see field(s): */5452/* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */5453#define MC_CMD_NVRAM_INFO_V2_OUT_SIZE_OFST 45454#define MC_CMD_NVRAM_INFO_V2_OUT_SIZE_LEN 45455#define MC_CMD_NVRAM_INFO_V2_OUT_ERASESIZE_OFST 85456#define MC_CMD_NVRAM_INFO_V2_OUT_ERASESIZE_LEN 45457#define MC_CMD_NVRAM_INFO_V2_OUT_FLAGS_OFST 125458#define MC_CMD_NVRAM_INFO_V2_OUT_FLAGS_LEN 45459#define MC_CMD_NVRAM_INFO_V2_OUT_PROTECTED_OFST 125460#define MC_CMD_NVRAM_INFO_V2_OUT_PROTECTED_LBN 05461#define MC_CMD_NVRAM_INFO_V2_OUT_PROTECTED_WIDTH 15462#define MC_CMD_NVRAM_INFO_V2_OUT_TLV_OFST 125463#define MC_CMD_NVRAM_INFO_V2_OUT_TLV_LBN 15464#define MC_CMD_NVRAM_INFO_V2_OUT_TLV_WIDTH 15465#define MC_CMD_NVRAM_INFO_V2_OUT_READ_ONLY_IF_TSA_BOUND_OFST 125466#define MC_CMD_NVRAM_INFO_V2_OUT_READ_ONLY_IF_TSA_BOUND_LBN 25467#define MC_CMD_NVRAM_INFO_V2_OUT_READ_ONLY_IF_TSA_BOUND_WIDTH 15468#define MC_CMD_NVRAM_INFO_V2_OUT_READ_ONLY_OFST 125469#define MC_CMD_NVRAM_INFO_V2_OUT_READ_ONLY_LBN 55470#define MC_CMD_NVRAM_INFO_V2_OUT_READ_ONLY_WIDTH 15471#define MC_CMD_NVRAM_INFO_V2_OUT_A_B_OFST 125472#define MC_CMD_NVRAM_INFO_V2_OUT_A_B_LBN 75473#define MC_CMD_NVRAM_INFO_V2_OUT_A_B_WIDTH 15474#define MC_CMD_NVRAM_INFO_V2_OUT_PHYSDEV_OFST 165475#define MC_CMD_NVRAM_INFO_V2_OUT_PHYSDEV_LEN 45476#define MC_CMD_NVRAM_INFO_V2_OUT_PHYSADDR_OFST 205477#define MC_CMD_NVRAM_INFO_V2_OUT_PHYSADDR_LEN 45478/* Writes must be multiples of this size. Added to support the MUM on Sorrento.5479 */5480#define MC_CMD_NVRAM_INFO_V2_OUT_WRITESIZE_OFST 245481#define MC_CMD_NVRAM_INFO_V2_OUT_WRITESIZE_LEN 45482 5483 5484/***********************************/5485/* MC_CMD_NVRAM_UPDATE_START5486 * Start a group of update operations on a virtual NVRAM partition. Locks5487 * required: PHY_LOCK if type==*PHY*. Returns: 0, EINVAL (bad type), EACCES (if5488 * PHY_LOCK required and not held). In an adapter bound to a TSA controller,5489 * MC_CMD_NVRAM_UPDATE_START can only be used on a subset of partition types5490 * i.e. static config, dynamic config and expansion ROM config. Attempting to5491 * perform this operation on a restricted partition will return the error5492 * EPERM.5493 */5494#define MC_CMD_NVRAM_UPDATE_START 0x385495#undef MC_CMD_0x38_PRIVILEGE_CTG5496 5497#define MC_CMD_0x38_PRIVILEGE_CTG SRIOV_CTG_ADMIN5498 5499/* MC_CMD_NVRAM_UPDATE_START_IN msgrequest: Legacy NVRAM_UPDATE_START request.5500 * Use NVRAM_UPDATE_START_V2_IN in new code5501 */5502#define MC_CMD_NVRAM_UPDATE_START_IN_LEN 45503#define MC_CMD_NVRAM_UPDATE_START_IN_TYPE_OFST 05504#define MC_CMD_NVRAM_UPDATE_START_IN_TYPE_LEN 45505/* Enum values, see field(s): */5506/* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */5507 5508/* MC_CMD_NVRAM_UPDATE_START_V2_IN msgrequest: Extended NVRAM_UPDATE_START5509 * request with additional flags indicating version of command in use. See5510 * MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT for details of extended functionality. Use5511 * paired up with NVRAM_UPDATE_FINISH_V2_IN.5512 */5513#define MC_CMD_NVRAM_UPDATE_START_V2_IN_LEN 85514#define MC_CMD_NVRAM_UPDATE_START_V2_IN_TYPE_OFST 05515#define MC_CMD_NVRAM_UPDATE_START_V2_IN_TYPE_LEN 45516/* Enum values, see field(s): */5517/* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */5518#define MC_CMD_NVRAM_UPDATE_START_V2_IN_FLAGS_OFST 45519#define MC_CMD_NVRAM_UPDATE_START_V2_IN_FLAGS_LEN 45520#define MC_CMD_NVRAM_UPDATE_START_V2_IN_FLAG_REPORT_VERIFY_RESULT_OFST 45521#define MC_CMD_NVRAM_UPDATE_START_V2_IN_FLAG_REPORT_VERIFY_RESULT_LBN 05522#define MC_CMD_NVRAM_UPDATE_START_V2_IN_FLAG_REPORT_VERIFY_RESULT_WIDTH 15523 5524/* MC_CMD_NVRAM_UPDATE_START_OUT msgresponse */5525#define MC_CMD_NVRAM_UPDATE_START_OUT_LEN 05526 5527 5528/***********************************/5529/* MC_CMD_NVRAM_READ5530 * Read data from a virtual NVRAM partition. Locks required: PHY_LOCK if5531 * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if5532 * PHY_LOCK required and not held)5533 */5534#define MC_CMD_NVRAM_READ 0x395535#undef MC_CMD_0x39_PRIVILEGE_CTG5536 5537#define MC_CMD_0x39_PRIVILEGE_CTG SRIOV_CTG_ADMIN5538 5539/* MC_CMD_NVRAM_READ_IN msgrequest */5540#define MC_CMD_NVRAM_READ_IN_LEN 125541#define MC_CMD_NVRAM_READ_IN_TYPE_OFST 05542#define MC_CMD_NVRAM_READ_IN_TYPE_LEN 45543/* Enum values, see field(s): */5544/* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */5545#define MC_CMD_NVRAM_READ_IN_OFFSET_OFST 45546#define MC_CMD_NVRAM_READ_IN_OFFSET_LEN 45547/* amount to read in bytes */5548#define MC_CMD_NVRAM_READ_IN_LENGTH_OFST 85549#define MC_CMD_NVRAM_READ_IN_LENGTH_LEN 45550 5551/* MC_CMD_NVRAM_READ_IN_V2 msgrequest */5552#define MC_CMD_NVRAM_READ_IN_V2_LEN 165553#define MC_CMD_NVRAM_READ_IN_V2_TYPE_OFST 05554#define MC_CMD_NVRAM_READ_IN_V2_TYPE_LEN 45555/* Enum values, see field(s): */5556/* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */5557#define MC_CMD_NVRAM_READ_IN_V2_OFFSET_OFST 45558#define MC_CMD_NVRAM_READ_IN_V2_OFFSET_LEN 45559/* amount to read in bytes */5560#define MC_CMD_NVRAM_READ_IN_V2_LENGTH_OFST 85561#define MC_CMD_NVRAM_READ_IN_V2_LENGTH_LEN 45562/* Optional control info. If a partition is stored with an A/B versioning5563 * scheme (i.e. in more than one physical partition in NVRAM) the host can set5564 * this to control which underlying physical partition is used to read data5565 * from. This allows it to perform a read-modify-write-verify with the write5566 * lock continuously held by calling NVRAM_UPDATE_START, reading the old5567 * contents using MODE=TARGET_CURRENT, overwriting the old partition and then5568 * verifying by reading with MODE=TARGET_BACKUP.5569 */5570#define MC_CMD_NVRAM_READ_IN_V2_MODE_OFST 125571#define MC_CMD_NVRAM_READ_IN_V2_MODE_LEN 45572/* enum: Same as omitting MODE: caller sees data in current partition unless it5573 * holds the write lock in which case it sees data in the partition it is5574 * updating.5575 */5576#define MC_CMD_NVRAM_READ_IN_V2_DEFAULT 0x05577/* enum: Read from the current partition of an A/B pair, even if holding the5578 * write lock.5579 */5580#define MC_CMD_NVRAM_READ_IN_V2_TARGET_CURRENT 0x15581/* enum: Read from the non-current (i.e. to be updated) partition of an A/B5582 * pair5583 */5584#define MC_CMD_NVRAM_READ_IN_V2_TARGET_BACKUP 0x25585 5586/* MC_CMD_NVRAM_READ_OUT msgresponse */5587#define MC_CMD_NVRAM_READ_OUT_LENMIN 15588#define MC_CMD_NVRAM_READ_OUT_LENMAX 2525589#define MC_CMD_NVRAM_READ_OUT_LENMAX_MCDI2 10205590#define MC_CMD_NVRAM_READ_OUT_LEN(num) (0+1*(num))5591#define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_NUM(len) (((len)-0)/1)5592#define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_OFST 05593#define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_LEN 15594#define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_MINNUM 15595#define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_MAXNUM 2525596#define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_MAXNUM_MCDI2 10205597 5598 5599/***********************************/5600/* MC_CMD_NVRAM_WRITE5601 * Write data to a virtual NVRAM partition. Locks required: PHY_LOCK if5602 * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if5603 * PHY_LOCK required and not held)5604 */5605#define MC_CMD_NVRAM_WRITE 0x3a5606#undef MC_CMD_0x3a_PRIVILEGE_CTG5607 5608#define MC_CMD_0x3a_PRIVILEGE_CTG SRIOV_CTG_ADMIN5609 5610/* MC_CMD_NVRAM_WRITE_IN msgrequest */5611#define MC_CMD_NVRAM_WRITE_IN_LENMIN 135612#define MC_CMD_NVRAM_WRITE_IN_LENMAX 2525613#define MC_CMD_NVRAM_WRITE_IN_LENMAX_MCDI2 10205614#define MC_CMD_NVRAM_WRITE_IN_LEN(num) (12+1*(num))5615#define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_NUM(len) (((len)-12)/1)5616#define MC_CMD_NVRAM_WRITE_IN_TYPE_OFST 05617#define MC_CMD_NVRAM_WRITE_IN_TYPE_LEN 45618/* Enum values, see field(s): */5619/* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */5620#define MC_CMD_NVRAM_WRITE_IN_OFFSET_OFST 45621#define MC_CMD_NVRAM_WRITE_IN_OFFSET_LEN 45622#define MC_CMD_NVRAM_WRITE_IN_LENGTH_OFST 85623#define MC_CMD_NVRAM_WRITE_IN_LENGTH_LEN 45624#define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_OFST 125625#define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_LEN 15626#define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_MINNUM 15627#define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_MAXNUM 2405628#define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_MAXNUM_MCDI2 10085629 5630/* MC_CMD_NVRAM_WRITE_OUT msgresponse */5631#define MC_CMD_NVRAM_WRITE_OUT_LEN 05632 5633 5634/***********************************/5635/* MC_CMD_NVRAM_ERASE5636 * Erase sector(s) from a virtual NVRAM partition. Locks required: PHY_LOCK if5637 * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if5638 * PHY_LOCK required and not held)5639 */5640#define MC_CMD_NVRAM_ERASE 0x3b5641#undef MC_CMD_0x3b_PRIVILEGE_CTG5642 5643#define MC_CMD_0x3b_PRIVILEGE_CTG SRIOV_CTG_ADMIN5644 5645/* MC_CMD_NVRAM_ERASE_IN msgrequest */5646#define MC_CMD_NVRAM_ERASE_IN_LEN 125647#define MC_CMD_NVRAM_ERASE_IN_TYPE_OFST 05648#define MC_CMD_NVRAM_ERASE_IN_TYPE_LEN 45649/* Enum values, see field(s): */5650/* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */5651#define MC_CMD_NVRAM_ERASE_IN_OFFSET_OFST 45652#define MC_CMD_NVRAM_ERASE_IN_OFFSET_LEN 45653#define MC_CMD_NVRAM_ERASE_IN_LENGTH_OFST 85654#define MC_CMD_NVRAM_ERASE_IN_LENGTH_LEN 45655 5656/* MC_CMD_NVRAM_ERASE_OUT msgresponse */5657#define MC_CMD_NVRAM_ERASE_OUT_LEN 05658 5659 5660/***********************************/5661/* MC_CMD_NVRAM_UPDATE_FINISH5662 * Finish a group of update operations on a virtual NVRAM partition. Locks5663 * required: PHY_LOCK if type==*PHY*. Returns: 0, EINVAL (bad type/offset/5664 * length), EACCES (if PHY_LOCK required and not held). In an adapter bound to5665 * a TSA controller, MC_CMD_NVRAM_UPDATE_FINISH can only be used on a subset of5666 * partition types i.e. static config, dynamic config and expansion ROM config.5667 * Attempting to perform this operation on a restricted partition will return5668 * the error EPERM.5669 */5670#define MC_CMD_NVRAM_UPDATE_FINISH 0x3c5671#undef MC_CMD_0x3c_PRIVILEGE_CTG5672 5673#define MC_CMD_0x3c_PRIVILEGE_CTG SRIOV_CTG_ADMIN5674 5675/* MC_CMD_NVRAM_UPDATE_FINISH_IN msgrequest: Legacy NVRAM_UPDATE_FINISH5676 * request. Use NVRAM_UPDATE_FINISH_V2_IN in new code5677 */5678#define MC_CMD_NVRAM_UPDATE_FINISH_IN_LEN 85679#define MC_CMD_NVRAM_UPDATE_FINISH_IN_TYPE_OFST 05680#define MC_CMD_NVRAM_UPDATE_FINISH_IN_TYPE_LEN 45681/* Enum values, see field(s): */5682/* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */5683#define MC_CMD_NVRAM_UPDATE_FINISH_IN_REBOOT_OFST 45684#define MC_CMD_NVRAM_UPDATE_FINISH_IN_REBOOT_LEN 45685 5686/* MC_CMD_NVRAM_UPDATE_FINISH_V2_IN msgrequest: Extended NVRAM_UPDATE_FINISH5687 * request with additional flags indicating version of NVRAM_UPDATE commands in5688 * use. See MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT for details of extended5689 * functionality. Use paired up with NVRAM_UPDATE_START_V2_IN.5690 */5691#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_LEN 125692#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_TYPE_OFST 05693#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_TYPE_LEN 45694/* Enum values, see field(s): */5695/* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */5696#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_REBOOT_OFST 45697#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_REBOOT_LEN 45698#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAGS_OFST 85699#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAGS_LEN 45700#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_REPORT_VERIFY_RESULT_OFST 85701#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_REPORT_VERIFY_RESULT_LBN 05702#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_REPORT_VERIFY_RESULT_WIDTH 15703#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_RUN_IN_BACKGROUND_OFST 85704#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_RUN_IN_BACKGROUND_LBN 15705#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_RUN_IN_BACKGROUND_WIDTH 15706#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_POLL_VERIFY_RESULT_OFST 85707#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_POLL_VERIFY_RESULT_LBN 25708#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_POLL_VERIFY_RESULT_WIDTH 15709 5710/* MC_CMD_NVRAM_UPDATE_FINISH_OUT msgresponse: Legacy NVRAM_UPDATE_FINISH5711 * response. Use NVRAM_UPDATE_FINISH_V2_OUT in new code5712 */5713#define MC_CMD_NVRAM_UPDATE_FINISH_OUT_LEN 05714 5715/* MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT msgresponse:5716 *5717 * Extended NVRAM_UPDATE_FINISH response that communicates the result of secure5718 * firmware validation where applicable back to the host.5719 *5720 * Medford only: For signed firmware images, such as those for medford, the MC5721 * firmware verifies the signature before marking the firmware image as valid.5722 * This process takes a few seconds to complete. So is likely to take more than5723 * the MCDI timeout. Hence signature verification is initiated when5724 * MC_CMD_NVRAM_UPDATE_FINISH_V2_IN is received by the firmware, however, the5725 * MCDI command is run in a background MCDI processing thread. This response5726 * payload includes the results of the signature verification. Note that the5727 * per-partition nvram lock in firmware is only released after the verification5728 * has completed.5729 */5730#define MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT_LEN 45731/* Result of nvram update completion processing. Result codes that indicate an5732 * internal build failure and therefore not expected to be seen by customers in5733 * the field are marked with a prefix 'Internal-error'.5734 */5735#define MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT_RESULT_CODE_OFST 05736#define MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT_RESULT_CODE_LEN 45737/* enum: Invalid return code; only non-zero values are defined. Defined as5738 * unknown for backwards compatibility with NVRAM_UPDATE_FINISH_OUT.5739 */5740#define MC_CMD_NVRAM_VERIFY_RC_UNKNOWN 0x05741/* enum: Verify succeeded without any errors. */5742#define MC_CMD_NVRAM_VERIFY_RC_SUCCESS 0x15743/* enum: CMS format verification failed due to an internal error. */5744#define MC_CMD_NVRAM_VERIFY_RC_CMS_CHECK_FAILED 0x25745/* enum: Invalid CMS format in image metadata. */5746#define MC_CMD_NVRAM_VERIFY_RC_INVALID_CMS_FORMAT 0x35747/* enum: Message digest verification failed due to an internal error. */5748#define MC_CMD_NVRAM_VERIFY_RC_MESSAGE_DIGEST_CHECK_FAILED 0x45749/* enum: Error in message digest calculated over the reflash-header, payload5750 * and reflash-trailer.5751 */5752#define MC_CMD_NVRAM_VERIFY_RC_BAD_MESSAGE_DIGEST 0x55753/* enum: Signature verification failed due to an internal error. */5754#define MC_CMD_NVRAM_VERIFY_RC_SIGNATURE_CHECK_FAILED 0x65755/* enum: There are no valid signatures in the image. */5756#define MC_CMD_NVRAM_VERIFY_RC_NO_VALID_SIGNATURES 0x75757/* enum: Trusted approvers verification failed due to an internal error. */5758#define MC_CMD_NVRAM_VERIFY_RC_TRUSTED_APPROVERS_CHECK_FAILED 0x85759/* enum: The Trusted approver's list is empty. */5760#define MC_CMD_NVRAM_VERIFY_RC_NO_TRUSTED_APPROVERS 0x95761/* enum: Signature chain verification failed due to an internal error. */5762#define MC_CMD_NVRAM_VERIFY_RC_SIGNATURE_CHAIN_CHECK_FAILED 0xa5763/* enum: The signers of the signatures in the image are not listed in the5764 * Trusted approver's list.5765 */5766#define MC_CMD_NVRAM_VERIFY_RC_NO_SIGNATURE_MATCH 0xb5767/* enum: The image contains a test-signed certificate, but the adapter accepts5768 * only production signed images.5769 */5770#define MC_CMD_NVRAM_VERIFY_RC_REJECT_TEST_SIGNED 0xc5771/* enum: The image has a lower security level than the current firmware. */5772#define MC_CMD_NVRAM_VERIFY_RC_SECURITY_LEVEL_DOWNGRADE 0xd5773/* enum: Internal-error. The signed image is missing the 'contents' section,5774 * where the 'contents' section holds the actual image payload to be applied.5775 */5776#define MC_CMD_NVRAM_VERIFY_RC_CONTENT_NOT_FOUND 0xe5777/* enum: Internal-error. The bundle header is invalid. */5778#define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_CONTENT_HEADER_INVALID 0xf5779/* enum: Internal-error. The bundle does not have a valid reflash image layout.5780 */5781#define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_REFLASH_IMAGE_INVALID 0x105782/* enum: Internal-error. The bundle has an inconsistent layout of components or5783 * incorrect checksum.5784 */5785#define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_IMAGE_LAYOUT_INVALID 0x115786/* enum: Internal-error. The bundle manifest is inconsistent with components in5787 * the bundle.5788 */5789#define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_MANIFEST_INVALID 0x125790/* enum: Internal-error. The number of components in a bundle do not match the5791 * number of components advertised by the bundle manifest.5792 */5793#define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_MANIFEST_NUM_COMPONENTS_MISMATCH 0x135794/* enum: Internal-error. The bundle contains too many components for the MC5795 * firmware to process5796 */5797#define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_MANIFEST_TOO_MANY_COMPONENTS 0x145798/* enum: Internal-error. The bundle manifest has an invalid/inconsistent5799 * component.5800 */5801#define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_MANIFEST_COMPONENT_INVALID 0x155802/* enum: Internal-error. The hash of a component does not match the hash stored5803 * in the bundle manifest.5804 */5805#define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_MANIFEST_COMPONENT_HASH_MISMATCH 0x165806/* enum: Internal-error. Component hash calculation failed. */5807#define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_MANIFEST_COMPONENT_HASH_FAILED 0x175808/* enum: Internal-error. The component does not have a valid reflash image5809 * layout.5810 */5811#define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_COMPONENT_REFLASH_IMAGE_INVALID 0x185812/* enum: The bundle processing code failed to copy a component to its target5813 * partition.5814 */5815#define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_COMPONENT_COPY_FAILED 0x195816/* enum: The update operation is in-progress. */5817#define MC_CMD_NVRAM_VERIFY_RC_PENDING 0x1a5818 5819 5820/***********************************/5821/* MC_CMD_REBOOT5822 * Reboot the MC.5823 *5824 * The AFTER_ASSERTION flag is intended to be used when the driver notices an5825 * assertion failure (at which point it is expected to perform a complete tear5826 * down and reinitialise), to allow both ports to reset the MC once in an5827 * atomic fashion.5828 *5829 * Production mc firmwares are generally compiled with REBOOT_ON_ASSERT=1,5830 * which means that they will automatically reboot out of the assertion5831 * handler, so this is in practise an optional operation. It is still5832 * recommended that drivers execute this to support custom firmwares with5833 * REBOOT_ON_ASSERT=0.5834 *5835 * Locks required: NONE Returns: Nothing. You get back a response with ERR=1,5836 * DATALEN=05837 */5838#define MC_CMD_REBOOT 0x3d5839#undef MC_CMD_0x3d_PRIVILEGE_CTG5840 5841#define MC_CMD_0x3d_PRIVILEGE_CTG SRIOV_CTG_ADMIN5842 5843/* MC_CMD_REBOOT_IN msgrequest */5844#define MC_CMD_REBOOT_IN_LEN 45845#define MC_CMD_REBOOT_IN_FLAGS_OFST 05846#define MC_CMD_REBOOT_IN_FLAGS_LEN 45847#define MC_CMD_REBOOT_FLAGS_AFTER_ASSERTION 0x1 /* enum */5848 5849/* MC_CMD_REBOOT_OUT msgresponse */5850#define MC_CMD_REBOOT_OUT_LEN 05851 5852 5853/***********************************/5854/* MC_CMD_SCHEDINFO5855 * Request scheduler info. Locks required: NONE. Returns: An array of5856 * (timeslice,maximum overrun), one for each thread, in ascending order of5857 * thread address.5858 */5859#define MC_CMD_SCHEDINFO 0x3e5860#undef MC_CMD_0x3e_PRIVILEGE_CTG5861 5862#define MC_CMD_0x3e_PRIVILEGE_CTG SRIOV_CTG_ADMIN5863 5864/* MC_CMD_SCHEDINFO_IN msgrequest */5865#define MC_CMD_SCHEDINFO_IN_LEN 05866 5867/* MC_CMD_SCHEDINFO_OUT msgresponse */5868#define MC_CMD_SCHEDINFO_OUT_LENMIN 45869#define MC_CMD_SCHEDINFO_OUT_LENMAX 2525870#define MC_CMD_SCHEDINFO_OUT_LENMAX_MCDI2 10205871#define MC_CMD_SCHEDINFO_OUT_LEN(num) (0+4*(num))5872#define MC_CMD_SCHEDINFO_OUT_DATA_NUM(len) (((len)-0)/4)5873#define MC_CMD_SCHEDINFO_OUT_DATA_OFST 05874#define MC_CMD_SCHEDINFO_OUT_DATA_LEN 45875#define MC_CMD_SCHEDINFO_OUT_DATA_MINNUM 15876#define MC_CMD_SCHEDINFO_OUT_DATA_MAXNUM 635877#define MC_CMD_SCHEDINFO_OUT_DATA_MAXNUM_MCDI2 2555878 5879 5880/***********************************/5881/* MC_CMD_REBOOT_MODE5882 * Set the mode for the next MC reboot. Locks required: NONE. Sets the reboot5883 * mode to the specified value. Returns the old mode.5884 */5885#define MC_CMD_REBOOT_MODE 0x3f5886#undef MC_CMD_0x3f_PRIVILEGE_CTG5887 5888#define MC_CMD_0x3f_PRIVILEGE_CTG SRIOV_CTG_INSECURE5889 5890/* MC_CMD_REBOOT_MODE_IN msgrequest */5891#define MC_CMD_REBOOT_MODE_IN_LEN 45892#define MC_CMD_REBOOT_MODE_IN_VALUE_OFST 05893#define MC_CMD_REBOOT_MODE_IN_VALUE_LEN 45894/* enum: Normal. */5895#define MC_CMD_REBOOT_MODE_NORMAL 0x05896/* enum: Power-on Reset. */5897#define MC_CMD_REBOOT_MODE_POR 0x25898/* enum: Snapper. */5899#define MC_CMD_REBOOT_MODE_SNAPPER 0x35900/* enum: snapper fake POR */5901#define MC_CMD_REBOOT_MODE_SNAPPER_POR 0x45902#define MC_CMD_REBOOT_MODE_IN_FAKE_OFST 05903#define MC_CMD_REBOOT_MODE_IN_FAKE_LBN 75904#define MC_CMD_REBOOT_MODE_IN_FAKE_WIDTH 15905 5906/* MC_CMD_REBOOT_MODE_OUT msgresponse */5907#define MC_CMD_REBOOT_MODE_OUT_LEN 45908#define MC_CMD_REBOOT_MODE_OUT_VALUE_OFST 05909#define MC_CMD_REBOOT_MODE_OUT_VALUE_LEN 45910 5911 5912/***********************************/5913/* MC_CMD_SENSOR_INFO5914 * Returns information about every available sensor.5915 *5916 * Each sensor has a single (16bit) value, and a corresponding state. The5917 * mapping between value and state is nominally determined by the MC, but may5918 * be implemented using up to 2 ranges per sensor.5919 *5920 * This call returns a mask (32bit) of the sensors that are supported by this5921 * platform, then an array of sensor information structures, in order of sensor5922 * type (but without gaps for unimplemented sensors). Each structure defines5923 * the ranges for the corresponding sensor. An unused range is indicated by5924 * equal limit values. If one range is used, a value outside that range results5925 * in STATE_FATAL. If two ranges are used, a value outside the second range5926 * results in STATE_FATAL while a value outside the first and inside the second5927 * range results in STATE_WARNING.5928 *5929 * Sensor masks and sensor information arrays are organised into pages. For5930 * backward compatibility, older host software can only use sensors in page 0.5931 * Bit 32 in the sensor mask was previously unused, and is no reserved for use5932 * as the next page flag.5933 *5934 * If the request does not contain a PAGE value then firmware will only return5935 * page 0 of sensor information, with bit 31 in the sensor mask cleared.5936 *5937 * If the request contains a PAGE value then firmware responds with the sensor5938 * mask and sensor information array for that page of sensors. In this case bit5939 * 31 in the mask is set if another page exists.5940 *5941 * Locks required: None Returns: 05942 */5943#define MC_CMD_SENSOR_INFO 0x415944#undef MC_CMD_0x41_PRIVILEGE_CTG5945 5946#define MC_CMD_0x41_PRIVILEGE_CTG SRIOV_CTG_GENERAL5947 5948/* MC_CMD_SENSOR_INFO_IN msgrequest */5949#define MC_CMD_SENSOR_INFO_IN_LEN 05950 5951/* MC_CMD_SENSOR_INFO_EXT_IN msgrequest */5952#define MC_CMD_SENSOR_INFO_EXT_IN_LEN 45953/* Which page of sensors to report.5954 *5955 * Page 0 contains sensors 0 to 30 (sensor 31 is the next page bit).5956 *5957 * Page 1 contains sensors 32 to 62 (sensor 63 is the next page bit). etc.5958 */5959#define MC_CMD_SENSOR_INFO_EXT_IN_PAGE_OFST 05960#define MC_CMD_SENSOR_INFO_EXT_IN_PAGE_LEN 45961 5962/* MC_CMD_SENSOR_INFO_EXT_IN_V2 msgrequest */5963#define MC_CMD_SENSOR_INFO_EXT_IN_V2_LEN 85964/* Which page of sensors to report.5965 *5966 * Page 0 contains sensors 0 to 30 (sensor 31 is the next page bit).5967 *5968 * Page 1 contains sensors 32 to 62 (sensor 63 is the next page bit). etc.5969 */5970#define MC_CMD_SENSOR_INFO_EXT_IN_V2_PAGE_OFST 05971#define MC_CMD_SENSOR_INFO_EXT_IN_V2_PAGE_LEN 45972/* Flags controlling information retrieved */5973#define MC_CMD_SENSOR_INFO_EXT_IN_V2_FLAGS_OFST 45974#define MC_CMD_SENSOR_INFO_EXT_IN_V2_FLAGS_LEN 45975#define MC_CMD_SENSOR_INFO_EXT_IN_V2_ENGINEERING_OFST 45976#define MC_CMD_SENSOR_INFO_EXT_IN_V2_ENGINEERING_LBN 05977#define MC_CMD_SENSOR_INFO_EXT_IN_V2_ENGINEERING_WIDTH 15978 5979/* MC_CMD_SENSOR_INFO_OUT msgresponse */5980#define MC_CMD_SENSOR_INFO_OUT_LENMIN 45981#define MC_CMD_SENSOR_INFO_OUT_LENMAX 2525982#define MC_CMD_SENSOR_INFO_OUT_LENMAX_MCDI2 10205983#define MC_CMD_SENSOR_INFO_OUT_LEN(num) (4+8*(num))5984#define MC_CMD_SENSOR_INFO_OUT_MC_CMD_SENSOR_ENTRY_NUM(len) (((len)-4)/8)5985#define MC_CMD_SENSOR_INFO_OUT_MASK_OFST 05986#define MC_CMD_SENSOR_INFO_OUT_MASK_LEN 45987/* enum: Controller temperature: degC */5988#define MC_CMD_SENSOR_CONTROLLER_TEMP 0x05989/* enum: Phy common temperature: degC */5990#define MC_CMD_SENSOR_PHY_COMMON_TEMP 0x15991/* enum: Controller cooling: bool */5992#define MC_CMD_SENSOR_CONTROLLER_COOLING 0x25993/* enum: Phy 0 temperature: degC */5994#define MC_CMD_SENSOR_PHY0_TEMP 0x35995/* enum: Phy 0 cooling: bool */5996#define MC_CMD_SENSOR_PHY0_COOLING 0x45997/* enum: Phy 1 temperature: degC */5998#define MC_CMD_SENSOR_PHY1_TEMP 0x55999/* enum: Phy 1 cooling: bool */6000#define MC_CMD_SENSOR_PHY1_COOLING 0x66001/* enum: 1.0v power: mV */6002#define MC_CMD_SENSOR_IN_1V0 0x76003/* enum: 1.2v power: mV */6004#define MC_CMD_SENSOR_IN_1V2 0x86005/* enum: 1.8v power: mV */6006#define MC_CMD_SENSOR_IN_1V8 0x96007/* enum: 2.5v power: mV */6008#define MC_CMD_SENSOR_IN_2V5 0xa6009/* enum: 3.3v power: mV */6010#define MC_CMD_SENSOR_IN_3V3 0xb6011/* enum: 12v power: mV */6012#define MC_CMD_SENSOR_IN_12V0 0xc6013/* enum: 1.2v analogue power: mV */6014#define MC_CMD_SENSOR_IN_1V2A 0xd6015/* enum: reference voltage: mV */6016#define MC_CMD_SENSOR_IN_VREF 0xe6017/* enum: AOE FPGA power: mV */6018#define MC_CMD_SENSOR_OUT_VAOE 0xf6019/* enum: AOE FPGA temperature: degC */6020#define MC_CMD_SENSOR_AOE_TEMP 0x106021/* enum: AOE FPGA PSU temperature: degC */6022#define MC_CMD_SENSOR_PSU_AOE_TEMP 0x116023/* enum: AOE PSU temperature: degC */6024#define MC_CMD_SENSOR_PSU_TEMP 0x126025/* enum: Fan 0 speed: RPM */6026#define MC_CMD_SENSOR_FAN_0 0x136027/* enum: Fan 1 speed: RPM */6028#define MC_CMD_SENSOR_FAN_1 0x146029/* enum: Fan 2 speed: RPM */6030#define MC_CMD_SENSOR_FAN_2 0x156031/* enum: Fan 3 speed: RPM */6032#define MC_CMD_SENSOR_FAN_3 0x166033/* enum: Fan 4 speed: RPM */6034#define MC_CMD_SENSOR_FAN_4 0x176035/* enum: AOE FPGA input power: mV */6036#define MC_CMD_SENSOR_IN_VAOE 0x186037/* enum: AOE FPGA current: mA */6038#define MC_CMD_SENSOR_OUT_IAOE 0x196039/* enum: AOE FPGA input current: mA */6040#define MC_CMD_SENSOR_IN_IAOE 0x1a6041/* enum: NIC power consumption: W */6042#define MC_CMD_SENSOR_NIC_POWER 0x1b6043/* enum: 0.9v power voltage: mV */6044#define MC_CMD_SENSOR_IN_0V9 0x1c6045/* enum: 0.9v power current: mA */6046#define MC_CMD_SENSOR_IN_I0V9 0x1d6047/* enum: 1.2v power current: mA */6048#define MC_CMD_SENSOR_IN_I1V2 0x1e6049/* enum: Not a sensor: reserved for the next page flag */6050#define MC_CMD_SENSOR_PAGE0_NEXT 0x1f6051/* enum: 0.9v power voltage (at ADC): mV */6052#define MC_CMD_SENSOR_IN_0V9_ADC 0x206053/* enum: Controller temperature 2: degC */6054#define MC_CMD_SENSOR_CONTROLLER_2_TEMP 0x216055/* enum: Voltage regulator internal temperature: degC */6056#define MC_CMD_SENSOR_VREG_INTERNAL_TEMP 0x226057/* enum: 0.9V voltage regulator temperature: degC */6058#define MC_CMD_SENSOR_VREG_0V9_TEMP 0x236059/* enum: 1.2V voltage regulator temperature: degC */6060#define MC_CMD_SENSOR_VREG_1V2_TEMP 0x246061/* enum: controller internal temperature sensor voltage (internal ADC): mV */6062#define MC_CMD_SENSOR_CONTROLLER_VPTAT 0x256063/* enum: controller internal temperature (internal ADC): degC */6064#define MC_CMD_SENSOR_CONTROLLER_INTERNAL_TEMP 0x266065/* enum: controller internal temperature sensor voltage (external ADC): mV */6066#define MC_CMD_SENSOR_CONTROLLER_VPTAT_EXTADC 0x276067/* enum: controller internal temperature (external ADC): degC */6068#define MC_CMD_SENSOR_CONTROLLER_INTERNAL_TEMP_EXTADC 0x286069/* enum: ambient temperature: degC */6070#define MC_CMD_SENSOR_AMBIENT_TEMP 0x296071/* enum: air flow: bool */6072#define MC_CMD_SENSOR_AIRFLOW 0x2a6073/* enum: voltage between VSS08D and VSS08D at CSR: mV */6074#define MC_CMD_SENSOR_VDD08D_VSS08D_CSR 0x2b6075/* enum: voltage between VSS08D and VSS08D at CSR (external ADC): mV */6076#define MC_CMD_SENSOR_VDD08D_VSS08D_CSR_EXTADC 0x2c6077/* enum: Hotpoint temperature: degC */6078#define MC_CMD_SENSOR_HOTPOINT_TEMP 0x2d6079/* enum: Port 0 PHY power switch over-current: bool */6080#define MC_CMD_SENSOR_PHY_POWER_PORT0 0x2e6081/* enum: Port 1 PHY power switch over-current: bool */6082#define MC_CMD_SENSOR_PHY_POWER_PORT1 0x2f6083/* enum: Mop-up microcontroller reference voltage: mV */6084#define MC_CMD_SENSOR_MUM_VCC 0x306085/* enum: 0.9v power phase A voltage: mV */6086#define MC_CMD_SENSOR_IN_0V9_A 0x316087/* enum: 0.9v power phase A current: mA */6088#define MC_CMD_SENSOR_IN_I0V9_A 0x326089/* enum: 0.9V voltage regulator phase A temperature: degC */6090#define MC_CMD_SENSOR_VREG_0V9_A_TEMP 0x336091/* enum: 0.9v power phase B voltage: mV */6092#define MC_CMD_SENSOR_IN_0V9_B 0x346093/* enum: 0.9v power phase B current: mA */6094#define MC_CMD_SENSOR_IN_I0V9_B 0x356095/* enum: 0.9V voltage regulator phase B temperature: degC */6096#define MC_CMD_SENSOR_VREG_0V9_B_TEMP 0x366097/* enum: CCOM AVREG 1v2 supply (interval ADC): mV */6098#define MC_CMD_SENSOR_CCOM_AVREG_1V2_SUPPLY 0x376099/* enum: CCOM AVREG 1v2 supply (external ADC): mV */6100#define MC_CMD_SENSOR_CCOM_AVREG_1V2_SUPPLY_EXTADC 0x386101/* enum: CCOM AVREG 1v8 supply (interval ADC): mV */6102#define MC_CMD_SENSOR_CCOM_AVREG_1V8_SUPPLY 0x396103/* enum: CCOM AVREG 1v8 supply (external ADC): mV */6104#define MC_CMD_SENSOR_CCOM_AVREG_1V8_SUPPLY_EXTADC 0x3a6105/* enum: CCOM RTS temperature: degC */6106#define MC_CMD_SENSOR_CONTROLLER_RTS 0x3b6107/* enum: Not a sensor: reserved for the next page flag */6108#define MC_CMD_SENSOR_PAGE1_NEXT 0x3f6109/* enum: controller internal temperature sensor voltage on master core6110 * (internal ADC): mV6111 */6112#define MC_CMD_SENSOR_CONTROLLER_MASTER_VPTAT 0x406113/* enum: controller internal temperature on master core (internal ADC): degC */6114#define MC_CMD_SENSOR_CONTROLLER_MASTER_INTERNAL_TEMP 0x416115/* enum: controller internal temperature sensor voltage on master core6116 * (external ADC): mV6117 */6118#define MC_CMD_SENSOR_CONTROLLER_MASTER_VPTAT_EXTADC 0x426119/* enum: controller internal temperature on master core (external ADC): degC */6120#define MC_CMD_SENSOR_CONTROLLER_MASTER_INTERNAL_TEMP_EXTADC 0x436121/* enum: controller internal temperature on slave core sensor voltage (internal6122 * ADC): mV6123 */6124#define MC_CMD_SENSOR_CONTROLLER_SLAVE_VPTAT 0x446125/* enum: controller internal temperature on slave core (internal ADC): degC */6126#define MC_CMD_SENSOR_CONTROLLER_SLAVE_INTERNAL_TEMP 0x456127/* enum: controller internal temperature on slave core sensor voltage (external6128 * ADC): mV6129 */6130#define MC_CMD_SENSOR_CONTROLLER_SLAVE_VPTAT_EXTADC 0x466131/* enum: controller internal temperature on slave core (external ADC): degC */6132#define MC_CMD_SENSOR_CONTROLLER_SLAVE_INTERNAL_TEMP_EXTADC 0x476133/* enum: Voltage supplied to the SODIMMs from their power supply: mV */6134#define MC_CMD_SENSOR_SODIMM_VOUT 0x496135/* enum: Temperature of SODIMM 0 (if installed): degC */6136#define MC_CMD_SENSOR_SODIMM_0_TEMP 0x4a6137/* enum: Temperature of SODIMM 1 (if installed): degC */6138#define MC_CMD_SENSOR_SODIMM_1_TEMP 0x4b6139/* enum: Voltage supplied to the QSFP #0 from their power supply: mV */6140#define MC_CMD_SENSOR_PHY0_VCC 0x4c6141/* enum: Voltage supplied to the QSFP #1 from their power supply: mV */6142#define MC_CMD_SENSOR_PHY1_VCC 0x4d6143/* enum: Controller die temperature (TDIODE): degC */6144#define MC_CMD_SENSOR_CONTROLLER_TDIODE_TEMP 0x4e6145/* enum: Board temperature (front): degC */6146#define MC_CMD_SENSOR_BOARD_FRONT_TEMP 0x4f6147/* enum: Board temperature (back): degC */6148#define MC_CMD_SENSOR_BOARD_BACK_TEMP 0x506149/* enum: 1.8v power current: mA */6150#define MC_CMD_SENSOR_IN_I1V8 0x516151/* enum: 2.5v power current: mA */6152#define MC_CMD_SENSOR_IN_I2V5 0x526153/* enum: 3.3v power current: mA */6154#define MC_CMD_SENSOR_IN_I3V3 0x536155/* enum: 12v power current: mA */6156#define MC_CMD_SENSOR_IN_I12V0 0x546157/* enum: 1.3v power: mV */6158#define MC_CMD_SENSOR_IN_1V3 0x556159/* enum: 1.3v power current: mA */6160#define MC_CMD_SENSOR_IN_I1V3 0x566161/* enum: Engineering sensor 1 */6162#define MC_CMD_SENSOR_ENGINEERING_1 0x576163/* enum: Engineering sensor 2 */6164#define MC_CMD_SENSOR_ENGINEERING_2 0x586165/* enum: Engineering sensor 3 */6166#define MC_CMD_SENSOR_ENGINEERING_3 0x596167/* enum: Engineering sensor 4 */6168#define MC_CMD_SENSOR_ENGINEERING_4 0x5a6169/* enum: Engineering sensor 5 */6170#define MC_CMD_SENSOR_ENGINEERING_5 0x5b6171/* enum: Engineering sensor 6 */6172#define MC_CMD_SENSOR_ENGINEERING_6 0x5c6173/* enum: Engineering sensor 7 */6174#define MC_CMD_SENSOR_ENGINEERING_7 0x5d6175/* enum: Engineering sensor 8 */6176#define MC_CMD_SENSOR_ENGINEERING_8 0x5e6177/* enum: Not a sensor: reserved for the next page flag */6178#define MC_CMD_SENSOR_PAGE2_NEXT 0x5f6179/* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF */6180#define MC_CMD_SENSOR_ENTRY_OFST 46181#define MC_CMD_SENSOR_ENTRY_LEN 86182#define MC_CMD_SENSOR_ENTRY_LO_OFST 46183#define MC_CMD_SENSOR_ENTRY_HI_OFST 86184#define MC_CMD_SENSOR_ENTRY_MINNUM 06185#define MC_CMD_SENSOR_ENTRY_MAXNUM 316186#define MC_CMD_SENSOR_ENTRY_MAXNUM_MCDI2 1276187 6188/* MC_CMD_SENSOR_INFO_EXT_OUT msgresponse */6189#define MC_CMD_SENSOR_INFO_EXT_OUT_LENMIN 46190#define MC_CMD_SENSOR_INFO_EXT_OUT_LENMAX 2526191#define MC_CMD_SENSOR_INFO_EXT_OUT_LENMAX_MCDI2 10206192#define MC_CMD_SENSOR_INFO_EXT_OUT_LEN(num) (4+8*(num))6193#define MC_CMD_SENSOR_INFO_EXT_OUT_MC_CMD_SENSOR_ENTRY_NUM(len) (((len)-4)/8)6194#define MC_CMD_SENSOR_INFO_EXT_OUT_MASK_OFST 06195#define MC_CMD_SENSOR_INFO_EXT_OUT_MASK_LEN 46196/* Enum values, see field(s): */6197/* MC_CMD_SENSOR_INFO_OUT */6198#define MC_CMD_SENSOR_INFO_EXT_OUT_NEXT_PAGE_OFST 06199#define MC_CMD_SENSOR_INFO_EXT_OUT_NEXT_PAGE_LBN 316200#define MC_CMD_SENSOR_INFO_EXT_OUT_NEXT_PAGE_WIDTH 16201/* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF */6202/* MC_CMD_SENSOR_ENTRY_OFST 4 */6203/* MC_CMD_SENSOR_ENTRY_LEN 8 */6204/* MC_CMD_SENSOR_ENTRY_LO_OFST 4 */6205/* MC_CMD_SENSOR_ENTRY_HI_OFST 8 */6206/* MC_CMD_SENSOR_ENTRY_MINNUM 0 */6207/* MC_CMD_SENSOR_ENTRY_MAXNUM 31 */6208/* MC_CMD_SENSOR_ENTRY_MAXNUM_MCDI2 127 */6209 6210/* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF structuredef */6211#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_LEN 86212#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_OFST 06213#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_LEN 26214#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_LBN 06215#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_WIDTH 166216#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_OFST 26217#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_LEN 26218#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_LBN 166219#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_WIDTH 166220#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_OFST 46221#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_LEN 26222#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_LBN 326223#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_WIDTH 166224#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_OFST 66225#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_LEN 26226#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_LBN 486227#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_WIDTH 166228 6229 6230/***********************************/6231/* MC_CMD_READ_SENSORS6232 * Returns the current reading from each sensor. DMAs an array of sensor6233 * readings, in order of sensor type (but without gaps for unimplemented6234 * sensors), into host memory. Each array element is a6235 * MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF dword.6236 *6237 * If the request does not contain the LENGTH field then only sensors 0 to 306238 * are reported, to avoid DMA buffer overflow in older host software. If the6239 * sensor reading require more space than the LENGTH allows, then return6240 * EINVAL.6241 *6242 * The MC will send a SENSOREVT event every time any sensor changes state. The6243 * driver is responsible for ensuring that it doesn't miss any events. The6244 * board will function normally if all sensors are in STATE_OK or6245 * STATE_WARNING. Otherwise the board should not be expected to function.6246 */6247#define MC_CMD_READ_SENSORS 0x426248#undef MC_CMD_0x42_PRIVILEGE_CTG6249 6250#define MC_CMD_0x42_PRIVILEGE_CTG SRIOV_CTG_GENERAL6251 6252/* MC_CMD_READ_SENSORS_IN msgrequest */6253#define MC_CMD_READ_SENSORS_IN_LEN 86254/* DMA address of host buffer for sensor readings (must be 4Kbyte aligned).6255 *6256 * If the address is 0xffffffffffffffff send the readings in the response (used6257 * by cmdclient).6258 */6259#define MC_CMD_READ_SENSORS_IN_DMA_ADDR_OFST 06260#define MC_CMD_READ_SENSORS_IN_DMA_ADDR_LEN 86261#define MC_CMD_READ_SENSORS_IN_DMA_ADDR_LO_OFST 06262#define MC_CMD_READ_SENSORS_IN_DMA_ADDR_HI_OFST 46263 6264/* MC_CMD_READ_SENSORS_EXT_IN msgrequest */6265#define MC_CMD_READ_SENSORS_EXT_IN_LEN 126266/* DMA address of host buffer for sensor readings (must be 4Kbyte aligned).6267 *6268 * If the address is 0xffffffffffffffff send the readings in the response (used6269 * by cmdclient).6270 */6271#define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_OFST 06272#define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LEN 86273#define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LO_OFST 06274#define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_HI_OFST 46275/* Size in bytes of host buffer. */6276#define MC_CMD_READ_SENSORS_EXT_IN_LENGTH_OFST 86277#define MC_CMD_READ_SENSORS_EXT_IN_LENGTH_LEN 46278 6279/* MC_CMD_READ_SENSORS_EXT_IN_V2 msgrequest */6280#define MC_CMD_READ_SENSORS_EXT_IN_V2_LEN 166281/* DMA address of host buffer for sensor readings (must be 4Kbyte aligned).6282 *6283 * If the address is 0xffffffffffffffff send the readings in the response (used6284 * by cmdclient).6285 */6286#define MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_OFST 06287#define MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_LEN 86288#define MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_LO_OFST 06289#define MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_HI_OFST 46290/* Size in bytes of host buffer. */6291#define MC_CMD_READ_SENSORS_EXT_IN_V2_LENGTH_OFST 86292#define MC_CMD_READ_SENSORS_EXT_IN_V2_LENGTH_LEN 46293/* Flags controlling information retrieved */6294#define MC_CMD_READ_SENSORS_EXT_IN_V2_FLAGS_OFST 126295#define MC_CMD_READ_SENSORS_EXT_IN_V2_FLAGS_LEN 46296#define MC_CMD_READ_SENSORS_EXT_IN_V2_ENGINEERING_OFST 126297#define MC_CMD_READ_SENSORS_EXT_IN_V2_ENGINEERING_LBN 06298#define MC_CMD_READ_SENSORS_EXT_IN_V2_ENGINEERING_WIDTH 16299 6300/* MC_CMD_READ_SENSORS_OUT msgresponse */6301#define MC_CMD_READ_SENSORS_OUT_LEN 06302 6303/* MC_CMD_READ_SENSORS_EXT_OUT msgresponse */6304#define MC_CMD_READ_SENSORS_EXT_OUT_LEN 06305 6306/* MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF structuredef */6307#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_LEN 46308#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_OFST 06309#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_LEN 26310#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_LBN 06311#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_WIDTH 166312#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_OFST 26313#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_LEN 16314/* enum: Ok. */6315#define MC_CMD_SENSOR_STATE_OK 0x06316/* enum: Breached warning threshold. */6317#define MC_CMD_SENSOR_STATE_WARNING 0x16318/* enum: Breached fatal threshold. */6319#define MC_CMD_SENSOR_STATE_FATAL 0x26320/* enum: Fault with sensor. */6321#define MC_CMD_SENSOR_STATE_BROKEN 0x36322/* enum: Sensor is working but does not currently have a reading. */6323#define MC_CMD_SENSOR_STATE_NO_READING 0x46324/* enum: Sensor initialisation failed. */6325#define MC_CMD_SENSOR_STATE_INIT_FAILED 0x56326#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_LBN 166327#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_WIDTH 86328#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_OFST 36329#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_LEN 16330/* Enum values, see field(s): */6331/* MC_CMD_SENSOR_INFO/MC_CMD_SENSOR_INFO_OUT/MASK */6332#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_LBN 246333#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_WIDTH 86334 6335 6336/***********************************/6337/* MC_CMD_GET_PHY_STATE6338 * Report current state of PHY. A 'zombie' PHY is a PHY that has failed to boot6339 * (e.g. due to missing or corrupted firmware). Locks required: None. Return6340 * code: 06341 */6342#define MC_CMD_GET_PHY_STATE 0x436343#undef MC_CMD_0x43_PRIVILEGE_CTG6344 6345#define MC_CMD_0x43_PRIVILEGE_CTG SRIOV_CTG_GENERAL6346 6347/* MC_CMD_GET_PHY_STATE_IN msgrequest */6348#define MC_CMD_GET_PHY_STATE_IN_LEN 06349 6350/* MC_CMD_GET_PHY_STATE_OUT msgresponse */6351#define MC_CMD_GET_PHY_STATE_OUT_LEN 46352#define MC_CMD_GET_PHY_STATE_OUT_STATE_OFST 06353#define MC_CMD_GET_PHY_STATE_OUT_STATE_LEN 46354/* enum: Ok. */6355#define MC_CMD_PHY_STATE_OK 0x16356/* enum: Faulty. */6357#define MC_CMD_PHY_STATE_ZOMBIE 0x26358 6359 6360/***********************************/6361/* MC_CMD_SETUP_8021QBB6362 * 802.1Qbb control. 8 Tx queues that map to priorities 0 - 7. Use all 1s to6363 * disable 802.Qbb for a given priority.6364 */6365#define MC_CMD_SETUP_8021QBB 0x446366 6367/* MC_CMD_SETUP_8021QBB_IN msgrequest */6368#define MC_CMD_SETUP_8021QBB_IN_LEN 326369#define MC_CMD_SETUP_8021QBB_IN_TXQS_OFST 06370#define MC_CMD_SETUP_8021QBB_IN_TXQS_LEN 326371 6372/* MC_CMD_SETUP_8021QBB_OUT msgresponse */6373#define MC_CMD_SETUP_8021QBB_OUT_LEN 06374 6375 6376/***********************************/6377/* MC_CMD_WOL_FILTER_GET6378 * Retrieve ID of any WoL filters. Locks required: None. Returns: 0, ENOSYS6379 */6380#define MC_CMD_WOL_FILTER_GET 0x456381#undef MC_CMD_0x45_PRIVILEGE_CTG6382 6383#define MC_CMD_0x45_PRIVILEGE_CTG SRIOV_CTG_LINK6384 6385/* MC_CMD_WOL_FILTER_GET_IN msgrequest */6386#define MC_CMD_WOL_FILTER_GET_IN_LEN 06387 6388/* MC_CMD_WOL_FILTER_GET_OUT msgresponse */6389#define MC_CMD_WOL_FILTER_GET_OUT_LEN 46390#define MC_CMD_WOL_FILTER_GET_OUT_FILTER_ID_OFST 06391#define MC_CMD_WOL_FILTER_GET_OUT_FILTER_ID_LEN 46392 6393 6394/***********************************/6395/* MC_CMD_ADD_LIGHTSOUT_OFFLOAD6396 * Add a protocol offload to NIC for lights-out state. Locks required: None.6397 * Returns: 0, ENOSYS6398 */6399#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD 0x466400#undef MC_CMD_0x46_PRIVILEGE_CTG6401 6402#define MC_CMD_0x46_PRIVILEGE_CTG SRIOV_CTG_LINK6403 6404/* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN msgrequest */6405#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LENMIN 86406#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LENMAX 2526407#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LENMAX_MCDI2 10206408#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LEN(num) (4+4*(num))6409#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_NUM(len) (((len)-4)/4)6410#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 06411#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_LEN 46412#define MC_CMD_LIGHTSOUT_OFFLOAD_PROTOCOL_ARP 0x1 /* enum */6413#define MC_CMD_LIGHTSOUT_OFFLOAD_PROTOCOL_NS 0x2 /* enum */6414#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_OFST 46415#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_LEN 46416#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_MINNUM 16417#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_MAXNUM 626418#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_MAXNUM_MCDI2 2546419 6420/* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP msgrequest */6421#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_LEN 146422/* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 */6423/* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_LEN 4 */6424#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_MAC_OFST 46425#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_MAC_LEN 66426#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_IP_OFST 106427#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_IP_LEN 46428 6429/* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS msgrequest */6430#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_LEN 426431/* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 */6432/* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_LEN 4 */6433#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_MAC_OFST 46434#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_MAC_LEN 66435#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_SNIPV6_OFST 106436#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_SNIPV6_LEN 166437#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_IPV6_OFST 266438#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_IPV6_LEN 166439 6440/* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT msgresponse */6441#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_LEN 46442#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_FILTER_ID_OFST 06443#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_FILTER_ID_LEN 46444 6445 6446/***********************************/6447/* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD6448 * Remove a protocol offload from NIC for lights-out state. Locks required:6449 * None. Returns: 0, ENOSYS6450 */6451#define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD 0x476452#undef MC_CMD_0x47_PRIVILEGE_CTG6453 6454#define MC_CMD_0x47_PRIVILEGE_CTG SRIOV_CTG_LINK6455 6456/* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN msgrequest */6457#define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_LEN 86458#define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 06459#define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_LEN 46460#define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_FILTER_ID_OFST 46461#define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_FILTER_ID_LEN 46462 6463/* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_OUT msgresponse */6464#define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_OUT_LEN 06465 6466 6467/***********************************/6468/* MC_CMD_MAC_RESET_RESTORE6469 * Restore MAC after block reset. Locks required: None. Returns: 0.6470 */6471#define MC_CMD_MAC_RESET_RESTORE 0x486472 6473/* MC_CMD_MAC_RESET_RESTORE_IN msgrequest */6474#define MC_CMD_MAC_RESET_RESTORE_IN_LEN 06475 6476/* MC_CMD_MAC_RESET_RESTORE_OUT msgresponse */6477#define MC_CMD_MAC_RESET_RESTORE_OUT_LEN 06478 6479 6480/***********************************/6481/* MC_CMD_TESTASSERT6482 * Deliberately trigger an assert-detonation in the firmware for testing6483 * purposes (i.e. to allow tests that the driver copes gracefully). Locks6484 * required: None Returns: 06485 */6486#define MC_CMD_TESTASSERT 0x496487#undef MC_CMD_0x49_PRIVILEGE_CTG6488 6489#define MC_CMD_0x49_PRIVILEGE_CTG SRIOV_CTG_ADMIN6490 6491/* MC_CMD_TESTASSERT_IN msgrequest */6492#define MC_CMD_TESTASSERT_IN_LEN 06493 6494/* MC_CMD_TESTASSERT_OUT msgresponse */6495#define MC_CMD_TESTASSERT_OUT_LEN 06496 6497/* MC_CMD_TESTASSERT_V2_IN msgrequest */6498#define MC_CMD_TESTASSERT_V2_IN_LEN 46499/* How to provoke the assertion */6500#define MC_CMD_TESTASSERT_V2_IN_TYPE_OFST 06501#define MC_CMD_TESTASSERT_V2_IN_TYPE_LEN 46502/* enum: Assert using the FAIL_ASSERTION_WITH_USEFUL_VALUES macro. Unless6503 * you're testing firmware, this is what you want.6504 */6505#define MC_CMD_TESTASSERT_V2_IN_FAIL_ASSERTION_WITH_USEFUL_VALUES 0x06506/* enum: Assert using assert(0); */6507#define MC_CMD_TESTASSERT_V2_IN_ASSERT_FALSE 0x16508/* enum: Deliberately trigger a watchdog */6509#define MC_CMD_TESTASSERT_V2_IN_WATCHDOG 0x26510/* enum: Deliberately trigger a trap by loading from an invalid address */6511#define MC_CMD_TESTASSERT_V2_IN_LOAD_TRAP 0x36512/* enum: Deliberately trigger a trap by storing to an invalid address */6513#define MC_CMD_TESTASSERT_V2_IN_STORE_TRAP 0x46514/* enum: Jump to an invalid address */6515#define MC_CMD_TESTASSERT_V2_IN_JUMP_TRAP 0x56516 6517/* MC_CMD_TESTASSERT_V2_OUT msgresponse */6518#define MC_CMD_TESTASSERT_V2_OUT_LEN 06519 6520 6521/***********************************/6522/* MC_CMD_WORKAROUND6523 * Enable/Disable a given workaround. The mcfw will return EINVAL if it doesn't6524 * understand the given workaround number - which should not be treated as a6525 * hard error by client code. This op does not imply any semantics about each6526 * workaround, that's between the driver and the mcfw on a per-workaround6527 * basis. Locks required: None. Returns: 0, EINVAL .6528 */6529#define MC_CMD_WORKAROUND 0x4a6530#undef MC_CMD_0x4a_PRIVILEGE_CTG6531 6532#define MC_CMD_0x4a_PRIVILEGE_CTG SRIOV_CTG_ADMIN6533 6534/* MC_CMD_WORKAROUND_IN msgrequest */6535#define MC_CMD_WORKAROUND_IN_LEN 86536/* The enums here must correspond with those in MC_CMD_GET_WORKAROUND. */6537#define MC_CMD_WORKAROUND_IN_TYPE_OFST 06538#define MC_CMD_WORKAROUND_IN_TYPE_LEN 46539/* enum: Bug 17230 work around. */6540#define MC_CMD_WORKAROUND_BUG17230 0x16541/* enum: Bug 35388 work around (unsafe EVQ writes). */6542#define MC_CMD_WORKAROUND_BUG35388 0x26543/* enum: Bug35017 workaround (A64 tables must be identity map) */6544#define MC_CMD_WORKAROUND_BUG35017 0x36545/* enum: Bug 41750 present (MC_CMD_TRIGGER_INTERRUPT won't work) */6546#define MC_CMD_WORKAROUND_BUG41750 0x46547/* enum: Bug 42008 present (Interrupts can overtake associated events). Caution6548 * - before adding code that queries this workaround, remember that there's6549 * released Monza firmware that doesn't understand MC_CMD_WORKAROUND_BUG42008,6550 * and will hence (incorrectly) report that the bug doesn't exist.6551 */6552#define MC_CMD_WORKAROUND_BUG42008 0x56553/* enum: Bug 26807 features present in firmware (multicast filter chaining)6554 * This feature cannot be turned on/off while there are any filters already6555 * present. The behaviour in such case depends on the acting client's privilege6556 * level. If the client has the admin privilege, then all functions that have6557 * filters installed will be FLRed and the FLR_DONE flag will be set. Otherwise6558 * the command will fail with MC_CMD_ERR_FILTERS_PRESENT.6559 */6560#define MC_CMD_WORKAROUND_BUG26807 0x66561/* enum: Bug 61265 work around (broken EVQ TMR writes). */6562#define MC_CMD_WORKAROUND_BUG61265 0x76563/* 0 = disable the workaround indicated by TYPE; any non-zero value = enable6564 * the workaround6565 */6566#define MC_CMD_WORKAROUND_IN_ENABLED_OFST 46567#define MC_CMD_WORKAROUND_IN_ENABLED_LEN 46568 6569/* MC_CMD_WORKAROUND_OUT msgresponse */6570#define MC_CMD_WORKAROUND_OUT_LEN 06571 6572/* MC_CMD_WORKAROUND_EXT_OUT msgresponse: This response format will be used6573 * when (TYPE == MC_CMD_WORKAROUND_BUG26807)6574 */6575#define MC_CMD_WORKAROUND_EXT_OUT_LEN 46576#define MC_CMD_WORKAROUND_EXT_OUT_FLAGS_OFST 06577#define MC_CMD_WORKAROUND_EXT_OUT_FLAGS_LEN 46578#define MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_OFST 06579#define MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN 06580#define MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_WIDTH 16581 6582 6583/***********************************/6584/* MC_CMD_GET_PHY_MEDIA_INFO6585 * Read media-specific data from PHY (e.g. SFP/SFP+ module ID information for6586 * SFP+ PHYs). The 'media type' can be found via GET_PHY_CFG6587 * (GET_PHY_CFG_OUT_MEDIA_TYPE); the valid 'page number' input values, and the6588 * output data, are interpreted on a per-type basis. For SFP+: PAGE=0 or 16589 * returns a 128-byte block read from module I2C address 0xA0 offset 0 or 0x80.6590 * Anything else: currently undefined. Locks required: None. Return code: 0.6591 */6592#define MC_CMD_GET_PHY_MEDIA_INFO 0x4b6593#undef MC_CMD_0x4b_PRIVILEGE_CTG6594 6595#define MC_CMD_0x4b_PRIVILEGE_CTG SRIOV_CTG_ADMIN6596 6597/* MC_CMD_GET_PHY_MEDIA_INFO_IN msgrequest */6598#define MC_CMD_GET_PHY_MEDIA_INFO_IN_LEN 46599#define MC_CMD_GET_PHY_MEDIA_INFO_IN_PAGE_OFST 06600#define MC_CMD_GET_PHY_MEDIA_INFO_IN_PAGE_LEN 46601 6602/* MC_CMD_GET_PHY_MEDIA_INFO_OUT msgresponse */6603#define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LENMIN 56604#define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LENMAX 2526605#define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LENMAX_MCDI2 10206606#define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LEN(num) (4+1*(num))6607#define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_NUM(len) (((len)-4)/1)6608/* in bytes */6609#define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATALEN_OFST 06610#define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATALEN_LEN 46611#define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_OFST 46612#define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_LEN 16613#define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_MINNUM 16614#define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_MAXNUM 2486615#define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_MAXNUM_MCDI2 10166616 6617 6618/***********************************/6619/* MC_CMD_NVRAM_TEST6620 * Test a particular NVRAM partition for valid contents (where "valid" depends6621 * on the type of partition).6622 */6623#define MC_CMD_NVRAM_TEST 0x4c6624#undef MC_CMD_0x4c_PRIVILEGE_CTG6625 6626#define MC_CMD_0x4c_PRIVILEGE_CTG SRIOV_CTG_ADMIN6627 6628/* MC_CMD_NVRAM_TEST_IN msgrequest */6629#define MC_CMD_NVRAM_TEST_IN_LEN 46630#define MC_CMD_NVRAM_TEST_IN_TYPE_OFST 06631#define MC_CMD_NVRAM_TEST_IN_TYPE_LEN 46632/* Enum values, see field(s): */6633/* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */6634 6635/* MC_CMD_NVRAM_TEST_OUT msgresponse */6636#define MC_CMD_NVRAM_TEST_OUT_LEN 46637#define MC_CMD_NVRAM_TEST_OUT_RESULT_OFST 06638#define MC_CMD_NVRAM_TEST_OUT_RESULT_LEN 46639/* enum: Passed. */6640#define MC_CMD_NVRAM_TEST_PASS 0x06641/* enum: Failed. */6642#define MC_CMD_NVRAM_TEST_FAIL 0x16643/* enum: Not supported. */6644#define MC_CMD_NVRAM_TEST_NOTSUPP 0x26645 6646 6647/***********************************/6648/* MC_CMD_MRSFP_TWEAK6649 * Read status and/or set parameters for the 'mrsfp' driver in mr_rusty builds.6650 * I2C I/O expander bits are always read; if equaliser parameters are supplied,6651 * they are configured first. Locks required: None. Return code: 0, EINVAL.6652 */6653#define MC_CMD_MRSFP_TWEAK 0x4d6654 6655/* MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG msgrequest */6656#define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_LEN 166657/* 0-6 low->high de-emph. */6658#define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_LEVEL_OFST 06659#define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_LEVEL_LEN 46660/* 0-8 low->high ref.V */6661#define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_DT_CFG_OFST 46662#define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_DT_CFG_LEN 46663/* 0-8 0-8 low->high boost */6664#define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_BOOST_OFST 86665#define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_BOOST_LEN 46666/* 0-8 low->high ref.V */6667#define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_DT_CFG_OFST 126668#define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_DT_CFG_LEN 46669 6670/* MC_CMD_MRSFP_TWEAK_IN_READ_ONLY msgrequest */6671#define MC_CMD_MRSFP_TWEAK_IN_READ_ONLY_LEN 06672 6673/* MC_CMD_MRSFP_TWEAK_OUT msgresponse */6674#define MC_CMD_MRSFP_TWEAK_OUT_LEN 126675/* input bits */6676#define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_INPUTS_OFST 06677#define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_INPUTS_LEN 46678/* output bits */6679#define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_OUTPUTS_OFST 46680#define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_OUTPUTS_LEN 46681/* direction */6682#define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_OFST 86683#define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_LEN 46684/* enum: Out. */6685#define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_OUT 0x06686/* enum: In. */6687#define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_IN 0x16688 6689 6690/***********************************/6691/* MC_CMD_SENSOR_SET_LIMS6692 * Adjusts the sensor limits. This is a warranty-voiding operation. Returns:6693 * ENOENT if the sensor specified does not exist, EINVAL if the limits are out6694 * of range.6695 */6696#define MC_CMD_SENSOR_SET_LIMS 0x4e6697#undef MC_CMD_0x4e_PRIVILEGE_CTG6698 6699#define MC_CMD_0x4e_PRIVILEGE_CTG SRIOV_CTG_INSECURE6700 6701/* MC_CMD_SENSOR_SET_LIMS_IN msgrequest */6702#define MC_CMD_SENSOR_SET_LIMS_IN_LEN 206703#define MC_CMD_SENSOR_SET_LIMS_IN_SENSOR_OFST 06704#define MC_CMD_SENSOR_SET_LIMS_IN_SENSOR_LEN 46705/* Enum values, see field(s): */6706/* MC_CMD_SENSOR_INFO/MC_CMD_SENSOR_INFO_OUT/MASK */6707/* interpretation is is sensor-specific. */6708#define MC_CMD_SENSOR_SET_LIMS_IN_LOW0_OFST 46709#define MC_CMD_SENSOR_SET_LIMS_IN_LOW0_LEN 46710/* interpretation is is sensor-specific. */6711#define MC_CMD_SENSOR_SET_LIMS_IN_HI0_OFST 86712#define MC_CMD_SENSOR_SET_LIMS_IN_HI0_LEN 46713/* interpretation is is sensor-specific. */6714#define MC_CMD_SENSOR_SET_LIMS_IN_LOW1_OFST 126715#define MC_CMD_SENSOR_SET_LIMS_IN_LOW1_LEN 46716/* interpretation is is sensor-specific. */6717#define MC_CMD_SENSOR_SET_LIMS_IN_HI1_OFST 166718#define MC_CMD_SENSOR_SET_LIMS_IN_HI1_LEN 46719 6720/* MC_CMD_SENSOR_SET_LIMS_OUT msgresponse */6721#define MC_CMD_SENSOR_SET_LIMS_OUT_LEN 06722 6723 6724/***********************************/6725/* MC_CMD_GET_RESOURCE_LIMITS6726 */6727#define MC_CMD_GET_RESOURCE_LIMITS 0x4f6728 6729/* MC_CMD_GET_RESOURCE_LIMITS_IN msgrequest */6730#define MC_CMD_GET_RESOURCE_LIMITS_IN_LEN 06731 6732/* MC_CMD_GET_RESOURCE_LIMITS_OUT msgresponse */6733#define MC_CMD_GET_RESOURCE_LIMITS_OUT_LEN 166734#define MC_CMD_GET_RESOURCE_LIMITS_OUT_BUFTBL_OFST 06735#define MC_CMD_GET_RESOURCE_LIMITS_OUT_BUFTBL_LEN 46736#define MC_CMD_GET_RESOURCE_LIMITS_OUT_EVQ_OFST 46737#define MC_CMD_GET_RESOURCE_LIMITS_OUT_EVQ_LEN 46738#define MC_CMD_GET_RESOURCE_LIMITS_OUT_RXQ_OFST 86739#define MC_CMD_GET_RESOURCE_LIMITS_OUT_RXQ_LEN 46740#define MC_CMD_GET_RESOURCE_LIMITS_OUT_TXQ_OFST 126741#define MC_CMD_GET_RESOURCE_LIMITS_OUT_TXQ_LEN 46742 6743 6744/***********************************/6745/* MC_CMD_NVRAM_PARTITIONS6746 * Reads the list of available virtual NVRAM partition types. Locks required:6747 * none. Returns: 0, EINVAL (bad type).6748 */6749#define MC_CMD_NVRAM_PARTITIONS 0x516750#undef MC_CMD_0x51_PRIVILEGE_CTG6751 6752#define MC_CMD_0x51_PRIVILEGE_CTG SRIOV_CTG_ADMIN6753 6754/* MC_CMD_NVRAM_PARTITIONS_IN msgrequest */6755#define MC_CMD_NVRAM_PARTITIONS_IN_LEN 06756 6757/* MC_CMD_NVRAM_PARTITIONS_OUT msgresponse */6758#define MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN 46759#define MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX 2526760#define MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX_MCDI2 10206761#define MC_CMD_NVRAM_PARTITIONS_OUT_LEN(num) (4+4*(num))6762#define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_NUM(len) (((len)-4)/4)6763/* total number of partitions */6764#define MC_CMD_NVRAM_PARTITIONS_OUT_NUM_PARTITIONS_OFST 06765#define MC_CMD_NVRAM_PARTITIONS_OUT_NUM_PARTITIONS_LEN 46766/* type ID code for each of NUM_PARTITIONS partitions */6767#define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_OFST 46768#define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_LEN 46769#define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_MINNUM 06770#define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_MAXNUM 626771#define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_MAXNUM_MCDI2 2546772 6773 6774/***********************************/6775/* MC_CMD_NVRAM_METADATA6776 * Reads soft metadata for a virtual NVRAM partition type. Locks required:6777 * none. Returns: 0, EINVAL (bad type).6778 */6779#define MC_CMD_NVRAM_METADATA 0x526780#undef MC_CMD_0x52_PRIVILEGE_CTG6781 6782#define MC_CMD_0x52_PRIVILEGE_CTG SRIOV_CTG_ADMIN6783 6784/* MC_CMD_NVRAM_METADATA_IN msgrequest */6785#define MC_CMD_NVRAM_METADATA_IN_LEN 46786/* Partition type ID code */6787#define MC_CMD_NVRAM_METADATA_IN_TYPE_OFST 06788#define MC_CMD_NVRAM_METADATA_IN_TYPE_LEN 46789 6790/* MC_CMD_NVRAM_METADATA_OUT msgresponse */6791#define MC_CMD_NVRAM_METADATA_OUT_LENMIN 206792#define MC_CMD_NVRAM_METADATA_OUT_LENMAX 2526793#define MC_CMD_NVRAM_METADATA_OUT_LENMAX_MCDI2 10206794#define MC_CMD_NVRAM_METADATA_OUT_LEN(num) (20+1*(num))6795#define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_NUM(len) (((len)-20)/1)6796/* Partition type ID code */6797#define MC_CMD_NVRAM_METADATA_OUT_TYPE_OFST 06798#define MC_CMD_NVRAM_METADATA_OUT_TYPE_LEN 46799#define MC_CMD_NVRAM_METADATA_OUT_FLAGS_OFST 46800#define MC_CMD_NVRAM_METADATA_OUT_FLAGS_LEN 46801#define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_OFST 46802#define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN 06803#define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_WIDTH 16804#define MC_CMD_NVRAM_METADATA_OUT_VERSION_VALID_OFST 46805#define MC_CMD_NVRAM_METADATA_OUT_VERSION_VALID_LBN 16806#define MC_CMD_NVRAM_METADATA_OUT_VERSION_VALID_WIDTH 16807#define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_VALID_OFST 46808#define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_VALID_LBN 26809#define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_VALID_WIDTH 16810/* Subtype ID code for content of this partition */6811#define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_OFST 86812#define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_LEN 46813/* 1st component of W.X.Y.Z version number for content of this partition */6814#define MC_CMD_NVRAM_METADATA_OUT_VERSION_W_OFST 126815#define MC_CMD_NVRAM_METADATA_OUT_VERSION_W_LEN 26816/* 2nd component of W.X.Y.Z version number for content of this partition */6817#define MC_CMD_NVRAM_METADATA_OUT_VERSION_X_OFST 146818#define MC_CMD_NVRAM_METADATA_OUT_VERSION_X_LEN 26819/* 3rd component of W.X.Y.Z version number for content of this partition */6820#define MC_CMD_NVRAM_METADATA_OUT_VERSION_Y_OFST 166821#define MC_CMD_NVRAM_METADATA_OUT_VERSION_Y_LEN 26822/* 4th component of W.X.Y.Z version number for content of this partition */6823#define MC_CMD_NVRAM_METADATA_OUT_VERSION_Z_OFST 186824#define MC_CMD_NVRAM_METADATA_OUT_VERSION_Z_LEN 26825/* Zero-terminated string describing the content of this partition */6826#define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_OFST 206827#define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_LEN 16828#define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_MINNUM 06829#define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_MAXNUM 2326830#define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_MAXNUM_MCDI2 10006831 6832 6833/***********************************/6834/* MC_CMD_GET_MAC_ADDRESSES6835 * Returns the base MAC, count and stride for the requesting function6836 */6837#define MC_CMD_GET_MAC_ADDRESSES 0x556838#undef MC_CMD_0x55_PRIVILEGE_CTG6839 6840#define MC_CMD_0x55_PRIVILEGE_CTG SRIOV_CTG_GENERAL6841 6842/* MC_CMD_GET_MAC_ADDRESSES_IN msgrequest */6843#define MC_CMD_GET_MAC_ADDRESSES_IN_LEN 06844 6845/* MC_CMD_GET_MAC_ADDRESSES_OUT msgresponse */6846#define MC_CMD_GET_MAC_ADDRESSES_OUT_LEN 166847/* Base MAC address */6848#define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE_OFST 06849#define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE_LEN 66850/* Padding */6851#define MC_CMD_GET_MAC_ADDRESSES_OUT_RESERVED_OFST 66852#define MC_CMD_GET_MAC_ADDRESSES_OUT_RESERVED_LEN 26853/* Number of allocated MAC addresses */6854#define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_COUNT_OFST 86855#define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_COUNT_LEN 46856/* Spacing of allocated MAC addresses */6857#define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_STRIDE_OFST 126858#define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_STRIDE_LEN 46859 6860 6861/***********************************/6862/* MC_CMD_CLP6863 * Perform a CLP related operation, see SF-110495-PS for details of CLP6864 * processing. This command has been extended to accomodate the requirements of6865 * different manufacturers which are to be found in SF-119187-TC, SF-119186-TC,6866 * SF-120509-TC and SF-117282-PS.6867 */6868#define MC_CMD_CLP 0x566869#undef MC_CMD_0x56_PRIVILEGE_CTG6870 6871#define MC_CMD_0x56_PRIVILEGE_CTG SRIOV_CTG_ADMIN6872 6873/* MC_CMD_CLP_IN msgrequest */6874#define MC_CMD_CLP_IN_LEN 46875/* Sub operation */6876#define MC_CMD_CLP_IN_OP_OFST 06877#define MC_CMD_CLP_IN_OP_LEN 46878/* enum: Return to factory default settings */6879#define MC_CMD_CLP_OP_DEFAULT 0x16880/* enum: Set MAC address */6881#define MC_CMD_CLP_OP_SET_MAC 0x26882/* enum: Get MAC address */6883#define MC_CMD_CLP_OP_GET_MAC 0x36884/* enum: Set UEFI/GPXE boot mode */6885#define MC_CMD_CLP_OP_SET_BOOT 0x46886/* enum: Get UEFI/GPXE boot mode */6887#define MC_CMD_CLP_OP_GET_BOOT 0x56888 6889/* MC_CMD_CLP_OUT msgresponse */6890#define MC_CMD_CLP_OUT_LEN 06891 6892/* MC_CMD_CLP_IN_DEFAULT msgrequest */6893#define MC_CMD_CLP_IN_DEFAULT_LEN 46894/* MC_CMD_CLP_IN_OP_OFST 0 */6895/* MC_CMD_CLP_IN_OP_LEN 4 */6896 6897/* MC_CMD_CLP_OUT_DEFAULT msgresponse */6898#define MC_CMD_CLP_OUT_DEFAULT_LEN 06899 6900/* MC_CMD_CLP_IN_SET_MAC msgrequest */6901#define MC_CMD_CLP_IN_SET_MAC_LEN 126902/* MC_CMD_CLP_IN_OP_OFST 0 */6903/* MC_CMD_CLP_IN_OP_LEN 4 */6904/* The MAC address assigned to port. A zero MAC address of 00:00:00:00:00:006905 * restores the permanent (factory-programmed) MAC address associated with the6906 * port. A non-zero MAC address persists until a PCIe reset or a power cycle.6907 */6908#define MC_CMD_CLP_IN_SET_MAC_ADDR_OFST 46909#define MC_CMD_CLP_IN_SET_MAC_ADDR_LEN 66910/* Padding */6911#define MC_CMD_CLP_IN_SET_MAC_RESERVED_OFST 106912#define MC_CMD_CLP_IN_SET_MAC_RESERVED_LEN 26913 6914/* MC_CMD_CLP_OUT_SET_MAC msgresponse */6915#define MC_CMD_CLP_OUT_SET_MAC_LEN 06916 6917/* MC_CMD_CLP_IN_SET_MAC_V2 msgrequest */6918#define MC_CMD_CLP_IN_SET_MAC_V2_LEN 166919/* MC_CMD_CLP_IN_OP_OFST 0 */6920/* MC_CMD_CLP_IN_OP_LEN 4 */6921/* The MAC address assigned to port. A zero MAC address of 00:00:00:00:00:006922 * restores the permanent (factory-programmed) MAC address associated with the6923 * port. A non-zero MAC address persists until a PCIe reset or a power cycle.6924 */6925#define MC_CMD_CLP_IN_SET_MAC_V2_ADDR_OFST 46926#define MC_CMD_CLP_IN_SET_MAC_V2_ADDR_LEN 66927/* Padding */6928#define MC_CMD_CLP_IN_SET_MAC_V2_RESERVED_OFST 106929#define MC_CMD_CLP_IN_SET_MAC_V2_RESERVED_LEN 26930#define MC_CMD_CLP_IN_SET_MAC_V2_FLAGS_OFST 126931#define MC_CMD_CLP_IN_SET_MAC_V2_FLAGS_LEN 46932#define MC_CMD_CLP_IN_SET_MAC_V2_VIRTUAL_OFST 126933#define MC_CMD_CLP_IN_SET_MAC_V2_VIRTUAL_LBN 06934#define MC_CMD_CLP_IN_SET_MAC_V2_VIRTUAL_WIDTH 16935 6936/* MC_CMD_CLP_IN_GET_MAC msgrequest */6937#define MC_CMD_CLP_IN_GET_MAC_LEN 46938/* MC_CMD_CLP_IN_OP_OFST 0 */6939/* MC_CMD_CLP_IN_OP_LEN 4 */6940 6941/* MC_CMD_CLP_IN_GET_MAC_V2 msgrequest */6942#define MC_CMD_CLP_IN_GET_MAC_V2_LEN 86943/* MC_CMD_CLP_IN_OP_OFST 0 */6944/* MC_CMD_CLP_IN_OP_LEN 4 */6945#define MC_CMD_CLP_IN_GET_MAC_V2_FLAGS_OFST 46946#define MC_CMD_CLP_IN_GET_MAC_V2_FLAGS_LEN 46947#define MC_CMD_CLP_IN_GET_MAC_V2_PERMANENT_OFST 46948#define MC_CMD_CLP_IN_GET_MAC_V2_PERMANENT_LBN 06949#define MC_CMD_CLP_IN_GET_MAC_V2_PERMANENT_WIDTH 16950 6951/* MC_CMD_CLP_OUT_GET_MAC msgresponse */6952#define MC_CMD_CLP_OUT_GET_MAC_LEN 86953/* MAC address assigned to port */6954#define MC_CMD_CLP_OUT_GET_MAC_ADDR_OFST 06955#define MC_CMD_CLP_OUT_GET_MAC_ADDR_LEN 66956/* Padding */6957#define MC_CMD_CLP_OUT_GET_MAC_RESERVED_OFST 66958#define MC_CMD_CLP_OUT_GET_MAC_RESERVED_LEN 26959 6960/* MC_CMD_CLP_IN_SET_BOOT msgrequest */6961#define MC_CMD_CLP_IN_SET_BOOT_LEN 56962/* MC_CMD_CLP_IN_OP_OFST 0 */6963/* MC_CMD_CLP_IN_OP_LEN 4 */6964/* Boot flag */6965#define MC_CMD_CLP_IN_SET_BOOT_FLAG_OFST 46966#define MC_CMD_CLP_IN_SET_BOOT_FLAG_LEN 16967 6968/* MC_CMD_CLP_OUT_SET_BOOT msgresponse */6969#define MC_CMD_CLP_OUT_SET_BOOT_LEN 06970 6971/* MC_CMD_CLP_IN_GET_BOOT msgrequest */6972#define MC_CMD_CLP_IN_GET_BOOT_LEN 46973/* MC_CMD_CLP_IN_OP_OFST 0 */6974/* MC_CMD_CLP_IN_OP_LEN 4 */6975 6976/* MC_CMD_CLP_OUT_GET_BOOT msgresponse */6977#define MC_CMD_CLP_OUT_GET_BOOT_LEN 46978/* Boot flag */6979#define MC_CMD_CLP_OUT_GET_BOOT_FLAG_OFST 06980#define MC_CMD_CLP_OUT_GET_BOOT_FLAG_LEN 16981/* Padding */6982#define MC_CMD_CLP_OUT_GET_BOOT_RESERVED_OFST 16983#define MC_CMD_CLP_OUT_GET_BOOT_RESERVED_LEN 36984 6985 6986/***********************************/6987/* MC_CMD_MUM6988 * Perform a MUM operation6989 */6990#define MC_CMD_MUM 0x576991#undef MC_CMD_0x57_PRIVILEGE_CTG6992 6993#define MC_CMD_0x57_PRIVILEGE_CTG SRIOV_CTG_INSECURE6994 6995/* MC_CMD_MUM_IN msgrequest */6996#define MC_CMD_MUM_IN_LEN 46997#define MC_CMD_MUM_IN_OP_HDR_OFST 06998#define MC_CMD_MUM_IN_OP_HDR_LEN 46999#define MC_CMD_MUM_IN_OP_OFST 07000#define MC_CMD_MUM_IN_OP_LBN 07001#define MC_CMD_MUM_IN_OP_WIDTH 87002/* enum: NULL MCDI command to MUM */7003#define MC_CMD_MUM_OP_NULL 0x17004/* enum: Get MUM version */7005#define MC_CMD_MUM_OP_GET_VERSION 0x27006/* enum: Issue raw I2C command to MUM */7007#define MC_CMD_MUM_OP_RAW_CMD 0x37008/* enum: Read from registers on devices connected to MUM. */7009#define MC_CMD_MUM_OP_READ 0x47010/* enum: Write to registers on devices connected to MUM. */7011#define MC_CMD_MUM_OP_WRITE 0x57012/* enum: Control UART logging. */7013#define MC_CMD_MUM_OP_LOG 0x67014/* enum: Operations on MUM GPIO lines */7015#define MC_CMD_MUM_OP_GPIO 0x77016/* enum: Get sensor readings from MUM */7017#define MC_CMD_MUM_OP_READ_SENSORS 0x87018/* enum: Initiate clock programming on the MUM */7019#define MC_CMD_MUM_OP_PROGRAM_CLOCKS 0x97020/* enum: Initiate FPGA load from flash on the MUM */7021#define MC_CMD_MUM_OP_FPGA_LOAD 0xa7022/* enum: Request sensor reading from MUM ADC resulting from earlier request via7023 * MUM ATB7024 */7025#define MC_CMD_MUM_OP_READ_ATB_SENSOR 0xb7026/* enum: Send commands relating to the QSFP ports via the MUM for PHY7027 * operations7028 */7029#define MC_CMD_MUM_OP_QSFP 0xc7030/* enum: Request discrete and SODIMM DDR info (type, size, speed grade, voltage7031 * level) from MUM7032 */7033#define MC_CMD_MUM_OP_READ_DDR_INFO 0xd7034 7035/* MC_CMD_MUM_IN_NULL msgrequest */7036#define MC_CMD_MUM_IN_NULL_LEN 47037/* MUM cmd header */7038#define MC_CMD_MUM_IN_CMD_OFST 07039#define MC_CMD_MUM_IN_CMD_LEN 47040 7041/* MC_CMD_MUM_IN_GET_VERSION msgrequest */7042#define MC_CMD_MUM_IN_GET_VERSION_LEN 47043/* MUM cmd header */7044/* MC_CMD_MUM_IN_CMD_OFST 0 */7045/* MC_CMD_MUM_IN_CMD_LEN 4 */7046 7047/* MC_CMD_MUM_IN_READ msgrequest */7048#define MC_CMD_MUM_IN_READ_LEN 167049/* MUM cmd header */7050/* MC_CMD_MUM_IN_CMD_OFST 0 */7051/* MC_CMD_MUM_IN_CMD_LEN 4 */7052/* ID of (device connected to MUM) to read from registers of */7053#define MC_CMD_MUM_IN_READ_DEVICE_OFST 47054#define MC_CMD_MUM_IN_READ_DEVICE_LEN 47055/* enum: Hittite HMC1035 clock generator on Sorrento board */7056#define MC_CMD_MUM_DEV_HITTITE 0x17057/* enum: Hittite HMC1035 clock generator for NIC-side on Sorrento board */7058#define MC_CMD_MUM_DEV_HITTITE_NIC 0x27059/* 32-bit address to read from */7060#define MC_CMD_MUM_IN_READ_ADDR_OFST 87061#define MC_CMD_MUM_IN_READ_ADDR_LEN 47062/* Number of words to read. */7063#define MC_CMD_MUM_IN_READ_NUMWORDS_OFST 127064#define MC_CMD_MUM_IN_READ_NUMWORDS_LEN 47065 7066/* MC_CMD_MUM_IN_WRITE msgrequest */7067#define MC_CMD_MUM_IN_WRITE_LENMIN 167068#define MC_CMD_MUM_IN_WRITE_LENMAX 2527069#define MC_CMD_MUM_IN_WRITE_LENMAX_MCDI2 10207070#define MC_CMD_MUM_IN_WRITE_LEN(num) (12+4*(num))7071#define MC_CMD_MUM_IN_WRITE_BUFFER_NUM(len) (((len)-12)/4)7072/* MUM cmd header */7073/* MC_CMD_MUM_IN_CMD_OFST 0 */7074/* MC_CMD_MUM_IN_CMD_LEN 4 */7075/* ID of (device connected to MUM) to write to registers of */7076#define MC_CMD_MUM_IN_WRITE_DEVICE_OFST 47077#define MC_CMD_MUM_IN_WRITE_DEVICE_LEN 47078/* enum: Hittite HMC1035 clock generator on Sorrento board */7079/* MC_CMD_MUM_DEV_HITTITE 0x1 */7080/* 32-bit address to write to */7081#define MC_CMD_MUM_IN_WRITE_ADDR_OFST 87082#define MC_CMD_MUM_IN_WRITE_ADDR_LEN 47083/* Words to write */7084#define MC_CMD_MUM_IN_WRITE_BUFFER_OFST 127085#define MC_CMD_MUM_IN_WRITE_BUFFER_LEN 47086#define MC_CMD_MUM_IN_WRITE_BUFFER_MINNUM 17087#define MC_CMD_MUM_IN_WRITE_BUFFER_MAXNUM 607088#define MC_CMD_MUM_IN_WRITE_BUFFER_MAXNUM_MCDI2 2527089 7090/* MC_CMD_MUM_IN_RAW_CMD msgrequest */7091#define MC_CMD_MUM_IN_RAW_CMD_LENMIN 177092#define MC_CMD_MUM_IN_RAW_CMD_LENMAX 2527093#define MC_CMD_MUM_IN_RAW_CMD_LENMAX_MCDI2 10207094#define MC_CMD_MUM_IN_RAW_CMD_LEN(num) (16+1*(num))7095#define MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_NUM(len) (((len)-16)/1)7096/* MUM cmd header */7097/* MC_CMD_MUM_IN_CMD_OFST 0 */7098/* MC_CMD_MUM_IN_CMD_LEN 4 */7099/* MUM I2C cmd code */7100#define MC_CMD_MUM_IN_RAW_CMD_CMD_CODE_OFST 47101#define MC_CMD_MUM_IN_RAW_CMD_CMD_CODE_LEN 47102/* Number of bytes to write */7103#define MC_CMD_MUM_IN_RAW_CMD_NUM_WRITE_OFST 87104#define MC_CMD_MUM_IN_RAW_CMD_NUM_WRITE_LEN 47105/* Number of bytes to read */7106#define MC_CMD_MUM_IN_RAW_CMD_NUM_READ_OFST 127107#define MC_CMD_MUM_IN_RAW_CMD_NUM_READ_LEN 47108/* Bytes to write */7109#define MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_OFST 167110#define MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_LEN 17111#define MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_MINNUM 17112#define MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_MAXNUM 2367113#define MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_MAXNUM_MCDI2 10047114 7115/* MC_CMD_MUM_IN_LOG msgrequest */7116#define MC_CMD_MUM_IN_LOG_LEN 87117/* MUM cmd header */7118/* MC_CMD_MUM_IN_CMD_OFST 0 */7119/* MC_CMD_MUM_IN_CMD_LEN 4 */7120#define MC_CMD_MUM_IN_LOG_OP_OFST 47121#define MC_CMD_MUM_IN_LOG_OP_LEN 47122#define MC_CMD_MUM_IN_LOG_OP_UART 0x1 /* enum */7123 7124/* MC_CMD_MUM_IN_LOG_OP_UART msgrequest */7125#define MC_CMD_MUM_IN_LOG_OP_UART_LEN 127126/* MC_CMD_MUM_IN_CMD_OFST 0 */7127/* MC_CMD_MUM_IN_CMD_LEN 4 */7128/* MC_CMD_MUM_IN_LOG_OP_OFST 4 */7129/* MC_CMD_MUM_IN_LOG_OP_LEN 4 */7130/* Enable/disable debug output to UART */7131#define MC_CMD_MUM_IN_LOG_OP_UART_ENABLE_OFST 87132#define MC_CMD_MUM_IN_LOG_OP_UART_ENABLE_LEN 47133 7134/* MC_CMD_MUM_IN_GPIO msgrequest */7135#define MC_CMD_MUM_IN_GPIO_LEN 87136/* MUM cmd header */7137/* MC_CMD_MUM_IN_CMD_OFST 0 */7138/* MC_CMD_MUM_IN_CMD_LEN 4 */7139#define MC_CMD_MUM_IN_GPIO_HDR_OFST 47140#define MC_CMD_MUM_IN_GPIO_HDR_LEN 47141#define MC_CMD_MUM_IN_GPIO_OPCODE_OFST 47142#define MC_CMD_MUM_IN_GPIO_OPCODE_LBN 07143#define MC_CMD_MUM_IN_GPIO_OPCODE_WIDTH 87144#define MC_CMD_MUM_IN_GPIO_IN_READ 0x0 /* enum */7145#define MC_CMD_MUM_IN_GPIO_OUT_WRITE 0x1 /* enum */7146#define MC_CMD_MUM_IN_GPIO_OUT_READ 0x2 /* enum */7147#define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE 0x3 /* enum */7148#define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ 0x4 /* enum */7149#define MC_CMD_MUM_IN_GPIO_OP 0x5 /* enum */7150 7151/* MC_CMD_MUM_IN_GPIO_IN_READ msgrequest */7152#define MC_CMD_MUM_IN_GPIO_IN_READ_LEN 87153/* MC_CMD_MUM_IN_CMD_OFST 0 */7154/* MC_CMD_MUM_IN_CMD_LEN 4 */7155#define MC_CMD_MUM_IN_GPIO_IN_READ_HDR_OFST 47156#define MC_CMD_MUM_IN_GPIO_IN_READ_HDR_LEN 47157 7158/* MC_CMD_MUM_IN_GPIO_OUT_WRITE msgrequest */7159#define MC_CMD_MUM_IN_GPIO_OUT_WRITE_LEN 167160/* MC_CMD_MUM_IN_CMD_OFST 0 */7161/* MC_CMD_MUM_IN_CMD_LEN 4 */7162#define MC_CMD_MUM_IN_GPIO_OUT_WRITE_HDR_OFST 47163#define MC_CMD_MUM_IN_GPIO_OUT_WRITE_HDR_LEN 47164/* The first 32-bit word to be written to the GPIO OUT register. */7165#define MC_CMD_MUM_IN_GPIO_OUT_WRITE_GPIOMASK1_OFST 87166#define MC_CMD_MUM_IN_GPIO_OUT_WRITE_GPIOMASK1_LEN 47167/* The second 32-bit word to be written to the GPIO OUT register. */7168#define MC_CMD_MUM_IN_GPIO_OUT_WRITE_GPIOMASK2_OFST 127169#define MC_CMD_MUM_IN_GPIO_OUT_WRITE_GPIOMASK2_LEN 47170 7171/* MC_CMD_MUM_IN_GPIO_OUT_READ msgrequest */7172#define MC_CMD_MUM_IN_GPIO_OUT_READ_LEN 87173/* MC_CMD_MUM_IN_CMD_OFST 0 */7174/* MC_CMD_MUM_IN_CMD_LEN 4 */7175#define MC_CMD_MUM_IN_GPIO_OUT_READ_HDR_OFST 47176#define MC_CMD_MUM_IN_GPIO_OUT_READ_HDR_LEN 47177 7178/* MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE msgrequest */7179#define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_LEN 167180/* MC_CMD_MUM_IN_CMD_OFST 0 */7181/* MC_CMD_MUM_IN_CMD_LEN 4 */7182#define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_HDR_OFST 47183#define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_HDR_LEN 47184/* The first 32-bit word to be written to the GPIO OUT ENABLE register. */7185#define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_GPIOMASK1_OFST 87186#define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_GPIOMASK1_LEN 47187/* The second 32-bit word to be written to the GPIO OUT ENABLE register. */7188#define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_GPIOMASK2_OFST 127189#define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_GPIOMASK2_LEN 47190 7191/* MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ msgrequest */7192#define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ_LEN 87193/* MC_CMD_MUM_IN_CMD_OFST 0 */7194/* MC_CMD_MUM_IN_CMD_LEN 4 */7195#define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ_HDR_OFST 47196#define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ_HDR_LEN 47197 7198/* MC_CMD_MUM_IN_GPIO_OP msgrequest */7199#define MC_CMD_MUM_IN_GPIO_OP_LEN 87200/* MC_CMD_MUM_IN_CMD_OFST 0 */7201/* MC_CMD_MUM_IN_CMD_LEN 4 */7202#define MC_CMD_MUM_IN_GPIO_OP_HDR_OFST 47203#define MC_CMD_MUM_IN_GPIO_OP_HDR_LEN 47204#define MC_CMD_MUM_IN_GPIO_OP_BITWISE_OP_OFST 47205#define MC_CMD_MUM_IN_GPIO_OP_BITWISE_OP_LBN 87206#define MC_CMD_MUM_IN_GPIO_OP_BITWISE_OP_WIDTH 87207#define MC_CMD_MUM_IN_GPIO_OP_OUT_READ 0x0 /* enum */7208#define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE 0x1 /* enum */7209#define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG 0x2 /* enum */7210#define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE 0x3 /* enum */7211#define MC_CMD_MUM_IN_GPIO_OP_GPIO_NUMBER_OFST 47212#define MC_CMD_MUM_IN_GPIO_OP_GPIO_NUMBER_LBN 167213#define MC_CMD_MUM_IN_GPIO_OP_GPIO_NUMBER_WIDTH 87214 7215/* MC_CMD_MUM_IN_GPIO_OP_OUT_READ msgrequest */7216#define MC_CMD_MUM_IN_GPIO_OP_OUT_READ_LEN 87217/* MC_CMD_MUM_IN_CMD_OFST 0 */7218/* MC_CMD_MUM_IN_CMD_LEN 4 */7219#define MC_CMD_MUM_IN_GPIO_OP_OUT_READ_HDR_OFST 47220#define MC_CMD_MUM_IN_GPIO_OP_OUT_READ_HDR_LEN 47221 7222/* MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE msgrequest */7223#define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_LEN 87224/* MC_CMD_MUM_IN_CMD_OFST 0 */7225/* MC_CMD_MUM_IN_CMD_LEN 4 */7226#define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_HDR_OFST 47227#define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_HDR_LEN 47228#define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_WRITEBIT_OFST 47229#define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_WRITEBIT_LBN 247230#define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_WRITEBIT_WIDTH 87231 7232/* MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG msgrequest */7233#define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_LEN 87234/* MC_CMD_MUM_IN_CMD_OFST 0 */7235/* MC_CMD_MUM_IN_CMD_LEN 4 */7236#define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_HDR_OFST 47237#define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_HDR_LEN 47238#define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_CFG_OFST 47239#define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_CFG_LBN 247240#define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_CFG_WIDTH 87241 7242/* MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE msgrequest */7243#define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_LEN 87244/* MC_CMD_MUM_IN_CMD_OFST 0 */7245/* MC_CMD_MUM_IN_CMD_LEN 4 */7246#define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_HDR_OFST 47247#define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_HDR_LEN 47248#define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_ENABLEBIT_OFST 47249#define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_ENABLEBIT_LBN 247250#define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_ENABLEBIT_WIDTH 87251 7252/* MC_CMD_MUM_IN_READ_SENSORS msgrequest */7253#define MC_CMD_MUM_IN_READ_SENSORS_LEN 87254/* MUM cmd header */7255/* MC_CMD_MUM_IN_CMD_OFST 0 */7256/* MC_CMD_MUM_IN_CMD_LEN 4 */7257#define MC_CMD_MUM_IN_READ_SENSORS_PARAMS_OFST 47258#define MC_CMD_MUM_IN_READ_SENSORS_PARAMS_LEN 47259#define MC_CMD_MUM_IN_READ_SENSORS_SENSOR_ID_OFST 47260#define MC_CMD_MUM_IN_READ_SENSORS_SENSOR_ID_LBN 07261#define MC_CMD_MUM_IN_READ_SENSORS_SENSOR_ID_WIDTH 87262#define MC_CMD_MUM_IN_READ_SENSORS_NUM_SENSORS_OFST 47263#define MC_CMD_MUM_IN_READ_SENSORS_NUM_SENSORS_LBN 87264#define MC_CMD_MUM_IN_READ_SENSORS_NUM_SENSORS_WIDTH 87265 7266/* MC_CMD_MUM_IN_PROGRAM_CLOCKS msgrequest */7267#define MC_CMD_MUM_IN_PROGRAM_CLOCKS_LEN 127268/* MUM cmd header */7269/* MC_CMD_MUM_IN_CMD_OFST 0 */7270/* MC_CMD_MUM_IN_CMD_LEN 4 */7271/* Bit-mask of clocks to be programmed */7272#define MC_CMD_MUM_IN_PROGRAM_CLOCKS_MASK_OFST 47273#define MC_CMD_MUM_IN_PROGRAM_CLOCKS_MASK_LEN 47274#define MC_CMD_MUM_CLOCK_ID_FPGA 0x0 /* enum */7275#define MC_CMD_MUM_CLOCK_ID_DDR 0x1 /* enum */7276#define MC_CMD_MUM_CLOCK_ID_NIC 0x2 /* enum */7277/* Control flags for clock programming */7278#define MC_CMD_MUM_IN_PROGRAM_CLOCKS_FLAGS_OFST 87279#define MC_CMD_MUM_IN_PROGRAM_CLOCKS_FLAGS_LEN 47280#define MC_CMD_MUM_IN_PROGRAM_CLOCKS_OVERCLOCK_110_OFST 87281#define MC_CMD_MUM_IN_PROGRAM_CLOCKS_OVERCLOCK_110_LBN 07282#define MC_CMD_MUM_IN_PROGRAM_CLOCKS_OVERCLOCK_110_WIDTH 17283#define MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_NIC_FROM_FPGA_OFST 87284#define MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_NIC_FROM_FPGA_LBN 17285#define MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_NIC_FROM_FPGA_WIDTH 17286#define MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_REF_FROM_XO_OFST 87287#define MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_REF_FROM_XO_LBN 27288#define MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_REF_FROM_XO_WIDTH 17289 7290/* MC_CMD_MUM_IN_FPGA_LOAD msgrequest */7291#define MC_CMD_MUM_IN_FPGA_LOAD_LEN 87292/* MUM cmd header */7293/* MC_CMD_MUM_IN_CMD_OFST 0 */7294/* MC_CMD_MUM_IN_CMD_LEN 4 */7295/* Enable/Disable FPGA config from flash */7296#define MC_CMD_MUM_IN_FPGA_LOAD_ENABLE_OFST 47297#define MC_CMD_MUM_IN_FPGA_LOAD_ENABLE_LEN 47298 7299/* MC_CMD_MUM_IN_READ_ATB_SENSOR msgrequest */7300#define MC_CMD_MUM_IN_READ_ATB_SENSOR_LEN 47301/* MUM cmd header */7302/* MC_CMD_MUM_IN_CMD_OFST 0 */7303/* MC_CMD_MUM_IN_CMD_LEN 4 */7304 7305/* MC_CMD_MUM_IN_QSFP msgrequest */7306#define MC_CMD_MUM_IN_QSFP_LEN 127307/* MUM cmd header */7308/* MC_CMD_MUM_IN_CMD_OFST 0 */7309/* MC_CMD_MUM_IN_CMD_LEN 4 */7310#define MC_CMD_MUM_IN_QSFP_HDR_OFST 47311#define MC_CMD_MUM_IN_QSFP_HDR_LEN 47312#define MC_CMD_MUM_IN_QSFP_OPCODE_OFST 47313#define MC_CMD_MUM_IN_QSFP_OPCODE_LBN 07314#define MC_CMD_MUM_IN_QSFP_OPCODE_WIDTH 47315#define MC_CMD_MUM_IN_QSFP_INIT 0x0 /* enum */7316#define MC_CMD_MUM_IN_QSFP_RECONFIGURE 0x1 /* enum */7317#define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP 0x2 /* enum */7318#define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO 0x3 /* enum */7319#define MC_CMD_MUM_IN_QSFP_FILL_STATS 0x4 /* enum */7320#define MC_CMD_MUM_IN_QSFP_POLL_BIST 0x5 /* enum */7321#define MC_CMD_MUM_IN_QSFP_IDX_OFST 87322#define MC_CMD_MUM_IN_QSFP_IDX_LEN 47323 7324/* MC_CMD_MUM_IN_QSFP_INIT msgrequest */7325#define MC_CMD_MUM_IN_QSFP_INIT_LEN 167326/* MC_CMD_MUM_IN_CMD_OFST 0 */7327/* MC_CMD_MUM_IN_CMD_LEN 4 */7328#define MC_CMD_MUM_IN_QSFP_INIT_HDR_OFST 47329#define MC_CMD_MUM_IN_QSFP_INIT_HDR_LEN 47330#define MC_CMD_MUM_IN_QSFP_INIT_IDX_OFST 87331#define MC_CMD_MUM_IN_QSFP_INIT_IDX_LEN 47332#define MC_CMD_MUM_IN_QSFP_INIT_CAGE_OFST 127333#define MC_CMD_MUM_IN_QSFP_INIT_CAGE_LEN 47334 7335/* MC_CMD_MUM_IN_QSFP_RECONFIGURE msgrequest */7336#define MC_CMD_MUM_IN_QSFP_RECONFIGURE_LEN 247337/* MC_CMD_MUM_IN_CMD_OFST 0 */7338/* MC_CMD_MUM_IN_CMD_LEN 4 */7339#define MC_CMD_MUM_IN_QSFP_RECONFIGURE_HDR_OFST 47340#define MC_CMD_MUM_IN_QSFP_RECONFIGURE_HDR_LEN 47341#define MC_CMD_MUM_IN_QSFP_RECONFIGURE_IDX_OFST 87342#define MC_CMD_MUM_IN_QSFP_RECONFIGURE_IDX_LEN 47343#define MC_CMD_MUM_IN_QSFP_RECONFIGURE_TX_DISABLE_OFST 127344#define MC_CMD_MUM_IN_QSFP_RECONFIGURE_TX_DISABLE_LEN 47345#define MC_CMD_MUM_IN_QSFP_RECONFIGURE_PORT_LANES_OFST 167346#define MC_CMD_MUM_IN_QSFP_RECONFIGURE_PORT_LANES_LEN 47347#define MC_CMD_MUM_IN_QSFP_RECONFIGURE_PORT_LINK_SPEED_OFST 207348#define MC_CMD_MUM_IN_QSFP_RECONFIGURE_PORT_LINK_SPEED_LEN 47349 7350/* MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP msgrequest */7351#define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_LEN 127352/* MC_CMD_MUM_IN_CMD_OFST 0 */7353/* MC_CMD_MUM_IN_CMD_LEN 4 */7354#define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_HDR_OFST 47355#define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_HDR_LEN 47356#define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_IDX_OFST 87357#define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_IDX_LEN 47358 7359/* MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO msgrequest */7360#define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_LEN 167361/* MC_CMD_MUM_IN_CMD_OFST 0 */7362/* MC_CMD_MUM_IN_CMD_LEN 4 */7363#define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_HDR_OFST 47364#define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_HDR_LEN 47365#define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_IDX_OFST 87366#define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_IDX_LEN 47367#define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_PAGE_OFST 127368#define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_PAGE_LEN 47369 7370/* MC_CMD_MUM_IN_QSFP_FILL_STATS msgrequest */7371#define MC_CMD_MUM_IN_QSFP_FILL_STATS_LEN 127372/* MC_CMD_MUM_IN_CMD_OFST 0 */7373/* MC_CMD_MUM_IN_CMD_LEN 4 */7374#define MC_CMD_MUM_IN_QSFP_FILL_STATS_HDR_OFST 47375#define MC_CMD_MUM_IN_QSFP_FILL_STATS_HDR_LEN 47376#define MC_CMD_MUM_IN_QSFP_FILL_STATS_IDX_OFST 87377#define MC_CMD_MUM_IN_QSFP_FILL_STATS_IDX_LEN 47378 7379/* MC_CMD_MUM_IN_QSFP_POLL_BIST msgrequest */7380#define MC_CMD_MUM_IN_QSFP_POLL_BIST_LEN 127381/* MC_CMD_MUM_IN_CMD_OFST 0 */7382/* MC_CMD_MUM_IN_CMD_LEN 4 */7383#define MC_CMD_MUM_IN_QSFP_POLL_BIST_HDR_OFST 47384#define MC_CMD_MUM_IN_QSFP_POLL_BIST_HDR_LEN 47385#define MC_CMD_MUM_IN_QSFP_POLL_BIST_IDX_OFST 87386#define MC_CMD_MUM_IN_QSFP_POLL_BIST_IDX_LEN 47387 7388/* MC_CMD_MUM_IN_READ_DDR_INFO msgrequest */7389#define MC_CMD_MUM_IN_READ_DDR_INFO_LEN 47390/* MUM cmd header */7391/* MC_CMD_MUM_IN_CMD_OFST 0 */7392/* MC_CMD_MUM_IN_CMD_LEN 4 */7393 7394/* MC_CMD_MUM_OUT msgresponse */7395#define MC_CMD_MUM_OUT_LEN 07396 7397/* MC_CMD_MUM_OUT_NULL msgresponse */7398#define MC_CMD_MUM_OUT_NULL_LEN 07399 7400/* MC_CMD_MUM_OUT_GET_VERSION msgresponse */7401#define MC_CMD_MUM_OUT_GET_VERSION_LEN 127402#define MC_CMD_MUM_OUT_GET_VERSION_FIRMWARE_OFST 07403#define MC_CMD_MUM_OUT_GET_VERSION_FIRMWARE_LEN 47404#define MC_CMD_MUM_OUT_GET_VERSION_VERSION_OFST 47405#define MC_CMD_MUM_OUT_GET_VERSION_VERSION_LEN 87406#define MC_CMD_MUM_OUT_GET_VERSION_VERSION_LO_OFST 47407#define MC_CMD_MUM_OUT_GET_VERSION_VERSION_HI_OFST 87408 7409/* MC_CMD_MUM_OUT_RAW_CMD msgresponse */7410#define MC_CMD_MUM_OUT_RAW_CMD_LENMIN 17411#define MC_CMD_MUM_OUT_RAW_CMD_LENMAX 2527412#define MC_CMD_MUM_OUT_RAW_CMD_LENMAX_MCDI2 10207413#define MC_CMD_MUM_OUT_RAW_CMD_LEN(num) (0+1*(num))7414#define MC_CMD_MUM_OUT_RAW_CMD_DATA_NUM(len) (((len)-0)/1)7415/* returned data */7416#define MC_CMD_MUM_OUT_RAW_CMD_DATA_OFST 07417#define MC_CMD_MUM_OUT_RAW_CMD_DATA_LEN 17418#define MC_CMD_MUM_OUT_RAW_CMD_DATA_MINNUM 17419#define MC_CMD_MUM_OUT_RAW_CMD_DATA_MAXNUM 2527420#define MC_CMD_MUM_OUT_RAW_CMD_DATA_MAXNUM_MCDI2 10207421 7422/* MC_CMD_MUM_OUT_READ msgresponse */7423#define MC_CMD_MUM_OUT_READ_LENMIN 47424#define MC_CMD_MUM_OUT_READ_LENMAX 2527425#define MC_CMD_MUM_OUT_READ_LENMAX_MCDI2 10207426#define MC_CMD_MUM_OUT_READ_LEN(num) (0+4*(num))7427#define MC_CMD_MUM_OUT_READ_BUFFER_NUM(len) (((len)-0)/4)7428#define MC_CMD_MUM_OUT_READ_BUFFER_OFST 07429#define MC_CMD_MUM_OUT_READ_BUFFER_LEN 47430#define MC_CMD_MUM_OUT_READ_BUFFER_MINNUM 17431#define MC_CMD_MUM_OUT_READ_BUFFER_MAXNUM 637432#define MC_CMD_MUM_OUT_READ_BUFFER_MAXNUM_MCDI2 2557433 7434/* MC_CMD_MUM_OUT_WRITE msgresponse */7435#define MC_CMD_MUM_OUT_WRITE_LEN 07436 7437/* MC_CMD_MUM_OUT_LOG msgresponse */7438#define MC_CMD_MUM_OUT_LOG_LEN 07439 7440/* MC_CMD_MUM_OUT_LOG_OP_UART msgresponse */7441#define MC_CMD_MUM_OUT_LOG_OP_UART_LEN 07442 7443/* MC_CMD_MUM_OUT_GPIO_IN_READ msgresponse */7444#define MC_CMD_MUM_OUT_GPIO_IN_READ_LEN 87445/* The first 32-bit word read from the GPIO IN register. */7446#define MC_CMD_MUM_OUT_GPIO_IN_READ_GPIOMASK1_OFST 07447#define MC_CMD_MUM_OUT_GPIO_IN_READ_GPIOMASK1_LEN 47448/* The second 32-bit word read from the GPIO IN register. */7449#define MC_CMD_MUM_OUT_GPIO_IN_READ_GPIOMASK2_OFST 47450#define MC_CMD_MUM_OUT_GPIO_IN_READ_GPIOMASK2_LEN 47451 7452/* MC_CMD_MUM_OUT_GPIO_OUT_WRITE msgresponse */7453#define MC_CMD_MUM_OUT_GPIO_OUT_WRITE_LEN 07454 7455/* MC_CMD_MUM_OUT_GPIO_OUT_READ msgresponse */7456#define MC_CMD_MUM_OUT_GPIO_OUT_READ_LEN 87457/* The first 32-bit word read from the GPIO OUT register. */7458#define MC_CMD_MUM_OUT_GPIO_OUT_READ_GPIOMASK1_OFST 07459#define MC_CMD_MUM_OUT_GPIO_OUT_READ_GPIOMASK1_LEN 47460/* The second 32-bit word read from the GPIO OUT register. */7461#define MC_CMD_MUM_OUT_GPIO_OUT_READ_GPIOMASK2_OFST 47462#define MC_CMD_MUM_OUT_GPIO_OUT_READ_GPIOMASK2_LEN 47463 7464/* MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_WRITE msgresponse */7465#define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_WRITE_LEN 07466 7467/* MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ msgresponse */7468#define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_LEN 87469#define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_GPIOMASK1_OFST 07470#define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_GPIOMASK1_LEN 47471#define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_GPIOMASK2_OFST 47472#define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_GPIOMASK2_LEN 47473 7474/* MC_CMD_MUM_OUT_GPIO_OP_OUT_READ msgresponse */7475#define MC_CMD_MUM_OUT_GPIO_OP_OUT_READ_LEN 47476#define MC_CMD_MUM_OUT_GPIO_OP_OUT_READ_BIT_READ_OFST 07477#define MC_CMD_MUM_OUT_GPIO_OP_OUT_READ_BIT_READ_LEN 47478 7479/* MC_CMD_MUM_OUT_GPIO_OP_OUT_WRITE msgresponse */7480#define MC_CMD_MUM_OUT_GPIO_OP_OUT_WRITE_LEN 07481 7482/* MC_CMD_MUM_OUT_GPIO_OP_OUT_CONFIG msgresponse */7483#define MC_CMD_MUM_OUT_GPIO_OP_OUT_CONFIG_LEN 07484 7485/* MC_CMD_MUM_OUT_GPIO_OP_OUT_ENABLE msgresponse */7486#define MC_CMD_MUM_OUT_GPIO_OP_OUT_ENABLE_LEN 07487 7488/* MC_CMD_MUM_OUT_READ_SENSORS msgresponse */7489#define MC_CMD_MUM_OUT_READ_SENSORS_LENMIN 47490#define MC_CMD_MUM_OUT_READ_SENSORS_LENMAX 2527491#define MC_CMD_MUM_OUT_READ_SENSORS_LENMAX_MCDI2 10207492#define MC_CMD_MUM_OUT_READ_SENSORS_LEN(num) (0+4*(num))7493#define MC_CMD_MUM_OUT_READ_SENSORS_DATA_NUM(len) (((len)-0)/4)7494#define MC_CMD_MUM_OUT_READ_SENSORS_DATA_OFST 07495#define MC_CMD_MUM_OUT_READ_SENSORS_DATA_LEN 47496#define MC_CMD_MUM_OUT_READ_SENSORS_DATA_MINNUM 17497#define MC_CMD_MUM_OUT_READ_SENSORS_DATA_MAXNUM 637498#define MC_CMD_MUM_OUT_READ_SENSORS_DATA_MAXNUM_MCDI2 2557499#define MC_CMD_MUM_OUT_READ_SENSORS_READING_OFST 07500#define MC_CMD_MUM_OUT_READ_SENSORS_READING_LBN 07501#define MC_CMD_MUM_OUT_READ_SENSORS_READING_WIDTH 167502#define MC_CMD_MUM_OUT_READ_SENSORS_STATE_OFST 07503#define MC_CMD_MUM_OUT_READ_SENSORS_STATE_LBN 167504#define MC_CMD_MUM_OUT_READ_SENSORS_STATE_WIDTH 87505#define MC_CMD_MUM_OUT_READ_SENSORS_TYPE_OFST 07506#define MC_CMD_MUM_OUT_READ_SENSORS_TYPE_LBN 247507#define MC_CMD_MUM_OUT_READ_SENSORS_TYPE_WIDTH 87508 7509/* MC_CMD_MUM_OUT_PROGRAM_CLOCKS msgresponse */7510#define MC_CMD_MUM_OUT_PROGRAM_CLOCKS_LEN 47511#define MC_CMD_MUM_OUT_PROGRAM_CLOCKS_OK_MASK_OFST 07512#define MC_CMD_MUM_OUT_PROGRAM_CLOCKS_OK_MASK_LEN 47513 7514/* MC_CMD_MUM_OUT_FPGA_LOAD msgresponse */7515#define MC_CMD_MUM_OUT_FPGA_LOAD_LEN 07516 7517/* MC_CMD_MUM_OUT_READ_ATB_SENSOR msgresponse */7518#define MC_CMD_MUM_OUT_READ_ATB_SENSOR_LEN 47519#define MC_CMD_MUM_OUT_READ_ATB_SENSOR_RESULT_OFST 07520#define MC_CMD_MUM_OUT_READ_ATB_SENSOR_RESULT_LEN 47521 7522/* MC_CMD_MUM_OUT_QSFP_INIT msgresponse */7523#define MC_CMD_MUM_OUT_QSFP_INIT_LEN 07524 7525/* MC_CMD_MUM_OUT_QSFP_RECONFIGURE msgresponse */7526#define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_LEN 87527#define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LP_CAP_OFST 07528#define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LP_CAP_LEN 47529#define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_FLAGS_OFST 47530#define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_FLAGS_LEN 47531#define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_READY_OFST 47532#define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_READY_LBN 07533#define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_READY_WIDTH 17534#define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LINK_UP_OFST 47535#define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LINK_UP_LBN 17536#define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LINK_UP_WIDTH 17537 7538/* MC_CMD_MUM_OUT_QSFP_GET_SUPPORTED_CAP msgresponse */7539#define MC_CMD_MUM_OUT_QSFP_GET_SUPPORTED_CAP_LEN 47540#define MC_CMD_MUM_OUT_QSFP_GET_SUPPORTED_CAP_PORT_PHY_LP_CAP_OFST 07541#define MC_CMD_MUM_OUT_QSFP_GET_SUPPORTED_CAP_PORT_PHY_LP_CAP_LEN 47542 7543/* MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO msgresponse */7544#define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_LENMIN 57545#define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_LENMAX 2527546#define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_LENMAX_MCDI2 10207547#define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_LEN(num) (4+1*(num))7548#define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_NUM(len) (((len)-4)/1)7549/* in bytes */7550#define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATALEN_OFST 07551#define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATALEN_LEN 47552#define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_OFST 47553#define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_LEN 17554#define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_MINNUM 17555#define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_MAXNUM 2487556#define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_MAXNUM_MCDI2 10167557 7558/* MC_CMD_MUM_OUT_QSFP_FILL_STATS msgresponse */7559#define MC_CMD_MUM_OUT_QSFP_FILL_STATS_LEN 87560#define MC_CMD_MUM_OUT_QSFP_FILL_STATS_PORT_PHY_STATS_PMA_PMD_LINK_UP_OFST 07561#define MC_CMD_MUM_OUT_QSFP_FILL_STATS_PORT_PHY_STATS_PMA_PMD_LINK_UP_LEN 47562#define MC_CMD_MUM_OUT_QSFP_FILL_STATS_PORT_PHY_STATS_PCS_LINK_UP_OFST 47563#define MC_CMD_MUM_OUT_QSFP_FILL_STATS_PORT_PHY_STATS_PCS_LINK_UP_LEN 47564 7565/* MC_CMD_MUM_OUT_QSFP_POLL_BIST msgresponse */7566#define MC_CMD_MUM_OUT_QSFP_POLL_BIST_LEN 47567#define MC_CMD_MUM_OUT_QSFP_POLL_BIST_TEST_OFST 07568#define MC_CMD_MUM_OUT_QSFP_POLL_BIST_TEST_LEN 47569 7570/* MC_CMD_MUM_OUT_READ_DDR_INFO msgresponse */7571#define MC_CMD_MUM_OUT_READ_DDR_INFO_LENMIN 247572#define MC_CMD_MUM_OUT_READ_DDR_INFO_LENMAX 2487573#define MC_CMD_MUM_OUT_READ_DDR_INFO_LENMAX_MCDI2 10167574#define MC_CMD_MUM_OUT_READ_DDR_INFO_LEN(num) (8+8*(num))7575#define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_NUM(len) (((len)-8)/8)7576/* Discrete (soldered) DDR resistor strap info */7577#define MC_CMD_MUM_OUT_READ_DDR_INFO_DISCRETE_DDR_INFO_OFST 07578#define MC_CMD_MUM_OUT_READ_DDR_INFO_DISCRETE_DDR_INFO_LEN 47579#define MC_CMD_MUM_OUT_READ_DDR_INFO_VRATIO_OFST 07580#define MC_CMD_MUM_OUT_READ_DDR_INFO_VRATIO_LBN 07581#define MC_CMD_MUM_OUT_READ_DDR_INFO_VRATIO_WIDTH 167582#define MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED1_OFST 07583#define MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED1_LBN 167584#define MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED1_WIDTH 167585/* Number of SODIMM info records */7586#define MC_CMD_MUM_OUT_READ_DDR_INFO_NUM_RECORDS_OFST 47587#define MC_CMD_MUM_OUT_READ_DDR_INFO_NUM_RECORDS_LEN 47588/* Array of SODIMM info records */7589#define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_OFST 87590#define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_LEN 87591#define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_LO_OFST 87592#define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_HI_OFST 127593#define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_MINNUM 27594#define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_MAXNUM 307595#define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_MAXNUM_MCDI2 1267596#define MC_CMD_MUM_OUT_READ_DDR_INFO_BANK_ID_OFST 87597#define MC_CMD_MUM_OUT_READ_DDR_INFO_BANK_ID_LBN 07598#define MC_CMD_MUM_OUT_READ_DDR_INFO_BANK_ID_WIDTH 87599/* enum: SODIMM bank 1 (Top SODIMM for Sorrento) */7600#define MC_CMD_MUM_OUT_READ_DDR_INFO_BANK1 0x07601/* enum: SODIMM bank 2 (Bottom SODDIMM for Sorrento) */7602#define MC_CMD_MUM_OUT_READ_DDR_INFO_BANK2 0x17603/* enum: Total number of SODIMM banks */7604#define MC_CMD_MUM_OUT_READ_DDR_INFO_NUM_BANKS 0x27605#define MC_CMD_MUM_OUT_READ_DDR_INFO_TYPE_OFST 87606#define MC_CMD_MUM_OUT_READ_DDR_INFO_TYPE_LBN 87607#define MC_CMD_MUM_OUT_READ_DDR_INFO_TYPE_WIDTH 87608#define MC_CMD_MUM_OUT_READ_DDR_INFO_RANK_OFST 87609#define MC_CMD_MUM_OUT_READ_DDR_INFO_RANK_LBN 167610#define MC_CMD_MUM_OUT_READ_DDR_INFO_RANK_WIDTH 47611#define MC_CMD_MUM_OUT_READ_DDR_INFO_VOLTAGE_OFST 87612#define MC_CMD_MUM_OUT_READ_DDR_INFO_VOLTAGE_LBN 207613#define MC_CMD_MUM_OUT_READ_DDR_INFO_VOLTAGE_WIDTH 47614#define MC_CMD_MUM_OUT_READ_DDR_INFO_NOT_POWERED 0x0 /* enum */7615#define MC_CMD_MUM_OUT_READ_DDR_INFO_1V25 0x1 /* enum */7616#define MC_CMD_MUM_OUT_READ_DDR_INFO_1V35 0x2 /* enum */7617#define MC_CMD_MUM_OUT_READ_DDR_INFO_1V5 0x3 /* enum */7618/* enum: Values 5-15 are reserved for future usage */7619#define MC_CMD_MUM_OUT_READ_DDR_INFO_1V8 0x47620#define MC_CMD_MUM_OUT_READ_DDR_INFO_SIZE_OFST 87621#define MC_CMD_MUM_OUT_READ_DDR_INFO_SIZE_LBN 247622#define MC_CMD_MUM_OUT_READ_DDR_INFO_SIZE_WIDTH 87623#define MC_CMD_MUM_OUT_READ_DDR_INFO_SPEED_OFST 87624#define MC_CMD_MUM_OUT_READ_DDR_INFO_SPEED_LBN 327625#define MC_CMD_MUM_OUT_READ_DDR_INFO_SPEED_WIDTH 167626#define MC_CMD_MUM_OUT_READ_DDR_INFO_STATE_OFST 87627#define MC_CMD_MUM_OUT_READ_DDR_INFO_STATE_LBN 487628#define MC_CMD_MUM_OUT_READ_DDR_INFO_STATE_WIDTH 47629/* enum: No module present */7630#define MC_CMD_MUM_OUT_READ_DDR_INFO_ABSENT 0x07631/* enum: Module present supported and powered on */7632#define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_POWERED 0x17633/* enum: Module present but bad type */7634#define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_TYPE 0x27635/* enum: Module present but incompatible voltage */7636#define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_VOLTAGE 0x37637/* enum: Module present but unknown SPD */7638#define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_SPD 0x47639/* enum: Module present but slot cannot support it */7640#define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_SLOT 0x57641/* enum: Modules may or may not be present, but cannot establish contact by I2C7642 */7643#define MC_CMD_MUM_OUT_READ_DDR_INFO_NOT_REACHABLE 0x67644#define MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED2_OFST 87645#define MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED2_LBN 527646#define MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED2_WIDTH 127647 7648/* MC_CMD_DYNAMIC_SENSORS_LIMITS structuredef: Set of sensor limits. This7649 * should match the equivalent structure in the sensor_query SPHINX service.7650 */7651#define MC_CMD_DYNAMIC_SENSORS_LIMITS_LEN 247652/* A value below this will trigger a warning event. */7653#define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_WARNING_OFST 07654#define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_WARNING_LEN 47655#define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_WARNING_LBN 07656#define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_WARNING_WIDTH 327657/* A value below this will trigger a critical event. */7658#define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_CRITICAL_OFST 47659#define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_CRITICAL_LEN 47660#define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_CRITICAL_LBN 327661#define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_CRITICAL_WIDTH 327662/* A value below this will shut down the card. */7663#define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_FATAL_OFST 87664#define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_FATAL_LEN 47665#define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_FATAL_LBN 647666#define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_FATAL_WIDTH 327667/* A value above this will trigger a warning event. */7668#define MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_WARNING_OFST 127669#define MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_WARNING_LEN 47670#define MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_WARNING_LBN 967671#define MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_WARNING_WIDTH 327672/* A value above this will trigger a critical event. */7673#define MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_CRITICAL_OFST 167674#define MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_CRITICAL_LEN 47675#define MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_CRITICAL_LBN 1287676#define MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_CRITICAL_WIDTH 327677/* A value above this will shut down the card. */7678#define MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_FATAL_OFST 207679#define MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_FATAL_LEN 47680#define MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_FATAL_LBN 1607681#define MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_FATAL_WIDTH 327682 7683/* MC_CMD_DYNAMIC_SENSORS_DESCRIPTION structuredef: Description of a sensor.7684 * This should match the equivalent structure in the sensor_query SPHINX7685 * service.7686 */7687#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_LEN 647688/* The handle used to identify the sensor in calls to7689 * MC_CMD_DYNAMIC_SENSORS_GET_VALUES7690 */7691#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_HANDLE_OFST 07692#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_HANDLE_LEN 47693#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_HANDLE_LBN 07694#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_HANDLE_WIDTH 327695/* A human-readable name for the sensor (zero terminated string, max 32 bytes)7696 */7697#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_NAME_OFST 47698#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_NAME_LEN 327699#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_NAME_LBN 327700#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_NAME_WIDTH 2567701/* The type of the sensor device, and by implication the unit of that the7702 * values will be reported in7703 */7704#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_TYPE_OFST 367705#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_TYPE_LEN 47706/* enum: A voltage sensor. Unit is mV */7707#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_VOLTAGE 0x07708/* enum: A current sensor. Unit is mA */7709#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_CURRENT 0x17710/* enum: A power sensor. Unit is mW */7711#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_POWER 0x27712/* enum: A temperature sensor. Unit is Celsius */7713#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_TEMPERATURE 0x37714/* enum: A cooling fan sensor. Unit is RPM */7715#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_FAN 0x47716#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_TYPE_LBN 2887717#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_TYPE_WIDTH 327718/* A single MC_CMD_DYNAMIC_SENSORS_LIMITS structure */7719#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_LIMITS_OFST 407720#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_LIMITS_LEN 247721#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_LIMITS_LBN 3207722#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_LIMITS_WIDTH 1927723 7724/* MC_CMD_DYNAMIC_SENSORS_READING structuredef: State and value of a sensor.7725 * This should match the equivalent structure in the sensor_query SPHINX7726 * service.7727 */7728#define MC_CMD_DYNAMIC_SENSORS_READING_LEN 127729/* The handle used to identify the sensor */7730#define MC_CMD_DYNAMIC_SENSORS_READING_HANDLE_OFST 07731#define MC_CMD_DYNAMIC_SENSORS_READING_HANDLE_LEN 47732#define MC_CMD_DYNAMIC_SENSORS_READING_HANDLE_LBN 07733#define MC_CMD_DYNAMIC_SENSORS_READING_HANDLE_WIDTH 327734/* The current value of the sensor */7735#define MC_CMD_DYNAMIC_SENSORS_READING_VALUE_OFST 47736#define MC_CMD_DYNAMIC_SENSORS_READING_VALUE_LEN 47737#define MC_CMD_DYNAMIC_SENSORS_READING_VALUE_LBN 327738#define MC_CMD_DYNAMIC_SENSORS_READING_VALUE_WIDTH 327739/* The sensor's condition, e.g. good, broken or removed */7740#define MC_CMD_DYNAMIC_SENSORS_READING_STATE_OFST 87741#define MC_CMD_DYNAMIC_SENSORS_READING_STATE_LEN 47742/* enum: Sensor working normally within limits */7743#define MC_CMD_DYNAMIC_SENSORS_READING_OK 0x07744/* enum: Warning threshold breached */7745#define MC_CMD_DYNAMIC_SENSORS_READING_WARNING 0x17746/* enum: Critical threshold breached */7747#define MC_CMD_DYNAMIC_SENSORS_READING_CRITICAL 0x27748/* enum: Fatal threshold breached */7749#define MC_CMD_DYNAMIC_SENSORS_READING_FATAL 0x37750/* enum: Sensor not working */7751#define MC_CMD_DYNAMIC_SENSORS_READING_BROKEN 0x47752/* enum: Sensor working but no reading available */7753#define MC_CMD_DYNAMIC_SENSORS_READING_NO_READING 0x57754/* enum: Sensor initialization failed */7755#define MC_CMD_DYNAMIC_SENSORS_READING_INIT_FAILED 0x67756#define MC_CMD_DYNAMIC_SENSORS_READING_STATE_LBN 647757#define MC_CMD_DYNAMIC_SENSORS_READING_STATE_WIDTH 327758 7759 7760/***********************************/7761/* MC_CMD_DYNAMIC_SENSORS_LIST7762 * Return a complete list of handles for sensors currently managed by the MC,7763 * and a generation count for this version of the sensor table. On systems7764 * advertising the DYNAMIC_SENSORS capability bit, this replaces the7765 * MC_CMD_READ_SENSORS command. On multi-MC systems this may include sensors7766 * added by the NMC.7767 *7768 * Sensor handles are persistent for the lifetime of the sensor and are used to7769 * identify sensors in MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS and7770 * MC_CMD_DYNAMIC_SENSORS_GET_VALUES.7771 *7772 * The generation count is maintained by the MC, is persistent across reboots7773 * and will be incremented each time the sensor table is modified. When the7774 * table is modified, a CODE_DYNAMIC_SENSORS_CHANGE event will be generated7775 * containing the new generation count. The driver should compare this against7776 * the current generation count, and if it is different, call7777 * MC_CMD_DYNAMIC_SENSORS_LIST again to update it's copy of the sensor table.7778 *7779 * The sensor count is provided to allow a future path to supporting more than7780 * MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_HANDLES_MAXNUM_MCDI2 sensors, i.e.7781 * the maximum number that will fit in a single response. As this is a fairly7782 * large number (253) it is not anticipated that this will be needed in the7783 * near future, so can currently be ignored.7784 *7785 * On Riverhead this command is implemented as a wrapper for `list` in the7786 * sensor_query SPHINX service.7787 */7788#define MC_CMD_DYNAMIC_SENSORS_LIST 0x667789#undef MC_CMD_0x66_PRIVILEGE_CTG7790 7791#define MC_CMD_0x66_PRIVILEGE_CTG SRIOV_CTG_GENERAL7792 7793/* MC_CMD_DYNAMIC_SENSORS_LIST_IN msgrequest */7794#define MC_CMD_DYNAMIC_SENSORS_LIST_IN_LEN 07795 7796/* MC_CMD_DYNAMIC_SENSORS_LIST_OUT msgresponse */7797#define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_LENMIN 87798#define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_LENMAX 2527799#define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_LENMAX_MCDI2 10207800#define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_LEN(num) (8+4*(num))7801#define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_HANDLES_NUM(len) (((len)-8)/4)7802/* Generation count, which will be updated each time a sensor is added to or7803 * removed from the MC sensor table.7804 */7805#define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_GENERATION_OFST 07806#define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_GENERATION_LEN 47807/* Number of sensors managed by the MC. Note that in principle, this can be7808 * larger than the size of the HANDLES array.7809 */7810#define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_COUNT_OFST 47811#define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_COUNT_LEN 47812/* Array of sensor handles */7813#define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_HANDLES_OFST 87814#define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_HANDLES_LEN 47815#define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_HANDLES_MINNUM 07816#define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_HANDLES_MAXNUM 617817#define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_HANDLES_MAXNUM_MCDI2 2537818 7819 7820/***********************************/7821/* MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS7822 * Get descriptions for a set of sensors, specified as an array of sensor7823 * handles as returned by MC_CMD_DYNAMIC_SENSORS_LIST7824 *7825 * Any handles which do not correspond to a sensor currently managed by the MC7826 * will be dropped from from the response. This may happen when a sensor table7827 * update is in progress, and effectively means the set of usable sensors is7828 * the intersection between the sets of sensors known to the driver and the MC.7829 *7830 * On Riverhead this command is implemented as a wrapper for7831 * `get_descriptions` in the sensor_query SPHINX service.7832 */7833#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS 0x677834#undef MC_CMD_0x67_PRIVILEGE_CTG7835 7836#define MC_CMD_0x67_PRIVILEGE_CTG SRIOV_CTG_GENERAL7837 7838/* MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN msgrequest */7839#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_LENMIN 07840#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_LENMAX 2527841#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_LENMAX_MCDI2 10207842#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_LEN(num) (0+4*(num))7843#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_HANDLES_NUM(len) (((len)-0)/4)7844/* Array of sensor handles */7845#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_HANDLES_OFST 07846#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_HANDLES_LEN 47847#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_HANDLES_MINNUM 07848#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_HANDLES_MAXNUM 637849#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_HANDLES_MAXNUM_MCDI2 2557850 7851/* MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT msgresponse */7852#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_LENMIN 07853#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_LENMAX 1927854#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_LENMAX_MCDI2 9607855#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_LEN(num) (0+64*(num))7856#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_SENSORS_NUM(len) (((len)-0)/64)7857/* Array of MC_CMD_DYNAMIC_SENSORS_DESCRIPTION structures */7858#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_SENSORS_OFST 07859#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_SENSORS_LEN 647860#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_SENSORS_MINNUM 07861#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_SENSORS_MAXNUM 37862#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_SENSORS_MAXNUM_MCDI2 157863 7864 7865/***********************************/7866/* MC_CMD_DYNAMIC_SENSORS_GET_READINGS7867 * Read the state and value for a set of sensors, specified as an array of7868 * sensor handles as returned by MC_CMD_DYNAMIC_SENSORS_LIST.7869 *7870 * In the case of a broken sensor, then the state of the response's7871 * MC_CMD_DYNAMIC_SENSORS_VALUE entry will be set to BROKEN, and any value7872 * provided should be treated as erroneous.7873 *7874 * Any handles which do not correspond to a sensor currently managed by the MC7875 * will be dropped from from the response. This may happen when a sensor table7876 * update is in progress, and effectively means the set of usable sensors is7877 * the intersection between the sets of sensors known to the driver and the MC.7878 *7879 * On Riverhead this command is implemented as a wrapper for `get_readings`7880 * in the sensor_query SPHINX service.7881 */7882#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS 0x687883#undef MC_CMD_0x68_PRIVILEGE_CTG7884 7885#define MC_CMD_0x68_PRIVILEGE_CTG SRIOV_CTG_GENERAL7886 7887/* MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN msgrequest */7888#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_LENMIN 07889#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_LENMAX 2527890#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_LENMAX_MCDI2 10207891#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_LEN(num) (0+4*(num))7892#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_HANDLES_NUM(len) (((len)-0)/4)7893/* Array of sensor handles */7894#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_HANDLES_OFST 07895#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_HANDLES_LEN 47896#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_HANDLES_MINNUM 07897#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_HANDLES_MAXNUM 637898#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_HANDLES_MAXNUM_MCDI2 2557899 7900/* MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT msgresponse */7901#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_LENMIN 07902#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_LENMAX 2527903#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_LENMAX_MCDI2 10207904#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_LEN(num) (0+12*(num))7905#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_VALUES_NUM(len) (((len)-0)/12)7906/* Array of MC_CMD_DYNAMIC_SENSORS_READING structures */7907#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_VALUES_OFST 07908#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_VALUES_LEN 127909#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_VALUES_MINNUM 07910#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_VALUES_MAXNUM 217911#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_VALUES_MAXNUM_MCDI2 857912 7913 7914/***********************************/7915/* MC_CMD_EVENT_CTRL7916 * Configure which categories of unsolicited events the driver expects to7917 * receive (Riverhead).7918 */7919#define MC_CMD_EVENT_CTRL 0x697920#undef MC_CMD_0x69_PRIVILEGE_CTG7921 7922#define MC_CMD_0x69_PRIVILEGE_CTG SRIOV_CTG_GENERAL7923 7924/* MC_CMD_EVENT_CTRL_IN msgrequest */7925#define MC_CMD_EVENT_CTRL_IN_LENMIN 07926#define MC_CMD_EVENT_CTRL_IN_LENMAX 2527927#define MC_CMD_EVENT_CTRL_IN_LENMAX_MCDI2 10207928#define MC_CMD_EVENT_CTRL_IN_LEN(num) (0+4*(num))7929#define MC_CMD_EVENT_CTRL_IN_EVENT_TYPE_NUM(len) (((len)-0)/4)7930/* Array of event categories for which the driver wishes to receive events. */7931#define MC_CMD_EVENT_CTRL_IN_EVENT_TYPE_OFST 07932#define MC_CMD_EVENT_CTRL_IN_EVENT_TYPE_LEN 47933#define MC_CMD_EVENT_CTRL_IN_EVENT_TYPE_MINNUM 07934#define MC_CMD_EVENT_CTRL_IN_EVENT_TYPE_MAXNUM 637935#define MC_CMD_EVENT_CTRL_IN_EVENT_TYPE_MAXNUM_MCDI2 2557936/* enum: Driver wishes to receive LINKCHANGE events. */7937#define MC_CMD_EVENT_CTRL_IN_MCDI_EVENT_CODE_LINKCHANGE 0x07938/* enum: Driver wishes to receive SENSOR_CHANGE and SENSOR_STATE_CHANGE events.7939 */7940#define MC_CMD_EVENT_CTRL_IN_MCDI_EVENT_CODE_SENSOREVT 0x17941/* enum: Driver wishes to receive receive errors. */7942#define MC_CMD_EVENT_CTRL_IN_MCDI_EVENT_CODE_RX_ERR 0x27943/* enum: Driver wishes to receive transmit errors. */7944#define MC_CMD_EVENT_CTRL_IN_MCDI_EVENT_CODE_TX_ERR 0x37945/* enum: Driver wishes to receive firmware alerts. */7946#define MC_CMD_EVENT_CTRL_IN_MCDI_EVENT_CODE_FWALERT 0x47947/* enum: Driver wishes to receive reboot events. */7948#define MC_CMD_EVENT_CTRL_IN_MCDI_EVENT_CODE_MC_REBOOT 0x57949 7950/* MC_CMD_EVENT_CTRL_OUT msgrequest */7951#define MC_CMD_EVENT_CTRL_OUT_LEN 07952 7953/* EVB_PORT_ID structuredef */7954#define EVB_PORT_ID_LEN 47955#define EVB_PORT_ID_PORT_ID_OFST 07956#define EVB_PORT_ID_PORT_ID_LEN 47957/* enum: An invalid port handle. */7958#define EVB_PORT_ID_NULL 0x07959/* enum: The port assigned to this function.. */7960#define EVB_PORT_ID_ASSIGNED 0x10000007961/* enum: External network port 0 */7962#define EVB_PORT_ID_MAC0 0x20000007963/* enum: External network port 1 */7964#define EVB_PORT_ID_MAC1 0x20000017965/* enum: External network port 2 */7966#define EVB_PORT_ID_MAC2 0x20000027967/* enum: External network port 3 */7968#define EVB_PORT_ID_MAC3 0x20000037969#define EVB_PORT_ID_PORT_ID_LBN 07970#define EVB_PORT_ID_PORT_ID_WIDTH 327971 7972/* EVB_VLAN_TAG structuredef */7973#define EVB_VLAN_TAG_LEN 27974/* The VLAN tag value */7975#define EVB_VLAN_TAG_VLAN_ID_LBN 07976#define EVB_VLAN_TAG_VLAN_ID_WIDTH 127977#define EVB_VLAN_TAG_MODE_LBN 127978#define EVB_VLAN_TAG_MODE_WIDTH 47979/* enum: Insert the VLAN. */7980#define EVB_VLAN_TAG_INSERT 0x07981/* enum: Replace the VLAN if already present. */7982#define EVB_VLAN_TAG_REPLACE 0x17983 7984/* BUFTBL_ENTRY structuredef */7985#define BUFTBL_ENTRY_LEN 127986/* the owner ID */7987#define BUFTBL_ENTRY_OID_OFST 07988#define BUFTBL_ENTRY_OID_LEN 27989#define BUFTBL_ENTRY_OID_LBN 07990#define BUFTBL_ENTRY_OID_WIDTH 167991/* the page parameter as one of ESE_DZ_SMC_PAGE_SIZE_ */7992#define BUFTBL_ENTRY_PGSZ_OFST 27993#define BUFTBL_ENTRY_PGSZ_LEN 27994#define BUFTBL_ENTRY_PGSZ_LBN 167995#define BUFTBL_ENTRY_PGSZ_WIDTH 167996/* the raw 64-bit address field from the SMC, not adjusted for page size */7997#define BUFTBL_ENTRY_RAWADDR_OFST 47998#define BUFTBL_ENTRY_RAWADDR_LEN 87999#define BUFTBL_ENTRY_RAWADDR_LO_OFST 48000#define BUFTBL_ENTRY_RAWADDR_HI_OFST 88001#define BUFTBL_ENTRY_RAWADDR_LBN 328002#define BUFTBL_ENTRY_RAWADDR_WIDTH 648003 8004/* NVRAM_PARTITION_TYPE structuredef */8005#define NVRAM_PARTITION_TYPE_LEN 28006#define NVRAM_PARTITION_TYPE_ID_OFST 08007#define NVRAM_PARTITION_TYPE_ID_LEN 28008/* enum: Primary MC firmware partition */8009#define NVRAM_PARTITION_TYPE_MC_FIRMWARE 0x1008010/* enum: Secondary MC firmware partition */8011#define NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP 0x2008012/* enum: Expansion ROM partition */8013#define NVRAM_PARTITION_TYPE_EXPANSION_ROM 0x3008014/* enum: Static configuration TLV partition */8015#define NVRAM_PARTITION_TYPE_STATIC_CONFIG 0x4008016/* enum: Dynamic configuration TLV partition */8017#define NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG 0x5008018/* enum: Expansion ROM configuration data for port 0 */8019#define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0 0x6008020/* enum: Synonym for EXPROM_CONFIG_PORT0 as used in pmap files */8021#define NVRAM_PARTITION_TYPE_EXPROM_CONFIG 0x6008022/* enum: Expansion ROM configuration data for port 1 */8023#define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1 0x6018024/* enum: Expansion ROM configuration data for port 2 */8025#define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2 0x6028026/* enum: Expansion ROM configuration data for port 3 */8027#define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3 0x6038028/* enum: Non-volatile log output partition */8029#define NVRAM_PARTITION_TYPE_LOG 0x7008030/* enum: Non-volatile log output of second core on dual-core device */8031#define NVRAM_PARTITION_TYPE_LOG_SLAVE 0x7018032/* enum: Device state dump output partition */8033#define NVRAM_PARTITION_TYPE_DUMP 0x8008034/* enum: Application license key storage partition */8035#define NVRAM_PARTITION_TYPE_LICENSE 0x9008036/* enum: Start of range used for PHY partitions (low 8 bits are the PHY ID) */8037#define NVRAM_PARTITION_TYPE_PHY_MIN 0xa008038/* enum: End of range used for PHY partitions (low 8 bits are the PHY ID) */8039#define NVRAM_PARTITION_TYPE_PHY_MAX 0xaff8040/* enum: Primary FPGA partition */8041#define NVRAM_PARTITION_TYPE_FPGA 0xb008042/* enum: Secondary FPGA partition */8043#define NVRAM_PARTITION_TYPE_FPGA_BACKUP 0xb018044/* enum: FC firmware partition */8045#define NVRAM_PARTITION_TYPE_FC_FIRMWARE 0xb028046/* enum: FC License partition */8047#define NVRAM_PARTITION_TYPE_FC_LICENSE 0xb038048/* enum: Non-volatile log output partition for FC */8049#define NVRAM_PARTITION_TYPE_FC_LOG 0xb048050/* enum: MUM firmware partition */8051#define NVRAM_PARTITION_TYPE_MUM_FIRMWARE 0xc008052/* enum: SUC firmware partition (this is intentionally an alias of8053 * MUM_FIRMWARE)8054 */8055#define NVRAM_PARTITION_TYPE_SUC_FIRMWARE 0xc008056/* enum: MUM Non-volatile log output partition. */8057#define NVRAM_PARTITION_TYPE_MUM_LOG 0xc018058/* enum: MUM Application table partition. */8059#define NVRAM_PARTITION_TYPE_MUM_APPTABLE 0xc028060/* enum: MUM boot rom partition. */8061#define NVRAM_PARTITION_TYPE_MUM_BOOT_ROM 0xc038062/* enum: MUM production signatures & calibration rom partition. */8063#define NVRAM_PARTITION_TYPE_MUM_PROD_ROM 0xc048064/* enum: MUM user signatures & calibration rom partition. */8065#define NVRAM_PARTITION_TYPE_MUM_USER_ROM 0xc058066/* enum: MUM fuses and lockbits partition. */8067#define NVRAM_PARTITION_TYPE_MUM_FUSELOCK 0xc068068/* enum: UEFI expansion ROM if separate from PXE */8069#define NVRAM_PARTITION_TYPE_EXPANSION_UEFI 0xd008070/* enum: Used by the expansion ROM for logging */8071#define NVRAM_PARTITION_TYPE_PXE_LOG 0x10008072/* enum: Used for XIP code of shmbooted images */8073#define NVRAM_PARTITION_TYPE_XIP_SCRATCH 0x11008074/* enum: Spare partition 2 */8075#define NVRAM_PARTITION_TYPE_SPARE_2 0x12008076/* enum: Manufacturing partition. Used during manufacture to pass information8077 * between XJTAG and Manftest.8078 */8079#define NVRAM_PARTITION_TYPE_MANUFACTURING 0x13008080/* enum: Spare partition 4 */8081#define NVRAM_PARTITION_TYPE_SPARE_4 0x14008082/* enum: Spare partition 5 */8083#define NVRAM_PARTITION_TYPE_SPARE_5 0x15008084/* enum: Partition for reporting MC status. See mc_flash_layout.h8085 * medford_mc_status_hdr_t for layout on Medford.8086 */8087#define NVRAM_PARTITION_TYPE_STATUS 0x16008088/* enum: Spare partition 13 */8089#define NVRAM_PARTITION_TYPE_SPARE_13 0x17008090/* enum: Spare partition 14 */8091#define NVRAM_PARTITION_TYPE_SPARE_14 0x18008092/* enum: Spare partition 15 */8093#define NVRAM_PARTITION_TYPE_SPARE_15 0x19008094/* enum: Spare partition 16 */8095#define NVRAM_PARTITION_TYPE_SPARE_16 0x1a008096/* enum: Factory defaults for dynamic configuration */8097#define NVRAM_PARTITION_TYPE_DYNCONFIG_DEFAULTS 0x1b008098/* enum: Factory defaults for expansion ROM configuration */8099#define NVRAM_PARTITION_TYPE_ROMCONFIG_DEFAULTS 0x1c008100/* enum: Field Replaceable Unit inventory information for use on IPMI8101 * platforms. See SF-119124-PS. The STATIC_CONFIG partition may contain a8102 * subset of the information stored in this partition.8103 */8104#define NVRAM_PARTITION_TYPE_FRU_INFORMATION 0x1d008105/* enum: Bundle image partition */8106#define NVRAM_PARTITION_TYPE_BUNDLE 0x1e008107/* enum: Bundle metadata partition that holds additional information related to8108 * a bundle update in TLV format8109 */8110#define NVRAM_PARTITION_TYPE_BUNDLE_METADATA 0x1e018111/* enum: Bundle update non-volatile log output partition */8112#define NVRAM_PARTITION_TYPE_BUNDLE_LOG 0x1e028113/* enum: Partition for Solarflare gPXE bootrom installed via Bundle update. */8114#define NVRAM_PARTITION_TYPE_EXPANSION_ROM_INTERNAL 0x1e038115/* enum: Start of reserved value range (firmware may use for any purpose) */8116#define NVRAM_PARTITION_TYPE_RESERVED_VALUES_MIN 0xff008117/* enum: End of reserved value range (firmware may use for any purpose) */8118#define NVRAM_PARTITION_TYPE_RESERVED_VALUES_MAX 0xfffd8119/* enum: Recovery partition map (provided if real map is missing or corrupt) */8120#define NVRAM_PARTITION_TYPE_RECOVERY_MAP 0xfffe8121/* enum: Partition map (real map as stored in flash) */8122#define NVRAM_PARTITION_TYPE_PARTITION_MAP 0xffff8123#define NVRAM_PARTITION_TYPE_ID_LBN 08124#define NVRAM_PARTITION_TYPE_ID_WIDTH 168125 8126/* LICENSED_APP_ID structuredef */8127#define LICENSED_APP_ID_LEN 48128#define LICENSED_APP_ID_ID_OFST 08129#define LICENSED_APP_ID_ID_LEN 48130/* enum: OpenOnload */8131#define LICENSED_APP_ID_ONLOAD 0x18132/* enum: PTP timestamping */8133#define LICENSED_APP_ID_PTP 0x28134/* enum: SolarCapture Pro */8135#define LICENSED_APP_ID_SOLARCAPTURE_PRO 0x48136/* enum: SolarSecure filter engine */8137#define LICENSED_APP_ID_SOLARSECURE 0x88138/* enum: Performance monitor */8139#define LICENSED_APP_ID_PERF_MONITOR 0x108140/* enum: SolarCapture Live */8141#define LICENSED_APP_ID_SOLARCAPTURE_LIVE 0x208142/* enum: Capture SolarSystem */8143#define LICENSED_APP_ID_CAPTURE_SOLARSYSTEM 0x408144/* enum: Network Access Control */8145#define LICENSED_APP_ID_NETWORK_ACCESS_CONTROL 0x808146/* enum: TCP Direct */8147#define LICENSED_APP_ID_TCP_DIRECT 0x1008148/* enum: Low Latency */8149#define LICENSED_APP_ID_LOW_LATENCY 0x2008150/* enum: SolarCapture Tap */8151#define LICENSED_APP_ID_SOLARCAPTURE_TAP 0x4008152/* enum: Capture SolarSystem 40G */8153#define LICENSED_APP_ID_CAPTURE_SOLARSYSTEM_40G 0x8008154/* enum: Capture SolarSystem 1G */8155#define LICENSED_APP_ID_CAPTURE_SOLARSYSTEM_1G 0x10008156/* enum: ScaleOut Onload */8157#define LICENSED_APP_ID_SCALEOUT_ONLOAD 0x20008158/* enum: SCS Network Analytics Dashboard */8159#define LICENSED_APP_ID_DSHBRD 0x40008160/* enum: SolarCapture Trading Analytics */8161#define LICENSED_APP_ID_SCATRD 0x80008162#define LICENSED_APP_ID_ID_LBN 08163#define LICENSED_APP_ID_ID_WIDTH 328164 8165/* LICENSED_FEATURES structuredef */8166#define LICENSED_FEATURES_LEN 88167/* Bitmask of licensed firmware features */8168#define LICENSED_FEATURES_MASK_OFST 08169#define LICENSED_FEATURES_MASK_LEN 88170#define LICENSED_FEATURES_MASK_LO_OFST 08171#define LICENSED_FEATURES_MASK_HI_OFST 48172#define LICENSED_FEATURES_RX_CUT_THROUGH_OFST 08173#define LICENSED_FEATURES_RX_CUT_THROUGH_LBN 08174#define LICENSED_FEATURES_RX_CUT_THROUGH_WIDTH 18175#define LICENSED_FEATURES_PIO_OFST 08176#define LICENSED_FEATURES_PIO_LBN 18177#define LICENSED_FEATURES_PIO_WIDTH 18178#define LICENSED_FEATURES_EVQ_TIMER_OFST 08179#define LICENSED_FEATURES_EVQ_TIMER_LBN 28180#define LICENSED_FEATURES_EVQ_TIMER_WIDTH 18181#define LICENSED_FEATURES_CLOCK_OFST 08182#define LICENSED_FEATURES_CLOCK_LBN 38183#define LICENSED_FEATURES_CLOCK_WIDTH 18184#define LICENSED_FEATURES_RX_TIMESTAMPS_OFST 08185#define LICENSED_FEATURES_RX_TIMESTAMPS_LBN 48186#define LICENSED_FEATURES_RX_TIMESTAMPS_WIDTH 18187#define LICENSED_FEATURES_TX_TIMESTAMPS_OFST 08188#define LICENSED_FEATURES_TX_TIMESTAMPS_LBN 58189#define LICENSED_FEATURES_TX_TIMESTAMPS_WIDTH 18190#define LICENSED_FEATURES_RX_SNIFF_OFST 08191#define LICENSED_FEATURES_RX_SNIFF_LBN 68192#define LICENSED_FEATURES_RX_SNIFF_WIDTH 18193#define LICENSED_FEATURES_TX_SNIFF_OFST 08194#define LICENSED_FEATURES_TX_SNIFF_LBN 78195#define LICENSED_FEATURES_TX_SNIFF_WIDTH 18196#define LICENSED_FEATURES_PROXY_FILTER_OPS_OFST 08197#define LICENSED_FEATURES_PROXY_FILTER_OPS_LBN 88198#define LICENSED_FEATURES_PROXY_FILTER_OPS_WIDTH 18199#define LICENSED_FEATURES_EVENT_CUT_THROUGH_OFST 08200#define LICENSED_FEATURES_EVENT_CUT_THROUGH_LBN 98201#define LICENSED_FEATURES_EVENT_CUT_THROUGH_WIDTH 18202#define LICENSED_FEATURES_MASK_LBN 08203#define LICENSED_FEATURES_MASK_WIDTH 648204 8205/* LICENSED_V3_APPS structuredef */8206#define LICENSED_V3_APPS_LEN 88207/* Bitmask of licensed applications */8208#define LICENSED_V3_APPS_MASK_OFST 08209#define LICENSED_V3_APPS_MASK_LEN 88210#define LICENSED_V3_APPS_MASK_LO_OFST 08211#define LICENSED_V3_APPS_MASK_HI_OFST 48212#define LICENSED_V3_APPS_ONLOAD_OFST 08213#define LICENSED_V3_APPS_ONLOAD_LBN 08214#define LICENSED_V3_APPS_ONLOAD_WIDTH 18215#define LICENSED_V3_APPS_PTP_OFST 08216#define LICENSED_V3_APPS_PTP_LBN 18217#define LICENSED_V3_APPS_PTP_WIDTH 18218#define LICENSED_V3_APPS_SOLARCAPTURE_PRO_OFST 08219#define LICENSED_V3_APPS_SOLARCAPTURE_PRO_LBN 28220#define LICENSED_V3_APPS_SOLARCAPTURE_PRO_WIDTH 18221#define LICENSED_V3_APPS_SOLARSECURE_OFST 08222#define LICENSED_V3_APPS_SOLARSECURE_LBN 38223#define LICENSED_V3_APPS_SOLARSECURE_WIDTH 18224#define LICENSED_V3_APPS_PERF_MONITOR_OFST 08225#define LICENSED_V3_APPS_PERF_MONITOR_LBN 48226#define LICENSED_V3_APPS_PERF_MONITOR_WIDTH 18227#define LICENSED_V3_APPS_SOLARCAPTURE_LIVE_OFST 08228#define LICENSED_V3_APPS_SOLARCAPTURE_LIVE_LBN 58229#define LICENSED_V3_APPS_SOLARCAPTURE_LIVE_WIDTH 18230#define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_OFST 08231#define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_LBN 68232#define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_WIDTH 18233#define LICENSED_V3_APPS_NETWORK_ACCESS_CONTROL_OFST 08234#define LICENSED_V3_APPS_NETWORK_ACCESS_CONTROL_LBN 78235#define LICENSED_V3_APPS_NETWORK_ACCESS_CONTROL_WIDTH 18236#define LICENSED_V3_APPS_TCP_DIRECT_OFST 08237#define LICENSED_V3_APPS_TCP_DIRECT_LBN 88238#define LICENSED_V3_APPS_TCP_DIRECT_WIDTH 18239#define LICENSED_V3_APPS_LOW_LATENCY_OFST 08240#define LICENSED_V3_APPS_LOW_LATENCY_LBN 98241#define LICENSED_V3_APPS_LOW_LATENCY_WIDTH 18242#define LICENSED_V3_APPS_SOLARCAPTURE_TAP_OFST 08243#define LICENSED_V3_APPS_SOLARCAPTURE_TAP_LBN 108244#define LICENSED_V3_APPS_SOLARCAPTURE_TAP_WIDTH 18245#define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_40G_OFST 08246#define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_40G_LBN 118247#define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_40G_WIDTH 18248#define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_1G_OFST 08249#define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_1G_LBN 128250#define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_1G_WIDTH 18251#define LICENSED_V3_APPS_SCALEOUT_ONLOAD_OFST 08252#define LICENSED_V3_APPS_SCALEOUT_ONLOAD_LBN 138253#define LICENSED_V3_APPS_SCALEOUT_ONLOAD_WIDTH 18254#define LICENSED_V3_APPS_DSHBRD_OFST 08255#define LICENSED_V3_APPS_DSHBRD_LBN 148256#define LICENSED_V3_APPS_DSHBRD_WIDTH 18257#define LICENSED_V3_APPS_SCATRD_OFST 08258#define LICENSED_V3_APPS_SCATRD_LBN 158259#define LICENSED_V3_APPS_SCATRD_WIDTH 18260#define LICENSED_V3_APPS_MASK_LBN 08261#define LICENSED_V3_APPS_MASK_WIDTH 648262 8263/* LICENSED_V3_FEATURES structuredef */8264#define LICENSED_V3_FEATURES_LEN 88265/* Bitmask of licensed firmware features */8266#define LICENSED_V3_FEATURES_MASK_OFST 08267#define LICENSED_V3_FEATURES_MASK_LEN 88268#define LICENSED_V3_FEATURES_MASK_LO_OFST 08269#define LICENSED_V3_FEATURES_MASK_HI_OFST 48270#define LICENSED_V3_FEATURES_RX_CUT_THROUGH_OFST 08271#define LICENSED_V3_FEATURES_RX_CUT_THROUGH_LBN 08272#define LICENSED_V3_FEATURES_RX_CUT_THROUGH_WIDTH 18273#define LICENSED_V3_FEATURES_PIO_OFST 08274#define LICENSED_V3_FEATURES_PIO_LBN 18275#define LICENSED_V3_FEATURES_PIO_WIDTH 18276#define LICENSED_V3_FEATURES_EVQ_TIMER_OFST 08277#define LICENSED_V3_FEATURES_EVQ_TIMER_LBN 28278#define LICENSED_V3_FEATURES_EVQ_TIMER_WIDTH 18279#define LICENSED_V3_FEATURES_CLOCK_OFST 08280#define LICENSED_V3_FEATURES_CLOCK_LBN 38281#define LICENSED_V3_FEATURES_CLOCK_WIDTH 18282#define LICENSED_V3_FEATURES_RX_TIMESTAMPS_OFST 08283#define LICENSED_V3_FEATURES_RX_TIMESTAMPS_LBN 48284#define LICENSED_V3_FEATURES_RX_TIMESTAMPS_WIDTH 18285#define LICENSED_V3_FEATURES_TX_TIMESTAMPS_OFST 08286#define LICENSED_V3_FEATURES_TX_TIMESTAMPS_LBN 58287#define LICENSED_V3_FEATURES_TX_TIMESTAMPS_WIDTH 18288#define LICENSED_V3_FEATURES_RX_SNIFF_OFST 08289#define LICENSED_V3_FEATURES_RX_SNIFF_LBN 68290#define LICENSED_V3_FEATURES_RX_SNIFF_WIDTH 18291#define LICENSED_V3_FEATURES_TX_SNIFF_OFST 08292#define LICENSED_V3_FEATURES_TX_SNIFF_LBN 78293#define LICENSED_V3_FEATURES_TX_SNIFF_WIDTH 18294#define LICENSED_V3_FEATURES_PROXY_FILTER_OPS_OFST 08295#define LICENSED_V3_FEATURES_PROXY_FILTER_OPS_LBN 88296#define LICENSED_V3_FEATURES_PROXY_FILTER_OPS_WIDTH 18297#define LICENSED_V3_FEATURES_EVENT_CUT_THROUGH_OFST 08298#define LICENSED_V3_FEATURES_EVENT_CUT_THROUGH_LBN 98299#define LICENSED_V3_FEATURES_EVENT_CUT_THROUGH_WIDTH 18300#define LICENSED_V3_FEATURES_MASK_LBN 08301#define LICENSED_V3_FEATURES_MASK_WIDTH 648302 8303/* TX_TIMESTAMP_EVENT structuredef */8304#define TX_TIMESTAMP_EVENT_LEN 68305/* lower 16 bits of timestamp data */8306#define TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_OFST 08307#define TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_LEN 28308#define TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_LBN 08309#define TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_WIDTH 168310/* Type of TX event, ordinary TX completion, low or high part of TX timestamp8311 */8312#define TX_TIMESTAMP_EVENT_TX_EV_TYPE_OFST 38313#define TX_TIMESTAMP_EVENT_TX_EV_TYPE_LEN 18314/* enum: This is a TX completion event, not a timestamp */8315#define TX_TIMESTAMP_EVENT_TX_EV_COMPLETION 0x08316/* enum: This is a TX completion event for a CTPIO transmit. The event format8317 * is the same as for TX_EV_COMPLETION.8318 */8319#define TX_TIMESTAMP_EVENT_TX_EV_CTPIO_COMPLETION 0x118320/* enum: This is the low part of a TX timestamp for a CTPIO transmission. The8321 * event format is the same as for TX_EV_TSTAMP_LO8322 */8323#define TX_TIMESTAMP_EVENT_TX_EV_CTPIO_TS_LO 0x128324/* enum: This is the high part of a TX timestamp for a CTPIO transmission. The8325 * event format is the same as for TX_EV_TSTAMP_HI8326 */8327#define TX_TIMESTAMP_EVENT_TX_EV_CTPIO_TS_HI 0x138328/* enum: This is the low part of a TX timestamp event */8329#define TX_TIMESTAMP_EVENT_TX_EV_TSTAMP_LO 0x518330/* enum: This is the high part of a TX timestamp event */8331#define TX_TIMESTAMP_EVENT_TX_EV_TSTAMP_HI 0x528332#define TX_TIMESTAMP_EVENT_TX_EV_TYPE_LBN 248333#define TX_TIMESTAMP_EVENT_TX_EV_TYPE_WIDTH 88334/* upper 16 bits of timestamp data */8335#define TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_OFST 48336#define TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_LEN 28337#define TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_LBN 328338#define TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_WIDTH 168339 8340/* RSS_MODE structuredef */8341#define RSS_MODE_LEN 18342/* The RSS mode for a particular packet type is a value from 0 - 15 which can8343 * be considered as 4 bits selecting which fields are included in the hash. (A8344 * value 0 effectively disables RSS spreading for the packet type.) The YAML8345 * generation tools require this structure to be a whole number of bytes wide,8346 * but only 4 bits are relevant.8347 */8348#define RSS_MODE_HASH_SELECTOR_OFST 08349#define RSS_MODE_HASH_SELECTOR_LEN 18350#define RSS_MODE_HASH_SRC_ADDR_OFST 08351#define RSS_MODE_HASH_SRC_ADDR_LBN 08352#define RSS_MODE_HASH_SRC_ADDR_WIDTH 18353#define RSS_MODE_HASH_DST_ADDR_OFST 08354#define RSS_MODE_HASH_DST_ADDR_LBN 18355#define RSS_MODE_HASH_DST_ADDR_WIDTH 18356#define RSS_MODE_HASH_SRC_PORT_OFST 08357#define RSS_MODE_HASH_SRC_PORT_LBN 28358#define RSS_MODE_HASH_SRC_PORT_WIDTH 18359#define RSS_MODE_HASH_DST_PORT_OFST 08360#define RSS_MODE_HASH_DST_PORT_LBN 38361#define RSS_MODE_HASH_DST_PORT_WIDTH 18362#define RSS_MODE_HASH_SELECTOR_LBN 08363#define RSS_MODE_HASH_SELECTOR_WIDTH 88364 8365/* CTPIO_STATS_MAP structuredef */8366#define CTPIO_STATS_MAP_LEN 48367/* The (function relative) VI number */8368#define CTPIO_STATS_MAP_VI_OFST 08369#define CTPIO_STATS_MAP_VI_LEN 28370#define CTPIO_STATS_MAP_VI_LBN 08371#define CTPIO_STATS_MAP_VI_WIDTH 168372/* The target bucket for the VI */8373#define CTPIO_STATS_MAP_BUCKET_OFST 28374#define CTPIO_STATS_MAP_BUCKET_LEN 28375#define CTPIO_STATS_MAP_BUCKET_LBN 168376#define CTPIO_STATS_MAP_BUCKET_WIDTH 168377 8378 8379/***********************************/8380/* MC_CMD_READ_REGS8381 * Get a dump of the MCPU registers8382 */8383#define MC_CMD_READ_REGS 0x508384#undef MC_CMD_0x50_PRIVILEGE_CTG8385 8386#define MC_CMD_0x50_PRIVILEGE_CTG SRIOV_CTG_INSECURE8387 8388/* MC_CMD_READ_REGS_IN msgrequest */8389#define MC_CMD_READ_REGS_IN_LEN 08390 8391/* MC_CMD_READ_REGS_OUT msgresponse */8392#define MC_CMD_READ_REGS_OUT_LEN 3088393/* Whether the corresponding register entry contains a valid value */8394#define MC_CMD_READ_REGS_OUT_MASK_OFST 08395#define MC_CMD_READ_REGS_OUT_MASK_LEN 168396/* Same order as MIPS GDB (r0-r31, sr, lo, hi, bad, cause, 32 x float, fsr,8397 * fir, fp)8398 */8399#define MC_CMD_READ_REGS_OUT_REGS_OFST 168400#define MC_CMD_READ_REGS_OUT_REGS_LEN 48401#define MC_CMD_READ_REGS_OUT_REGS_NUM 738402 8403 8404/***********************************/8405/* MC_CMD_INIT_EVQ8406 * Set up an event queue according to the supplied parameters. The IN arguments8407 * end with an address for each 4k of host memory required to back the EVQ.8408 */8409#define MC_CMD_INIT_EVQ 0x808410#undef MC_CMD_0x80_PRIVILEGE_CTG8411 8412#define MC_CMD_0x80_PRIVILEGE_CTG SRIOV_CTG_GENERAL8413 8414/* MC_CMD_INIT_EVQ_IN msgrequest */8415#define MC_CMD_INIT_EVQ_IN_LENMIN 448416#define MC_CMD_INIT_EVQ_IN_LENMAX 5488417#define MC_CMD_INIT_EVQ_IN_LENMAX_MCDI2 5488418#define MC_CMD_INIT_EVQ_IN_LEN(num) (36+8*(num))8419#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_NUM(len) (((len)-36)/8)8420/* Size, in entries */8421#define MC_CMD_INIT_EVQ_IN_SIZE_OFST 08422#define MC_CMD_INIT_EVQ_IN_SIZE_LEN 48423/* Desired instance. Must be set to a specific instance, which is a function8424 * local queue index.8425 */8426#define MC_CMD_INIT_EVQ_IN_INSTANCE_OFST 48427#define MC_CMD_INIT_EVQ_IN_INSTANCE_LEN 48428/* The initial timer value. The load value is ignored if the timer mode is DIS.8429 */8430#define MC_CMD_INIT_EVQ_IN_TMR_LOAD_OFST 88431#define MC_CMD_INIT_EVQ_IN_TMR_LOAD_LEN 48432/* The reload value is ignored in one-shot modes */8433#define MC_CMD_INIT_EVQ_IN_TMR_RELOAD_OFST 128434#define MC_CMD_INIT_EVQ_IN_TMR_RELOAD_LEN 48435/* tbd */8436#define MC_CMD_INIT_EVQ_IN_FLAGS_OFST 168437#define MC_CMD_INIT_EVQ_IN_FLAGS_LEN 48438#define MC_CMD_INIT_EVQ_IN_FLAG_INTERRUPTING_OFST 168439#define MC_CMD_INIT_EVQ_IN_FLAG_INTERRUPTING_LBN 08440#define MC_CMD_INIT_EVQ_IN_FLAG_INTERRUPTING_WIDTH 18441#define MC_CMD_INIT_EVQ_IN_FLAG_RPTR_DOS_OFST 168442#define MC_CMD_INIT_EVQ_IN_FLAG_RPTR_DOS_LBN 18443#define MC_CMD_INIT_EVQ_IN_FLAG_RPTR_DOS_WIDTH 18444#define MC_CMD_INIT_EVQ_IN_FLAG_INT_ARMD_OFST 168445#define MC_CMD_INIT_EVQ_IN_FLAG_INT_ARMD_LBN 28446#define MC_CMD_INIT_EVQ_IN_FLAG_INT_ARMD_WIDTH 18447#define MC_CMD_INIT_EVQ_IN_FLAG_CUT_THRU_OFST 168448#define MC_CMD_INIT_EVQ_IN_FLAG_CUT_THRU_LBN 38449#define MC_CMD_INIT_EVQ_IN_FLAG_CUT_THRU_WIDTH 18450#define MC_CMD_INIT_EVQ_IN_FLAG_RX_MERGE_OFST 168451#define MC_CMD_INIT_EVQ_IN_FLAG_RX_MERGE_LBN 48452#define MC_CMD_INIT_EVQ_IN_FLAG_RX_MERGE_WIDTH 18453#define MC_CMD_INIT_EVQ_IN_FLAG_TX_MERGE_OFST 168454#define MC_CMD_INIT_EVQ_IN_FLAG_TX_MERGE_LBN 58455#define MC_CMD_INIT_EVQ_IN_FLAG_TX_MERGE_WIDTH 18456#define MC_CMD_INIT_EVQ_IN_FLAG_USE_TIMER_OFST 168457#define MC_CMD_INIT_EVQ_IN_FLAG_USE_TIMER_LBN 68458#define MC_CMD_INIT_EVQ_IN_FLAG_USE_TIMER_WIDTH 18459#define MC_CMD_INIT_EVQ_IN_TMR_MODE_OFST 208460#define MC_CMD_INIT_EVQ_IN_TMR_MODE_LEN 48461/* enum: Disabled */8462#define MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS 0x08463/* enum: Immediate */8464#define MC_CMD_INIT_EVQ_IN_TMR_IMMED_START 0x18465/* enum: Triggered */8466#define MC_CMD_INIT_EVQ_IN_TMR_TRIG_START 0x28467/* enum: Hold-off */8468#define MC_CMD_INIT_EVQ_IN_TMR_INT_HLDOFF 0x38469/* Target EVQ for wakeups if in wakeup mode. */8470#define MC_CMD_INIT_EVQ_IN_TARGET_EVQ_OFST 248471#define MC_CMD_INIT_EVQ_IN_TARGET_EVQ_LEN 48472/* Target interrupt if in interrupting mode (note union with target EVQ). Use8473 * MC_CMD_RESOURCE_INSTANCE_ANY unless a specific one required for test8474 * purposes.8475 */8476#define MC_CMD_INIT_EVQ_IN_IRQ_NUM_OFST 248477#define MC_CMD_INIT_EVQ_IN_IRQ_NUM_LEN 48478/* Event Counter Mode. */8479#define MC_CMD_INIT_EVQ_IN_COUNT_MODE_OFST 288480#define MC_CMD_INIT_EVQ_IN_COUNT_MODE_LEN 48481/* enum: Disabled */8482#define MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS 0x08483/* enum: Disabled */8484#define MC_CMD_INIT_EVQ_IN_COUNT_MODE_RX 0x18485/* enum: Disabled */8486#define MC_CMD_INIT_EVQ_IN_COUNT_MODE_TX 0x28487/* enum: Disabled */8488#define MC_CMD_INIT_EVQ_IN_COUNT_MODE_RXTX 0x38489/* Event queue packet count threshold. */8490#define MC_CMD_INIT_EVQ_IN_COUNT_THRSHLD_OFST 328491#define MC_CMD_INIT_EVQ_IN_COUNT_THRSHLD_LEN 48492/* 64-bit address of 4k of 4k-aligned host memory buffer */8493#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_OFST 368494#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_LEN 88495#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_LO_OFST 368496#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_HI_OFST 408497#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_MINNUM 18498#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_MAXNUM 648499#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_MAXNUM_MCDI2 648500 8501/* MC_CMD_INIT_EVQ_OUT msgresponse */8502#define MC_CMD_INIT_EVQ_OUT_LEN 48503/* Only valid if INTRFLAG was true */8504#define MC_CMD_INIT_EVQ_OUT_IRQ_OFST 08505#define MC_CMD_INIT_EVQ_OUT_IRQ_LEN 48506 8507/* MC_CMD_INIT_EVQ_V2_IN msgrequest */8508#define MC_CMD_INIT_EVQ_V2_IN_LENMIN 448509#define MC_CMD_INIT_EVQ_V2_IN_LENMAX 5488510#define MC_CMD_INIT_EVQ_V2_IN_LENMAX_MCDI2 5488511#define MC_CMD_INIT_EVQ_V2_IN_LEN(num) (36+8*(num))8512#define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_NUM(len) (((len)-36)/8)8513/* Size, in entries */8514#define MC_CMD_INIT_EVQ_V2_IN_SIZE_OFST 08515#define MC_CMD_INIT_EVQ_V2_IN_SIZE_LEN 48516/* Desired instance. Must be set to a specific instance, which is a function8517 * local queue index.8518 */8519#define MC_CMD_INIT_EVQ_V2_IN_INSTANCE_OFST 48520#define MC_CMD_INIT_EVQ_V2_IN_INSTANCE_LEN 48521/* The initial timer value. The load value is ignored if the timer mode is DIS.8522 */8523#define MC_CMD_INIT_EVQ_V2_IN_TMR_LOAD_OFST 88524#define MC_CMD_INIT_EVQ_V2_IN_TMR_LOAD_LEN 48525/* The reload value is ignored in one-shot modes */8526#define MC_CMD_INIT_EVQ_V2_IN_TMR_RELOAD_OFST 128527#define MC_CMD_INIT_EVQ_V2_IN_TMR_RELOAD_LEN 48528/* tbd */8529#define MC_CMD_INIT_EVQ_V2_IN_FLAGS_OFST 168530#define MC_CMD_INIT_EVQ_V2_IN_FLAGS_LEN 48531#define MC_CMD_INIT_EVQ_V2_IN_FLAG_INTERRUPTING_OFST 168532#define MC_CMD_INIT_EVQ_V2_IN_FLAG_INTERRUPTING_LBN 08533#define MC_CMD_INIT_EVQ_V2_IN_FLAG_INTERRUPTING_WIDTH 18534#define MC_CMD_INIT_EVQ_V2_IN_FLAG_RPTR_DOS_OFST 168535#define MC_CMD_INIT_EVQ_V2_IN_FLAG_RPTR_DOS_LBN 18536#define MC_CMD_INIT_EVQ_V2_IN_FLAG_RPTR_DOS_WIDTH 18537#define MC_CMD_INIT_EVQ_V2_IN_FLAG_INT_ARMD_OFST 168538#define MC_CMD_INIT_EVQ_V2_IN_FLAG_INT_ARMD_LBN 28539#define MC_CMD_INIT_EVQ_V2_IN_FLAG_INT_ARMD_WIDTH 18540#define MC_CMD_INIT_EVQ_V2_IN_FLAG_CUT_THRU_OFST 168541#define MC_CMD_INIT_EVQ_V2_IN_FLAG_CUT_THRU_LBN 38542#define MC_CMD_INIT_EVQ_V2_IN_FLAG_CUT_THRU_WIDTH 18543#define MC_CMD_INIT_EVQ_V2_IN_FLAG_RX_MERGE_OFST 168544#define MC_CMD_INIT_EVQ_V2_IN_FLAG_RX_MERGE_LBN 48545#define MC_CMD_INIT_EVQ_V2_IN_FLAG_RX_MERGE_WIDTH 18546#define MC_CMD_INIT_EVQ_V2_IN_FLAG_TX_MERGE_OFST 168547#define MC_CMD_INIT_EVQ_V2_IN_FLAG_TX_MERGE_LBN 58548#define MC_CMD_INIT_EVQ_V2_IN_FLAG_TX_MERGE_WIDTH 18549#define MC_CMD_INIT_EVQ_V2_IN_FLAG_USE_TIMER_OFST 168550#define MC_CMD_INIT_EVQ_V2_IN_FLAG_USE_TIMER_LBN 68551#define MC_CMD_INIT_EVQ_V2_IN_FLAG_USE_TIMER_WIDTH 18552#define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_OFST 168553#define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_LBN 78554#define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_WIDTH 48555/* enum: All initialisation flags specified by host. */8556#define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_MANUAL 0x08557/* enum: MEDFORD only. Certain initialisation flags specified by host may be8558 * over-ridden by firmware based on licenses and firmware variant in order to8559 * provide the lowest latency achievable. See8560 * MC_CMD_INIT_EVQ_V2/MC_CMD_INIT_EVQ_V2_OUT/FLAGS for list of affected flags.8561 */8562#define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_LOW_LATENCY 0x18563/* enum: MEDFORD only. Certain initialisation flags specified by host may be8564 * over-ridden by firmware based on licenses and firmware variant in order to8565 * provide the best throughput achievable. See8566 * MC_CMD_INIT_EVQ_V2/MC_CMD_INIT_EVQ_V2_OUT/FLAGS for list of affected flags.8567 */8568#define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_THROUGHPUT 0x28569/* enum: MEDFORD only. Certain initialisation flags may be over-ridden by8570 * firmware based on licenses and firmware variant. See8571 * MC_CMD_INIT_EVQ_V2/MC_CMD_INIT_EVQ_V2_OUT/FLAGS for list of affected flags.8572 */8573#define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_AUTO 0x38574#define MC_CMD_INIT_EVQ_V2_IN_FLAG_EXT_WIDTH_OFST 168575#define MC_CMD_INIT_EVQ_V2_IN_FLAG_EXT_WIDTH_LBN 118576#define MC_CMD_INIT_EVQ_V2_IN_FLAG_EXT_WIDTH_WIDTH 18577#define MC_CMD_INIT_EVQ_V2_IN_TMR_MODE_OFST 208578#define MC_CMD_INIT_EVQ_V2_IN_TMR_MODE_LEN 48579/* enum: Disabled */8580#define MC_CMD_INIT_EVQ_V2_IN_TMR_MODE_DIS 0x08581/* enum: Immediate */8582#define MC_CMD_INIT_EVQ_V2_IN_TMR_IMMED_START 0x18583/* enum: Triggered */8584#define MC_CMD_INIT_EVQ_V2_IN_TMR_TRIG_START 0x28585/* enum: Hold-off */8586#define MC_CMD_INIT_EVQ_V2_IN_TMR_INT_HLDOFF 0x38587/* Target EVQ for wakeups if in wakeup mode. */8588#define MC_CMD_INIT_EVQ_V2_IN_TARGET_EVQ_OFST 248589#define MC_CMD_INIT_EVQ_V2_IN_TARGET_EVQ_LEN 48590/* Target interrupt if in interrupting mode (note union with target EVQ). Use8591 * MC_CMD_RESOURCE_INSTANCE_ANY unless a specific one required for test8592 * purposes.8593 */8594#define MC_CMD_INIT_EVQ_V2_IN_IRQ_NUM_OFST 248595#define MC_CMD_INIT_EVQ_V2_IN_IRQ_NUM_LEN 48596/* Event Counter Mode. */8597#define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_OFST 288598#define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_LEN 48599/* enum: Disabled */8600#define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_DIS 0x08601/* enum: Disabled */8602#define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_RX 0x18603/* enum: Disabled */8604#define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_TX 0x28605/* enum: Disabled */8606#define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_RXTX 0x38607/* Event queue packet count threshold. */8608#define MC_CMD_INIT_EVQ_V2_IN_COUNT_THRSHLD_OFST 328609#define MC_CMD_INIT_EVQ_V2_IN_COUNT_THRSHLD_LEN 48610/* 64-bit address of 4k of 4k-aligned host memory buffer */8611#define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_OFST 368612#define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_LEN 88613#define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_LO_OFST 368614#define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_HI_OFST 408615#define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_MINNUM 18616#define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_MAXNUM 648617#define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_MAXNUM_MCDI2 648618 8619/* MC_CMD_INIT_EVQ_V2_OUT msgresponse */8620#define MC_CMD_INIT_EVQ_V2_OUT_LEN 88621/* Only valid if INTRFLAG was true */8622#define MC_CMD_INIT_EVQ_V2_OUT_IRQ_OFST 08623#define MC_CMD_INIT_EVQ_V2_OUT_IRQ_LEN 48624/* Actual configuration applied on the card */8625#define MC_CMD_INIT_EVQ_V2_OUT_FLAGS_OFST 48626#define MC_CMD_INIT_EVQ_V2_OUT_FLAGS_LEN 48627#define MC_CMD_INIT_EVQ_V2_OUT_FLAG_CUT_THRU_OFST 48628#define MC_CMD_INIT_EVQ_V2_OUT_FLAG_CUT_THRU_LBN 08629#define MC_CMD_INIT_EVQ_V2_OUT_FLAG_CUT_THRU_WIDTH 18630#define MC_CMD_INIT_EVQ_V2_OUT_FLAG_RX_MERGE_OFST 48631#define MC_CMD_INIT_EVQ_V2_OUT_FLAG_RX_MERGE_LBN 18632#define MC_CMD_INIT_EVQ_V2_OUT_FLAG_RX_MERGE_WIDTH 18633#define MC_CMD_INIT_EVQ_V2_OUT_FLAG_TX_MERGE_OFST 48634#define MC_CMD_INIT_EVQ_V2_OUT_FLAG_TX_MERGE_LBN 28635#define MC_CMD_INIT_EVQ_V2_OUT_FLAG_TX_MERGE_WIDTH 18636#define MC_CMD_INIT_EVQ_V2_OUT_FLAG_RXQ_FORCE_EV_MERGING_OFST 48637#define MC_CMD_INIT_EVQ_V2_OUT_FLAG_RXQ_FORCE_EV_MERGING_LBN 38638#define MC_CMD_INIT_EVQ_V2_OUT_FLAG_RXQ_FORCE_EV_MERGING_WIDTH 18639 8640/* QUEUE_CRC_MODE structuredef */8641#define QUEUE_CRC_MODE_LEN 18642#define QUEUE_CRC_MODE_MODE_LBN 08643#define QUEUE_CRC_MODE_MODE_WIDTH 48644/* enum: No CRC. */8645#define QUEUE_CRC_MODE_NONE 0x08646/* enum: CRC Fiber channel over ethernet. */8647#define QUEUE_CRC_MODE_FCOE 0x18648/* enum: CRC (digest) iSCSI header only. */8649#define QUEUE_CRC_MODE_ISCSI_HDR 0x28650/* enum: CRC (digest) iSCSI header and payload. */8651#define QUEUE_CRC_MODE_ISCSI 0x38652/* enum: CRC Fiber channel over IP over ethernet. */8653#define QUEUE_CRC_MODE_FCOIPOE 0x48654/* enum: CRC MPA. */8655#define QUEUE_CRC_MODE_MPA 0x58656#define QUEUE_CRC_MODE_SPARE_LBN 48657#define QUEUE_CRC_MODE_SPARE_WIDTH 48658 8659 8660/***********************************/8661/* MC_CMD_INIT_RXQ8662 * set up a receive queue according to the supplied parameters. The IN8663 * arguments end with an address for each 4k of host memory required to back8664 * the RXQ.8665 */8666#define MC_CMD_INIT_RXQ 0x818667#undef MC_CMD_0x81_PRIVILEGE_CTG8668 8669#define MC_CMD_0x81_PRIVILEGE_CTG SRIOV_CTG_GENERAL8670 8671/* MC_CMD_INIT_RXQ_IN msgrequest: Legacy RXQ_INIT request. Use extended version8672 * in new code.8673 */8674#define MC_CMD_INIT_RXQ_IN_LENMIN 368675#define MC_CMD_INIT_RXQ_IN_LENMAX 2528676#define MC_CMD_INIT_RXQ_IN_LENMAX_MCDI2 10208677#define MC_CMD_INIT_RXQ_IN_LEN(num) (28+8*(num))8678#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_NUM(len) (((len)-28)/8)8679/* Size, in entries */8680#define MC_CMD_INIT_RXQ_IN_SIZE_OFST 08681#define MC_CMD_INIT_RXQ_IN_SIZE_LEN 48682/* The EVQ to send events to. This is an index originally specified to INIT_EVQ8683 */8684#define MC_CMD_INIT_RXQ_IN_TARGET_EVQ_OFST 48685#define MC_CMD_INIT_RXQ_IN_TARGET_EVQ_LEN 48686/* The value to put in the event data. Check hardware spec. for valid range. */8687#define MC_CMD_INIT_RXQ_IN_LABEL_OFST 88688#define MC_CMD_INIT_RXQ_IN_LABEL_LEN 48689/* Desired instance. Must be set to a specific instance, which is a function8690 * local queue index.8691 */8692#define MC_CMD_INIT_RXQ_IN_INSTANCE_OFST 128693#define MC_CMD_INIT_RXQ_IN_INSTANCE_LEN 48694/* There will be more flags here. */8695#define MC_CMD_INIT_RXQ_IN_FLAGS_OFST 168696#define MC_CMD_INIT_RXQ_IN_FLAGS_LEN 48697#define MC_CMD_INIT_RXQ_IN_FLAG_BUFF_MODE_OFST 168698#define MC_CMD_INIT_RXQ_IN_FLAG_BUFF_MODE_LBN 08699#define MC_CMD_INIT_RXQ_IN_FLAG_BUFF_MODE_WIDTH 18700#define MC_CMD_INIT_RXQ_IN_FLAG_HDR_SPLIT_OFST 168701#define MC_CMD_INIT_RXQ_IN_FLAG_HDR_SPLIT_LBN 18702#define MC_CMD_INIT_RXQ_IN_FLAG_HDR_SPLIT_WIDTH 18703#define MC_CMD_INIT_RXQ_IN_FLAG_TIMESTAMP_OFST 168704#define MC_CMD_INIT_RXQ_IN_FLAG_TIMESTAMP_LBN 28705#define MC_CMD_INIT_RXQ_IN_FLAG_TIMESTAMP_WIDTH 18706#define MC_CMD_INIT_RXQ_IN_CRC_MODE_OFST 168707#define MC_CMD_INIT_RXQ_IN_CRC_MODE_LBN 38708#define MC_CMD_INIT_RXQ_IN_CRC_MODE_WIDTH 48709#define MC_CMD_INIT_RXQ_IN_FLAG_CHAIN_OFST 168710#define MC_CMD_INIT_RXQ_IN_FLAG_CHAIN_LBN 78711#define MC_CMD_INIT_RXQ_IN_FLAG_CHAIN_WIDTH 18712#define MC_CMD_INIT_RXQ_IN_FLAG_PREFIX_OFST 168713#define MC_CMD_INIT_RXQ_IN_FLAG_PREFIX_LBN 88714#define MC_CMD_INIT_RXQ_IN_FLAG_PREFIX_WIDTH 18715#define MC_CMD_INIT_RXQ_IN_FLAG_DISABLE_SCATTER_OFST 168716#define MC_CMD_INIT_RXQ_IN_FLAG_DISABLE_SCATTER_LBN 98717#define MC_CMD_INIT_RXQ_IN_FLAG_DISABLE_SCATTER_WIDTH 18718#define MC_CMD_INIT_RXQ_IN_UNUSED_OFST 168719#define MC_CMD_INIT_RXQ_IN_UNUSED_LBN 108720#define MC_CMD_INIT_RXQ_IN_UNUSED_WIDTH 18721/* Owner ID to use if in buffer mode (zero if physical) */8722#define MC_CMD_INIT_RXQ_IN_OWNER_ID_OFST 208723#define MC_CMD_INIT_RXQ_IN_OWNER_ID_LEN 48724/* The port ID associated with the v-adaptor which should contain this DMAQ. */8725#define MC_CMD_INIT_RXQ_IN_PORT_ID_OFST 248726#define MC_CMD_INIT_RXQ_IN_PORT_ID_LEN 48727/* 64-bit address of 4k of 4k-aligned host memory buffer */8728#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_OFST 288729#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_LEN 88730#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_LO_OFST 288731#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_HI_OFST 328732#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_MINNUM 18733#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_MAXNUM 288734#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_MAXNUM_MCDI2 1248735 8736/* MC_CMD_INIT_RXQ_EXT_IN msgrequest: Extended RXQ_INIT with additional mode8737 * flags8738 */8739#define MC_CMD_INIT_RXQ_EXT_IN_LEN 5448740/* Size, in entries */8741#define MC_CMD_INIT_RXQ_EXT_IN_SIZE_OFST 08742#define MC_CMD_INIT_RXQ_EXT_IN_SIZE_LEN 48743/* The EVQ to send events to. This is an index originally specified to8744 * INIT_EVQ. If DMA_MODE == PACKED_STREAM this must be equal to INSTANCE.8745 */8746#define MC_CMD_INIT_RXQ_EXT_IN_TARGET_EVQ_OFST 48747#define MC_CMD_INIT_RXQ_EXT_IN_TARGET_EVQ_LEN 48748/* The value to put in the event data. Check hardware spec. for valid range.8749 * This field is ignored if DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER or DMA_MODE8750 * == PACKED_STREAM.8751 */8752#define MC_CMD_INIT_RXQ_EXT_IN_LABEL_OFST 88753#define MC_CMD_INIT_RXQ_EXT_IN_LABEL_LEN 48754/* Desired instance. Must be set to a specific instance, which is a function8755 * local queue index.8756 */8757#define MC_CMD_INIT_RXQ_EXT_IN_INSTANCE_OFST 128758#define MC_CMD_INIT_RXQ_EXT_IN_INSTANCE_LEN 48759/* There will be more flags here. */8760#define MC_CMD_INIT_RXQ_EXT_IN_FLAGS_OFST 168761#define MC_CMD_INIT_RXQ_EXT_IN_FLAGS_LEN 48762#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_BUFF_MODE_OFST 168763#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_BUFF_MODE_LBN 08764#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_BUFF_MODE_WIDTH 18765#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_HDR_SPLIT_OFST 168766#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_HDR_SPLIT_LBN 18767#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_HDR_SPLIT_WIDTH 18768#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_TIMESTAMP_OFST 168769#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_TIMESTAMP_LBN 28770#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_TIMESTAMP_WIDTH 18771#define MC_CMD_INIT_RXQ_EXT_IN_CRC_MODE_OFST 168772#define MC_CMD_INIT_RXQ_EXT_IN_CRC_MODE_LBN 38773#define MC_CMD_INIT_RXQ_EXT_IN_CRC_MODE_WIDTH 48774#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_CHAIN_OFST 168775#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_CHAIN_LBN 78776#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_CHAIN_WIDTH 18777#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_PREFIX_OFST 168778#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_PREFIX_LBN 88779#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_PREFIX_WIDTH 18780#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_DISABLE_SCATTER_OFST 168781#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_DISABLE_SCATTER_LBN 98782#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_DISABLE_SCATTER_WIDTH 18783#define MC_CMD_INIT_RXQ_EXT_IN_DMA_MODE_OFST 168784#define MC_CMD_INIT_RXQ_EXT_IN_DMA_MODE_LBN 108785#define MC_CMD_INIT_RXQ_EXT_IN_DMA_MODE_WIDTH 48786/* enum: One packet per descriptor (for normal networking) */8787#define MC_CMD_INIT_RXQ_EXT_IN_SINGLE_PACKET 0x08788/* enum: Pack multiple packets into large descriptors (for SolarCapture) */8789#define MC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM 0x18790/* enum: Pack multiple packets into large descriptors using the format designed8791 * to maximise packet rate. This mode uses 1 "bucket" per descriptor with8792 * multiple fixed-size packet buffers within each bucket. For a full8793 * description see SF-119419-TC. This mode is only supported by "dpdk" datapath8794 * firmware.8795 */8796#define MC_CMD_INIT_RXQ_EXT_IN_EQUAL_STRIDE_SUPER_BUFFER 0x28797/* enum: Deprecated name for EQUAL_STRIDE_SUPER_BUFFER. */8798#define MC_CMD_INIT_RXQ_EXT_IN_EQUAL_STRIDE_PACKED_STREAM 0x28799#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_SNAPSHOT_MODE_OFST 168800#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_SNAPSHOT_MODE_LBN 148801#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_SNAPSHOT_MODE_WIDTH 18802#define MC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM_BUFF_SIZE_OFST 168803#define MC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM_BUFF_SIZE_LBN 158804#define MC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM_BUFF_SIZE_WIDTH 38805#define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_1M 0x0 /* enum */8806#define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_512K 0x1 /* enum */8807#define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_256K 0x2 /* enum */8808#define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_128K 0x3 /* enum */8809#define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_64K 0x4 /* enum */8810#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_WANT_OUTER_CLASSES_OFST 168811#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_WANT_OUTER_CLASSES_LBN 188812#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_WANT_OUTER_CLASSES_WIDTH 18813#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_FORCE_EV_MERGING_OFST 168814#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_FORCE_EV_MERGING_LBN 198815#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_FORCE_EV_MERGING_WIDTH 18816#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_NO_CONT_EV_OFST 168817#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_NO_CONT_EV_LBN 208818#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_NO_CONT_EV_WIDTH 18819/* Owner ID to use if in buffer mode (zero if physical) */8820#define MC_CMD_INIT_RXQ_EXT_IN_OWNER_ID_OFST 208821#define MC_CMD_INIT_RXQ_EXT_IN_OWNER_ID_LEN 48822/* The port ID associated with the v-adaptor which should contain this DMAQ. */8823#define MC_CMD_INIT_RXQ_EXT_IN_PORT_ID_OFST 248824#define MC_CMD_INIT_RXQ_EXT_IN_PORT_ID_LEN 48825/* 64-bit address of 4k of 4k-aligned host memory buffer */8826#define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_OFST 288827#define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_LEN 88828#define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_LO_OFST 288829#define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_HI_OFST 328830#define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_NUM 648831/* Maximum length of packet to receive, if SNAPSHOT_MODE flag is set */8832#define MC_CMD_INIT_RXQ_EXT_IN_SNAPSHOT_LENGTH_OFST 5408833#define MC_CMD_INIT_RXQ_EXT_IN_SNAPSHOT_LENGTH_LEN 48834 8835/* MC_CMD_INIT_RXQ_V3_IN msgrequest */8836#define MC_CMD_INIT_RXQ_V3_IN_LEN 5608837/* Size, in entries */8838#define MC_CMD_INIT_RXQ_V3_IN_SIZE_OFST 08839#define MC_CMD_INIT_RXQ_V3_IN_SIZE_LEN 48840/* The EVQ to send events to. This is an index originally specified to8841 * INIT_EVQ. If DMA_MODE == PACKED_STREAM this must be equal to INSTANCE.8842 */8843#define MC_CMD_INIT_RXQ_V3_IN_TARGET_EVQ_OFST 48844#define MC_CMD_INIT_RXQ_V3_IN_TARGET_EVQ_LEN 48845/* The value to put in the event data. Check hardware spec. for valid range.8846 * This field is ignored if DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER or DMA_MODE8847 * == PACKED_STREAM.8848 */8849#define MC_CMD_INIT_RXQ_V3_IN_LABEL_OFST 88850#define MC_CMD_INIT_RXQ_V3_IN_LABEL_LEN 48851/* Desired instance. Must be set to a specific instance, which is a function8852 * local queue index.8853 */8854#define MC_CMD_INIT_RXQ_V3_IN_INSTANCE_OFST 128855#define MC_CMD_INIT_RXQ_V3_IN_INSTANCE_LEN 48856/* There will be more flags here. */8857#define MC_CMD_INIT_RXQ_V3_IN_FLAGS_OFST 168858#define MC_CMD_INIT_RXQ_V3_IN_FLAGS_LEN 48859#define MC_CMD_INIT_RXQ_V3_IN_FLAG_BUFF_MODE_OFST 168860#define MC_CMD_INIT_RXQ_V3_IN_FLAG_BUFF_MODE_LBN 08861#define MC_CMD_INIT_RXQ_V3_IN_FLAG_BUFF_MODE_WIDTH 18862#define MC_CMD_INIT_RXQ_V3_IN_FLAG_HDR_SPLIT_OFST 168863#define MC_CMD_INIT_RXQ_V3_IN_FLAG_HDR_SPLIT_LBN 18864#define MC_CMD_INIT_RXQ_V3_IN_FLAG_HDR_SPLIT_WIDTH 18865#define MC_CMD_INIT_RXQ_V3_IN_FLAG_TIMESTAMP_OFST 168866#define MC_CMD_INIT_RXQ_V3_IN_FLAG_TIMESTAMP_LBN 28867#define MC_CMD_INIT_RXQ_V3_IN_FLAG_TIMESTAMP_WIDTH 18868#define MC_CMD_INIT_RXQ_V3_IN_CRC_MODE_OFST 168869#define MC_CMD_INIT_RXQ_V3_IN_CRC_MODE_LBN 38870#define MC_CMD_INIT_RXQ_V3_IN_CRC_MODE_WIDTH 48871#define MC_CMD_INIT_RXQ_V3_IN_FLAG_CHAIN_OFST 168872#define MC_CMD_INIT_RXQ_V3_IN_FLAG_CHAIN_LBN 78873#define MC_CMD_INIT_RXQ_V3_IN_FLAG_CHAIN_WIDTH 18874#define MC_CMD_INIT_RXQ_V3_IN_FLAG_PREFIX_OFST 168875#define MC_CMD_INIT_RXQ_V3_IN_FLAG_PREFIX_LBN 88876#define MC_CMD_INIT_RXQ_V3_IN_FLAG_PREFIX_WIDTH 18877#define MC_CMD_INIT_RXQ_V3_IN_FLAG_DISABLE_SCATTER_OFST 168878#define MC_CMD_INIT_RXQ_V3_IN_FLAG_DISABLE_SCATTER_LBN 98879#define MC_CMD_INIT_RXQ_V3_IN_FLAG_DISABLE_SCATTER_WIDTH 18880#define MC_CMD_INIT_RXQ_V3_IN_DMA_MODE_OFST 168881#define MC_CMD_INIT_RXQ_V3_IN_DMA_MODE_LBN 108882#define MC_CMD_INIT_RXQ_V3_IN_DMA_MODE_WIDTH 48883/* enum: One packet per descriptor (for normal networking) */8884#define MC_CMD_INIT_RXQ_V3_IN_SINGLE_PACKET 0x08885/* enum: Pack multiple packets into large descriptors (for SolarCapture) */8886#define MC_CMD_INIT_RXQ_V3_IN_PACKED_STREAM 0x18887/* enum: Pack multiple packets into large descriptors using the format designed8888 * to maximise packet rate. This mode uses 1 "bucket" per descriptor with8889 * multiple fixed-size packet buffers within each bucket. For a full8890 * description see SF-119419-TC. This mode is only supported by "dpdk" datapath8891 * firmware.8892 */8893#define MC_CMD_INIT_RXQ_V3_IN_EQUAL_STRIDE_SUPER_BUFFER 0x28894/* enum: Deprecated name for EQUAL_STRIDE_SUPER_BUFFER. */8895#define MC_CMD_INIT_RXQ_V3_IN_EQUAL_STRIDE_PACKED_STREAM 0x28896#define MC_CMD_INIT_RXQ_V3_IN_FLAG_SNAPSHOT_MODE_OFST 168897#define MC_CMD_INIT_RXQ_V3_IN_FLAG_SNAPSHOT_MODE_LBN 148898#define MC_CMD_INIT_RXQ_V3_IN_FLAG_SNAPSHOT_MODE_WIDTH 18899#define MC_CMD_INIT_RXQ_V3_IN_PACKED_STREAM_BUFF_SIZE_OFST 168900#define MC_CMD_INIT_RXQ_V3_IN_PACKED_STREAM_BUFF_SIZE_LBN 158901#define MC_CMD_INIT_RXQ_V3_IN_PACKED_STREAM_BUFF_SIZE_WIDTH 38902#define MC_CMD_INIT_RXQ_V3_IN_PS_BUFF_1M 0x0 /* enum */8903#define MC_CMD_INIT_RXQ_V3_IN_PS_BUFF_512K 0x1 /* enum */8904#define MC_CMD_INIT_RXQ_V3_IN_PS_BUFF_256K 0x2 /* enum */8905#define MC_CMD_INIT_RXQ_V3_IN_PS_BUFF_128K 0x3 /* enum */8906#define MC_CMD_INIT_RXQ_V3_IN_PS_BUFF_64K 0x4 /* enum */8907#define MC_CMD_INIT_RXQ_V3_IN_FLAG_WANT_OUTER_CLASSES_OFST 168908#define MC_CMD_INIT_RXQ_V3_IN_FLAG_WANT_OUTER_CLASSES_LBN 188909#define MC_CMD_INIT_RXQ_V3_IN_FLAG_WANT_OUTER_CLASSES_WIDTH 18910#define MC_CMD_INIT_RXQ_V3_IN_FLAG_FORCE_EV_MERGING_OFST 168911#define MC_CMD_INIT_RXQ_V3_IN_FLAG_FORCE_EV_MERGING_LBN 198912#define MC_CMD_INIT_RXQ_V3_IN_FLAG_FORCE_EV_MERGING_WIDTH 18913#define MC_CMD_INIT_RXQ_V3_IN_FLAG_NO_CONT_EV_OFST 168914#define MC_CMD_INIT_RXQ_V3_IN_FLAG_NO_CONT_EV_LBN 208915#define MC_CMD_INIT_RXQ_V3_IN_FLAG_NO_CONT_EV_WIDTH 18916/* Owner ID to use if in buffer mode (zero if physical) */8917#define MC_CMD_INIT_RXQ_V3_IN_OWNER_ID_OFST 208918#define MC_CMD_INIT_RXQ_V3_IN_OWNER_ID_LEN 48919/* The port ID associated with the v-adaptor which should contain this DMAQ. */8920#define MC_CMD_INIT_RXQ_V3_IN_PORT_ID_OFST 248921#define MC_CMD_INIT_RXQ_V3_IN_PORT_ID_LEN 48922/* 64-bit address of 4k of 4k-aligned host memory buffer */8923#define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_OFST 288924#define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_LEN 88925#define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_LO_OFST 288926#define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_HI_OFST 328927#define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_NUM 648928/* Maximum length of packet to receive, if SNAPSHOT_MODE flag is set */8929#define MC_CMD_INIT_RXQ_V3_IN_SNAPSHOT_LENGTH_OFST 5408930#define MC_CMD_INIT_RXQ_V3_IN_SNAPSHOT_LENGTH_LEN 48931/* The number of packet buffers that will be contained within each8932 * EQUAL_STRIDE_SUPER_BUFFER format bucket supplied by the driver. This field8933 * is ignored unless DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER.8934 */8935#define MC_CMD_INIT_RXQ_V3_IN_ES_PACKET_BUFFERS_PER_BUCKET_OFST 5448936#define MC_CMD_INIT_RXQ_V3_IN_ES_PACKET_BUFFERS_PER_BUCKET_LEN 48937/* The length in bytes of the area in each packet buffer that can be written to8938 * by the adapter. This is used to store the packet prefix and the packet8939 * payload. This length does not include any end padding added by the driver.8940 * This field is ignored unless DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER.8941 */8942#define MC_CMD_INIT_RXQ_V3_IN_ES_MAX_DMA_LEN_OFST 5488943#define MC_CMD_INIT_RXQ_V3_IN_ES_MAX_DMA_LEN_LEN 48944/* The length in bytes of a single packet buffer within a8945 * EQUAL_STRIDE_SUPER_BUFFER format bucket. This field is ignored unless8946 * DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER.8947 */8948#define MC_CMD_INIT_RXQ_V3_IN_ES_PACKET_STRIDE_OFST 5528949#define MC_CMD_INIT_RXQ_V3_IN_ES_PACKET_STRIDE_LEN 48950/* The maximum time in nanoseconds that the datapath will be backpressured if8951 * there are no RX descriptors available. If the timeout is reached and there8952 * are still no descriptors then the packet will be dropped. A timeout of 08953 * means the datapath will never be blocked. This field is ignored unless8954 * DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER.8955 */8956#define MC_CMD_INIT_RXQ_V3_IN_ES_HEAD_OF_LINE_BLOCK_TIMEOUT_OFST 5568957#define MC_CMD_INIT_RXQ_V3_IN_ES_HEAD_OF_LINE_BLOCK_TIMEOUT_LEN 48958 8959/* MC_CMD_INIT_RXQ_V4_IN msgrequest: INIT_RXQ request with new field required8960 * for systems with a QDMA (currently, Riverhead)8961 */8962#define MC_CMD_INIT_RXQ_V4_IN_LEN 5648963/* Size, in entries */8964#define MC_CMD_INIT_RXQ_V4_IN_SIZE_OFST 08965#define MC_CMD_INIT_RXQ_V4_IN_SIZE_LEN 48966/* The EVQ to send events to. This is an index originally specified to8967 * INIT_EVQ. If DMA_MODE == PACKED_STREAM this must be equal to INSTANCE.8968 */8969#define MC_CMD_INIT_RXQ_V4_IN_TARGET_EVQ_OFST 48970#define MC_CMD_INIT_RXQ_V4_IN_TARGET_EVQ_LEN 48971/* The value to put in the event data. Check hardware spec. for valid range.8972 * This field is ignored if DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER or DMA_MODE8973 * == PACKED_STREAM.8974 */8975#define MC_CMD_INIT_RXQ_V4_IN_LABEL_OFST 88976#define MC_CMD_INIT_RXQ_V4_IN_LABEL_LEN 48977/* Desired instance. Must be set to a specific instance, which is a function8978 * local queue index.8979 */8980#define MC_CMD_INIT_RXQ_V4_IN_INSTANCE_OFST 128981#define MC_CMD_INIT_RXQ_V4_IN_INSTANCE_LEN 48982/* There will be more flags here. */8983#define MC_CMD_INIT_RXQ_V4_IN_FLAGS_OFST 168984#define MC_CMD_INIT_RXQ_V4_IN_FLAGS_LEN 48985#define MC_CMD_INIT_RXQ_V4_IN_FLAG_BUFF_MODE_OFST 168986#define MC_CMD_INIT_RXQ_V4_IN_FLAG_BUFF_MODE_LBN 08987#define MC_CMD_INIT_RXQ_V4_IN_FLAG_BUFF_MODE_WIDTH 18988#define MC_CMD_INIT_RXQ_V4_IN_FLAG_HDR_SPLIT_OFST 168989#define MC_CMD_INIT_RXQ_V4_IN_FLAG_HDR_SPLIT_LBN 18990#define MC_CMD_INIT_RXQ_V4_IN_FLAG_HDR_SPLIT_WIDTH 18991#define MC_CMD_INIT_RXQ_V4_IN_FLAG_TIMESTAMP_OFST 168992#define MC_CMD_INIT_RXQ_V4_IN_FLAG_TIMESTAMP_LBN 28993#define MC_CMD_INIT_RXQ_V4_IN_FLAG_TIMESTAMP_WIDTH 18994#define MC_CMD_INIT_RXQ_V4_IN_CRC_MODE_OFST 168995#define MC_CMD_INIT_RXQ_V4_IN_CRC_MODE_LBN 38996#define MC_CMD_INIT_RXQ_V4_IN_CRC_MODE_WIDTH 48997#define MC_CMD_INIT_RXQ_V4_IN_FLAG_CHAIN_OFST 168998#define MC_CMD_INIT_RXQ_V4_IN_FLAG_CHAIN_LBN 78999#define MC_CMD_INIT_RXQ_V4_IN_FLAG_CHAIN_WIDTH 19000#define MC_CMD_INIT_RXQ_V4_IN_FLAG_PREFIX_OFST 169001#define MC_CMD_INIT_RXQ_V4_IN_FLAG_PREFIX_LBN 89002#define MC_CMD_INIT_RXQ_V4_IN_FLAG_PREFIX_WIDTH 19003#define MC_CMD_INIT_RXQ_V4_IN_FLAG_DISABLE_SCATTER_OFST 169004#define MC_CMD_INIT_RXQ_V4_IN_FLAG_DISABLE_SCATTER_LBN 99005#define MC_CMD_INIT_RXQ_V4_IN_FLAG_DISABLE_SCATTER_WIDTH 19006#define MC_CMD_INIT_RXQ_V4_IN_DMA_MODE_OFST 169007#define MC_CMD_INIT_RXQ_V4_IN_DMA_MODE_LBN 109008#define MC_CMD_INIT_RXQ_V4_IN_DMA_MODE_WIDTH 49009/* enum: One packet per descriptor (for normal networking) */9010#define MC_CMD_INIT_RXQ_V4_IN_SINGLE_PACKET 0x09011/* enum: Pack multiple packets into large descriptors (for SolarCapture) */9012#define MC_CMD_INIT_RXQ_V4_IN_PACKED_STREAM 0x19013/* enum: Pack multiple packets into large descriptors using the format designed9014 * to maximise packet rate. This mode uses 1 "bucket" per descriptor with9015 * multiple fixed-size packet buffers within each bucket. For a full9016 * description see SF-119419-TC. This mode is only supported by "dpdk" datapath9017 * firmware.9018 */9019#define MC_CMD_INIT_RXQ_V4_IN_EQUAL_STRIDE_SUPER_BUFFER 0x29020/* enum: Deprecated name for EQUAL_STRIDE_SUPER_BUFFER. */9021#define MC_CMD_INIT_RXQ_V4_IN_EQUAL_STRIDE_PACKED_STREAM 0x29022#define MC_CMD_INIT_RXQ_V4_IN_FLAG_SNAPSHOT_MODE_OFST 169023#define MC_CMD_INIT_RXQ_V4_IN_FLAG_SNAPSHOT_MODE_LBN 149024#define MC_CMD_INIT_RXQ_V4_IN_FLAG_SNAPSHOT_MODE_WIDTH 19025#define MC_CMD_INIT_RXQ_V4_IN_PACKED_STREAM_BUFF_SIZE_OFST 169026#define MC_CMD_INIT_RXQ_V4_IN_PACKED_STREAM_BUFF_SIZE_LBN 159027#define MC_CMD_INIT_RXQ_V4_IN_PACKED_STREAM_BUFF_SIZE_WIDTH 39028#define MC_CMD_INIT_RXQ_V4_IN_PS_BUFF_1M 0x0 /* enum */9029#define MC_CMD_INIT_RXQ_V4_IN_PS_BUFF_512K 0x1 /* enum */9030#define MC_CMD_INIT_RXQ_V4_IN_PS_BUFF_256K 0x2 /* enum */9031#define MC_CMD_INIT_RXQ_V4_IN_PS_BUFF_128K 0x3 /* enum */9032#define MC_CMD_INIT_RXQ_V4_IN_PS_BUFF_64K 0x4 /* enum */9033#define MC_CMD_INIT_RXQ_V4_IN_FLAG_WANT_OUTER_CLASSES_OFST 169034#define MC_CMD_INIT_RXQ_V4_IN_FLAG_WANT_OUTER_CLASSES_LBN 189035#define MC_CMD_INIT_RXQ_V4_IN_FLAG_WANT_OUTER_CLASSES_WIDTH 19036#define MC_CMD_INIT_RXQ_V4_IN_FLAG_FORCE_EV_MERGING_OFST 169037#define MC_CMD_INIT_RXQ_V4_IN_FLAG_FORCE_EV_MERGING_LBN 199038#define MC_CMD_INIT_RXQ_V4_IN_FLAG_FORCE_EV_MERGING_WIDTH 19039#define MC_CMD_INIT_RXQ_V4_IN_FLAG_NO_CONT_EV_OFST 169040#define MC_CMD_INIT_RXQ_V4_IN_FLAG_NO_CONT_EV_LBN 209041#define MC_CMD_INIT_RXQ_V4_IN_FLAG_NO_CONT_EV_WIDTH 19042/* Owner ID to use if in buffer mode (zero if physical) */9043#define MC_CMD_INIT_RXQ_V4_IN_OWNER_ID_OFST 209044#define MC_CMD_INIT_RXQ_V4_IN_OWNER_ID_LEN 49045/* The port ID associated with the v-adaptor which should contain this DMAQ. */9046#define MC_CMD_INIT_RXQ_V4_IN_PORT_ID_OFST 249047#define MC_CMD_INIT_RXQ_V4_IN_PORT_ID_LEN 49048/* 64-bit address of 4k of 4k-aligned host memory buffer */9049#define MC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_OFST 289050#define MC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_LEN 89051#define MC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_LO_OFST 289052#define MC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_HI_OFST 329053#define MC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_NUM 649054/* Maximum length of packet to receive, if SNAPSHOT_MODE flag is set */9055#define MC_CMD_INIT_RXQ_V4_IN_SNAPSHOT_LENGTH_OFST 5409056#define MC_CMD_INIT_RXQ_V4_IN_SNAPSHOT_LENGTH_LEN 49057/* The number of packet buffers that will be contained within each9058 * EQUAL_STRIDE_SUPER_BUFFER format bucket supplied by the driver. This field9059 * is ignored unless DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER.9060 */9061#define MC_CMD_INIT_RXQ_V4_IN_ES_PACKET_BUFFERS_PER_BUCKET_OFST 5449062#define MC_CMD_INIT_RXQ_V4_IN_ES_PACKET_BUFFERS_PER_BUCKET_LEN 49063/* The length in bytes of the area in each packet buffer that can be written to9064 * by the adapter. This is used to store the packet prefix and the packet9065 * payload. This length does not include any end padding added by the driver.9066 * This field is ignored unless DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER.9067 */9068#define MC_CMD_INIT_RXQ_V4_IN_ES_MAX_DMA_LEN_OFST 5489069#define MC_CMD_INIT_RXQ_V4_IN_ES_MAX_DMA_LEN_LEN 49070/* The length in bytes of a single packet buffer within a9071 * EQUAL_STRIDE_SUPER_BUFFER format bucket. This field is ignored unless9072 * DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER.9073 */9074#define MC_CMD_INIT_RXQ_V4_IN_ES_PACKET_STRIDE_OFST 5529075#define MC_CMD_INIT_RXQ_V4_IN_ES_PACKET_STRIDE_LEN 49076/* The maximum time in nanoseconds that the datapath will be backpressured if9077 * there are no RX descriptors available. If the timeout is reached and there9078 * are still no descriptors then the packet will be dropped. A timeout of 09079 * means the datapath will never be blocked. This field is ignored unless9080 * DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER.9081 */9082#define MC_CMD_INIT_RXQ_V4_IN_ES_HEAD_OF_LINE_BLOCK_TIMEOUT_OFST 5569083#define MC_CMD_INIT_RXQ_V4_IN_ES_HEAD_OF_LINE_BLOCK_TIMEOUT_LEN 49084/* V4 message data */9085#define MC_CMD_INIT_RXQ_V4_IN_V4_DATA_OFST 5609086#define MC_CMD_INIT_RXQ_V4_IN_V4_DATA_LEN 49087/* Size in bytes of buffers attached to descriptors posted to this queue. Set9088 * to zero if using this message on non-QDMA based platforms. Currently in9089 * Riverhead there is a global limit of eight different buffer sizes across all9090 * active queues. A 2KB and 4KB buffer is guaranteed to be available, but a9091 * request for a different buffer size will fail if there are already eight9092 * other buffer sizes in use. In future Riverhead this limit will go away and9093 * any size will be accepted.9094 */9095#define MC_CMD_INIT_RXQ_V4_IN_BUFFER_SIZE_BYTES_OFST 5609096#define MC_CMD_INIT_RXQ_V4_IN_BUFFER_SIZE_BYTES_LEN 49097 9098/* MC_CMD_INIT_RXQ_V5_IN msgrequest: INIT_RXQ request with ability to request a9099 * different RX packet prefix9100 */9101#define MC_CMD_INIT_RXQ_V5_IN_LEN 5689102/* Size, in entries */9103#define MC_CMD_INIT_RXQ_V5_IN_SIZE_OFST 09104#define MC_CMD_INIT_RXQ_V5_IN_SIZE_LEN 49105/* The EVQ to send events to. This is an index originally specified to9106 * INIT_EVQ. If DMA_MODE == PACKED_STREAM this must be equal to INSTANCE.9107 */9108#define MC_CMD_INIT_RXQ_V5_IN_TARGET_EVQ_OFST 49109#define MC_CMD_INIT_RXQ_V5_IN_TARGET_EVQ_LEN 49110/* The value to put in the event data. Check hardware spec. for valid range.9111 * This field is ignored if DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER or DMA_MODE9112 * == PACKED_STREAM.9113 */9114#define MC_CMD_INIT_RXQ_V5_IN_LABEL_OFST 89115#define MC_CMD_INIT_RXQ_V5_IN_LABEL_LEN 49116/* Desired instance. Must be set to a specific instance, which is a function9117 * local queue index.9118 */9119#define MC_CMD_INIT_RXQ_V5_IN_INSTANCE_OFST 129120#define MC_CMD_INIT_RXQ_V5_IN_INSTANCE_LEN 49121/* There will be more flags here. */9122#define MC_CMD_INIT_RXQ_V5_IN_FLAGS_OFST 169123#define MC_CMD_INIT_RXQ_V5_IN_FLAGS_LEN 49124#define MC_CMD_INIT_RXQ_V5_IN_FLAG_BUFF_MODE_OFST 169125#define MC_CMD_INIT_RXQ_V5_IN_FLAG_BUFF_MODE_LBN 09126#define MC_CMD_INIT_RXQ_V5_IN_FLAG_BUFF_MODE_WIDTH 19127#define MC_CMD_INIT_RXQ_V5_IN_FLAG_HDR_SPLIT_OFST 169128#define MC_CMD_INIT_RXQ_V5_IN_FLAG_HDR_SPLIT_LBN 19129#define MC_CMD_INIT_RXQ_V5_IN_FLAG_HDR_SPLIT_WIDTH 19130#define MC_CMD_INIT_RXQ_V5_IN_FLAG_TIMESTAMP_OFST 169131#define MC_CMD_INIT_RXQ_V5_IN_FLAG_TIMESTAMP_LBN 29132#define MC_CMD_INIT_RXQ_V5_IN_FLAG_TIMESTAMP_WIDTH 19133#define MC_CMD_INIT_RXQ_V5_IN_CRC_MODE_OFST 169134#define MC_CMD_INIT_RXQ_V5_IN_CRC_MODE_LBN 39135#define MC_CMD_INIT_RXQ_V5_IN_CRC_MODE_WIDTH 49136#define MC_CMD_INIT_RXQ_V5_IN_FLAG_CHAIN_OFST 169137#define MC_CMD_INIT_RXQ_V5_IN_FLAG_CHAIN_LBN 79138#define MC_CMD_INIT_RXQ_V5_IN_FLAG_CHAIN_WIDTH 19139#define MC_CMD_INIT_RXQ_V5_IN_FLAG_PREFIX_OFST 169140#define MC_CMD_INIT_RXQ_V5_IN_FLAG_PREFIX_LBN 89141#define MC_CMD_INIT_RXQ_V5_IN_FLAG_PREFIX_WIDTH 19142#define MC_CMD_INIT_RXQ_V5_IN_FLAG_DISABLE_SCATTER_OFST 169143#define MC_CMD_INIT_RXQ_V5_IN_FLAG_DISABLE_SCATTER_LBN 99144#define MC_CMD_INIT_RXQ_V5_IN_FLAG_DISABLE_SCATTER_WIDTH 19145#define MC_CMD_INIT_RXQ_V5_IN_DMA_MODE_OFST 169146#define MC_CMD_INIT_RXQ_V5_IN_DMA_MODE_LBN 109147#define MC_CMD_INIT_RXQ_V5_IN_DMA_MODE_WIDTH 49148/* enum: One packet per descriptor (for normal networking) */9149#define MC_CMD_INIT_RXQ_V5_IN_SINGLE_PACKET 0x09150/* enum: Pack multiple packets into large descriptors (for SolarCapture) */9151#define MC_CMD_INIT_RXQ_V5_IN_PACKED_STREAM 0x19152/* enum: Pack multiple packets into large descriptors using the format designed9153 * to maximise packet rate. This mode uses 1 "bucket" per descriptor with9154 * multiple fixed-size packet buffers within each bucket. For a full9155 * description see SF-119419-TC. This mode is only supported by "dpdk" datapath9156 * firmware.9157 */9158#define MC_CMD_INIT_RXQ_V5_IN_EQUAL_STRIDE_SUPER_BUFFER 0x29159/* enum: Deprecated name for EQUAL_STRIDE_SUPER_BUFFER. */9160#define MC_CMD_INIT_RXQ_V5_IN_EQUAL_STRIDE_PACKED_STREAM 0x29161#define MC_CMD_INIT_RXQ_V5_IN_FLAG_SNAPSHOT_MODE_OFST 169162#define MC_CMD_INIT_RXQ_V5_IN_FLAG_SNAPSHOT_MODE_LBN 149163#define MC_CMD_INIT_RXQ_V5_IN_FLAG_SNAPSHOT_MODE_WIDTH 19164#define MC_CMD_INIT_RXQ_V5_IN_PACKED_STREAM_BUFF_SIZE_OFST 169165#define MC_CMD_INIT_RXQ_V5_IN_PACKED_STREAM_BUFF_SIZE_LBN 159166#define MC_CMD_INIT_RXQ_V5_IN_PACKED_STREAM_BUFF_SIZE_WIDTH 39167#define MC_CMD_INIT_RXQ_V5_IN_PS_BUFF_1M 0x0 /* enum */9168#define MC_CMD_INIT_RXQ_V5_IN_PS_BUFF_512K 0x1 /* enum */9169#define MC_CMD_INIT_RXQ_V5_IN_PS_BUFF_256K 0x2 /* enum */9170#define MC_CMD_INIT_RXQ_V5_IN_PS_BUFF_128K 0x3 /* enum */9171#define MC_CMD_INIT_RXQ_V5_IN_PS_BUFF_64K 0x4 /* enum */9172#define MC_CMD_INIT_RXQ_V5_IN_FLAG_WANT_OUTER_CLASSES_OFST 169173#define MC_CMD_INIT_RXQ_V5_IN_FLAG_WANT_OUTER_CLASSES_LBN 189174#define MC_CMD_INIT_RXQ_V5_IN_FLAG_WANT_OUTER_CLASSES_WIDTH 19175#define MC_CMD_INIT_RXQ_V5_IN_FLAG_FORCE_EV_MERGING_OFST 169176#define MC_CMD_INIT_RXQ_V5_IN_FLAG_FORCE_EV_MERGING_LBN 199177#define MC_CMD_INIT_RXQ_V5_IN_FLAG_FORCE_EV_MERGING_WIDTH 19178#define MC_CMD_INIT_RXQ_V5_IN_FLAG_NO_CONT_EV_OFST 169179#define MC_CMD_INIT_RXQ_V5_IN_FLAG_NO_CONT_EV_LBN 209180#define MC_CMD_INIT_RXQ_V5_IN_FLAG_NO_CONT_EV_WIDTH 19181/* Owner ID to use if in buffer mode (zero if physical) */9182#define MC_CMD_INIT_RXQ_V5_IN_OWNER_ID_OFST 209183#define MC_CMD_INIT_RXQ_V5_IN_OWNER_ID_LEN 49184/* The port ID associated with the v-adaptor which should contain this DMAQ. */9185#define MC_CMD_INIT_RXQ_V5_IN_PORT_ID_OFST 249186#define MC_CMD_INIT_RXQ_V5_IN_PORT_ID_LEN 49187/* 64-bit address of 4k of 4k-aligned host memory buffer */9188#define MC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_OFST 289189#define MC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_LEN 89190#define MC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_LO_OFST 289191#define MC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_HI_OFST 329192#define MC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_NUM 649193/* Maximum length of packet to receive, if SNAPSHOT_MODE flag is set */9194#define MC_CMD_INIT_RXQ_V5_IN_SNAPSHOT_LENGTH_OFST 5409195#define MC_CMD_INIT_RXQ_V5_IN_SNAPSHOT_LENGTH_LEN 49196/* The number of packet buffers that will be contained within each9197 * EQUAL_STRIDE_SUPER_BUFFER format bucket supplied by the driver. This field9198 * is ignored unless DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER.9199 */9200#define MC_CMD_INIT_RXQ_V5_IN_ES_PACKET_BUFFERS_PER_BUCKET_OFST 5449201#define MC_CMD_INIT_RXQ_V5_IN_ES_PACKET_BUFFERS_PER_BUCKET_LEN 49202/* The length in bytes of the area in each packet buffer that can be written to9203 * by the adapter. This is used to store the packet prefix and the packet9204 * payload. This length does not include any end padding added by the driver.9205 * This field is ignored unless DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER.9206 */9207#define MC_CMD_INIT_RXQ_V5_IN_ES_MAX_DMA_LEN_OFST 5489208#define MC_CMD_INIT_RXQ_V5_IN_ES_MAX_DMA_LEN_LEN 49209/* The length in bytes of a single packet buffer within a9210 * EQUAL_STRIDE_SUPER_BUFFER format bucket. This field is ignored unless9211 * DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER.9212 */9213#define MC_CMD_INIT_RXQ_V5_IN_ES_PACKET_STRIDE_OFST 5529214#define MC_CMD_INIT_RXQ_V5_IN_ES_PACKET_STRIDE_LEN 49215/* The maximum time in nanoseconds that the datapath will be backpressured if9216 * there are no RX descriptors available. If the timeout is reached and there9217 * are still no descriptors then the packet will be dropped. A timeout of 09218 * means the datapath will never be blocked. This field is ignored unless9219 * DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER.9220 */9221#define MC_CMD_INIT_RXQ_V5_IN_ES_HEAD_OF_LINE_BLOCK_TIMEOUT_OFST 5569222#define MC_CMD_INIT_RXQ_V5_IN_ES_HEAD_OF_LINE_BLOCK_TIMEOUT_LEN 49223/* V4 message data */9224#define MC_CMD_INIT_RXQ_V5_IN_V4_DATA_OFST 5609225#define MC_CMD_INIT_RXQ_V5_IN_V4_DATA_LEN 49226/* Size in bytes of buffers attached to descriptors posted to this queue. Set9227 * to zero if using this message on non-QDMA based platforms. Currently in9228 * Riverhead there is a global limit of eight different buffer sizes across all9229 * active queues. A 2KB and 4KB buffer is guaranteed to be available, but a9230 * request for a different buffer size will fail if there are already eight9231 * other buffer sizes in use. In future Riverhead this limit will go away and9232 * any size will be accepted.9233 */9234#define MC_CMD_INIT_RXQ_V5_IN_BUFFER_SIZE_BYTES_OFST 5609235#define MC_CMD_INIT_RXQ_V5_IN_BUFFER_SIZE_BYTES_LEN 49236/* Prefix id for the RX prefix format to use on packets delivered this queue.9237 * Zero is always a valid prefix id and means the default prefix format9238 * documented for the platform. Other prefix ids can be obtained by calling9239 * MC_CMD_GET_RX_PREFIX_ID with a requested set of prefix fields.9240 */9241#define MC_CMD_INIT_RXQ_V5_IN_RX_PREFIX_ID_OFST 5649242#define MC_CMD_INIT_RXQ_V5_IN_RX_PREFIX_ID_LEN 49243 9244/* MC_CMD_INIT_RXQ_OUT msgresponse */9245#define MC_CMD_INIT_RXQ_OUT_LEN 09246 9247/* MC_CMD_INIT_RXQ_EXT_OUT msgresponse */9248#define MC_CMD_INIT_RXQ_EXT_OUT_LEN 09249 9250/* MC_CMD_INIT_RXQ_V3_OUT msgresponse */9251#define MC_CMD_INIT_RXQ_V3_OUT_LEN 09252 9253/* MC_CMD_INIT_RXQ_V4_OUT msgresponse */9254#define MC_CMD_INIT_RXQ_V4_OUT_LEN 09255 9256/* MC_CMD_INIT_RXQ_V5_OUT msgresponse */9257#define MC_CMD_INIT_RXQ_V5_OUT_LEN 09258 9259 9260/***********************************/9261/* MC_CMD_INIT_TXQ9262 */9263#define MC_CMD_INIT_TXQ 0x829264#undef MC_CMD_0x82_PRIVILEGE_CTG9265 9266#define MC_CMD_0x82_PRIVILEGE_CTG SRIOV_CTG_GENERAL9267 9268/* MC_CMD_INIT_TXQ_IN msgrequest: Legacy INIT_TXQ request. Use extended version9269 * in new code.9270 */9271#define MC_CMD_INIT_TXQ_IN_LENMIN 369272#define MC_CMD_INIT_TXQ_IN_LENMAX 2529273#define MC_CMD_INIT_TXQ_IN_LENMAX_MCDI2 10209274#define MC_CMD_INIT_TXQ_IN_LEN(num) (28+8*(num))9275#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_NUM(len) (((len)-28)/8)9276/* Size, in entries */9277#define MC_CMD_INIT_TXQ_IN_SIZE_OFST 09278#define MC_CMD_INIT_TXQ_IN_SIZE_LEN 49279/* The EVQ to send events to. This is an index originally specified to9280 * INIT_EVQ.9281 */9282#define MC_CMD_INIT_TXQ_IN_TARGET_EVQ_OFST 49283#define MC_CMD_INIT_TXQ_IN_TARGET_EVQ_LEN 49284/* The value to put in the event data. Check hardware spec. for valid range. */9285#define MC_CMD_INIT_TXQ_IN_LABEL_OFST 89286#define MC_CMD_INIT_TXQ_IN_LABEL_LEN 49287/* Desired instance. Must be set to a specific instance, which is a function9288 * local queue index.9289 */9290#define MC_CMD_INIT_TXQ_IN_INSTANCE_OFST 129291#define MC_CMD_INIT_TXQ_IN_INSTANCE_LEN 49292/* There will be more flags here. */9293#define MC_CMD_INIT_TXQ_IN_FLAGS_OFST 169294#define MC_CMD_INIT_TXQ_IN_FLAGS_LEN 49295#define MC_CMD_INIT_TXQ_IN_FLAG_BUFF_MODE_OFST 169296#define MC_CMD_INIT_TXQ_IN_FLAG_BUFF_MODE_LBN 09297#define MC_CMD_INIT_TXQ_IN_FLAG_BUFF_MODE_WIDTH 19298#define MC_CMD_INIT_TXQ_IN_FLAG_IP_CSUM_DIS_OFST 169299#define MC_CMD_INIT_TXQ_IN_FLAG_IP_CSUM_DIS_LBN 19300#define MC_CMD_INIT_TXQ_IN_FLAG_IP_CSUM_DIS_WIDTH 19301#define MC_CMD_INIT_TXQ_IN_FLAG_TCP_CSUM_DIS_OFST 169302#define MC_CMD_INIT_TXQ_IN_FLAG_TCP_CSUM_DIS_LBN 29303#define MC_CMD_INIT_TXQ_IN_FLAG_TCP_CSUM_DIS_WIDTH 19304#define MC_CMD_INIT_TXQ_IN_FLAG_TCP_UDP_ONLY_OFST 169305#define MC_CMD_INIT_TXQ_IN_FLAG_TCP_UDP_ONLY_LBN 39306#define MC_CMD_INIT_TXQ_IN_FLAG_TCP_UDP_ONLY_WIDTH 19307#define MC_CMD_INIT_TXQ_IN_CRC_MODE_OFST 169308#define MC_CMD_INIT_TXQ_IN_CRC_MODE_LBN 49309#define MC_CMD_INIT_TXQ_IN_CRC_MODE_WIDTH 49310#define MC_CMD_INIT_TXQ_IN_FLAG_TIMESTAMP_OFST 169311#define MC_CMD_INIT_TXQ_IN_FLAG_TIMESTAMP_LBN 89312#define MC_CMD_INIT_TXQ_IN_FLAG_TIMESTAMP_WIDTH 19313#define MC_CMD_INIT_TXQ_IN_FLAG_PACER_BYPASS_OFST 169314#define MC_CMD_INIT_TXQ_IN_FLAG_PACER_BYPASS_LBN 99315#define MC_CMD_INIT_TXQ_IN_FLAG_PACER_BYPASS_WIDTH 19316#define MC_CMD_INIT_TXQ_IN_FLAG_INNER_IP_CSUM_EN_OFST 169317#define MC_CMD_INIT_TXQ_IN_FLAG_INNER_IP_CSUM_EN_LBN 109318#define MC_CMD_INIT_TXQ_IN_FLAG_INNER_IP_CSUM_EN_WIDTH 19319#define MC_CMD_INIT_TXQ_IN_FLAG_INNER_TCP_CSUM_EN_OFST 169320#define MC_CMD_INIT_TXQ_IN_FLAG_INNER_TCP_CSUM_EN_LBN 119321#define MC_CMD_INIT_TXQ_IN_FLAG_INNER_TCP_CSUM_EN_WIDTH 19322/* Owner ID to use if in buffer mode (zero if physical) */9323#define MC_CMD_INIT_TXQ_IN_OWNER_ID_OFST 209324#define MC_CMD_INIT_TXQ_IN_OWNER_ID_LEN 49325/* The port ID associated with the v-adaptor which should contain this DMAQ. */9326#define MC_CMD_INIT_TXQ_IN_PORT_ID_OFST 249327#define MC_CMD_INIT_TXQ_IN_PORT_ID_LEN 49328/* 64-bit address of 4k of 4k-aligned host memory buffer */9329#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_OFST 289330#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_LEN 89331#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_LO_OFST 289332#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_HI_OFST 329333#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_MINNUM 19334#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_MAXNUM 289335#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_MAXNUM_MCDI2 1249336 9337/* MC_CMD_INIT_TXQ_EXT_IN msgrequest: Extended INIT_TXQ with additional mode9338 * flags9339 */9340#define MC_CMD_INIT_TXQ_EXT_IN_LEN 5449341/* Size, in entries */9342#define MC_CMD_INIT_TXQ_EXT_IN_SIZE_OFST 09343#define MC_CMD_INIT_TXQ_EXT_IN_SIZE_LEN 49344/* The EVQ to send events to. This is an index originally specified to9345 * INIT_EVQ.9346 */9347#define MC_CMD_INIT_TXQ_EXT_IN_TARGET_EVQ_OFST 49348#define MC_CMD_INIT_TXQ_EXT_IN_TARGET_EVQ_LEN 49349/* The value to put in the event data. Check hardware spec. for valid range. */9350#define MC_CMD_INIT_TXQ_EXT_IN_LABEL_OFST 89351#define MC_CMD_INIT_TXQ_EXT_IN_LABEL_LEN 49352/* Desired instance. Must be set to a specific instance, which is a function9353 * local queue index.9354 */9355#define MC_CMD_INIT_TXQ_EXT_IN_INSTANCE_OFST 129356#define MC_CMD_INIT_TXQ_EXT_IN_INSTANCE_LEN 49357/* There will be more flags here. */9358#define MC_CMD_INIT_TXQ_EXT_IN_FLAGS_OFST 169359#define MC_CMD_INIT_TXQ_EXT_IN_FLAGS_LEN 49360#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_BUFF_MODE_OFST 169361#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_BUFF_MODE_LBN 09362#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_BUFF_MODE_WIDTH 19363#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_IP_CSUM_DIS_OFST 169364#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_IP_CSUM_DIS_LBN 19365#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_IP_CSUM_DIS_WIDTH 19366#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_CSUM_DIS_OFST 169367#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_CSUM_DIS_LBN 29368#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_CSUM_DIS_WIDTH 19369#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_UDP_ONLY_OFST 169370#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_UDP_ONLY_LBN 39371#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_UDP_ONLY_WIDTH 19372#define MC_CMD_INIT_TXQ_EXT_IN_CRC_MODE_OFST 169373#define MC_CMD_INIT_TXQ_EXT_IN_CRC_MODE_LBN 49374#define MC_CMD_INIT_TXQ_EXT_IN_CRC_MODE_WIDTH 49375#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TIMESTAMP_OFST 169376#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TIMESTAMP_LBN 89377#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TIMESTAMP_WIDTH 19378#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_PACER_BYPASS_OFST 169379#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_PACER_BYPASS_LBN 99380#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_PACER_BYPASS_WIDTH 19381#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_IP_CSUM_EN_OFST 169382#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_IP_CSUM_EN_LBN 109383#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_IP_CSUM_EN_WIDTH 19384#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_TCP_CSUM_EN_OFST 169385#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_TCP_CSUM_EN_LBN 119386#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_TCP_CSUM_EN_WIDTH 19387#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TSOV2_EN_OFST 169388#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TSOV2_EN_LBN 129389#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TSOV2_EN_WIDTH 19390#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_CTPIO_OFST 169391#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_CTPIO_LBN 139392#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_CTPIO_WIDTH 19393#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_CTPIO_UTHRESH_OFST 169394#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_CTPIO_UTHRESH_LBN 149395#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_CTPIO_UTHRESH_WIDTH 19396#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_M2M_D2C_OFST 169397#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_M2M_D2C_LBN 159398#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_M2M_D2C_WIDTH 19399#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_DESC_PROXY_OFST 169400#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_DESC_PROXY_LBN 169401#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_DESC_PROXY_WIDTH 19402/* Owner ID to use if in buffer mode (zero if physical) */9403#define MC_CMD_INIT_TXQ_EXT_IN_OWNER_ID_OFST 209404#define MC_CMD_INIT_TXQ_EXT_IN_OWNER_ID_LEN 49405/* The port ID associated with the v-adaptor which should contain this DMAQ. */9406#define MC_CMD_INIT_TXQ_EXT_IN_PORT_ID_OFST 249407#define MC_CMD_INIT_TXQ_EXT_IN_PORT_ID_LEN 49408/* 64-bit address of 4k of 4k-aligned host memory buffer */9409#define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_OFST 289410#define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_LEN 89411#define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_LO_OFST 289412#define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_HI_OFST 329413#define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_MINNUM 19414#define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_MAXNUM 649415#define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_MAXNUM_MCDI2 649416/* Flags related to Qbb flow control mode. */9417#define MC_CMD_INIT_TXQ_EXT_IN_QBB_FLAGS_OFST 5409418#define MC_CMD_INIT_TXQ_EXT_IN_QBB_FLAGS_LEN 49419#define MC_CMD_INIT_TXQ_EXT_IN_QBB_ENABLE_OFST 5409420#define MC_CMD_INIT_TXQ_EXT_IN_QBB_ENABLE_LBN 09421#define MC_CMD_INIT_TXQ_EXT_IN_QBB_ENABLE_WIDTH 19422#define MC_CMD_INIT_TXQ_EXT_IN_QBB_PRIORITY_OFST 5409423#define MC_CMD_INIT_TXQ_EXT_IN_QBB_PRIORITY_LBN 19424#define MC_CMD_INIT_TXQ_EXT_IN_QBB_PRIORITY_WIDTH 39425 9426/* MC_CMD_INIT_TXQ_OUT msgresponse */9427#define MC_CMD_INIT_TXQ_OUT_LEN 09428 9429 9430/***********************************/9431/* MC_CMD_FINI_EVQ9432 * Teardown an EVQ.9433 *9434 * All DMAQs or EVQs that point to the EVQ to tear down must be torn down first9435 * or the operation will fail with EBUSY9436 */9437#define MC_CMD_FINI_EVQ 0x839438#undef MC_CMD_0x83_PRIVILEGE_CTG9439 9440#define MC_CMD_0x83_PRIVILEGE_CTG SRIOV_CTG_GENERAL9441 9442/* MC_CMD_FINI_EVQ_IN msgrequest */9443#define MC_CMD_FINI_EVQ_IN_LEN 49444/* Instance of EVQ to destroy. Should be the same instance as that previously9445 * passed to INIT_EVQ9446 */9447#define MC_CMD_FINI_EVQ_IN_INSTANCE_OFST 09448#define MC_CMD_FINI_EVQ_IN_INSTANCE_LEN 49449 9450/* MC_CMD_FINI_EVQ_OUT msgresponse */9451#define MC_CMD_FINI_EVQ_OUT_LEN 09452 9453 9454/***********************************/9455/* MC_CMD_FINI_RXQ9456 * Teardown a RXQ.9457 */9458#define MC_CMD_FINI_RXQ 0x849459#undef MC_CMD_0x84_PRIVILEGE_CTG9460 9461#define MC_CMD_0x84_PRIVILEGE_CTG SRIOV_CTG_GENERAL9462 9463/* MC_CMD_FINI_RXQ_IN msgrequest */9464#define MC_CMD_FINI_RXQ_IN_LEN 49465/* Instance of RXQ to destroy */9466#define MC_CMD_FINI_RXQ_IN_INSTANCE_OFST 09467#define MC_CMD_FINI_RXQ_IN_INSTANCE_LEN 49468 9469/* MC_CMD_FINI_RXQ_OUT msgresponse */9470#define MC_CMD_FINI_RXQ_OUT_LEN 09471 9472 9473/***********************************/9474/* MC_CMD_FINI_TXQ9475 * Teardown a TXQ.9476 */9477#define MC_CMD_FINI_TXQ 0x859478#undef MC_CMD_0x85_PRIVILEGE_CTG9479 9480#define MC_CMD_0x85_PRIVILEGE_CTG SRIOV_CTG_GENERAL9481 9482/* MC_CMD_FINI_TXQ_IN msgrequest */9483#define MC_CMD_FINI_TXQ_IN_LEN 49484/* Instance of TXQ to destroy */9485#define MC_CMD_FINI_TXQ_IN_INSTANCE_OFST 09486#define MC_CMD_FINI_TXQ_IN_INSTANCE_LEN 49487 9488/* MC_CMD_FINI_TXQ_OUT msgresponse */9489#define MC_CMD_FINI_TXQ_OUT_LEN 09490 9491 9492/***********************************/9493/* MC_CMD_DRIVER_EVENT9494 * Generate an event on an EVQ belonging to the function issuing the command.9495 */9496#define MC_CMD_DRIVER_EVENT 0x869497#undef MC_CMD_0x86_PRIVILEGE_CTG9498 9499#define MC_CMD_0x86_PRIVILEGE_CTG SRIOV_CTG_GENERAL9500 9501/* MC_CMD_DRIVER_EVENT_IN msgrequest */9502#define MC_CMD_DRIVER_EVENT_IN_LEN 129503/* Handle of target EVQ */9504#define MC_CMD_DRIVER_EVENT_IN_EVQ_OFST 09505#define MC_CMD_DRIVER_EVENT_IN_EVQ_LEN 49506/* Bits 0 - 63 of event */9507#define MC_CMD_DRIVER_EVENT_IN_DATA_OFST 49508#define MC_CMD_DRIVER_EVENT_IN_DATA_LEN 89509#define MC_CMD_DRIVER_EVENT_IN_DATA_LO_OFST 49510#define MC_CMD_DRIVER_EVENT_IN_DATA_HI_OFST 89511 9512/* MC_CMD_DRIVER_EVENT_OUT msgresponse */9513#define MC_CMD_DRIVER_EVENT_OUT_LEN 09514 9515 9516/***********************************/9517/* MC_CMD_ALLOC_BUFTBL_CHUNK9518 * Allocate a set of buffer table entries using the specified owner ID. This9519 * operation allocates the required buffer table entries (and fails if it9520 * cannot do so). The buffer table entries will initially be zeroed.9521 */9522#define MC_CMD_ALLOC_BUFTBL_CHUNK 0x879523#undef MC_CMD_0x87_PRIVILEGE_CTG9524 9525#define MC_CMD_0x87_PRIVILEGE_CTG SRIOV_CTG_ONLOAD9526 9527/* MC_CMD_ALLOC_BUFTBL_CHUNK_IN msgrequest */9528#define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_LEN 89529/* Owner ID to use */9530#define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_OWNER_OFST 09531#define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_OWNER_LEN 49532/* Size of buffer table pages to use, in bytes (note that only a few values are9533 * legal on any specific hardware).9534 */9535#define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_PAGE_SIZE_OFST 49536#define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_PAGE_SIZE_LEN 49537 9538/* MC_CMD_ALLOC_BUFTBL_CHUNK_OUT msgresponse */9539#define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_LEN 129540#define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_HANDLE_OFST 09541#define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_HANDLE_LEN 49542#define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_NUMENTRIES_OFST 49543#define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_NUMENTRIES_LEN 49544/* Buffer table IDs for use in DMA descriptors. */9545#define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_ID_OFST 89546#define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_ID_LEN 49547 9548 9549/***********************************/9550/* MC_CMD_PROGRAM_BUFTBL_ENTRIES9551 * Reprogram a set of buffer table entries in the specified chunk.9552 */9553#define MC_CMD_PROGRAM_BUFTBL_ENTRIES 0x889554#undef MC_CMD_0x88_PRIVILEGE_CTG9555 9556#define MC_CMD_0x88_PRIVILEGE_CTG SRIOV_CTG_ONLOAD9557 9558/* MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN msgrequest */9559#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LENMIN 209560#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LENMAX 2689561#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LENMAX_MCDI2 2689562#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LEN(num) (12+8*(num))9563#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_NUM(len) (((len)-12)/8)9564#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_HANDLE_OFST 09565#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_HANDLE_LEN 49566/* ID */9567#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_FIRSTID_OFST 49568#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_FIRSTID_LEN 49569/* Num entries */9570#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_NUMENTRIES_OFST 89571#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_NUMENTRIES_LEN 49572/* Buffer table entry address */9573#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_OFST 129574#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_LEN 89575#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_LO_OFST 129576#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_HI_OFST 169577#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_MINNUM 19578#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_MAXNUM 329579#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_MAXNUM_MCDI2 329580 9581/* MC_CMD_PROGRAM_BUFTBL_ENTRIES_OUT msgresponse */9582#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_OUT_LEN 09583 9584 9585/***********************************/9586/* MC_CMD_FREE_BUFTBL_CHUNK9587 */9588#define MC_CMD_FREE_BUFTBL_CHUNK 0x899589#undef MC_CMD_0x89_PRIVILEGE_CTG9590 9591#define MC_CMD_0x89_PRIVILEGE_CTG SRIOV_CTG_ONLOAD9592 9593/* MC_CMD_FREE_BUFTBL_CHUNK_IN msgrequest */9594#define MC_CMD_FREE_BUFTBL_CHUNK_IN_LEN 49595#define MC_CMD_FREE_BUFTBL_CHUNK_IN_HANDLE_OFST 09596#define MC_CMD_FREE_BUFTBL_CHUNK_IN_HANDLE_LEN 49597 9598/* MC_CMD_FREE_BUFTBL_CHUNK_OUT msgresponse */9599#define MC_CMD_FREE_BUFTBL_CHUNK_OUT_LEN 09600 9601 9602/***********************************/9603/* MC_CMD_FILTER_OP9604 * Multiplexed MCDI call for filter operations9605 */9606#define MC_CMD_FILTER_OP 0x8a9607#undef MC_CMD_0x8a_PRIVILEGE_CTG9608 9609#define MC_CMD_0x8a_PRIVILEGE_CTG SRIOV_CTG_GENERAL9610 9611/* MC_CMD_FILTER_OP_IN msgrequest */9612#define MC_CMD_FILTER_OP_IN_LEN 1089613/* identifies the type of operation requested */9614#define MC_CMD_FILTER_OP_IN_OP_OFST 09615#define MC_CMD_FILTER_OP_IN_OP_LEN 49616/* enum: single-recipient filter insert */9617#define MC_CMD_FILTER_OP_IN_OP_INSERT 0x09618/* enum: single-recipient filter remove */9619#define MC_CMD_FILTER_OP_IN_OP_REMOVE 0x19620/* enum: multi-recipient filter subscribe */9621#define MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE 0x29622/* enum: multi-recipient filter unsubscribe */9623#define MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE 0x39624/* enum: replace one recipient with another (warning - the filter handle may9625 * change)9626 */9627#define MC_CMD_FILTER_OP_IN_OP_REPLACE 0x49628/* filter handle (for remove / unsubscribe operations) */9629#define MC_CMD_FILTER_OP_IN_HANDLE_OFST 49630#define MC_CMD_FILTER_OP_IN_HANDLE_LEN 89631#define MC_CMD_FILTER_OP_IN_HANDLE_LO_OFST 49632#define MC_CMD_FILTER_OP_IN_HANDLE_HI_OFST 89633/* The port ID associated with the v-adaptor which should contain this filter.9634 */9635#define MC_CMD_FILTER_OP_IN_PORT_ID_OFST 129636#define MC_CMD_FILTER_OP_IN_PORT_ID_LEN 49637/* fields to include in match criteria */9638#define MC_CMD_FILTER_OP_IN_MATCH_FIELDS_OFST 169639#define MC_CMD_FILTER_OP_IN_MATCH_FIELDS_LEN 49640#define MC_CMD_FILTER_OP_IN_MATCH_SRC_IP_OFST 169641#define MC_CMD_FILTER_OP_IN_MATCH_SRC_IP_LBN 09642#define MC_CMD_FILTER_OP_IN_MATCH_SRC_IP_WIDTH 19643#define MC_CMD_FILTER_OP_IN_MATCH_DST_IP_OFST 169644#define MC_CMD_FILTER_OP_IN_MATCH_DST_IP_LBN 19645#define MC_CMD_FILTER_OP_IN_MATCH_DST_IP_WIDTH 19646#define MC_CMD_FILTER_OP_IN_MATCH_SRC_MAC_OFST 169647#define MC_CMD_FILTER_OP_IN_MATCH_SRC_MAC_LBN 29648#define MC_CMD_FILTER_OP_IN_MATCH_SRC_MAC_WIDTH 19649#define MC_CMD_FILTER_OP_IN_MATCH_SRC_PORT_OFST 169650#define MC_CMD_FILTER_OP_IN_MATCH_SRC_PORT_LBN 39651#define MC_CMD_FILTER_OP_IN_MATCH_SRC_PORT_WIDTH 19652#define MC_CMD_FILTER_OP_IN_MATCH_DST_MAC_OFST 169653#define MC_CMD_FILTER_OP_IN_MATCH_DST_MAC_LBN 49654#define MC_CMD_FILTER_OP_IN_MATCH_DST_MAC_WIDTH 19655#define MC_CMD_FILTER_OP_IN_MATCH_DST_PORT_OFST 169656#define MC_CMD_FILTER_OP_IN_MATCH_DST_PORT_LBN 59657#define MC_CMD_FILTER_OP_IN_MATCH_DST_PORT_WIDTH 19658#define MC_CMD_FILTER_OP_IN_MATCH_ETHER_TYPE_OFST 169659#define MC_CMD_FILTER_OP_IN_MATCH_ETHER_TYPE_LBN 69660#define MC_CMD_FILTER_OP_IN_MATCH_ETHER_TYPE_WIDTH 19661#define MC_CMD_FILTER_OP_IN_MATCH_INNER_VLAN_OFST 169662#define MC_CMD_FILTER_OP_IN_MATCH_INNER_VLAN_LBN 79663#define MC_CMD_FILTER_OP_IN_MATCH_INNER_VLAN_WIDTH 19664#define MC_CMD_FILTER_OP_IN_MATCH_OUTER_VLAN_OFST 169665#define MC_CMD_FILTER_OP_IN_MATCH_OUTER_VLAN_LBN 89666#define MC_CMD_FILTER_OP_IN_MATCH_OUTER_VLAN_WIDTH 19667#define MC_CMD_FILTER_OP_IN_MATCH_IP_PROTO_OFST 169668#define MC_CMD_FILTER_OP_IN_MATCH_IP_PROTO_LBN 99669#define MC_CMD_FILTER_OP_IN_MATCH_IP_PROTO_WIDTH 19670#define MC_CMD_FILTER_OP_IN_MATCH_FWDEF0_OFST 169671#define MC_CMD_FILTER_OP_IN_MATCH_FWDEF0_LBN 109672#define MC_CMD_FILTER_OP_IN_MATCH_FWDEF0_WIDTH 19673#define MC_CMD_FILTER_OP_IN_MATCH_FWDEF1_OFST 169674#define MC_CMD_FILTER_OP_IN_MATCH_FWDEF1_LBN 119675#define MC_CMD_FILTER_OP_IN_MATCH_FWDEF1_WIDTH 19676#define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_OFST 169677#define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_LBN 309678#define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_WIDTH 19679#define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_OFST 169680#define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_LBN 319681#define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_WIDTH 19682/* receive destination */9683#define MC_CMD_FILTER_OP_IN_RX_DEST_OFST 209684#define MC_CMD_FILTER_OP_IN_RX_DEST_LEN 49685/* enum: drop packets */9686#define MC_CMD_FILTER_OP_IN_RX_DEST_DROP 0x09687/* enum: receive to host */9688#define MC_CMD_FILTER_OP_IN_RX_DEST_HOST 0x19689/* enum: receive to MC */9690#define MC_CMD_FILTER_OP_IN_RX_DEST_MC 0x29691/* enum: loop back to TXDP 0 */9692#define MC_CMD_FILTER_OP_IN_RX_DEST_TX0 0x39693/* enum: loop back to TXDP 1 */9694#define MC_CMD_FILTER_OP_IN_RX_DEST_TX1 0x49695/* receive queue handle (for multiple queue modes, this is the base queue) */9696#define MC_CMD_FILTER_OP_IN_RX_QUEUE_OFST 249697#define MC_CMD_FILTER_OP_IN_RX_QUEUE_LEN 49698/* receive mode */9699#define MC_CMD_FILTER_OP_IN_RX_MODE_OFST 289700#define MC_CMD_FILTER_OP_IN_RX_MODE_LEN 49701/* enum: receive to just the specified queue */9702#define MC_CMD_FILTER_OP_IN_RX_MODE_SIMPLE 0x09703/* enum: receive to multiple queues using RSS context */9704#define MC_CMD_FILTER_OP_IN_RX_MODE_RSS 0x19705/* enum: receive to multiple queues using .1p mapping */9706#define MC_CMD_FILTER_OP_IN_RX_MODE_DOT1P_MAPPING 0x29707/* enum: install a filter entry that will never match; for test purposes only9708 */9709#define MC_CMD_FILTER_OP_IN_RX_MODE_TEST_NEVER_MATCH 0x800000009710/* RSS context (for RX_MODE_RSS) or .1p mapping handle (for9711 * RX_MODE_DOT1P_MAPPING), as returned by MC_CMD_RSS_CONTEXT_ALLOC or9712 * MC_CMD_DOT1P_MAPPING_ALLOC.9713 */9714#define MC_CMD_FILTER_OP_IN_RX_CONTEXT_OFST 329715#define MC_CMD_FILTER_OP_IN_RX_CONTEXT_LEN 49716/* transmit domain (reserved; set to 0) */9717#define MC_CMD_FILTER_OP_IN_TX_DOMAIN_OFST 369718#define MC_CMD_FILTER_OP_IN_TX_DOMAIN_LEN 49719/* transmit destination (either set the MAC and/or PM bits for explicit9720 * control, or set this field to TX_DEST_DEFAULT for sensible default9721 * behaviour)9722 */9723#define MC_CMD_FILTER_OP_IN_TX_DEST_OFST 409724#define MC_CMD_FILTER_OP_IN_TX_DEST_LEN 49725/* enum: request default behaviour (based on filter type) */9726#define MC_CMD_FILTER_OP_IN_TX_DEST_DEFAULT 0xffffffff9727#define MC_CMD_FILTER_OP_IN_TX_DEST_MAC_OFST 409728#define MC_CMD_FILTER_OP_IN_TX_DEST_MAC_LBN 09729#define MC_CMD_FILTER_OP_IN_TX_DEST_MAC_WIDTH 19730#define MC_CMD_FILTER_OP_IN_TX_DEST_PM_OFST 409731#define MC_CMD_FILTER_OP_IN_TX_DEST_PM_LBN 19732#define MC_CMD_FILTER_OP_IN_TX_DEST_PM_WIDTH 19733/* source MAC address to match (as bytes in network order) */9734#define MC_CMD_FILTER_OP_IN_SRC_MAC_OFST 449735#define MC_CMD_FILTER_OP_IN_SRC_MAC_LEN 69736/* source port to match (as bytes in network order) */9737#define MC_CMD_FILTER_OP_IN_SRC_PORT_OFST 509738#define MC_CMD_FILTER_OP_IN_SRC_PORT_LEN 29739/* destination MAC address to match (as bytes in network order) */9740#define MC_CMD_FILTER_OP_IN_DST_MAC_OFST 529741#define MC_CMD_FILTER_OP_IN_DST_MAC_LEN 69742/* destination port to match (as bytes in network order) */9743#define MC_CMD_FILTER_OP_IN_DST_PORT_OFST 589744#define MC_CMD_FILTER_OP_IN_DST_PORT_LEN 29745/* Ethernet type to match (as bytes in network order) */9746#define MC_CMD_FILTER_OP_IN_ETHER_TYPE_OFST 609747#define MC_CMD_FILTER_OP_IN_ETHER_TYPE_LEN 29748/* Inner VLAN tag to match (as bytes in network order) */9749#define MC_CMD_FILTER_OP_IN_INNER_VLAN_OFST 629750#define MC_CMD_FILTER_OP_IN_INNER_VLAN_LEN 29751/* Outer VLAN tag to match (as bytes in network order) */9752#define MC_CMD_FILTER_OP_IN_OUTER_VLAN_OFST 649753#define MC_CMD_FILTER_OP_IN_OUTER_VLAN_LEN 29754/* IP protocol to match (in low byte; set high byte to 0) */9755#define MC_CMD_FILTER_OP_IN_IP_PROTO_OFST 669756#define MC_CMD_FILTER_OP_IN_IP_PROTO_LEN 29757/* Firmware defined register 0 to match (reserved; set to 0) */9758#define MC_CMD_FILTER_OP_IN_FWDEF0_OFST 689759#define MC_CMD_FILTER_OP_IN_FWDEF0_LEN 49760/* Firmware defined register 1 to match (reserved; set to 0) */9761#define MC_CMD_FILTER_OP_IN_FWDEF1_OFST 729762#define MC_CMD_FILTER_OP_IN_FWDEF1_LEN 49763/* source IP address to match (as bytes in network order; set last 12 bytes to9764 * 0 for IPv4 address)9765 */9766#define MC_CMD_FILTER_OP_IN_SRC_IP_OFST 769767#define MC_CMD_FILTER_OP_IN_SRC_IP_LEN 169768/* destination IP address to match (as bytes in network order; set last 129769 * bytes to 0 for IPv4 address)9770 */9771#define MC_CMD_FILTER_OP_IN_DST_IP_OFST 929772#define MC_CMD_FILTER_OP_IN_DST_IP_LEN 169773 9774/* MC_CMD_FILTER_OP_EXT_IN msgrequest: Extension to MC_CMD_FILTER_OP_IN to9775 * include handling of VXLAN/NVGRE encapsulated frame filtering (which is9776 * supported on Medford only).9777 */9778#define MC_CMD_FILTER_OP_EXT_IN_LEN 1729779/* identifies the type of operation requested */9780#define MC_CMD_FILTER_OP_EXT_IN_OP_OFST 09781#define MC_CMD_FILTER_OP_EXT_IN_OP_LEN 49782/* Enum values, see field(s): */9783/* MC_CMD_FILTER_OP_IN/OP */9784/* filter handle (for remove / unsubscribe operations) */9785#define MC_CMD_FILTER_OP_EXT_IN_HANDLE_OFST 49786#define MC_CMD_FILTER_OP_EXT_IN_HANDLE_LEN 89787#define MC_CMD_FILTER_OP_EXT_IN_HANDLE_LO_OFST 49788#define MC_CMD_FILTER_OP_EXT_IN_HANDLE_HI_OFST 89789/* The port ID associated with the v-adaptor which should contain this filter.9790 */9791#define MC_CMD_FILTER_OP_EXT_IN_PORT_ID_OFST 129792#define MC_CMD_FILTER_OP_EXT_IN_PORT_ID_LEN 49793/* fields to include in match criteria */9794#define MC_CMD_FILTER_OP_EXT_IN_MATCH_FIELDS_OFST 169795#define MC_CMD_FILTER_OP_EXT_IN_MATCH_FIELDS_LEN 49796#define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_IP_OFST 169797#define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_IP_LBN 09798#define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_IP_WIDTH 19799#define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_IP_OFST 169800#define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_IP_LBN 19801#define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_IP_WIDTH 19802#define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_MAC_OFST 169803#define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_MAC_LBN 29804#define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_MAC_WIDTH 19805#define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_PORT_OFST 169806#define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_PORT_LBN 39807#define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_PORT_WIDTH 19808#define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_MAC_OFST 169809#define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_MAC_LBN 49810#define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_MAC_WIDTH 19811#define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_PORT_OFST 169812#define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_PORT_LBN 59813#define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_PORT_WIDTH 19814#define MC_CMD_FILTER_OP_EXT_IN_MATCH_ETHER_TYPE_OFST 169815#define MC_CMD_FILTER_OP_EXT_IN_MATCH_ETHER_TYPE_LBN 69816#define MC_CMD_FILTER_OP_EXT_IN_MATCH_ETHER_TYPE_WIDTH 19817#define MC_CMD_FILTER_OP_EXT_IN_MATCH_INNER_VLAN_OFST 169818#define MC_CMD_FILTER_OP_EXT_IN_MATCH_INNER_VLAN_LBN 79819#define MC_CMD_FILTER_OP_EXT_IN_MATCH_INNER_VLAN_WIDTH 19820#define MC_CMD_FILTER_OP_EXT_IN_MATCH_OUTER_VLAN_OFST 169821#define MC_CMD_FILTER_OP_EXT_IN_MATCH_OUTER_VLAN_LBN 89822#define MC_CMD_FILTER_OP_EXT_IN_MATCH_OUTER_VLAN_WIDTH 19823#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IP_PROTO_OFST 169824#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IP_PROTO_LBN 99825#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IP_PROTO_WIDTH 19826#define MC_CMD_FILTER_OP_EXT_IN_MATCH_FWDEF0_OFST 169827#define MC_CMD_FILTER_OP_EXT_IN_MATCH_FWDEF0_LBN 109828#define MC_CMD_FILTER_OP_EXT_IN_MATCH_FWDEF0_WIDTH 19829#define MC_CMD_FILTER_OP_EXT_IN_MATCH_VNI_OR_VSID_OFST 169830#define MC_CMD_FILTER_OP_EXT_IN_MATCH_VNI_OR_VSID_LBN 119831#define MC_CMD_FILTER_OP_EXT_IN_MATCH_VNI_OR_VSID_WIDTH 19832#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_IP_OFST 169833#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_IP_LBN 129834#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_IP_WIDTH 19835#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_IP_OFST 169836#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_IP_LBN 139837#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_IP_WIDTH 19838#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_MAC_OFST 169839#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_MAC_LBN 149840#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_MAC_WIDTH 19841#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_PORT_OFST 169842#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_PORT_LBN 159843#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_PORT_WIDTH 19844#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_MAC_OFST 169845#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_MAC_LBN 169846#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_MAC_WIDTH 19847#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_PORT_OFST 169848#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_PORT_LBN 179849#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_PORT_WIDTH 19850#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_ETHER_TYPE_OFST 169851#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_ETHER_TYPE_LBN 189852#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_ETHER_TYPE_WIDTH 19853#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_INNER_VLAN_OFST 169854#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_INNER_VLAN_LBN 199855#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_INNER_VLAN_WIDTH 19856#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_OUTER_VLAN_OFST 169857#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_OUTER_VLAN_LBN 209858#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_OUTER_VLAN_WIDTH 19859#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_IP_PROTO_OFST 169860#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_IP_PROTO_LBN 219861#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_IP_PROTO_WIDTH 19862#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF0_OFST 169863#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF0_LBN 229864#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF0_WIDTH 19865#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF1_OFST 169866#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF1_LBN 239867#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF1_WIDTH 19868#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_OFST 169869#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_LBN 249870#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_WIDTH 19871#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_OFST 169872#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_LBN 259873#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_WIDTH 19874#define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_MCAST_DST_OFST 169875#define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_MCAST_DST_LBN 309876#define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_MCAST_DST_WIDTH 19877#define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_UCAST_DST_OFST 169878#define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_UCAST_DST_LBN 319879#define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_UCAST_DST_WIDTH 19880/* receive destination */9881#define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_OFST 209882#define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_LEN 49883/* enum: drop packets */9884#define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_DROP 0x09885/* enum: receive to host */9886#define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_HOST 0x19887/* enum: receive to MC */9888#define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_MC 0x29889/* enum: loop back to TXDP 0 */9890#define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_TX0 0x39891/* enum: loop back to TXDP 1 */9892#define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_TX1 0x49893/* receive queue handle (for multiple queue modes, this is the base queue) */9894#define MC_CMD_FILTER_OP_EXT_IN_RX_QUEUE_OFST 249895#define MC_CMD_FILTER_OP_EXT_IN_RX_QUEUE_LEN 49896/* receive mode */9897#define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_OFST 289898#define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_LEN 49899/* enum: receive to just the specified queue */9900#define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_SIMPLE 0x09901/* enum: receive to multiple queues using RSS context */9902#define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_RSS 0x19903/* enum: receive to multiple queues using .1p mapping */9904#define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_DOT1P_MAPPING 0x29905/* enum: install a filter entry that will never match; for test purposes only9906 */9907#define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_TEST_NEVER_MATCH 0x800000009908/* RSS context (for RX_MODE_RSS) or .1p mapping handle (for9909 * RX_MODE_DOT1P_MAPPING), as returned by MC_CMD_RSS_CONTEXT_ALLOC or9910 * MC_CMD_DOT1P_MAPPING_ALLOC.9911 */9912#define MC_CMD_FILTER_OP_EXT_IN_RX_CONTEXT_OFST 329913#define MC_CMD_FILTER_OP_EXT_IN_RX_CONTEXT_LEN 49914/* transmit domain (reserved; set to 0) */9915#define MC_CMD_FILTER_OP_EXT_IN_TX_DOMAIN_OFST 369916#define MC_CMD_FILTER_OP_EXT_IN_TX_DOMAIN_LEN 49917/* transmit destination (either set the MAC and/or PM bits for explicit9918 * control, or set this field to TX_DEST_DEFAULT for sensible default9919 * behaviour)9920 */9921#define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_OFST 409922#define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_LEN 49923/* enum: request default behaviour (based on filter type) */9924#define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_DEFAULT 0xffffffff9925#define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_MAC_OFST 409926#define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_MAC_LBN 09927#define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_MAC_WIDTH 19928#define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_PM_OFST 409929#define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_PM_LBN 19930#define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_PM_WIDTH 19931/* source MAC address to match (as bytes in network order) */9932#define MC_CMD_FILTER_OP_EXT_IN_SRC_MAC_OFST 449933#define MC_CMD_FILTER_OP_EXT_IN_SRC_MAC_LEN 69934/* source port to match (as bytes in network order) */9935#define MC_CMD_FILTER_OP_EXT_IN_SRC_PORT_OFST 509936#define MC_CMD_FILTER_OP_EXT_IN_SRC_PORT_LEN 29937/* destination MAC address to match (as bytes in network order) */9938#define MC_CMD_FILTER_OP_EXT_IN_DST_MAC_OFST 529939#define MC_CMD_FILTER_OP_EXT_IN_DST_MAC_LEN 69940/* destination port to match (as bytes in network order) */9941#define MC_CMD_FILTER_OP_EXT_IN_DST_PORT_OFST 589942#define MC_CMD_FILTER_OP_EXT_IN_DST_PORT_LEN 29943/* Ethernet type to match (as bytes in network order) */9944#define MC_CMD_FILTER_OP_EXT_IN_ETHER_TYPE_OFST 609945#define MC_CMD_FILTER_OP_EXT_IN_ETHER_TYPE_LEN 29946/* Inner VLAN tag to match (as bytes in network order) */9947#define MC_CMD_FILTER_OP_EXT_IN_INNER_VLAN_OFST 629948#define MC_CMD_FILTER_OP_EXT_IN_INNER_VLAN_LEN 29949/* Outer VLAN tag to match (as bytes in network order) */9950#define MC_CMD_FILTER_OP_EXT_IN_OUTER_VLAN_OFST 649951#define MC_CMD_FILTER_OP_EXT_IN_OUTER_VLAN_LEN 29952/* IP protocol to match (in low byte; set high byte to 0) */9953#define MC_CMD_FILTER_OP_EXT_IN_IP_PROTO_OFST 669954#define MC_CMD_FILTER_OP_EXT_IN_IP_PROTO_LEN 29955/* Firmware defined register 0 to match (reserved; set to 0) */9956#define MC_CMD_FILTER_OP_EXT_IN_FWDEF0_OFST 689957#define MC_CMD_FILTER_OP_EXT_IN_FWDEF0_LEN 49958/* VNI (for VXLAN/Geneve, when IP protocol is UDP) or VSID (for NVGRE, when IP9959 * protocol is GRE) to match (as bytes in network order; set last byte to 0 for9960 * VXLAN/NVGRE, or 1 for Geneve)9961 */9962#define MC_CMD_FILTER_OP_EXT_IN_VNI_OR_VSID_OFST 729963#define MC_CMD_FILTER_OP_EXT_IN_VNI_OR_VSID_LEN 49964#define MC_CMD_FILTER_OP_EXT_IN_VNI_VALUE_OFST 729965#define MC_CMD_FILTER_OP_EXT_IN_VNI_VALUE_LBN 09966#define MC_CMD_FILTER_OP_EXT_IN_VNI_VALUE_WIDTH 249967#define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_OFST 729968#define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_LBN 249969#define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_WIDTH 89970/* enum: Match VXLAN traffic with this VNI */9971#define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_VXLAN 0x09972/* enum: Match Geneve traffic with this VNI */9973#define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_GENEVE 0x19974/* enum: Reserved for experimental development use */9975#define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_EXPERIMENTAL 0xfe9976#define MC_CMD_FILTER_OP_EXT_IN_VSID_VALUE_OFST 729977#define MC_CMD_FILTER_OP_EXT_IN_VSID_VALUE_LBN 09978#define MC_CMD_FILTER_OP_EXT_IN_VSID_VALUE_WIDTH 249979#define MC_CMD_FILTER_OP_EXT_IN_VSID_TYPE_OFST 729980#define MC_CMD_FILTER_OP_EXT_IN_VSID_TYPE_LBN 249981#define MC_CMD_FILTER_OP_EXT_IN_VSID_TYPE_WIDTH 89982/* enum: Match NVGRE traffic with this VSID */9983#define MC_CMD_FILTER_OP_EXT_IN_VSID_TYPE_NVGRE 0x09984/* source IP address to match (as bytes in network order; set last 12 bytes to9985 * 0 for IPv4 address)9986 */9987#define MC_CMD_FILTER_OP_EXT_IN_SRC_IP_OFST 769988#define MC_CMD_FILTER_OP_EXT_IN_SRC_IP_LEN 169989/* destination IP address to match (as bytes in network order; set last 129990 * bytes to 0 for IPv4 address)9991 */9992#define MC_CMD_FILTER_OP_EXT_IN_DST_IP_OFST 929993#define MC_CMD_FILTER_OP_EXT_IN_DST_IP_LEN 169994/* VXLAN/NVGRE inner frame source MAC address to match (as bytes in network9995 * order)9996 */9997#define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_MAC_OFST 1089998#define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_MAC_LEN 69999/* VXLAN/NVGRE inner frame source port to match (as bytes in network order) */10000#define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_PORT_OFST 11410001#define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_PORT_LEN 210002/* VXLAN/NVGRE inner frame destination MAC address to match (as bytes in10003 * network order)10004 */10005#define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_MAC_OFST 11610006#define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_MAC_LEN 610007/* VXLAN/NVGRE inner frame destination port to match (as bytes in network10008 * order)10009 */10010#define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_PORT_OFST 12210011#define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_PORT_LEN 210012/* VXLAN/NVGRE inner frame Ethernet type to match (as bytes in network order)10013 */10014#define MC_CMD_FILTER_OP_EXT_IN_IFRM_ETHER_TYPE_OFST 12410015#define MC_CMD_FILTER_OP_EXT_IN_IFRM_ETHER_TYPE_LEN 210016/* VXLAN/NVGRE inner frame Inner VLAN tag to match (as bytes in network order)10017 */10018#define MC_CMD_FILTER_OP_EXT_IN_IFRM_INNER_VLAN_OFST 12610019#define MC_CMD_FILTER_OP_EXT_IN_IFRM_INNER_VLAN_LEN 210020/* VXLAN/NVGRE inner frame Outer VLAN tag to match (as bytes in network order)10021 */10022#define MC_CMD_FILTER_OP_EXT_IN_IFRM_OUTER_VLAN_OFST 12810023#define MC_CMD_FILTER_OP_EXT_IN_IFRM_OUTER_VLAN_LEN 210024/* VXLAN/NVGRE inner frame IP protocol to match (in low byte; set high byte to10025 * 0)10026 */10027#define MC_CMD_FILTER_OP_EXT_IN_IFRM_IP_PROTO_OFST 13010028#define MC_CMD_FILTER_OP_EXT_IN_IFRM_IP_PROTO_LEN 210029/* VXLAN/NVGRE inner frame Firmware defined register 0 to match (reserved; set10030 * to 0)10031 */10032#define MC_CMD_FILTER_OP_EXT_IN_IFRM_FWDEF0_OFST 13210033#define MC_CMD_FILTER_OP_EXT_IN_IFRM_FWDEF0_LEN 410034/* VXLAN/NVGRE inner frame Firmware defined register 1 to match (reserved; set10035 * to 0)10036 */10037#define MC_CMD_FILTER_OP_EXT_IN_IFRM_FWDEF1_OFST 13610038#define MC_CMD_FILTER_OP_EXT_IN_IFRM_FWDEF1_LEN 410039/* VXLAN/NVGRE inner frame source IP address to match (as bytes in network10040 * order; set last 12 bytes to 0 for IPv4 address)10041 */10042#define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_IP_OFST 14010043#define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_IP_LEN 1610044/* VXLAN/NVGRE inner frame destination IP address to match (as bytes in network10045 * order; set last 12 bytes to 0 for IPv4 address)10046 */10047#define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_IP_OFST 15610048#define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_IP_LEN 1610049 10050/* MC_CMD_FILTER_OP_V3_IN msgrequest: FILTER_OP extension to support additional10051 * filter actions for Intel's DPDK (Data Plane Development Kit, dpdk.org) via10052 * its rte_flow API. This extension is only useful with the sfc_efx driver10053 * included as part of DPDK, used in conjunction with the dpdk datapath10054 * firmware variant.10055 */10056#define MC_CMD_FILTER_OP_V3_IN_LEN 18010057/* identifies the type of operation requested */10058#define MC_CMD_FILTER_OP_V3_IN_OP_OFST 010059#define MC_CMD_FILTER_OP_V3_IN_OP_LEN 410060/* Enum values, see field(s): */10061/* MC_CMD_FILTER_OP_IN/OP */10062/* filter handle (for remove / unsubscribe operations) */10063#define MC_CMD_FILTER_OP_V3_IN_HANDLE_OFST 410064#define MC_CMD_FILTER_OP_V3_IN_HANDLE_LEN 810065#define MC_CMD_FILTER_OP_V3_IN_HANDLE_LO_OFST 410066#define MC_CMD_FILTER_OP_V3_IN_HANDLE_HI_OFST 810067/* The port ID associated with the v-adaptor which should contain this filter.10068 */10069#define MC_CMD_FILTER_OP_V3_IN_PORT_ID_OFST 1210070#define MC_CMD_FILTER_OP_V3_IN_PORT_ID_LEN 410071/* fields to include in match criteria */10072#define MC_CMD_FILTER_OP_V3_IN_MATCH_FIELDS_OFST 1610073#define MC_CMD_FILTER_OP_V3_IN_MATCH_FIELDS_LEN 410074#define MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_IP_OFST 1610075#define MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_IP_LBN 010076#define MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_IP_WIDTH 110077#define MC_CMD_FILTER_OP_V3_IN_MATCH_DST_IP_OFST 1610078#define MC_CMD_FILTER_OP_V3_IN_MATCH_DST_IP_LBN 110079#define MC_CMD_FILTER_OP_V3_IN_MATCH_DST_IP_WIDTH 110080#define MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_MAC_OFST 1610081#define MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_MAC_LBN 210082#define MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_MAC_WIDTH 110083#define MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_PORT_OFST 1610084#define MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_PORT_LBN 310085#define MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_PORT_WIDTH 110086#define MC_CMD_FILTER_OP_V3_IN_MATCH_DST_MAC_OFST 1610087#define MC_CMD_FILTER_OP_V3_IN_MATCH_DST_MAC_LBN 410088#define MC_CMD_FILTER_OP_V3_IN_MATCH_DST_MAC_WIDTH 110089#define MC_CMD_FILTER_OP_V3_IN_MATCH_DST_PORT_OFST 1610090#define MC_CMD_FILTER_OP_V3_IN_MATCH_DST_PORT_LBN 510091#define MC_CMD_FILTER_OP_V3_IN_MATCH_DST_PORT_WIDTH 110092#define MC_CMD_FILTER_OP_V3_IN_MATCH_ETHER_TYPE_OFST 1610093#define MC_CMD_FILTER_OP_V3_IN_MATCH_ETHER_TYPE_LBN 610094#define MC_CMD_FILTER_OP_V3_IN_MATCH_ETHER_TYPE_WIDTH 110095#define MC_CMD_FILTER_OP_V3_IN_MATCH_INNER_VLAN_OFST 1610096#define MC_CMD_FILTER_OP_V3_IN_MATCH_INNER_VLAN_LBN 710097#define MC_CMD_FILTER_OP_V3_IN_MATCH_INNER_VLAN_WIDTH 110098#define MC_CMD_FILTER_OP_V3_IN_MATCH_OUTER_VLAN_OFST 1610099#define MC_CMD_FILTER_OP_V3_IN_MATCH_OUTER_VLAN_LBN 810100#define MC_CMD_FILTER_OP_V3_IN_MATCH_OUTER_VLAN_WIDTH 110101#define MC_CMD_FILTER_OP_V3_IN_MATCH_IP_PROTO_OFST 1610102#define MC_CMD_FILTER_OP_V3_IN_MATCH_IP_PROTO_LBN 910103#define MC_CMD_FILTER_OP_V3_IN_MATCH_IP_PROTO_WIDTH 110104#define MC_CMD_FILTER_OP_V3_IN_MATCH_FWDEF0_OFST 1610105#define MC_CMD_FILTER_OP_V3_IN_MATCH_FWDEF0_LBN 1010106#define MC_CMD_FILTER_OP_V3_IN_MATCH_FWDEF0_WIDTH 110107#define MC_CMD_FILTER_OP_V3_IN_MATCH_VNI_OR_VSID_OFST 1610108#define MC_CMD_FILTER_OP_V3_IN_MATCH_VNI_OR_VSID_LBN 1110109#define MC_CMD_FILTER_OP_V3_IN_MATCH_VNI_OR_VSID_WIDTH 110110#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_IP_OFST 1610111#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_IP_LBN 1210112#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_IP_WIDTH 110113#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_IP_OFST 1610114#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_IP_LBN 1310115#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_IP_WIDTH 110116#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_MAC_OFST 1610117#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_MAC_LBN 1410118#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_MAC_WIDTH 110119#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_PORT_OFST 1610120#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_PORT_LBN 1510121#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_PORT_WIDTH 110122#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_MAC_OFST 1610123#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_MAC_LBN 1610124#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_MAC_WIDTH 110125#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_PORT_OFST 1610126#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_PORT_LBN 1710127#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_PORT_WIDTH 110128#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_ETHER_TYPE_OFST 1610129#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_ETHER_TYPE_LBN 1810130#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_ETHER_TYPE_WIDTH 110131#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_INNER_VLAN_OFST 1610132#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_INNER_VLAN_LBN 1910133#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_INNER_VLAN_WIDTH 110134#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_OUTER_VLAN_OFST 1610135#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_OUTER_VLAN_LBN 2010136#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_OUTER_VLAN_WIDTH 110137#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_IP_PROTO_OFST 1610138#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_IP_PROTO_LBN 2110139#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_IP_PROTO_WIDTH 110140#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_FWDEF0_OFST 1610141#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_FWDEF0_LBN 2210142#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_FWDEF0_WIDTH 110143#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_FWDEF1_OFST 1610144#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_FWDEF1_LBN 2310145#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_FWDEF1_WIDTH 110146#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_OFST 1610147#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_LBN 2410148#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_WIDTH 110149#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_OFST 1610150#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_LBN 2510151#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_WIDTH 110152#define MC_CMD_FILTER_OP_V3_IN_MATCH_UNKNOWN_MCAST_DST_OFST 1610153#define MC_CMD_FILTER_OP_V3_IN_MATCH_UNKNOWN_MCAST_DST_LBN 3010154#define MC_CMD_FILTER_OP_V3_IN_MATCH_UNKNOWN_MCAST_DST_WIDTH 110155#define MC_CMD_FILTER_OP_V3_IN_MATCH_UNKNOWN_UCAST_DST_OFST 1610156#define MC_CMD_FILTER_OP_V3_IN_MATCH_UNKNOWN_UCAST_DST_LBN 3110157#define MC_CMD_FILTER_OP_V3_IN_MATCH_UNKNOWN_UCAST_DST_WIDTH 110158/* receive destination */10159#define MC_CMD_FILTER_OP_V3_IN_RX_DEST_OFST 2010160#define MC_CMD_FILTER_OP_V3_IN_RX_DEST_LEN 410161/* enum: drop packets */10162#define MC_CMD_FILTER_OP_V3_IN_RX_DEST_DROP 0x010163/* enum: receive to host */10164#define MC_CMD_FILTER_OP_V3_IN_RX_DEST_HOST 0x110165/* enum: receive to MC */10166#define MC_CMD_FILTER_OP_V3_IN_RX_DEST_MC 0x210167/* enum: loop back to TXDP 0 */10168#define MC_CMD_FILTER_OP_V3_IN_RX_DEST_TX0 0x310169/* enum: loop back to TXDP 1 */10170#define MC_CMD_FILTER_OP_V3_IN_RX_DEST_TX1 0x410171/* receive queue handle (for multiple queue modes, this is the base queue) */10172#define MC_CMD_FILTER_OP_V3_IN_RX_QUEUE_OFST 2410173#define MC_CMD_FILTER_OP_V3_IN_RX_QUEUE_LEN 410174/* receive mode */10175#define MC_CMD_FILTER_OP_V3_IN_RX_MODE_OFST 2810176#define MC_CMD_FILTER_OP_V3_IN_RX_MODE_LEN 410177/* enum: receive to just the specified queue */10178#define MC_CMD_FILTER_OP_V3_IN_RX_MODE_SIMPLE 0x010179/* enum: receive to multiple queues using RSS context */10180#define MC_CMD_FILTER_OP_V3_IN_RX_MODE_RSS 0x110181/* enum: receive to multiple queues using .1p mapping */10182#define MC_CMD_FILTER_OP_V3_IN_RX_MODE_DOT1P_MAPPING 0x210183/* enum: install a filter entry that will never match; for test purposes only10184 */10185#define MC_CMD_FILTER_OP_V3_IN_RX_MODE_TEST_NEVER_MATCH 0x8000000010186/* RSS context (for RX_MODE_RSS) or .1p mapping handle (for10187 * RX_MODE_DOT1P_MAPPING), as returned by MC_CMD_RSS_CONTEXT_ALLOC or10188 * MC_CMD_DOT1P_MAPPING_ALLOC.10189 */10190#define MC_CMD_FILTER_OP_V3_IN_RX_CONTEXT_OFST 3210191#define MC_CMD_FILTER_OP_V3_IN_RX_CONTEXT_LEN 410192/* transmit domain (reserved; set to 0) */10193#define MC_CMD_FILTER_OP_V3_IN_TX_DOMAIN_OFST 3610194#define MC_CMD_FILTER_OP_V3_IN_TX_DOMAIN_LEN 410195/* transmit destination (either set the MAC and/or PM bits for explicit10196 * control, or set this field to TX_DEST_DEFAULT for sensible default10197 * behaviour)10198 */10199#define MC_CMD_FILTER_OP_V3_IN_TX_DEST_OFST 4010200#define MC_CMD_FILTER_OP_V3_IN_TX_DEST_LEN 410201/* enum: request default behaviour (based on filter type) */10202#define MC_CMD_FILTER_OP_V3_IN_TX_DEST_DEFAULT 0xffffffff10203#define MC_CMD_FILTER_OP_V3_IN_TX_DEST_MAC_OFST 4010204#define MC_CMD_FILTER_OP_V3_IN_TX_DEST_MAC_LBN 010205#define MC_CMD_FILTER_OP_V3_IN_TX_DEST_MAC_WIDTH 110206#define MC_CMD_FILTER_OP_V3_IN_TX_DEST_PM_OFST 4010207#define MC_CMD_FILTER_OP_V3_IN_TX_DEST_PM_LBN 110208#define MC_CMD_FILTER_OP_V3_IN_TX_DEST_PM_WIDTH 110209/* source MAC address to match (as bytes in network order) */10210#define MC_CMD_FILTER_OP_V3_IN_SRC_MAC_OFST 4410211#define MC_CMD_FILTER_OP_V3_IN_SRC_MAC_LEN 610212/* source port to match (as bytes in network order) */10213#define MC_CMD_FILTER_OP_V3_IN_SRC_PORT_OFST 5010214#define MC_CMD_FILTER_OP_V3_IN_SRC_PORT_LEN 210215/* destination MAC address to match (as bytes in network order) */10216#define MC_CMD_FILTER_OP_V3_IN_DST_MAC_OFST 5210217#define MC_CMD_FILTER_OP_V3_IN_DST_MAC_LEN 610218/* destination port to match (as bytes in network order) */10219#define MC_CMD_FILTER_OP_V3_IN_DST_PORT_OFST 5810220#define MC_CMD_FILTER_OP_V3_IN_DST_PORT_LEN 210221/* Ethernet type to match (as bytes in network order) */10222#define MC_CMD_FILTER_OP_V3_IN_ETHER_TYPE_OFST 6010223#define MC_CMD_FILTER_OP_V3_IN_ETHER_TYPE_LEN 210224/* Inner VLAN tag to match (as bytes in network order) */10225#define MC_CMD_FILTER_OP_V3_IN_INNER_VLAN_OFST 6210226#define MC_CMD_FILTER_OP_V3_IN_INNER_VLAN_LEN 210227/* Outer VLAN tag to match (as bytes in network order) */10228#define MC_CMD_FILTER_OP_V3_IN_OUTER_VLAN_OFST 6410229#define MC_CMD_FILTER_OP_V3_IN_OUTER_VLAN_LEN 210230/* IP protocol to match (in low byte; set high byte to 0) */10231#define MC_CMD_FILTER_OP_V3_IN_IP_PROTO_OFST 6610232#define MC_CMD_FILTER_OP_V3_IN_IP_PROTO_LEN 210233/* Firmware defined register 0 to match (reserved; set to 0) */10234#define MC_CMD_FILTER_OP_V3_IN_FWDEF0_OFST 6810235#define MC_CMD_FILTER_OP_V3_IN_FWDEF0_LEN 410236/* VNI (for VXLAN/Geneve, when IP protocol is UDP) or VSID (for NVGRE, when IP10237 * protocol is GRE) to match (as bytes in network order; set last byte to 0 for10238 * VXLAN/NVGRE, or 1 for Geneve)10239 */10240#define MC_CMD_FILTER_OP_V3_IN_VNI_OR_VSID_OFST 7210241#define MC_CMD_FILTER_OP_V3_IN_VNI_OR_VSID_LEN 410242#define MC_CMD_FILTER_OP_V3_IN_VNI_VALUE_OFST 7210243#define MC_CMD_FILTER_OP_V3_IN_VNI_VALUE_LBN 010244#define MC_CMD_FILTER_OP_V3_IN_VNI_VALUE_WIDTH 2410245#define MC_CMD_FILTER_OP_V3_IN_VNI_TYPE_OFST 7210246#define MC_CMD_FILTER_OP_V3_IN_VNI_TYPE_LBN 2410247#define MC_CMD_FILTER_OP_V3_IN_VNI_TYPE_WIDTH 810248/* enum: Match VXLAN traffic with this VNI */10249#define MC_CMD_FILTER_OP_V3_IN_VNI_TYPE_VXLAN 0x010250/* enum: Match Geneve traffic with this VNI */10251#define MC_CMD_FILTER_OP_V3_IN_VNI_TYPE_GENEVE 0x110252/* enum: Reserved for experimental development use */10253#define MC_CMD_FILTER_OP_V3_IN_VNI_TYPE_EXPERIMENTAL 0xfe10254#define MC_CMD_FILTER_OP_V3_IN_VSID_VALUE_OFST 7210255#define MC_CMD_FILTER_OP_V3_IN_VSID_VALUE_LBN 010256#define MC_CMD_FILTER_OP_V3_IN_VSID_VALUE_WIDTH 2410257#define MC_CMD_FILTER_OP_V3_IN_VSID_TYPE_OFST 7210258#define MC_CMD_FILTER_OP_V3_IN_VSID_TYPE_LBN 2410259#define MC_CMD_FILTER_OP_V3_IN_VSID_TYPE_WIDTH 810260/* enum: Match NVGRE traffic with this VSID */10261#define MC_CMD_FILTER_OP_V3_IN_VSID_TYPE_NVGRE 0x010262/* source IP address to match (as bytes in network order; set last 12 bytes to10263 * 0 for IPv4 address)10264 */10265#define MC_CMD_FILTER_OP_V3_IN_SRC_IP_OFST 7610266#define MC_CMD_FILTER_OP_V3_IN_SRC_IP_LEN 1610267/* destination IP address to match (as bytes in network order; set last 1210268 * bytes to 0 for IPv4 address)10269 */10270#define MC_CMD_FILTER_OP_V3_IN_DST_IP_OFST 9210271#define MC_CMD_FILTER_OP_V3_IN_DST_IP_LEN 1610272/* VXLAN/NVGRE inner frame source MAC address to match (as bytes in network10273 * order)10274 */10275#define MC_CMD_FILTER_OP_V3_IN_IFRM_SRC_MAC_OFST 10810276#define MC_CMD_FILTER_OP_V3_IN_IFRM_SRC_MAC_LEN 610277/* VXLAN/NVGRE inner frame source port to match (as bytes in network order) */10278#define MC_CMD_FILTER_OP_V3_IN_IFRM_SRC_PORT_OFST 11410279#define MC_CMD_FILTER_OP_V3_IN_IFRM_SRC_PORT_LEN 210280/* VXLAN/NVGRE inner frame destination MAC address to match (as bytes in10281 * network order)10282 */10283#define MC_CMD_FILTER_OP_V3_IN_IFRM_DST_MAC_OFST 11610284#define MC_CMD_FILTER_OP_V3_IN_IFRM_DST_MAC_LEN 610285/* VXLAN/NVGRE inner frame destination port to match (as bytes in network10286 * order)10287 */10288#define MC_CMD_FILTER_OP_V3_IN_IFRM_DST_PORT_OFST 12210289#define MC_CMD_FILTER_OP_V3_IN_IFRM_DST_PORT_LEN 210290/* VXLAN/NVGRE inner frame Ethernet type to match (as bytes in network order)10291 */10292#define MC_CMD_FILTER_OP_V3_IN_IFRM_ETHER_TYPE_OFST 12410293#define MC_CMD_FILTER_OP_V3_IN_IFRM_ETHER_TYPE_LEN 210294/* VXLAN/NVGRE inner frame Inner VLAN tag to match (as bytes in network order)10295 */10296#define MC_CMD_FILTER_OP_V3_IN_IFRM_INNER_VLAN_OFST 12610297#define MC_CMD_FILTER_OP_V3_IN_IFRM_INNER_VLAN_LEN 210298/* VXLAN/NVGRE inner frame Outer VLAN tag to match (as bytes in network order)10299 */10300#define MC_CMD_FILTER_OP_V3_IN_IFRM_OUTER_VLAN_OFST 12810301#define MC_CMD_FILTER_OP_V3_IN_IFRM_OUTER_VLAN_LEN 210302/* VXLAN/NVGRE inner frame IP protocol to match (in low byte; set high byte to10303 * 0)10304 */10305#define MC_CMD_FILTER_OP_V3_IN_IFRM_IP_PROTO_OFST 13010306#define MC_CMD_FILTER_OP_V3_IN_IFRM_IP_PROTO_LEN 210307/* VXLAN/NVGRE inner frame Firmware defined register 0 to match (reserved; set10308 * to 0)10309 */10310#define MC_CMD_FILTER_OP_V3_IN_IFRM_FWDEF0_OFST 13210311#define MC_CMD_FILTER_OP_V3_IN_IFRM_FWDEF0_LEN 410312/* VXLAN/NVGRE inner frame Firmware defined register 1 to match (reserved; set10313 * to 0)10314 */10315#define MC_CMD_FILTER_OP_V3_IN_IFRM_FWDEF1_OFST 13610316#define MC_CMD_FILTER_OP_V3_IN_IFRM_FWDEF1_LEN 410317/* VXLAN/NVGRE inner frame source IP address to match (as bytes in network10318 * order; set last 12 bytes to 0 for IPv4 address)10319 */10320#define MC_CMD_FILTER_OP_V3_IN_IFRM_SRC_IP_OFST 14010321#define MC_CMD_FILTER_OP_V3_IN_IFRM_SRC_IP_LEN 1610322/* VXLAN/NVGRE inner frame destination IP address to match (as bytes in network10323 * order; set last 12 bytes to 0 for IPv4 address)10324 */10325#define MC_CMD_FILTER_OP_V3_IN_IFRM_DST_IP_OFST 15610326#define MC_CMD_FILTER_OP_V3_IN_IFRM_DST_IP_LEN 1610327/* Set an action for all packets matching this filter. The DPDK driver and dpdk10328 * f/w variant use their own specific delivery structures, which are documented10329 * in the DPDK Firmware Driver Interface (SF-119419-TC). Requesting anything10330 * other than MATCH_ACTION_NONE when the NIC is running another f/w variant10331 * will cause the filter insertion to fail with ENOTSUP.10332 */10333#define MC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_OFST 17210334#define MC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_LEN 410335/* enum: do nothing extra */10336#define MC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_NONE 0x010337/* enum: Set the match flag in the packet prefix for packets matching the10338 * filter (only with dpdk firmware, otherwise fails with ENOTSUP). Used to10339 * support the DPDK rte_flow "FLAG" action.10340 */10341#define MC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_FLAG 0x110342/* enum: Insert MATCH_MARK_VALUE into the packet prefix for packets matching10343 * the filter (only with dpdk firmware, otherwise fails with ENOTSUP). Used to10344 * support the DPDK rte_flow "MARK" action.10345 */10346#define MC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_MARK 0x210347/* the mark value for MATCH_ACTION_MARK. Requesting a value larger than the10348 * maximum (obtained from MC_CMD_GET_CAPABILITIES_V5/FILTER_ACTION_MARK_MAX)10349 * will cause the filter insertion to fail with EINVAL.10350 */10351#define MC_CMD_FILTER_OP_V3_IN_MATCH_MARK_VALUE_OFST 17610352#define MC_CMD_FILTER_OP_V3_IN_MATCH_MARK_VALUE_LEN 410353 10354/* MC_CMD_FILTER_OP_OUT msgresponse */10355#define MC_CMD_FILTER_OP_OUT_LEN 1210356/* identifies the type of operation requested */10357#define MC_CMD_FILTER_OP_OUT_OP_OFST 010358#define MC_CMD_FILTER_OP_OUT_OP_LEN 410359/* Enum values, see field(s): */10360/* MC_CMD_FILTER_OP_IN/OP */10361/* Returned filter handle (for insert / subscribe operations). Note that these10362 * handles should be considered opaque to the host, although a value of10363 * 0xFFFFFFFF_FFFFFFFF is guaranteed never to be a valid handle.10364 */10365#define MC_CMD_FILTER_OP_OUT_HANDLE_OFST 410366#define MC_CMD_FILTER_OP_OUT_HANDLE_LEN 810367#define MC_CMD_FILTER_OP_OUT_HANDLE_LO_OFST 410368#define MC_CMD_FILTER_OP_OUT_HANDLE_HI_OFST 810369/* enum: guaranteed invalid filter handle (low 32 bits) */10370#define MC_CMD_FILTER_OP_OUT_HANDLE_LO_INVALID 0xffffffff10371/* enum: guaranteed invalid filter handle (high 32 bits) */10372#define MC_CMD_FILTER_OP_OUT_HANDLE_HI_INVALID 0xffffffff10373 10374/* MC_CMD_FILTER_OP_EXT_OUT msgresponse */10375#define MC_CMD_FILTER_OP_EXT_OUT_LEN 1210376/* identifies the type of operation requested */10377#define MC_CMD_FILTER_OP_EXT_OUT_OP_OFST 010378#define MC_CMD_FILTER_OP_EXT_OUT_OP_LEN 410379/* Enum values, see field(s): */10380/* MC_CMD_FILTER_OP_EXT_IN/OP */10381/* Returned filter handle (for insert / subscribe operations). Note that these10382 * handles should be considered opaque to the host, although a value of10383 * 0xFFFFFFFF_FFFFFFFF is guaranteed never to be a valid handle.10384 */10385#define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_OFST 410386#define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_LEN 810387#define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_LO_OFST 410388#define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_HI_OFST 810389/* Enum values, see field(s): */10390/* MC_CMD_FILTER_OP_OUT/HANDLE */10391 10392 10393/***********************************/10394/* MC_CMD_GET_PARSER_DISP_INFO10395 * Get information related to the parser-dispatcher subsystem10396 */10397#define MC_CMD_GET_PARSER_DISP_INFO 0xe410398#undef MC_CMD_0xe4_PRIVILEGE_CTG10399 10400#define MC_CMD_0xe4_PRIVILEGE_CTG SRIOV_CTG_GENERAL10401 10402/* MC_CMD_GET_PARSER_DISP_INFO_IN msgrequest */10403#define MC_CMD_GET_PARSER_DISP_INFO_IN_LEN 410404/* identifies the type of operation requested */10405#define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_OFST 010406#define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_LEN 410407/* enum: read the list of supported RX filter matches */10408#define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_RX_MATCHES 0x110409/* enum: read flags indicating restrictions on filter insertion for the calling10410 * client10411 */10412#define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_RESTRICTIONS 0x210413/* enum: read properties relating to security rules (Medford-only; for use by10414 * SolarSecure apps, not directly by drivers. See SF-114946-SW.)10415 */10416#define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SECURITY_RULE_INFO 0x310417/* enum: read the list of supported RX filter matches for VXLAN/NVGRE10418 * encapsulated frames, which follow a different match sequence to normal10419 * frames (Medford only)10420 */10421#define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_ENCAP_RX_MATCHES 0x410422/* enum: read the list of supported matches for the encapsulation detection10423 * rules inserted by MC_CMD_VNIC_ENCAP_RULE_ADD. (ef100 and later)10424 */10425#define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_VNIC_ENCAP_MATCHES 0x510426 10427/* MC_CMD_GET_PARSER_DISP_INFO_OUT msgresponse */10428#define MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMIN 810429#define MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMAX 25210430#define MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMAX_MCDI2 102010431#define MC_CMD_GET_PARSER_DISP_INFO_OUT_LEN(num) (8+4*(num))10432#define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_NUM(len) (((len)-8)/4)10433/* identifies the type of operation requested */10434#define MC_CMD_GET_PARSER_DISP_INFO_OUT_OP_OFST 010435#define MC_CMD_GET_PARSER_DISP_INFO_OUT_OP_LEN 410436/* Enum values, see field(s): */10437/* MC_CMD_GET_PARSER_DISP_INFO_IN/OP */10438/* number of supported match types */10439#define MC_CMD_GET_PARSER_DISP_INFO_OUT_NUM_SUPPORTED_MATCHES_OFST 410440#define MC_CMD_GET_PARSER_DISP_INFO_OUT_NUM_SUPPORTED_MATCHES_LEN 410441/* array of supported match types (valid MATCH_FIELDS values for10442 * MC_CMD_FILTER_OP) sorted in decreasing priority order10443 */10444#define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_OFST 810445#define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_LEN 410446#define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MINNUM 010447#define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MAXNUM 6110448#define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MAXNUM_MCDI2 25310449 10450/* MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT msgresponse */10451#define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_LEN 810452/* identifies the type of operation requested */10453#define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_OP_OFST 010454#define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_OP_LEN 410455/* Enum values, see field(s): */10456/* MC_CMD_GET_PARSER_DISP_INFO_IN/OP */10457/* bitfield of filter insertion restrictions */10458#define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_RESTRICTION_FLAGS_OFST 410459#define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_RESTRICTION_FLAGS_LEN 410460#define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_DST_IP_MCAST_ONLY_OFST 410461#define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_DST_IP_MCAST_ONLY_LBN 010462#define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_DST_IP_MCAST_ONLY_WIDTH 110463 10464/* MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT msgresponse: This response is10465 * returned if a MC_CMD_GET_PARSER_DISP_INFO_IN request is sent with OP value10466 * OP_GET_SUPPORTED_VNIC_ENCAP_MATCHES. It contains information about the10467 * supported match types that can be used in the encapsulation detection rules10468 * inserted by MC_CMD_VNIC_ENCAP_RULE_ADD.10469 */10470#define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_LENMIN 810471#define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_LENMAX 25210472#define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_LENMAX_MCDI2 102010473#define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_LEN(num) (8+4*(num))10474#define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_SUPPORTED_MATCHES_NUM(len) (((len)-8)/4)10475/* The op code OP_GET_SUPPORTED_VNIC_ENCAP_MATCHES is returned. */10476#define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_OP_OFST 010477#define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_OP_LEN 410478/* Enum values, see field(s): */10479/* MC_CMD_GET_PARSER_DISP_INFO_IN/OP */10480/* number of supported match types */10481#define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_NUM_SUPPORTED_MATCHES_OFST 410482#define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_NUM_SUPPORTED_MATCHES_LEN 410483/* array of supported match types (valid MATCH_FLAGS values for10484 * MC_CMD_VNIC_ENCAP_RULE_ADD) sorted in decreasing priority order10485 */10486#define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_SUPPORTED_MATCHES_OFST 810487#define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_SUPPORTED_MATCHES_LEN 410488#define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_SUPPORTED_MATCHES_MINNUM 010489#define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_SUPPORTED_MATCHES_MAXNUM 6110490#define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_SUPPORTED_MATCHES_MAXNUM_MCDI2 25310491 10492 10493/***********************************/10494/* MC_CMD_GET_PORT_ASSIGNMENT10495 * Get port assignment for current PCI function.10496 */10497#define MC_CMD_GET_PORT_ASSIGNMENT 0xb810498#undef MC_CMD_0xb8_PRIVILEGE_CTG10499 10500#define MC_CMD_0xb8_PRIVILEGE_CTG SRIOV_CTG_GENERAL10501 10502/* MC_CMD_GET_PORT_ASSIGNMENT_IN msgrequest */10503#define MC_CMD_GET_PORT_ASSIGNMENT_IN_LEN 010504 10505/* MC_CMD_GET_PORT_ASSIGNMENT_OUT msgresponse */10506#define MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN 410507/* Identifies the port assignment for this function. */10508#define MC_CMD_GET_PORT_ASSIGNMENT_OUT_PORT_OFST 010509#define MC_CMD_GET_PORT_ASSIGNMENT_OUT_PORT_LEN 410510 10511 10512/***********************************/10513/* MC_CMD_SET_PORT_ASSIGNMENT10514 * Set port assignment for current PCI function.10515 */10516#define MC_CMD_SET_PORT_ASSIGNMENT 0xb910517#undef MC_CMD_0xb9_PRIVILEGE_CTG10518 10519#define MC_CMD_0xb9_PRIVILEGE_CTG SRIOV_CTG_ADMIN10520 10521/* MC_CMD_SET_PORT_ASSIGNMENT_IN msgrequest */10522#define MC_CMD_SET_PORT_ASSIGNMENT_IN_LEN 410523/* Identifies the port assignment for this function. */10524#define MC_CMD_SET_PORT_ASSIGNMENT_IN_PORT_OFST 010525#define MC_CMD_SET_PORT_ASSIGNMENT_IN_PORT_LEN 410526 10527/* MC_CMD_SET_PORT_ASSIGNMENT_OUT msgresponse */10528#define MC_CMD_SET_PORT_ASSIGNMENT_OUT_LEN 010529 10530 10531/***********************************/10532/* MC_CMD_ALLOC_VIS10533 * Allocate VIs for current PCI function.10534 */10535#define MC_CMD_ALLOC_VIS 0x8b10536#undef MC_CMD_0x8b_PRIVILEGE_CTG10537 10538#define MC_CMD_0x8b_PRIVILEGE_CTG SRIOV_CTG_GENERAL10539 10540/* MC_CMD_ALLOC_VIS_IN msgrequest */10541#define MC_CMD_ALLOC_VIS_IN_LEN 810542/* The minimum number of VIs that is acceptable */10543#define MC_CMD_ALLOC_VIS_IN_MIN_VI_COUNT_OFST 010544#define MC_CMD_ALLOC_VIS_IN_MIN_VI_COUNT_LEN 410545/* The maximum number of VIs that would be useful */10546#define MC_CMD_ALLOC_VIS_IN_MAX_VI_COUNT_OFST 410547#define MC_CMD_ALLOC_VIS_IN_MAX_VI_COUNT_LEN 410548 10549/* MC_CMD_ALLOC_VIS_OUT msgresponse: Huntington-compatible VI_ALLOC request.10550 * Use extended version in new code.10551 */10552#define MC_CMD_ALLOC_VIS_OUT_LEN 810553/* The number of VIs allocated on this function */10554#define MC_CMD_ALLOC_VIS_OUT_VI_COUNT_OFST 010555#define MC_CMD_ALLOC_VIS_OUT_VI_COUNT_LEN 410556/* The base absolute VI number allocated to this function. Required to10557 * correctly interpret wakeup events.10558 */10559#define MC_CMD_ALLOC_VIS_OUT_VI_BASE_OFST 410560#define MC_CMD_ALLOC_VIS_OUT_VI_BASE_LEN 410561 10562/* MC_CMD_ALLOC_VIS_EXT_OUT msgresponse */10563#define MC_CMD_ALLOC_VIS_EXT_OUT_LEN 1210564/* The number of VIs allocated on this function */10565#define MC_CMD_ALLOC_VIS_EXT_OUT_VI_COUNT_OFST 010566#define MC_CMD_ALLOC_VIS_EXT_OUT_VI_COUNT_LEN 410567/* The base absolute VI number allocated to this function. Required to10568 * correctly interpret wakeup events.10569 */10570#define MC_CMD_ALLOC_VIS_EXT_OUT_VI_BASE_OFST 410571#define MC_CMD_ALLOC_VIS_EXT_OUT_VI_BASE_LEN 410572/* Function's port vi_shift value (always 0 on Huntington) */10573#define MC_CMD_ALLOC_VIS_EXT_OUT_VI_SHIFT_OFST 810574#define MC_CMD_ALLOC_VIS_EXT_OUT_VI_SHIFT_LEN 410575 10576 10577/***********************************/10578/* MC_CMD_FREE_VIS10579 * Free VIs for current PCI function. Any linked PIO buffers will be unlinked,10580 * but not freed.10581 */10582#define MC_CMD_FREE_VIS 0x8c10583#undef MC_CMD_0x8c_PRIVILEGE_CTG10584 10585#define MC_CMD_0x8c_PRIVILEGE_CTG SRIOV_CTG_GENERAL10586 10587/* MC_CMD_FREE_VIS_IN msgrequest */10588#define MC_CMD_FREE_VIS_IN_LEN 010589 10590/* MC_CMD_FREE_VIS_OUT msgresponse */10591#define MC_CMD_FREE_VIS_OUT_LEN 010592 10593 10594/***********************************/10595/* MC_CMD_GET_SRIOV_CFG10596 * Get SRIOV config for this PF.10597 */10598#define MC_CMD_GET_SRIOV_CFG 0xba10599#undef MC_CMD_0xba_PRIVILEGE_CTG10600 10601#define MC_CMD_0xba_PRIVILEGE_CTG SRIOV_CTG_GENERAL10602 10603/* MC_CMD_GET_SRIOV_CFG_IN msgrequest */10604#define MC_CMD_GET_SRIOV_CFG_IN_LEN 010605 10606/* MC_CMD_GET_SRIOV_CFG_OUT msgresponse */10607#define MC_CMD_GET_SRIOV_CFG_OUT_LEN 2010608/* Number of VFs currently enabled. */10609#define MC_CMD_GET_SRIOV_CFG_OUT_VF_CURRENT_OFST 010610#define MC_CMD_GET_SRIOV_CFG_OUT_VF_CURRENT_LEN 410611/* Max number of VFs before sriov stride and offset may need to be changed. */10612#define MC_CMD_GET_SRIOV_CFG_OUT_VF_MAX_OFST 410613#define MC_CMD_GET_SRIOV_CFG_OUT_VF_MAX_LEN 410614#define MC_CMD_GET_SRIOV_CFG_OUT_FLAGS_OFST 810615#define MC_CMD_GET_SRIOV_CFG_OUT_FLAGS_LEN 410616#define MC_CMD_GET_SRIOV_CFG_OUT_VF_ENABLED_OFST 810617#define MC_CMD_GET_SRIOV_CFG_OUT_VF_ENABLED_LBN 010618#define MC_CMD_GET_SRIOV_CFG_OUT_VF_ENABLED_WIDTH 110619/* RID offset of first VF from PF. */10620#define MC_CMD_GET_SRIOV_CFG_OUT_VF_OFFSET_OFST 1210621#define MC_CMD_GET_SRIOV_CFG_OUT_VF_OFFSET_LEN 410622/* RID offset of each subsequent VF from the previous. */10623#define MC_CMD_GET_SRIOV_CFG_OUT_VF_STRIDE_OFST 1610624#define MC_CMD_GET_SRIOV_CFG_OUT_VF_STRIDE_LEN 410625 10626 10627/***********************************/10628/* MC_CMD_SET_SRIOV_CFG10629 * Set SRIOV config for this PF.10630 */10631#define MC_CMD_SET_SRIOV_CFG 0xbb10632#undef MC_CMD_0xbb_PRIVILEGE_CTG10633 10634#define MC_CMD_0xbb_PRIVILEGE_CTG SRIOV_CTG_ADMIN10635 10636/* MC_CMD_SET_SRIOV_CFG_IN msgrequest */10637#define MC_CMD_SET_SRIOV_CFG_IN_LEN 2010638/* Number of VFs currently enabled. */10639#define MC_CMD_SET_SRIOV_CFG_IN_VF_CURRENT_OFST 010640#define MC_CMD_SET_SRIOV_CFG_IN_VF_CURRENT_LEN 410641/* Max number of VFs before sriov stride and offset may need to be changed. */10642#define MC_CMD_SET_SRIOV_CFG_IN_VF_MAX_OFST 410643#define MC_CMD_SET_SRIOV_CFG_IN_VF_MAX_LEN 410644#define MC_CMD_SET_SRIOV_CFG_IN_FLAGS_OFST 810645#define MC_CMD_SET_SRIOV_CFG_IN_FLAGS_LEN 410646#define MC_CMD_SET_SRIOV_CFG_IN_VF_ENABLED_OFST 810647#define MC_CMD_SET_SRIOV_CFG_IN_VF_ENABLED_LBN 010648#define MC_CMD_SET_SRIOV_CFG_IN_VF_ENABLED_WIDTH 110649/* RID offset of first VF from PF, or 0 for no change, or10650 * MC_CMD_RESOURCE_INSTANCE_ANY to allow the system to allocate an offset.10651 */10652#define MC_CMD_SET_SRIOV_CFG_IN_VF_OFFSET_OFST 1210653#define MC_CMD_SET_SRIOV_CFG_IN_VF_OFFSET_LEN 410654/* RID offset of each subsequent VF from the previous, 0 for no change, or10655 * MC_CMD_RESOURCE_INSTANCE_ANY to allow the system to allocate a stride.10656 */10657#define MC_CMD_SET_SRIOV_CFG_IN_VF_STRIDE_OFST 1610658#define MC_CMD_SET_SRIOV_CFG_IN_VF_STRIDE_LEN 410659 10660/* MC_CMD_SET_SRIOV_CFG_OUT msgresponse */10661#define MC_CMD_SET_SRIOV_CFG_OUT_LEN 010662 10663 10664/***********************************/10665/* MC_CMD_GET_VI_ALLOC_INFO10666 * Get information about number of VI's and base VI number allocated to this10667 * function.10668 */10669#define MC_CMD_GET_VI_ALLOC_INFO 0x8d10670#undef MC_CMD_0x8d_PRIVILEGE_CTG10671 10672#define MC_CMD_0x8d_PRIVILEGE_CTG SRIOV_CTG_GENERAL10673 10674/* MC_CMD_GET_VI_ALLOC_INFO_IN msgrequest */10675#define MC_CMD_GET_VI_ALLOC_INFO_IN_LEN 010676 10677/* MC_CMD_GET_VI_ALLOC_INFO_OUT msgresponse */10678#define MC_CMD_GET_VI_ALLOC_INFO_OUT_LEN 1210679/* The number of VIs allocated on this function */10680#define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_COUNT_OFST 010681#define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_COUNT_LEN 410682/* The base absolute VI number allocated to this function. Required to10683 * correctly interpret wakeup events.10684 */10685#define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_BASE_OFST 410686#define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_BASE_LEN 410687/* Function's port vi_shift value (always 0 on Huntington) */10688#define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_SHIFT_OFST 810689#define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_SHIFT_LEN 410690 10691 10692/***********************************/10693/* MC_CMD_DUMP_VI_STATE10694 * For CmdClient use. Dump pertinent information on a specific absolute VI.10695 */10696#define MC_CMD_DUMP_VI_STATE 0x8e10697#undef MC_CMD_0x8e_PRIVILEGE_CTG10698 10699#define MC_CMD_0x8e_PRIVILEGE_CTG SRIOV_CTG_GENERAL10700 10701/* MC_CMD_DUMP_VI_STATE_IN msgrequest */10702#define MC_CMD_DUMP_VI_STATE_IN_LEN 410703/* The VI number to query. */10704#define MC_CMD_DUMP_VI_STATE_IN_VI_NUMBER_OFST 010705#define MC_CMD_DUMP_VI_STATE_IN_VI_NUMBER_LEN 410706 10707/* MC_CMD_DUMP_VI_STATE_OUT msgresponse */10708#define MC_CMD_DUMP_VI_STATE_OUT_LEN 9610709/* The PF part of the function owning this VI. */10710#define MC_CMD_DUMP_VI_STATE_OUT_OWNER_PF_OFST 010711#define MC_CMD_DUMP_VI_STATE_OUT_OWNER_PF_LEN 210712/* The VF part of the function owning this VI. */10713#define MC_CMD_DUMP_VI_STATE_OUT_OWNER_VF_OFST 210714#define MC_CMD_DUMP_VI_STATE_OUT_OWNER_VF_LEN 210715/* Base of VIs allocated to this function. */10716#define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_BASE_OFST 410717#define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_BASE_LEN 210718/* Count of VIs allocated to the owner function. */10719#define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_COUNT_OFST 610720#define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_COUNT_LEN 210721/* Base interrupt vector allocated to this function. */10722#define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_BASE_OFST 810723#define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_BASE_LEN 210724/* Number of interrupt vectors allocated to this function. */10725#define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_COUNT_OFST 1010726#define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_COUNT_LEN 210727/* Raw evq ptr table data. */10728#define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_OFST 1210729#define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_LEN 810730#define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_LO_OFST 1210731#define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_HI_OFST 1610732/* Raw evq timer table data. */10733#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_OFST 2010734#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_LEN 810735#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_LO_OFST 2010736#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_HI_OFST 2410737/* Combined metadata field. */10738#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_OFST 2810739#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_LEN 410740#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_BASE_OFST 2810741#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_BASE_LBN 010742#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_BASE_WIDTH 1610743#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_NPAGES_OFST 2810744#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_NPAGES_LBN 1610745#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_NPAGES_WIDTH 810746#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_WKUP_REF_OFST 2810747#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_WKUP_REF_LBN 2410748#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_WKUP_REF_WIDTH 810749/* TXDPCPU raw table data for queue. */10750#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_OFST 3210751#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_LEN 810752#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_LO_OFST 3210753#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_HI_OFST 3610754/* TXDPCPU raw table data for queue. */10755#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_OFST 4010756#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_LEN 810757#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_LO_OFST 4010758#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_HI_OFST 4410759/* TXDPCPU raw table data for queue. */10760#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_OFST 4810761#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_LEN 810762#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_LO_OFST 4810763#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_HI_OFST 5210764/* Combined metadata field. */10765#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_OFST 5610766#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_LEN 810767#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_LO_OFST 5610768#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_HI_OFST 6010769#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_BASE_OFST 5610770#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_BASE_LBN 010771#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_BASE_WIDTH 1610772#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_NPAGES_OFST 5610773#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_NPAGES_LBN 1610774#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_NPAGES_WIDTH 810775#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_QSTATE_OFST 5610776#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_QSTATE_LBN 2410777#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_QSTATE_WIDTH 810778#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_WAITCOUNT_OFST 5610779#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_WAITCOUNT_LBN 3210780#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_WAITCOUNT_WIDTH 810781#define MC_CMD_DUMP_VI_STATE_OUT_VI_PADDING_OFST 5610782#define MC_CMD_DUMP_VI_STATE_OUT_VI_PADDING_LBN 4010783#define MC_CMD_DUMP_VI_STATE_OUT_VI_PADDING_WIDTH 2410784/* RXDPCPU raw table data for queue. */10785#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_OFST 6410786#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_LEN 810787#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_LO_OFST 6410788#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_HI_OFST 6810789/* RXDPCPU raw table data for queue. */10790#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_OFST 7210791#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_LEN 810792#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_LO_OFST 7210793#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_HI_OFST 7610794/* Reserved, currently 0. */10795#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_OFST 8010796#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_LEN 810797#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_LO_OFST 8010798#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_HI_OFST 8410799/* Combined metadata field. */10800#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_OFST 8810801#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_LEN 810802#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_LO_OFST 8810803#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_HI_OFST 9210804#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_BASE_OFST 8810805#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_BASE_LBN 010806#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_BASE_WIDTH 1610807#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_NPAGES_OFST 8810808#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_NPAGES_LBN 1610809#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_NPAGES_WIDTH 810810#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_QSTATE_OFST 8810811#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_QSTATE_LBN 2410812#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_QSTATE_WIDTH 810813#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_WAITCOUNT_OFST 8810814#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_WAITCOUNT_LBN 3210815#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_WAITCOUNT_WIDTH 810816 10817 10818/***********************************/10819/* MC_CMD_ALLOC_PIOBUF10820 * Allocate a push I/O buffer for later use with a tx queue.10821 */10822#define MC_CMD_ALLOC_PIOBUF 0x8f10823#undef MC_CMD_0x8f_PRIVILEGE_CTG10824 10825#define MC_CMD_0x8f_PRIVILEGE_CTG SRIOV_CTG_ONLOAD10826 10827/* MC_CMD_ALLOC_PIOBUF_IN msgrequest */10828#define MC_CMD_ALLOC_PIOBUF_IN_LEN 010829 10830/* MC_CMD_ALLOC_PIOBUF_OUT msgresponse */10831#define MC_CMD_ALLOC_PIOBUF_OUT_LEN 410832/* Handle for allocated push I/O buffer. */10833#define MC_CMD_ALLOC_PIOBUF_OUT_PIOBUF_HANDLE_OFST 010834#define MC_CMD_ALLOC_PIOBUF_OUT_PIOBUF_HANDLE_LEN 410835 10836 10837/***********************************/10838/* MC_CMD_FREE_PIOBUF10839 * Free a push I/O buffer.10840 */10841#define MC_CMD_FREE_PIOBUF 0x9010842#undef MC_CMD_0x90_PRIVILEGE_CTG10843 10844#define MC_CMD_0x90_PRIVILEGE_CTG SRIOV_CTG_ONLOAD10845 10846/* MC_CMD_FREE_PIOBUF_IN msgrequest */10847#define MC_CMD_FREE_PIOBUF_IN_LEN 410848/* Handle for allocated push I/O buffer. */10849#define MC_CMD_FREE_PIOBUF_IN_PIOBUF_HANDLE_OFST 010850#define MC_CMD_FREE_PIOBUF_IN_PIOBUF_HANDLE_LEN 410851 10852/* MC_CMD_FREE_PIOBUF_OUT msgresponse */10853#define MC_CMD_FREE_PIOBUF_OUT_LEN 010854 10855 10856/***********************************/10857/* MC_CMD_GET_CAPABILITIES10858 * Get device capabilities.10859 *10860 * This is supplementary to the MC_CMD_GET_BOARD_CFG command, and intended to10861 * reference inherent device capabilities as opposed to current NVRAM config.10862 */10863#define MC_CMD_GET_CAPABILITIES 0xbe10864#undef MC_CMD_0xbe_PRIVILEGE_CTG10865 10866#define MC_CMD_0xbe_PRIVILEGE_CTG SRIOV_CTG_GENERAL10867 10868/* MC_CMD_GET_CAPABILITIES_IN msgrequest */10869#define MC_CMD_GET_CAPABILITIES_IN_LEN 010870 10871/* MC_CMD_GET_CAPABILITIES_OUT msgresponse */10872#define MC_CMD_GET_CAPABILITIES_OUT_LEN 2010873/* First word of flags. */10874#define MC_CMD_GET_CAPABILITIES_OUT_FLAGS1_OFST 010875#define MC_CMD_GET_CAPABILITIES_OUT_FLAGS1_LEN 410876#define MC_CMD_GET_CAPABILITIES_OUT_VPORT_RECONFIGURE_OFST 010877#define MC_CMD_GET_CAPABILITIES_OUT_VPORT_RECONFIGURE_LBN 310878#define MC_CMD_GET_CAPABILITIES_OUT_VPORT_RECONFIGURE_WIDTH 110879#define MC_CMD_GET_CAPABILITIES_OUT_TX_STRIPING_OFST 010880#define MC_CMD_GET_CAPABILITIES_OUT_TX_STRIPING_LBN 410881#define MC_CMD_GET_CAPABILITIES_OUT_TX_STRIPING_WIDTH 110882#define MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_QUERY_OFST 010883#define MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_QUERY_LBN 510884#define MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_QUERY_WIDTH 110885#define MC_CMD_GET_CAPABILITIES_OUT_EVB_PORT_VLAN_RESTRICT_OFST 010886#define MC_CMD_GET_CAPABILITIES_OUT_EVB_PORT_VLAN_RESTRICT_LBN 610887#define MC_CMD_GET_CAPABILITIES_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 110888#define MC_CMD_GET_CAPABILITIES_OUT_DRV_ATTACH_PREBOOT_OFST 010889#define MC_CMD_GET_CAPABILITIES_OUT_DRV_ATTACH_PREBOOT_LBN 710890#define MC_CMD_GET_CAPABILITIES_OUT_DRV_ATTACH_PREBOOT_WIDTH 110891#define MC_CMD_GET_CAPABILITIES_OUT_RX_FORCE_EVENT_MERGING_OFST 010892#define MC_CMD_GET_CAPABILITIES_OUT_RX_FORCE_EVENT_MERGING_LBN 810893#define MC_CMD_GET_CAPABILITIES_OUT_RX_FORCE_EVENT_MERGING_WIDTH 110894#define MC_CMD_GET_CAPABILITIES_OUT_SET_MAC_ENHANCED_OFST 010895#define MC_CMD_GET_CAPABILITIES_OUT_SET_MAC_ENHANCED_LBN 910896#define MC_CMD_GET_CAPABILITIES_OUT_SET_MAC_ENHANCED_WIDTH 110897#define MC_CMD_GET_CAPABILITIES_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 010898#define MC_CMD_GET_CAPABILITIES_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 1010899#define MC_CMD_GET_CAPABILITIES_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 110900#define MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 010901#define MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 1110902#define MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 110903#define MC_CMD_GET_CAPABILITIES_OUT_TX_MAC_SECURITY_FILTERING_OFST 010904#define MC_CMD_GET_CAPABILITIES_OUT_TX_MAC_SECURITY_FILTERING_LBN 1210905#define MC_CMD_GET_CAPABILITIES_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 110906#define MC_CMD_GET_CAPABILITIES_OUT_ADDITIONAL_RSS_MODES_OFST 010907#define MC_CMD_GET_CAPABILITIES_OUT_ADDITIONAL_RSS_MODES_LBN 1310908#define MC_CMD_GET_CAPABILITIES_OUT_ADDITIONAL_RSS_MODES_WIDTH 110909#define MC_CMD_GET_CAPABILITIES_OUT_QBB_OFST 010910#define MC_CMD_GET_CAPABILITIES_OUT_QBB_LBN 1410911#define MC_CMD_GET_CAPABILITIES_OUT_QBB_WIDTH 110912#define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 010913#define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 1510914#define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 110915#define MC_CMD_GET_CAPABILITIES_OUT_RX_RSS_LIMITED_OFST 010916#define MC_CMD_GET_CAPABILITIES_OUT_RX_RSS_LIMITED_LBN 1610917#define MC_CMD_GET_CAPABILITIES_OUT_RX_RSS_LIMITED_WIDTH 110918#define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_OFST 010919#define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_LBN 1710920#define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_WIDTH 110921#define MC_CMD_GET_CAPABILITIES_OUT_RX_INCLUDE_FCS_OFST 010922#define MC_CMD_GET_CAPABILITIES_OUT_RX_INCLUDE_FCS_LBN 1810923#define MC_CMD_GET_CAPABILITIES_OUT_RX_INCLUDE_FCS_WIDTH 110924#define MC_CMD_GET_CAPABILITIES_OUT_TX_VLAN_INSERTION_OFST 010925#define MC_CMD_GET_CAPABILITIES_OUT_TX_VLAN_INSERTION_LBN 1910926#define MC_CMD_GET_CAPABILITIES_OUT_TX_VLAN_INSERTION_WIDTH 110927#define MC_CMD_GET_CAPABILITIES_OUT_RX_VLAN_STRIPPING_OFST 010928#define MC_CMD_GET_CAPABILITIES_OUT_RX_VLAN_STRIPPING_LBN 2010929#define MC_CMD_GET_CAPABILITIES_OUT_RX_VLAN_STRIPPING_WIDTH 110930#define MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_OFST 010931#define MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN 2110932#define MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_WIDTH 110933#define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_0_OFST 010934#define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_0_LBN 2210935#define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_0_WIDTH 110936#define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_OFST 010937#define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_LBN 2310938#define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_WIDTH 110939#define MC_CMD_GET_CAPABILITIES_OUT_RX_TIMESTAMP_OFST 010940#define MC_CMD_GET_CAPABILITIES_OUT_RX_TIMESTAMP_LBN 2410941#define MC_CMD_GET_CAPABILITIES_OUT_RX_TIMESTAMP_WIDTH 110942#define MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_OFST 010943#define MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN 2510944#define MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_WIDTH 110945#define MC_CMD_GET_CAPABILITIES_OUT_MCAST_FILTER_CHAINING_OFST 010946#define MC_CMD_GET_CAPABILITIES_OUT_MCAST_FILTER_CHAINING_LBN 2610947#define MC_CMD_GET_CAPABILITIES_OUT_MCAST_FILTER_CHAINING_WIDTH 110948#define MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_OFST 010949#define MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_LBN 2710950#define MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_WIDTH 110951#define MC_CMD_GET_CAPABILITIES_OUT_RX_DISABLE_SCATTER_OFST 010952#define MC_CMD_GET_CAPABILITIES_OUT_RX_DISABLE_SCATTER_LBN 2810953#define MC_CMD_GET_CAPABILITIES_OUT_RX_DISABLE_SCATTER_WIDTH 110954#define MC_CMD_GET_CAPABILITIES_OUT_TX_MCAST_UDP_LOOPBACK_OFST 010955#define MC_CMD_GET_CAPABILITIES_OUT_TX_MCAST_UDP_LOOPBACK_LBN 2910956#define MC_CMD_GET_CAPABILITIES_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 110957#define MC_CMD_GET_CAPABILITIES_OUT_EVB_OFST 010958#define MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN 3010959#define MC_CMD_GET_CAPABILITIES_OUT_EVB_WIDTH 110960#define MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_OFST 010961#define MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN 3110962#define MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_WIDTH 110963/* RxDPCPU firmware id. */10964#define MC_CMD_GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID_OFST 410965#define MC_CMD_GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID_LEN 210966/* enum: Standard RXDP firmware */10967#define MC_CMD_GET_CAPABILITIES_OUT_RXDP 0x010968/* enum: Low latency RXDP firmware */10969#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_LOW_LATENCY 0x110970/* enum: Packed stream RXDP firmware */10971#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_PACKED_STREAM 0x210972/* enum: Rules engine RXDP firmware */10973#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_RULES_ENGINE 0x510974/* enum: DPDK RXDP firmware */10975#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_DPDK 0x610976/* enum: BIST RXDP firmware */10977#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_BIST 0x10a10978/* enum: RXDP Test firmware image 1 */10979#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x10110980/* enum: RXDP Test firmware image 2 */10981#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x10210982/* enum: RXDP Test firmware image 3 */10983#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x10310984/* enum: RXDP Test firmware image 4 */10985#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x10410986/* enum: RXDP Test firmware image 5 */10987#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_BACKPRESSURE 0x10510988/* enum: RXDP Test firmware image 6 */10989#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_PACKET_EDITS 0x10610990/* enum: RXDP Test firmware image 7 */10991#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x10710992/* enum: RXDP Test firmware image 8 */10993#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_DISABLE_DL 0x10810994/* enum: RXDP Test firmware image 9 */10995#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b10996/* enum: RXDP Test firmware image 10 */10997#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_SLOW 0x10c10998/* TxDPCPU firmware id. */10999#define MC_CMD_GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID_OFST 611000#define MC_CMD_GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID_LEN 211001/* enum: Standard TXDP firmware */11002#define MC_CMD_GET_CAPABILITIES_OUT_TXDP 0x011003/* enum: Low latency TXDP firmware */11004#define MC_CMD_GET_CAPABILITIES_OUT_TXDP_LOW_LATENCY 0x111005/* enum: High packet rate TXDP firmware */11006#define MC_CMD_GET_CAPABILITIES_OUT_TXDP_HIGH_PACKET_RATE 0x311007/* enum: Rules engine TXDP firmware */11008#define MC_CMD_GET_CAPABILITIES_OUT_TXDP_RULES_ENGINE 0x511009/* enum: DPDK TXDP firmware */11010#define MC_CMD_GET_CAPABILITIES_OUT_TXDP_DPDK 0x611011/* enum: BIST TXDP firmware */11012#define MC_CMD_GET_CAPABILITIES_OUT_TXDP_BIST 0x12d11013/* enum: TXDP Test firmware image 1 */11014#define MC_CMD_GET_CAPABILITIES_OUT_TXDP_TEST_FW_TSO_EDIT 0x10111015/* enum: TXDP Test firmware image 2 */11016#define MC_CMD_GET_CAPABILITIES_OUT_TXDP_TEST_FW_PACKET_EDITS 0x10211017/* enum: TXDP CSR bus test firmware */11018#define MC_CMD_GET_CAPABILITIES_OUT_TXDP_TEST_FW_CSR 0x10311019#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_OFST 811020#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_LEN 211021#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_REV_OFST 811022#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_REV_LBN 011023#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_REV_WIDTH 1211024#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_TYPE_OFST 811025#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_TYPE_LBN 1211026#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_TYPE_WIDTH 411027/* enum: reserved value - do not use (may indicate alternative interpretation11028 * of REV field in future)11029 */11030#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_RESERVED 0x011031/* enum: Trivial RX PD firmware for early Huntington development (Huntington11032 * development only)11033 */11034#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_FIRST_PKT 0x111035/* enum: RX PD firmware for telemetry prototyping (Medford2 development only)11036 */11037#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x111038/* enum: RX PD firmware with approximately Siena-compatible behaviour11039 * (Huntington development only)11040 */11041#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x211042/* enum: Full featured RX PD production firmware */11043#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x311044/* enum: (deprecated original name for the FULL_FEATURED variant) */11045#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_VSWITCH 0x311046/* enum: siena_compat variant RX PD firmware using PM rather than MAC11047 * (Huntington development only)11048 */11049#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x411050/* enum: Low latency RX PD production firmware */11051#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x511052/* enum: Packed stream RX PD production firmware */11053#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x611054/* enum: RX PD firmware handling layer 2 only for high packet rate performance11055 * tests (Medford development only)11056 */11057#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x711058/* enum: Rules engine RX PD production firmware */11059#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x811060/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */11061#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_L3XUDP 0x911062/* enum: DPDK RX PD production firmware */11063#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_DPDK 0xa11064/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */11065#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe11066/* enum: RX PD firmware parsing but not filtering network overlay tunnel11067 * encapsulations (Medford development only)11068 */11069#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf11070#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_OFST 1011071#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_LEN 211072#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_REV_OFST 1011073#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_REV_LBN 011074#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_REV_WIDTH 1211075#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_TYPE_OFST 1011076#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_TYPE_LBN 1211077#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_TYPE_WIDTH 411078/* enum: reserved value - do not use (may indicate alternative interpretation11079 * of REV field in future)11080 */11081#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_RESERVED 0x011082/* enum: Trivial TX PD firmware for early Huntington development (Huntington11083 * development only)11084 */11085#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_FIRST_PKT 0x111086/* enum: TX PD firmware for telemetry prototyping (Medford2 development only)11087 */11088#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x111089/* enum: TX PD firmware with approximately Siena-compatible behaviour11090 * (Huntington development only)11091 */11092#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x211093/* enum: Full featured TX PD production firmware */11094#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x311095/* enum: (deprecated original name for the FULL_FEATURED variant) */11096#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_VSWITCH 0x311097/* enum: siena_compat variant TX PD firmware using PM rather than MAC11098 * (Huntington development only)11099 */11100#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x411101#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */11102/* enum: TX PD firmware handling layer 2 only for high packet rate performance11103 * tests (Medford development only)11104 */11105#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x711106/* enum: Rules engine TX PD production firmware */11107#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x811108/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */11109#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_L3XUDP 0x911110/* enum: DPDK TX PD production firmware */11111#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_DPDK 0xa11112/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */11113#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe11114/* Hardware capabilities of NIC */11115#define MC_CMD_GET_CAPABILITIES_OUT_HW_CAPABILITIES_OFST 1211116#define MC_CMD_GET_CAPABILITIES_OUT_HW_CAPABILITIES_LEN 411117/* Licensed capabilities */11118#define MC_CMD_GET_CAPABILITIES_OUT_LICENSE_CAPABILITIES_OFST 1611119#define MC_CMD_GET_CAPABILITIES_OUT_LICENSE_CAPABILITIES_LEN 411120 11121/* MC_CMD_GET_CAPABILITIES_V2_IN msgrequest */11122#define MC_CMD_GET_CAPABILITIES_V2_IN_LEN 011123 11124/* MC_CMD_GET_CAPABILITIES_V2_OUT msgresponse */11125#define MC_CMD_GET_CAPABILITIES_V2_OUT_LEN 7211126/* First word of flags. */11127#define MC_CMD_GET_CAPABILITIES_V2_OUT_FLAGS1_OFST 011128#define MC_CMD_GET_CAPABILITIES_V2_OUT_FLAGS1_LEN 411129#define MC_CMD_GET_CAPABILITIES_V2_OUT_VPORT_RECONFIGURE_OFST 011130#define MC_CMD_GET_CAPABILITIES_V2_OUT_VPORT_RECONFIGURE_LBN 311131#define MC_CMD_GET_CAPABILITIES_V2_OUT_VPORT_RECONFIGURE_WIDTH 111132#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_STRIPING_OFST 011133#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_STRIPING_LBN 411134#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_STRIPING_WIDTH 111135#define MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_QUERY_OFST 011136#define MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_QUERY_LBN 511137#define MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_QUERY_WIDTH 111138#define MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_PORT_VLAN_RESTRICT_OFST 011139#define MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_PORT_VLAN_RESTRICT_LBN 611140#define MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 111141#define MC_CMD_GET_CAPABILITIES_V2_OUT_DRV_ATTACH_PREBOOT_OFST 011142#define MC_CMD_GET_CAPABILITIES_V2_OUT_DRV_ATTACH_PREBOOT_LBN 711143#define MC_CMD_GET_CAPABILITIES_V2_OUT_DRV_ATTACH_PREBOOT_WIDTH 111144#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_FORCE_EVENT_MERGING_OFST 011145#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_FORCE_EVENT_MERGING_LBN 811146#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_FORCE_EVENT_MERGING_WIDTH 111147#define MC_CMD_GET_CAPABILITIES_V2_OUT_SET_MAC_ENHANCED_OFST 011148#define MC_CMD_GET_CAPABILITIES_V2_OUT_SET_MAC_ENHANCED_LBN 911149#define MC_CMD_GET_CAPABILITIES_V2_OUT_SET_MAC_ENHANCED_WIDTH 111150#define MC_CMD_GET_CAPABILITIES_V2_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 011151#define MC_CMD_GET_CAPABILITIES_V2_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 1011152#define MC_CMD_GET_CAPABILITIES_V2_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 111153#define MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 011154#define MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 1111155#define MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 111156#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_SECURITY_FILTERING_OFST 011157#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_SECURITY_FILTERING_LBN 1211158#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 111159#define MC_CMD_GET_CAPABILITIES_V2_OUT_ADDITIONAL_RSS_MODES_OFST 011160#define MC_CMD_GET_CAPABILITIES_V2_OUT_ADDITIONAL_RSS_MODES_LBN 1311161#define MC_CMD_GET_CAPABILITIES_V2_OUT_ADDITIONAL_RSS_MODES_WIDTH 111162#define MC_CMD_GET_CAPABILITIES_V2_OUT_QBB_OFST 011163#define MC_CMD_GET_CAPABILITIES_V2_OUT_QBB_LBN 1411164#define MC_CMD_GET_CAPABILITIES_V2_OUT_QBB_WIDTH 111165#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 011166#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 1511167#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 111168#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_RSS_LIMITED_OFST 011169#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_RSS_LIMITED_LBN 1611170#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_RSS_LIMITED_WIDTH 111171#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_OFST 011172#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_LBN 1711173#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_WIDTH 111174#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_INCLUDE_FCS_OFST 011175#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_INCLUDE_FCS_LBN 1811176#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_INCLUDE_FCS_WIDTH 111177#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_VLAN_INSERTION_OFST 011178#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_VLAN_INSERTION_LBN 1911179#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_VLAN_INSERTION_WIDTH 111180#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_VLAN_STRIPPING_OFST 011181#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_VLAN_STRIPPING_LBN 2011182#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_VLAN_STRIPPING_WIDTH 111183#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_OFST 011184#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_LBN 2111185#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_WIDTH 111186#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_0_OFST 011187#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_0_LBN 2211188#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_0_WIDTH 111189#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_14_OFST 011190#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_14_LBN 2311191#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_14_WIDTH 111192#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_TIMESTAMP_OFST 011193#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_TIMESTAMP_LBN 2411194#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_TIMESTAMP_WIDTH 111195#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_BATCHING_OFST 011196#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_BATCHING_LBN 2511197#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_BATCHING_WIDTH 111198#define MC_CMD_GET_CAPABILITIES_V2_OUT_MCAST_FILTER_CHAINING_OFST 011199#define MC_CMD_GET_CAPABILITIES_V2_OUT_MCAST_FILTER_CHAINING_LBN 2611200#define MC_CMD_GET_CAPABILITIES_V2_OUT_MCAST_FILTER_CHAINING_WIDTH 111201#define MC_CMD_GET_CAPABILITIES_V2_OUT_PM_AND_RXDP_COUNTERS_OFST 011202#define MC_CMD_GET_CAPABILITIES_V2_OUT_PM_AND_RXDP_COUNTERS_LBN 2711203#define MC_CMD_GET_CAPABILITIES_V2_OUT_PM_AND_RXDP_COUNTERS_WIDTH 111204#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DISABLE_SCATTER_OFST 011205#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DISABLE_SCATTER_LBN 2811206#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DISABLE_SCATTER_WIDTH 111207#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MCAST_UDP_LOOPBACK_OFST 011208#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MCAST_UDP_LOOPBACK_LBN 2911209#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 111210#define MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_OFST 011211#define MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_LBN 3011212#define MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_WIDTH 111213#define MC_CMD_GET_CAPABILITIES_V2_OUT_VXLAN_NVGRE_OFST 011214#define MC_CMD_GET_CAPABILITIES_V2_OUT_VXLAN_NVGRE_LBN 3111215#define MC_CMD_GET_CAPABILITIES_V2_OUT_VXLAN_NVGRE_WIDTH 111216/* RxDPCPU firmware id. */11217#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DPCPU_FW_ID_OFST 411218#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DPCPU_FW_ID_LEN 211219/* enum: Standard RXDP firmware */11220#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP 0x011221/* enum: Low latency RXDP firmware */11222#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_LOW_LATENCY 0x111223/* enum: Packed stream RXDP firmware */11224#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_PACKED_STREAM 0x211225/* enum: Rules engine RXDP firmware */11226#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_RULES_ENGINE 0x511227/* enum: DPDK RXDP firmware */11228#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_DPDK 0x611229/* enum: BIST RXDP firmware */11230#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_BIST 0x10a11231/* enum: RXDP Test firmware image 1 */11232#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x10111233/* enum: RXDP Test firmware image 2 */11234#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x10211235/* enum: RXDP Test firmware image 3 */11236#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x10311237/* enum: RXDP Test firmware image 4 */11238#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x10411239/* enum: RXDP Test firmware image 5 */11240#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_BACKPRESSURE 0x10511241/* enum: RXDP Test firmware image 6 */11242#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_PACKET_EDITS 0x10611243/* enum: RXDP Test firmware image 7 */11244#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x10711245/* enum: RXDP Test firmware image 8 */11246#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_DISABLE_DL 0x10811247/* enum: RXDP Test firmware image 9 */11248#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b11249/* enum: RXDP Test firmware image 10 */11250#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_SLOW 0x10c11251/* TxDPCPU firmware id. */11252#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_DPCPU_FW_ID_OFST 611253#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_DPCPU_FW_ID_LEN 211254/* enum: Standard TXDP firmware */11255#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP 0x011256/* enum: Low latency TXDP firmware */11257#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_LOW_LATENCY 0x111258/* enum: High packet rate TXDP firmware */11259#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_HIGH_PACKET_RATE 0x311260/* enum: Rules engine TXDP firmware */11261#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_RULES_ENGINE 0x511262/* enum: DPDK TXDP firmware */11263#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_DPDK 0x611264/* enum: BIST TXDP firmware */11265#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_BIST 0x12d11266/* enum: TXDP Test firmware image 1 */11267#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_TEST_FW_TSO_EDIT 0x10111268/* enum: TXDP Test firmware image 2 */11269#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_TEST_FW_PACKET_EDITS 0x10211270/* enum: TXDP CSR bus test firmware */11271#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_TEST_FW_CSR 0x10311272#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_OFST 811273#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_LEN 211274#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_REV_OFST 811275#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_REV_LBN 011276#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_REV_WIDTH 1211277#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_TYPE_OFST 811278#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_TYPE_LBN 1211279#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_TYPE_WIDTH 411280/* enum: reserved value - do not use (may indicate alternative interpretation11281 * of REV field in future)11282 */11283#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_RESERVED 0x011284/* enum: Trivial RX PD firmware for early Huntington development (Huntington11285 * development only)11286 */11287#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_FIRST_PKT 0x111288/* enum: RX PD firmware for telemetry prototyping (Medford2 development only)11289 */11290#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x111291/* enum: RX PD firmware with approximately Siena-compatible behaviour11292 * (Huntington development only)11293 */11294#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x211295/* enum: Full featured RX PD production firmware */11296#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x311297/* enum: (deprecated original name for the FULL_FEATURED variant) */11298#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_VSWITCH 0x311299/* enum: siena_compat variant RX PD firmware using PM rather than MAC11300 * (Huntington development only)11301 */11302#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x411303/* enum: Low latency RX PD production firmware */11304#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x511305/* enum: Packed stream RX PD production firmware */11306#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x611307/* enum: RX PD firmware handling layer 2 only for high packet rate performance11308 * tests (Medford development only)11309 */11310#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x711311/* enum: Rules engine RX PD production firmware */11312#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x811313/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */11314#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_L3XUDP 0x911315/* enum: DPDK RX PD production firmware */11316#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_DPDK 0xa11317/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */11318#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe11319/* enum: RX PD firmware parsing but not filtering network overlay tunnel11320 * encapsulations (Medford development only)11321 */11322#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf11323#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_OFST 1011324#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_LEN 211325#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_REV_OFST 1011326#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_REV_LBN 011327#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_REV_WIDTH 1211328#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_TYPE_OFST 1011329#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_TYPE_LBN 1211330#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_TYPE_WIDTH 411331/* enum: reserved value - do not use (may indicate alternative interpretation11332 * of REV field in future)11333 */11334#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_RESERVED 0x011335/* enum: Trivial TX PD firmware for early Huntington development (Huntington11336 * development only)11337 */11338#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_FIRST_PKT 0x111339/* enum: TX PD firmware for telemetry prototyping (Medford2 development only)11340 */11341#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x111342/* enum: TX PD firmware with approximately Siena-compatible behaviour11343 * (Huntington development only)11344 */11345#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x211346/* enum: Full featured TX PD production firmware */11347#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x311348/* enum: (deprecated original name for the FULL_FEATURED variant) */11349#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_VSWITCH 0x311350/* enum: siena_compat variant TX PD firmware using PM rather than MAC11351 * (Huntington development only)11352 */11353#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x411354#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */11355/* enum: TX PD firmware handling layer 2 only for high packet rate performance11356 * tests (Medford development only)11357 */11358#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x711359/* enum: Rules engine TX PD production firmware */11360#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x811361/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */11362#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_L3XUDP 0x911363/* enum: DPDK TX PD production firmware */11364#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_DPDK 0xa11365/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */11366#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe11367/* Hardware capabilities of NIC */11368#define MC_CMD_GET_CAPABILITIES_V2_OUT_HW_CAPABILITIES_OFST 1211369#define MC_CMD_GET_CAPABILITIES_V2_OUT_HW_CAPABILITIES_LEN 411370/* Licensed capabilities */11371#define MC_CMD_GET_CAPABILITIES_V2_OUT_LICENSE_CAPABILITIES_OFST 1611372#define MC_CMD_GET_CAPABILITIES_V2_OUT_LICENSE_CAPABILITIES_LEN 411373/* Second word of flags. Not present on older firmware (check the length). */11374#define MC_CMD_GET_CAPABILITIES_V2_OUT_FLAGS2_OFST 2011375#define MC_CMD_GET_CAPABILITIES_V2_OUT_FLAGS2_LEN 411376#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_OFST 2011377#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_LBN 011378#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_WIDTH 111379#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_ENCAP_OFST 2011380#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_ENCAP_LBN 111381#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_ENCAP_WIDTH 111382#define MC_CMD_GET_CAPABILITIES_V2_OUT_EVQ_TIMER_CTRL_OFST 2011383#define MC_CMD_GET_CAPABILITIES_V2_OUT_EVQ_TIMER_CTRL_LBN 211384#define MC_CMD_GET_CAPABILITIES_V2_OUT_EVQ_TIMER_CTRL_WIDTH 111385#define MC_CMD_GET_CAPABILITIES_V2_OUT_EVENT_CUT_THROUGH_OFST 2011386#define MC_CMD_GET_CAPABILITIES_V2_OUT_EVENT_CUT_THROUGH_LBN 311387#define MC_CMD_GET_CAPABILITIES_V2_OUT_EVENT_CUT_THROUGH_WIDTH 111388#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_CUT_THROUGH_OFST 2011389#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_CUT_THROUGH_LBN 411390#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_CUT_THROUGH_WIDTH 111391#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_VFIFO_ULL_MODE_OFST 2011392#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_VFIFO_ULL_MODE_LBN 511393#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_VFIFO_ULL_MODE_WIDTH 111394#define MC_CMD_GET_CAPABILITIES_V2_OUT_MAC_STATS_40G_TX_SIZE_BINS_OFST 2011395#define MC_CMD_GET_CAPABILITIES_V2_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 611396#define MC_CMD_GET_CAPABILITIES_V2_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 111397#define MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_EVQ_TYPE_SUPPORTED_OFST 2011398#define MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_EVQ_TYPE_SUPPORTED_LBN 711399#define MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_EVQ_TYPE_SUPPORTED_WIDTH 111400#define MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_EVQ_V2_OFST 2011401#define MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_EVQ_V2_LBN 711402#define MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_EVQ_V2_WIDTH 111403#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_TIMESTAMPING_OFST 2011404#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_TIMESTAMPING_LBN 811405#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_TIMESTAMPING_WIDTH 111406#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TIMESTAMP_OFST 2011407#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TIMESTAMP_LBN 911408#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TIMESTAMP_WIDTH 111409#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_SNIFF_OFST 2011410#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_SNIFF_LBN 1011411#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_SNIFF_WIDTH 111412#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_SNIFF_OFST 2011413#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_SNIFF_LBN 1111414#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_SNIFF_WIDTH 111415#define MC_CMD_GET_CAPABILITIES_V2_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_OFST 2011416#define MC_CMD_GET_CAPABILITIES_V2_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_LBN 1211417#define MC_CMD_GET_CAPABILITIES_V2_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 111418#define MC_CMD_GET_CAPABILITIES_V2_OUT_MCDI_BACKGROUND_OFST 2011419#define MC_CMD_GET_CAPABILITIES_V2_OUT_MCDI_BACKGROUND_LBN 1311420#define MC_CMD_GET_CAPABILITIES_V2_OUT_MCDI_BACKGROUND_WIDTH 111421#define MC_CMD_GET_CAPABILITIES_V2_OUT_MCDI_DB_RETURN_OFST 2011422#define MC_CMD_GET_CAPABILITIES_V2_OUT_MCDI_DB_RETURN_LBN 1411423#define MC_CMD_GET_CAPABILITIES_V2_OUT_MCDI_DB_RETURN_WIDTH 111424#define MC_CMD_GET_CAPABILITIES_V2_OUT_CTPIO_OFST 2011425#define MC_CMD_GET_CAPABILITIES_V2_OUT_CTPIO_LBN 1511426#define MC_CMD_GET_CAPABILITIES_V2_OUT_CTPIO_WIDTH 111427#define MC_CMD_GET_CAPABILITIES_V2_OUT_TSA_SUPPORT_OFST 2011428#define MC_CMD_GET_CAPABILITIES_V2_OUT_TSA_SUPPORT_LBN 1611429#define MC_CMD_GET_CAPABILITIES_V2_OUT_TSA_SUPPORT_WIDTH 111430#define MC_CMD_GET_CAPABILITIES_V2_OUT_TSA_BOUND_OFST 2011431#define MC_CMD_GET_CAPABILITIES_V2_OUT_TSA_BOUND_LBN 1711432#define MC_CMD_GET_CAPABILITIES_V2_OUT_TSA_BOUND_WIDTH 111433#define MC_CMD_GET_CAPABILITIES_V2_OUT_SF_ADAPTER_AUTHENTICATION_OFST 2011434#define MC_CMD_GET_CAPABILITIES_V2_OUT_SF_ADAPTER_AUTHENTICATION_LBN 1811435#define MC_CMD_GET_CAPABILITIES_V2_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 111436#define MC_CMD_GET_CAPABILITIES_V2_OUT_FILTER_ACTION_FLAG_OFST 2011437#define MC_CMD_GET_CAPABILITIES_V2_OUT_FILTER_ACTION_FLAG_LBN 1911438#define MC_CMD_GET_CAPABILITIES_V2_OUT_FILTER_ACTION_FLAG_WIDTH 111439#define MC_CMD_GET_CAPABILITIES_V2_OUT_FILTER_ACTION_MARK_OFST 2011440#define MC_CMD_GET_CAPABILITIES_V2_OUT_FILTER_ACTION_MARK_LBN 2011441#define MC_CMD_GET_CAPABILITIES_V2_OUT_FILTER_ACTION_MARK_WIDTH 111442#define MC_CMD_GET_CAPABILITIES_V2_OUT_EQUAL_STRIDE_SUPER_BUFFER_OFST 2011443#define MC_CMD_GET_CAPABILITIES_V2_OUT_EQUAL_STRIDE_SUPER_BUFFER_LBN 2111444#define MC_CMD_GET_CAPABILITIES_V2_OUT_EQUAL_STRIDE_SUPER_BUFFER_WIDTH 111445#define MC_CMD_GET_CAPABILITIES_V2_OUT_EQUAL_STRIDE_PACKED_STREAM_OFST 2011446#define MC_CMD_GET_CAPABILITIES_V2_OUT_EQUAL_STRIDE_PACKED_STREAM_LBN 2111447#define MC_CMD_GET_CAPABILITIES_V2_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 111448#define MC_CMD_GET_CAPABILITIES_V2_OUT_L3XUDP_SUPPORT_OFST 2011449#define MC_CMD_GET_CAPABILITIES_V2_OUT_L3XUDP_SUPPORT_LBN 2211450#define MC_CMD_GET_CAPABILITIES_V2_OUT_L3XUDP_SUPPORT_WIDTH 111451#define MC_CMD_GET_CAPABILITIES_V2_OUT_FW_SUBVARIANT_NO_TX_CSUM_OFST 2011452#define MC_CMD_GET_CAPABILITIES_V2_OUT_FW_SUBVARIANT_NO_TX_CSUM_LBN 2311453#define MC_CMD_GET_CAPABILITIES_V2_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 111454#define MC_CMD_GET_CAPABILITIES_V2_OUT_VI_SPREADING_OFST 2011455#define MC_CMD_GET_CAPABILITIES_V2_OUT_VI_SPREADING_LBN 2411456#define MC_CMD_GET_CAPABILITIES_V2_OUT_VI_SPREADING_WIDTH 111457#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_HLB_IDLE_OFST 2011458#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_HLB_IDLE_LBN 2511459#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_HLB_IDLE_WIDTH 111460#define MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_RXQ_NO_CONT_EV_OFST 2011461#define MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_RXQ_NO_CONT_EV_LBN 2611462#define MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_RXQ_NO_CONT_EV_WIDTH 111463#define MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_RXQ_WITH_BUFFER_SIZE_OFST 2011464#define MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_RXQ_WITH_BUFFER_SIZE_LBN 2711465#define MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_RXQ_WITH_BUFFER_SIZE_WIDTH 111466#define MC_CMD_GET_CAPABILITIES_V2_OUT_BUNDLE_UPDATE_OFST 2011467#define MC_CMD_GET_CAPABILITIES_V2_OUT_BUNDLE_UPDATE_LBN 2811468#define MC_CMD_GET_CAPABILITIES_V2_OUT_BUNDLE_UPDATE_WIDTH 111469#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V3_OFST 2011470#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V3_LBN 2911471#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V3_WIDTH 111472#define MC_CMD_GET_CAPABILITIES_V2_OUT_DYNAMIC_SENSORS_OFST 2011473#define MC_CMD_GET_CAPABILITIES_V2_OUT_DYNAMIC_SENSORS_LBN 3011474#define MC_CMD_GET_CAPABILITIES_V2_OUT_DYNAMIC_SENSORS_WIDTH 111475#define MC_CMD_GET_CAPABILITIES_V2_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_OFST 2011476#define MC_CMD_GET_CAPABILITIES_V2_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_LBN 3111477#define MC_CMD_GET_CAPABILITIES_V2_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_WIDTH 111478/* Number of FATSOv2 contexts per datapath supported by this NIC (when11479 * TX_TSO_V2 == 1). Not present on older firmware (check the length).11480 */11481#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_N_CONTEXTS_OFST 2411482#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_N_CONTEXTS_LEN 211483/* One byte per PF containing the number of the external port assigned to this11484 * PF, indexed by PF number. Special values indicate that a PF is either not11485 * present or not assigned.11486 */11487#define MC_CMD_GET_CAPABILITIES_V2_OUT_PFS_TO_PORTS_ASSIGNMENT_OFST 2611488#define MC_CMD_GET_CAPABILITIES_V2_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 111489#define MC_CMD_GET_CAPABILITIES_V2_OUT_PFS_TO_PORTS_ASSIGNMENT_NUM 1611490/* enum: The caller is not permitted to access information on this PF. */11491#define MC_CMD_GET_CAPABILITIES_V2_OUT_ACCESS_NOT_PERMITTED 0xff11492/* enum: PF does not exist. */11493#define MC_CMD_GET_CAPABILITIES_V2_OUT_PF_NOT_PRESENT 0xfe11494/* enum: PF does exist but is not assigned to any external port. */11495#define MC_CMD_GET_CAPABILITIES_V2_OUT_PF_NOT_ASSIGNED 0xfd11496/* enum: This value indicates that PF is assigned, but it cannot be expressed11497 * in this field. It is intended for a possible future situation where a more11498 * complex scheme of PFs to ports mapping is being used. The future driver11499 * should look for a new field supporting the new scheme. The current/old11500 * driver should treat this value as PF_NOT_ASSIGNED.11501 */11502#define MC_CMD_GET_CAPABILITIES_V2_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc11503/* One byte per PF containing the number of its VFs, indexed by PF number. A11504 * special value indicates that a PF is not present.11505 */11506#define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VFS_PER_PF_OFST 4211507#define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VFS_PER_PF_LEN 111508#define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VFS_PER_PF_NUM 1611509/* enum: The caller is not permitted to access information on this PF. */11510/* MC_CMD_GET_CAPABILITIES_V2_OUT_ACCESS_NOT_PERMITTED 0xff */11511/* enum: PF does not exist. */11512/* MC_CMD_GET_CAPABILITIES_V2_OUT_PF_NOT_PRESENT 0xfe */11513/* Number of VIs available for each external port */11514#define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VIS_PER_PORT_OFST 5811515#define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VIS_PER_PORT_LEN 211516#define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VIS_PER_PORT_NUM 411517/* Size of RX descriptor cache expressed as binary logarithm The actual size11518 * equals (2 ^ RX_DESC_CACHE_SIZE)11519 */11520#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DESC_CACHE_SIZE_OFST 6611521#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DESC_CACHE_SIZE_LEN 111522/* Size of TX descriptor cache expressed as binary logarithm The actual size11523 * equals (2 ^ TX_DESC_CACHE_SIZE)11524 */11525#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_DESC_CACHE_SIZE_OFST 6711526#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_DESC_CACHE_SIZE_LEN 111527/* Total number of available PIO buffers */11528#define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_PIO_BUFFS_OFST 6811529#define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_PIO_BUFFS_LEN 211530/* Size of a single PIO buffer */11531#define MC_CMD_GET_CAPABILITIES_V2_OUT_SIZE_PIO_BUFF_OFST 7011532#define MC_CMD_GET_CAPABILITIES_V2_OUT_SIZE_PIO_BUFF_LEN 211533 11534/* MC_CMD_GET_CAPABILITIES_V3_OUT msgresponse */11535#define MC_CMD_GET_CAPABILITIES_V3_OUT_LEN 7611536/* First word of flags. */11537#define MC_CMD_GET_CAPABILITIES_V3_OUT_FLAGS1_OFST 011538#define MC_CMD_GET_CAPABILITIES_V3_OUT_FLAGS1_LEN 411539#define MC_CMD_GET_CAPABILITIES_V3_OUT_VPORT_RECONFIGURE_OFST 011540#define MC_CMD_GET_CAPABILITIES_V3_OUT_VPORT_RECONFIGURE_LBN 311541#define MC_CMD_GET_CAPABILITIES_V3_OUT_VPORT_RECONFIGURE_WIDTH 111542#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_STRIPING_OFST 011543#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_STRIPING_LBN 411544#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_STRIPING_WIDTH 111545#define MC_CMD_GET_CAPABILITIES_V3_OUT_VADAPTOR_QUERY_OFST 011546#define MC_CMD_GET_CAPABILITIES_V3_OUT_VADAPTOR_QUERY_LBN 511547#define MC_CMD_GET_CAPABILITIES_V3_OUT_VADAPTOR_QUERY_WIDTH 111548#define MC_CMD_GET_CAPABILITIES_V3_OUT_EVB_PORT_VLAN_RESTRICT_OFST 011549#define MC_CMD_GET_CAPABILITIES_V3_OUT_EVB_PORT_VLAN_RESTRICT_LBN 611550#define MC_CMD_GET_CAPABILITIES_V3_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 111551#define MC_CMD_GET_CAPABILITIES_V3_OUT_DRV_ATTACH_PREBOOT_OFST 011552#define MC_CMD_GET_CAPABILITIES_V3_OUT_DRV_ATTACH_PREBOOT_LBN 711553#define MC_CMD_GET_CAPABILITIES_V3_OUT_DRV_ATTACH_PREBOOT_WIDTH 111554#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_FORCE_EVENT_MERGING_OFST 011555#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_FORCE_EVENT_MERGING_LBN 811556#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_FORCE_EVENT_MERGING_WIDTH 111557#define MC_CMD_GET_CAPABILITIES_V3_OUT_SET_MAC_ENHANCED_OFST 011558#define MC_CMD_GET_CAPABILITIES_V3_OUT_SET_MAC_ENHANCED_LBN 911559#define MC_CMD_GET_CAPABILITIES_V3_OUT_SET_MAC_ENHANCED_WIDTH 111560#define MC_CMD_GET_CAPABILITIES_V3_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 011561#define MC_CMD_GET_CAPABILITIES_V3_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 1011562#define MC_CMD_GET_CAPABILITIES_V3_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 111563#define MC_CMD_GET_CAPABILITIES_V3_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 011564#define MC_CMD_GET_CAPABILITIES_V3_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 1111565#define MC_CMD_GET_CAPABILITIES_V3_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 111566#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MAC_SECURITY_FILTERING_OFST 011567#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MAC_SECURITY_FILTERING_LBN 1211568#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 111569#define MC_CMD_GET_CAPABILITIES_V3_OUT_ADDITIONAL_RSS_MODES_OFST 011570#define MC_CMD_GET_CAPABILITIES_V3_OUT_ADDITIONAL_RSS_MODES_LBN 1311571#define MC_CMD_GET_CAPABILITIES_V3_OUT_ADDITIONAL_RSS_MODES_WIDTH 111572#define MC_CMD_GET_CAPABILITIES_V3_OUT_QBB_OFST 011573#define MC_CMD_GET_CAPABILITIES_V3_OUT_QBB_LBN 1411574#define MC_CMD_GET_CAPABILITIES_V3_OUT_QBB_WIDTH 111575#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 011576#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 1511577#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 111578#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_RSS_LIMITED_OFST 011579#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_RSS_LIMITED_LBN 1611580#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_RSS_LIMITED_WIDTH 111581#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PACKED_STREAM_OFST 011582#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PACKED_STREAM_LBN 1711583#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PACKED_STREAM_WIDTH 111584#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_INCLUDE_FCS_OFST 011585#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_INCLUDE_FCS_LBN 1811586#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_INCLUDE_FCS_WIDTH 111587#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_VLAN_INSERTION_OFST 011588#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_VLAN_INSERTION_LBN 1911589#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_VLAN_INSERTION_WIDTH 111590#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_VLAN_STRIPPING_OFST 011591#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_VLAN_STRIPPING_LBN 2011592#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_VLAN_STRIPPING_WIDTH 111593#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_OFST 011594#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_LBN 2111595#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_WIDTH 111596#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PREFIX_LEN_0_OFST 011597#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PREFIX_LEN_0_LBN 2211598#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PREFIX_LEN_0_WIDTH 111599#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PREFIX_LEN_14_OFST 011600#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PREFIX_LEN_14_LBN 2311601#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PREFIX_LEN_14_WIDTH 111602#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_TIMESTAMP_OFST 011603#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_TIMESTAMP_LBN 2411604#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_TIMESTAMP_WIDTH 111605#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_BATCHING_OFST 011606#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_BATCHING_LBN 2511607#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_BATCHING_WIDTH 111608#define MC_CMD_GET_CAPABILITIES_V3_OUT_MCAST_FILTER_CHAINING_OFST 011609#define MC_CMD_GET_CAPABILITIES_V3_OUT_MCAST_FILTER_CHAINING_LBN 2611610#define MC_CMD_GET_CAPABILITIES_V3_OUT_MCAST_FILTER_CHAINING_WIDTH 111611#define MC_CMD_GET_CAPABILITIES_V3_OUT_PM_AND_RXDP_COUNTERS_OFST 011612#define MC_CMD_GET_CAPABILITIES_V3_OUT_PM_AND_RXDP_COUNTERS_LBN 2711613#define MC_CMD_GET_CAPABILITIES_V3_OUT_PM_AND_RXDP_COUNTERS_WIDTH 111614#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DISABLE_SCATTER_OFST 011615#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DISABLE_SCATTER_LBN 2811616#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DISABLE_SCATTER_WIDTH 111617#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MCAST_UDP_LOOPBACK_OFST 011618#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MCAST_UDP_LOOPBACK_LBN 2911619#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 111620#define MC_CMD_GET_CAPABILITIES_V3_OUT_EVB_OFST 011621#define MC_CMD_GET_CAPABILITIES_V3_OUT_EVB_LBN 3011622#define MC_CMD_GET_CAPABILITIES_V3_OUT_EVB_WIDTH 111623#define MC_CMD_GET_CAPABILITIES_V3_OUT_VXLAN_NVGRE_OFST 011624#define MC_CMD_GET_CAPABILITIES_V3_OUT_VXLAN_NVGRE_LBN 3111625#define MC_CMD_GET_CAPABILITIES_V3_OUT_VXLAN_NVGRE_WIDTH 111626/* RxDPCPU firmware id. */11627#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DPCPU_FW_ID_OFST 411628#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DPCPU_FW_ID_LEN 211629/* enum: Standard RXDP firmware */11630#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP 0x011631/* enum: Low latency RXDP firmware */11632#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_LOW_LATENCY 0x111633/* enum: Packed stream RXDP firmware */11634#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_PACKED_STREAM 0x211635/* enum: Rules engine RXDP firmware */11636#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_RULES_ENGINE 0x511637/* enum: DPDK RXDP firmware */11638#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_DPDK 0x611639/* enum: BIST RXDP firmware */11640#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_BIST 0x10a11641/* enum: RXDP Test firmware image 1 */11642#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x10111643/* enum: RXDP Test firmware image 2 */11644#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x10211645/* enum: RXDP Test firmware image 3 */11646#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x10311647/* enum: RXDP Test firmware image 4 */11648#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x10411649/* enum: RXDP Test firmware image 5 */11650#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_BACKPRESSURE 0x10511651/* enum: RXDP Test firmware image 6 */11652#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_PACKET_EDITS 0x10611653/* enum: RXDP Test firmware image 7 */11654#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x10711655/* enum: RXDP Test firmware image 8 */11656#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_DISABLE_DL 0x10811657/* enum: RXDP Test firmware image 9 */11658#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b11659/* enum: RXDP Test firmware image 10 */11660#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_SLOW 0x10c11661/* TxDPCPU firmware id. */11662#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_DPCPU_FW_ID_OFST 611663#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_DPCPU_FW_ID_LEN 211664/* enum: Standard TXDP firmware */11665#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP 0x011666/* enum: Low latency TXDP firmware */11667#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_LOW_LATENCY 0x111668/* enum: High packet rate TXDP firmware */11669#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_HIGH_PACKET_RATE 0x311670/* enum: Rules engine TXDP firmware */11671#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_RULES_ENGINE 0x511672/* enum: DPDK TXDP firmware */11673#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_DPDK 0x611674/* enum: BIST TXDP firmware */11675#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_BIST 0x12d11676/* enum: TXDP Test firmware image 1 */11677#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_TEST_FW_TSO_EDIT 0x10111678/* enum: TXDP Test firmware image 2 */11679#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_TEST_FW_PACKET_EDITS 0x10211680/* enum: TXDP CSR bus test firmware */11681#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_TEST_FW_CSR 0x10311682#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_OFST 811683#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_LEN 211684#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_REV_OFST 811685#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_REV_LBN 011686#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_REV_WIDTH 1211687#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_TYPE_OFST 811688#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_TYPE_LBN 1211689#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_TYPE_WIDTH 411690/* enum: reserved value - do not use (may indicate alternative interpretation11691 * of REV field in future)11692 */11693#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_RESERVED 0x011694/* enum: Trivial RX PD firmware for early Huntington development (Huntington11695 * development only)11696 */11697#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_FIRST_PKT 0x111698/* enum: RX PD firmware for telemetry prototyping (Medford2 development only)11699 */11700#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x111701/* enum: RX PD firmware with approximately Siena-compatible behaviour11702 * (Huntington development only)11703 */11704#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x211705/* enum: Full featured RX PD production firmware */11706#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x311707/* enum: (deprecated original name for the FULL_FEATURED variant) */11708#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_VSWITCH 0x311709/* enum: siena_compat variant RX PD firmware using PM rather than MAC11710 * (Huntington development only)11711 */11712#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x411713/* enum: Low latency RX PD production firmware */11714#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x511715/* enum: Packed stream RX PD production firmware */11716#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x611717/* enum: RX PD firmware handling layer 2 only for high packet rate performance11718 * tests (Medford development only)11719 */11720#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x711721/* enum: Rules engine RX PD production firmware */11722#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x811723/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */11724#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_L3XUDP 0x911725/* enum: DPDK RX PD production firmware */11726#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_DPDK 0xa11727/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */11728#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe11729/* enum: RX PD firmware parsing but not filtering network overlay tunnel11730 * encapsulations (Medford development only)11731 */11732#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf11733#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_OFST 1011734#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_LEN 211735#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_REV_OFST 1011736#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_REV_LBN 011737#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_REV_WIDTH 1211738#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_TYPE_OFST 1011739#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_TYPE_LBN 1211740#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_TYPE_WIDTH 411741/* enum: reserved value - do not use (may indicate alternative interpretation11742 * of REV field in future)11743 */11744#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_RESERVED 0x011745/* enum: Trivial TX PD firmware for early Huntington development (Huntington11746 * development only)11747 */11748#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_FIRST_PKT 0x111749/* enum: TX PD firmware for telemetry prototyping (Medford2 development only)11750 */11751#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x111752/* enum: TX PD firmware with approximately Siena-compatible behaviour11753 * (Huntington development only)11754 */11755#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x211756/* enum: Full featured TX PD production firmware */11757#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x311758/* enum: (deprecated original name for the FULL_FEATURED variant) */11759#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_VSWITCH 0x311760/* enum: siena_compat variant TX PD firmware using PM rather than MAC11761 * (Huntington development only)11762 */11763#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x411764#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */11765/* enum: TX PD firmware handling layer 2 only for high packet rate performance11766 * tests (Medford development only)11767 */11768#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x711769/* enum: Rules engine TX PD production firmware */11770#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x811771/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */11772#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_L3XUDP 0x911773/* enum: DPDK TX PD production firmware */11774#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_DPDK 0xa11775/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */11776#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe11777/* Hardware capabilities of NIC */11778#define MC_CMD_GET_CAPABILITIES_V3_OUT_HW_CAPABILITIES_OFST 1211779#define MC_CMD_GET_CAPABILITIES_V3_OUT_HW_CAPABILITIES_LEN 411780/* Licensed capabilities */11781#define MC_CMD_GET_CAPABILITIES_V3_OUT_LICENSE_CAPABILITIES_OFST 1611782#define MC_CMD_GET_CAPABILITIES_V3_OUT_LICENSE_CAPABILITIES_LEN 411783/* Second word of flags. Not present on older firmware (check the length). */11784#define MC_CMD_GET_CAPABILITIES_V3_OUT_FLAGS2_OFST 2011785#define MC_CMD_GET_CAPABILITIES_V3_OUT_FLAGS2_LEN 411786#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_OFST 2011787#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_LBN 011788#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_WIDTH 111789#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_ENCAP_OFST 2011790#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_ENCAP_LBN 111791#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_ENCAP_WIDTH 111792#define MC_CMD_GET_CAPABILITIES_V3_OUT_EVQ_TIMER_CTRL_OFST 2011793#define MC_CMD_GET_CAPABILITIES_V3_OUT_EVQ_TIMER_CTRL_LBN 211794#define MC_CMD_GET_CAPABILITIES_V3_OUT_EVQ_TIMER_CTRL_WIDTH 111795#define MC_CMD_GET_CAPABILITIES_V3_OUT_EVENT_CUT_THROUGH_OFST 2011796#define MC_CMD_GET_CAPABILITIES_V3_OUT_EVENT_CUT_THROUGH_LBN 311797#define MC_CMD_GET_CAPABILITIES_V3_OUT_EVENT_CUT_THROUGH_WIDTH 111798#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_CUT_THROUGH_OFST 2011799#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_CUT_THROUGH_LBN 411800#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_CUT_THROUGH_WIDTH 111801#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_VFIFO_ULL_MODE_OFST 2011802#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_VFIFO_ULL_MODE_LBN 511803#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_VFIFO_ULL_MODE_WIDTH 111804#define MC_CMD_GET_CAPABILITIES_V3_OUT_MAC_STATS_40G_TX_SIZE_BINS_OFST 2011805#define MC_CMD_GET_CAPABILITIES_V3_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 611806#define MC_CMD_GET_CAPABILITIES_V3_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 111807#define MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_EVQ_TYPE_SUPPORTED_OFST 2011808#define MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_EVQ_TYPE_SUPPORTED_LBN 711809#define MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_EVQ_TYPE_SUPPORTED_WIDTH 111810#define MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_EVQ_V2_OFST 2011811#define MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_EVQ_V2_LBN 711812#define MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_EVQ_V2_WIDTH 111813#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MAC_TIMESTAMPING_OFST 2011814#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MAC_TIMESTAMPING_LBN 811815#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MAC_TIMESTAMPING_WIDTH 111816#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TIMESTAMP_OFST 2011817#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TIMESTAMP_LBN 911818#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TIMESTAMP_WIDTH 111819#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_SNIFF_OFST 2011820#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_SNIFF_LBN 1011821#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_SNIFF_WIDTH 111822#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_SNIFF_OFST 2011823#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_SNIFF_LBN 1111824#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_SNIFF_WIDTH 111825#define MC_CMD_GET_CAPABILITIES_V3_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_OFST 2011826#define MC_CMD_GET_CAPABILITIES_V3_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_LBN 1211827#define MC_CMD_GET_CAPABILITIES_V3_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 111828#define MC_CMD_GET_CAPABILITIES_V3_OUT_MCDI_BACKGROUND_OFST 2011829#define MC_CMD_GET_CAPABILITIES_V3_OUT_MCDI_BACKGROUND_LBN 1311830#define MC_CMD_GET_CAPABILITIES_V3_OUT_MCDI_BACKGROUND_WIDTH 111831#define MC_CMD_GET_CAPABILITIES_V3_OUT_MCDI_DB_RETURN_OFST 2011832#define MC_CMD_GET_CAPABILITIES_V3_OUT_MCDI_DB_RETURN_LBN 1411833#define MC_CMD_GET_CAPABILITIES_V3_OUT_MCDI_DB_RETURN_WIDTH 111834#define MC_CMD_GET_CAPABILITIES_V3_OUT_CTPIO_OFST 2011835#define MC_CMD_GET_CAPABILITIES_V3_OUT_CTPIO_LBN 1511836#define MC_CMD_GET_CAPABILITIES_V3_OUT_CTPIO_WIDTH 111837#define MC_CMD_GET_CAPABILITIES_V3_OUT_TSA_SUPPORT_OFST 2011838#define MC_CMD_GET_CAPABILITIES_V3_OUT_TSA_SUPPORT_LBN 1611839#define MC_CMD_GET_CAPABILITIES_V3_OUT_TSA_SUPPORT_WIDTH 111840#define MC_CMD_GET_CAPABILITIES_V3_OUT_TSA_BOUND_OFST 2011841#define MC_CMD_GET_CAPABILITIES_V3_OUT_TSA_BOUND_LBN 1711842#define MC_CMD_GET_CAPABILITIES_V3_OUT_TSA_BOUND_WIDTH 111843#define MC_CMD_GET_CAPABILITIES_V3_OUT_SF_ADAPTER_AUTHENTICATION_OFST 2011844#define MC_CMD_GET_CAPABILITIES_V3_OUT_SF_ADAPTER_AUTHENTICATION_LBN 1811845#define MC_CMD_GET_CAPABILITIES_V3_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 111846#define MC_CMD_GET_CAPABILITIES_V3_OUT_FILTER_ACTION_FLAG_OFST 2011847#define MC_CMD_GET_CAPABILITIES_V3_OUT_FILTER_ACTION_FLAG_LBN 1911848#define MC_CMD_GET_CAPABILITIES_V3_OUT_FILTER_ACTION_FLAG_WIDTH 111849#define MC_CMD_GET_CAPABILITIES_V3_OUT_FILTER_ACTION_MARK_OFST 2011850#define MC_CMD_GET_CAPABILITIES_V3_OUT_FILTER_ACTION_MARK_LBN 2011851#define MC_CMD_GET_CAPABILITIES_V3_OUT_FILTER_ACTION_MARK_WIDTH 111852#define MC_CMD_GET_CAPABILITIES_V3_OUT_EQUAL_STRIDE_SUPER_BUFFER_OFST 2011853#define MC_CMD_GET_CAPABILITIES_V3_OUT_EQUAL_STRIDE_SUPER_BUFFER_LBN 2111854#define MC_CMD_GET_CAPABILITIES_V3_OUT_EQUAL_STRIDE_SUPER_BUFFER_WIDTH 111855#define MC_CMD_GET_CAPABILITIES_V3_OUT_EQUAL_STRIDE_PACKED_STREAM_OFST 2011856#define MC_CMD_GET_CAPABILITIES_V3_OUT_EQUAL_STRIDE_PACKED_STREAM_LBN 2111857#define MC_CMD_GET_CAPABILITIES_V3_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 111858#define MC_CMD_GET_CAPABILITIES_V3_OUT_L3XUDP_SUPPORT_OFST 2011859#define MC_CMD_GET_CAPABILITIES_V3_OUT_L3XUDP_SUPPORT_LBN 2211860#define MC_CMD_GET_CAPABILITIES_V3_OUT_L3XUDP_SUPPORT_WIDTH 111861#define MC_CMD_GET_CAPABILITIES_V3_OUT_FW_SUBVARIANT_NO_TX_CSUM_OFST 2011862#define MC_CMD_GET_CAPABILITIES_V3_OUT_FW_SUBVARIANT_NO_TX_CSUM_LBN 2311863#define MC_CMD_GET_CAPABILITIES_V3_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 111864#define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_SPREADING_OFST 2011865#define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_SPREADING_LBN 2411866#define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_SPREADING_WIDTH 111867#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_HLB_IDLE_OFST 2011868#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_HLB_IDLE_LBN 2511869#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_HLB_IDLE_WIDTH 111870#define MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_RXQ_NO_CONT_EV_OFST 2011871#define MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_RXQ_NO_CONT_EV_LBN 2611872#define MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_RXQ_NO_CONT_EV_WIDTH 111873#define MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_RXQ_WITH_BUFFER_SIZE_OFST 2011874#define MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_RXQ_WITH_BUFFER_SIZE_LBN 2711875#define MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_RXQ_WITH_BUFFER_SIZE_WIDTH 111876#define MC_CMD_GET_CAPABILITIES_V3_OUT_BUNDLE_UPDATE_OFST 2011877#define MC_CMD_GET_CAPABILITIES_V3_OUT_BUNDLE_UPDATE_LBN 2811878#define MC_CMD_GET_CAPABILITIES_V3_OUT_BUNDLE_UPDATE_WIDTH 111879#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V3_OFST 2011880#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V3_LBN 2911881#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V3_WIDTH 111882#define MC_CMD_GET_CAPABILITIES_V3_OUT_DYNAMIC_SENSORS_OFST 2011883#define MC_CMD_GET_CAPABILITIES_V3_OUT_DYNAMIC_SENSORS_LBN 3011884#define MC_CMD_GET_CAPABILITIES_V3_OUT_DYNAMIC_SENSORS_WIDTH 111885#define MC_CMD_GET_CAPABILITIES_V3_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_OFST 2011886#define MC_CMD_GET_CAPABILITIES_V3_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_LBN 3111887#define MC_CMD_GET_CAPABILITIES_V3_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_WIDTH 111888/* Number of FATSOv2 contexts per datapath supported by this NIC (when11889 * TX_TSO_V2 == 1). Not present on older firmware (check the length).11890 */11891#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_N_CONTEXTS_OFST 2411892#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_N_CONTEXTS_LEN 211893/* One byte per PF containing the number of the external port assigned to this11894 * PF, indexed by PF number. Special values indicate that a PF is either not11895 * present or not assigned.11896 */11897#define MC_CMD_GET_CAPABILITIES_V3_OUT_PFS_TO_PORTS_ASSIGNMENT_OFST 2611898#define MC_CMD_GET_CAPABILITIES_V3_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 111899#define MC_CMD_GET_CAPABILITIES_V3_OUT_PFS_TO_PORTS_ASSIGNMENT_NUM 1611900/* enum: The caller is not permitted to access information on this PF. */11901#define MC_CMD_GET_CAPABILITIES_V3_OUT_ACCESS_NOT_PERMITTED 0xff11902/* enum: PF does not exist. */11903#define MC_CMD_GET_CAPABILITIES_V3_OUT_PF_NOT_PRESENT 0xfe11904/* enum: PF does exist but is not assigned to any external port. */11905#define MC_CMD_GET_CAPABILITIES_V3_OUT_PF_NOT_ASSIGNED 0xfd11906/* enum: This value indicates that PF is assigned, but it cannot be expressed11907 * in this field. It is intended for a possible future situation where a more11908 * complex scheme of PFs to ports mapping is being used. The future driver11909 * should look for a new field supporting the new scheme. The current/old11910 * driver should treat this value as PF_NOT_ASSIGNED.11911 */11912#define MC_CMD_GET_CAPABILITIES_V3_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc11913/* One byte per PF containing the number of its VFs, indexed by PF number. A11914 * special value indicates that a PF is not present.11915 */11916#define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VFS_PER_PF_OFST 4211917#define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VFS_PER_PF_LEN 111918#define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VFS_PER_PF_NUM 1611919/* enum: The caller is not permitted to access information on this PF. */11920/* MC_CMD_GET_CAPABILITIES_V3_OUT_ACCESS_NOT_PERMITTED 0xff */11921/* enum: PF does not exist. */11922/* MC_CMD_GET_CAPABILITIES_V3_OUT_PF_NOT_PRESENT 0xfe */11923/* Number of VIs available for each external port */11924#define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VIS_PER_PORT_OFST 5811925#define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VIS_PER_PORT_LEN 211926#define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VIS_PER_PORT_NUM 411927/* Size of RX descriptor cache expressed as binary logarithm The actual size11928 * equals (2 ^ RX_DESC_CACHE_SIZE)11929 */11930#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DESC_CACHE_SIZE_OFST 6611931#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DESC_CACHE_SIZE_LEN 111932/* Size of TX descriptor cache expressed as binary logarithm The actual size11933 * equals (2 ^ TX_DESC_CACHE_SIZE)11934 */11935#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_DESC_CACHE_SIZE_OFST 6711936#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_DESC_CACHE_SIZE_LEN 111937/* Total number of available PIO buffers */11938#define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_PIO_BUFFS_OFST 6811939#define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_PIO_BUFFS_LEN 211940/* Size of a single PIO buffer */11941#define MC_CMD_GET_CAPABILITIES_V3_OUT_SIZE_PIO_BUFF_OFST 7011942#define MC_CMD_GET_CAPABILITIES_V3_OUT_SIZE_PIO_BUFF_LEN 211943/* On chips later than Medford the amount of address space assigned to each VI11944 * is configurable. This is a global setting that the driver must query to11945 * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available11946 * with 8k VI windows.11947 */11948#define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_OFST 7211949#define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_LEN 111950/* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k.11951 * CTPIO is not mapped.11952 */11953#define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_8K 0x011954/* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */11955#define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_16K 0x111956/* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */11957#define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_64K 0x211958/* Number of vFIFOs per adapter that can be used for VFIFO Stuffing11959 * (SF-115995-SW) in the present configuration of firmware and port mode.11960 */11961#define MC_CMD_GET_CAPABILITIES_V3_OUT_VFIFO_STUFFING_NUM_VFIFOS_OFST 7311962#define MC_CMD_GET_CAPABILITIES_V3_OUT_VFIFO_STUFFING_NUM_VFIFOS_LEN 111963/* Number of buffers per adapter that can be used for VFIFO Stuffing11964 * (SF-115995-SW) in the present configuration of firmware and port mode.11965 */11966#define MC_CMD_GET_CAPABILITIES_V3_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_OFST 7411967#define MC_CMD_GET_CAPABILITIES_V3_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_LEN 211968 11969/* MC_CMD_GET_CAPABILITIES_V4_OUT msgresponse */11970#define MC_CMD_GET_CAPABILITIES_V4_OUT_LEN 7811971/* First word of flags. */11972#define MC_CMD_GET_CAPABILITIES_V4_OUT_FLAGS1_OFST 011973#define MC_CMD_GET_CAPABILITIES_V4_OUT_FLAGS1_LEN 411974#define MC_CMD_GET_CAPABILITIES_V4_OUT_VPORT_RECONFIGURE_OFST 011975#define MC_CMD_GET_CAPABILITIES_V4_OUT_VPORT_RECONFIGURE_LBN 311976#define MC_CMD_GET_CAPABILITIES_V4_OUT_VPORT_RECONFIGURE_WIDTH 111977#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_STRIPING_OFST 011978#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_STRIPING_LBN 411979#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_STRIPING_WIDTH 111980#define MC_CMD_GET_CAPABILITIES_V4_OUT_VADAPTOR_QUERY_OFST 011981#define MC_CMD_GET_CAPABILITIES_V4_OUT_VADAPTOR_QUERY_LBN 511982#define MC_CMD_GET_CAPABILITIES_V4_OUT_VADAPTOR_QUERY_WIDTH 111983#define MC_CMD_GET_CAPABILITIES_V4_OUT_EVB_PORT_VLAN_RESTRICT_OFST 011984#define MC_CMD_GET_CAPABILITIES_V4_OUT_EVB_PORT_VLAN_RESTRICT_LBN 611985#define MC_CMD_GET_CAPABILITIES_V4_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 111986#define MC_CMD_GET_CAPABILITIES_V4_OUT_DRV_ATTACH_PREBOOT_OFST 011987#define MC_CMD_GET_CAPABILITIES_V4_OUT_DRV_ATTACH_PREBOOT_LBN 711988#define MC_CMD_GET_CAPABILITIES_V4_OUT_DRV_ATTACH_PREBOOT_WIDTH 111989#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_FORCE_EVENT_MERGING_OFST 011990#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_FORCE_EVENT_MERGING_LBN 811991#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_FORCE_EVENT_MERGING_WIDTH 111992#define MC_CMD_GET_CAPABILITIES_V4_OUT_SET_MAC_ENHANCED_OFST 011993#define MC_CMD_GET_CAPABILITIES_V4_OUT_SET_MAC_ENHANCED_LBN 911994#define MC_CMD_GET_CAPABILITIES_V4_OUT_SET_MAC_ENHANCED_WIDTH 111995#define MC_CMD_GET_CAPABILITIES_V4_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 011996#define MC_CMD_GET_CAPABILITIES_V4_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 1011997#define MC_CMD_GET_CAPABILITIES_V4_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 111998#define MC_CMD_GET_CAPABILITIES_V4_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 011999#define MC_CMD_GET_CAPABILITIES_V4_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 1112000#define MC_CMD_GET_CAPABILITIES_V4_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 112001#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MAC_SECURITY_FILTERING_OFST 012002#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MAC_SECURITY_FILTERING_LBN 1212003#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 112004#define MC_CMD_GET_CAPABILITIES_V4_OUT_ADDITIONAL_RSS_MODES_OFST 012005#define MC_CMD_GET_CAPABILITIES_V4_OUT_ADDITIONAL_RSS_MODES_LBN 1312006#define MC_CMD_GET_CAPABILITIES_V4_OUT_ADDITIONAL_RSS_MODES_WIDTH 112007#define MC_CMD_GET_CAPABILITIES_V4_OUT_QBB_OFST 012008#define MC_CMD_GET_CAPABILITIES_V4_OUT_QBB_LBN 1412009#define MC_CMD_GET_CAPABILITIES_V4_OUT_QBB_WIDTH 112010#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 012011#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 1512012#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 112013#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_RSS_LIMITED_OFST 012014#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_RSS_LIMITED_LBN 1612015#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_RSS_LIMITED_WIDTH 112016#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PACKED_STREAM_OFST 012017#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PACKED_STREAM_LBN 1712018#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PACKED_STREAM_WIDTH 112019#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_INCLUDE_FCS_OFST 012020#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_INCLUDE_FCS_LBN 1812021#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_INCLUDE_FCS_WIDTH 112022#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_VLAN_INSERTION_OFST 012023#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_VLAN_INSERTION_LBN 1912024#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_VLAN_INSERTION_WIDTH 112025#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_VLAN_STRIPPING_OFST 012026#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_VLAN_STRIPPING_LBN 2012027#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_VLAN_STRIPPING_WIDTH 112028#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_OFST 012029#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_LBN 2112030#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_WIDTH 112031#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PREFIX_LEN_0_OFST 012032#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PREFIX_LEN_0_LBN 2212033#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PREFIX_LEN_0_WIDTH 112034#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PREFIX_LEN_14_OFST 012035#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PREFIX_LEN_14_LBN 2312036#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PREFIX_LEN_14_WIDTH 112037#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_TIMESTAMP_OFST 012038#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_TIMESTAMP_LBN 2412039#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_TIMESTAMP_WIDTH 112040#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_BATCHING_OFST 012041#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_BATCHING_LBN 2512042#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_BATCHING_WIDTH 112043#define MC_CMD_GET_CAPABILITIES_V4_OUT_MCAST_FILTER_CHAINING_OFST 012044#define MC_CMD_GET_CAPABILITIES_V4_OUT_MCAST_FILTER_CHAINING_LBN 2612045#define MC_CMD_GET_CAPABILITIES_V4_OUT_MCAST_FILTER_CHAINING_WIDTH 112046#define MC_CMD_GET_CAPABILITIES_V4_OUT_PM_AND_RXDP_COUNTERS_OFST 012047#define MC_CMD_GET_CAPABILITIES_V4_OUT_PM_AND_RXDP_COUNTERS_LBN 2712048#define MC_CMD_GET_CAPABILITIES_V4_OUT_PM_AND_RXDP_COUNTERS_WIDTH 112049#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_DISABLE_SCATTER_OFST 012050#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_DISABLE_SCATTER_LBN 2812051#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_DISABLE_SCATTER_WIDTH 112052#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MCAST_UDP_LOOPBACK_OFST 012053#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MCAST_UDP_LOOPBACK_LBN 2912054#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 112055#define MC_CMD_GET_CAPABILITIES_V4_OUT_EVB_OFST 012056#define MC_CMD_GET_CAPABILITIES_V4_OUT_EVB_LBN 3012057#define MC_CMD_GET_CAPABILITIES_V4_OUT_EVB_WIDTH 112058#define MC_CMD_GET_CAPABILITIES_V4_OUT_VXLAN_NVGRE_OFST 012059#define MC_CMD_GET_CAPABILITIES_V4_OUT_VXLAN_NVGRE_LBN 3112060#define MC_CMD_GET_CAPABILITIES_V4_OUT_VXLAN_NVGRE_WIDTH 112061/* RxDPCPU firmware id. */12062#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_DPCPU_FW_ID_OFST 412063#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_DPCPU_FW_ID_LEN 212064/* enum: Standard RXDP firmware */12065#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP 0x012066/* enum: Low latency RXDP firmware */12067#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_LOW_LATENCY 0x112068/* enum: Packed stream RXDP firmware */12069#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_PACKED_STREAM 0x212070/* enum: Rules engine RXDP firmware */12071#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_RULES_ENGINE 0x512072/* enum: DPDK RXDP firmware */12073#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_DPDK 0x612074/* enum: BIST RXDP firmware */12075#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_BIST 0x10a12076/* enum: RXDP Test firmware image 1 */12077#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x10112078/* enum: RXDP Test firmware image 2 */12079#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x10212080/* enum: RXDP Test firmware image 3 */12081#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x10312082/* enum: RXDP Test firmware image 4 */12083#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x10412084/* enum: RXDP Test firmware image 5 */12085#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_BACKPRESSURE 0x10512086/* enum: RXDP Test firmware image 6 */12087#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_PACKET_EDITS 0x10612088/* enum: RXDP Test firmware image 7 */12089#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x10712090/* enum: RXDP Test firmware image 8 */12091#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_DISABLE_DL 0x10812092/* enum: RXDP Test firmware image 9 */12093#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b12094/* enum: RXDP Test firmware image 10 */12095#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_SLOW 0x10c12096/* TxDPCPU firmware id. */12097#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_DPCPU_FW_ID_OFST 612098#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_DPCPU_FW_ID_LEN 212099/* enum: Standard TXDP firmware */12100#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP 0x012101/* enum: Low latency TXDP firmware */12102#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_LOW_LATENCY 0x112103/* enum: High packet rate TXDP firmware */12104#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_HIGH_PACKET_RATE 0x312105/* enum: Rules engine TXDP firmware */12106#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_RULES_ENGINE 0x512107/* enum: DPDK TXDP firmware */12108#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_DPDK 0x612109/* enum: BIST TXDP firmware */12110#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_BIST 0x12d12111/* enum: TXDP Test firmware image 1 */12112#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_TEST_FW_TSO_EDIT 0x10112113/* enum: TXDP Test firmware image 2 */12114#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_TEST_FW_PACKET_EDITS 0x10212115/* enum: TXDP CSR bus test firmware */12116#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_TEST_FW_CSR 0x10312117#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_OFST 812118#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_LEN 212119#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_REV_OFST 812120#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_REV_LBN 012121#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_REV_WIDTH 1212122#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_TYPE_OFST 812123#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_TYPE_LBN 1212124#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_TYPE_WIDTH 412125/* enum: reserved value - do not use (may indicate alternative interpretation12126 * of REV field in future)12127 */12128#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_RESERVED 0x012129/* enum: Trivial RX PD firmware for early Huntington development (Huntington12130 * development only)12131 */12132#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_FIRST_PKT 0x112133/* enum: RX PD firmware for telemetry prototyping (Medford2 development only)12134 */12135#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x112136/* enum: RX PD firmware with approximately Siena-compatible behaviour12137 * (Huntington development only)12138 */12139#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x212140/* enum: Full featured RX PD production firmware */12141#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x312142/* enum: (deprecated original name for the FULL_FEATURED variant) */12143#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_VSWITCH 0x312144/* enum: siena_compat variant RX PD firmware using PM rather than MAC12145 * (Huntington development only)12146 */12147#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x412148/* enum: Low latency RX PD production firmware */12149#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x512150/* enum: Packed stream RX PD production firmware */12151#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x612152/* enum: RX PD firmware handling layer 2 only for high packet rate performance12153 * tests (Medford development only)12154 */12155#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x712156/* enum: Rules engine RX PD production firmware */12157#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x812158/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */12159#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_L3XUDP 0x912160/* enum: DPDK RX PD production firmware */12161#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_DPDK 0xa12162/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */12163#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe12164/* enum: RX PD firmware parsing but not filtering network overlay tunnel12165 * encapsulations (Medford development only)12166 */12167#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf12168#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_OFST 1012169#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_LEN 212170#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_REV_OFST 1012171#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_REV_LBN 012172#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_REV_WIDTH 1212173#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_TYPE_OFST 1012174#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_TYPE_LBN 1212175#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_TYPE_WIDTH 412176/* enum: reserved value - do not use (may indicate alternative interpretation12177 * of REV field in future)12178 */12179#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_RESERVED 0x012180/* enum: Trivial TX PD firmware for early Huntington development (Huntington12181 * development only)12182 */12183#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_FIRST_PKT 0x112184/* enum: TX PD firmware for telemetry prototyping (Medford2 development only)12185 */12186#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x112187/* enum: TX PD firmware with approximately Siena-compatible behaviour12188 * (Huntington development only)12189 */12190#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x212191/* enum: Full featured TX PD production firmware */12192#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x312193/* enum: (deprecated original name for the FULL_FEATURED variant) */12194#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_VSWITCH 0x312195/* enum: siena_compat variant TX PD firmware using PM rather than MAC12196 * (Huntington development only)12197 */12198#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x412199#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */12200/* enum: TX PD firmware handling layer 2 only for high packet rate performance12201 * tests (Medford development only)12202 */12203#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x712204/* enum: Rules engine TX PD production firmware */12205#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x812206/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */12207#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_L3XUDP 0x912208/* enum: DPDK TX PD production firmware */12209#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_DPDK 0xa12210/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */12211#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe12212/* Hardware capabilities of NIC */12213#define MC_CMD_GET_CAPABILITIES_V4_OUT_HW_CAPABILITIES_OFST 1212214#define MC_CMD_GET_CAPABILITIES_V4_OUT_HW_CAPABILITIES_LEN 412215/* Licensed capabilities */12216#define MC_CMD_GET_CAPABILITIES_V4_OUT_LICENSE_CAPABILITIES_OFST 1612217#define MC_CMD_GET_CAPABILITIES_V4_OUT_LICENSE_CAPABILITIES_LEN 412218/* Second word of flags. Not present on older firmware (check the length). */12219#define MC_CMD_GET_CAPABILITIES_V4_OUT_FLAGS2_OFST 2012220#define MC_CMD_GET_CAPABILITIES_V4_OUT_FLAGS2_LEN 412221#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_OFST 2012222#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_LBN 012223#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_WIDTH 112224#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_ENCAP_OFST 2012225#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_ENCAP_LBN 112226#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_ENCAP_WIDTH 112227#define MC_CMD_GET_CAPABILITIES_V4_OUT_EVQ_TIMER_CTRL_OFST 2012228#define MC_CMD_GET_CAPABILITIES_V4_OUT_EVQ_TIMER_CTRL_LBN 212229#define MC_CMD_GET_CAPABILITIES_V4_OUT_EVQ_TIMER_CTRL_WIDTH 112230#define MC_CMD_GET_CAPABILITIES_V4_OUT_EVENT_CUT_THROUGH_OFST 2012231#define MC_CMD_GET_CAPABILITIES_V4_OUT_EVENT_CUT_THROUGH_LBN 312232#define MC_CMD_GET_CAPABILITIES_V4_OUT_EVENT_CUT_THROUGH_WIDTH 112233#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_CUT_THROUGH_OFST 2012234#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_CUT_THROUGH_LBN 412235#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_CUT_THROUGH_WIDTH 112236#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_VFIFO_ULL_MODE_OFST 2012237#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_VFIFO_ULL_MODE_LBN 512238#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_VFIFO_ULL_MODE_WIDTH 112239#define MC_CMD_GET_CAPABILITIES_V4_OUT_MAC_STATS_40G_TX_SIZE_BINS_OFST 2012240#define MC_CMD_GET_CAPABILITIES_V4_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 612241#define MC_CMD_GET_CAPABILITIES_V4_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 112242#define MC_CMD_GET_CAPABILITIES_V4_OUT_INIT_EVQ_TYPE_SUPPORTED_OFST 2012243#define MC_CMD_GET_CAPABILITIES_V4_OUT_INIT_EVQ_TYPE_SUPPORTED_LBN 712244#define MC_CMD_GET_CAPABILITIES_V4_OUT_INIT_EVQ_TYPE_SUPPORTED_WIDTH 112245#define MC_CMD_GET_CAPABILITIES_V4_OUT_INIT_EVQ_V2_OFST 2012246#define MC_CMD_GET_CAPABILITIES_V4_OUT_INIT_EVQ_V2_LBN 712247#define MC_CMD_GET_CAPABILITIES_V4_OUT_INIT_EVQ_V2_WIDTH 112248#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MAC_TIMESTAMPING_OFST 2012249#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MAC_TIMESTAMPING_LBN 812250#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MAC_TIMESTAMPING_WIDTH 112251#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TIMESTAMP_OFST 2012252#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TIMESTAMP_LBN 912253#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TIMESTAMP_WIDTH 112254#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_SNIFF_OFST 2012255#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_SNIFF_LBN 1012256#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_SNIFF_WIDTH 112257#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_SNIFF_OFST 2012258#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_SNIFF_LBN 1112259#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_SNIFF_WIDTH 112260#define MC_CMD_GET_CAPABILITIES_V4_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_OFST 2012261#define MC_CMD_GET_CAPABILITIES_V4_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_LBN 1212262#define MC_CMD_GET_CAPABILITIES_V4_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 112263#define MC_CMD_GET_CAPABILITIES_V4_OUT_MCDI_BACKGROUND_OFST 2012264#define MC_CMD_GET_CAPABILITIES_V4_OUT_MCDI_BACKGROUND_LBN 1312265#define MC_CMD_GET_CAPABILITIES_V4_OUT_MCDI_BACKGROUND_WIDTH 112266#define MC_CMD_GET_CAPABILITIES_V4_OUT_MCDI_DB_RETURN_OFST 2012267#define MC_CMD_GET_CAPABILITIES_V4_OUT_MCDI_DB_RETURN_LBN 1412268#define MC_CMD_GET_CAPABILITIES_V4_OUT_MCDI_DB_RETURN_WIDTH 112269#define MC_CMD_GET_CAPABILITIES_V4_OUT_CTPIO_OFST 2012270#define MC_CMD_GET_CAPABILITIES_V4_OUT_CTPIO_LBN 1512271#define MC_CMD_GET_CAPABILITIES_V4_OUT_CTPIO_WIDTH 112272#define MC_CMD_GET_CAPABILITIES_V4_OUT_TSA_SUPPORT_OFST 2012273#define MC_CMD_GET_CAPABILITIES_V4_OUT_TSA_SUPPORT_LBN 1612274#define MC_CMD_GET_CAPABILITIES_V4_OUT_TSA_SUPPORT_WIDTH 112275#define MC_CMD_GET_CAPABILITIES_V4_OUT_TSA_BOUND_OFST 2012276#define MC_CMD_GET_CAPABILITIES_V4_OUT_TSA_BOUND_LBN 1712277#define MC_CMD_GET_CAPABILITIES_V4_OUT_TSA_BOUND_WIDTH 112278#define MC_CMD_GET_CAPABILITIES_V4_OUT_SF_ADAPTER_AUTHENTICATION_OFST 2012279#define MC_CMD_GET_CAPABILITIES_V4_OUT_SF_ADAPTER_AUTHENTICATION_LBN 1812280#define MC_CMD_GET_CAPABILITIES_V4_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 112281#define MC_CMD_GET_CAPABILITIES_V4_OUT_FILTER_ACTION_FLAG_OFST 2012282#define MC_CMD_GET_CAPABILITIES_V4_OUT_FILTER_ACTION_FLAG_LBN 1912283#define MC_CMD_GET_CAPABILITIES_V4_OUT_FILTER_ACTION_FLAG_WIDTH 112284#define MC_CMD_GET_CAPABILITIES_V4_OUT_FILTER_ACTION_MARK_OFST 2012285#define MC_CMD_GET_CAPABILITIES_V4_OUT_FILTER_ACTION_MARK_LBN 2012286#define MC_CMD_GET_CAPABILITIES_V4_OUT_FILTER_ACTION_MARK_WIDTH 112287#define MC_CMD_GET_CAPABILITIES_V4_OUT_EQUAL_STRIDE_SUPER_BUFFER_OFST 2012288#define MC_CMD_GET_CAPABILITIES_V4_OUT_EQUAL_STRIDE_SUPER_BUFFER_LBN 2112289#define MC_CMD_GET_CAPABILITIES_V4_OUT_EQUAL_STRIDE_SUPER_BUFFER_WIDTH 112290#define MC_CMD_GET_CAPABILITIES_V4_OUT_EQUAL_STRIDE_PACKED_STREAM_OFST 2012291#define MC_CMD_GET_CAPABILITIES_V4_OUT_EQUAL_STRIDE_PACKED_STREAM_LBN 2112292#define MC_CMD_GET_CAPABILITIES_V4_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 112293#define MC_CMD_GET_CAPABILITIES_V4_OUT_L3XUDP_SUPPORT_OFST 2012294#define MC_CMD_GET_CAPABILITIES_V4_OUT_L3XUDP_SUPPORT_LBN 2212295#define MC_CMD_GET_CAPABILITIES_V4_OUT_L3XUDP_SUPPORT_WIDTH 112296#define MC_CMD_GET_CAPABILITIES_V4_OUT_FW_SUBVARIANT_NO_TX_CSUM_OFST 2012297#define MC_CMD_GET_CAPABILITIES_V4_OUT_FW_SUBVARIANT_NO_TX_CSUM_LBN 2312298#define MC_CMD_GET_CAPABILITIES_V4_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 112299#define MC_CMD_GET_CAPABILITIES_V4_OUT_VI_SPREADING_OFST 2012300#define MC_CMD_GET_CAPABILITIES_V4_OUT_VI_SPREADING_LBN 2412301#define MC_CMD_GET_CAPABILITIES_V4_OUT_VI_SPREADING_WIDTH 112302#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_HLB_IDLE_OFST 2012303#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_HLB_IDLE_LBN 2512304#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_HLB_IDLE_WIDTH 112305#define MC_CMD_GET_CAPABILITIES_V4_OUT_INIT_RXQ_NO_CONT_EV_OFST 2012306#define MC_CMD_GET_CAPABILITIES_V4_OUT_INIT_RXQ_NO_CONT_EV_LBN 2612307#define MC_CMD_GET_CAPABILITIES_V4_OUT_INIT_RXQ_NO_CONT_EV_WIDTH 112308#define MC_CMD_GET_CAPABILITIES_V4_OUT_INIT_RXQ_WITH_BUFFER_SIZE_OFST 2012309#define MC_CMD_GET_CAPABILITIES_V4_OUT_INIT_RXQ_WITH_BUFFER_SIZE_LBN 2712310#define MC_CMD_GET_CAPABILITIES_V4_OUT_INIT_RXQ_WITH_BUFFER_SIZE_WIDTH 112311#define MC_CMD_GET_CAPABILITIES_V4_OUT_BUNDLE_UPDATE_OFST 2012312#define MC_CMD_GET_CAPABILITIES_V4_OUT_BUNDLE_UPDATE_LBN 2812313#define MC_CMD_GET_CAPABILITIES_V4_OUT_BUNDLE_UPDATE_WIDTH 112314#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V3_OFST 2012315#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V3_LBN 2912316#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V3_WIDTH 112317#define MC_CMD_GET_CAPABILITIES_V4_OUT_DYNAMIC_SENSORS_OFST 2012318#define MC_CMD_GET_CAPABILITIES_V4_OUT_DYNAMIC_SENSORS_LBN 3012319#define MC_CMD_GET_CAPABILITIES_V4_OUT_DYNAMIC_SENSORS_WIDTH 112320#define MC_CMD_GET_CAPABILITIES_V4_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_OFST 2012321#define MC_CMD_GET_CAPABILITIES_V4_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_LBN 3112322#define MC_CMD_GET_CAPABILITIES_V4_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_WIDTH 112323/* Number of FATSOv2 contexts per datapath supported by this NIC (when12324 * TX_TSO_V2 == 1). Not present on older firmware (check the length).12325 */12326#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_N_CONTEXTS_OFST 2412327#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_N_CONTEXTS_LEN 212328/* One byte per PF containing the number of the external port assigned to this12329 * PF, indexed by PF number. Special values indicate that a PF is either not12330 * present or not assigned.12331 */12332#define MC_CMD_GET_CAPABILITIES_V4_OUT_PFS_TO_PORTS_ASSIGNMENT_OFST 2612333#define MC_CMD_GET_CAPABILITIES_V4_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 112334#define MC_CMD_GET_CAPABILITIES_V4_OUT_PFS_TO_PORTS_ASSIGNMENT_NUM 1612335/* enum: The caller is not permitted to access information on this PF. */12336#define MC_CMD_GET_CAPABILITIES_V4_OUT_ACCESS_NOT_PERMITTED 0xff12337/* enum: PF does not exist. */12338#define MC_CMD_GET_CAPABILITIES_V4_OUT_PF_NOT_PRESENT 0xfe12339/* enum: PF does exist but is not assigned to any external port. */12340#define MC_CMD_GET_CAPABILITIES_V4_OUT_PF_NOT_ASSIGNED 0xfd12341/* enum: This value indicates that PF is assigned, but it cannot be expressed12342 * in this field. It is intended for a possible future situation where a more12343 * complex scheme of PFs to ports mapping is being used. The future driver12344 * should look for a new field supporting the new scheme. The current/old12345 * driver should treat this value as PF_NOT_ASSIGNED.12346 */12347#define MC_CMD_GET_CAPABILITIES_V4_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc12348/* One byte per PF containing the number of its VFs, indexed by PF number. A12349 * special value indicates that a PF is not present.12350 */12351#define MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_VFS_PER_PF_OFST 4212352#define MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_VFS_PER_PF_LEN 112353#define MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_VFS_PER_PF_NUM 1612354/* enum: The caller is not permitted to access information on this PF. */12355/* MC_CMD_GET_CAPABILITIES_V4_OUT_ACCESS_NOT_PERMITTED 0xff */12356/* enum: PF does not exist. */12357/* MC_CMD_GET_CAPABILITIES_V4_OUT_PF_NOT_PRESENT 0xfe */12358/* Number of VIs available for each external port */12359#define MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_VIS_PER_PORT_OFST 5812360#define MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_VIS_PER_PORT_LEN 212361#define MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_VIS_PER_PORT_NUM 412362/* Size of RX descriptor cache expressed as binary logarithm The actual size12363 * equals (2 ^ RX_DESC_CACHE_SIZE)12364 */12365#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_DESC_CACHE_SIZE_OFST 6612366#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_DESC_CACHE_SIZE_LEN 112367/* Size of TX descriptor cache expressed as binary logarithm The actual size12368 * equals (2 ^ TX_DESC_CACHE_SIZE)12369 */12370#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_DESC_CACHE_SIZE_OFST 6712371#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_DESC_CACHE_SIZE_LEN 112372/* Total number of available PIO buffers */12373#define MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_PIO_BUFFS_OFST 6812374#define MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_PIO_BUFFS_LEN 212375/* Size of a single PIO buffer */12376#define MC_CMD_GET_CAPABILITIES_V4_OUT_SIZE_PIO_BUFF_OFST 7012377#define MC_CMD_GET_CAPABILITIES_V4_OUT_SIZE_PIO_BUFF_LEN 212378/* On chips later than Medford the amount of address space assigned to each VI12379 * is configurable. This is a global setting that the driver must query to12380 * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available12381 * with 8k VI windows.12382 */12383#define MC_CMD_GET_CAPABILITIES_V4_OUT_VI_WINDOW_MODE_OFST 7212384#define MC_CMD_GET_CAPABILITIES_V4_OUT_VI_WINDOW_MODE_LEN 112385/* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k.12386 * CTPIO is not mapped.12387 */12388#define MC_CMD_GET_CAPABILITIES_V4_OUT_VI_WINDOW_MODE_8K 0x012389/* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */12390#define MC_CMD_GET_CAPABILITIES_V4_OUT_VI_WINDOW_MODE_16K 0x112391/* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */12392#define MC_CMD_GET_CAPABILITIES_V4_OUT_VI_WINDOW_MODE_64K 0x212393/* Number of vFIFOs per adapter that can be used for VFIFO Stuffing12394 * (SF-115995-SW) in the present configuration of firmware and port mode.12395 */12396#define MC_CMD_GET_CAPABILITIES_V4_OUT_VFIFO_STUFFING_NUM_VFIFOS_OFST 7312397#define MC_CMD_GET_CAPABILITIES_V4_OUT_VFIFO_STUFFING_NUM_VFIFOS_LEN 112398/* Number of buffers per adapter that can be used for VFIFO Stuffing12399 * (SF-115995-SW) in the present configuration of firmware and port mode.12400 */12401#define MC_CMD_GET_CAPABILITIES_V4_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_OFST 7412402#define MC_CMD_GET_CAPABILITIES_V4_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_LEN 212403/* Entry count in the MAC stats array, including the final GENERATION_END12404 * entry. For MAC stats DMA, drivers should allocate a buffer large enough to12405 * hold at least this many 64-bit stats values, if they wish to receive all12406 * available stats. If the buffer is shorter than MAC_STATS_NUM_STATS * 8, the12407 * stats array returned will be truncated.12408 */12409#define MC_CMD_GET_CAPABILITIES_V4_OUT_MAC_STATS_NUM_STATS_OFST 7612410#define MC_CMD_GET_CAPABILITIES_V4_OUT_MAC_STATS_NUM_STATS_LEN 212411 12412/* MC_CMD_GET_CAPABILITIES_V5_OUT msgresponse */12413#define MC_CMD_GET_CAPABILITIES_V5_OUT_LEN 8412414/* First word of flags. */12415#define MC_CMD_GET_CAPABILITIES_V5_OUT_FLAGS1_OFST 012416#define MC_CMD_GET_CAPABILITIES_V5_OUT_FLAGS1_LEN 412417#define MC_CMD_GET_CAPABILITIES_V5_OUT_VPORT_RECONFIGURE_OFST 012418#define MC_CMD_GET_CAPABILITIES_V5_OUT_VPORT_RECONFIGURE_LBN 312419#define MC_CMD_GET_CAPABILITIES_V5_OUT_VPORT_RECONFIGURE_WIDTH 112420#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_STRIPING_OFST 012421#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_STRIPING_LBN 412422#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_STRIPING_WIDTH 112423#define MC_CMD_GET_CAPABILITIES_V5_OUT_VADAPTOR_QUERY_OFST 012424#define MC_CMD_GET_CAPABILITIES_V5_OUT_VADAPTOR_QUERY_LBN 512425#define MC_CMD_GET_CAPABILITIES_V5_OUT_VADAPTOR_QUERY_WIDTH 112426#define MC_CMD_GET_CAPABILITIES_V5_OUT_EVB_PORT_VLAN_RESTRICT_OFST 012427#define MC_CMD_GET_CAPABILITIES_V5_OUT_EVB_PORT_VLAN_RESTRICT_LBN 612428#define MC_CMD_GET_CAPABILITIES_V5_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 112429#define MC_CMD_GET_CAPABILITIES_V5_OUT_DRV_ATTACH_PREBOOT_OFST 012430#define MC_CMD_GET_CAPABILITIES_V5_OUT_DRV_ATTACH_PREBOOT_LBN 712431#define MC_CMD_GET_CAPABILITIES_V5_OUT_DRV_ATTACH_PREBOOT_WIDTH 112432#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_FORCE_EVENT_MERGING_OFST 012433#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_FORCE_EVENT_MERGING_LBN 812434#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_FORCE_EVENT_MERGING_WIDTH 112435#define MC_CMD_GET_CAPABILITIES_V5_OUT_SET_MAC_ENHANCED_OFST 012436#define MC_CMD_GET_CAPABILITIES_V5_OUT_SET_MAC_ENHANCED_LBN 912437#define MC_CMD_GET_CAPABILITIES_V5_OUT_SET_MAC_ENHANCED_WIDTH 112438#define MC_CMD_GET_CAPABILITIES_V5_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 012439#define MC_CMD_GET_CAPABILITIES_V5_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 1012440#define MC_CMD_GET_CAPABILITIES_V5_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 112441#define MC_CMD_GET_CAPABILITIES_V5_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 012442#define MC_CMD_GET_CAPABILITIES_V5_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 1112443#define MC_CMD_GET_CAPABILITIES_V5_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 112444#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_MAC_SECURITY_FILTERING_OFST 012445#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_MAC_SECURITY_FILTERING_LBN 1212446#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 112447#define MC_CMD_GET_CAPABILITIES_V5_OUT_ADDITIONAL_RSS_MODES_OFST 012448#define MC_CMD_GET_CAPABILITIES_V5_OUT_ADDITIONAL_RSS_MODES_LBN 1312449#define MC_CMD_GET_CAPABILITIES_V5_OUT_ADDITIONAL_RSS_MODES_WIDTH 112450#define MC_CMD_GET_CAPABILITIES_V5_OUT_QBB_OFST 012451#define MC_CMD_GET_CAPABILITIES_V5_OUT_QBB_LBN 1412452#define MC_CMD_GET_CAPABILITIES_V5_OUT_QBB_WIDTH 112453#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 012454#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 1512455#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 112456#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_RSS_LIMITED_OFST 012457#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_RSS_LIMITED_LBN 1612458#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_RSS_LIMITED_WIDTH 112459#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PACKED_STREAM_OFST 012460#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PACKED_STREAM_LBN 1712461#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PACKED_STREAM_WIDTH 112462#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_INCLUDE_FCS_OFST 012463#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_INCLUDE_FCS_LBN 1812464#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_INCLUDE_FCS_WIDTH 112465#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_VLAN_INSERTION_OFST 012466#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_VLAN_INSERTION_LBN 1912467#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_VLAN_INSERTION_WIDTH 112468#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_VLAN_STRIPPING_OFST 012469#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_VLAN_STRIPPING_LBN 2012470#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_VLAN_STRIPPING_WIDTH 112471#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_OFST 012472#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_LBN 2112473#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_WIDTH 112474#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PREFIX_LEN_0_OFST 012475#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PREFIX_LEN_0_LBN 2212476#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PREFIX_LEN_0_WIDTH 112477#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PREFIX_LEN_14_OFST 012478#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PREFIX_LEN_14_LBN 2312479#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PREFIX_LEN_14_WIDTH 112480#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_TIMESTAMP_OFST 012481#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_TIMESTAMP_LBN 2412482#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_TIMESTAMP_WIDTH 112483#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_BATCHING_OFST 012484#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_BATCHING_LBN 2512485#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_BATCHING_WIDTH 112486#define MC_CMD_GET_CAPABILITIES_V5_OUT_MCAST_FILTER_CHAINING_OFST 012487#define MC_CMD_GET_CAPABILITIES_V5_OUT_MCAST_FILTER_CHAINING_LBN 2612488#define MC_CMD_GET_CAPABILITIES_V5_OUT_MCAST_FILTER_CHAINING_WIDTH 112489#define MC_CMD_GET_CAPABILITIES_V5_OUT_PM_AND_RXDP_COUNTERS_OFST 012490#define MC_CMD_GET_CAPABILITIES_V5_OUT_PM_AND_RXDP_COUNTERS_LBN 2712491#define MC_CMD_GET_CAPABILITIES_V5_OUT_PM_AND_RXDP_COUNTERS_WIDTH 112492#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_DISABLE_SCATTER_OFST 012493#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_DISABLE_SCATTER_LBN 2812494#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_DISABLE_SCATTER_WIDTH 112495#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_MCAST_UDP_LOOPBACK_OFST 012496#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_MCAST_UDP_LOOPBACK_LBN 2912497#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 112498#define MC_CMD_GET_CAPABILITIES_V5_OUT_EVB_OFST 012499#define MC_CMD_GET_CAPABILITIES_V5_OUT_EVB_LBN 3012500#define MC_CMD_GET_CAPABILITIES_V5_OUT_EVB_WIDTH 112501#define MC_CMD_GET_CAPABILITIES_V5_OUT_VXLAN_NVGRE_OFST 012502#define MC_CMD_GET_CAPABILITIES_V5_OUT_VXLAN_NVGRE_LBN 3112503#define MC_CMD_GET_CAPABILITIES_V5_OUT_VXLAN_NVGRE_WIDTH 112504/* RxDPCPU firmware id. */12505#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_DPCPU_FW_ID_OFST 412506#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_DPCPU_FW_ID_LEN 212507/* enum: Standard RXDP firmware */12508#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP 0x012509/* enum: Low latency RXDP firmware */12510#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_LOW_LATENCY 0x112511/* enum: Packed stream RXDP firmware */12512#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_PACKED_STREAM 0x212513/* enum: Rules engine RXDP firmware */12514#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_RULES_ENGINE 0x512515/* enum: DPDK RXDP firmware */12516#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_DPDK 0x612517/* enum: BIST RXDP firmware */12518#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_BIST 0x10a12519/* enum: RXDP Test firmware image 1 */12520#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x10112521/* enum: RXDP Test firmware image 2 */12522#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x10212523/* enum: RXDP Test firmware image 3 */12524#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x10312525/* enum: RXDP Test firmware image 4 */12526#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x10412527/* enum: RXDP Test firmware image 5 */12528#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_BACKPRESSURE 0x10512529/* enum: RXDP Test firmware image 6 */12530#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_PACKET_EDITS 0x10612531/* enum: RXDP Test firmware image 7 */12532#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x10712533/* enum: RXDP Test firmware image 8 */12534#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_DISABLE_DL 0x10812535/* enum: RXDP Test firmware image 9 */12536#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b12537/* enum: RXDP Test firmware image 10 */12538#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_SLOW 0x10c12539/* TxDPCPU firmware id. */12540#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_DPCPU_FW_ID_OFST 612541#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_DPCPU_FW_ID_LEN 212542/* enum: Standard TXDP firmware */12543#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP 0x012544/* enum: Low latency TXDP firmware */12545#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_LOW_LATENCY 0x112546/* enum: High packet rate TXDP firmware */12547#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_HIGH_PACKET_RATE 0x312548/* enum: Rules engine TXDP firmware */12549#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_RULES_ENGINE 0x512550/* enum: DPDK TXDP firmware */12551#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_DPDK 0x612552/* enum: BIST TXDP firmware */12553#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_BIST 0x12d12554/* enum: TXDP Test firmware image 1 */12555#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_TEST_FW_TSO_EDIT 0x10112556/* enum: TXDP Test firmware image 2 */12557#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_TEST_FW_PACKET_EDITS 0x10212558/* enum: TXDP CSR bus test firmware */12559#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_TEST_FW_CSR 0x10312560#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_VERSION_OFST 812561#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_VERSION_LEN 212562#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_VERSION_REV_OFST 812563#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_VERSION_REV_LBN 012564#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_VERSION_REV_WIDTH 1212565#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_VERSION_TYPE_OFST 812566#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_VERSION_TYPE_LBN 1212567#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_VERSION_TYPE_WIDTH 412568/* enum: reserved value - do not use (may indicate alternative interpretation12569 * of REV field in future)12570 */12571#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_RESERVED 0x012572/* enum: Trivial RX PD firmware for early Huntington development (Huntington12573 * development only)12574 */12575#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_FIRST_PKT 0x112576/* enum: RX PD firmware for telemetry prototyping (Medford2 development only)12577 */12578#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x112579/* enum: RX PD firmware with approximately Siena-compatible behaviour12580 * (Huntington development only)12581 */12582#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x212583/* enum: Full featured RX PD production firmware */12584#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x312585/* enum: (deprecated original name for the FULL_FEATURED variant) */12586#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_VSWITCH 0x312587/* enum: siena_compat variant RX PD firmware using PM rather than MAC12588 * (Huntington development only)12589 */12590#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x412591/* enum: Low latency RX PD production firmware */12592#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x512593/* enum: Packed stream RX PD production firmware */12594#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x612595/* enum: RX PD firmware handling layer 2 only for high packet rate performance12596 * tests (Medford development only)12597 */12598#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x712599/* enum: Rules engine RX PD production firmware */12600#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x812601/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */12602#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_L3XUDP 0x912603/* enum: DPDK RX PD production firmware */12604#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_DPDK 0xa12605/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */12606#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe12607/* enum: RX PD firmware parsing but not filtering network overlay tunnel12608 * encapsulations (Medford development only)12609 */12610#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf12611#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_VERSION_OFST 1012612#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_VERSION_LEN 212613#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_VERSION_REV_OFST 1012614#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_VERSION_REV_LBN 012615#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_VERSION_REV_WIDTH 1212616#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_VERSION_TYPE_OFST 1012617#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_VERSION_TYPE_LBN 1212618#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_VERSION_TYPE_WIDTH 412619/* enum: reserved value - do not use (may indicate alternative interpretation12620 * of REV field in future)12621 */12622#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_RESERVED 0x012623/* enum: Trivial TX PD firmware for early Huntington development (Huntington12624 * development only)12625 */12626#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_FIRST_PKT 0x112627/* enum: TX PD firmware for telemetry prototyping (Medford2 development only)12628 */12629#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x112630/* enum: TX PD firmware with approximately Siena-compatible behaviour12631 * (Huntington development only)12632 */12633#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x212634/* enum: Full featured TX PD production firmware */12635#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x312636/* enum: (deprecated original name for the FULL_FEATURED variant) */12637#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_VSWITCH 0x312638/* enum: siena_compat variant TX PD firmware using PM rather than MAC12639 * (Huntington development only)12640 */12641#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x412642#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */12643/* enum: TX PD firmware handling layer 2 only for high packet rate performance12644 * tests (Medford development only)12645 */12646#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x712647/* enum: Rules engine TX PD production firmware */12648#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x812649/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */12650#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_L3XUDP 0x912651/* enum: DPDK TX PD production firmware */12652#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_DPDK 0xa12653/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */12654#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe12655/* Hardware capabilities of NIC */12656#define MC_CMD_GET_CAPABILITIES_V5_OUT_HW_CAPABILITIES_OFST 1212657#define MC_CMD_GET_CAPABILITIES_V5_OUT_HW_CAPABILITIES_LEN 412658/* Licensed capabilities */12659#define MC_CMD_GET_CAPABILITIES_V5_OUT_LICENSE_CAPABILITIES_OFST 1612660#define MC_CMD_GET_CAPABILITIES_V5_OUT_LICENSE_CAPABILITIES_LEN 412661/* Second word of flags. Not present on older firmware (check the length). */12662#define MC_CMD_GET_CAPABILITIES_V5_OUT_FLAGS2_OFST 2012663#define MC_CMD_GET_CAPABILITIES_V5_OUT_FLAGS2_LEN 412664#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V2_OFST 2012665#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V2_LBN 012666#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V2_WIDTH 112667#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V2_ENCAP_OFST 2012668#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V2_ENCAP_LBN 112669#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V2_ENCAP_WIDTH 112670#define MC_CMD_GET_CAPABILITIES_V5_OUT_EVQ_TIMER_CTRL_OFST 2012671#define MC_CMD_GET_CAPABILITIES_V5_OUT_EVQ_TIMER_CTRL_LBN 212672#define MC_CMD_GET_CAPABILITIES_V5_OUT_EVQ_TIMER_CTRL_WIDTH 112673#define MC_CMD_GET_CAPABILITIES_V5_OUT_EVENT_CUT_THROUGH_OFST 2012674#define MC_CMD_GET_CAPABILITIES_V5_OUT_EVENT_CUT_THROUGH_LBN 312675#define MC_CMD_GET_CAPABILITIES_V5_OUT_EVENT_CUT_THROUGH_WIDTH 112676#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_CUT_THROUGH_OFST 2012677#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_CUT_THROUGH_LBN 412678#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_CUT_THROUGH_WIDTH 112679#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_VFIFO_ULL_MODE_OFST 2012680#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_VFIFO_ULL_MODE_LBN 512681#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_VFIFO_ULL_MODE_WIDTH 112682#define MC_CMD_GET_CAPABILITIES_V5_OUT_MAC_STATS_40G_TX_SIZE_BINS_OFST 2012683#define MC_CMD_GET_CAPABILITIES_V5_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 612684#define MC_CMD_GET_CAPABILITIES_V5_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 112685#define MC_CMD_GET_CAPABILITIES_V5_OUT_INIT_EVQ_TYPE_SUPPORTED_OFST 2012686#define MC_CMD_GET_CAPABILITIES_V5_OUT_INIT_EVQ_TYPE_SUPPORTED_LBN 712687#define MC_CMD_GET_CAPABILITIES_V5_OUT_INIT_EVQ_TYPE_SUPPORTED_WIDTH 112688#define MC_CMD_GET_CAPABILITIES_V5_OUT_INIT_EVQ_V2_OFST 2012689#define MC_CMD_GET_CAPABILITIES_V5_OUT_INIT_EVQ_V2_LBN 712690#define MC_CMD_GET_CAPABILITIES_V5_OUT_INIT_EVQ_V2_WIDTH 112691#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_MAC_TIMESTAMPING_OFST 2012692#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_MAC_TIMESTAMPING_LBN 812693#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_MAC_TIMESTAMPING_WIDTH 112694#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TIMESTAMP_OFST 2012695#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TIMESTAMP_LBN 912696#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TIMESTAMP_WIDTH 112697#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_SNIFF_OFST 2012698#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_SNIFF_LBN 1012699#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_SNIFF_WIDTH 112700#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_SNIFF_OFST 2012701#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_SNIFF_LBN 1112702#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_SNIFF_WIDTH 112703#define MC_CMD_GET_CAPABILITIES_V5_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_OFST 2012704#define MC_CMD_GET_CAPABILITIES_V5_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_LBN 1212705#define MC_CMD_GET_CAPABILITIES_V5_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 112706#define MC_CMD_GET_CAPABILITIES_V5_OUT_MCDI_BACKGROUND_OFST 2012707#define MC_CMD_GET_CAPABILITIES_V5_OUT_MCDI_BACKGROUND_LBN 1312708#define MC_CMD_GET_CAPABILITIES_V5_OUT_MCDI_BACKGROUND_WIDTH 112709#define MC_CMD_GET_CAPABILITIES_V5_OUT_MCDI_DB_RETURN_OFST 2012710#define MC_CMD_GET_CAPABILITIES_V5_OUT_MCDI_DB_RETURN_LBN 1412711#define MC_CMD_GET_CAPABILITIES_V5_OUT_MCDI_DB_RETURN_WIDTH 112712#define MC_CMD_GET_CAPABILITIES_V5_OUT_CTPIO_OFST 2012713#define MC_CMD_GET_CAPABILITIES_V5_OUT_CTPIO_LBN 1512714#define MC_CMD_GET_CAPABILITIES_V5_OUT_CTPIO_WIDTH 112715#define MC_CMD_GET_CAPABILITIES_V5_OUT_TSA_SUPPORT_OFST 2012716#define MC_CMD_GET_CAPABILITIES_V5_OUT_TSA_SUPPORT_LBN 1612717#define MC_CMD_GET_CAPABILITIES_V5_OUT_TSA_SUPPORT_WIDTH 112718#define MC_CMD_GET_CAPABILITIES_V5_OUT_TSA_BOUND_OFST 2012719#define MC_CMD_GET_CAPABILITIES_V5_OUT_TSA_BOUND_LBN 1712720#define MC_CMD_GET_CAPABILITIES_V5_OUT_TSA_BOUND_WIDTH 112721#define MC_CMD_GET_CAPABILITIES_V5_OUT_SF_ADAPTER_AUTHENTICATION_OFST 2012722#define MC_CMD_GET_CAPABILITIES_V5_OUT_SF_ADAPTER_AUTHENTICATION_LBN 1812723#define MC_CMD_GET_CAPABILITIES_V5_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 112724#define MC_CMD_GET_CAPABILITIES_V5_OUT_FILTER_ACTION_FLAG_OFST 2012725#define MC_CMD_GET_CAPABILITIES_V5_OUT_FILTER_ACTION_FLAG_LBN 1912726#define MC_CMD_GET_CAPABILITIES_V5_OUT_FILTER_ACTION_FLAG_WIDTH 112727#define MC_CMD_GET_CAPABILITIES_V5_OUT_FILTER_ACTION_MARK_OFST 2012728#define MC_CMD_GET_CAPABILITIES_V5_OUT_FILTER_ACTION_MARK_LBN 2012729#define MC_CMD_GET_CAPABILITIES_V5_OUT_FILTER_ACTION_MARK_WIDTH 112730#define MC_CMD_GET_CAPABILITIES_V5_OUT_EQUAL_STRIDE_SUPER_BUFFER_OFST 2012731#define MC_CMD_GET_CAPABILITIES_V5_OUT_EQUAL_STRIDE_SUPER_BUFFER_LBN 2112732#define MC_CMD_GET_CAPABILITIES_V5_OUT_EQUAL_STRIDE_SUPER_BUFFER_WIDTH 112733#define MC_CMD_GET_CAPABILITIES_V5_OUT_EQUAL_STRIDE_PACKED_STREAM_OFST 2012734#define MC_CMD_GET_CAPABILITIES_V5_OUT_EQUAL_STRIDE_PACKED_STREAM_LBN 2112735#define MC_CMD_GET_CAPABILITIES_V5_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 112736#define MC_CMD_GET_CAPABILITIES_V5_OUT_L3XUDP_SUPPORT_OFST 2012737#define MC_CMD_GET_CAPABILITIES_V5_OUT_L3XUDP_SUPPORT_LBN 2212738#define MC_CMD_GET_CAPABILITIES_V5_OUT_L3XUDP_SUPPORT_WIDTH 112739#define MC_CMD_GET_CAPABILITIES_V5_OUT_FW_SUBVARIANT_NO_TX_CSUM_OFST 2012740#define MC_CMD_GET_CAPABILITIES_V5_OUT_FW_SUBVARIANT_NO_TX_CSUM_LBN 2312741#define MC_CMD_GET_CAPABILITIES_V5_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 112742#define MC_CMD_GET_CAPABILITIES_V5_OUT_VI_SPREADING_OFST 2012743#define MC_CMD_GET_CAPABILITIES_V5_OUT_VI_SPREADING_LBN 2412744#define MC_CMD_GET_CAPABILITIES_V5_OUT_VI_SPREADING_WIDTH 112745#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_HLB_IDLE_OFST 2012746#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_HLB_IDLE_LBN 2512747#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_HLB_IDLE_WIDTH 112748#define MC_CMD_GET_CAPABILITIES_V5_OUT_INIT_RXQ_NO_CONT_EV_OFST 2012749#define MC_CMD_GET_CAPABILITIES_V5_OUT_INIT_RXQ_NO_CONT_EV_LBN 2612750#define MC_CMD_GET_CAPABILITIES_V5_OUT_INIT_RXQ_NO_CONT_EV_WIDTH 112751#define MC_CMD_GET_CAPABILITIES_V5_OUT_INIT_RXQ_WITH_BUFFER_SIZE_OFST 2012752#define MC_CMD_GET_CAPABILITIES_V5_OUT_INIT_RXQ_WITH_BUFFER_SIZE_LBN 2712753#define MC_CMD_GET_CAPABILITIES_V5_OUT_INIT_RXQ_WITH_BUFFER_SIZE_WIDTH 112754#define MC_CMD_GET_CAPABILITIES_V5_OUT_BUNDLE_UPDATE_OFST 2012755#define MC_CMD_GET_CAPABILITIES_V5_OUT_BUNDLE_UPDATE_LBN 2812756#define MC_CMD_GET_CAPABILITIES_V5_OUT_BUNDLE_UPDATE_WIDTH 112757#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V3_OFST 2012758#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V3_LBN 2912759#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V3_WIDTH 112760#define MC_CMD_GET_CAPABILITIES_V5_OUT_DYNAMIC_SENSORS_OFST 2012761#define MC_CMD_GET_CAPABILITIES_V5_OUT_DYNAMIC_SENSORS_LBN 3012762#define MC_CMD_GET_CAPABILITIES_V5_OUT_DYNAMIC_SENSORS_WIDTH 112763#define MC_CMD_GET_CAPABILITIES_V5_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_OFST 2012764#define MC_CMD_GET_CAPABILITIES_V5_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_LBN 3112765#define MC_CMD_GET_CAPABILITIES_V5_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_WIDTH 112766/* Number of FATSOv2 contexts per datapath supported by this NIC (when12767 * TX_TSO_V2 == 1). Not present on older firmware (check the length).12768 */12769#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V2_N_CONTEXTS_OFST 2412770#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V2_N_CONTEXTS_LEN 212771/* One byte per PF containing the number of the external port assigned to this12772 * PF, indexed by PF number. Special values indicate that a PF is either not12773 * present or not assigned.12774 */12775#define MC_CMD_GET_CAPABILITIES_V5_OUT_PFS_TO_PORTS_ASSIGNMENT_OFST 2612776#define MC_CMD_GET_CAPABILITIES_V5_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 112777#define MC_CMD_GET_CAPABILITIES_V5_OUT_PFS_TO_PORTS_ASSIGNMENT_NUM 1612778/* enum: The caller is not permitted to access information on this PF. */12779#define MC_CMD_GET_CAPABILITIES_V5_OUT_ACCESS_NOT_PERMITTED 0xff12780/* enum: PF does not exist. */12781#define MC_CMD_GET_CAPABILITIES_V5_OUT_PF_NOT_PRESENT 0xfe12782/* enum: PF does exist but is not assigned to any external port. */12783#define MC_CMD_GET_CAPABILITIES_V5_OUT_PF_NOT_ASSIGNED 0xfd12784/* enum: This value indicates that PF is assigned, but it cannot be expressed12785 * in this field. It is intended for a possible future situation where a more12786 * complex scheme of PFs to ports mapping is being used. The future driver12787 * should look for a new field supporting the new scheme. The current/old12788 * driver should treat this value as PF_NOT_ASSIGNED.12789 */12790#define MC_CMD_GET_CAPABILITIES_V5_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc12791/* One byte per PF containing the number of its VFs, indexed by PF number. A12792 * special value indicates that a PF is not present.12793 */12794#define MC_CMD_GET_CAPABILITIES_V5_OUT_NUM_VFS_PER_PF_OFST 4212795#define MC_CMD_GET_CAPABILITIES_V5_OUT_NUM_VFS_PER_PF_LEN 112796#define MC_CMD_GET_CAPABILITIES_V5_OUT_NUM_VFS_PER_PF_NUM 1612797/* enum: The caller is not permitted to access information on this PF. */12798/* MC_CMD_GET_CAPABILITIES_V5_OUT_ACCESS_NOT_PERMITTED 0xff */12799/* enum: PF does not exist. */12800/* MC_CMD_GET_CAPABILITIES_V5_OUT_PF_NOT_PRESENT 0xfe */12801/* Number of VIs available for each external port */12802#define MC_CMD_GET_CAPABILITIES_V5_OUT_NUM_VIS_PER_PORT_OFST 5812803#define MC_CMD_GET_CAPABILITIES_V5_OUT_NUM_VIS_PER_PORT_LEN 212804#define MC_CMD_GET_CAPABILITIES_V5_OUT_NUM_VIS_PER_PORT_NUM 412805/* Size of RX descriptor cache expressed as binary logarithm The actual size12806 * equals (2 ^ RX_DESC_CACHE_SIZE)12807 */12808#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_DESC_CACHE_SIZE_OFST 6612809#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_DESC_CACHE_SIZE_LEN 112810/* Size of TX descriptor cache expressed as binary logarithm The actual size12811 * equals (2 ^ TX_DESC_CACHE_SIZE)12812 */12813#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_DESC_CACHE_SIZE_OFST 6712814#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_DESC_CACHE_SIZE_LEN 112815/* Total number of available PIO buffers */12816#define MC_CMD_GET_CAPABILITIES_V5_OUT_NUM_PIO_BUFFS_OFST 6812817#define MC_CMD_GET_CAPABILITIES_V5_OUT_NUM_PIO_BUFFS_LEN 212818/* Size of a single PIO buffer */12819#define MC_CMD_GET_CAPABILITIES_V5_OUT_SIZE_PIO_BUFF_OFST 7012820#define MC_CMD_GET_CAPABILITIES_V5_OUT_SIZE_PIO_BUFF_LEN 212821/* On chips later than Medford the amount of address space assigned to each VI12822 * is configurable. This is a global setting that the driver must query to12823 * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available12824 * with 8k VI windows.12825 */12826#define MC_CMD_GET_CAPABILITIES_V5_OUT_VI_WINDOW_MODE_OFST 7212827#define MC_CMD_GET_CAPABILITIES_V5_OUT_VI_WINDOW_MODE_LEN 112828/* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k.12829 * CTPIO is not mapped.12830 */12831#define MC_CMD_GET_CAPABILITIES_V5_OUT_VI_WINDOW_MODE_8K 0x012832/* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */12833#define MC_CMD_GET_CAPABILITIES_V5_OUT_VI_WINDOW_MODE_16K 0x112834/* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */12835#define MC_CMD_GET_CAPABILITIES_V5_OUT_VI_WINDOW_MODE_64K 0x212836/* Number of vFIFOs per adapter that can be used for VFIFO Stuffing12837 * (SF-115995-SW) in the present configuration of firmware and port mode.12838 */12839#define MC_CMD_GET_CAPABILITIES_V5_OUT_VFIFO_STUFFING_NUM_VFIFOS_OFST 7312840#define MC_CMD_GET_CAPABILITIES_V5_OUT_VFIFO_STUFFING_NUM_VFIFOS_LEN 112841/* Number of buffers per adapter that can be used for VFIFO Stuffing12842 * (SF-115995-SW) in the present configuration of firmware and port mode.12843 */12844#define MC_CMD_GET_CAPABILITIES_V5_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_OFST 7412845#define MC_CMD_GET_CAPABILITIES_V5_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_LEN 212846/* Entry count in the MAC stats array, including the final GENERATION_END12847 * entry. For MAC stats DMA, drivers should allocate a buffer large enough to12848 * hold at least this many 64-bit stats values, if they wish to receive all12849 * available stats. If the buffer is shorter than MAC_STATS_NUM_STATS * 8, the12850 * stats array returned will be truncated.12851 */12852#define MC_CMD_GET_CAPABILITIES_V5_OUT_MAC_STATS_NUM_STATS_OFST 7612853#define MC_CMD_GET_CAPABILITIES_V5_OUT_MAC_STATS_NUM_STATS_LEN 212854/* Maximum supported value for MC_CMD_FILTER_OP_V3/MATCH_MARK_VALUE. This field12855 * will only be non-zero if MC_CMD_GET_CAPABILITIES/FILTER_ACTION_MARK is set.12856 */12857#define MC_CMD_GET_CAPABILITIES_V5_OUT_FILTER_ACTION_MARK_MAX_OFST 8012858#define MC_CMD_GET_CAPABILITIES_V5_OUT_FILTER_ACTION_MARK_MAX_LEN 412859 12860/* MC_CMD_GET_CAPABILITIES_V6_OUT msgresponse */12861#define MC_CMD_GET_CAPABILITIES_V6_OUT_LEN 14812862/* First word of flags. */12863#define MC_CMD_GET_CAPABILITIES_V6_OUT_FLAGS1_OFST 012864#define MC_CMD_GET_CAPABILITIES_V6_OUT_FLAGS1_LEN 412865#define MC_CMD_GET_CAPABILITIES_V6_OUT_VPORT_RECONFIGURE_OFST 012866#define MC_CMD_GET_CAPABILITIES_V6_OUT_VPORT_RECONFIGURE_LBN 312867#define MC_CMD_GET_CAPABILITIES_V6_OUT_VPORT_RECONFIGURE_WIDTH 112868#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_STRIPING_OFST 012869#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_STRIPING_LBN 412870#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_STRIPING_WIDTH 112871#define MC_CMD_GET_CAPABILITIES_V6_OUT_VADAPTOR_QUERY_OFST 012872#define MC_CMD_GET_CAPABILITIES_V6_OUT_VADAPTOR_QUERY_LBN 512873#define MC_CMD_GET_CAPABILITIES_V6_OUT_VADAPTOR_QUERY_WIDTH 112874#define MC_CMD_GET_CAPABILITIES_V6_OUT_EVB_PORT_VLAN_RESTRICT_OFST 012875#define MC_CMD_GET_CAPABILITIES_V6_OUT_EVB_PORT_VLAN_RESTRICT_LBN 612876#define MC_CMD_GET_CAPABILITIES_V6_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 112877#define MC_CMD_GET_CAPABILITIES_V6_OUT_DRV_ATTACH_PREBOOT_OFST 012878#define MC_CMD_GET_CAPABILITIES_V6_OUT_DRV_ATTACH_PREBOOT_LBN 712879#define MC_CMD_GET_CAPABILITIES_V6_OUT_DRV_ATTACH_PREBOOT_WIDTH 112880#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_FORCE_EVENT_MERGING_OFST 012881#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_FORCE_EVENT_MERGING_LBN 812882#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_FORCE_EVENT_MERGING_WIDTH 112883#define MC_CMD_GET_CAPABILITIES_V6_OUT_SET_MAC_ENHANCED_OFST 012884#define MC_CMD_GET_CAPABILITIES_V6_OUT_SET_MAC_ENHANCED_LBN 912885#define MC_CMD_GET_CAPABILITIES_V6_OUT_SET_MAC_ENHANCED_WIDTH 112886#define MC_CMD_GET_CAPABILITIES_V6_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 012887#define MC_CMD_GET_CAPABILITIES_V6_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 1012888#define MC_CMD_GET_CAPABILITIES_V6_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 112889#define MC_CMD_GET_CAPABILITIES_V6_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 012890#define MC_CMD_GET_CAPABILITIES_V6_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 1112891#define MC_CMD_GET_CAPABILITIES_V6_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 112892#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_MAC_SECURITY_FILTERING_OFST 012893#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_MAC_SECURITY_FILTERING_LBN 1212894#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 112895#define MC_CMD_GET_CAPABILITIES_V6_OUT_ADDITIONAL_RSS_MODES_OFST 012896#define MC_CMD_GET_CAPABILITIES_V6_OUT_ADDITIONAL_RSS_MODES_LBN 1312897#define MC_CMD_GET_CAPABILITIES_V6_OUT_ADDITIONAL_RSS_MODES_WIDTH 112898#define MC_CMD_GET_CAPABILITIES_V6_OUT_QBB_OFST 012899#define MC_CMD_GET_CAPABILITIES_V6_OUT_QBB_LBN 1412900#define MC_CMD_GET_CAPABILITIES_V6_OUT_QBB_WIDTH 112901#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 012902#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 1512903#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 112904#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_RSS_LIMITED_OFST 012905#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_RSS_LIMITED_LBN 1612906#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_RSS_LIMITED_WIDTH 112907#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PACKED_STREAM_OFST 012908#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PACKED_STREAM_LBN 1712909#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PACKED_STREAM_WIDTH 112910#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_INCLUDE_FCS_OFST 012911#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_INCLUDE_FCS_LBN 1812912#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_INCLUDE_FCS_WIDTH 112913#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_VLAN_INSERTION_OFST 012914#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_VLAN_INSERTION_LBN 1912915#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_VLAN_INSERTION_WIDTH 112916#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_VLAN_STRIPPING_OFST 012917#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_VLAN_STRIPPING_LBN 2012918#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_VLAN_STRIPPING_WIDTH 112919#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_OFST 012920#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_LBN 2112921#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_WIDTH 112922#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PREFIX_LEN_0_OFST 012923#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PREFIX_LEN_0_LBN 2212924#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PREFIX_LEN_0_WIDTH 112925#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PREFIX_LEN_14_OFST 012926#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PREFIX_LEN_14_LBN 2312927#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PREFIX_LEN_14_WIDTH 112928#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_TIMESTAMP_OFST 012929#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_TIMESTAMP_LBN 2412930#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_TIMESTAMP_WIDTH 112931#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_BATCHING_OFST 012932#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_BATCHING_LBN 2512933#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_BATCHING_WIDTH 112934#define MC_CMD_GET_CAPABILITIES_V6_OUT_MCAST_FILTER_CHAINING_OFST 012935#define MC_CMD_GET_CAPABILITIES_V6_OUT_MCAST_FILTER_CHAINING_LBN 2612936#define MC_CMD_GET_CAPABILITIES_V6_OUT_MCAST_FILTER_CHAINING_WIDTH 112937#define MC_CMD_GET_CAPABILITIES_V6_OUT_PM_AND_RXDP_COUNTERS_OFST 012938#define MC_CMD_GET_CAPABILITIES_V6_OUT_PM_AND_RXDP_COUNTERS_LBN 2712939#define MC_CMD_GET_CAPABILITIES_V6_OUT_PM_AND_RXDP_COUNTERS_WIDTH 112940#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_DISABLE_SCATTER_OFST 012941#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_DISABLE_SCATTER_LBN 2812942#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_DISABLE_SCATTER_WIDTH 112943#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_MCAST_UDP_LOOPBACK_OFST 012944#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_MCAST_UDP_LOOPBACK_LBN 2912945#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 112946#define MC_CMD_GET_CAPABILITIES_V6_OUT_EVB_OFST 012947#define MC_CMD_GET_CAPABILITIES_V6_OUT_EVB_LBN 3012948#define MC_CMD_GET_CAPABILITIES_V6_OUT_EVB_WIDTH 112949#define MC_CMD_GET_CAPABILITIES_V6_OUT_VXLAN_NVGRE_OFST 012950#define MC_CMD_GET_CAPABILITIES_V6_OUT_VXLAN_NVGRE_LBN 3112951#define MC_CMD_GET_CAPABILITIES_V6_OUT_VXLAN_NVGRE_WIDTH 112952/* RxDPCPU firmware id. */12953#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_DPCPU_FW_ID_OFST 412954#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_DPCPU_FW_ID_LEN 212955/* enum: Standard RXDP firmware */12956#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP 0x012957/* enum: Low latency RXDP firmware */12958#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_LOW_LATENCY 0x112959/* enum: Packed stream RXDP firmware */12960#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_PACKED_STREAM 0x212961/* enum: Rules engine RXDP firmware */12962#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_RULES_ENGINE 0x512963/* enum: DPDK RXDP firmware */12964#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_DPDK 0x612965/* enum: BIST RXDP firmware */12966#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_BIST 0x10a12967/* enum: RXDP Test firmware image 1 */12968#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x10112969/* enum: RXDP Test firmware image 2 */12970#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x10212971/* enum: RXDP Test firmware image 3 */12972#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x10312973/* enum: RXDP Test firmware image 4 */12974#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x10412975/* enum: RXDP Test firmware image 5 */12976#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_BACKPRESSURE 0x10512977/* enum: RXDP Test firmware image 6 */12978#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_FW_PACKET_EDITS 0x10612979/* enum: RXDP Test firmware image 7 */12980#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x10712981/* enum: RXDP Test firmware image 8 */12982#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_FW_DISABLE_DL 0x10812983/* enum: RXDP Test firmware image 9 */12984#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b12985/* enum: RXDP Test firmware image 10 */12986#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_FW_SLOW 0x10c12987/* TxDPCPU firmware id. */12988#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_DPCPU_FW_ID_OFST 612989#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_DPCPU_FW_ID_LEN 212990/* enum: Standard TXDP firmware */12991#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXDP 0x012992/* enum: Low latency TXDP firmware */12993#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXDP_LOW_LATENCY 0x112994/* enum: High packet rate TXDP firmware */12995#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXDP_HIGH_PACKET_RATE 0x312996/* enum: Rules engine TXDP firmware */12997#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXDP_RULES_ENGINE 0x512998/* enum: DPDK TXDP firmware */12999#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXDP_DPDK 0x613000/* enum: BIST TXDP firmware */13001#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXDP_BIST 0x12d13002/* enum: TXDP Test firmware image 1 */13003#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXDP_TEST_FW_TSO_EDIT 0x10113004/* enum: TXDP Test firmware image 2 */13005#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXDP_TEST_FW_PACKET_EDITS 0x10213006/* enum: TXDP CSR bus test firmware */13007#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXDP_TEST_FW_CSR 0x10313008#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_VERSION_OFST 813009#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_VERSION_LEN 213010#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_VERSION_REV_OFST 813011#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_VERSION_REV_LBN 013012#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_VERSION_REV_WIDTH 1213013#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_VERSION_TYPE_OFST 813014#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_VERSION_TYPE_LBN 1213015#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_VERSION_TYPE_WIDTH 413016/* enum: reserved value - do not use (may indicate alternative interpretation13017 * of REV field in future)13018 */13019#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_RESERVED 0x013020/* enum: Trivial RX PD firmware for early Huntington development (Huntington13021 * development only)13022 */13023#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_FIRST_PKT 0x113024/* enum: RX PD firmware for telemetry prototyping (Medford2 development only)13025 */13026#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x113027/* enum: RX PD firmware with approximately Siena-compatible behaviour13028 * (Huntington development only)13029 */13030#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x213031/* enum: Full featured RX PD production firmware */13032#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x313033/* enum: (deprecated original name for the FULL_FEATURED variant) */13034#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_VSWITCH 0x313035/* enum: siena_compat variant RX PD firmware using PM rather than MAC13036 * (Huntington development only)13037 */13038#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x413039/* enum: Low latency RX PD production firmware */13040#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x513041/* enum: Packed stream RX PD production firmware */13042#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x613043/* enum: RX PD firmware handling layer 2 only for high packet rate performance13044 * tests (Medford development only)13045 */13046#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x713047/* enum: Rules engine RX PD production firmware */13048#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x813049/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */13050#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_L3XUDP 0x913051/* enum: DPDK RX PD production firmware */13052#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_DPDK 0xa13053/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */13054#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe13055/* enum: RX PD firmware parsing but not filtering network overlay tunnel13056 * encapsulations (Medford development only)13057 */13058#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf13059#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_VERSION_OFST 1013060#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_VERSION_LEN 213061#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_VERSION_REV_OFST 1013062#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_VERSION_REV_LBN 013063#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_VERSION_REV_WIDTH 1213064#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_VERSION_TYPE_OFST 1013065#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_VERSION_TYPE_LBN 1213066#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_VERSION_TYPE_WIDTH 413067/* enum: reserved value - do not use (may indicate alternative interpretation13068 * of REV field in future)13069 */13070#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_RESERVED 0x013071/* enum: Trivial TX PD firmware for early Huntington development (Huntington13072 * development only)13073 */13074#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_FIRST_PKT 0x113075/* enum: TX PD firmware for telemetry prototyping (Medford2 development only)13076 */13077#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x113078/* enum: TX PD firmware with approximately Siena-compatible behaviour13079 * (Huntington development only)13080 */13081#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x213082/* enum: Full featured TX PD production firmware */13083#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x313084/* enum: (deprecated original name for the FULL_FEATURED variant) */13085#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_VSWITCH 0x313086/* enum: siena_compat variant TX PD firmware using PM rather than MAC13087 * (Huntington development only)13088 */13089#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x413090#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */13091/* enum: TX PD firmware handling layer 2 only for high packet rate performance13092 * tests (Medford development only)13093 */13094#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x713095/* enum: Rules engine TX PD production firmware */13096#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x813097/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */13098#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_L3XUDP 0x913099/* enum: DPDK TX PD production firmware */13100#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_DPDK 0xa13101/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */13102#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe13103/* Hardware capabilities of NIC */13104#define MC_CMD_GET_CAPABILITIES_V6_OUT_HW_CAPABILITIES_OFST 1213105#define MC_CMD_GET_CAPABILITIES_V6_OUT_HW_CAPABILITIES_LEN 413106/* Licensed capabilities */13107#define MC_CMD_GET_CAPABILITIES_V6_OUT_LICENSE_CAPABILITIES_OFST 1613108#define MC_CMD_GET_CAPABILITIES_V6_OUT_LICENSE_CAPABILITIES_LEN 413109/* Second word of flags. Not present on older firmware (check the length). */13110#define MC_CMD_GET_CAPABILITIES_V6_OUT_FLAGS2_OFST 2013111#define MC_CMD_GET_CAPABILITIES_V6_OUT_FLAGS2_LEN 413112#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_V2_OFST 2013113#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_V2_LBN 013114#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_V2_WIDTH 113115#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_V2_ENCAP_OFST 2013116#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_V2_ENCAP_LBN 113117#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_V2_ENCAP_WIDTH 113118#define MC_CMD_GET_CAPABILITIES_V6_OUT_EVQ_TIMER_CTRL_OFST 2013119#define MC_CMD_GET_CAPABILITIES_V6_OUT_EVQ_TIMER_CTRL_LBN 213120#define MC_CMD_GET_CAPABILITIES_V6_OUT_EVQ_TIMER_CTRL_WIDTH 113121#define MC_CMD_GET_CAPABILITIES_V6_OUT_EVENT_CUT_THROUGH_OFST 2013122#define MC_CMD_GET_CAPABILITIES_V6_OUT_EVENT_CUT_THROUGH_LBN 313123#define MC_CMD_GET_CAPABILITIES_V6_OUT_EVENT_CUT_THROUGH_WIDTH 113124#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_CUT_THROUGH_OFST 2013125#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_CUT_THROUGH_LBN 413126#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_CUT_THROUGH_WIDTH 113127#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_VFIFO_ULL_MODE_OFST 2013128#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_VFIFO_ULL_MODE_LBN 513129#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_VFIFO_ULL_MODE_WIDTH 113130#define MC_CMD_GET_CAPABILITIES_V6_OUT_MAC_STATS_40G_TX_SIZE_BINS_OFST 2013131#define MC_CMD_GET_CAPABILITIES_V6_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 613132#define MC_CMD_GET_CAPABILITIES_V6_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 113133#define MC_CMD_GET_CAPABILITIES_V6_OUT_INIT_EVQ_TYPE_SUPPORTED_OFST 2013134#define MC_CMD_GET_CAPABILITIES_V6_OUT_INIT_EVQ_TYPE_SUPPORTED_LBN 713135#define MC_CMD_GET_CAPABILITIES_V6_OUT_INIT_EVQ_TYPE_SUPPORTED_WIDTH 113136#define MC_CMD_GET_CAPABILITIES_V6_OUT_INIT_EVQ_V2_OFST 2013137#define MC_CMD_GET_CAPABILITIES_V6_OUT_INIT_EVQ_V2_LBN 713138#define MC_CMD_GET_CAPABILITIES_V6_OUT_INIT_EVQ_V2_WIDTH 113139#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_MAC_TIMESTAMPING_OFST 2013140#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_MAC_TIMESTAMPING_LBN 813141#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_MAC_TIMESTAMPING_WIDTH 113142#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TIMESTAMP_OFST 2013143#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TIMESTAMP_LBN 913144#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TIMESTAMP_WIDTH 113145#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_SNIFF_OFST 2013146#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_SNIFF_LBN 1013147#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_SNIFF_WIDTH 113148#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_SNIFF_OFST 2013149#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_SNIFF_LBN 1113150#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_SNIFF_WIDTH 113151#define MC_CMD_GET_CAPABILITIES_V6_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_OFST 2013152#define MC_CMD_GET_CAPABILITIES_V6_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_LBN 1213153#define MC_CMD_GET_CAPABILITIES_V6_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 113154#define MC_CMD_GET_CAPABILITIES_V6_OUT_MCDI_BACKGROUND_OFST 2013155#define MC_CMD_GET_CAPABILITIES_V6_OUT_MCDI_BACKGROUND_LBN 1313156#define MC_CMD_GET_CAPABILITIES_V6_OUT_MCDI_BACKGROUND_WIDTH 113157#define MC_CMD_GET_CAPABILITIES_V6_OUT_MCDI_DB_RETURN_OFST 2013158#define MC_CMD_GET_CAPABILITIES_V6_OUT_MCDI_DB_RETURN_LBN 1413159#define MC_CMD_GET_CAPABILITIES_V6_OUT_MCDI_DB_RETURN_WIDTH 113160#define MC_CMD_GET_CAPABILITIES_V6_OUT_CTPIO_OFST 2013161#define MC_CMD_GET_CAPABILITIES_V6_OUT_CTPIO_LBN 1513162#define MC_CMD_GET_CAPABILITIES_V6_OUT_CTPIO_WIDTH 113163#define MC_CMD_GET_CAPABILITIES_V6_OUT_TSA_SUPPORT_OFST 2013164#define MC_CMD_GET_CAPABILITIES_V6_OUT_TSA_SUPPORT_LBN 1613165#define MC_CMD_GET_CAPABILITIES_V6_OUT_TSA_SUPPORT_WIDTH 113166#define MC_CMD_GET_CAPABILITIES_V6_OUT_TSA_BOUND_OFST 2013167#define MC_CMD_GET_CAPABILITIES_V6_OUT_TSA_BOUND_LBN 1713168#define MC_CMD_GET_CAPABILITIES_V6_OUT_TSA_BOUND_WIDTH 113169#define MC_CMD_GET_CAPABILITIES_V6_OUT_SF_ADAPTER_AUTHENTICATION_OFST 2013170#define MC_CMD_GET_CAPABILITIES_V6_OUT_SF_ADAPTER_AUTHENTICATION_LBN 1813171#define MC_CMD_GET_CAPABILITIES_V6_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 113172#define MC_CMD_GET_CAPABILITIES_V6_OUT_FILTER_ACTION_FLAG_OFST 2013173#define MC_CMD_GET_CAPABILITIES_V6_OUT_FILTER_ACTION_FLAG_LBN 1913174#define MC_CMD_GET_CAPABILITIES_V6_OUT_FILTER_ACTION_FLAG_WIDTH 113175#define MC_CMD_GET_CAPABILITIES_V6_OUT_FILTER_ACTION_MARK_OFST 2013176#define MC_CMD_GET_CAPABILITIES_V6_OUT_FILTER_ACTION_MARK_LBN 2013177#define MC_CMD_GET_CAPABILITIES_V6_OUT_FILTER_ACTION_MARK_WIDTH 113178#define MC_CMD_GET_CAPABILITIES_V6_OUT_EQUAL_STRIDE_SUPER_BUFFER_OFST 2013179#define MC_CMD_GET_CAPABILITIES_V6_OUT_EQUAL_STRIDE_SUPER_BUFFER_LBN 2113180#define MC_CMD_GET_CAPABILITIES_V6_OUT_EQUAL_STRIDE_SUPER_BUFFER_WIDTH 113181#define MC_CMD_GET_CAPABILITIES_V6_OUT_EQUAL_STRIDE_PACKED_STREAM_OFST 2013182#define MC_CMD_GET_CAPABILITIES_V6_OUT_EQUAL_STRIDE_PACKED_STREAM_LBN 2113183#define MC_CMD_GET_CAPABILITIES_V6_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 113184#define MC_CMD_GET_CAPABILITIES_V6_OUT_L3XUDP_SUPPORT_OFST 2013185#define MC_CMD_GET_CAPABILITIES_V6_OUT_L3XUDP_SUPPORT_LBN 2213186#define MC_CMD_GET_CAPABILITIES_V6_OUT_L3XUDP_SUPPORT_WIDTH 113187#define MC_CMD_GET_CAPABILITIES_V6_OUT_FW_SUBVARIANT_NO_TX_CSUM_OFST 2013188#define MC_CMD_GET_CAPABILITIES_V6_OUT_FW_SUBVARIANT_NO_TX_CSUM_LBN 2313189#define MC_CMD_GET_CAPABILITIES_V6_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 113190#define MC_CMD_GET_CAPABILITIES_V6_OUT_VI_SPREADING_OFST 2013191#define MC_CMD_GET_CAPABILITIES_V6_OUT_VI_SPREADING_LBN 2413192#define MC_CMD_GET_CAPABILITIES_V6_OUT_VI_SPREADING_WIDTH 113193#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_HLB_IDLE_OFST 2013194#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_HLB_IDLE_LBN 2513195#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_HLB_IDLE_WIDTH 113196#define MC_CMD_GET_CAPABILITIES_V6_OUT_INIT_RXQ_NO_CONT_EV_OFST 2013197#define MC_CMD_GET_CAPABILITIES_V6_OUT_INIT_RXQ_NO_CONT_EV_LBN 2613198#define MC_CMD_GET_CAPABILITIES_V6_OUT_INIT_RXQ_NO_CONT_EV_WIDTH 113199#define MC_CMD_GET_CAPABILITIES_V6_OUT_INIT_RXQ_WITH_BUFFER_SIZE_OFST 2013200#define MC_CMD_GET_CAPABILITIES_V6_OUT_INIT_RXQ_WITH_BUFFER_SIZE_LBN 2713201#define MC_CMD_GET_CAPABILITIES_V6_OUT_INIT_RXQ_WITH_BUFFER_SIZE_WIDTH 113202#define MC_CMD_GET_CAPABILITIES_V6_OUT_BUNDLE_UPDATE_OFST 2013203#define MC_CMD_GET_CAPABILITIES_V6_OUT_BUNDLE_UPDATE_LBN 2813204#define MC_CMD_GET_CAPABILITIES_V6_OUT_BUNDLE_UPDATE_WIDTH 113205#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_V3_OFST 2013206#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_V3_LBN 2913207#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_V3_WIDTH 113208#define MC_CMD_GET_CAPABILITIES_V6_OUT_DYNAMIC_SENSORS_OFST 2013209#define MC_CMD_GET_CAPABILITIES_V6_OUT_DYNAMIC_SENSORS_LBN 3013210#define MC_CMD_GET_CAPABILITIES_V6_OUT_DYNAMIC_SENSORS_WIDTH 113211#define MC_CMD_GET_CAPABILITIES_V6_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_OFST 2013212#define MC_CMD_GET_CAPABILITIES_V6_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_LBN 3113213#define MC_CMD_GET_CAPABILITIES_V6_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_WIDTH 113214/* Number of FATSOv2 contexts per datapath supported by this NIC (when13215 * TX_TSO_V2 == 1). Not present on older firmware (check the length).13216 */13217#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_V2_N_CONTEXTS_OFST 2413218#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_V2_N_CONTEXTS_LEN 213219/* One byte per PF containing the number of the external port assigned to this13220 * PF, indexed by PF number. Special values indicate that a PF is either not13221 * present or not assigned.13222 */13223#define MC_CMD_GET_CAPABILITIES_V6_OUT_PFS_TO_PORTS_ASSIGNMENT_OFST 2613224#define MC_CMD_GET_CAPABILITIES_V6_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 113225#define MC_CMD_GET_CAPABILITIES_V6_OUT_PFS_TO_PORTS_ASSIGNMENT_NUM 1613226/* enum: The caller is not permitted to access information on this PF. */13227#define MC_CMD_GET_CAPABILITIES_V6_OUT_ACCESS_NOT_PERMITTED 0xff13228/* enum: PF does not exist. */13229#define MC_CMD_GET_CAPABILITIES_V6_OUT_PF_NOT_PRESENT 0xfe13230/* enum: PF does exist but is not assigned to any external port. */13231#define MC_CMD_GET_CAPABILITIES_V6_OUT_PF_NOT_ASSIGNED 0xfd13232/* enum: This value indicates that PF is assigned, but it cannot be expressed13233 * in this field. It is intended for a possible future situation where a more13234 * complex scheme of PFs to ports mapping is being used. The future driver13235 * should look for a new field supporting the new scheme. The current/old13236 * driver should treat this value as PF_NOT_ASSIGNED.13237 */13238#define MC_CMD_GET_CAPABILITIES_V6_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc13239/* One byte per PF containing the number of its VFs, indexed by PF number. A13240 * special value indicates that a PF is not present.13241 */13242#define MC_CMD_GET_CAPABILITIES_V6_OUT_NUM_VFS_PER_PF_OFST 4213243#define MC_CMD_GET_CAPABILITIES_V6_OUT_NUM_VFS_PER_PF_LEN 113244#define MC_CMD_GET_CAPABILITIES_V6_OUT_NUM_VFS_PER_PF_NUM 1613245/* enum: The caller is not permitted to access information on this PF. */13246/* MC_CMD_GET_CAPABILITIES_V6_OUT_ACCESS_NOT_PERMITTED 0xff */13247/* enum: PF does not exist. */13248/* MC_CMD_GET_CAPABILITIES_V6_OUT_PF_NOT_PRESENT 0xfe */13249/* Number of VIs available for each external port */13250#define MC_CMD_GET_CAPABILITIES_V6_OUT_NUM_VIS_PER_PORT_OFST 5813251#define MC_CMD_GET_CAPABILITIES_V6_OUT_NUM_VIS_PER_PORT_LEN 213252#define MC_CMD_GET_CAPABILITIES_V6_OUT_NUM_VIS_PER_PORT_NUM 413253/* Size of RX descriptor cache expressed as binary logarithm The actual size13254 * equals (2 ^ RX_DESC_CACHE_SIZE)13255 */13256#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_DESC_CACHE_SIZE_OFST 6613257#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_DESC_CACHE_SIZE_LEN 113258/* Size of TX descriptor cache expressed as binary logarithm The actual size13259 * equals (2 ^ TX_DESC_CACHE_SIZE)13260 */13261#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_DESC_CACHE_SIZE_OFST 6713262#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_DESC_CACHE_SIZE_LEN 113263/* Total number of available PIO buffers */13264#define MC_CMD_GET_CAPABILITIES_V6_OUT_NUM_PIO_BUFFS_OFST 6813265#define MC_CMD_GET_CAPABILITIES_V6_OUT_NUM_PIO_BUFFS_LEN 213266/* Size of a single PIO buffer */13267#define MC_CMD_GET_CAPABILITIES_V6_OUT_SIZE_PIO_BUFF_OFST 7013268#define MC_CMD_GET_CAPABILITIES_V6_OUT_SIZE_PIO_BUFF_LEN 213269/* On chips later than Medford the amount of address space assigned to each VI13270 * is configurable. This is a global setting that the driver must query to13271 * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available13272 * with 8k VI windows.13273 */13274#define MC_CMD_GET_CAPABILITIES_V6_OUT_VI_WINDOW_MODE_OFST 7213275#define MC_CMD_GET_CAPABILITIES_V6_OUT_VI_WINDOW_MODE_LEN 113276/* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k.13277 * CTPIO is not mapped.13278 */13279#define MC_CMD_GET_CAPABILITIES_V6_OUT_VI_WINDOW_MODE_8K 0x013280/* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */13281#define MC_CMD_GET_CAPABILITIES_V6_OUT_VI_WINDOW_MODE_16K 0x113282/* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */13283#define MC_CMD_GET_CAPABILITIES_V6_OUT_VI_WINDOW_MODE_64K 0x213284/* Number of vFIFOs per adapter that can be used for VFIFO Stuffing13285 * (SF-115995-SW) in the present configuration of firmware and port mode.13286 */13287#define MC_CMD_GET_CAPABILITIES_V6_OUT_VFIFO_STUFFING_NUM_VFIFOS_OFST 7313288#define MC_CMD_GET_CAPABILITIES_V6_OUT_VFIFO_STUFFING_NUM_VFIFOS_LEN 113289/* Number of buffers per adapter that can be used for VFIFO Stuffing13290 * (SF-115995-SW) in the present configuration of firmware and port mode.13291 */13292#define MC_CMD_GET_CAPABILITIES_V6_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_OFST 7413293#define MC_CMD_GET_CAPABILITIES_V6_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_LEN 213294/* Entry count in the MAC stats array, including the final GENERATION_END13295 * entry. For MAC stats DMA, drivers should allocate a buffer large enough to13296 * hold at least this many 64-bit stats values, if they wish to receive all13297 * available stats. If the buffer is shorter than MAC_STATS_NUM_STATS * 8, the13298 * stats array returned will be truncated.13299 */13300#define MC_CMD_GET_CAPABILITIES_V6_OUT_MAC_STATS_NUM_STATS_OFST 7613301#define MC_CMD_GET_CAPABILITIES_V6_OUT_MAC_STATS_NUM_STATS_LEN 213302/* Maximum supported value for MC_CMD_FILTER_OP_V3/MATCH_MARK_VALUE. This field13303 * will only be non-zero if MC_CMD_GET_CAPABILITIES/FILTER_ACTION_MARK is set.13304 */13305#define MC_CMD_GET_CAPABILITIES_V6_OUT_FILTER_ACTION_MARK_MAX_OFST 8013306#define MC_CMD_GET_CAPABILITIES_V6_OUT_FILTER_ACTION_MARK_MAX_LEN 413307/* On devices where the INIT_RXQ_WITH_BUFFER_SIZE flag (in13308 * GET_CAPABILITIES_OUT_V2) is set, drivers have to specify a buffer size when13309 * they create an RX queue. Due to hardware limitations, only a small number of13310 * different buffer sizes may be available concurrently. Nonzero entries in13311 * this array are the sizes of buffers which the system guarantees will be13312 * available for use. If the list is empty, there are no limitations on13313 * concurrent buffer sizes.13314 */13315#define MC_CMD_GET_CAPABILITIES_V6_OUT_GUARANTEED_RX_BUFFER_SIZES_OFST 8413316#define MC_CMD_GET_CAPABILITIES_V6_OUT_GUARANTEED_RX_BUFFER_SIZES_LEN 413317#define MC_CMD_GET_CAPABILITIES_V6_OUT_GUARANTEED_RX_BUFFER_SIZES_NUM 1613318 13319/* MC_CMD_GET_CAPABILITIES_V7_OUT msgresponse */13320#define MC_CMD_GET_CAPABILITIES_V7_OUT_LEN 15213321/* First word of flags. */13322#define MC_CMD_GET_CAPABILITIES_V7_OUT_FLAGS1_OFST 013323#define MC_CMD_GET_CAPABILITIES_V7_OUT_FLAGS1_LEN 413324#define MC_CMD_GET_CAPABILITIES_V7_OUT_VPORT_RECONFIGURE_OFST 013325#define MC_CMD_GET_CAPABILITIES_V7_OUT_VPORT_RECONFIGURE_LBN 313326#define MC_CMD_GET_CAPABILITIES_V7_OUT_VPORT_RECONFIGURE_WIDTH 113327#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_STRIPING_OFST 013328#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_STRIPING_LBN 413329#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_STRIPING_WIDTH 113330#define MC_CMD_GET_CAPABILITIES_V7_OUT_VADAPTOR_QUERY_OFST 013331#define MC_CMD_GET_CAPABILITIES_V7_OUT_VADAPTOR_QUERY_LBN 513332#define MC_CMD_GET_CAPABILITIES_V7_OUT_VADAPTOR_QUERY_WIDTH 113333#define MC_CMD_GET_CAPABILITIES_V7_OUT_EVB_PORT_VLAN_RESTRICT_OFST 013334#define MC_CMD_GET_CAPABILITIES_V7_OUT_EVB_PORT_VLAN_RESTRICT_LBN 613335#define MC_CMD_GET_CAPABILITIES_V7_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 113336#define MC_CMD_GET_CAPABILITIES_V7_OUT_DRV_ATTACH_PREBOOT_OFST 013337#define MC_CMD_GET_CAPABILITIES_V7_OUT_DRV_ATTACH_PREBOOT_LBN 713338#define MC_CMD_GET_CAPABILITIES_V7_OUT_DRV_ATTACH_PREBOOT_WIDTH 113339#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_FORCE_EVENT_MERGING_OFST 013340#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_FORCE_EVENT_MERGING_LBN 813341#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_FORCE_EVENT_MERGING_WIDTH 113342#define MC_CMD_GET_CAPABILITIES_V7_OUT_SET_MAC_ENHANCED_OFST 013343#define MC_CMD_GET_CAPABILITIES_V7_OUT_SET_MAC_ENHANCED_LBN 913344#define MC_CMD_GET_CAPABILITIES_V7_OUT_SET_MAC_ENHANCED_WIDTH 113345#define MC_CMD_GET_CAPABILITIES_V7_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 013346#define MC_CMD_GET_CAPABILITIES_V7_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 1013347#define MC_CMD_GET_CAPABILITIES_V7_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 113348#define MC_CMD_GET_CAPABILITIES_V7_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 013349#define MC_CMD_GET_CAPABILITIES_V7_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 1113350#define MC_CMD_GET_CAPABILITIES_V7_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 113351#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_MAC_SECURITY_FILTERING_OFST 013352#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_MAC_SECURITY_FILTERING_LBN 1213353#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 113354#define MC_CMD_GET_CAPABILITIES_V7_OUT_ADDITIONAL_RSS_MODES_OFST 013355#define MC_CMD_GET_CAPABILITIES_V7_OUT_ADDITIONAL_RSS_MODES_LBN 1313356#define MC_CMD_GET_CAPABILITIES_V7_OUT_ADDITIONAL_RSS_MODES_WIDTH 113357#define MC_CMD_GET_CAPABILITIES_V7_OUT_QBB_OFST 013358#define MC_CMD_GET_CAPABILITIES_V7_OUT_QBB_LBN 1413359#define MC_CMD_GET_CAPABILITIES_V7_OUT_QBB_WIDTH 113360#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 013361#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 1513362#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 113363#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_RSS_LIMITED_OFST 013364#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_RSS_LIMITED_LBN 1613365#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_RSS_LIMITED_WIDTH 113366#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_PACKED_STREAM_OFST 013367#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_PACKED_STREAM_LBN 1713368#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_PACKED_STREAM_WIDTH 113369#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_INCLUDE_FCS_OFST 013370#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_INCLUDE_FCS_LBN 1813371#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_INCLUDE_FCS_WIDTH 113372#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_VLAN_INSERTION_OFST 013373#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_VLAN_INSERTION_LBN 1913374#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_VLAN_INSERTION_WIDTH 113375#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_VLAN_STRIPPING_OFST 013376#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_VLAN_STRIPPING_LBN 2013377#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_VLAN_STRIPPING_WIDTH 113378#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_OFST 013379#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_LBN 2113380#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_WIDTH 113381#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_PREFIX_LEN_0_OFST 013382#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_PREFIX_LEN_0_LBN 2213383#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_PREFIX_LEN_0_WIDTH 113384#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_PREFIX_LEN_14_OFST 013385#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_PREFIX_LEN_14_LBN 2313386#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_PREFIX_LEN_14_WIDTH 113387#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_TIMESTAMP_OFST 013388#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_TIMESTAMP_LBN 2413389#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_TIMESTAMP_WIDTH 113390#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_BATCHING_OFST 013391#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_BATCHING_LBN 2513392#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_BATCHING_WIDTH 113393#define MC_CMD_GET_CAPABILITIES_V7_OUT_MCAST_FILTER_CHAINING_OFST 013394#define MC_CMD_GET_CAPABILITIES_V7_OUT_MCAST_FILTER_CHAINING_LBN 2613395#define MC_CMD_GET_CAPABILITIES_V7_OUT_MCAST_FILTER_CHAINING_WIDTH 113396#define MC_CMD_GET_CAPABILITIES_V7_OUT_PM_AND_RXDP_COUNTERS_OFST 013397#define MC_CMD_GET_CAPABILITIES_V7_OUT_PM_AND_RXDP_COUNTERS_LBN 2713398#define MC_CMD_GET_CAPABILITIES_V7_OUT_PM_AND_RXDP_COUNTERS_WIDTH 113399#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_DISABLE_SCATTER_OFST 013400#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_DISABLE_SCATTER_LBN 2813401#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_DISABLE_SCATTER_WIDTH 113402#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_MCAST_UDP_LOOPBACK_OFST 013403#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_MCAST_UDP_LOOPBACK_LBN 2913404#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 113405#define MC_CMD_GET_CAPABILITIES_V7_OUT_EVB_OFST 013406#define MC_CMD_GET_CAPABILITIES_V7_OUT_EVB_LBN 3013407#define MC_CMD_GET_CAPABILITIES_V7_OUT_EVB_WIDTH 113408#define MC_CMD_GET_CAPABILITIES_V7_OUT_VXLAN_NVGRE_OFST 013409#define MC_CMD_GET_CAPABILITIES_V7_OUT_VXLAN_NVGRE_LBN 3113410#define MC_CMD_GET_CAPABILITIES_V7_OUT_VXLAN_NVGRE_WIDTH 113411/* RxDPCPU firmware id. */13412#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_DPCPU_FW_ID_OFST 413413#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_DPCPU_FW_ID_LEN 213414/* enum: Standard RXDP firmware */13415#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP 0x013416/* enum: Low latency RXDP firmware */13417#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_LOW_LATENCY 0x113418/* enum: Packed stream RXDP firmware */13419#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_PACKED_STREAM 0x213420/* enum: Rules engine RXDP firmware */13421#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_RULES_ENGINE 0x513422/* enum: DPDK RXDP firmware */13423#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_DPDK 0x613424/* enum: BIST RXDP firmware */13425#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_BIST 0x10a13426/* enum: RXDP Test firmware image 1 */13427#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x10113428/* enum: RXDP Test firmware image 2 */13429#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x10213430/* enum: RXDP Test firmware image 3 */13431#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x10313432/* enum: RXDP Test firmware image 4 */13433#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x10413434/* enum: RXDP Test firmware image 5 */13435#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_BACKPRESSURE 0x10513436/* enum: RXDP Test firmware image 6 */13437#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_FW_PACKET_EDITS 0x10613438/* enum: RXDP Test firmware image 7 */13439#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x10713440/* enum: RXDP Test firmware image 8 */13441#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_FW_DISABLE_DL 0x10813442/* enum: RXDP Test firmware image 9 */13443#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b13444/* enum: RXDP Test firmware image 10 */13445#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_FW_SLOW 0x10c13446/* TxDPCPU firmware id. */13447#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_DPCPU_FW_ID_OFST 613448#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_DPCPU_FW_ID_LEN 213449/* enum: Standard TXDP firmware */13450#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXDP 0x013451/* enum: Low latency TXDP firmware */13452#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXDP_LOW_LATENCY 0x113453/* enum: High packet rate TXDP firmware */13454#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXDP_HIGH_PACKET_RATE 0x313455/* enum: Rules engine TXDP firmware */13456#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXDP_RULES_ENGINE 0x513457/* enum: DPDK TXDP firmware */13458#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXDP_DPDK 0x613459/* enum: BIST TXDP firmware */13460#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXDP_BIST 0x12d13461/* enum: TXDP Test firmware image 1 */13462#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXDP_TEST_FW_TSO_EDIT 0x10113463/* enum: TXDP Test firmware image 2 */13464#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXDP_TEST_FW_PACKET_EDITS 0x10213465/* enum: TXDP CSR bus test firmware */13466#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXDP_TEST_FW_CSR 0x10313467#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_VERSION_OFST 813468#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_VERSION_LEN 213469#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_VERSION_REV_OFST 813470#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_VERSION_REV_LBN 013471#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_VERSION_REV_WIDTH 1213472#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_VERSION_TYPE_OFST 813473#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_VERSION_TYPE_LBN 1213474#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_VERSION_TYPE_WIDTH 413475/* enum: reserved value - do not use (may indicate alternative interpretation13476 * of REV field in future)13477 */13478#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_RESERVED 0x013479/* enum: Trivial RX PD firmware for early Huntington development (Huntington13480 * development only)13481 */13482#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_FIRST_PKT 0x113483/* enum: RX PD firmware for telemetry prototyping (Medford2 development only)13484 */13485#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x113486/* enum: RX PD firmware with approximately Siena-compatible behaviour13487 * (Huntington development only)13488 */13489#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x213490/* enum: Full featured RX PD production firmware */13491#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x313492/* enum: (deprecated original name for the FULL_FEATURED variant) */13493#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_VSWITCH 0x313494/* enum: siena_compat variant RX PD firmware using PM rather than MAC13495 * (Huntington development only)13496 */13497#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x413498/* enum: Low latency RX PD production firmware */13499#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x513500/* enum: Packed stream RX PD production firmware */13501#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x613502/* enum: RX PD firmware handling layer 2 only for high packet rate performance13503 * tests (Medford development only)13504 */13505#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x713506/* enum: Rules engine RX PD production firmware */13507#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x813508/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */13509#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_L3XUDP 0x913510/* enum: DPDK RX PD production firmware */13511#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_DPDK 0xa13512/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */13513#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe13514/* enum: RX PD firmware parsing but not filtering network overlay tunnel13515 * encapsulations (Medford development only)13516 */13517#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf13518#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_VERSION_OFST 1013519#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_VERSION_LEN 213520#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_VERSION_REV_OFST 1013521#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_VERSION_REV_LBN 013522#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_VERSION_REV_WIDTH 1213523#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_VERSION_TYPE_OFST 1013524#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_VERSION_TYPE_LBN 1213525#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_VERSION_TYPE_WIDTH 413526/* enum: reserved value - do not use (may indicate alternative interpretation13527 * of REV field in future)13528 */13529#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_RESERVED 0x013530/* enum: Trivial TX PD firmware for early Huntington development (Huntington13531 * development only)13532 */13533#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_FIRST_PKT 0x113534/* enum: TX PD firmware for telemetry prototyping (Medford2 development only)13535 */13536#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x113537/* enum: TX PD firmware with approximately Siena-compatible behaviour13538 * (Huntington development only)13539 */13540#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x213541/* enum: Full featured TX PD production firmware */13542#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x313543/* enum: (deprecated original name for the FULL_FEATURED variant) */13544#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_VSWITCH 0x313545/* enum: siena_compat variant TX PD firmware using PM rather than MAC13546 * (Huntington development only)13547 */13548#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x413549#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */13550/* enum: TX PD firmware handling layer 2 only for high packet rate performance13551 * tests (Medford development only)13552 */13553#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x713554/* enum: Rules engine TX PD production firmware */13555#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x813556/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */13557#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_L3XUDP 0x913558/* enum: DPDK TX PD production firmware */13559#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_DPDK 0xa13560/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */13561#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe13562/* Hardware capabilities of NIC */13563#define MC_CMD_GET_CAPABILITIES_V7_OUT_HW_CAPABILITIES_OFST 1213564#define MC_CMD_GET_CAPABILITIES_V7_OUT_HW_CAPABILITIES_LEN 413565/* Licensed capabilities */13566#define MC_CMD_GET_CAPABILITIES_V7_OUT_LICENSE_CAPABILITIES_OFST 1613567#define MC_CMD_GET_CAPABILITIES_V7_OUT_LICENSE_CAPABILITIES_LEN 413568/* Second word of flags. Not present on older firmware (check the length). */13569#define MC_CMD_GET_CAPABILITIES_V7_OUT_FLAGS2_OFST 2013570#define MC_CMD_GET_CAPABILITIES_V7_OUT_FLAGS2_LEN 413571#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_V2_OFST 2013572#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_V2_LBN 013573#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_V2_WIDTH 113574#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_V2_ENCAP_OFST 2013575#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_V2_ENCAP_LBN 113576#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_V2_ENCAP_WIDTH 113577#define MC_CMD_GET_CAPABILITIES_V7_OUT_EVQ_TIMER_CTRL_OFST 2013578#define MC_CMD_GET_CAPABILITIES_V7_OUT_EVQ_TIMER_CTRL_LBN 213579#define MC_CMD_GET_CAPABILITIES_V7_OUT_EVQ_TIMER_CTRL_WIDTH 113580#define MC_CMD_GET_CAPABILITIES_V7_OUT_EVENT_CUT_THROUGH_OFST 2013581#define MC_CMD_GET_CAPABILITIES_V7_OUT_EVENT_CUT_THROUGH_LBN 313582#define MC_CMD_GET_CAPABILITIES_V7_OUT_EVENT_CUT_THROUGH_WIDTH 113583#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_CUT_THROUGH_OFST 2013584#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_CUT_THROUGH_LBN 413585#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_CUT_THROUGH_WIDTH 113586#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_VFIFO_ULL_MODE_OFST 2013587#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_VFIFO_ULL_MODE_LBN 513588#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_VFIFO_ULL_MODE_WIDTH 113589#define MC_CMD_GET_CAPABILITIES_V7_OUT_MAC_STATS_40G_TX_SIZE_BINS_OFST 2013590#define MC_CMD_GET_CAPABILITIES_V7_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 613591#define MC_CMD_GET_CAPABILITIES_V7_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 113592#define MC_CMD_GET_CAPABILITIES_V7_OUT_INIT_EVQ_TYPE_SUPPORTED_OFST 2013593#define MC_CMD_GET_CAPABILITIES_V7_OUT_INIT_EVQ_TYPE_SUPPORTED_LBN 713594#define MC_CMD_GET_CAPABILITIES_V7_OUT_INIT_EVQ_TYPE_SUPPORTED_WIDTH 113595#define MC_CMD_GET_CAPABILITIES_V7_OUT_INIT_EVQ_V2_OFST 2013596#define MC_CMD_GET_CAPABILITIES_V7_OUT_INIT_EVQ_V2_LBN 713597#define MC_CMD_GET_CAPABILITIES_V7_OUT_INIT_EVQ_V2_WIDTH 113598#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_MAC_TIMESTAMPING_OFST 2013599#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_MAC_TIMESTAMPING_LBN 813600#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_MAC_TIMESTAMPING_WIDTH 113601#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TIMESTAMP_OFST 2013602#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TIMESTAMP_LBN 913603#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TIMESTAMP_WIDTH 113604#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_SNIFF_OFST 2013605#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_SNIFF_LBN 1013606#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_SNIFF_WIDTH 113607#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_SNIFF_OFST 2013608#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_SNIFF_LBN 1113609#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_SNIFF_WIDTH 113610#define MC_CMD_GET_CAPABILITIES_V7_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_OFST 2013611#define MC_CMD_GET_CAPABILITIES_V7_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_LBN 1213612#define MC_CMD_GET_CAPABILITIES_V7_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 113613#define MC_CMD_GET_CAPABILITIES_V7_OUT_MCDI_BACKGROUND_OFST 2013614#define MC_CMD_GET_CAPABILITIES_V7_OUT_MCDI_BACKGROUND_LBN 1313615#define MC_CMD_GET_CAPABILITIES_V7_OUT_MCDI_BACKGROUND_WIDTH 113616#define MC_CMD_GET_CAPABILITIES_V7_OUT_MCDI_DB_RETURN_OFST 2013617#define MC_CMD_GET_CAPABILITIES_V7_OUT_MCDI_DB_RETURN_LBN 1413618#define MC_CMD_GET_CAPABILITIES_V7_OUT_MCDI_DB_RETURN_WIDTH 113619#define MC_CMD_GET_CAPABILITIES_V7_OUT_CTPIO_OFST 2013620#define MC_CMD_GET_CAPABILITIES_V7_OUT_CTPIO_LBN 1513621#define MC_CMD_GET_CAPABILITIES_V7_OUT_CTPIO_WIDTH 113622#define MC_CMD_GET_CAPABILITIES_V7_OUT_TSA_SUPPORT_OFST 2013623#define MC_CMD_GET_CAPABILITIES_V7_OUT_TSA_SUPPORT_LBN 1613624#define MC_CMD_GET_CAPABILITIES_V7_OUT_TSA_SUPPORT_WIDTH 113625#define MC_CMD_GET_CAPABILITIES_V7_OUT_TSA_BOUND_OFST 2013626#define MC_CMD_GET_CAPABILITIES_V7_OUT_TSA_BOUND_LBN 1713627#define MC_CMD_GET_CAPABILITIES_V7_OUT_TSA_BOUND_WIDTH 113628#define MC_CMD_GET_CAPABILITIES_V7_OUT_SF_ADAPTER_AUTHENTICATION_OFST 2013629#define MC_CMD_GET_CAPABILITIES_V7_OUT_SF_ADAPTER_AUTHENTICATION_LBN 1813630#define MC_CMD_GET_CAPABILITIES_V7_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 113631#define MC_CMD_GET_CAPABILITIES_V7_OUT_FILTER_ACTION_FLAG_OFST 2013632#define MC_CMD_GET_CAPABILITIES_V7_OUT_FILTER_ACTION_FLAG_LBN 1913633#define MC_CMD_GET_CAPABILITIES_V7_OUT_FILTER_ACTION_FLAG_WIDTH 113634#define MC_CMD_GET_CAPABILITIES_V7_OUT_FILTER_ACTION_MARK_OFST 2013635#define MC_CMD_GET_CAPABILITIES_V7_OUT_FILTER_ACTION_MARK_LBN 2013636#define MC_CMD_GET_CAPABILITIES_V7_OUT_FILTER_ACTION_MARK_WIDTH 113637#define MC_CMD_GET_CAPABILITIES_V7_OUT_EQUAL_STRIDE_SUPER_BUFFER_OFST 2013638#define MC_CMD_GET_CAPABILITIES_V7_OUT_EQUAL_STRIDE_SUPER_BUFFER_LBN 2113639#define MC_CMD_GET_CAPABILITIES_V7_OUT_EQUAL_STRIDE_SUPER_BUFFER_WIDTH 113640#define MC_CMD_GET_CAPABILITIES_V7_OUT_EQUAL_STRIDE_PACKED_STREAM_OFST 2013641#define MC_CMD_GET_CAPABILITIES_V7_OUT_EQUAL_STRIDE_PACKED_STREAM_LBN 2113642#define MC_CMD_GET_CAPABILITIES_V7_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 113643#define MC_CMD_GET_CAPABILITIES_V7_OUT_L3XUDP_SUPPORT_OFST 2013644#define MC_CMD_GET_CAPABILITIES_V7_OUT_L3XUDP_SUPPORT_LBN 2213645#define MC_CMD_GET_CAPABILITIES_V7_OUT_L3XUDP_SUPPORT_WIDTH 113646#define MC_CMD_GET_CAPABILITIES_V7_OUT_FW_SUBVARIANT_NO_TX_CSUM_OFST 2013647#define MC_CMD_GET_CAPABILITIES_V7_OUT_FW_SUBVARIANT_NO_TX_CSUM_LBN 2313648#define MC_CMD_GET_CAPABILITIES_V7_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 113649#define MC_CMD_GET_CAPABILITIES_V7_OUT_VI_SPREADING_OFST 2013650#define MC_CMD_GET_CAPABILITIES_V7_OUT_VI_SPREADING_LBN 2413651#define MC_CMD_GET_CAPABILITIES_V7_OUT_VI_SPREADING_WIDTH 113652#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_HLB_IDLE_OFST 2013653#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_HLB_IDLE_LBN 2513654#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_HLB_IDLE_WIDTH 113655#define MC_CMD_GET_CAPABILITIES_V7_OUT_INIT_RXQ_NO_CONT_EV_OFST 2013656#define MC_CMD_GET_CAPABILITIES_V7_OUT_INIT_RXQ_NO_CONT_EV_LBN 2613657#define MC_CMD_GET_CAPABILITIES_V7_OUT_INIT_RXQ_NO_CONT_EV_WIDTH 113658#define MC_CMD_GET_CAPABILITIES_V7_OUT_INIT_RXQ_WITH_BUFFER_SIZE_OFST 2013659#define MC_CMD_GET_CAPABILITIES_V7_OUT_INIT_RXQ_WITH_BUFFER_SIZE_LBN 2713660#define MC_CMD_GET_CAPABILITIES_V7_OUT_INIT_RXQ_WITH_BUFFER_SIZE_WIDTH 113661#define MC_CMD_GET_CAPABILITIES_V7_OUT_BUNDLE_UPDATE_OFST 2013662#define MC_CMD_GET_CAPABILITIES_V7_OUT_BUNDLE_UPDATE_LBN 2813663#define MC_CMD_GET_CAPABILITIES_V7_OUT_BUNDLE_UPDATE_WIDTH 113664#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_V3_OFST 2013665#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_V3_LBN 2913666#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_V3_WIDTH 113667#define MC_CMD_GET_CAPABILITIES_V7_OUT_DYNAMIC_SENSORS_OFST 2013668#define MC_CMD_GET_CAPABILITIES_V7_OUT_DYNAMIC_SENSORS_LBN 3013669#define MC_CMD_GET_CAPABILITIES_V7_OUT_DYNAMIC_SENSORS_WIDTH 113670#define MC_CMD_GET_CAPABILITIES_V7_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_OFST 2013671#define MC_CMD_GET_CAPABILITIES_V7_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_LBN 3113672#define MC_CMD_GET_CAPABILITIES_V7_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_WIDTH 113673/* Number of FATSOv2 contexts per datapath supported by this NIC (when13674 * TX_TSO_V2 == 1). Not present on older firmware (check the length).13675 */13676#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_V2_N_CONTEXTS_OFST 2413677#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_V2_N_CONTEXTS_LEN 213678/* One byte per PF containing the number of the external port assigned to this13679 * PF, indexed by PF number. Special values indicate that a PF is either not13680 * present or not assigned.13681 */13682#define MC_CMD_GET_CAPABILITIES_V7_OUT_PFS_TO_PORTS_ASSIGNMENT_OFST 2613683#define MC_CMD_GET_CAPABILITIES_V7_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 113684#define MC_CMD_GET_CAPABILITIES_V7_OUT_PFS_TO_PORTS_ASSIGNMENT_NUM 1613685/* enum: The caller is not permitted to access information on this PF. */13686#define MC_CMD_GET_CAPABILITIES_V7_OUT_ACCESS_NOT_PERMITTED 0xff13687/* enum: PF does not exist. */13688#define MC_CMD_GET_CAPABILITIES_V7_OUT_PF_NOT_PRESENT 0xfe13689/* enum: PF does exist but is not assigned to any external port. */13690#define MC_CMD_GET_CAPABILITIES_V7_OUT_PF_NOT_ASSIGNED 0xfd13691/* enum: This value indicates that PF is assigned, but it cannot be expressed13692 * in this field. It is intended for a possible future situation where a more13693 * complex scheme of PFs to ports mapping is being used. The future driver13694 * should look for a new field supporting the new scheme. The current/old13695 * driver should treat this value as PF_NOT_ASSIGNED.13696 */13697#define MC_CMD_GET_CAPABILITIES_V7_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc13698/* One byte per PF containing the number of its VFs, indexed by PF number. A13699 * special value indicates that a PF is not present.13700 */13701#define MC_CMD_GET_CAPABILITIES_V7_OUT_NUM_VFS_PER_PF_OFST 4213702#define MC_CMD_GET_CAPABILITIES_V7_OUT_NUM_VFS_PER_PF_LEN 113703#define MC_CMD_GET_CAPABILITIES_V7_OUT_NUM_VFS_PER_PF_NUM 1613704/* enum: The caller is not permitted to access information on this PF. */13705/* MC_CMD_GET_CAPABILITIES_V7_OUT_ACCESS_NOT_PERMITTED 0xff */13706/* enum: PF does not exist. */13707/* MC_CMD_GET_CAPABILITIES_V7_OUT_PF_NOT_PRESENT 0xfe */13708/* Number of VIs available for each external port */13709#define MC_CMD_GET_CAPABILITIES_V7_OUT_NUM_VIS_PER_PORT_OFST 5813710#define MC_CMD_GET_CAPABILITIES_V7_OUT_NUM_VIS_PER_PORT_LEN 213711#define MC_CMD_GET_CAPABILITIES_V7_OUT_NUM_VIS_PER_PORT_NUM 413712/* Size of RX descriptor cache expressed as binary logarithm The actual size13713 * equals (2 ^ RX_DESC_CACHE_SIZE)13714 */13715#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_DESC_CACHE_SIZE_OFST 6613716#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_DESC_CACHE_SIZE_LEN 113717/* Size of TX descriptor cache expressed as binary logarithm The actual size13718 * equals (2 ^ TX_DESC_CACHE_SIZE)13719 */13720#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_DESC_CACHE_SIZE_OFST 6713721#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_DESC_CACHE_SIZE_LEN 113722/* Total number of available PIO buffers */13723#define MC_CMD_GET_CAPABILITIES_V7_OUT_NUM_PIO_BUFFS_OFST 6813724#define MC_CMD_GET_CAPABILITIES_V7_OUT_NUM_PIO_BUFFS_LEN 213725/* Size of a single PIO buffer */13726#define MC_CMD_GET_CAPABILITIES_V7_OUT_SIZE_PIO_BUFF_OFST 7013727#define MC_CMD_GET_CAPABILITIES_V7_OUT_SIZE_PIO_BUFF_LEN 213728/* On chips later than Medford the amount of address space assigned to each VI13729 * is configurable. This is a global setting that the driver must query to13730 * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available13731 * with 8k VI windows.13732 */13733#define MC_CMD_GET_CAPABILITIES_V7_OUT_VI_WINDOW_MODE_OFST 7213734#define MC_CMD_GET_CAPABILITIES_V7_OUT_VI_WINDOW_MODE_LEN 113735/* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k.13736 * CTPIO is not mapped.13737 */13738#define MC_CMD_GET_CAPABILITIES_V7_OUT_VI_WINDOW_MODE_8K 0x013739/* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */13740#define MC_CMD_GET_CAPABILITIES_V7_OUT_VI_WINDOW_MODE_16K 0x113741/* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */13742#define MC_CMD_GET_CAPABILITIES_V7_OUT_VI_WINDOW_MODE_64K 0x213743/* Number of vFIFOs per adapter that can be used for VFIFO Stuffing13744 * (SF-115995-SW) in the present configuration of firmware and port mode.13745 */13746#define MC_CMD_GET_CAPABILITIES_V7_OUT_VFIFO_STUFFING_NUM_VFIFOS_OFST 7313747#define MC_CMD_GET_CAPABILITIES_V7_OUT_VFIFO_STUFFING_NUM_VFIFOS_LEN 113748/* Number of buffers per adapter that can be used for VFIFO Stuffing13749 * (SF-115995-SW) in the present configuration of firmware and port mode.13750 */13751#define MC_CMD_GET_CAPABILITIES_V7_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_OFST 7413752#define MC_CMD_GET_CAPABILITIES_V7_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_LEN 213753/* Entry count in the MAC stats array, including the final GENERATION_END13754 * entry. For MAC stats DMA, drivers should allocate a buffer large enough to13755 * hold at least this many 64-bit stats values, if they wish to receive all13756 * available stats. If the buffer is shorter than MAC_STATS_NUM_STATS * 8, the13757 * stats array returned will be truncated.13758 */13759#define MC_CMD_GET_CAPABILITIES_V7_OUT_MAC_STATS_NUM_STATS_OFST 7613760#define MC_CMD_GET_CAPABILITIES_V7_OUT_MAC_STATS_NUM_STATS_LEN 213761/* Maximum supported value for MC_CMD_FILTER_OP_V3/MATCH_MARK_VALUE. This field13762 * will only be non-zero if MC_CMD_GET_CAPABILITIES/FILTER_ACTION_MARK is set.13763 */13764#define MC_CMD_GET_CAPABILITIES_V7_OUT_FILTER_ACTION_MARK_MAX_OFST 8013765#define MC_CMD_GET_CAPABILITIES_V7_OUT_FILTER_ACTION_MARK_MAX_LEN 413766/* On devices where the INIT_RXQ_WITH_BUFFER_SIZE flag (in13767 * GET_CAPABILITIES_OUT_V2) is set, drivers have to specify a buffer size when13768 * they create an RX queue. Due to hardware limitations, only a small number of13769 * different buffer sizes may be available concurrently. Nonzero entries in13770 * this array are the sizes of buffers which the system guarantees will be13771 * available for use. If the list is empty, there are no limitations on13772 * concurrent buffer sizes.13773 */13774#define MC_CMD_GET_CAPABILITIES_V7_OUT_GUARANTEED_RX_BUFFER_SIZES_OFST 8413775#define MC_CMD_GET_CAPABILITIES_V7_OUT_GUARANTEED_RX_BUFFER_SIZES_LEN 413776#define MC_CMD_GET_CAPABILITIES_V7_OUT_GUARANTEED_RX_BUFFER_SIZES_NUM 1613777/* Third word of flags. Not present on older firmware (check the length). */13778#define MC_CMD_GET_CAPABILITIES_V7_OUT_FLAGS3_OFST 14813779#define MC_CMD_GET_CAPABILITIES_V7_OUT_FLAGS3_LEN 413780#define MC_CMD_GET_CAPABILITIES_V7_OUT_WOL_ETHERWAKE_OFST 14813781#define MC_CMD_GET_CAPABILITIES_V7_OUT_WOL_ETHERWAKE_LBN 013782#define MC_CMD_GET_CAPABILITIES_V7_OUT_WOL_ETHERWAKE_WIDTH 113783#define MC_CMD_GET_CAPABILITIES_V7_OUT_RSS_EVEN_SPREADING_OFST 14813784#define MC_CMD_GET_CAPABILITIES_V7_OUT_RSS_EVEN_SPREADING_LBN 113785#define MC_CMD_GET_CAPABILITIES_V7_OUT_RSS_EVEN_SPREADING_WIDTH 113786#define MC_CMD_GET_CAPABILITIES_V7_OUT_RSS_SELECTABLE_TABLE_SIZE_OFST 14813787#define MC_CMD_GET_CAPABILITIES_V7_OUT_RSS_SELECTABLE_TABLE_SIZE_LBN 213788#define MC_CMD_GET_CAPABILITIES_V7_OUT_RSS_SELECTABLE_TABLE_SIZE_WIDTH 113789#define MC_CMD_GET_CAPABILITIES_V7_OUT_MAE_SUPPORTED_OFST 14813790#define MC_CMD_GET_CAPABILITIES_V7_OUT_MAE_SUPPORTED_LBN 313791#define MC_CMD_GET_CAPABILITIES_V7_OUT_MAE_SUPPORTED_WIDTH 113792#define MC_CMD_GET_CAPABILITIES_V7_OUT_VDPA_SUPPORTED_OFST 14813793#define MC_CMD_GET_CAPABILITIES_V7_OUT_VDPA_SUPPORTED_LBN 413794#define MC_CMD_GET_CAPABILITIES_V7_OUT_VDPA_SUPPORTED_WIDTH 113795#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_OFST 14813796#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_LBN 513797#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_WIDTH 113798#define MC_CMD_GET_CAPABILITIES_V7_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_OFST 14813799#define MC_CMD_GET_CAPABILITIES_V7_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_LBN 613800#define MC_CMD_GET_CAPABILITIES_V7_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_WIDTH 113801#define MC_CMD_GET_CAPABILITIES_V7_OUT_UNSOL_EV_CREDIT_SUPPORTED_OFST 14813802#define MC_CMD_GET_CAPABILITIES_V7_OUT_UNSOL_EV_CREDIT_SUPPORTED_LBN 713803#define MC_CMD_GET_CAPABILITIES_V7_OUT_UNSOL_EV_CREDIT_SUPPORTED_WIDTH 113804 13805/* MC_CMD_GET_CAPABILITIES_V8_OUT msgresponse */13806#define MC_CMD_GET_CAPABILITIES_V8_OUT_LEN 16013807/* First word of flags. */13808#define MC_CMD_GET_CAPABILITIES_V8_OUT_FLAGS1_OFST 013809#define MC_CMD_GET_CAPABILITIES_V8_OUT_FLAGS1_LEN 413810#define MC_CMD_GET_CAPABILITIES_V8_OUT_VPORT_RECONFIGURE_OFST 013811#define MC_CMD_GET_CAPABILITIES_V8_OUT_VPORT_RECONFIGURE_LBN 313812#define MC_CMD_GET_CAPABILITIES_V8_OUT_VPORT_RECONFIGURE_WIDTH 113813#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_STRIPING_OFST 013814#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_STRIPING_LBN 413815#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_STRIPING_WIDTH 113816#define MC_CMD_GET_CAPABILITIES_V8_OUT_VADAPTOR_QUERY_OFST 013817#define MC_CMD_GET_CAPABILITIES_V8_OUT_VADAPTOR_QUERY_LBN 513818#define MC_CMD_GET_CAPABILITIES_V8_OUT_VADAPTOR_QUERY_WIDTH 113819#define MC_CMD_GET_CAPABILITIES_V8_OUT_EVB_PORT_VLAN_RESTRICT_OFST 013820#define MC_CMD_GET_CAPABILITIES_V8_OUT_EVB_PORT_VLAN_RESTRICT_LBN 613821#define MC_CMD_GET_CAPABILITIES_V8_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 113822#define MC_CMD_GET_CAPABILITIES_V8_OUT_DRV_ATTACH_PREBOOT_OFST 013823#define MC_CMD_GET_CAPABILITIES_V8_OUT_DRV_ATTACH_PREBOOT_LBN 713824#define MC_CMD_GET_CAPABILITIES_V8_OUT_DRV_ATTACH_PREBOOT_WIDTH 113825#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_FORCE_EVENT_MERGING_OFST 013826#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_FORCE_EVENT_MERGING_LBN 813827#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_FORCE_EVENT_MERGING_WIDTH 113828#define MC_CMD_GET_CAPABILITIES_V8_OUT_SET_MAC_ENHANCED_OFST 013829#define MC_CMD_GET_CAPABILITIES_V8_OUT_SET_MAC_ENHANCED_LBN 913830#define MC_CMD_GET_CAPABILITIES_V8_OUT_SET_MAC_ENHANCED_WIDTH 113831#define MC_CMD_GET_CAPABILITIES_V8_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 013832#define MC_CMD_GET_CAPABILITIES_V8_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 1013833#define MC_CMD_GET_CAPABILITIES_V8_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 113834#define MC_CMD_GET_CAPABILITIES_V8_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 013835#define MC_CMD_GET_CAPABILITIES_V8_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 1113836#define MC_CMD_GET_CAPABILITIES_V8_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 113837#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_MAC_SECURITY_FILTERING_OFST 013838#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_MAC_SECURITY_FILTERING_LBN 1213839#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 113840#define MC_CMD_GET_CAPABILITIES_V8_OUT_ADDITIONAL_RSS_MODES_OFST 013841#define MC_CMD_GET_CAPABILITIES_V8_OUT_ADDITIONAL_RSS_MODES_LBN 1313842#define MC_CMD_GET_CAPABILITIES_V8_OUT_ADDITIONAL_RSS_MODES_WIDTH 113843#define MC_CMD_GET_CAPABILITIES_V8_OUT_QBB_OFST 013844#define MC_CMD_GET_CAPABILITIES_V8_OUT_QBB_LBN 1413845#define MC_CMD_GET_CAPABILITIES_V8_OUT_QBB_WIDTH 113846#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 013847#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 1513848#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 113849#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_RSS_LIMITED_OFST 013850#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_RSS_LIMITED_LBN 1613851#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_RSS_LIMITED_WIDTH 113852#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_PACKED_STREAM_OFST 013853#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_PACKED_STREAM_LBN 1713854#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_PACKED_STREAM_WIDTH 113855#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_INCLUDE_FCS_OFST 013856#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_INCLUDE_FCS_LBN 1813857#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_INCLUDE_FCS_WIDTH 113858#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_VLAN_INSERTION_OFST 013859#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_VLAN_INSERTION_LBN 1913860#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_VLAN_INSERTION_WIDTH 113861#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_VLAN_STRIPPING_OFST 013862#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_VLAN_STRIPPING_LBN 2013863#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_VLAN_STRIPPING_WIDTH 113864#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_OFST 013865#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_LBN 2113866#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_WIDTH 113867#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_PREFIX_LEN_0_OFST 013868#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_PREFIX_LEN_0_LBN 2213869#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_PREFIX_LEN_0_WIDTH 113870#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_PREFIX_LEN_14_OFST 013871#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_PREFIX_LEN_14_LBN 2313872#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_PREFIX_LEN_14_WIDTH 113873#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_TIMESTAMP_OFST 013874#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_TIMESTAMP_LBN 2413875#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_TIMESTAMP_WIDTH 113876#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_BATCHING_OFST 013877#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_BATCHING_LBN 2513878#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_BATCHING_WIDTH 113879#define MC_CMD_GET_CAPABILITIES_V8_OUT_MCAST_FILTER_CHAINING_OFST 013880#define MC_CMD_GET_CAPABILITIES_V8_OUT_MCAST_FILTER_CHAINING_LBN 2613881#define MC_CMD_GET_CAPABILITIES_V8_OUT_MCAST_FILTER_CHAINING_WIDTH 113882#define MC_CMD_GET_CAPABILITIES_V8_OUT_PM_AND_RXDP_COUNTERS_OFST 013883#define MC_CMD_GET_CAPABILITIES_V8_OUT_PM_AND_RXDP_COUNTERS_LBN 2713884#define MC_CMD_GET_CAPABILITIES_V8_OUT_PM_AND_RXDP_COUNTERS_WIDTH 113885#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_DISABLE_SCATTER_OFST 013886#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_DISABLE_SCATTER_LBN 2813887#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_DISABLE_SCATTER_WIDTH 113888#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_MCAST_UDP_LOOPBACK_OFST 013889#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_MCAST_UDP_LOOPBACK_LBN 2913890#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 113891#define MC_CMD_GET_CAPABILITIES_V8_OUT_EVB_OFST 013892#define MC_CMD_GET_CAPABILITIES_V8_OUT_EVB_LBN 3013893#define MC_CMD_GET_CAPABILITIES_V8_OUT_EVB_WIDTH 113894#define MC_CMD_GET_CAPABILITIES_V8_OUT_VXLAN_NVGRE_OFST 013895#define MC_CMD_GET_CAPABILITIES_V8_OUT_VXLAN_NVGRE_LBN 3113896#define MC_CMD_GET_CAPABILITIES_V8_OUT_VXLAN_NVGRE_WIDTH 113897/* RxDPCPU firmware id. */13898#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_DPCPU_FW_ID_OFST 413899#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_DPCPU_FW_ID_LEN 213900/* enum: Standard RXDP firmware */13901#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP 0x013902/* enum: Low latency RXDP firmware */13903#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_LOW_LATENCY 0x113904/* enum: Packed stream RXDP firmware */13905#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_PACKED_STREAM 0x213906/* enum: Rules engine RXDP firmware */13907#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_RULES_ENGINE 0x513908/* enum: DPDK RXDP firmware */13909#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_DPDK 0x613910/* enum: BIST RXDP firmware */13911#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_BIST 0x10a13912/* enum: RXDP Test firmware image 1 */13913#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x10113914/* enum: RXDP Test firmware image 2 */13915#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x10213916/* enum: RXDP Test firmware image 3 */13917#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x10313918/* enum: RXDP Test firmware image 4 */13919#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x10413920/* enum: RXDP Test firmware image 5 */13921#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_BACKPRESSURE 0x10513922/* enum: RXDP Test firmware image 6 */13923#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_FW_PACKET_EDITS 0x10613924/* enum: RXDP Test firmware image 7 */13925#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x10713926/* enum: RXDP Test firmware image 8 */13927#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_FW_DISABLE_DL 0x10813928/* enum: RXDP Test firmware image 9 */13929#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b13930/* enum: RXDP Test firmware image 10 */13931#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_FW_SLOW 0x10c13932/* TxDPCPU firmware id. */13933#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_DPCPU_FW_ID_OFST 613934#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_DPCPU_FW_ID_LEN 213935/* enum: Standard TXDP firmware */13936#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXDP 0x013937/* enum: Low latency TXDP firmware */13938#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXDP_LOW_LATENCY 0x113939/* enum: High packet rate TXDP firmware */13940#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXDP_HIGH_PACKET_RATE 0x313941/* enum: Rules engine TXDP firmware */13942#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXDP_RULES_ENGINE 0x513943/* enum: DPDK TXDP firmware */13944#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXDP_DPDK 0x613945/* enum: BIST TXDP firmware */13946#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXDP_BIST 0x12d13947/* enum: TXDP Test firmware image 1 */13948#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXDP_TEST_FW_TSO_EDIT 0x10113949/* enum: TXDP Test firmware image 2 */13950#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXDP_TEST_FW_PACKET_EDITS 0x10213951/* enum: TXDP CSR bus test firmware */13952#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXDP_TEST_FW_CSR 0x10313953#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_VERSION_OFST 813954#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_VERSION_LEN 213955#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_VERSION_REV_OFST 813956#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_VERSION_REV_LBN 013957#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_VERSION_REV_WIDTH 1213958#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_VERSION_TYPE_OFST 813959#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_VERSION_TYPE_LBN 1213960#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_VERSION_TYPE_WIDTH 413961/* enum: reserved value - do not use (may indicate alternative interpretation13962 * of REV field in future)13963 */13964#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_RESERVED 0x013965/* enum: Trivial RX PD firmware for early Huntington development (Huntington13966 * development only)13967 */13968#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_FIRST_PKT 0x113969/* enum: RX PD firmware for telemetry prototyping (Medford2 development only)13970 */13971#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x113972/* enum: RX PD firmware with approximately Siena-compatible behaviour13973 * (Huntington development only)13974 */13975#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x213976/* enum: Full featured RX PD production firmware */13977#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x313978/* enum: (deprecated original name for the FULL_FEATURED variant) */13979#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_VSWITCH 0x313980/* enum: siena_compat variant RX PD firmware using PM rather than MAC13981 * (Huntington development only)13982 */13983#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x413984/* enum: Low latency RX PD production firmware */13985#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x513986/* enum: Packed stream RX PD production firmware */13987#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x613988/* enum: RX PD firmware handling layer 2 only for high packet rate performance13989 * tests (Medford development only)13990 */13991#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x713992/* enum: Rules engine RX PD production firmware */13993#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x813994/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */13995#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_L3XUDP 0x913996/* enum: DPDK RX PD production firmware */13997#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_DPDK 0xa13998/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */13999#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe14000/* enum: RX PD firmware parsing but not filtering network overlay tunnel14001 * encapsulations (Medford development only)14002 */14003#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf14004#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_VERSION_OFST 1014005#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_VERSION_LEN 214006#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_VERSION_REV_OFST 1014007#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_VERSION_REV_LBN 014008#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_VERSION_REV_WIDTH 1214009#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_VERSION_TYPE_OFST 1014010#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_VERSION_TYPE_LBN 1214011#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_VERSION_TYPE_WIDTH 414012/* enum: reserved value - do not use (may indicate alternative interpretation14013 * of REV field in future)14014 */14015#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_RESERVED 0x014016/* enum: Trivial TX PD firmware for early Huntington development (Huntington14017 * development only)14018 */14019#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_FIRST_PKT 0x114020/* enum: TX PD firmware for telemetry prototyping (Medford2 development only)14021 */14022#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x114023/* enum: TX PD firmware with approximately Siena-compatible behaviour14024 * (Huntington development only)14025 */14026#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x214027/* enum: Full featured TX PD production firmware */14028#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x314029/* enum: (deprecated original name for the FULL_FEATURED variant) */14030#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_VSWITCH 0x314031/* enum: siena_compat variant TX PD firmware using PM rather than MAC14032 * (Huntington development only)14033 */14034#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x414035#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */14036/* enum: TX PD firmware handling layer 2 only for high packet rate performance14037 * tests (Medford development only)14038 */14039#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x714040/* enum: Rules engine TX PD production firmware */14041#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x814042/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */14043#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_L3XUDP 0x914044/* enum: DPDK TX PD production firmware */14045#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_DPDK 0xa14046/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */14047#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe14048/* Hardware capabilities of NIC */14049#define MC_CMD_GET_CAPABILITIES_V8_OUT_HW_CAPABILITIES_OFST 1214050#define MC_CMD_GET_CAPABILITIES_V8_OUT_HW_CAPABILITIES_LEN 414051/* Licensed capabilities */14052#define MC_CMD_GET_CAPABILITIES_V8_OUT_LICENSE_CAPABILITIES_OFST 1614053#define MC_CMD_GET_CAPABILITIES_V8_OUT_LICENSE_CAPABILITIES_LEN 414054/* Second word of flags. Not present on older firmware (check the length). */14055#define MC_CMD_GET_CAPABILITIES_V8_OUT_FLAGS2_OFST 2014056#define MC_CMD_GET_CAPABILITIES_V8_OUT_FLAGS2_LEN 414057#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_V2_OFST 2014058#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_V2_LBN 014059#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_V2_WIDTH 114060#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_V2_ENCAP_OFST 2014061#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_V2_ENCAP_LBN 114062#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_V2_ENCAP_WIDTH 114063#define MC_CMD_GET_CAPABILITIES_V8_OUT_EVQ_TIMER_CTRL_OFST 2014064#define MC_CMD_GET_CAPABILITIES_V8_OUT_EVQ_TIMER_CTRL_LBN 214065#define MC_CMD_GET_CAPABILITIES_V8_OUT_EVQ_TIMER_CTRL_WIDTH 114066#define MC_CMD_GET_CAPABILITIES_V8_OUT_EVENT_CUT_THROUGH_OFST 2014067#define MC_CMD_GET_CAPABILITIES_V8_OUT_EVENT_CUT_THROUGH_LBN 314068#define MC_CMD_GET_CAPABILITIES_V8_OUT_EVENT_CUT_THROUGH_WIDTH 114069#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_CUT_THROUGH_OFST 2014070#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_CUT_THROUGH_LBN 414071#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_CUT_THROUGH_WIDTH 114072#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_VFIFO_ULL_MODE_OFST 2014073#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_VFIFO_ULL_MODE_LBN 514074#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_VFIFO_ULL_MODE_WIDTH 114075#define MC_CMD_GET_CAPABILITIES_V8_OUT_MAC_STATS_40G_TX_SIZE_BINS_OFST 2014076#define MC_CMD_GET_CAPABILITIES_V8_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 614077#define MC_CMD_GET_CAPABILITIES_V8_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 114078#define MC_CMD_GET_CAPABILITIES_V8_OUT_INIT_EVQ_TYPE_SUPPORTED_OFST 2014079#define MC_CMD_GET_CAPABILITIES_V8_OUT_INIT_EVQ_TYPE_SUPPORTED_LBN 714080#define MC_CMD_GET_CAPABILITIES_V8_OUT_INIT_EVQ_TYPE_SUPPORTED_WIDTH 114081#define MC_CMD_GET_CAPABILITIES_V8_OUT_INIT_EVQ_V2_OFST 2014082#define MC_CMD_GET_CAPABILITIES_V8_OUT_INIT_EVQ_V2_LBN 714083#define MC_CMD_GET_CAPABILITIES_V8_OUT_INIT_EVQ_V2_WIDTH 114084#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_MAC_TIMESTAMPING_OFST 2014085#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_MAC_TIMESTAMPING_LBN 814086#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_MAC_TIMESTAMPING_WIDTH 114087#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TIMESTAMP_OFST 2014088#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TIMESTAMP_LBN 914089#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TIMESTAMP_WIDTH 114090#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_SNIFF_OFST 2014091#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_SNIFF_LBN 1014092#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_SNIFF_WIDTH 114093#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_SNIFF_OFST 2014094#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_SNIFF_LBN 1114095#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_SNIFF_WIDTH 114096#define MC_CMD_GET_CAPABILITIES_V8_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_OFST 2014097#define MC_CMD_GET_CAPABILITIES_V8_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_LBN 1214098#define MC_CMD_GET_CAPABILITIES_V8_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 114099#define MC_CMD_GET_CAPABILITIES_V8_OUT_MCDI_BACKGROUND_OFST 2014100#define MC_CMD_GET_CAPABILITIES_V8_OUT_MCDI_BACKGROUND_LBN 1314101#define MC_CMD_GET_CAPABILITIES_V8_OUT_MCDI_BACKGROUND_WIDTH 114102#define MC_CMD_GET_CAPABILITIES_V8_OUT_MCDI_DB_RETURN_OFST 2014103#define MC_CMD_GET_CAPABILITIES_V8_OUT_MCDI_DB_RETURN_LBN 1414104#define MC_CMD_GET_CAPABILITIES_V8_OUT_MCDI_DB_RETURN_WIDTH 114105#define MC_CMD_GET_CAPABILITIES_V8_OUT_CTPIO_OFST 2014106#define MC_CMD_GET_CAPABILITIES_V8_OUT_CTPIO_LBN 1514107#define MC_CMD_GET_CAPABILITIES_V8_OUT_CTPIO_WIDTH 114108#define MC_CMD_GET_CAPABILITIES_V8_OUT_TSA_SUPPORT_OFST 2014109#define MC_CMD_GET_CAPABILITIES_V8_OUT_TSA_SUPPORT_LBN 1614110#define MC_CMD_GET_CAPABILITIES_V8_OUT_TSA_SUPPORT_WIDTH 114111#define MC_CMD_GET_CAPABILITIES_V8_OUT_TSA_BOUND_OFST 2014112#define MC_CMD_GET_CAPABILITIES_V8_OUT_TSA_BOUND_LBN 1714113#define MC_CMD_GET_CAPABILITIES_V8_OUT_TSA_BOUND_WIDTH 114114#define MC_CMD_GET_CAPABILITIES_V8_OUT_SF_ADAPTER_AUTHENTICATION_OFST 2014115#define MC_CMD_GET_CAPABILITIES_V8_OUT_SF_ADAPTER_AUTHENTICATION_LBN 1814116#define MC_CMD_GET_CAPABILITIES_V8_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 114117#define MC_CMD_GET_CAPABILITIES_V8_OUT_FILTER_ACTION_FLAG_OFST 2014118#define MC_CMD_GET_CAPABILITIES_V8_OUT_FILTER_ACTION_FLAG_LBN 1914119#define MC_CMD_GET_CAPABILITIES_V8_OUT_FILTER_ACTION_FLAG_WIDTH 114120#define MC_CMD_GET_CAPABILITIES_V8_OUT_FILTER_ACTION_MARK_OFST 2014121#define MC_CMD_GET_CAPABILITIES_V8_OUT_FILTER_ACTION_MARK_LBN 2014122#define MC_CMD_GET_CAPABILITIES_V8_OUT_FILTER_ACTION_MARK_WIDTH 114123#define MC_CMD_GET_CAPABILITIES_V8_OUT_EQUAL_STRIDE_SUPER_BUFFER_OFST 2014124#define MC_CMD_GET_CAPABILITIES_V8_OUT_EQUAL_STRIDE_SUPER_BUFFER_LBN 2114125#define MC_CMD_GET_CAPABILITIES_V8_OUT_EQUAL_STRIDE_SUPER_BUFFER_WIDTH 114126#define MC_CMD_GET_CAPABILITIES_V8_OUT_EQUAL_STRIDE_PACKED_STREAM_OFST 2014127#define MC_CMD_GET_CAPABILITIES_V8_OUT_EQUAL_STRIDE_PACKED_STREAM_LBN 2114128#define MC_CMD_GET_CAPABILITIES_V8_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 114129#define MC_CMD_GET_CAPABILITIES_V8_OUT_L3XUDP_SUPPORT_OFST 2014130#define MC_CMD_GET_CAPABILITIES_V8_OUT_L3XUDP_SUPPORT_LBN 2214131#define MC_CMD_GET_CAPABILITIES_V8_OUT_L3XUDP_SUPPORT_WIDTH 114132#define MC_CMD_GET_CAPABILITIES_V8_OUT_FW_SUBVARIANT_NO_TX_CSUM_OFST 2014133#define MC_CMD_GET_CAPABILITIES_V8_OUT_FW_SUBVARIANT_NO_TX_CSUM_LBN 2314134#define MC_CMD_GET_CAPABILITIES_V8_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 114135#define MC_CMD_GET_CAPABILITIES_V8_OUT_VI_SPREADING_OFST 2014136#define MC_CMD_GET_CAPABILITIES_V8_OUT_VI_SPREADING_LBN 2414137#define MC_CMD_GET_CAPABILITIES_V8_OUT_VI_SPREADING_WIDTH 114138#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_HLB_IDLE_OFST 2014139#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_HLB_IDLE_LBN 2514140#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_HLB_IDLE_WIDTH 114141#define MC_CMD_GET_CAPABILITIES_V8_OUT_INIT_RXQ_NO_CONT_EV_OFST 2014142#define MC_CMD_GET_CAPABILITIES_V8_OUT_INIT_RXQ_NO_CONT_EV_LBN 2614143#define MC_CMD_GET_CAPABILITIES_V8_OUT_INIT_RXQ_NO_CONT_EV_WIDTH 114144#define MC_CMD_GET_CAPABILITIES_V8_OUT_INIT_RXQ_WITH_BUFFER_SIZE_OFST 2014145#define MC_CMD_GET_CAPABILITIES_V8_OUT_INIT_RXQ_WITH_BUFFER_SIZE_LBN 2714146#define MC_CMD_GET_CAPABILITIES_V8_OUT_INIT_RXQ_WITH_BUFFER_SIZE_WIDTH 114147#define MC_CMD_GET_CAPABILITIES_V8_OUT_BUNDLE_UPDATE_OFST 2014148#define MC_CMD_GET_CAPABILITIES_V8_OUT_BUNDLE_UPDATE_LBN 2814149#define MC_CMD_GET_CAPABILITIES_V8_OUT_BUNDLE_UPDATE_WIDTH 114150#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_V3_OFST 2014151#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_V3_LBN 2914152#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_V3_WIDTH 114153#define MC_CMD_GET_CAPABILITIES_V8_OUT_DYNAMIC_SENSORS_OFST 2014154#define MC_CMD_GET_CAPABILITIES_V8_OUT_DYNAMIC_SENSORS_LBN 3014155#define MC_CMD_GET_CAPABILITIES_V8_OUT_DYNAMIC_SENSORS_WIDTH 114156#define MC_CMD_GET_CAPABILITIES_V8_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_OFST 2014157#define MC_CMD_GET_CAPABILITIES_V8_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_LBN 3114158#define MC_CMD_GET_CAPABILITIES_V8_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_WIDTH 114159/* Number of FATSOv2 contexts per datapath supported by this NIC (when14160 * TX_TSO_V2 == 1). Not present on older firmware (check the length).14161 */14162#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_V2_N_CONTEXTS_OFST 2414163#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_V2_N_CONTEXTS_LEN 214164/* One byte per PF containing the number of the external port assigned to this14165 * PF, indexed by PF number. Special values indicate that a PF is either not14166 * present or not assigned.14167 */14168#define MC_CMD_GET_CAPABILITIES_V8_OUT_PFS_TO_PORTS_ASSIGNMENT_OFST 2614169#define MC_CMD_GET_CAPABILITIES_V8_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 114170#define MC_CMD_GET_CAPABILITIES_V8_OUT_PFS_TO_PORTS_ASSIGNMENT_NUM 1614171/* enum: The caller is not permitted to access information on this PF. */14172#define MC_CMD_GET_CAPABILITIES_V8_OUT_ACCESS_NOT_PERMITTED 0xff14173/* enum: PF does not exist. */14174#define MC_CMD_GET_CAPABILITIES_V8_OUT_PF_NOT_PRESENT 0xfe14175/* enum: PF does exist but is not assigned to any external port. */14176#define MC_CMD_GET_CAPABILITIES_V8_OUT_PF_NOT_ASSIGNED 0xfd14177/* enum: This value indicates that PF is assigned, but it cannot be expressed14178 * in this field. It is intended for a possible future situation where a more14179 * complex scheme of PFs to ports mapping is being used. The future driver14180 * should look for a new field supporting the new scheme. The current/old14181 * driver should treat this value as PF_NOT_ASSIGNED.14182 */14183#define MC_CMD_GET_CAPABILITIES_V8_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc14184/* One byte per PF containing the number of its VFs, indexed by PF number. A14185 * special value indicates that a PF is not present.14186 */14187#define MC_CMD_GET_CAPABILITIES_V8_OUT_NUM_VFS_PER_PF_OFST 4214188#define MC_CMD_GET_CAPABILITIES_V8_OUT_NUM_VFS_PER_PF_LEN 114189#define MC_CMD_GET_CAPABILITIES_V8_OUT_NUM_VFS_PER_PF_NUM 1614190/* enum: The caller is not permitted to access information on this PF. */14191/* MC_CMD_GET_CAPABILITIES_V8_OUT_ACCESS_NOT_PERMITTED 0xff */14192/* enum: PF does not exist. */14193/* MC_CMD_GET_CAPABILITIES_V8_OUT_PF_NOT_PRESENT 0xfe */14194/* Number of VIs available for each external port */14195#define MC_CMD_GET_CAPABILITIES_V8_OUT_NUM_VIS_PER_PORT_OFST 5814196#define MC_CMD_GET_CAPABILITIES_V8_OUT_NUM_VIS_PER_PORT_LEN 214197#define MC_CMD_GET_CAPABILITIES_V8_OUT_NUM_VIS_PER_PORT_NUM 414198/* Size of RX descriptor cache expressed as binary logarithm The actual size14199 * equals (2 ^ RX_DESC_CACHE_SIZE)14200 */14201#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_DESC_CACHE_SIZE_OFST 6614202#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_DESC_CACHE_SIZE_LEN 114203/* Size of TX descriptor cache expressed as binary logarithm The actual size14204 * equals (2 ^ TX_DESC_CACHE_SIZE)14205 */14206#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_DESC_CACHE_SIZE_OFST 6714207#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_DESC_CACHE_SIZE_LEN 114208/* Total number of available PIO buffers */14209#define MC_CMD_GET_CAPABILITIES_V8_OUT_NUM_PIO_BUFFS_OFST 6814210#define MC_CMD_GET_CAPABILITIES_V8_OUT_NUM_PIO_BUFFS_LEN 214211/* Size of a single PIO buffer */14212#define MC_CMD_GET_CAPABILITIES_V8_OUT_SIZE_PIO_BUFF_OFST 7014213#define MC_CMD_GET_CAPABILITIES_V8_OUT_SIZE_PIO_BUFF_LEN 214214/* On chips later than Medford the amount of address space assigned to each VI14215 * is configurable. This is a global setting that the driver must query to14216 * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available14217 * with 8k VI windows.14218 */14219#define MC_CMD_GET_CAPABILITIES_V8_OUT_VI_WINDOW_MODE_OFST 7214220#define MC_CMD_GET_CAPABILITIES_V8_OUT_VI_WINDOW_MODE_LEN 114221/* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k.14222 * CTPIO is not mapped.14223 */14224#define MC_CMD_GET_CAPABILITIES_V8_OUT_VI_WINDOW_MODE_8K 0x014225/* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */14226#define MC_CMD_GET_CAPABILITIES_V8_OUT_VI_WINDOW_MODE_16K 0x114227/* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */14228#define MC_CMD_GET_CAPABILITIES_V8_OUT_VI_WINDOW_MODE_64K 0x214229/* Number of vFIFOs per adapter that can be used for VFIFO Stuffing14230 * (SF-115995-SW) in the present configuration of firmware and port mode.14231 */14232#define MC_CMD_GET_CAPABILITIES_V8_OUT_VFIFO_STUFFING_NUM_VFIFOS_OFST 7314233#define MC_CMD_GET_CAPABILITIES_V8_OUT_VFIFO_STUFFING_NUM_VFIFOS_LEN 114234/* Number of buffers per adapter that can be used for VFIFO Stuffing14235 * (SF-115995-SW) in the present configuration of firmware and port mode.14236 */14237#define MC_CMD_GET_CAPABILITIES_V8_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_OFST 7414238#define MC_CMD_GET_CAPABILITIES_V8_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_LEN 214239/* Entry count in the MAC stats array, including the final GENERATION_END14240 * entry. For MAC stats DMA, drivers should allocate a buffer large enough to14241 * hold at least this many 64-bit stats values, if they wish to receive all14242 * available stats. If the buffer is shorter than MAC_STATS_NUM_STATS * 8, the14243 * stats array returned will be truncated.14244 */14245#define MC_CMD_GET_CAPABILITIES_V8_OUT_MAC_STATS_NUM_STATS_OFST 7614246#define MC_CMD_GET_CAPABILITIES_V8_OUT_MAC_STATS_NUM_STATS_LEN 214247/* Maximum supported value for MC_CMD_FILTER_OP_V3/MATCH_MARK_VALUE. This field14248 * will only be non-zero if MC_CMD_GET_CAPABILITIES/FILTER_ACTION_MARK is set.14249 */14250#define MC_CMD_GET_CAPABILITIES_V8_OUT_FILTER_ACTION_MARK_MAX_OFST 8014251#define MC_CMD_GET_CAPABILITIES_V8_OUT_FILTER_ACTION_MARK_MAX_LEN 414252/* On devices where the INIT_RXQ_WITH_BUFFER_SIZE flag (in14253 * GET_CAPABILITIES_OUT_V2) is set, drivers have to specify a buffer size when14254 * they create an RX queue. Due to hardware limitations, only a small number of14255 * different buffer sizes may be available concurrently. Nonzero entries in14256 * this array are the sizes of buffers which the system guarantees will be14257 * available for use. If the list is empty, there are no limitations on14258 * concurrent buffer sizes.14259 */14260#define MC_CMD_GET_CAPABILITIES_V8_OUT_GUARANTEED_RX_BUFFER_SIZES_OFST 8414261#define MC_CMD_GET_CAPABILITIES_V8_OUT_GUARANTEED_RX_BUFFER_SIZES_LEN 414262#define MC_CMD_GET_CAPABILITIES_V8_OUT_GUARANTEED_RX_BUFFER_SIZES_NUM 1614263/* Third word of flags. Not present on older firmware (check the length). */14264#define MC_CMD_GET_CAPABILITIES_V8_OUT_FLAGS3_OFST 14814265#define MC_CMD_GET_CAPABILITIES_V8_OUT_FLAGS3_LEN 414266#define MC_CMD_GET_CAPABILITIES_V8_OUT_WOL_ETHERWAKE_OFST 14814267#define MC_CMD_GET_CAPABILITIES_V8_OUT_WOL_ETHERWAKE_LBN 014268#define MC_CMD_GET_CAPABILITIES_V8_OUT_WOL_ETHERWAKE_WIDTH 114269#define MC_CMD_GET_CAPABILITIES_V8_OUT_RSS_EVEN_SPREADING_OFST 14814270#define MC_CMD_GET_CAPABILITIES_V8_OUT_RSS_EVEN_SPREADING_LBN 114271#define MC_CMD_GET_CAPABILITIES_V8_OUT_RSS_EVEN_SPREADING_WIDTH 114272#define MC_CMD_GET_CAPABILITIES_V8_OUT_RSS_SELECTABLE_TABLE_SIZE_OFST 14814273#define MC_CMD_GET_CAPABILITIES_V8_OUT_RSS_SELECTABLE_TABLE_SIZE_LBN 214274#define MC_CMD_GET_CAPABILITIES_V8_OUT_RSS_SELECTABLE_TABLE_SIZE_WIDTH 114275#define MC_CMD_GET_CAPABILITIES_V8_OUT_MAE_SUPPORTED_OFST 14814276#define MC_CMD_GET_CAPABILITIES_V8_OUT_MAE_SUPPORTED_LBN 314277#define MC_CMD_GET_CAPABILITIES_V8_OUT_MAE_SUPPORTED_WIDTH 114278#define MC_CMD_GET_CAPABILITIES_V8_OUT_VDPA_SUPPORTED_OFST 14814279#define MC_CMD_GET_CAPABILITIES_V8_OUT_VDPA_SUPPORTED_LBN 414280#define MC_CMD_GET_CAPABILITIES_V8_OUT_VDPA_SUPPORTED_WIDTH 114281#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_OFST 14814282#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_LBN 514283#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_WIDTH 114284#define MC_CMD_GET_CAPABILITIES_V8_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_OFST 14814285#define MC_CMD_GET_CAPABILITIES_V8_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_LBN 614286#define MC_CMD_GET_CAPABILITIES_V8_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_WIDTH 114287#define MC_CMD_GET_CAPABILITIES_V8_OUT_UNSOL_EV_CREDIT_SUPPORTED_OFST 14814288#define MC_CMD_GET_CAPABILITIES_V8_OUT_UNSOL_EV_CREDIT_SUPPORTED_LBN 714289#define MC_CMD_GET_CAPABILITIES_V8_OUT_UNSOL_EV_CREDIT_SUPPORTED_WIDTH 114290/* These bits are reserved for communicating test-specific capabilities to14291 * host-side test software. All production drivers should treat this field as14292 * opaque.14293 */14294#define MC_CMD_GET_CAPABILITIES_V8_OUT_TEST_RESERVED_OFST 15214295#define MC_CMD_GET_CAPABILITIES_V8_OUT_TEST_RESERVED_LEN 814296#define MC_CMD_GET_CAPABILITIES_V8_OUT_TEST_RESERVED_LO_OFST 15214297#define MC_CMD_GET_CAPABILITIES_V8_OUT_TEST_RESERVED_HI_OFST 15614298 14299/* MC_CMD_GET_CAPABILITIES_V9_OUT msgresponse */14300#define MC_CMD_GET_CAPABILITIES_V9_OUT_LEN 18414301/* First word of flags. */14302#define MC_CMD_GET_CAPABILITIES_V9_OUT_FLAGS1_OFST 014303#define MC_CMD_GET_CAPABILITIES_V9_OUT_FLAGS1_LEN 414304#define MC_CMD_GET_CAPABILITIES_V9_OUT_VPORT_RECONFIGURE_OFST 014305#define MC_CMD_GET_CAPABILITIES_V9_OUT_VPORT_RECONFIGURE_LBN 314306#define MC_CMD_GET_CAPABILITIES_V9_OUT_VPORT_RECONFIGURE_WIDTH 114307#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_STRIPING_OFST 014308#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_STRIPING_LBN 414309#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_STRIPING_WIDTH 114310#define MC_CMD_GET_CAPABILITIES_V9_OUT_VADAPTOR_QUERY_OFST 014311#define MC_CMD_GET_CAPABILITIES_V9_OUT_VADAPTOR_QUERY_LBN 514312#define MC_CMD_GET_CAPABILITIES_V9_OUT_VADAPTOR_QUERY_WIDTH 114313#define MC_CMD_GET_CAPABILITIES_V9_OUT_EVB_PORT_VLAN_RESTRICT_OFST 014314#define MC_CMD_GET_CAPABILITIES_V9_OUT_EVB_PORT_VLAN_RESTRICT_LBN 614315#define MC_CMD_GET_CAPABILITIES_V9_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 114316#define MC_CMD_GET_CAPABILITIES_V9_OUT_DRV_ATTACH_PREBOOT_OFST 014317#define MC_CMD_GET_CAPABILITIES_V9_OUT_DRV_ATTACH_PREBOOT_LBN 714318#define MC_CMD_GET_CAPABILITIES_V9_OUT_DRV_ATTACH_PREBOOT_WIDTH 114319#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_FORCE_EVENT_MERGING_OFST 014320#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_FORCE_EVENT_MERGING_LBN 814321#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_FORCE_EVENT_MERGING_WIDTH 114322#define MC_CMD_GET_CAPABILITIES_V9_OUT_SET_MAC_ENHANCED_OFST 014323#define MC_CMD_GET_CAPABILITIES_V9_OUT_SET_MAC_ENHANCED_LBN 914324#define MC_CMD_GET_CAPABILITIES_V9_OUT_SET_MAC_ENHANCED_WIDTH 114325#define MC_CMD_GET_CAPABILITIES_V9_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 014326#define MC_CMD_GET_CAPABILITIES_V9_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 1014327#define MC_CMD_GET_CAPABILITIES_V9_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 114328#define MC_CMD_GET_CAPABILITIES_V9_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 014329#define MC_CMD_GET_CAPABILITIES_V9_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 1114330#define MC_CMD_GET_CAPABILITIES_V9_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 114331#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_MAC_SECURITY_FILTERING_OFST 014332#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_MAC_SECURITY_FILTERING_LBN 1214333#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 114334#define MC_CMD_GET_CAPABILITIES_V9_OUT_ADDITIONAL_RSS_MODES_OFST 014335#define MC_CMD_GET_CAPABILITIES_V9_OUT_ADDITIONAL_RSS_MODES_LBN 1314336#define MC_CMD_GET_CAPABILITIES_V9_OUT_ADDITIONAL_RSS_MODES_WIDTH 114337#define MC_CMD_GET_CAPABILITIES_V9_OUT_QBB_OFST 014338#define MC_CMD_GET_CAPABILITIES_V9_OUT_QBB_LBN 1414339#define MC_CMD_GET_CAPABILITIES_V9_OUT_QBB_WIDTH 114340#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 014341#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 1514342#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 114343#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_RSS_LIMITED_OFST 014344#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_RSS_LIMITED_LBN 1614345#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_RSS_LIMITED_WIDTH 114346#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_PACKED_STREAM_OFST 014347#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_PACKED_STREAM_LBN 1714348#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_PACKED_STREAM_WIDTH 114349#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_INCLUDE_FCS_OFST 014350#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_INCLUDE_FCS_LBN 1814351#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_INCLUDE_FCS_WIDTH 114352#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_VLAN_INSERTION_OFST 014353#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_VLAN_INSERTION_LBN 1914354#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_VLAN_INSERTION_WIDTH 114355#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_VLAN_STRIPPING_OFST 014356#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_VLAN_STRIPPING_LBN 2014357#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_VLAN_STRIPPING_WIDTH 114358#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_OFST 014359#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_LBN 2114360#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_WIDTH 114361#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_PREFIX_LEN_0_OFST 014362#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_PREFIX_LEN_0_LBN 2214363#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_PREFIX_LEN_0_WIDTH 114364#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_PREFIX_LEN_14_OFST 014365#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_PREFIX_LEN_14_LBN 2314366#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_PREFIX_LEN_14_WIDTH 114367#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_TIMESTAMP_OFST 014368#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_TIMESTAMP_LBN 2414369#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_TIMESTAMP_WIDTH 114370#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_BATCHING_OFST 014371#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_BATCHING_LBN 2514372#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_BATCHING_WIDTH 114373#define MC_CMD_GET_CAPABILITIES_V9_OUT_MCAST_FILTER_CHAINING_OFST 014374#define MC_CMD_GET_CAPABILITIES_V9_OUT_MCAST_FILTER_CHAINING_LBN 2614375#define MC_CMD_GET_CAPABILITIES_V9_OUT_MCAST_FILTER_CHAINING_WIDTH 114376#define MC_CMD_GET_CAPABILITIES_V9_OUT_PM_AND_RXDP_COUNTERS_OFST 014377#define MC_CMD_GET_CAPABILITIES_V9_OUT_PM_AND_RXDP_COUNTERS_LBN 2714378#define MC_CMD_GET_CAPABILITIES_V9_OUT_PM_AND_RXDP_COUNTERS_WIDTH 114379#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_DISABLE_SCATTER_OFST 014380#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_DISABLE_SCATTER_LBN 2814381#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_DISABLE_SCATTER_WIDTH 114382#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_MCAST_UDP_LOOPBACK_OFST 014383#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_MCAST_UDP_LOOPBACK_LBN 2914384#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 114385#define MC_CMD_GET_CAPABILITIES_V9_OUT_EVB_OFST 014386#define MC_CMD_GET_CAPABILITIES_V9_OUT_EVB_LBN 3014387#define MC_CMD_GET_CAPABILITIES_V9_OUT_EVB_WIDTH 114388#define MC_CMD_GET_CAPABILITIES_V9_OUT_VXLAN_NVGRE_OFST 014389#define MC_CMD_GET_CAPABILITIES_V9_OUT_VXLAN_NVGRE_LBN 3114390#define MC_CMD_GET_CAPABILITIES_V9_OUT_VXLAN_NVGRE_WIDTH 114391/* RxDPCPU firmware id. */14392#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_DPCPU_FW_ID_OFST 414393#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_DPCPU_FW_ID_LEN 214394/* enum: Standard RXDP firmware */14395#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP 0x014396/* enum: Low latency RXDP firmware */14397#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_LOW_LATENCY 0x114398/* enum: Packed stream RXDP firmware */14399#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_PACKED_STREAM 0x214400/* enum: Rules engine RXDP firmware */14401#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_RULES_ENGINE 0x514402/* enum: DPDK RXDP firmware */14403#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_DPDK 0x614404/* enum: BIST RXDP firmware */14405#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_BIST 0x10a14406/* enum: RXDP Test firmware image 1 */14407#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x10114408/* enum: RXDP Test firmware image 2 */14409#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x10214410/* enum: RXDP Test firmware image 3 */14411#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x10314412/* enum: RXDP Test firmware image 4 */14413#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x10414414/* enum: RXDP Test firmware image 5 */14415#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_BACKPRESSURE 0x10514416/* enum: RXDP Test firmware image 6 */14417#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_FW_PACKET_EDITS 0x10614418/* enum: RXDP Test firmware image 7 */14419#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x10714420/* enum: RXDP Test firmware image 8 */14421#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_FW_DISABLE_DL 0x10814422/* enum: RXDP Test firmware image 9 */14423#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b14424/* enum: RXDP Test firmware image 10 */14425#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_FW_SLOW 0x10c14426/* TxDPCPU firmware id. */14427#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_DPCPU_FW_ID_OFST 614428#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_DPCPU_FW_ID_LEN 214429/* enum: Standard TXDP firmware */14430#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXDP 0x014431/* enum: Low latency TXDP firmware */14432#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXDP_LOW_LATENCY 0x114433/* enum: High packet rate TXDP firmware */14434#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXDP_HIGH_PACKET_RATE 0x314435/* enum: Rules engine TXDP firmware */14436#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXDP_RULES_ENGINE 0x514437/* enum: DPDK TXDP firmware */14438#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXDP_DPDK 0x614439/* enum: BIST TXDP firmware */14440#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXDP_BIST 0x12d14441/* enum: TXDP Test firmware image 1 */14442#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXDP_TEST_FW_TSO_EDIT 0x10114443/* enum: TXDP Test firmware image 2 */14444#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXDP_TEST_FW_PACKET_EDITS 0x10214445/* enum: TXDP CSR bus test firmware */14446#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXDP_TEST_FW_CSR 0x10314447#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_VERSION_OFST 814448#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_VERSION_LEN 214449#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_VERSION_REV_OFST 814450#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_VERSION_REV_LBN 014451#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_VERSION_REV_WIDTH 1214452#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_VERSION_TYPE_OFST 814453#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_VERSION_TYPE_LBN 1214454#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_VERSION_TYPE_WIDTH 414455/* enum: reserved value - do not use (may indicate alternative interpretation14456 * of REV field in future)14457 */14458#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_RESERVED 0x014459/* enum: Trivial RX PD firmware for early Huntington development (Huntington14460 * development only)14461 */14462#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_FIRST_PKT 0x114463/* enum: RX PD firmware for telemetry prototyping (Medford2 development only)14464 */14465#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x114466/* enum: RX PD firmware with approximately Siena-compatible behaviour14467 * (Huntington development only)14468 */14469#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x214470/* enum: Full featured RX PD production firmware */14471#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x314472/* enum: (deprecated original name for the FULL_FEATURED variant) */14473#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_VSWITCH 0x314474/* enum: siena_compat variant RX PD firmware using PM rather than MAC14475 * (Huntington development only)14476 */14477#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x414478/* enum: Low latency RX PD production firmware */14479#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x514480/* enum: Packed stream RX PD production firmware */14481#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x614482/* enum: RX PD firmware handling layer 2 only for high packet rate performance14483 * tests (Medford development only)14484 */14485#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x714486/* enum: Rules engine RX PD production firmware */14487#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x814488/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */14489#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_L3XUDP 0x914490/* enum: DPDK RX PD production firmware */14491#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_DPDK 0xa14492/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */14493#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe14494/* enum: RX PD firmware parsing but not filtering network overlay tunnel14495 * encapsulations (Medford development only)14496 */14497#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf14498#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_VERSION_OFST 1014499#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_VERSION_LEN 214500#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_VERSION_REV_OFST 1014501#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_VERSION_REV_LBN 014502#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_VERSION_REV_WIDTH 1214503#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_VERSION_TYPE_OFST 1014504#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_VERSION_TYPE_LBN 1214505#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_VERSION_TYPE_WIDTH 414506/* enum: reserved value - do not use (may indicate alternative interpretation14507 * of REV field in future)14508 */14509#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_RESERVED 0x014510/* enum: Trivial TX PD firmware for early Huntington development (Huntington14511 * development only)14512 */14513#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_FIRST_PKT 0x114514/* enum: TX PD firmware for telemetry prototyping (Medford2 development only)14515 */14516#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x114517/* enum: TX PD firmware with approximately Siena-compatible behaviour14518 * (Huntington development only)14519 */14520#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x214521/* enum: Full featured TX PD production firmware */14522#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x314523/* enum: (deprecated original name for the FULL_FEATURED variant) */14524#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_VSWITCH 0x314525/* enum: siena_compat variant TX PD firmware using PM rather than MAC14526 * (Huntington development only)14527 */14528#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x414529#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */14530/* enum: TX PD firmware handling layer 2 only for high packet rate performance14531 * tests (Medford development only)14532 */14533#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x714534/* enum: Rules engine TX PD production firmware */14535#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x814536/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */14537#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_L3XUDP 0x914538/* enum: DPDK TX PD production firmware */14539#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_DPDK 0xa14540/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */14541#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe14542/* Hardware capabilities of NIC */14543#define MC_CMD_GET_CAPABILITIES_V9_OUT_HW_CAPABILITIES_OFST 1214544#define MC_CMD_GET_CAPABILITIES_V9_OUT_HW_CAPABILITIES_LEN 414545/* Licensed capabilities */14546#define MC_CMD_GET_CAPABILITIES_V9_OUT_LICENSE_CAPABILITIES_OFST 1614547#define MC_CMD_GET_CAPABILITIES_V9_OUT_LICENSE_CAPABILITIES_LEN 414548/* Second word of flags. Not present on older firmware (check the length). */14549#define MC_CMD_GET_CAPABILITIES_V9_OUT_FLAGS2_OFST 2014550#define MC_CMD_GET_CAPABILITIES_V9_OUT_FLAGS2_LEN 414551#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_V2_OFST 2014552#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_V2_LBN 014553#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_V2_WIDTH 114554#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_V2_ENCAP_OFST 2014555#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_V2_ENCAP_LBN 114556#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_V2_ENCAP_WIDTH 114557#define MC_CMD_GET_CAPABILITIES_V9_OUT_EVQ_TIMER_CTRL_OFST 2014558#define MC_CMD_GET_CAPABILITIES_V9_OUT_EVQ_TIMER_CTRL_LBN 214559#define MC_CMD_GET_CAPABILITIES_V9_OUT_EVQ_TIMER_CTRL_WIDTH 114560#define MC_CMD_GET_CAPABILITIES_V9_OUT_EVENT_CUT_THROUGH_OFST 2014561#define MC_CMD_GET_CAPABILITIES_V9_OUT_EVENT_CUT_THROUGH_LBN 314562#define MC_CMD_GET_CAPABILITIES_V9_OUT_EVENT_CUT_THROUGH_WIDTH 114563#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_CUT_THROUGH_OFST 2014564#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_CUT_THROUGH_LBN 414565#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_CUT_THROUGH_WIDTH 114566#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_VFIFO_ULL_MODE_OFST 2014567#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_VFIFO_ULL_MODE_LBN 514568#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_VFIFO_ULL_MODE_WIDTH 114569#define MC_CMD_GET_CAPABILITIES_V9_OUT_MAC_STATS_40G_TX_SIZE_BINS_OFST 2014570#define MC_CMD_GET_CAPABILITIES_V9_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 614571#define MC_CMD_GET_CAPABILITIES_V9_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 114572#define MC_CMD_GET_CAPABILITIES_V9_OUT_INIT_EVQ_TYPE_SUPPORTED_OFST 2014573#define MC_CMD_GET_CAPABILITIES_V9_OUT_INIT_EVQ_TYPE_SUPPORTED_LBN 714574#define MC_CMD_GET_CAPABILITIES_V9_OUT_INIT_EVQ_TYPE_SUPPORTED_WIDTH 114575#define MC_CMD_GET_CAPABILITIES_V9_OUT_INIT_EVQ_V2_OFST 2014576#define MC_CMD_GET_CAPABILITIES_V9_OUT_INIT_EVQ_V2_LBN 714577#define MC_CMD_GET_CAPABILITIES_V9_OUT_INIT_EVQ_V2_WIDTH 114578#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_MAC_TIMESTAMPING_OFST 2014579#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_MAC_TIMESTAMPING_LBN 814580#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_MAC_TIMESTAMPING_WIDTH 114581#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TIMESTAMP_OFST 2014582#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TIMESTAMP_LBN 914583#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TIMESTAMP_WIDTH 114584#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_SNIFF_OFST 2014585#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_SNIFF_LBN 1014586#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_SNIFF_WIDTH 114587#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_SNIFF_OFST 2014588#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_SNIFF_LBN 1114589#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_SNIFF_WIDTH 114590#define MC_CMD_GET_CAPABILITIES_V9_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_OFST 2014591#define MC_CMD_GET_CAPABILITIES_V9_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_LBN 1214592#define MC_CMD_GET_CAPABILITIES_V9_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 114593#define MC_CMD_GET_CAPABILITIES_V9_OUT_MCDI_BACKGROUND_OFST 2014594#define MC_CMD_GET_CAPABILITIES_V9_OUT_MCDI_BACKGROUND_LBN 1314595#define MC_CMD_GET_CAPABILITIES_V9_OUT_MCDI_BACKGROUND_WIDTH 114596#define MC_CMD_GET_CAPABILITIES_V9_OUT_MCDI_DB_RETURN_OFST 2014597#define MC_CMD_GET_CAPABILITIES_V9_OUT_MCDI_DB_RETURN_LBN 1414598#define MC_CMD_GET_CAPABILITIES_V9_OUT_MCDI_DB_RETURN_WIDTH 114599#define MC_CMD_GET_CAPABILITIES_V9_OUT_CTPIO_OFST 2014600#define MC_CMD_GET_CAPABILITIES_V9_OUT_CTPIO_LBN 1514601#define MC_CMD_GET_CAPABILITIES_V9_OUT_CTPIO_WIDTH 114602#define MC_CMD_GET_CAPABILITIES_V9_OUT_TSA_SUPPORT_OFST 2014603#define MC_CMD_GET_CAPABILITIES_V9_OUT_TSA_SUPPORT_LBN 1614604#define MC_CMD_GET_CAPABILITIES_V9_OUT_TSA_SUPPORT_WIDTH 114605#define MC_CMD_GET_CAPABILITIES_V9_OUT_TSA_BOUND_OFST 2014606#define MC_CMD_GET_CAPABILITIES_V9_OUT_TSA_BOUND_LBN 1714607#define MC_CMD_GET_CAPABILITIES_V9_OUT_TSA_BOUND_WIDTH 114608#define MC_CMD_GET_CAPABILITIES_V9_OUT_SF_ADAPTER_AUTHENTICATION_OFST 2014609#define MC_CMD_GET_CAPABILITIES_V9_OUT_SF_ADAPTER_AUTHENTICATION_LBN 1814610#define MC_CMD_GET_CAPABILITIES_V9_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 114611#define MC_CMD_GET_CAPABILITIES_V9_OUT_FILTER_ACTION_FLAG_OFST 2014612#define MC_CMD_GET_CAPABILITIES_V9_OUT_FILTER_ACTION_FLAG_LBN 1914613#define MC_CMD_GET_CAPABILITIES_V9_OUT_FILTER_ACTION_FLAG_WIDTH 114614#define MC_CMD_GET_CAPABILITIES_V9_OUT_FILTER_ACTION_MARK_OFST 2014615#define MC_CMD_GET_CAPABILITIES_V9_OUT_FILTER_ACTION_MARK_LBN 2014616#define MC_CMD_GET_CAPABILITIES_V9_OUT_FILTER_ACTION_MARK_WIDTH 114617#define MC_CMD_GET_CAPABILITIES_V9_OUT_EQUAL_STRIDE_SUPER_BUFFER_OFST 2014618#define MC_CMD_GET_CAPABILITIES_V9_OUT_EQUAL_STRIDE_SUPER_BUFFER_LBN 2114619#define MC_CMD_GET_CAPABILITIES_V9_OUT_EQUAL_STRIDE_SUPER_BUFFER_WIDTH 114620#define MC_CMD_GET_CAPABILITIES_V9_OUT_EQUAL_STRIDE_PACKED_STREAM_OFST 2014621#define MC_CMD_GET_CAPABILITIES_V9_OUT_EQUAL_STRIDE_PACKED_STREAM_LBN 2114622#define MC_CMD_GET_CAPABILITIES_V9_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 114623#define MC_CMD_GET_CAPABILITIES_V9_OUT_L3XUDP_SUPPORT_OFST 2014624#define MC_CMD_GET_CAPABILITIES_V9_OUT_L3XUDP_SUPPORT_LBN 2214625#define MC_CMD_GET_CAPABILITIES_V9_OUT_L3XUDP_SUPPORT_WIDTH 114626#define MC_CMD_GET_CAPABILITIES_V9_OUT_FW_SUBVARIANT_NO_TX_CSUM_OFST 2014627#define MC_CMD_GET_CAPABILITIES_V9_OUT_FW_SUBVARIANT_NO_TX_CSUM_LBN 2314628#define MC_CMD_GET_CAPABILITIES_V9_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 114629#define MC_CMD_GET_CAPABILITIES_V9_OUT_VI_SPREADING_OFST 2014630#define MC_CMD_GET_CAPABILITIES_V9_OUT_VI_SPREADING_LBN 2414631#define MC_CMD_GET_CAPABILITIES_V9_OUT_VI_SPREADING_WIDTH 114632#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_HLB_IDLE_OFST 2014633#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_HLB_IDLE_LBN 2514634#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_HLB_IDLE_WIDTH 114635#define MC_CMD_GET_CAPABILITIES_V9_OUT_INIT_RXQ_NO_CONT_EV_OFST 2014636#define MC_CMD_GET_CAPABILITIES_V9_OUT_INIT_RXQ_NO_CONT_EV_LBN 2614637#define MC_CMD_GET_CAPABILITIES_V9_OUT_INIT_RXQ_NO_CONT_EV_WIDTH 114638#define MC_CMD_GET_CAPABILITIES_V9_OUT_INIT_RXQ_WITH_BUFFER_SIZE_OFST 2014639#define MC_CMD_GET_CAPABILITIES_V9_OUT_INIT_RXQ_WITH_BUFFER_SIZE_LBN 2714640#define MC_CMD_GET_CAPABILITIES_V9_OUT_INIT_RXQ_WITH_BUFFER_SIZE_WIDTH 114641#define MC_CMD_GET_CAPABILITIES_V9_OUT_BUNDLE_UPDATE_OFST 2014642#define MC_CMD_GET_CAPABILITIES_V9_OUT_BUNDLE_UPDATE_LBN 2814643#define MC_CMD_GET_CAPABILITIES_V9_OUT_BUNDLE_UPDATE_WIDTH 114644#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_V3_OFST 2014645#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_V3_LBN 2914646#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_V3_WIDTH 114647#define MC_CMD_GET_CAPABILITIES_V9_OUT_DYNAMIC_SENSORS_OFST 2014648#define MC_CMD_GET_CAPABILITIES_V9_OUT_DYNAMIC_SENSORS_LBN 3014649#define MC_CMD_GET_CAPABILITIES_V9_OUT_DYNAMIC_SENSORS_WIDTH 114650#define MC_CMD_GET_CAPABILITIES_V9_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_OFST 2014651#define MC_CMD_GET_CAPABILITIES_V9_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_LBN 3114652#define MC_CMD_GET_CAPABILITIES_V9_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_WIDTH 114653/* Number of FATSOv2 contexts per datapath supported by this NIC (when14654 * TX_TSO_V2 == 1). Not present on older firmware (check the length).14655 */14656#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_V2_N_CONTEXTS_OFST 2414657#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_V2_N_CONTEXTS_LEN 214658/* One byte per PF containing the number of the external port assigned to this14659 * PF, indexed by PF number. Special values indicate that a PF is either not14660 * present or not assigned.14661 */14662#define MC_CMD_GET_CAPABILITIES_V9_OUT_PFS_TO_PORTS_ASSIGNMENT_OFST 2614663#define MC_CMD_GET_CAPABILITIES_V9_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 114664#define MC_CMD_GET_CAPABILITIES_V9_OUT_PFS_TO_PORTS_ASSIGNMENT_NUM 1614665/* enum: The caller is not permitted to access information on this PF. */14666#define MC_CMD_GET_CAPABILITIES_V9_OUT_ACCESS_NOT_PERMITTED 0xff14667/* enum: PF does not exist. */14668#define MC_CMD_GET_CAPABILITIES_V9_OUT_PF_NOT_PRESENT 0xfe14669/* enum: PF does exist but is not assigned to any external port. */14670#define MC_CMD_GET_CAPABILITIES_V9_OUT_PF_NOT_ASSIGNED 0xfd14671/* enum: This value indicates that PF is assigned, but it cannot be expressed14672 * in this field. It is intended for a possible future situation where a more14673 * complex scheme of PFs to ports mapping is being used. The future driver14674 * should look for a new field supporting the new scheme. The current/old14675 * driver should treat this value as PF_NOT_ASSIGNED.14676 */14677#define MC_CMD_GET_CAPABILITIES_V9_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc14678/* One byte per PF containing the number of its VFs, indexed by PF number. A14679 * special value indicates that a PF is not present.14680 */14681#define MC_CMD_GET_CAPABILITIES_V9_OUT_NUM_VFS_PER_PF_OFST 4214682#define MC_CMD_GET_CAPABILITIES_V9_OUT_NUM_VFS_PER_PF_LEN 114683#define MC_CMD_GET_CAPABILITIES_V9_OUT_NUM_VFS_PER_PF_NUM 1614684/* enum: The caller is not permitted to access information on this PF. */14685/* MC_CMD_GET_CAPABILITIES_V9_OUT_ACCESS_NOT_PERMITTED 0xff */14686/* enum: PF does not exist. */14687/* MC_CMD_GET_CAPABILITIES_V9_OUT_PF_NOT_PRESENT 0xfe */14688/* Number of VIs available for each external port */14689#define MC_CMD_GET_CAPABILITIES_V9_OUT_NUM_VIS_PER_PORT_OFST 5814690#define MC_CMD_GET_CAPABILITIES_V9_OUT_NUM_VIS_PER_PORT_LEN 214691#define MC_CMD_GET_CAPABILITIES_V9_OUT_NUM_VIS_PER_PORT_NUM 414692/* Size of RX descriptor cache expressed as binary logarithm The actual size14693 * equals (2 ^ RX_DESC_CACHE_SIZE)14694 */14695#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_DESC_CACHE_SIZE_OFST 6614696#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_DESC_CACHE_SIZE_LEN 114697/* Size of TX descriptor cache expressed as binary logarithm The actual size14698 * equals (2 ^ TX_DESC_CACHE_SIZE)14699 */14700#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_DESC_CACHE_SIZE_OFST 6714701#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_DESC_CACHE_SIZE_LEN 114702/* Total number of available PIO buffers */14703#define MC_CMD_GET_CAPABILITIES_V9_OUT_NUM_PIO_BUFFS_OFST 6814704#define MC_CMD_GET_CAPABILITIES_V9_OUT_NUM_PIO_BUFFS_LEN 214705/* Size of a single PIO buffer */14706#define MC_CMD_GET_CAPABILITIES_V9_OUT_SIZE_PIO_BUFF_OFST 7014707#define MC_CMD_GET_CAPABILITIES_V9_OUT_SIZE_PIO_BUFF_LEN 214708/* On chips later than Medford the amount of address space assigned to each VI14709 * is configurable. This is a global setting that the driver must query to14710 * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available14711 * with 8k VI windows.14712 */14713#define MC_CMD_GET_CAPABILITIES_V9_OUT_VI_WINDOW_MODE_OFST 7214714#define MC_CMD_GET_CAPABILITIES_V9_OUT_VI_WINDOW_MODE_LEN 114715/* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k.14716 * CTPIO is not mapped.14717 */14718#define MC_CMD_GET_CAPABILITIES_V9_OUT_VI_WINDOW_MODE_8K 0x014719/* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */14720#define MC_CMD_GET_CAPABILITIES_V9_OUT_VI_WINDOW_MODE_16K 0x114721/* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */14722#define MC_CMD_GET_CAPABILITIES_V9_OUT_VI_WINDOW_MODE_64K 0x214723/* Number of vFIFOs per adapter that can be used for VFIFO Stuffing14724 * (SF-115995-SW) in the present configuration of firmware and port mode.14725 */14726#define MC_CMD_GET_CAPABILITIES_V9_OUT_VFIFO_STUFFING_NUM_VFIFOS_OFST 7314727#define MC_CMD_GET_CAPABILITIES_V9_OUT_VFIFO_STUFFING_NUM_VFIFOS_LEN 114728/* Number of buffers per adapter that can be used for VFIFO Stuffing14729 * (SF-115995-SW) in the present configuration of firmware and port mode.14730 */14731#define MC_CMD_GET_CAPABILITIES_V9_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_OFST 7414732#define MC_CMD_GET_CAPABILITIES_V9_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_LEN 214733/* Entry count in the MAC stats array, including the final GENERATION_END14734 * entry. For MAC stats DMA, drivers should allocate a buffer large enough to14735 * hold at least this many 64-bit stats values, if they wish to receive all14736 * available stats. If the buffer is shorter than MAC_STATS_NUM_STATS * 8, the14737 * stats array returned will be truncated.14738 */14739#define MC_CMD_GET_CAPABILITIES_V9_OUT_MAC_STATS_NUM_STATS_OFST 7614740#define MC_CMD_GET_CAPABILITIES_V9_OUT_MAC_STATS_NUM_STATS_LEN 214741/* Maximum supported value for MC_CMD_FILTER_OP_V3/MATCH_MARK_VALUE. This field14742 * will only be non-zero if MC_CMD_GET_CAPABILITIES/FILTER_ACTION_MARK is set.14743 */14744#define MC_CMD_GET_CAPABILITIES_V9_OUT_FILTER_ACTION_MARK_MAX_OFST 8014745#define MC_CMD_GET_CAPABILITIES_V9_OUT_FILTER_ACTION_MARK_MAX_LEN 414746/* On devices where the INIT_RXQ_WITH_BUFFER_SIZE flag (in14747 * GET_CAPABILITIES_OUT_V2) is set, drivers have to specify a buffer size when14748 * they create an RX queue. Due to hardware limitations, only a small number of14749 * different buffer sizes may be available concurrently. Nonzero entries in14750 * this array are the sizes of buffers which the system guarantees will be14751 * available for use. If the list is empty, there are no limitations on14752 * concurrent buffer sizes.14753 */14754#define MC_CMD_GET_CAPABILITIES_V9_OUT_GUARANTEED_RX_BUFFER_SIZES_OFST 8414755#define MC_CMD_GET_CAPABILITIES_V9_OUT_GUARANTEED_RX_BUFFER_SIZES_LEN 414756#define MC_CMD_GET_CAPABILITIES_V9_OUT_GUARANTEED_RX_BUFFER_SIZES_NUM 1614757/* Third word of flags. Not present on older firmware (check the length). */14758#define MC_CMD_GET_CAPABILITIES_V9_OUT_FLAGS3_OFST 14814759#define MC_CMD_GET_CAPABILITIES_V9_OUT_FLAGS3_LEN 414760#define MC_CMD_GET_CAPABILITIES_V9_OUT_WOL_ETHERWAKE_OFST 14814761#define MC_CMD_GET_CAPABILITIES_V9_OUT_WOL_ETHERWAKE_LBN 014762#define MC_CMD_GET_CAPABILITIES_V9_OUT_WOL_ETHERWAKE_WIDTH 114763#define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_EVEN_SPREADING_OFST 14814764#define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_EVEN_SPREADING_LBN 114765#define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_EVEN_SPREADING_WIDTH 114766#define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_SELECTABLE_TABLE_SIZE_OFST 14814767#define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_SELECTABLE_TABLE_SIZE_LBN 214768#define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_SELECTABLE_TABLE_SIZE_WIDTH 114769#define MC_CMD_GET_CAPABILITIES_V9_OUT_MAE_SUPPORTED_OFST 14814770#define MC_CMD_GET_CAPABILITIES_V9_OUT_MAE_SUPPORTED_LBN 314771#define MC_CMD_GET_CAPABILITIES_V9_OUT_MAE_SUPPORTED_WIDTH 114772#define MC_CMD_GET_CAPABILITIES_V9_OUT_VDPA_SUPPORTED_OFST 14814773#define MC_CMD_GET_CAPABILITIES_V9_OUT_VDPA_SUPPORTED_LBN 414774#define MC_CMD_GET_CAPABILITIES_V9_OUT_VDPA_SUPPORTED_WIDTH 114775#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_OFST 14814776#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_LBN 514777#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_WIDTH 114778#define MC_CMD_GET_CAPABILITIES_V9_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_OFST 14814779#define MC_CMD_GET_CAPABILITIES_V9_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_LBN 614780#define MC_CMD_GET_CAPABILITIES_V9_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_WIDTH 114781#define MC_CMD_GET_CAPABILITIES_V9_OUT_UNSOL_EV_CREDIT_SUPPORTED_OFST 14814782#define MC_CMD_GET_CAPABILITIES_V9_OUT_UNSOL_EV_CREDIT_SUPPORTED_LBN 714783#define MC_CMD_GET_CAPABILITIES_V9_OUT_UNSOL_EV_CREDIT_SUPPORTED_WIDTH 114784/* These bits are reserved for communicating test-specific capabilities to14785 * host-side test software. All production drivers should treat this field as14786 * opaque.14787 */14788#define MC_CMD_GET_CAPABILITIES_V9_OUT_TEST_RESERVED_OFST 15214789#define MC_CMD_GET_CAPABILITIES_V9_OUT_TEST_RESERVED_LEN 814790#define MC_CMD_GET_CAPABILITIES_V9_OUT_TEST_RESERVED_LO_OFST 15214791#define MC_CMD_GET_CAPABILITIES_V9_OUT_TEST_RESERVED_HI_OFST 15614792/* The minimum size (in table entries) of indirection table to be allocated14793 * from the pool for an RSS context. Note that the table size used must be a14794 * power of 2.14795 */14796#define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_MIN_INDIRECTION_TABLE_SIZE_OFST 16014797#define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_MIN_INDIRECTION_TABLE_SIZE_LEN 414798/* The maximum size (in table entries) of indirection table to be allocated14799 * from the pool for an RSS context. Note that the table size used must be a14800 * power of 2.14801 */14802#define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_MAX_INDIRECTION_TABLE_SIZE_OFST 16414803#define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_MAX_INDIRECTION_TABLE_SIZE_LEN 414804/* The maximum number of queues that can be used by an RSS context in exclusive14805 * mode. In exclusive mode the context has a configurable indirection table and14806 * a configurable RSS key.14807 */14808#define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_MAX_INDIRECTION_QUEUES_OFST 16814809#define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_MAX_INDIRECTION_QUEUES_LEN 414810/* The maximum number of queues that can be used by an RSS context in even-14811 * spreading mode. In even-spreading mode the context has no indirection table14812 * but it does have a configurable RSS key.14813 */14814#define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_MAX_EVEN_SPREADING_QUEUES_OFST 17214815#define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_MAX_EVEN_SPREADING_QUEUES_LEN 414816/* The total number of RSS contexts supported. Note that the number of14817 * available contexts using indirection tables is also limited by the14818 * availability of indirection table space allocated from a common pool.14819 */14820#define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_NUM_CONTEXTS_OFST 17614821#define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_NUM_CONTEXTS_LEN 414822/* The total amount of indirection table space that can be shared between RSS14823 * contexts.14824 */14825#define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_TABLE_POOL_SIZE_OFST 18014826#define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_TABLE_POOL_SIZE_LEN 414827 14828 14829/***********************************/14830/* MC_CMD_V2_EXTN14831 * Encapsulation for a v2 extended command14832 */14833#define MC_CMD_V2_EXTN 0x7f14834 14835/* MC_CMD_V2_EXTN_IN msgrequest */14836#define MC_CMD_V2_EXTN_IN_LEN 414837/* the extended command number */14838#define MC_CMD_V2_EXTN_IN_EXTENDED_CMD_LBN 014839#define MC_CMD_V2_EXTN_IN_EXTENDED_CMD_WIDTH 1514840#define MC_CMD_V2_EXTN_IN_UNUSED_LBN 1514841#define MC_CMD_V2_EXTN_IN_UNUSED_WIDTH 114842/* the actual length of the encapsulated command (which is not in the v114843 * header)14844 */14845#define MC_CMD_V2_EXTN_IN_ACTUAL_LEN_LBN 1614846#define MC_CMD_V2_EXTN_IN_ACTUAL_LEN_WIDTH 1014847#define MC_CMD_V2_EXTN_IN_UNUSED2_LBN 2614848#define MC_CMD_V2_EXTN_IN_UNUSED2_WIDTH 214849/* Type of command/response */14850#define MC_CMD_V2_EXTN_IN_MESSAGE_TYPE_LBN 2814851#define MC_CMD_V2_EXTN_IN_MESSAGE_TYPE_WIDTH 414852/* enum: MCDI command directed to or response originating from the MC. */14853#define MC_CMD_V2_EXTN_IN_MCDI_MESSAGE_TYPE_MC 0x014854/* enum: MCDI command directed to a TSA controller. MCDI responses of this type14855 * are not defined.14856 */14857#define MC_CMD_V2_EXTN_IN_MCDI_MESSAGE_TYPE_TSA 0x114858 14859 14860/***********************************/14861/* MC_CMD_LINK_PIOBUF14862 * Link a push I/O buffer to a TxQ14863 */14864#define MC_CMD_LINK_PIOBUF 0x9214865#undef MC_CMD_0x92_PRIVILEGE_CTG14866 14867#define MC_CMD_0x92_PRIVILEGE_CTG SRIOV_CTG_ONLOAD14868 14869/* MC_CMD_LINK_PIOBUF_IN msgrequest */14870#define MC_CMD_LINK_PIOBUF_IN_LEN 814871/* Handle for allocated push I/O buffer. */14872#define MC_CMD_LINK_PIOBUF_IN_PIOBUF_HANDLE_OFST 014873#define MC_CMD_LINK_PIOBUF_IN_PIOBUF_HANDLE_LEN 414874/* Function Local Instance (VI) number. */14875#define MC_CMD_LINK_PIOBUF_IN_TXQ_INSTANCE_OFST 414876#define MC_CMD_LINK_PIOBUF_IN_TXQ_INSTANCE_LEN 414877 14878/* MC_CMD_LINK_PIOBUF_OUT msgresponse */14879#define MC_CMD_LINK_PIOBUF_OUT_LEN 014880 14881 14882/***********************************/14883/* MC_CMD_UNLINK_PIOBUF14884 * Unlink a push I/O buffer from a TxQ14885 */14886#define MC_CMD_UNLINK_PIOBUF 0x9314887#undef MC_CMD_0x93_PRIVILEGE_CTG14888 14889#define MC_CMD_0x93_PRIVILEGE_CTG SRIOV_CTG_ONLOAD14890 14891/* MC_CMD_UNLINK_PIOBUF_IN msgrequest */14892#define MC_CMD_UNLINK_PIOBUF_IN_LEN 414893/* Function Local Instance (VI) number. */14894#define MC_CMD_UNLINK_PIOBUF_IN_TXQ_INSTANCE_OFST 014895#define MC_CMD_UNLINK_PIOBUF_IN_TXQ_INSTANCE_LEN 414896 14897/* MC_CMD_UNLINK_PIOBUF_OUT msgresponse */14898#define MC_CMD_UNLINK_PIOBUF_OUT_LEN 014899 14900 14901/***********************************/14902/* MC_CMD_VSWITCH_ALLOC14903 * allocate and initialise a v-switch.14904 */14905#define MC_CMD_VSWITCH_ALLOC 0x9414906#undef MC_CMD_0x94_PRIVILEGE_CTG14907 14908#define MC_CMD_0x94_PRIVILEGE_CTG SRIOV_CTG_GENERAL14909 14910/* MC_CMD_VSWITCH_ALLOC_IN msgrequest */14911#define MC_CMD_VSWITCH_ALLOC_IN_LEN 1614912/* The port to connect to the v-switch's upstream port. */14913#define MC_CMD_VSWITCH_ALLOC_IN_UPSTREAM_PORT_ID_OFST 014914#define MC_CMD_VSWITCH_ALLOC_IN_UPSTREAM_PORT_ID_LEN 414915/* The type of v-switch to create. */14916#define MC_CMD_VSWITCH_ALLOC_IN_TYPE_OFST 414917#define MC_CMD_VSWITCH_ALLOC_IN_TYPE_LEN 414918/* enum: VLAN */14919#define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VLAN 0x114920/* enum: VEB */14921#define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VEB 0x214922/* enum: VEPA (obsolete) */14923#define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VEPA 0x314924/* enum: MUX */14925#define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_MUX 0x414926/* enum: Snapper specific; semantics TBD */14927#define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_TEST 0x514928/* Flags controlling v-port creation */14929#define MC_CMD_VSWITCH_ALLOC_IN_FLAGS_OFST 814930#define MC_CMD_VSWITCH_ALLOC_IN_FLAGS_LEN 414931#define MC_CMD_VSWITCH_ALLOC_IN_FLAG_AUTO_PORT_OFST 814932#define MC_CMD_VSWITCH_ALLOC_IN_FLAG_AUTO_PORT_LBN 014933#define MC_CMD_VSWITCH_ALLOC_IN_FLAG_AUTO_PORT_WIDTH 114934/* The number of VLAN tags to allow for attached v-ports. For VLAN aggregators,14935 * this must be one or greated, and the attached v-ports must have exactly this14936 * number of tags. For other v-switch types, this must be zero of greater, and14937 * is an upper limit on the number of VLAN tags for attached v-ports. An error14938 * will be returned if existing configuration means we can't support attached14939 * v-ports with this number of tags.14940 */14941#define MC_CMD_VSWITCH_ALLOC_IN_NUM_VLAN_TAGS_OFST 1214942#define MC_CMD_VSWITCH_ALLOC_IN_NUM_VLAN_TAGS_LEN 414943 14944/* MC_CMD_VSWITCH_ALLOC_OUT msgresponse */14945#define MC_CMD_VSWITCH_ALLOC_OUT_LEN 014946 14947 14948/***********************************/14949/* MC_CMD_VSWITCH_FREE14950 * de-allocate a v-switch.14951 */14952#define MC_CMD_VSWITCH_FREE 0x9514953#undef MC_CMD_0x95_PRIVILEGE_CTG14954 14955#define MC_CMD_0x95_PRIVILEGE_CTG SRIOV_CTG_GENERAL14956 14957/* MC_CMD_VSWITCH_FREE_IN msgrequest */14958#define MC_CMD_VSWITCH_FREE_IN_LEN 414959/* The port to which the v-switch is connected. */14960#define MC_CMD_VSWITCH_FREE_IN_UPSTREAM_PORT_ID_OFST 014961#define MC_CMD_VSWITCH_FREE_IN_UPSTREAM_PORT_ID_LEN 414962 14963/* MC_CMD_VSWITCH_FREE_OUT msgresponse */14964#define MC_CMD_VSWITCH_FREE_OUT_LEN 014965 14966 14967/***********************************/14968/* MC_CMD_VSWITCH_QUERY14969 * read some config of v-switch. For now this command is an empty placeholder.14970 * It may be used to check if a v-switch is connected to a given EVB port (if14971 * not, then the command returns ENOENT).14972 */14973#define MC_CMD_VSWITCH_QUERY 0x6314974#undef MC_CMD_0x63_PRIVILEGE_CTG14975 14976#define MC_CMD_0x63_PRIVILEGE_CTG SRIOV_CTG_GENERAL14977 14978/* MC_CMD_VSWITCH_QUERY_IN msgrequest */14979#define MC_CMD_VSWITCH_QUERY_IN_LEN 414980/* The port to which the v-switch is connected. */14981#define MC_CMD_VSWITCH_QUERY_IN_UPSTREAM_PORT_ID_OFST 014982#define MC_CMD_VSWITCH_QUERY_IN_UPSTREAM_PORT_ID_LEN 414983 14984/* MC_CMD_VSWITCH_QUERY_OUT msgresponse */14985#define MC_CMD_VSWITCH_QUERY_OUT_LEN 014986 14987 14988/***********************************/14989/* MC_CMD_VPORT_ALLOC14990 * allocate a v-port.14991 */14992#define MC_CMD_VPORT_ALLOC 0x9614993#undef MC_CMD_0x96_PRIVILEGE_CTG14994 14995#define MC_CMD_0x96_PRIVILEGE_CTG SRIOV_CTG_GENERAL14996 14997/* MC_CMD_VPORT_ALLOC_IN msgrequest */14998#define MC_CMD_VPORT_ALLOC_IN_LEN 2014999/* The port to which the v-switch is connected. */15000#define MC_CMD_VPORT_ALLOC_IN_UPSTREAM_PORT_ID_OFST 015001#define MC_CMD_VPORT_ALLOC_IN_UPSTREAM_PORT_ID_LEN 415002/* The type of the new v-port. */15003#define MC_CMD_VPORT_ALLOC_IN_TYPE_OFST 415004#define MC_CMD_VPORT_ALLOC_IN_TYPE_LEN 415005/* enum: VLAN (obsolete) */15006#define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VLAN 0x115007/* enum: VEB (obsolete) */15008#define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VEB 0x215009/* enum: VEPA (obsolete) */15010#define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VEPA 0x315011/* enum: A normal v-port receives packets which match a specified MAC and/or15012 * VLAN.15013 */15014#define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_NORMAL 0x415015/* enum: An expansion v-port packets traffic which don't match any other15016 * v-port.15017 */15018#define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_EXPANSION 0x515019/* enum: An test v-port receives packets which match any filters installed by15020 * its downstream components.15021 */15022#define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_TEST 0x615023/* Flags controlling v-port creation */15024#define MC_CMD_VPORT_ALLOC_IN_FLAGS_OFST 815025#define MC_CMD_VPORT_ALLOC_IN_FLAGS_LEN 415026#define MC_CMD_VPORT_ALLOC_IN_FLAG_AUTO_PORT_OFST 815027#define MC_CMD_VPORT_ALLOC_IN_FLAG_AUTO_PORT_LBN 015028#define MC_CMD_VPORT_ALLOC_IN_FLAG_AUTO_PORT_WIDTH 115029#define MC_CMD_VPORT_ALLOC_IN_FLAG_VLAN_RESTRICT_OFST 815030#define MC_CMD_VPORT_ALLOC_IN_FLAG_VLAN_RESTRICT_LBN 115031#define MC_CMD_VPORT_ALLOC_IN_FLAG_VLAN_RESTRICT_WIDTH 115032/* The number of VLAN tags to insert/remove. An error will be returned if15033 * incompatible with the number of VLAN tags specified for the upstream15034 * v-switch.15035 */15036#define MC_CMD_VPORT_ALLOC_IN_NUM_VLAN_TAGS_OFST 1215037#define MC_CMD_VPORT_ALLOC_IN_NUM_VLAN_TAGS_LEN 415038/* The actual VLAN tags to insert/remove */15039#define MC_CMD_VPORT_ALLOC_IN_VLAN_TAGS_OFST 1615040#define MC_CMD_VPORT_ALLOC_IN_VLAN_TAGS_LEN 415041#define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_0_OFST 1615042#define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_0_LBN 015043#define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_0_WIDTH 1615044#define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_1_OFST 1615045#define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_1_LBN 1615046#define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_1_WIDTH 1615047 15048/* MC_CMD_VPORT_ALLOC_OUT msgresponse */15049#define MC_CMD_VPORT_ALLOC_OUT_LEN 415050/* The handle of the new v-port */15051#define MC_CMD_VPORT_ALLOC_OUT_VPORT_ID_OFST 015052#define MC_CMD_VPORT_ALLOC_OUT_VPORT_ID_LEN 415053 15054 15055/***********************************/15056/* MC_CMD_VPORT_FREE15057 * de-allocate a v-port.15058 */15059#define MC_CMD_VPORT_FREE 0x9715060#undef MC_CMD_0x97_PRIVILEGE_CTG15061 15062#define MC_CMD_0x97_PRIVILEGE_CTG SRIOV_CTG_GENERAL15063 15064/* MC_CMD_VPORT_FREE_IN msgrequest */15065#define MC_CMD_VPORT_FREE_IN_LEN 415066/* The handle of the v-port */15067#define MC_CMD_VPORT_FREE_IN_VPORT_ID_OFST 015068#define MC_CMD_VPORT_FREE_IN_VPORT_ID_LEN 415069 15070/* MC_CMD_VPORT_FREE_OUT msgresponse */15071#define MC_CMD_VPORT_FREE_OUT_LEN 015072 15073 15074/***********************************/15075/* MC_CMD_VADAPTOR_ALLOC15076 * allocate a v-adaptor.15077 */15078#define MC_CMD_VADAPTOR_ALLOC 0x9815079#undef MC_CMD_0x98_PRIVILEGE_CTG15080 15081#define MC_CMD_0x98_PRIVILEGE_CTG SRIOV_CTG_GENERAL15082 15083/* MC_CMD_VADAPTOR_ALLOC_IN msgrequest */15084#define MC_CMD_VADAPTOR_ALLOC_IN_LEN 3015085/* The port to connect to the v-adaptor's port. */15086#define MC_CMD_VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID_OFST 015087#define MC_CMD_VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID_LEN 415088/* Flags controlling v-adaptor creation */15089#define MC_CMD_VADAPTOR_ALLOC_IN_FLAGS_OFST 815090#define MC_CMD_VADAPTOR_ALLOC_IN_FLAGS_LEN 415091#define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_AUTO_VADAPTOR_OFST 815092#define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_AUTO_VADAPTOR_LBN 015093#define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_AUTO_VADAPTOR_WIDTH 115094#define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 815095#define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 115096#define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 115097/* The number of VLAN tags to strip on receive */15098#define MC_CMD_VADAPTOR_ALLOC_IN_NUM_VLANS_OFST 1215099#define MC_CMD_VADAPTOR_ALLOC_IN_NUM_VLANS_LEN 415100/* The number of VLAN tags to transparently insert/remove. */15101#define MC_CMD_VADAPTOR_ALLOC_IN_NUM_VLAN_TAGS_OFST 1615102#define MC_CMD_VADAPTOR_ALLOC_IN_NUM_VLAN_TAGS_LEN 415103/* The actual VLAN tags to insert/remove */15104#define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAGS_OFST 2015105#define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAGS_LEN 415106#define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_0_OFST 2015107#define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_0_LBN 015108#define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_0_WIDTH 1615109#define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_1_OFST 2015110#define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_1_LBN 1615111#define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_1_WIDTH 1615112/* The MAC address to assign to this v-adaptor */15113#define MC_CMD_VADAPTOR_ALLOC_IN_MACADDR_OFST 2415114#define MC_CMD_VADAPTOR_ALLOC_IN_MACADDR_LEN 615115/* enum: Derive the MAC address from the upstream port */15116#define MC_CMD_VADAPTOR_ALLOC_IN_AUTO_MAC 0x015117 15118/* MC_CMD_VADAPTOR_ALLOC_OUT msgresponse */15119#define MC_CMD_VADAPTOR_ALLOC_OUT_LEN 015120 15121 15122/***********************************/15123/* MC_CMD_VADAPTOR_FREE15124 * de-allocate a v-adaptor.15125 */15126#define MC_CMD_VADAPTOR_FREE 0x9915127#undef MC_CMD_0x99_PRIVILEGE_CTG15128 15129#define MC_CMD_0x99_PRIVILEGE_CTG SRIOV_CTG_GENERAL15130 15131/* MC_CMD_VADAPTOR_FREE_IN msgrequest */15132#define MC_CMD_VADAPTOR_FREE_IN_LEN 415133/* The port to which the v-adaptor is connected. */15134#define MC_CMD_VADAPTOR_FREE_IN_UPSTREAM_PORT_ID_OFST 015135#define MC_CMD_VADAPTOR_FREE_IN_UPSTREAM_PORT_ID_LEN 415136 15137/* MC_CMD_VADAPTOR_FREE_OUT msgresponse */15138#define MC_CMD_VADAPTOR_FREE_OUT_LEN 015139 15140 15141/***********************************/15142/* MC_CMD_VADAPTOR_SET_MAC15143 * assign a new MAC address to a v-adaptor.15144 */15145#define MC_CMD_VADAPTOR_SET_MAC 0x5d15146#undef MC_CMD_0x5d_PRIVILEGE_CTG15147 15148#define MC_CMD_0x5d_PRIVILEGE_CTG SRIOV_CTG_GENERAL15149 15150/* MC_CMD_VADAPTOR_SET_MAC_IN msgrequest */15151#define MC_CMD_VADAPTOR_SET_MAC_IN_LEN 1015152/* The port to which the v-adaptor is connected. */15153#define MC_CMD_VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID_OFST 015154#define MC_CMD_VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID_LEN 415155/* The new MAC address to assign to this v-adaptor */15156#define MC_CMD_VADAPTOR_SET_MAC_IN_MACADDR_OFST 415157#define MC_CMD_VADAPTOR_SET_MAC_IN_MACADDR_LEN 615158 15159/* MC_CMD_VADAPTOR_SET_MAC_OUT msgresponse */15160#define MC_CMD_VADAPTOR_SET_MAC_OUT_LEN 015161 15162 15163/***********************************/15164/* MC_CMD_VADAPTOR_GET_MAC15165 * read the MAC address assigned to a v-adaptor.15166 */15167#define MC_CMD_VADAPTOR_GET_MAC 0x5e15168#undef MC_CMD_0x5e_PRIVILEGE_CTG15169 15170#define MC_CMD_0x5e_PRIVILEGE_CTG SRIOV_CTG_GENERAL15171 15172/* MC_CMD_VADAPTOR_GET_MAC_IN msgrequest */15173#define MC_CMD_VADAPTOR_GET_MAC_IN_LEN 415174/* The port to which the v-adaptor is connected. */15175#define MC_CMD_VADAPTOR_GET_MAC_IN_UPSTREAM_PORT_ID_OFST 015176#define MC_CMD_VADAPTOR_GET_MAC_IN_UPSTREAM_PORT_ID_LEN 415177 15178/* MC_CMD_VADAPTOR_GET_MAC_OUT msgresponse */15179#define MC_CMD_VADAPTOR_GET_MAC_OUT_LEN 615180/* The MAC address assigned to this v-adaptor */15181#define MC_CMD_VADAPTOR_GET_MAC_OUT_MACADDR_OFST 015182#define MC_CMD_VADAPTOR_GET_MAC_OUT_MACADDR_LEN 615183 15184 15185/***********************************/15186/* MC_CMD_VADAPTOR_QUERY15187 * read some config of v-adaptor.15188 */15189#define MC_CMD_VADAPTOR_QUERY 0x6115190#undef MC_CMD_0x61_PRIVILEGE_CTG15191 15192#define MC_CMD_0x61_PRIVILEGE_CTG SRIOV_CTG_GENERAL15193 15194/* MC_CMD_VADAPTOR_QUERY_IN msgrequest */15195#define MC_CMD_VADAPTOR_QUERY_IN_LEN 415196/* The port to which the v-adaptor is connected. */15197#define MC_CMD_VADAPTOR_QUERY_IN_UPSTREAM_PORT_ID_OFST 015198#define MC_CMD_VADAPTOR_QUERY_IN_UPSTREAM_PORT_ID_LEN 415199 15200/* MC_CMD_VADAPTOR_QUERY_OUT msgresponse */15201#define MC_CMD_VADAPTOR_QUERY_OUT_LEN 1215202/* The EVB port flags as defined at MC_CMD_VPORT_ALLOC. */15203#define MC_CMD_VADAPTOR_QUERY_OUT_PORT_FLAGS_OFST 015204#define MC_CMD_VADAPTOR_QUERY_OUT_PORT_FLAGS_LEN 415205/* The v-adaptor flags as defined at MC_CMD_VADAPTOR_ALLOC. */15206#define MC_CMD_VADAPTOR_QUERY_OUT_VADAPTOR_FLAGS_OFST 415207#define MC_CMD_VADAPTOR_QUERY_OUT_VADAPTOR_FLAGS_LEN 415208/* The number of VLAN tags that may still be added */15209#define MC_CMD_VADAPTOR_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS_OFST 815210#define MC_CMD_VADAPTOR_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS_LEN 415211 15212 15213/***********************************/15214/* MC_CMD_EVB_PORT_ASSIGN15215 * assign a port to a PCI function.15216 */15217#define MC_CMD_EVB_PORT_ASSIGN 0x9a15218#undef MC_CMD_0x9a_PRIVILEGE_CTG15219 15220#define MC_CMD_0x9a_PRIVILEGE_CTG SRIOV_CTG_GENERAL15221 15222/* MC_CMD_EVB_PORT_ASSIGN_IN msgrequest */15223#define MC_CMD_EVB_PORT_ASSIGN_IN_LEN 815224/* The port to assign. */15225#define MC_CMD_EVB_PORT_ASSIGN_IN_PORT_ID_OFST 015226#define MC_CMD_EVB_PORT_ASSIGN_IN_PORT_ID_LEN 415227/* The target function to modify. */15228#define MC_CMD_EVB_PORT_ASSIGN_IN_FUNCTION_OFST 415229#define MC_CMD_EVB_PORT_ASSIGN_IN_FUNCTION_LEN 415230#define MC_CMD_EVB_PORT_ASSIGN_IN_PF_OFST 415231#define MC_CMD_EVB_PORT_ASSIGN_IN_PF_LBN 015232#define MC_CMD_EVB_PORT_ASSIGN_IN_PF_WIDTH 1615233#define MC_CMD_EVB_PORT_ASSIGN_IN_VF_OFST 415234#define MC_CMD_EVB_PORT_ASSIGN_IN_VF_LBN 1615235#define MC_CMD_EVB_PORT_ASSIGN_IN_VF_WIDTH 1615236 15237/* MC_CMD_EVB_PORT_ASSIGN_OUT msgresponse */15238#define MC_CMD_EVB_PORT_ASSIGN_OUT_LEN 015239 15240 15241/***********************************/15242/* MC_CMD_RDWR_A64_REGIONS15243 * Assign the 64 bit region addresses.15244 */15245#define MC_CMD_RDWR_A64_REGIONS 0x9b15246#undef MC_CMD_0x9b_PRIVILEGE_CTG15247 15248#define MC_CMD_0x9b_PRIVILEGE_CTG SRIOV_CTG_ADMIN15249 15250/* MC_CMD_RDWR_A64_REGIONS_IN msgrequest */15251#define MC_CMD_RDWR_A64_REGIONS_IN_LEN 1715252#define MC_CMD_RDWR_A64_REGIONS_IN_REGION0_OFST 015253#define MC_CMD_RDWR_A64_REGIONS_IN_REGION0_LEN 415254#define MC_CMD_RDWR_A64_REGIONS_IN_REGION1_OFST 415255#define MC_CMD_RDWR_A64_REGIONS_IN_REGION1_LEN 415256#define MC_CMD_RDWR_A64_REGIONS_IN_REGION2_OFST 815257#define MC_CMD_RDWR_A64_REGIONS_IN_REGION2_LEN 415258#define MC_CMD_RDWR_A64_REGIONS_IN_REGION3_OFST 1215259#define MC_CMD_RDWR_A64_REGIONS_IN_REGION3_LEN 415260/* Write enable bits 0-3, set to write, clear to read. */15261#define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_LBN 12815262#define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_WIDTH 415263#define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_BYTE_OFST 1615264#define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_BYTE_LEN 115265 15266/* MC_CMD_RDWR_A64_REGIONS_OUT msgresponse: This data always included15267 * regardless of state of write bits in the request.15268 */15269#define MC_CMD_RDWR_A64_REGIONS_OUT_LEN 1615270#define MC_CMD_RDWR_A64_REGIONS_OUT_REGION0_OFST 015271#define MC_CMD_RDWR_A64_REGIONS_OUT_REGION0_LEN 415272#define MC_CMD_RDWR_A64_REGIONS_OUT_REGION1_OFST 415273#define MC_CMD_RDWR_A64_REGIONS_OUT_REGION1_LEN 415274#define MC_CMD_RDWR_A64_REGIONS_OUT_REGION2_OFST 815275#define MC_CMD_RDWR_A64_REGIONS_OUT_REGION2_LEN 415276#define MC_CMD_RDWR_A64_REGIONS_OUT_REGION3_OFST 1215277#define MC_CMD_RDWR_A64_REGIONS_OUT_REGION3_LEN 415278 15279 15280/***********************************/15281/* MC_CMD_ONLOAD_STACK_ALLOC15282 * Allocate an Onload stack ID.15283 */15284#define MC_CMD_ONLOAD_STACK_ALLOC 0x9c15285#undef MC_CMD_0x9c_PRIVILEGE_CTG15286 15287#define MC_CMD_0x9c_PRIVILEGE_CTG SRIOV_CTG_ONLOAD15288 15289/* MC_CMD_ONLOAD_STACK_ALLOC_IN msgrequest */15290#define MC_CMD_ONLOAD_STACK_ALLOC_IN_LEN 415291/* The handle of the owning upstream port */15292#define MC_CMD_ONLOAD_STACK_ALLOC_IN_UPSTREAM_PORT_ID_OFST 015293#define MC_CMD_ONLOAD_STACK_ALLOC_IN_UPSTREAM_PORT_ID_LEN 415294 15295/* MC_CMD_ONLOAD_STACK_ALLOC_OUT msgresponse */15296#define MC_CMD_ONLOAD_STACK_ALLOC_OUT_LEN 415297/* The handle of the new Onload stack */15298#define MC_CMD_ONLOAD_STACK_ALLOC_OUT_ONLOAD_STACK_ID_OFST 015299#define MC_CMD_ONLOAD_STACK_ALLOC_OUT_ONLOAD_STACK_ID_LEN 415300 15301 15302/***********************************/15303/* MC_CMD_ONLOAD_STACK_FREE15304 * Free an Onload stack ID.15305 */15306#define MC_CMD_ONLOAD_STACK_FREE 0x9d15307#undef MC_CMD_0x9d_PRIVILEGE_CTG15308 15309#define MC_CMD_0x9d_PRIVILEGE_CTG SRIOV_CTG_ONLOAD15310 15311/* MC_CMD_ONLOAD_STACK_FREE_IN msgrequest */15312#define MC_CMD_ONLOAD_STACK_FREE_IN_LEN 415313/* The handle of the Onload stack */15314#define MC_CMD_ONLOAD_STACK_FREE_IN_ONLOAD_STACK_ID_OFST 015315#define MC_CMD_ONLOAD_STACK_FREE_IN_ONLOAD_STACK_ID_LEN 415316 15317/* MC_CMD_ONLOAD_STACK_FREE_OUT msgresponse */15318#define MC_CMD_ONLOAD_STACK_FREE_OUT_LEN 015319 15320 15321/***********************************/15322/* MC_CMD_RSS_CONTEXT_ALLOC15323 * Allocate an RSS context.15324 */15325#define MC_CMD_RSS_CONTEXT_ALLOC 0x9e15326#undef MC_CMD_0x9e_PRIVILEGE_CTG15327 15328#define MC_CMD_0x9e_PRIVILEGE_CTG SRIOV_CTG_GENERAL15329 15330/* MC_CMD_RSS_CONTEXT_ALLOC_IN msgrequest */15331#define MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN 1215332/* The handle of the owning upstream port */15333#define MC_CMD_RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID_OFST 015334#define MC_CMD_RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID_LEN 415335/* The type of context to allocate */15336#define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_OFST 415337#define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_LEN 415338/* enum: Allocate a context for exclusive use. The key and indirection table15339 * must be explicitly configured.15340 */15341#define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE 0x015342/* enum: Allocate a context for shared use; this will spread across a range of15343 * queues, but the key and indirection table are pre-configured and may not be15344 * changed. For this mode, NUM_QUEUES must 2, 4, 8, 16, 32 or 64.15345 */15346#define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_SHARED 0x115347/* enum: Allocate a context to spread evenly across an arbitrary number of15348 * queues. No indirection table space is allocated for this context. (EF100 and15349 * later)15350 */15351#define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EVEN_SPREADING 0x215352/* Number of queues spanned by this context. For exclusive contexts this must15353 * be in the range 1 to RSS_MAX_INDIRECTION_QUEUES, where15354 * RSS_MAX_INDIRECTION_QUEUES is queried from MC_CMD_GET_CAPABILITIES_V9 or if15355 * V9 is not supported then RSS_MAX_INDIRECTION_QUEUES is 64. Valid entries in15356 * the indirection table will be in the range 0 to NUM_QUEUES-1. For even-15357 * spreading contexts this must be in the range 1 to15358 * RSS_MAX_EVEN_SPREADING_QUEUES as queried from MC_CMD_GET_CAPABILITIES. Note15359 * that specifying NUM_QUEUES = 1 will not perform any spreading but may still15360 * be useful as a way of obtaining the Toeplitz hash.15361 */15362#define MC_CMD_RSS_CONTEXT_ALLOC_IN_NUM_QUEUES_OFST 815363#define MC_CMD_RSS_CONTEXT_ALLOC_IN_NUM_QUEUES_LEN 415364 15365/* MC_CMD_RSS_CONTEXT_ALLOC_V2_IN msgrequest */15366#define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_LEN 1615367/* The handle of the owning upstream port */15368#define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_UPSTREAM_PORT_ID_OFST 015369#define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_UPSTREAM_PORT_ID_LEN 415370/* The type of context to allocate */15371#define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_TYPE_OFST 415372#define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_TYPE_LEN 415373/* enum: Allocate a context for exclusive use. The key and indirection table15374 * must be explicitly configured.15375 */15376#define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_TYPE_EXCLUSIVE 0x015377/* enum: Allocate a context for shared use; this will spread across a range of15378 * queues, but the key and indirection table are pre-configured and may not be15379 * changed. For this mode, NUM_QUEUES must 2, 4, 8, 16, 32 or 64.15380 */15381#define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_TYPE_SHARED 0x115382/* enum: Allocate a context to spread evenly across an arbitrary number of15383 * queues. No indirection table space is allocated for this context. (EF100 and15384 * later)15385 */15386#define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_TYPE_EVEN_SPREADING 0x215387/* Number of queues spanned by this context. For exclusive contexts this must15388 * be in the range 1 to RSS_MAX_INDIRECTION_QUEUES, where15389 * RSS_MAX_INDIRECTION_QUEUES is queried from MC_CMD_GET_CAPABILITIES_V9 or if15390 * V9 is not supported then RSS_MAX_INDIRECTION_QUEUES is 64. Valid entries in15391 * the indirection table will be in the range 0 to NUM_QUEUES-1. For even-15392 * spreading contexts this must be in the range 1 to15393 * RSS_MAX_EVEN_SPREADING_QUEUES as queried from MC_CMD_GET_CAPABILITIES. Note15394 * that specifying NUM_QUEUES = 1 will not perform any spreading but may still15395 * be useful as a way of obtaining the Toeplitz hash.15396 */15397#define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_NUM_QUEUES_OFST 815398#define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_NUM_QUEUES_LEN 415399/* Size of indirection table to be allocated to this context from the pool.15400 * Must be a power of 2. The minimum and maximum table size can be queried15401 * using MC_CMD_GET_CAPABILITIES_V9. If there is not enough space remaining in15402 * the common pool to allocate the requested table size, due to allocating15403 * table space to other RSS contexts, then the command will fail with15404 * MC_CMD_ERR_ENOSPC.15405 */15406#define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_INDIRECTION_TABLE_SIZE_OFST 1215407#define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_INDIRECTION_TABLE_SIZE_LEN 415408 15409/* MC_CMD_RSS_CONTEXT_ALLOC_OUT msgresponse */15410#define MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN 415411/* The handle of the new RSS context. This should be considered opaque to the15412 * host, although a value of 0xFFFFFFFF is guaranteed never to be a valid15413 * handle.15414 */15415#define MC_CMD_RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID_OFST 015416#define MC_CMD_RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID_LEN 415417/* enum: guaranteed invalid RSS context handle value */15418#define MC_CMD_RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID_INVALID 0xffffffff15419 15420 15421/***********************************/15422/* MC_CMD_RSS_CONTEXT_FREE15423 * Free an RSS context.15424 */15425#define MC_CMD_RSS_CONTEXT_FREE 0x9f15426#undef MC_CMD_0x9f_PRIVILEGE_CTG15427 15428#define MC_CMD_0x9f_PRIVILEGE_CTG SRIOV_CTG_GENERAL15429 15430/* MC_CMD_RSS_CONTEXT_FREE_IN msgrequest */15431#define MC_CMD_RSS_CONTEXT_FREE_IN_LEN 415432/* The handle of the RSS context */15433#define MC_CMD_RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID_OFST 015434#define MC_CMD_RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID_LEN 415435 15436/* MC_CMD_RSS_CONTEXT_FREE_OUT msgresponse */15437#define MC_CMD_RSS_CONTEXT_FREE_OUT_LEN 015438 15439 15440/***********************************/15441/* MC_CMD_RSS_CONTEXT_SET_KEY15442 * Set the Toeplitz hash key for an RSS context.15443 */15444#define MC_CMD_RSS_CONTEXT_SET_KEY 0xa015445#undef MC_CMD_0xa0_PRIVILEGE_CTG15446 15447#define MC_CMD_0xa0_PRIVILEGE_CTG SRIOV_CTG_GENERAL15448 15449/* MC_CMD_RSS_CONTEXT_SET_KEY_IN msgrequest */15450#define MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN 4415451/* The handle of the RSS context */15452#define MC_CMD_RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID_OFST 015453#define MC_CMD_RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID_LEN 415454/* The 40-byte Toeplitz hash key (TBD endianness issues?) */15455#define MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_OFST 415456#define MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN 4015457 15458/* MC_CMD_RSS_CONTEXT_SET_KEY_OUT msgresponse */15459#define MC_CMD_RSS_CONTEXT_SET_KEY_OUT_LEN 015460 15461 15462/***********************************/15463/* MC_CMD_RSS_CONTEXT_GET_KEY15464 * Get the Toeplitz hash key for an RSS context.15465 */15466#define MC_CMD_RSS_CONTEXT_GET_KEY 0xa115467#undef MC_CMD_0xa1_PRIVILEGE_CTG15468 15469#define MC_CMD_0xa1_PRIVILEGE_CTG SRIOV_CTG_GENERAL15470 15471/* MC_CMD_RSS_CONTEXT_GET_KEY_IN msgrequest */15472#define MC_CMD_RSS_CONTEXT_GET_KEY_IN_LEN 415473/* The handle of the RSS context */15474#define MC_CMD_RSS_CONTEXT_GET_KEY_IN_RSS_CONTEXT_ID_OFST 015475#define MC_CMD_RSS_CONTEXT_GET_KEY_IN_RSS_CONTEXT_ID_LEN 415476 15477/* MC_CMD_RSS_CONTEXT_GET_KEY_OUT msgresponse */15478#define MC_CMD_RSS_CONTEXT_GET_KEY_OUT_LEN 4415479/* The 40-byte Toeplitz hash key (TBD endianness issues?) */15480#define MC_CMD_RSS_CONTEXT_GET_KEY_OUT_TOEPLITZ_KEY_OFST 415481#define MC_CMD_RSS_CONTEXT_GET_KEY_OUT_TOEPLITZ_KEY_LEN 4015482 15483 15484/***********************************/15485/* MC_CMD_RSS_CONTEXT_SET_TABLE15486 * Set the indirection table for an RSS context. This command should only be15487 * used with indirection tables containing 128 entries, which is the default15488 * when the RSS context is allocated without specifying a table size.15489 */15490#define MC_CMD_RSS_CONTEXT_SET_TABLE 0xa215491#undef MC_CMD_0xa2_PRIVILEGE_CTG15492 15493#define MC_CMD_0xa2_PRIVILEGE_CTG SRIOV_CTG_GENERAL15494 15495/* MC_CMD_RSS_CONTEXT_SET_TABLE_IN msgrequest */15496#define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN 13215497/* The handle of the RSS context */15498#define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID_OFST 015499#define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID_LEN 415500/* The 128-byte indirection table (1 byte per entry) */15501#define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_OFST 415502#define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_LEN 12815503 15504/* MC_CMD_RSS_CONTEXT_SET_TABLE_OUT msgresponse */15505#define MC_CMD_RSS_CONTEXT_SET_TABLE_OUT_LEN 015506 15507 15508/***********************************/15509/* MC_CMD_RSS_CONTEXT_GET_TABLE15510 * Get the indirection table for an RSS context. This command should only be15511 * used with indirection tables containing 128 entries, which is the default15512 * when the RSS context is allocated without specifying a table size.15513 */15514#define MC_CMD_RSS_CONTEXT_GET_TABLE 0xa315515#undef MC_CMD_0xa3_PRIVILEGE_CTG15516 15517#define MC_CMD_0xa3_PRIVILEGE_CTG SRIOV_CTG_GENERAL15518 15519/* MC_CMD_RSS_CONTEXT_GET_TABLE_IN msgrequest */15520#define MC_CMD_RSS_CONTEXT_GET_TABLE_IN_LEN 415521/* The handle of the RSS context */15522#define MC_CMD_RSS_CONTEXT_GET_TABLE_IN_RSS_CONTEXT_ID_OFST 015523#define MC_CMD_RSS_CONTEXT_GET_TABLE_IN_RSS_CONTEXT_ID_LEN 415524 15525/* MC_CMD_RSS_CONTEXT_GET_TABLE_OUT msgresponse */15526#define MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_LEN 13215527/* The 128-byte indirection table (1 byte per entry) */15528#define MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_INDIRECTION_TABLE_OFST 415529#define MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_INDIRECTION_TABLE_LEN 12815530 15531 15532/***********************************/15533/* MC_CMD_RSS_CONTEXT_WRITE_TABLE15534 * Write a portion of a selectable-size indirection table for an RSS context.15535 * This command must be used instead of MC_CMD_RSS_CONTEXT_SET_TABLE if the15536 * RSS_SELECTABLE_TABLE_SIZE bit is set in MC_CMD_GET_CAPABILITIES.15537 */15538#define MC_CMD_RSS_CONTEXT_WRITE_TABLE 0x13e15539#undef MC_CMD_0x13e_PRIVILEGE_CTG15540 15541#define MC_CMD_0x13e_PRIVILEGE_CTG SRIOV_CTG_GENERAL15542 15543/* MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN msgrequest */15544#define MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_LENMIN 815545#define MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_LENMAX 25215546#define MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_LENMAX_MCDI2 102015547#define MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_LEN(num) (4+4*(num))15548#define MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_ENTRIES_NUM(len) (((len)-4)/4)15549/* The handle of the RSS context */15550#define MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_RSS_CONTEXT_ID_OFST 015551#define MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_RSS_CONTEXT_ID_LEN 415552/* An array of index-value pairs to be written to the table. Structure is15553 * MC_CMD_RSS_CONTEXT_WRITE_TABLE_ENTRY.15554 */15555#define MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_ENTRIES_OFST 415556#define MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_ENTRIES_LEN 415557#define MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_ENTRIES_MINNUM 115558#define MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_ENTRIES_MAXNUM 6215559#define MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_ENTRIES_MAXNUM_MCDI2 25415560 15561/* MC_CMD_RSS_CONTEXT_WRITE_TABLE_OUT msgresponse */15562#define MC_CMD_RSS_CONTEXT_WRITE_TABLE_OUT_LEN 015563 15564/* MC_CMD_RSS_CONTEXT_WRITE_TABLE_ENTRY structuredef */15565#define MC_CMD_RSS_CONTEXT_WRITE_TABLE_ENTRY_LEN 415566/* The index of the table entry to be written. */15567#define MC_CMD_RSS_CONTEXT_WRITE_TABLE_ENTRY_INDEX_OFST 015568#define MC_CMD_RSS_CONTEXT_WRITE_TABLE_ENTRY_INDEX_LEN 215569#define MC_CMD_RSS_CONTEXT_WRITE_TABLE_ENTRY_INDEX_LBN 015570#define MC_CMD_RSS_CONTEXT_WRITE_TABLE_ENTRY_INDEX_WIDTH 1615571/* The value to write into the table entry. */15572#define MC_CMD_RSS_CONTEXT_WRITE_TABLE_ENTRY_VALUE_OFST 215573#define MC_CMD_RSS_CONTEXT_WRITE_TABLE_ENTRY_VALUE_LEN 215574#define MC_CMD_RSS_CONTEXT_WRITE_TABLE_ENTRY_VALUE_LBN 1615575#define MC_CMD_RSS_CONTEXT_WRITE_TABLE_ENTRY_VALUE_WIDTH 1615576 15577 15578/***********************************/15579/* MC_CMD_RSS_CONTEXT_READ_TABLE15580 * Read a portion of a selectable-size indirection table for an RSS context.15581 * This command must be used instead of MC_CMD_RSS_CONTEXT_GET_TABLE if the15582 * RSS_SELECTABLE_TABLE_SIZE bit is set in MC_CMD_GET_CAPABILITIES.15583 */15584#define MC_CMD_RSS_CONTEXT_READ_TABLE 0x13f15585#undef MC_CMD_0x13f_PRIVILEGE_CTG15586 15587#define MC_CMD_0x13f_PRIVILEGE_CTG SRIOV_CTG_GENERAL15588 15589/* MC_CMD_RSS_CONTEXT_READ_TABLE_IN msgrequest */15590#define MC_CMD_RSS_CONTEXT_READ_TABLE_IN_LENMIN 615591#define MC_CMD_RSS_CONTEXT_READ_TABLE_IN_LENMAX 25215592#define MC_CMD_RSS_CONTEXT_READ_TABLE_IN_LENMAX_MCDI2 102015593#define MC_CMD_RSS_CONTEXT_READ_TABLE_IN_LEN(num) (4+2*(num))15594#define MC_CMD_RSS_CONTEXT_READ_TABLE_IN_INDICES_NUM(len) (((len)-4)/2)15595/* The handle of the RSS context */15596#define MC_CMD_RSS_CONTEXT_READ_TABLE_IN_RSS_CONTEXT_ID_OFST 015597#define MC_CMD_RSS_CONTEXT_READ_TABLE_IN_RSS_CONTEXT_ID_LEN 415598/* An array containing the indices of the entries to be read. */15599#define MC_CMD_RSS_CONTEXT_READ_TABLE_IN_INDICES_OFST 415600#define MC_CMD_RSS_CONTEXT_READ_TABLE_IN_INDICES_LEN 215601#define MC_CMD_RSS_CONTEXT_READ_TABLE_IN_INDICES_MINNUM 115602#define MC_CMD_RSS_CONTEXT_READ_TABLE_IN_INDICES_MAXNUM 12415603#define MC_CMD_RSS_CONTEXT_READ_TABLE_IN_INDICES_MAXNUM_MCDI2 50815604 15605/* MC_CMD_RSS_CONTEXT_READ_TABLE_OUT msgresponse */15606#define MC_CMD_RSS_CONTEXT_READ_TABLE_OUT_LENMIN 215607#define MC_CMD_RSS_CONTEXT_READ_TABLE_OUT_LENMAX 25215608#define MC_CMD_RSS_CONTEXT_READ_TABLE_OUT_LENMAX_MCDI2 102015609#define MC_CMD_RSS_CONTEXT_READ_TABLE_OUT_LEN(num) (0+2*(num))15610#define MC_CMD_RSS_CONTEXT_READ_TABLE_OUT_DATA_NUM(len) (((len)-0)/2)15611/* A buffer containing the requested entries read from the table. */15612#define MC_CMD_RSS_CONTEXT_READ_TABLE_OUT_DATA_OFST 015613#define MC_CMD_RSS_CONTEXT_READ_TABLE_OUT_DATA_LEN 215614#define MC_CMD_RSS_CONTEXT_READ_TABLE_OUT_DATA_MINNUM 115615#define MC_CMD_RSS_CONTEXT_READ_TABLE_OUT_DATA_MAXNUM 12615616#define MC_CMD_RSS_CONTEXT_READ_TABLE_OUT_DATA_MAXNUM_MCDI2 51015617 15618 15619/***********************************/15620/* MC_CMD_RSS_CONTEXT_SET_FLAGS15621 * Set various control flags for an RSS context.15622 */15623#define MC_CMD_RSS_CONTEXT_SET_FLAGS 0xe115624#undef MC_CMD_0xe1_PRIVILEGE_CTG15625 15626#define MC_CMD_0xe1_PRIVILEGE_CTG SRIOV_CTG_GENERAL15627 15628/* MC_CMD_RSS_CONTEXT_SET_FLAGS_IN msgrequest */15629#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_LEN 815630/* The handle of the RSS context */15631#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RSS_CONTEXT_ID_OFST 015632#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RSS_CONTEXT_ID_LEN 415633/* Hash control flags. The _EN bits are always supported, but new modes are15634 * available when ADDITIONAL_RSS_MODES is reported by MC_CMD_GET_CAPABILITIES:15635 * in this case, the MODE fields may be set to non-zero values, and will take15636 * effect regardless of the settings of the _EN flags. See the RSS_MODE15637 * structure for the meaning of the mode bits. Drivers must check the15638 * capability before trying to set any _MODE fields, as older firmware will15639 * reject any attempt to set the FLAGS field to a value > 0xff with EINVAL. In15640 * the case where all the _MODE flags are zero, the _EN flags take effect,15641 * providing backward compatibility for existing drivers. (Setting all _MODE15642 * *and* all _EN flags to zero is valid, to disable RSS spreading for that15643 * particular packet type.)15644 */15645#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_FLAGS_OFST 415646#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_FLAGS_LEN 415647#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV4_EN_OFST 415648#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV4_EN_LBN 015649#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV4_EN_WIDTH 115650#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV4_EN_OFST 415651#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV4_EN_LBN 115652#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV4_EN_WIDTH 115653#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV6_EN_OFST 415654#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV6_EN_LBN 215655#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV6_EN_WIDTH 115656#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV6_EN_OFST 415657#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV6_EN_LBN 315658#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV6_EN_WIDTH 115659#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RESERVED_OFST 415660#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RESERVED_LBN 415661#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RESERVED_WIDTH 415662#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV4_RSS_MODE_OFST 415663#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV4_RSS_MODE_LBN 815664#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV4_RSS_MODE_WIDTH 415665#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV4_RSS_MODE_OFST 415666#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV4_RSS_MODE_LBN 1215667#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV4_RSS_MODE_WIDTH 415668#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV4_RSS_MODE_OFST 415669#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV4_RSS_MODE_LBN 1615670#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV4_RSS_MODE_WIDTH 415671#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV6_RSS_MODE_OFST 415672#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV6_RSS_MODE_LBN 2015673#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV6_RSS_MODE_WIDTH 415674#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV6_RSS_MODE_OFST 415675#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV6_RSS_MODE_LBN 2415676#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV6_RSS_MODE_WIDTH 415677#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV6_RSS_MODE_OFST 415678#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV6_RSS_MODE_LBN 2815679#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV6_RSS_MODE_WIDTH 415680 15681/* MC_CMD_RSS_CONTEXT_SET_FLAGS_OUT msgresponse */15682#define MC_CMD_RSS_CONTEXT_SET_FLAGS_OUT_LEN 015683 15684 15685/***********************************/15686/* MC_CMD_RSS_CONTEXT_GET_FLAGS15687 * Get various control flags for an RSS context.15688 */15689#define MC_CMD_RSS_CONTEXT_GET_FLAGS 0xe215690#undef MC_CMD_0xe2_PRIVILEGE_CTG15691 15692#define MC_CMD_0xe2_PRIVILEGE_CTG SRIOV_CTG_GENERAL15693 15694/* MC_CMD_RSS_CONTEXT_GET_FLAGS_IN msgrequest */15695#define MC_CMD_RSS_CONTEXT_GET_FLAGS_IN_LEN 415696/* The handle of the RSS context */15697#define MC_CMD_RSS_CONTEXT_GET_FLAGS_IN_RSS_CONTEXT_ID_OFST 015698#define MC_CMD_RSS_CONTEXT_GET_FLAGS_IN_RSS_CONTEXT_ID_LEN 415699 15700/* MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT msgresponse */15701#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_LEN 815702/* Hash control flags. If all _MODE bits are zero (which will always be true15703 * for older firmware which does not report the ADDITIONAL_RSS_MODES15704 * capability), the _EN bits report the state. If any _MODE bits are non-zero15705 * (which will only be true when the firmware reports ADDITIONAL_RSS_MODES)15706 * then the _EN bits should be disregarded, although the _MODE flags are15707 * guaranteed to be consistent with the _EN flags for a freshly-allocated RSS15708 * context and in the case where the _EN flags were used in the SET. This15709 * provides backward compatibility: old drivers will not be attempting to15710 * derive any meaning from the _MODE bits (and can never set them to any value15711 * not representable by the _EN bits); new drivers can always determine the15712 * mode by looking only at the _MODE bits; the value returned by a GET can15713 * always be used for a SET regardless of old/new driver vs. old/new firmware.15714 */15715#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_FLAGS_OFST 415716#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_FLAGS_LEN 415717#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV4_EN_OFST 415718#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV4_EN_LBN 015719#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV4_EN_WIDTH 115720#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV4_EN_OFST 415721#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV4_EN_LBN 115722#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV4_EN_WIDTH 115723#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV6_EN_OFST 415724#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV6_EN_LBN 215725#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV6_EN_WIDTH 115726#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV6_EN_OFST 415727#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV6_EN_LBN 315728#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV6_EN_WIDTH 115729#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_RESERVED_OFST 415730#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_RESERVED_LBN 415731#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_RESERVED_WIDTH 415732#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV4_RSS_MODE_OFST 415733#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV4_RSS_MODE_LBN 815734#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV4_RSS_MODE_WIDTH 415735#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV4_RSS_MODE_OFST 415736#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV4_RSS_MODE_LBN 1215737#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV4_RSS_MODE_WIDTH 415738#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV4_RSS_MODE_OFST 415739#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV4_RSS_MODE_LBN 1615740#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV4_RSS_MODE_WIDTH 415741#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV6_RSS_MODE_OFST 415742#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV6_RSS_MODE_LBN 2015743#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV6_RSS_MODE_WIDTH 415744#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV6_RSS_MODE_OFST 415745#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV6_RSS_MODE_LBN 2415746#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV6_RSS_MODE_WIDTH 415747#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV6_RSS_MODE_OFST 415748#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV6_RSS_MODE_LBN 2815749#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV6_RSS_MODE_WIDTH 415750 15751 15752/***********************************/15753/* MC_CMD_VPORT_ADD_MAC_ADDRESS15754 * Add a MAC address to a v-port15755 */15756#define MC_CMD_VPORT_ADD_MAC_ADDRESS 0xa815757#undef MC_CMD_0xa8_PRIVILEGE_CTG15758 15759#define MC_CMD_0xa8_PRIVILEGE_CTG SRIOV_CTG_GENERAL15760 15761/* MC_CMD_VPORT_ADD_MAC_ADDRESS_IN msgrequest */15762#define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_LEN 1015763/* The handle of the v-port */15764#define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_VPORT_ID_OFST 015765#define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_VPORT_ID_LEN 415766/* MAC address to add */15767#define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_MACADDR_OFST 415768#define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_MACADDR_LEN 615769 15770/* MC_CMD_VPORT_ADD_MAC_ADDRESS_OUT msgresponse */15771#define MC_CMD_VPORT_ADD_MAC_ADDRESS_OUT_LEN 015772 15773 15774/***********************************/15775/* MC_CMD_VPORT_DEL_MAC_ADDRESS15776 * Delete a MAC address from a v-port15777 */15778#define MC_CMD_VPORT_DEL_MAC_ADDRESS 0xa915779#undef MC_CMD_0xa9_PRIVILEGE_CTG15780 15781#define MC_CMD_0xa9_PRIVILEGE_CTG SRIOV_CTG_GENERAL15782 15783/* MC_CMD_VPORT_DEL_MAC_ADDRESS_IN msgrequest */15784#define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_LEN 1015785/* The handle of the v-port */15786#define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_VPORT_ID_OFST 015787#define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_VPORT_ID_LEN 415788/* MAC address to add */15789#define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_MACADDR_OFST 415790#define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_MACADDR_LEN 615791 15792/* MC_CMD_VPORT_DEL_MAC_ADDRESS_OUT msgresponse */15793#define MC_CMD_VPORT_DEL_MAC_ADDRESS_OUT_LEN 015794 15795 15796/***********************************/15797/* MC_CMD_VPORT_GET_MAC_ADDRESSES15798 * Delete a MAC address from a v-port15799 */15800#define MC_CMD_VPORT_GET_MAC_ADDRESSES 0xaa15801#undef MC_CMD_0xaa_PRIVILEGE_CTG15802 15803#define MC_CMD_0xaa_PRIVILEGE_CTG SRIOV_CTG_GENERAL15804 15805/* MC_CMD_VPORT_GET_MAC_ADDRESSES_IN msgrequest */15806#define MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN 415807/* The handle of the v-port */15808#define MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID_OFST 015809#define MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID_LEN 415810 15811/* MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT msgresponse */15812#define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN 415813#define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX 25015814#define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX_MCDI2 101815815#define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LEN(num) (4+6*(num))15816#define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_NUM(len) (((len)-4)/6)15817/* The number of MAC addresses returned */15818#define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT_OFST 015819#define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT_LEN 415820/* Array of MAC addresses */15821#define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_OFST 415822#define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_LEN 615823#define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_MINNUM 015824#define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_MAXNUM 4115825#define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_MAXNUM_MCDI2 16915826 15827 15828/***********************************/15829/* MC_CMD_VPORT_RECONFIGURE15830 * Replace VLAN tags and/or MAC addresses of an existing v-port. If the v-port15831 * has already been passed to another function (v-port's user), then that15832 * function will be reset before applying the changes.15833 */15834#define MC_CMD_VPORT_RECONFIGURE 0xeb15835#undef MC_CMD_0xeb_PRIVILEGE_CTG15836 15837#define MC_CMD_0xeb_PRIVILEGE_CTG SRIOV_CTG_GENERAL15838 15839/* MC_CMD_VPORT_RECONFIGURE_IN msgrequest */15840#define MC_CMD_VPORT_RECONFIGURE_IN_LEN 4415841/* The handle of the v-port */15842#define MC_CMD_VPORT_RECONFIGURE_IN_VPORT_ID_OFST 015843#define MC_CMD_VPORT_RECONFIGURE_IN_VPORT_ID_LEN 415844/* Flags requesting what should be changed. */15845#define MC_CMD_VPORT_RECONFIGURE_IN_FLAGS_OFST 415846#define MC_CMD_VPORT_RECONFIGURE_IN_FLAGS_LEN 415847#define MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_VLAN_TAGS_OFST 415848#define MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_VLAN_TAGS_LBN 015849#define MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_VLAN_TAGS_WIDTH 115850#define MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_MACADDRS_OFST 415851#define MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_MACADDRS_LBN 115852#define MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_MACADDRS_WIDTH 115853/* The number of VLAN tags to insert/remove. An error will be returned if15854 * incompatible with the number of VLAN tags specified for the upstream15855 * v-switch.15856 */15857#define MC_CMD_VPORT_RECONFIGURE_IN_NUM_VLAN_TAGS_OFST 815858#define MC_CMD_VPORT_RECONFIGURE_IN_NUM_VLAN_TAGS_LEN 415859/* The actual VLAN tags to insert/remove */15860#define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAGS_OFST 1215861#define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAGS_LEN 415862#define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_0_OFST 1215863#define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_0_LBN 015864#define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_0_WIDTH 1615865#define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_1_OFST 1215866#define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_1_LBN 1615867#define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_1_WIDTH 1615868/* The number of MAC addresses to add */15869#define MC_CMD_VPORT_RECONFIGURE_IN_NUM_MACADDRS_OFST 1615870#define MC_CMD_VPORT_RECONFIGURE_IN_NUM_MACADDRS_LEN 415871/* MAC addresses to add */15872#define MC_CMD_VPORT_RECONFIGURE_IN_MACADDRS_OFST 2015873#define MC_CMD_VPORT_RECONFIGURE_IN_MACADDRS_LEN 615874#define MC_CMD_VPORT_RECONFIGURE_IN_MACADDRS_NUM 415875 15876/* MC_CMD_VPORT_RECONFIGURE_OUT msgresponse */15877#define MC_CMD_VPORT_RECONFIGURE_OUT_LEN 415878#define MC_CMD_VPORT_RECONFIGURE_OUT_FLAGS_OFST 015879#define MC_CMD_VPORT_RECONFIGURE_OUT_FLAGS_LEN 415880#define MC_CMD_VPORT_RECONFIGURE_OUT_RESET_DONE_OFST 015881#define MC_CMD_VPORT_RECONFIGURE_OUT_RESET_DONE_LBN 015882#define MC_CMD_VPORT_RECONFIGURE_OUT_RESET_DONE_WIDTH 115883 15884 15885/***********************************/15886/* MC_CMD_EVB_PORT_QUERY15887 * read some config of v-port.15888 */15889#define MC_CMD_EVB_PORT_QUERY 0x6215890#undef MC_CMD_0x62_PRIVILEGE_CTG15891 15892#define MC_CMD_0x62_PRIVILEGE_CTG SRIOV_CTG_GENERAL15893 15894/* MC_CMD_EVB_PORT_QUERY_IN msgrequest */15895#define MC_CMD_EVB_PORT_QUERY_IN_LEN 415896/* The handle of the v-port */15897#define MC_CMD_EVB_PORT_QUERY_IN_PORT_ID_OFST 015898#define MC_CMD_EVB_PORT_QUERY_IN_PORT_ID_LEN 415899 15900/* MC_CMD_EVB_PORT_QUERY_OUT msgresponse */15901#define MC_CMD_EVB_PORT_QUERY_OUT_LEN 815902/* The EVB port flags as defined at MC_CMD_VPORT_ALLOC. */15903#define MC_CMD_EVB_PORT_QUERY_OUT_PORT_FLAGS_OFST 015904#define MC_CMD_EVB_PORT_QUERY_OUT_PORT_FLAGS_LEN 415905/* The number of VLAN tags that may be used on a v-adaptor connected to this15906 * EVB port.15907 */15908#define MC_CMD_EVB_PORT_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS_OFST 415909#define MC_CMD_EVB_PORT_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS_LEN 415910 15911 15912/***********************************/15913/* MC_CMD_GET_CLOCK15914 * Return the system and PDCPU clock frequencies.15915 */15916#define MC_CMD_GET_CLOCK 0xac15917#undef MC_CMD_0xac_PRIVILEGE_CTG15918 15919#define MC_CMD_0xac_PRIVILEGE_CTG SRIOV_CTG_GENERAL15920 15921/* MC_CMD_GET_CLOCK_IN msgrequest */15922#define MC_CMD_GET_CLOCK_IN_LEN 015923 15924/* MC_CMD_GET_CLOCK_OUT msgresponse */15925#define MC_CMD_GET_CLOCK_OUT_LEN 815926/* System frequency, MHz */15927#define MC_CMD_GET_CLOCK_OUT_SYS_FREQ_OFST 015928#define MC_CMD_GET_CLOCK_OUT_SYS_FREQ_LEN 415929/* DPCPU frequency, MHz */15930#define MC_CMD_GET_CLOCK_OUT_DPCPU_FREQ_OFST 415931#define MC_CMD_GET_CLOCK_OUT_DPCPU_FREQ_LEN 415932 15933 15934/***********************************/15935/* MC_CMD_TRIGGER_INTERRUPT15936 * Trigger an interrupt by prodding the BIU.15937 */15938#define MC_CMD_TRIGGER_INTERRUPT 0xe315939#undef MC_CMD_0xe3_PRIVILEGE_CTG15940 15941#define MC_CMD_0xe3_PRIVILEGE_CTG SRIOV_CTG_GENERAL15942 15943/* MC_CMD_TRIGGER_INTERRUPT_IN msgrequest */15944#define MC_CMD_TRIGGER_INTERRUPT_IN_LEN 415945/* Interrupt level relative to base for function. */15946#define MC_CMD_TRIGGER_INTERRUPT_IN_INTR_LEVEL_OFST 015947#define MC_CMD_TRIGGER_INTERRUPT_IN_INTR_LEVEL_LEN 415948 15949/* MC_CMD_TRIGGER_INTERRUPT_OUT msgresponse */15950#define MC_CMD_TRIGGER_INTERRUPT_OUT_LEN 015951 15952 15953/***********************************/15954/* MC_CMD_SHMBOOT_OP15955 * Special operations to support (for now) shmboot.15956 */15957#define MC_CMD_SHMBOOT_OP 0xe615958#undef MC_CMD_0xe6_PRIVILEGE_CTG15959 15960#define MC_CMD_0xe6_PRIVILEGE_CTG SRIOV_CTG_ADMIN15961 15962/* MC_CMD_SHMBOOT_OP_IN msgrequest */15963#define MC_CMD_SHMBOOT_OP_IN_LEN 415964/* Identifies the operation to perform */15965#define MC_CMD_SHMBOOT_OP_IN_SHMBOOT_OP_OFST 015966#define MC_CMD_SHMBOOT_OP_IN_SHMBOOT_OP_LEN 415967/* enum: Copy slave_data section to the slave core. (Greenport only) */15968#define MC_CMD_SHMBOOT_OP_IN_PUSH_SLAVE_DATA 0x015969 15970/* MC_CMD_SHMBOOT_OP_OUT msgresponse */15971#define MC_CMD_SHMBOOT_OP_OUT_LEN 015972 15973 15974/***********************************/15975/* MC_CMD_SET_PSU15976 * Adjusts power supply parameters. This is a warranty-voiding operation.15977 * Returns: ENOENT if the parameter or rail specified does not exist, EINVAL if15978 * the parameter is out of range.15979 */15980#define MC_CMD_SET_PSU 0xea15981#undef MC_CMD_0xea_PRIVILEGE_CTG15982 15983#define MC_CMD_0xea_PRIVILEGE_CTG SRIOV_CTG_INSECURE15984 15985/* MC_CMD_SET_PSU_IN msgrequest */15986#define MC_CMD_SET_PSU_IN_LEN 1215987#define MC_CMD_SET_PSU_IN_PARAM_OFST 015988#define MC_CMD_SET_PSU_IN_PARAM_LEN 415989#define MC_CMD_SET_PSU_IN_PARAM_SUPPLY_VOLTAGE 0x0 /* enum */15990#define MC_CMD_SET_PSU_IN_RAIL_OFST 415991#define MC_CMD_SET_PSU_IN_RAIL_LEN 415992#define MC_CMD_SET_PSU_IN_RAIL_0V9 0x0 /* enum */15993#define MC_CMD_SET_PSU_IN_RAIL_1V2 0x1 /* enum */15994/* desired value, eg voltage in mV */15995#define MC_CMD_SET_PSU_IN_VALUE_OFST 815996#define MC_CMD_SET_PSU_IN_VALUE_LEN 415997 15998/* MC_CMD_SET_PSU_OUT msgresponse */15999#define MC_CMD_SET_PSU_OUT_LEN 016000 16001 16002/***********************************/16003/* MC_CMD_GET_FUNCTION_INFO16004 * Get function information. PF and VF number.16005 */16006#define MC_CMD_GET_FUNCTION_INFO 0xec16007#undef MC_CMD_0xec_PRIVILEGE_CTG16008 16009#define MC_CMD_0xec_PRIVILEGE_CTG SRIOV_CTG_GENERAL16010 16011/* MC_CMD_GET_FUNCTION_INFO_IN msgrequest */16012#define MC_CMD_GET_FUNCTION_INFO_IN_LEN 016013 16014/* MC_CMD_GET_FUNCTION_INFO_OUT msgresponse */16015#define MC_CMD_GET_FUNCTION_INFO_OUT_LEN 816016#define MC_CMD_GET_FUNCTION_INFO_OUT_PF_OFST 016017#define MC_CMD_GET_FUNCTION_INFO_OUT_PF_LEN 416018#define MC_CMD_GET_FUNCTION_INFO_OUT_VF_OFST 416019#define MC_CMD_GET_FUNCTION_INFO_OUT_VF_LEN 416020 16021 16022/***********************************/16023/* MC_CMD_ENABLE_OFFLINE_BIST16024 * Enters offline BIST mode. All queues are torn down, chip enters quiescent16025 * mode, calling function gets exclusive MCDI ownership. The only way out is16026 * reboot.16027 */16028#define MC_CMD_ENABLE_OFFLINE_BIST 0xed16029#undef MC_CMD_0xed_PRIVILEGE_CTG16030 16031#define MC_CMD_0xed_PRIVILEGE_CTG SRIOV_CTG_ADMIN16032 16033/* MC_CMD_ENABLE_OFFLINE_BIST_IN msgrequest */16034#define MC_CMD_ENABLE_OFFLINE_BIST_IN_LEN 016035 16036/* MC_CMD_ENABLE_OFFLINE_BIST_OUT msgresponse */16037#define MC_CMD_ENABLE_OFFLINE_BIST_OUT_LEN 016038 16039 16040/***********************************/16041/* MC_CMD_READ_FUSES16042 * Read data programmed into the device One-Time-Programmable (OTP) Fuses16043 */16044#define MC_CMD_READ_FUSES 0xf016045#undef MC_CMD_0xf0_PRIVILEGE_CTG16046 16047#define MC_CMD_0xf0_PRIVILEGE_CTG SRIOV_CTG_INSECURE16048 16049/* MC_CMD_READ_FUSES_IN msgrequest */16050#define MC_CMD_READ_FUSES_IN_LEN 816051/* Offset in OTP to read */16052#define MC_CMD_READ_FUSES_IN_OFFSET_OFST 016053#define MC_CMD_READ_FUSES_IN_OFFSET_LEN 416054/* Length of data to read in bytes */16055#define MC_CMD_READ_FUSES_IN_LENGTH_OFST 416056#define MC_CMD_READ_FUSES_IN_LENGTH_LEN 416057 16058/* MC_CMD_READ_FUSES_OUT msgresponse */16059#define MC_CMD_READ_FUSES_OUT_LENMIN 416060#define MC_CMD_READ_FUSES_OUT_LENMAX 25216061#define MC_CMD_READ_FUSES_OUT_LENMAX_MCDI2 102016062#define MC_CMD_READ_FUSES_OUT_LEN(num) (4+1*(num))16063#define MC_CMD_READ_FUSES_OUT_DATA_NUM(len) (((len)-4)/1)16064/* Length of returned OTP data in bytes */16065#define MC_CMD_READ_FUSES_OUT_LENGTH_OFST 016066#define MC_CMD_READ_FUSES_OUT_LENGTH_LEN 416067/* Returned data */16068#define MC_CMD_READ_FUSES_OUT_DATA_OFST 416069#define MC_CMD_READ_FUSES_OUT_DATA_LEN 116070#define MC_CMD_READ_FUSES_OUT_DATA_MINNUM 016071#define MC_CMD_READ_FUSES_OUT_DATA_MAXNUM 24816072#define MC_CMD_READ_FUSES_OUT_DATA_MAXNUM_MCDI2 101616073 16074 16075/***********************************/16076/* MC_CMD_LICENSING16077 * Operations on the NVRAM_PARTITION_TYPE_LICENSE application license partition16078 * - not used for V3 licensing16079 */16080#define MC_CMD_LICENSING 0xf316081#undef MC_CMD_0xf3_PRIVILEGE_CTG16082 16083#define MC_CMD_0xf3_PRIVILEGE_CTG SRIOV_CTG_GENERAL16084 16085/* MC_CMD_LICENSING_IN msgrequest */16086#define MC_CMD_LICENSING_IN_LEN 416087/* identifies the type of operation requested */16088#define MC_CMD_LICENSING_IN_OP_OFST 016089#define MC_CMD_LICENSING_IN_OP_LEN 416090/* enum: re-read and apply licenses after a license key partition update; note16091 * that this operation returns a zero-length response16092 */16093#define MC_CMD_LICENSING_IN_OP_UPDATE_LICENSE 0x016094/* enum: report counts of installed licenses */16095#define MC_CMD_LICENSING_IN_OP_GET_KEY_STATS 0x116096 16097/* MC_CMD_LICENSING_OUT msgresponse */16098#define MC_CMD_LICENSING_OUT_LEN 2816099/* count of application keys which are valid */16100#define MC_CMD_LICENSING_OUT_VALID_APP_KEYS_OFST 016101#define MC_CMD_LICENSING_OUT_VALID_APP_KEYS_LEN 416102/* sum of UNVERIFIABLE_APP_KEYS + WRONG_NODE_APP_KEYS (for compatibility with16103 * MC_CMD_FC_OP_LICENSE)16104 */16105#define MC_CMD_LICENSING_OUT_INVALID_APP_KEYS_OFST 416106#define MC_CMD_LICENSING_OUT_INVALID_APP_KEYS_LEN 416107/* count of application keys which are invalid due to being blacklisted */16108#define MC_CMD_LICENSING_OUT_BLACKLISTED_APP_KEYS_OFST 816109#define MC_CMD_LICENSING_OUT_BLACKLISTED_APP_KEYS_LEN 416110/* count of application keys which are invalid due to being unverifiable */16111#define MC_CMD_LICENSING_OUT_UNVERIFIABLE_APP_KEYS_OFST 1216112#define MC_CMD_LICENSING_OUT_UNVERIFIABLE_APP_KEYS_LEN 416113/* count of application keys which are invalid due to being for the wrong node16114 */16115#define MC_CMD_LICENSING_OUT_WRONG_NODE_APP_KEYS_OFST 1616116#define MC_CMD_LICENSING_OUT_WRONG_NODE_APP_KEYS_LEN 416117/* licensing state (for diagnostics; the exact meaning of the bits in this16118 * field are private to the firmware)16119 */16120#define MC_CMD_LICENSING_OUT_LICENSING_STATE_OFST 2016121#define MC_CMD_LICENSING_OUT_LICENSING_STATE_LEN 416122/* licensing subsystem self-test report (for manftest) */16123#define MC_CMD_LICENSING_OUT_LICENSING_SELF_TEST_OFST 2416124#define MC_CMD_LICENSING_OUT_LICENSING_SELF_TEST_LEN 416125/* enum: licensing subsystem self-test failed */16126#define MC_CMD_LICENSING_OUT_SELF_TEST_FAIL 0x016127/* enum: licensing subsystem self-test passed */16128#define MC_CMD_LICENSING_OUT_SELF_TEST_PASS 0x116129 16130 16131/***********************************/16132/* MC_CMD_LICENSING_V316133 * Operations on the NVRAM_PARTITION_TYPE_LICENSE application license partition16134 * - V3 licensing (Medford)16135 */16136#define MC_CMD_LICENSING_V3 0xd016137#undef MC_CMD_0xd0_PRIVILEGE_CTG16138 16139#define MC_CMD_0xd0_PRIVILEGE_CTG SRIOV_CTG_GENERAL16140 16141/* MC_CMD_LICENSING_V3_IN msgrequest */16142#define MC_CMD_LICENSING_V3_IN_LEN 416143/* identifies the type of operation requested */16144#define MC_CMD_LICENSING_V3_IN_OP_OFST 016145#define MC_CMD_LICENSING_V3_IN_OP_LEN 416146/* enum: re-read and apply licenses after a license key partition update; note16147 * that this operation returns a zero-length response16148 */16149#define MC_CMD_LICENSING_V3_IN_OP_UPDATE_LICENSE 0x016150/* enum: report counts of installed licenses Returns EAGAIN if license16151 * processing (updating) has been started but not yet completed.16152 */16153#define MC_CMD_LICENSING_V3_IN_OP_REPORT_LICENSE 0x116154 16155/* MC_CMD_LICENSING_V3_OUT msgresponse */16156#define MC_CMD_LICENSING_V3_OUT_LEN 8816157/* count of keys which are valid */16158#define MC_CMD_LICENSING_V3_OUT_VALID_KEYS_OFST 016159#define MC_CMD_LICENSING_V3_OUT_VALID_KEYS_LEN 416160/* sum of UNVERIFIABLE_KEYS + WRONG_NODE_KEYS (for compatibility with16161 * MC_CMD_FC_OP_LICENSE)16162 */16163#define MC_CMD_LICENSING_V3_OUT_INVALID_KEYS_OFST 416164#define MC_CMD_LICENSING_V3_OUT_INVALID_KEYS_LEN 416165/* count of keys which are invalid due to being unverifiable */16166#define MC_CMD_LICENSING_V3_OUT_UNVERIFIABLE_KEYS_OFST 816167#define MC_CMD_LICENSING_V3_OUT_UNVERIFIABLE_KEYS_LEN 416168/* count of keys which are invalid due to being for the wrong node */16169#define MC_CMD_LICENSING_V3_OUT_WRONG_NODE_KEYS_OFST 1216170#define MC_CMD_LICENSING_V3_OUT_WRONG_NODE_KEYS_LEN 416171/* licensing state (for diagnostics; the exact meaning of the bits in this16172 * field are private to the firmware)16173 */16174#define MC_CMD_LICENSING_V3_OUT_LICENSING_STATE_OFST 1616175#define MC_CMD_LICENSING_V3_OUT_LICENSING_STATE_LEN 416176/* licensing subsystem self-test report (for manftest) */16177#define MC_CMD_LICENSING_V3_OUT_LICENSING_SELF_TEST_OFST 2016178#define MC_CMD_LICENSING_V3_OUT_LICENSING_SELF_TEST_LEN 416179/* enum: licensing subsystem self-test failed */16180#define MC_CMD_LICENSING_V3_OUT_SELF_TEST_FAIL 0x016181/* enum: licensing subsystem self-test passed */16182#define MC_CMD_LICENSING_V3_OUT_SELF_TEST_PASS 0x116183/* bitmask of licensed applications */16184#define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_OFST 2416185#define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_LEN 816186#define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_LO_OFST 2416187#define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_HI_OFST 2816188/* reserved for future use */16189#define MC_CMD_LICENSING_V3_OUT_RESERVED_0_OFST 3216190#define MC_CMD_LICENSING_V3_OUT_RESERVED_0_LEN 2416191/* bitmask of licensed features */16192#define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_OFST 5616193#define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_LEN 816194#define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_LO_OFST 5616195#define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_HI_OFST 6016196/* reserved for future use */16197#define MC_CMD_LICENSING_V3_OUT_RESERVED_1_OFST 6416198#define MC_CMD_LICENSING_V3_OUT_RESERVED_1_LEN 2416199 16200 16201/***********************************/16202/* MC_CMD_LICENSING_GET_ID_V316203 * Get ID and type from the NVRAM_PARTITION_TYPE_LICENSE application license16204 * partition - V3 licensing (Medford)16205 */16206#define MC_CMD_LICENSING_GET_ID_V3 0xd116207#undef MC_CMD_0xd1_PRIVILEGE_CTG16208 16209#define MC_CMD_0xd1_PRIVILEGE_CTG SRIOV_CTG_GENERAL16210 16211/* MC_CMD_LICENSING_GET_ID_V3_IN msgrequest */16212#define MC_CMD_LICENSING_GET_ID_V3_IN_LEN 016213 16214/* MC_CMD_LICENSING_GET_ID_V3_OUT msgresponse */16215#define MC_CMD_LICENSING_GET_ID_V3_OUT_LENMIN 816216#define MC_CMD_LICENSING_GET_ID_V3_OUT_LENMAX 25216217#define MC_CMD_LICENSING_GET_ID_V3_OUT_LENMAX_MCDI2 102016218#define MC_CMD_LICENSING_GET_ID_V3_OUT_LEN(num) (8+1*(num))16219#define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_NUM(len) (((len)-8)/1)16220/* type of license (eg 3) */16221#define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_TYPE_OFST 016222#define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_TYPE_LEN 416223/* length of the license ID (in bytes) */16224#define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_LENGTH_OFST 416225#define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_LENGTH_LEN 416226/* the unique license ID of the adapter */16227#define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_OFST 816228#define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_LEN 116229#define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_MINNUM 016230#define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_MAXNUM 24416231#define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_MAXNUM_MCDI2 101216232 16233 16234/***********************************/16235/* MC_CMD_GET_LICENSED_APP_STATE16236 * Query the state of an individual licensed application. (Note that the actual16237 * state may be invalidated by the MC_CMD_LICENSING OP_UPDATE_LICENSE operation16238 * or a reboot of the MC.) Not used for V3 licensing16239 */16240#define MC_CMD_GET_LICENSED_APP_STATE 0xf516241#undef MC_CMD_0xf5_PRIVILEGE_CTG16242 16243#define MC_CMD_0xf5_PRIVILEGE_CTG SRIOV_CTG_GENERAL16244 16245/* MC_CMD_GET_LICENSED_APP_STATE_IN msgrequest */16246#define MC_CMD_GET_LICENSED_APP_STATE_IN_LEN 416247/* application ID to query (LICENSED_APP_ID_xxx) */16248#define MC_CMD_GET_LICENSED_APP_STATE_IN_APP_ID_OFST 016249#define MC_CMD_GET_LICENSED_APP_STATE_IN_APP_ID_LEN 416250 16251/* MC_CMD_GET_LICENSED_APP_STATE_OUT msgresponse */16252#define MC_CMD_GET_LICENSED_APP_STATE_OUT_LEN 416253/* state of this application */16254#define MC_CMD_GET_LICENSED_APP_STATE_OUT_STATE_OFST 016255#define MC_CMD_GET_LICENSED_APP_STATE_OUT_STATE_LEN 416256/* enum: no (or invalid) license is present for the application */16257#define MC_CMD_GET_LICENSED_APP_STATE_OUT_NOT_LICENSED 0x016258/* enum: a valid license is present for the application */16259#define MC_CMD_GET_LICENSED_APP_STATE_OUT_LICENSED 0x116260 16261 16262/***********************************/16263/* MC_CMD_GET_LICENSED_V3_APP_STATE16264 * Query the state of an individual licensed application. (Note that the actual16265 * state may be invalidated by the MC_CMD_LICENSING_V3 OP_UPDATE_LICENSE16266 * operation or a reboot of the MC.) Used for V3 licensing (Medford)16267 */16268#define MC_CMD_GET_LICENSED_V3_APP_STATE 0xd216269#undef MC_CMD_0xd2_PRIVILEGE_CTG16270 16271#define MC_CMD_0xd2_PRIVILEGE_CTG SRIOV_CTG_GENERAL16272 16273/* MC_CMD_GET_LICENSED_V3_APP_STATE_IN msgrequest */16274#define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_LEN 816275/* application ID to query (LICENSED_V3_APPS_xxx) expressed as a single bit16276 * mask16277 */16278#define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_OFST 016279#define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_LEN 816280#define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_LO_OFST 016281#define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_HI_OFST 416282 16283/* MC_CMD_GET_LICENSED_V3_APP_STATE_OUT msgresponse */16284#define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_LEN 416285/* state of this application */16286#define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_STATE_OFST 016287#define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_STATE_LEN 416288/* enum: no (or invalid) license is present for the application */16289#define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_NOT_LICENSED 0x016290/* enum: a valid license is present for the application */16291#define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_LICENSED 0x116292 16293 16294/***********************************/16295/* MC_CMD_GET_LICENSED_V3_FEATURE_STATES16296 * Query the state of an one or more licensed features. (Note that the actual16297 * state may be invalidated by the MC_CMD_LICENSING_V3 OP_UPDATE_LICENSE16298 * operation or a reboot of the MC.) Used for V3 licensing (Medford)16299 */16300#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES 0xd316301#undef MC_CMD_0xd3_PRIVILEGE_CTG16302 16303#define MC_CMD_0xd3_PRIVILEGE_CTG SRIOV_CTG_GENERAL16304 16305/* MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN msgrequest */16306#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_LEN 816307/* features to query (LICENSED_V3_FEATURES_xxx) expressed as a mask with one or16308 * more bits set16309 */16310#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_OFST 016311#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_LEN 816312#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_LO_OFST 016313#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_HI_OFST 416314 16315/* MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT msgresponse */16316#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_LEN 816317/* states of these features - bit set for licensed, clear for not licensed */16318#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_OFST 016319#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_LEN 816320#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_LO_OFST 016321#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_HI_OFST 416322 16323 16324/***********************************/16325/* MC_CMD_LICENSED_APP_OP16326 * Perform an action for an individual licensed application - not used for V316327 * licensing.16328 */16329#define MC_CMD_LICENSED_APP_OP 0xf616330#undef MC_CMD_0xf6_PRIVILEGE_CTG16331 16332#define MC_CMD_0xf6_PRIVILEGE_CTG SRIOV_CTG_GENERAL16333 16334/* MC_CMD_LICENSED_APP_OP_IN msgrequest */16335#define MC_CMD_LICENSED_APP_OP_IN_LENMIN 816336#define MC_CMD_LICENSED_APP_OP_IN_LENMAX 25216337#define MC_CMD_LICENSED_APP_OP_IN_LENMAX_MCDI2 102016338#define MC_CMD_LICENSED_APP_OP_IN_LEN(num) (8+4*(num))16339#define MC_CMD_LICENSED_APP_OP_IN_ARGS_NUM(len) (((len)-8)/4)16340/* application ID */16341#define MC_CMD_LICENSED_APP_OP_IN_APP_ID_OFST 016342#define MC_CMD_LICENSED_APP_OP_IN_APP_ID_LEN 416343/* the type of operation requested */16344#define MC_CMD_LICENSED_APP_OP_IN_OP_OFST 416345#define MC_CMD_LICENSED_APP_OP_IN_OP_LEN 416346/* enum: validate application */16347#define MC_CMD_LICENSED_APP_OP_IN_OP_VALIDATE 0x016348/* enum: mask application */16349#define MC_CMD_LICENSED_APP_OP_IN_OP_MASK 0x116350/* arguments specific to this particular operation */16351#define MC_CMD_LICENSED_APP_OP_IN_ARGS_OFST 816352#define MC_CMD_LICENSED_APP_OP_IN_ARGS_LEN 416353#define MC_CMD_LICENSED_APP_OP_IN_ARGS_MINNUM 016354#define MC_CMD_LICENSED_APP_OP_IN_ARGS_MAXNUM 6116355#define MC_CMD_LICENSED_APP_OP_IN_ARGS_MAXNUM_MCDI2 25316356 16357/* MC_CMD_LICENSED_APP_OP_OUT msgresponse */16358#define MC_CMD_LICENSED_APP_OP_OUT_LENMIN 016359#define MC_CMD_LICENSED_APP_OP_OUT_LENMAX 25216360#define MC_CMD_LICENSED_APP_OP_OUT_LENMAX_MCDI2 102016361#define MC_CMD_LICENSED_APP_OP_OUT_LEN(num) (0+4*(num))16362#define MC_CMD_LICENSED_APP_OP_OUT_RESULT_NUM(len) (((len)-0)/4)16363/* result specific to this particular operation */16364#define MC_CMD_LICENSED_APP_OP_OUT_RESULT_OFST 016365#define MC_CMD_LICENSED_APP_OP_OUT_RESULT_LEN 416366#define MC_CMD_LICENSED_APP_OP_OUT_RESULT_MINNUM 016367#define MC_CMD_LICENSED_APP_OP_OUT_RESULT_MAXNUM 6316368#define MC_CMD_LICENSED_APP_OP_OUT_RESULT_MAXNUM_MCDI2 25516369 16370/* MC_CMD_LICENSED_APP_OP_VALIDATE_IN msgrequest */16371#define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_LEN 7216372/* application ID */16373#define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_APP_ID_OFST 016374#define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_APP_ID_LEN 416375/* the type of operation requested */16376#define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_OP_OFST 416377#define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_OP_LEN 416378/* validation challenge */16379#define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_CHALLENGE_OFST 816380#define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_CHALLENGE_LEN 6416381 16382/* MC_CMD_LICENSED_APP_OP_VALIDATE_OUT msgresponse */16383#define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_LEN 6816384/* feature expiry (time_t) */16385#define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_EXPIRY_OFST 016386#define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_EXPIRY_LEN 416387/* validation response */16388#define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_RESPONSE_OFST 416389#define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_RESPONSE_LEN 6416390 16391/* MC_CMD_LICENSED_APP_OP_MASK_IN msgrequest */16392#define MC_CMD_LICENSED_APP_OP_MASK_IN_LEN 1216393/* application ID */16394#define MC_CMD_LICENSED_APP_OP_MASK_IN_APP_ID_OFST 016395#define MC_CMD_LICENSED_APP_OP_MASK_IN_APP_ID_LEN 416396/* the type of operation requested */16397#define MC_CMD_LICENSED_APP_OP_MASK_IN_OP_OFST 416398#define MC_CMD_LICENSED_APP_OP_MASK_IN_OP_LEN 416399/* flag */16400#define MC_CMD_LICENSED_APP_OP_MASK_IN_FLAG_OFST 816401#define MC_CMD_LICENSED_APP_OP_MASK_IN_FLAG_LEN 416402 16403/* MC_CMD_LICENSED_APP_OP_MASK_OUT msgresponse */16404#define MC_CMD_LICENSED_APP_OP_MASK_OUT_LEN 016405 16406 16407/***********************************/16408/* MC_CMD_LICENSED_V3_VALIDATE_APP16409 * Perform validation for an individual licensed application - V3 licensing16410 * (Medford)16411 */16412#define MC_CMD_LICENSED_V3_VALIDATE_APP 0xd416413#undef MC_CMD_0xd4_PRIVILEGE_CTG16414 16415#define MC_CMD_0xd4_PRIVILEGE_CTG SRIOV_CTG_GENERAL16416 16417/* MC_CMD_LICENSED_V3_VALIDATE_APP_IN msgrequest */16418#define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_LEN 5616419/* challenge for validation (384 bits) */16420#define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_CHALLENGE_OFST 016421#define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_CHALLENGE_LEN 4816422/* application ID expressed as a single bit mask */16423#define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_OFST 4816424#define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_LEN 816425#define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_LO_OFST 4816426#define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_HI_OFST 5216427 16428/* MC_CMD_LICENSED_V3_VALIDATE_APP_OUT msgresponse */16429#define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_LEN 11616430/* validation response to challenge in the form of ECDSA signature consisting16431 * of two 384-bit integers, r and s, in big-endian order. The signature signs a16432 * SHA-384 digest of a message constructed from the concatenation of the input16433 * message and the remaining fields of this output message, e.g. challenge[4816434 * bytes] ... expiry_time[4 bytes] ...16435 */16436#define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_RESPONSE_OFST 016437#define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_RESPONSE_LEN 9616438/* application expiry time */16439#define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_TIME_OFST 9616440#define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_TIME_LEN 416441/* application expiry units */16442#define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_UNITS_OFST 10016443#define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_UNITS_LEN 416444/* enum: expiry units are accounting units */16445#define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_UNIT_ACC 0x016446/* enum: expiry units are calendar days */16447#define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_UNIT_DAYS 0x116448/* base MAC address of the NIC stored in NVRAM (note that this is a constant16449 * value for a given NIC regardless which function is calling, effectively this16450 * is PF0 base MAC address)16451 */16452#define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_BASE_MACADDR_OFST 10416453#define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_BASE_MACADDR_LEN 616454/* MAC address of v-adaptor associated with the client. If no such v-adapator16455 * exists, then the field is filled with 0xFF.16456 */16457#define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_VADAPTOR_MACADDR_OFST 11016458#define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_VADAPTOR_MACADDR_LEN 616459 16460 16461/***********************************/16462/* MC_CMD_LICENSED_V3_MASK_FEATURES16463 * Mask features - V3 licensing (Medford)16464 */16465#define MC_CMD_LICENSED_V3_MASK_FEATURES 0xd516466#undef MC_CMD_0xd5_PRIVILEGE_CTG16467 16468#define MC_CMD_0xd5_PRIVILEGE_CTG SRIOV_CTG_ADMIN16469 16470/* MC_CMD_LICENSED_V3_MASK_FEATURES_IN msgrequest */16471#define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_LEN 1216472/* mask to be applied to features to be changed */16473#define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_OFST 016474#define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_LEN 816475#define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_LO_OFST 016476#define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_HI_OFST 416477/* whether to turn on or turn off the masked features */16478#define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_FLAG_OFST 816479#define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_FLAG_LEN 416480/* enum: turn the features off */16481#define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_OFF 0x016482/* enum: turn the features back on */16483#define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_ON 0x116484 16485/* MC_CMD_LICENSED_V3_MASK_FEATURES_OUT msgresponse */16486#define MC_CMD_LICENSED_V3_MASK_FEATURES_OUT_LEN 016487 16488 16489/***********************************/16490/* MC_CMD_LICENSING_V3_TEMPORARY16491 * Perform operations to support installation of a single temporary license in16492 * the adapter, in addition to those found in the licensing partition. See16493 * SF-116124-SW for an overview of how this could be used. The license is16494 * stored in MC persistent data and so will survive a MC reboot, but will be16495 * erased when the adapter is power cycled16496 */16497#define MC_CMD_LICENSING_V3_TEMPORARY 0xd616498#undef MC_CMD_0xd6_PRIVILEGE_CTG16499 16500#define MC_CMD_0xd6_PRIVILEGE_CTG SRIOV_CTG_ADMIN16501 16502/* MC_CMD_LICENSING_V3_TEMPORARY_IN msgrequest */16503#define MC_CMD_LICENSING_V3_TEMPORARY_IN_LEN 416504/* operation code */16505#define MC_CMD_LICENSING_V3_TEMPORARY_IN_OP_OFST 016506#define MC_CMD_LICENSING_V3_TEMPORARY_IN_OP_LEN 416507/* enum: install a new license, overwriting any existing temporary license.16508 * This is an asynchronous operation owing to the time taken to validate an16509 * ECDSA license16510 */16511#define MC_CMD_LICENSING_V3_TEMPORARY_SET 0x016512/* enum: clear the license immediately rather than waiting for the next power16513 * cycle16514 */16515#define MC_CMD_LICENSING_V3_TEMPORARY_CLEAR 0x116516/* enum: get the status of the asynchronous MC_CMD_LICENSING_V3_TEMPORARY_SET16517 * operation16518 */16519#define MC_CMD_LICENSING_V3_TEMPORARY_STATUS 0x216520 16521/* MC_CMD_LICENSING_V3_TEMPORARY_IN_SET msgrequest */16522#define MC_CMD_LICENSING_V3_TEMPORARY_IN_SET_LEN 16416523#define MC_CMD_LICENSING_V3_TEMPORARY_IN_SET_OP_OFST 016524#define MC_CMD_LICENSING_V3_TEMPORARY_IN_SET_OP_LEN 416525/* ECDSA license and signature */16526#define MC_CMD_LICENSING_V3_TEMPORARY_IN_SET_LICENSE_OFST 416527#define MC_CMD_LICENSING_V3_TEMPORARY_IN_SET_LICENSE_LEN 16016528 16529/* MC_CMD_LICENSING_V3_TEMPORARY_IN_CLEAR msgrequest */16530#define MC_CMD_LICENSING_V3_TEMPORARY_IN_CLEAR_LEN 416531#define MC_CMD_LICENSING_V3_TEMPORARY_IN_CLEAR_OP_OFST 016532#define MC_CMD_LICENSING_V3_TEMPORARY_IN_CLEAR_OP_LEN 416533 16534/* MC_CMD_LICENSING_V3_TEMPORARY_IN_STATUS msgrequest */16535#define MC_CMD_LICENSING_V3_TEMPORARY_IN_STATUS_LEN 416536#define MC_CMD_LICENSING_V3_TEMPORARY_IN_STATUS_OP_OFST 016537#define MC_CMD_LICENSING_V3_TEMPORARY_IN_STATUS_OP_LEN 416538 16539/* MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS msgresponse */16540#define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LEN 1216541/* status code */16542#define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_STATUS_OFST 016543#define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_STATUS_LEN 416544/* enum: finished validating and installing license */16545#define MC_CMD_LICENSING_V3_TEMPORARY_STATUS_OK 0x016546/* enum: license validation and installation in progress */16547#define MC_CMD_LICENSING_V3_TEMPORARY_STATUS_IN_PROGRESS 0x116548/* enum: licensing error. More specific error messages are not provided to16549 * avoid exposing details of the licensing system to the client16550 */16551#define MC_CMD_LICENSING_V3_TEMPORARY_STATUS_ERROR 0x216552/* bitmask of licensed features */16553#define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_OFST 416554#define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_LEN 816555#define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_LO_OFST 416556#define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_HI_OFST 816557 16558 16559/***********************************/16560/* MC_CMD_SET_PARSER_DISP_CONFIG16561 * Change configuration related to the parser-dispatcher subsystem.16562 */16563#define MC_CMD_SET_PARSER_DISP_CONFIG 0xf916564#undef MC_CMD_0xf9_PRIVILEGE_CTG16565 16566#define MC_CMD_0xf9_PRIVILEGE_CTG SRIOV_CTG_GENERAL16567 16568/* MC_CMD_SET_PARSER_DISP_CONFIG_IN msgrequest */16569#define MC_CMD_SET_PARSER_DISP_CONFIG_IN_LENMIN 1216570#define MC_CMD_SET_PARSER_DISP_CONFIG_IN_LENMAX 25216571#define MC_CMD_SET_PARSER_DISP_CONFIG_IN_LENMAX_MCDI2 102016572#define MC_CMD_SET_PARSER_DISP_CONFIG_IN_LEN(num) (8+4*(num))16573#define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_NUM(len) (((len)-8)/4)16574/* the type of configuration setting to change */16575#define MC_CMD_SET_PARSER_DISP_CONFIG_IN_TYPE_OFST 016576#define MC_CMD_SET_PARSER_DISP_CONFIG_IN_TYPE_LEN 416577/* enum: Per-TXQ enable for multicast UDP destination lookup for possible16578 * internal loopback. (ENTITY is a queue handle, VALUE is a single boolean.)16579 */16580#define MC_CMD_SET_PARSER_DISP_CONFIG_IN_TXQ_MCAST_UDP_DST_LOOKUP_EN 0x016581/* enum: Per-v-adaptor enable for suppression of self-transmissions on the16582 * internal loopback path. (ENTITY is an EVB_PORT_ID, VALUE is a single16583 * boolean.)16584 */16585#define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VADAPTOR_SUPPRESS_SELF_TX 0x116586/* handle for the entity to update: queue handle, EVB port ID, etc. depending16587 * on the type of configuration setting being changed16588 */16589#define MC_CMD_SET_PARSER_DISP_CONFIG_IN_ENTITY_OFST 416590#define MC_CMD_SET_PARSER_DISP_CONFIG_IN_ENTITY_LEN 416591/* new value: the details depend on the type of configuration setting being16592 * changed16593 */16594#define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_OFST 816595#define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_LEN 416596#define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_MINNUM 116597#define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_MAXNUM 6116598#define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_MAXNUM_MCDI2 25316599 16600/* MC_CMD_SET_PARSER_DISP_CONFIG_OUT msgresponse */16601#define MC_CMD_SET_PARSER_DISP_CONFIG_OUT_LEN 016602 16603 16604/***********************************/16605/* MC_CMD_GET_PARSER_DISP_CONFIG16606 * Read configuration related to the parser-dispatcher subsystem.16607 */16608#define MC_CMD_GET_PARSER_DISP_CONFIG 0xfa16609#undef MC_CMD_0xfa_PRIVILEGE_CTG16610 16611#define MC_CMD_0xfa_PRIVILEGE_CTG SRIOV_CTG_GENERAL16612 16613/* MC_CMD_GET_PARSER_DISP_CONFIG_IN msgrequest */16614#define MC_CMD_GET_PARSER_DISP_CONFIG_IN_LEN 816615/* the type of configuration setting to read */16616#define MC_CMD_GET_PARSER_DISP_CONFIG_IN_TYPE_OFST 016617#define MC_CMD_GET_PARSER_DISP_CONFIG_IN_TYPE_LEN 416618/* Enum values, see field(s): */16619/* MC_CMD_SET_PARSER_DISP_CONFIG/MC_CMD_SET_PARSER_DISP_CONFIG_IN/TYPE */16620/* handle for the entity to query: queue handle, EVB port ID, etc. depending on16621 * the type of configuration setting being read16622 */16623#define MC_CMD_GET_PARSER_DISP_CONFIG_IN_ENTITY_OFST 416624#define MC_CMD_GET_PARSER_DISP_CONFIG_IN_ENTITY_LEN 416625 16626/* MC_CMD_GET_PARSER_DISP_CONFIG_OUT msgresponse */16627#define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_LENMIN 416628#define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_LENMAX 25216629#define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_LENMAX_MCDI2 102016630#define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_LEN(num) (0+4*(num))16631#define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_NUM(len) (((len)-0)/4)16632/* current value: the details depend on the type of configuration setting being16633 * read16634 */16635#define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_OFST 016636#define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_LEN 416637#define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_MINNUM 116638#define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_MAXNUM 6316639#define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_MAXNUM_MCDI2 25516640 16641 16642/***********************************/16643/* MC_CMD_GET_PORT_MODES16644 * Find out about available port modes16645 */16646#define MC_CMD_GET_PORT_MODES 0xff16647#undef MC_CMD_0xff_PRIVILEGE_CTG16648 16649#define MC_CMD_0xff_PRIVILEGE_CTG SRIOV_CTG_GENERAL16650 16651/* MC_CMD_GET_PORT_MODES_IN msgrequest */16652#define MC_CMD_GET_PORT_MODES_IN_LEN 016653 16654/* MC_CMD_GET_PORT_MODES_OUT msgresponse */16655#define MC_CMD_GET_PORT_MODES_OUT_LEN 1216656/* Bitmask of port modes available on the board (indexed by TLV_PORT_MODE_*)16657 * that are supported for customer use in production firmware.16658 */16659#define MC_CMD_GET_PORT_MODES_OUT_MODES_OFST 016660#define MC_CMD_GET_PORT_MODES_OUT_MODES_LEN 416661/* Default (canonical) board mode */16662#define MC_CMD_GET_PORT_MODES_OUT_DEFAULT_MODE_OFST 416663#define MC_CMD_GET_PORT_MODES_OUT_DEFAULT_MODE_LEN 416664/* Current board mode */16665#define MC_CMD_GET_PORT_MODES_OUT_CURRENT_MODE_OFST 816666#define MC_CMD_GET_PORT_MODES_OUT_CURRENT_MODE_LEN 416667 16668/* MC_CMD_GET_PORT_MODES_OUT_V2 msgresponse */16669#define MC_CMD_GET_PORT_MODES_OUT_V2_LEN 1616670/* Bitmask of port modes available on the board (indexed by TLV_PORT_MODE_*)16671 * that are supported for customer use in production firmware.16672 */16673#define MC_CMD_GET_PORT_MODES_OUT_V2_MODES_OFST 016674#define MC_CMD_GET_PORT_MODES_OUT_V2_MODES_LEN 416675/* Default (canonical) board mode */16676#define MC_CMD_GET_PORT_MODES_OUT_V2_DEFAULT_MODE_OFST 416677#define MC_CMD_GET_PORT_MODES_OUT_V2_DEFAULT_MODE_LEN 416678/* Current board mode */16679#define MC_CMD_GET_PORT_MODES_OUT_V2_CURRENT_MODE_OFST 816680#define MC_CMD_GET_PORT_MODES_OUT_V2_CURRENT_MODE_LEN 416681/* Bitmask of engineering port modes available on the board (indexed by16682 * TLV_PORT_MODE_*). A superset of MC_CMD_GET_PORT_MODES_OUT/MODES that16683 * contains all modes implemented in firmware for a particular board. Modes16684 * listed in MODES are considered production modes and should be exposed in16685 * userland tools. Modes listed in ENGINEERING_MODES, but not in MODES16686 * should be considered hidden (not to be exposed in userland tools) and for16687 * engineering use only. There are no other semantic differences and any mode16688 * listed in either MODES or ENGINEERING_MODES can be set on the board.16689 */16690#define MC_CMD_GET_PORT_MODES_OUT_V2_ENGINEERING_MODES_OFST 1216691#define MC_CMD_GET_PORT_MODES_OUT_V2_ENGINEERING_MODES_LEN 416692 16693 16694/***********************************/16695/* MC_CMD_OVERRIDE_PORT_MODE16696 * Override flash config port mode for subsequent MC reboot(s). Override data16697 * is stored in the presistent data section of DMEM and activated on next MC16698 * warm reboot. A cold reboot resets the override. It is assumed that a16699 * sufficient number of PFs are available and that port mapping is valid for16700 * the new port mode, as the override does not affect PF configuration.16701 */16702#define MC_CMD_OVERRIDE_PORT_MODE 0x13716703#undef MC_CMD_0x137_PRIVILEGE_CTG16704 16705#define MC_CMD_0x137_PRIVILEGE_CTG SRIOV_CTG_ADMIN16706 16707/* MC_CMD_OVERRIDE_PORT_MODE_IN msgrequest */16708#define MC_CMD_OVERRIDE_PORT_MODE_IN_LEN 816709#define MC_CMD_OVERRIDE_PORT_MODE_IN_FLAGS_OFST 016710#define MC_CMD_OVERRIDE_PORT_MODE_IN_FLAGS_LEN 416711#define MC_CMD_OVERRIDE_PORT_MODE_IN_ENABLE_OFST 016712#define MC_CMD_OVERRIDE_PORT_MODE_IN_ENABLE_LBN 016713#define MC_CMD_OVERRIDE_PORT_MODE_IN_ENABLE_WIDTH 116714/* New mode (TLV_PORT_MODE_*) to set, if override enabled */16715#define MC_CMD_OVERRIDE_PORT_MODE_IN_MODE_OFST 416716#define MC_CMD_OVERRIDE_PORT_MODE_IN_MODE_LEN 416717 16718/* MC_CMD_OVERRIDE_PORT_MODE_OUT msgresponse */16719#define MC_CMD_OVERRIDE_PORT_MODE_OUT_LEN 016720 16721 16722/***********************************/16723/* MC_CMD_GET_WORKAROUNDS16724 * Read the list of all implemented and all currently enabled workarounds. The16725 * enums here must correspond with those in MC_CMD_WORKAROUND.16726 */16727#define MC_CMD_GET_WORKAROUNDS 0x5916728#undef MC_CMD_0x59_PRIVILEGE_CTG16729 16730#define MC_CMD_0x59_PRIVILEGE_CTG SRIOV_CTG_GENERAL16731 16732/* MC_CMD_GET_WORKAROUNDS_OUT msgresponse */16733#define MC_CMD_GET_WORKAROUNDS_OUT_LEN 816734/* Each workaround is represented by a single bit according to the enums below.16735 */16736#define MC_CMD_GET_WORKAROUNDS_OUT_IMPLEMENTED_OFST 016737#define MC_CMD_GET_WORKAROUNDS_OUT_IMPLEMENTED_LEN 416738#define MC_CMD_GET_WORKAROUNDS_OUT_ENABLED_OFST 416739#define MC_CMD_GET_WORKAROUNDS_OUT_ENABLED_LEN 416740/* enum: Bug 17230 work around. */16741#define MC_CMD_GET_WORKAROUNDS_OUT_BUG17230 0x216742/* enum: Bug 35388 work around (unsafe EVQ writes). */16743#define MC_CMD_GET_WORKAROUNDS_OUT_BUG35388 0x416744/* enum: Bug35017 workaround (A64 tables must be identity map) */16745#define MC_CMD_GET_WORKAROUNDS_OUT_BUG35017 0x816746/* enum: Bug 41750 present (MC_CMD_TRIGGER_INTERRUPT won't work) */16747#define MC_CMD_GET_WORKAROUNDS_OUT_BUG41750 0x1016748/* enum: Bug 42008 present (Interrupts can overtake associated events). Caution16749 * - before adding code that queries this workaround, remember that there's16750 * released Monza firmware that doesn't understand MC_CMD_WORKAROUND_BUG42008,16751 * and will hence (incorrectly) report that the bug doesn't exist.16752 */16753#define MC_CMD_GET_WORKAROUNDS_OUT_BUG42008 0x2016754/* enum: Bug 26807 features present in firmware (multicast filter chaining) */16755#define MC_CMD_GET_WORKAROUNDS_OUT_BUG26807 0x4016756/* enum: Bug 61265 work around (broken EVQ TMR writes). */16757#define MC_CMD_GET_WORKAROUNDS_OUT_BUG61265 0x8016758 16759 16760/***********************************/16761/* MC_CMD_PRIVILEGE_MASK16762 * Read/set privileges of an arbitrary PCIe function16763 */16764#define MC_CMD_PRIVILEGE_MASK 0x5a16765#undef MC_CMD_0x5a_PRIVILEGE_CTG16766 16767#define MC_CMD_0x5a_PRIVILEGE_CTG SRIOV_CTG_GENERAL16768 16769/* MC_CMD_PRIVILEGE_MASK_IN msgrequest */16770#define MC_CMD_PRIVILEGE_MASK_IN_LEN 816771/* The target function to have its mask read or set e.g. PF 0 = 0xFFFF0000, VF16772 * 1,3 = 0x0003000116773 */16774#define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_OFST 016775#define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_LEN 416776#define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_PF_OFST 016777#define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_PF_LBN 016778#define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_PF_WIDTH 1616779#define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_VF_OFST 016780#define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_VF_LBN 1616781#define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_VF_WIDTH 1616782#define MC_CMD_PRIVILEGE_MASK_IN_VF_NULL 0xffff /* enum */16783/* New privilege mask to be set. The mask will only be changed if the MSB is16784 * set to 1.16785 */16786#define MC_CMD_PRIVILEGE_MASK_IN_NEW_MASK_OFST 416787#define MC_CMD_PRIVILEGE_MASK_IN_NEW_MASK_LEN 416788#define MC_CMD_PRIVILEGE_MASK_IN_GRP_ADMIN 0x1 /* enum */16789#define MC_CMD_PRIVILEGE_MASK_IN_GRP_LINK 0x2 /* enum */16790#define MC_CMD_PRIVILEGE_MASK_IN_GRP_ONLOAD 0x4 /* enum */16791#define MC_CMD_PRIVILEGE_MASK_IN_GRP_PTP 0x8 /* enum */16792#define MC_CMD_PRIVILEGE_MASK_IN_GRP_INSECURE_FILTERS 0x10 /* enum */16793/* enum: Deprecated. Equivalent to MAC_SPOOFING_TX combined with CHANGE_MAC. */16794#define MC_CMD_PRIVILEGE_MASK_IN_GRP_MAC_SPOOFING 0x2016795#define MC_CMD_PRIVILEGE_MASK_IN_GRP_UNICAST 0x40 /* enum */16796#define MC_CMD_PRIVILEGE_MASK_IN_GRP_MULTICAST 0x80 /* enum */16797#define MC_CMD_PRIVILEGE_MASK_IN_GRP_BROADCAST 0x100 /* enum */16798#define MC_CMD_PRIVILEGE_MASK_IN_GRP_ALL_MULTICAST 0x200 /* enum */16799#define MC_CMD_PRIVILEGE_MASK_IN_GRP_PROMISCUOUS 0x400 /* enum */16800/* enum: Allows to set the TX packets' source MAC address to any arbitrary MAC16801 * adress.16802 */16803#define MC_CMD_PRIVILEGE_MASK_IN_GRP_MAC_SPOOFING_TX 0x80016804/* enum: Privilege that allows a Function to change the MAC address configured16805 * in its associated vAdapter/vPort.16806 */16807#define MC_CMD_PRIVILEGE_MASK_IN_GRP_CHANGE_MAC 0x100016808/* enum: Privilege that allows a Function to install filters that specify VLANs16809 * that are not in the permit list for the associated vPort. This privilege is16810 * primarily to support ESX where vPorts are created that restrict traffic to16811 * only a set of permitted VLANs. See the vPort flag FLAG_VLAN_RESTRICT.16812 */16813#define MC_CMD_PRIVILEGE_MASK_IN_GRP_UNRESTRICTED_VLAN 0x200016814/* enum: Privilege for insecure commands. Commands that belong to this group16815 * are not permitted on secure adapters regardless of the privilege mask.16816 */16817#define MC_CMD_PRIVILEGE_MASK_IN_GRP_INSECURE 0x400016818/* enum: Trusted Server Adapter (TSA) / ServerLock. Privilege for16819 * administrator-level operations that are not allowed from the local host once16820 * an adapter has Bound to a remote ServerLock Controller (see doxbox16821 * SF-117064-DG for background).16822 */16823#define MC_CMD_PRIVILEGE_MASK_IN_GRP_ADMIN_TSA_UNBOUND 0x800016824/* enum: Set this bit to indicate that a new privilege mask is to be set,16825 * otherwise the command will only read the existing mask.16826 */16827#define MC_CMD_PRIVILEGE_MASK_IN_DO_CHANGE 0x8000000016828 16829/* MC_CMD_PRIVILEGE_MASK_OUT msgresponse */16830#define MC_CMD_PRIVILEGE_MASK_OUT_LEN 416831/* For an admin function, always all the privileges are reported. */16832#define MC_CMD_PRIVILEGE_MASK_OUT_OLD_MASK_OFST 016833#define MC_CMD_PRIVILEGE_MASK_OUT_OLD_MASK_LEN 416834 16835 16836/***********************************/16837/* MC_CMD_LINK_STATE_MODE16838 * Read/set link state mode of a VF16839 */16840#define MC_CMD_LINK_STATE_MODE 0x5c16841#undef MC_CMD_0x5c_PRIVILEGE_CTG16842 16843#define MC_CMD_0x5c_PRIVILEGE_CTG SRIOV_CTG_GENERAL16844 16845/* MC_CMD_LINK_STATE_MODE_IN msgrequest */16846#define MC_CMD_LINK_STATE_MODE_IN_LEN 816847/* The target function to have its link state mode read or set, must be a VF16848 * e.g. VF 1,3 = 0x0003000116849 */16850#define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_OFST 016851#define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_LEN 416852#define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_PF_OFST 016853#define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_PF_LBN 016854#define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_PF_WIDTH 1616855#define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_VF_OFST 016856#define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_VF_LBN 1616857#define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_VF_WIDTH 1616858/* New link state mode to be set */16859#define MC_CMD_LINK_STATE_MODE_IN_NEW_MODE_OFST 416860#define MC_CMD_LINK_STATE_MODE_IN_NEW_MODE_LEN 416861#define MC_CMD_LINK_STATE_MODE_IN_LINK_STATE_AUTO 0x0 /* enum */16862#define MC_CMD_LINK_STATE_MODE_IN_LINK_STATE_UP 0x1 /* enum */16863#define MC_CMD_LINK_STATE_MODE_IN_LINK_STATE_DOWN 0x2 /* enum */16864/* enum: Use this value to just read the existing setting without modifying it.16865 */16866#define MC_CMD_LINK_STATE_MODE_IN_DO_NOT_CHANGE 0xffffffff16867 16868/* MC_CMD_LINK_STATE_MODE_OUT msgresponse */16869#define MC_CMD_LINK_STATE_MODE_OUT_LEN 416870#define MC_CMD_LINK_STATE_MODE_OUT_OLD_MODE_OFST 016871#define MC_CMD_LINK_STATE_MODE_OUT_OLD_MODE_LEN 416872 16873 16874/***********************************/16875/* MC_CMD_FUSE_DIAGS16876 * Additional fuse diagnostics16877 */16878#define MC_CMD_FUSE_DIAGS 0x10216879#undef MC_CMD_0x102_PRIVILEGE_CTG16880 16881#define MC_CMD_0x102_PRIVILEGE_CTG SRIOV_CTG_INSECURE16882 16883/* MC_CMD_FUSE_DIAGS_IN msgrequest */16884#define MC_CMD_FUSE_DIAGS_IN_LEN 016885 16886/* MC_CMD_FUSE_DIAGS_OUT msgresponse */16887#define MC_CMD_FUSE_DIAGS_OUT_LEN 4816888/* Total number of mismatched bits between pairs in area 0 */16889#define MC_CMD_FUSE_DIAGS_OUT_AREA0_MISMATCH_BITS_OFST 016890#define MC_CMD_FUSE_DIAGS_OUT_AREA0_MISMATCH_BITS_LEN 416891/* Total number of unexpectedly clear (set in B but not A) bits in area 0 */16892#define MC_CMD_FUSE_DIAGS_OUT_AREA0_PAIR_A_BAD_BITS_OFST 416893#define MC_CMD_FUSE_DIAGS_OUT_AREA0_PAIR_A_BAD_BITS_LEN 416894/* Total number of unexpectedly clear (set in A but not B) bits in area 0 */16895#define MC_CMD_FUSE_DIAGS_OUT_AREA0_PAIR_B_BAD_BITS_OFST 816896#define MC_CMD_FUSE_DIAGS_OUT_AREA0_PAIR_B_BAD_BITS_LEN 416897/* Checksum of data after logical OR of pairs in area 0 */16898#define MC_CMD_FUSE_DIAGS_OUT_AREA0_CHECKSUM_OFST 1216899#define MC_CMD_FUSE_DIAGS_OUT_AREA0_CHECKSUM_LEN 416900/* Total number of mismatched bits between pairs in area 1 */16901#define MC_CMD_FUSE_DIAGS_OUT_AREA1_MISMATCH_BITS_OFST 1616902#define MC_CMD_FUSE_DIAGS_OUT_AREA1_MISMATCH_BITS_LEN 416903/* Total number of unexpectedly clear (set in B but not A) bits in area 1 */16904#define MC_CMD_FUSE_DIAGS_OUT_AREA1_PAIR_A_BAD_BITS_OFST 2016905#define MC_CMD_FUSE_DIAGS_OUT_AREA1_PAIR_A_BAD_BITS_LEN 416906/* Total number of unexpectedly clear (set in A but not B) bits in area 1 */16907#define MC_CMD_FUSE_DIAGS_OUT_AREA1_PAIR_B_BAD_BITS_OFST 2416908#define MC_CMD_FUSE_DIAGS_OUT_AREA1_PAIR_B_BAD_BITS_LEN 416909/* Checksum of data after logical OR of pairs in area 1 */16910#define MC_CMD_FUSE_DIAGS_OUT_AREA1_CHECKSUM_OFST 2816911#define MC_CMD_FUSE_DIAGS_OUT_AREA1_CHECKSUM_LEN 416912/* Total number of mismatched bits between pairs in area 2 */16913#define MC_CMD_FUSE_DIAGS_OUT_AREA2_MISMATCH_BITS_OFST 3216914#define MC_CMD_FUSE_DIAGS_OUT_AREA2_MISMATCH_BITS_LEN 416915/* Total number of unexpectedly clear (set in B but not A) bits in area 2 */16916#define MC_CMD_FUSE_DIAGS_OUT_AREA2_PAIR_A_BAD_BITS_OFST 3616917#define MC_CMD_FUSE_DIAGS_OUT_AREA2_PAIR_A_BAD_BITS_LEN 416918/* Total number of unexpectedly clear (set in A but not B) bits in area 2 */16919#define MC_CMD_FUSE_DIAGS_OUT_AREA2_PAIR_B_BAD_BITS_OFST 4016920#define MC_CMD_FUSE_DIAGS_OUT_AREA2_PAIR_B_BAD_BITS_LEN 416921/* Checksum of data after logical OR of pairs in area 2 */16922#define MC_CMD_FUSE_DIAGS_OUT_AREA2_CHECKSUM_OFST 4416923#define MC_CMD_FUSE_DIAGS_OUT_AREA2_CHECKSUM_LEN 416924 16925 16926/***********************************/16927/* MC_CMD_PRIVILEGE_MODIFY16928 * Modify the privileges of a set of PCIe functions. Note that this operation16929 * only effects non-admin functions unless the admin privilege itself is16930 * included in one of the masks provided.16931 */16932#define MC_CMD_PRIVILEGE_MODIFY 0x6016933#undef MC_CMD_0x60_PRIVILEGE_CTG16934 16935#define MC_CMD_0x60_PRIVILEGE_CTG SRIOV_CTG_ADMIN16936 16937/* MC_CMD_PRIVILEGE_MODIFY_IN msgrequest */16938#define MC_CMD_PRIVILEGE_MODIFY_IN_LEN 1616939/* The groups of functions to have their privilege masks modified. */16940#define MC_CMD_PRIVILEGE_MODIFY_IN_FN_GROUP_OFST 016941#define MC_CMD_PRIVILEGE_MODIFY_IN_FN_GROUP_LEN 416942#define MC_CMD_PRIVILEGE_MODIFY_IN_NONE 0x0 /* enum */16943#define MC_CMD_PRIVILEGE_MODIFY_IN_ALL 0x1 /* enum */16944#define MC_CMD_PRIVILEGE_MODIFY_IN_PFS_ONLY 0x2 /* enum */16945#define MC_CMD_PRIVILEGE_MODIFY_IN_VFS_ONLY 0x3 /* enum */16946#define MC_CMD_PRIVILEGE_MODIFY_IN_VFS_OF_PF 0x4 /* enum */16947#define MC_CMD_PRIVILEGE_MODIFY_IN_ONE 0x5 /* enum */16948/* For VFS_OF_PF specify the PF, for ONE specify the target function */16949#define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_OFST 416950#define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_LEN 416951#define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_PF_OFST 416952#define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_PF_LBN 016953#define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_PF_WIDTH 1616954#define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_VF_OFST 416955#define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_VF_LBN 1616956#define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_VF_WIDTH 1616957/* Privileges to be added to the target functions. For privilege definitions16958 * refer to the command MC_CMD_PRIVILEGE_MASK16959 */16960#define MC_CMD_PRIVILEGE_MODIFY_IN_ADD_MASK_OFST 816961#define MC_CMD_PRIVILEGE_MODIFY_IN_ADD_MASK_LEN 416962/* Privileges to be removed from the target functions. For privilege16963 * definitions refer to the command MC_CMD_PRIVILEGE_MASK16964 */16965#define MC_CMD_PRIVILEGE_MODIFY_IN_REMOVE_MASK_OFST 1216966#define MC_CMD_PRIVILEGE_MODIFY_IN_REMOVE_MASK_LEN 416967 16968/* MC_CMD_PRIVILEGE_MODIFY_OUT msgresponse */16969#define MC_CMD_PRIVILEGE_MODIFY_OUT_LEN 016970 16971 16972/* TUNNEL_ENCAP_UDP_PORT_ENTRY structuredef */16973#define TUNNEL_ENCAP_UDP_PORT_ENTRY_LEN 416974/* UDP port (the standard ports are named below but any port may be used) */16975#define TUNNEL_ENCAP_UDP_PORT_ENTRY_UDP_PORT_OFST 016976#define TUNNEL_ENCAP_UDP_PORT_ENTRY_UDP_PORT_LEN 216977/* enum: the IANA allocated UDP port for VXLAN */16978#define TUNNEL_ENCAP_UDP_PORT_ENTRY_IANA_VXLAN_UDP_PORT 0x12b516979/* enum: the IANA allocated UDP port for Geneve */16980#define TUNNEL_ENCAP_UDP_PORT_ENTRY_IANA_GENEVE_UDP_PORT 0x17c116981#define TUNNEL_ENCAP_UDP_PORT_ENTRY_UDP_PORT_LBN 016982#define TUNNEL_ENCAP_UDP_PORT_ENTRY_UDP_PORT_WIDTH 1616983/* tunnel encapsulation protocol (only those named below are supported) */16984#define TUNNEL_ENCAP_UDP_PORT_ENTRY_PROTOCOL_OFST 216985#define TUNNEL_ENCAP_UDP_PORT_ENTRY_PROTOCOL_LEN 216986/* enum: This port will be used for VXLAN on both IPv4 and IPv6 */16987#define TUNNEL_ENCAP_UDP_PORT_ENTRY_VXLAN 0x016988/* enum: This port will be used for Geneve on both IPv4 and IPv6 */16989#define TUNNEL_ENCAP_UDP_PORT_ENTRY_GENEVE 0x116990#define TUNNEL_ENCAP_UDP_PORT_ENTRY_PROTOCOL_LBN 1616991#define TUNNEL_ENCAP_UDP_PORT_ENTRY_PROTOCOL_WIDTH 1616992 16993 16994/***********************************/16995/* MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS16996 * Configure UDP ports for tunnel encapsulation hardware acceleration. The16997 * parser-dispatcher will attempt to parse traffic on these ports as tunnel16998 * encapsulation PDUs and filter them using the tunnel encapsulation filter16999 * chain rather than the standard filter chain. Note that this command can17000 * cause all functions to see a reset. (Available on Medford only.)17001 */17002#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS 0x11717003#undef MC_CMD_0x117_PRIVILEGE_CTG17004 17005#define MC_CMD_0x117_PRIVILEGE_CTG SRIOV_CTG_ADMIN17006 17007/* MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN msgrequest */17008#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LENMIN 417009#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LENMAX 6817010#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LENMAX_MCDI2 6817011#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LEN(num) (4+4*(num))17012#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_NUM(len) (((len)-4)/4)17013/* Flags */17014#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_FLAGS_OFST 017015#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_FLAGS_LEN 217016#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_UNLOADING_OFST 017017#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_UNLOADING_LBN 017018#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_UNLOADING_WIDTH 117019/* The number of entries in the ENTRIES array */17020#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_NUM_ENTRIES_OFST 217021#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_NUM_ENTRIES_LEN 217022/* Entries defining the UDP port to protocol mapping, each laid out as a17023 * TUNNEL_ENCAP_UDP_PORT_ENTRY17024 */17025#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_OFST 417026#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_LEN 417027#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_MINNUM 017028#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_MAXNUM 1617029#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_MAXNUM_MCDI2 1617030 17031/* MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT msgresponse */17032#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_LEN 217033/* Flags */17034#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_FLAGS_OFST 017035#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_FLAGS_LEN 217036#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_RESETTING_OFST 017037#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_RESETTING_LBN 017038#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_RESETTING_WIDTH 117039 17040 17041/***********************************/17042/* MC_CMD_VNIC_ENCAP_RULE_ADD17043 * Add a rule for detecting encapsulations in the VNIC stage. Currently this only affects checksum validation in VNIC RX - on TX the send descriptor explicitly specifies encapsulation. These rules are per-VNIC, i.e. only apply to the current driver. If a rule matches, then the packet is considered to have the corresponding encapsulation type, and the inner packet is parsed. It is up to the driver to ensure that overlapping rules are not inserted. (If a packet would match multiple rules, a random one of them will be used.) A rule with the exact same match criteria may not be inserted twice (EALREADY). Only a limited number MATCH_FLAGS values are supported, use MC_CMD_GET_PARSER_DISP_INFO with OP OP_GET_SUPPORTED_VNIC_ENCAP_RULE_MATCHES to get a list of supported combinations. Each driver may only have a limited set of active rules - returns ENOSPC if the caller's table is full.17044 */17045#define MC_CMD_VNIC_ENCAP_RULE_ADD 0x16d17046#undef MC_CMD_0x16d_PRIVILEGE_CTG17047 17048#define MC_CMD_0x16d_PRIVILEGE_CTG SRIOV_CTG_GENERAL17049 17050/* MC_CMD_VNIC_ENCAP_RULE_ADD_IN msgrequest */17051#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_LEN 3617052/* Set to MAE_MPORT_SELECTOR_ASSIGNED. In the future this may be relaxed. */17053#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MPORT_SELECTOR_OFST 017054#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MPORT_SELECTOR_LEN 417055/* Any non-zero bits other than the ones named below or an unsupported17056 * combination will cause the NIC to return EOPNOTSUPP. In the future more17057 * flags may be added.17058 */17059#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_FLAGS_OFST 417060#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_FLAGS_LEN 417061#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_ETHER_TYPE_OFST 417062#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_ETHER_TYPE_LBN 017063#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_ETHER_TYPE_WIDTH 117064#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_OUTER_VLAN_OFST 417065#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_OUTER_VLAN_LBN 117066#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_OUTER_VLAN_WIDTH 117067#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_DST_IP_OFST 417068#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_DST_IP_LBN 217069#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_DST_IP_WIDTH 117070#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_IP_PROTO_OFST 417071#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_IP_PROTO_LBN 317072#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_IP_PROTO_WIDTH 117073#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_DST_PORT_OFST 417074#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_DST_PORT_LBN 417075#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_DST_PORT_WIDTH 117076/* Only if MATCH_ETHER_TYPE is set. Ethertype value as bytes in network order.17077 * Currently only IPv4 (0x0800) and IPv6 (0x86DD) ethertypes may be used.17078 */17079#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_ETHER_TYPE_OFST 817080#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_ETHER_TYPE_LEN 217081/* Only if MATCH_OUTER_VLAN is set. VID value as bytes in network order.17082 * (Deprecated)17083 */17084#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_OUTER_VLAN_LBN 8017085#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_OUTER_VLAN_WIDTH 1217086/* Only if MATCH_OUTER_VLAN is set. Aligned wrapper for OUTER_VLAN_VID. */17087#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_OUTER_VLAN_WORD_OFST 1017088#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_OUTER_VLAN_WORD_LEN 217089#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_OUTER_VLAN_VID_OFST 1017090#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_OUTER_VLAN_VID_LBN 017091#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_OUTER_VLAN_VID_WIDTH 1217092/* Only if MATCH_DST_IP is set. IP address as bytes in network order. In the17093 * case of IPv4, the IP should be in the first 4 bytes and all other bytes17094 * should be zero.17095 */17096#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_DST_IP_OFST 1217097#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_DST_IP_LEN 1617098/* Only if MATCH_IP_PROTO is set. Currently only UDP proto (17) may be used. */17099#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_IP_PROTO_OFST 2817100#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_IP_PROTO_LEN 117101/* Actions that should be applied to packets match the rule. */17102#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_ACTION_FLAGS_OFST 2917103#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_ACTION_FLAGS_LEN 117104#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_STRIP_OUTER_VLAN_OFST 2917105#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_STRIP_OUTER_VLAN_LBN 017106#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_STRIP_OUTER_VLAN_WIDTH 117107/* Only if MATCH_DST_PORT is set. Port number as bytes in network order. */17108#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_DST_PORT_OFST 3017109#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_DST_PORT_LEN 217110/* Resulting encapsulation type, as per MAE_MCDI_ENCAP_TYPE enumeration. */17111#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_ENCAP_TYPE_OFST 3217112#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_ENCAP_TYPE_LEN 417113 17114/* MC_CMD_VNIC_ENCAP_RULE_ADD_OUT msgresponse */17115#define MC_CMD_VNIC_ENCAP_RULE_ADD_OUT_LEN 417116/* Handle to inserted rule. Used for removing the rule. */17117#define MC_CMD_VNIC_ENCAP_RULE_ADD_OUT_HANDLE_OFST 017118#define MC_CMD_VNIC_ENCAP_RULE_ADD_OUT_HANDLE_LEN 417119 17120 17121/***********************************/17122/* MC_CMD_VNIC_ENCAP_RULE_REMOVE17123 * Remove a VNIC encapsulation rule. Packets which would have previously matched the rule will then be considered as unencapsulated. Returns EALREADY if the input HANDLE doesn't correspond to an existing rule.17124 */17125#define MC_CMD_VNIC_ENCAP_RULE_REMOVE 0x16e17126#undef MC_CMD_0x16e_PRIVILEGE_CTG17127 17128#define MC_CMD_0x16e_PRIVILEGE_CTG SRIOV_CTG_GENERAL17129 17130/* MC_CMD_VNIC_ENCAP_RULE_REMOVE_IN msgrequest */17131#define MC_CMD_VNIC_ENCAP_RULE_REMOVE_IN_LEN 417132/* Handle which was returned by MC_CMD_VNIC_ENCAP_RULE_ADD. */17133#define MC_CMD_VNIC_ENCAP_RULE_REMOVE_IN_HANDLE_OFST 017134#define MC_CMD_VNIC_ENCAP_RULE_REMOVE_IN_HANDLE_LEN 417135 17136/* MC_CMD_VNIC_ENCAP_RULE_REMOVE_OUT msgresponse */17137#define MC_CMD_VNIC_ENCAP_RULE_REMOVE_OUT_LEN 017138 17139/* FUNCTION_PERSONALITY structuredef: The meanings of the personalities are17140 * defined in SF-120734-TC with more information in SF-122717-TC.17141 */17142#define FUNCTION_PERSONALITY_LEN 417143#define FUNCTION_PERSONALITY_ID_OFST 017144#define FUNCTION_PERSONALITY_ID_LEN 417145/* enum: Function has no assigned personality */17146#define FUNCTION_PERSONALITY_NULL 0x017147/* enum: Function has an EF100-style function control window and VI windows17148 * with both EF100 and vDPA doorbells.17149 */17150#define FUNCTION_PERSONALITY_EF100 0x117151/* enum: Function has virtio net device configuration registers and doorbells17152 * for virtio queue pairs.17153 */17154#define FUNCTION_PERSONALITY_VIRTIO_NET 0x217155/* enum: Function has virtio block device configuration registers and a17156 * doorbell for a single virtqueue.17157 */17158#define FUNCTION_PERSONALITY_VIRTIO_BLK 0x317159/* enum: Function is a Xilinx acceleration device - management function */17160#define FUNCTION_PERSONALITY_ACCEL_MGMT 0x417161/* enum: Function is a Xilinx acceleration device - user function */17162#define FUNCTION_PERSONALITY_ACCEL_USR 0x517163#define FUNCTION_PERSONALITY_ID_LBN 017164#define FUNCTION_PERSONALITY_ID_WIDTH 3217165 17166/* PCIE_FUNCTION structuredef: Structure representing a PCIe function ID17167 * (interface/PF/VF tuple)17168 */17169#define PCIE_FUNCTION_LEN 817170/* PCIe PF function number */17171#define PCIE_FUNCTION_PF_OFST 017172#define PCIE_FUNCTION_PF_LEN 217173/* enum: Wildcard value representing any available function (e.g in resource17174 * allocation requests)17175 */17176#define PCIE_FUNCTION_PF_ANY 0xfffe17177/* enum: Value representing invalid (null) function */17178#define PCIE_FUNCTION_PF_NULL 0xffff17179#define PCIE_FUNCTION_PF_LBN 017180#define PCIE_FUNCTION_PF_WIDTH 1617181/* PCIe VF Function number (PF relative) */17182#define PCIE_FUNCTION_VF_OFST 217183#define PCIE_FUNCTION_VF_LEN 217184/* enum: Wildcard value representing any available function (e.g in resource17185 * allocation requests)17186 */17187#define PCIE_FUNCTION_VF_ANY 0xfffe17188/* enum: Function is a PF (when PF != PF_NULL) or invalid function (when PF ==17189 * PF_NULL)17190 */17191#define PCIE_FUNCTION_VF_NULL 0xffff17192#define PCIE_FUNCTION_VF_LBN 1617193#define PCIE_FUNCTION_VF_WIDTH 1617194/* PCIe interface of the function */17195#define PCIE_FUNCTION_INTF_OFST 417196#define PCIE_FUNCTION_INTF_LEN 417197/* enum: Host PCIe interface */17198#define PCIE_FUNCTION_INTF_HOST 0x017199/* enum: Application Processor interface */17200#define PCIE_FUNCTION_INTF_AP 0x117201#define PCIE_FUNCTION_INTF_LBN 3217202#define PCIE_FUNCTION_INTF_WIDTH 3217203 17204#endif /* MCDI_PCOL_H */17205