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1/* SPDX-License-Identifier: GPL-2.0-only */2/****************************************************************************3 * Driver for Solarflare network controllers and boards4 * Copyright 2005-2006 Fen Systems Ltd.5 * Copyright 2006-2013 Solarflare Communications Inc.6 */7 8#ifndef EFX_NIC_H9#define EFX_NIC_H10 11#include "nic_common.h"12#include "efx.h"13 14u32 efx_farch_fpga_ver(struct efx_nic *efx);15 16enum {17 PHY_TYPE_NONE = 0,18 PHY_TYPE_TXC43128 = 1,19 PHY_TYPE_88E1111 = 2,20 PHY_TYPE_SFX7101 = 3,21 PHY_TYPE_QT2022C2 = 4,22 PHY_TYPE_PM8358 = 6,23 PHY_TYPE_SFT9001A = 8,24 PHY_TYPE_QT2025C = 9,25 PHY_TYPE_SFT9001B = 10,26};27 28enum {29 SIENA_STAT_tx_bytes = GENERIC_STAT_COUNT,30 SIENA_STAT_tx_good_bytes,31 SIENA_STAT_tx_bad_bytes,32 SIENA_STAT_tx_packets,33 SIENA_STAT_tx_bad,34 SIENA_STAT_tx_pause,35 SIENA_STAT_tx_control,36 SIENA_STAT_tx_unicast,37 SIENA_STAT_tx_multicast,38 SIENA_STAT_tx_broadcast,39 SIENA_STAT_tx_lt64,40 SIENA_STAT_tx_64,41 SIENA_STAT_tx_65_to_127,42 SIENA_STAT_tx_128_to_255,43 SIENA_STAT_tx_256_to_511,44 SIENA_STAT_tx_512_to_1023,45 SIENA_STAT_tx_1024_to_15xx,46 SIENA_STAT_tx_15xx_to_jumbo,47 SIENA_STAT_tx_gtjumbo,48 SIENA_STAT_tx_collision,49 SIENA_STAT_tx_single_collision,50 SIENA_STAT_tx_multiple_collision,51 SIENA_STAT_tx_excessive_collision,52 SIENA_STAT_tx_deferred,53 SIENA_STAT_tx_late_collision,54 SIENA_STAT_tx_excessive_deferred,55 SIENA_STAT_tx_non_tcpudp,56 SIENA_STAT_tx_mac_src_error,57 SIENA_STAT_tx_ip_src_error,58 SIENA_STAT_rx_bytes,59 SIENA_STAT_rx_good_bytes,60 SIENA_STAT_rx_bad_bytes,61 SIENA_STAT_rx_packets,62 SIENA_STAT_rx_good,63 SIENA_STAT_rx_bad,64 SIENA_STAT_rx_pause,65 SIENA_STAT_rx_control,66 SIENA_STAT_rx_unicast,67 SIENA_STAT_rx_multicast,68 SIENA_STAT_rx_broadcast,69 SIENA_STAT_rx_lt64,70 SIENA_STAT_rx_64,71 SIENA_STAT_rx_65_to_127,72 SIENA_STAT_rx_128_to_255,73 SIENA_STAT_rx_256_to_511,74 SIENA_STAT_rx_512_to_1023,75 SIENA_STAT_rx_1024_to_15xx,76 SIENA_STAT_rx_15xx_to_jumbo,77 SIENA_STAT_rx_gtjumbo,78 SIENA_STAT_rx_bad_gtjumbo,79 SIENA_STAT_rx_overflow,80 SIENA_STAT_rx_false_carrier,81 SIENA_STAT_rx_symbol_error,82 SIENA_STAT_rx_align_error,83 SIENA_STAT_rx_length_error,84 SIENA_STAT_rx_internal_error,85 SIENA_STAT_rx_nodesc_drop_cnt,86 SIENA_STAT_COUNT87};88 89/**90 * struct siena_nic_data - Siena NIC state91 * @efx: Pointer back to main interface structure92 * @wol_filter_id: Wake-on-LAN packet filter id93 * @stats: Hardware statistics94 * @vf: Array of &struct siena_vf objects95 * @vf_buftbl_base: The zeroth buffer table index used to back VF queues.96 * @vfdi_status: Common VFDI status page to be dmad to VF address space.97 * @local_addr_list: List of local addresses. Protected by %local_lock.98 * @local_page_list: List of DMA addressable pages used to broadcast99 * %local_addr_list. Protected by %local_lock.100 * @local_lock: Mutex protecting %local_addr_list and %local_page_list.101 * @peer_work: Work item to broadcast peer addresses to VMs.102 */103struct siena_nic_data {104 struct efx_nic *efx;105 int wol_filter_id;106 u64 stats[SIENA_STAT_COUNT];107#ifdef CONFIG_SFC_SIENA_SRIOV108 struct siena_vf *vf;109 struct efx_channel *vfdi_channel;110 unsigned vf_buftbl_base;111 struct efx_buffer vfdi_status;112 struct list_head local_addr_list;113 struct list_head local_page_list;114 struct mutex local_lock;115 struct work_struct peer_work;116#endif117};118 119extern const struct efx_nic_type siena_a0_nic_type;120 121int falcon_probe_board(struct efx_nic *efx, u16 revision_info);122 123/* Falcon/Siena queue operations */124int efx_farch_tx_probe(struct efx_tx_queue *tx_queue);125void efx_farch_tx_init(struct efx_tx_queue *tx_queue);126void efx_farch_tx_fini(struct efx_tx_queue *tx_queue);127void efx_farch_tx_remove(struct efx_tx_queue *tx_queue);128void efx_farch_tx_write(struct efx_tx_queue *tx_queue);129unsigned int efx_farch_tx_limit_len(struct efx_tx_queue *tx_queue,130 dma_addr_t dma_addr, unsigned int len);131int efx_farch_rx_probe(struct efx_rx_queue *rx_queue);132void efx_farch_rx_init(struct efx_rx_queue *rx_queue);133void efx_farch_rx_fini(struct efx_rx_queue *rx_queue);134void efx_farch_rx_remove(struct efx_rx_queue *rx_queue);135void efx_farch_rx_write(struct efx_rx_queue *rx_queue);136void efx_farch_rx_defer_refill(struct efx_rx_queue *rx_queue);137int efx_farch_ev_probe(struct efx_channel *channel);138int efx_farch_ev_init(struct efx_channel *channel);139void efx_farch_ev_fini(struct efx_channel *channel);140void efx_farch_ev_remove(struct efx_channel *channel);141int efx_farch_ev_process(struct efx_channel *channel, int quota);142void efx_farch_ev_read_ack(struct efx_channel *channel);143void efx_farch_ev_test_generate(struct efx_channel *channel);144 145/* Falcon/Siena filter operations */146int efx_farch_filter_table_probe(struct efx_nic *efx);147void efx_farch_filter_table_restore(struct efx_nic *efx);148void efx_farch_filter_table_remove(struct efx_nic *efx);149void efx_farch_filter_update_rx_scatter(struct efx_nic *efx);150s32 efx_farch_filter_insert(struct efx_nic *efx, struct efx_filter_spec *spec,151 bool replace);152int efx_farch_filter_remove_safe(struct efx_nic *efx,153 enum efx_filter_priority priority,154 u32 filter_id);155int efx_farch_filter_get_safe(struct efx_nic *efx,156 enum efx_filter_priority priority, u32 filter_id,157 struct efx_filter_spec *);158int efx_farch_filter_clear_rx(struct efx_nic *efx,159 enum efx_filter_priority priority);160u32 efx_farch_filter_count_rx_used(struct efx_nic *efx,161 enum efx_filter_priority priority);162u32 efx_farch_filter_get_rx_id_limit(struct efx_nic *efx);163s32 efx_farch_filter_get_rx_ids(struct efx_nic *efx,164 enum efx_filter_priority priority, u32 *buf,165 u32 size);166#ifdef CONFIG_RFS_ACCEL167bool efx_farch_filter_rfs_expire_one(struct efx_nic *efx, u32 flow_id,168 unsigned int index);169#endif170void efx_farch_filter_sync_rx_mode(struct efx_nic *efx);171 172/* Falcon/Siena interrupts */173void efx_farch_irq_enable_master(struct efx_nic *efx);174int efx_farch_irq_test_generate(struct efx_nic *efx);175void efx_farch_irq_disable_master(struct efx_nic *efx);176irqreturn_t efx_farch_msi_interrupt(int irq, void *dev_id);177irqreturn_t efx_farch_legacy_interrupt(int irq, void *dev_id);178irqreturn_t efx_farch_fatal_interrupt(struct efx_nic *efx);179 180/* Global Resources */181void efx_siena_prepare_flush(struct efx_nic *efx);182int efx_farch_fini_dmaq(struct efx_nic *efx);183void efx_farch_finish_flr(struct efx_nic *efx);184void siena_finish_flush(struct efx_nic *efx);185void falcon_start_nic_stats(struct efx_nic *efx);186void falcon_stop_nic_stats(struct efx_nic *efx);187int falcon_reset_xaui(struct efx_nic *efx);188void efx_farch_dimension_resources(struct efx_nic *efx, unsigned sram_lim_qw);189void efx_farch_init_common(struct efx_nic *efx);190void efx_farch_rx_push_indir_table(struct efx_nic *efx);191void efx_farch_rx_pull_indir_table(struct efx_nic *efx);192 193/* Tests */194struct efx_farch_register_test {195 unsigned address;196 efx_oword_t mask;197};198 199int efx_farch_test_registers(struct efx_nic *efx,200 const struct efx_farch_register_test *regs,201 size_t n_regs);202 203void efx_farch_generate_event(struct efx_nic *efx, unsigned int evq,204 efx_qword_t *event);205 206#endif /* EFX_NIC_H */207