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1/*------------------------------------------------------------------------2 . smc9194.h3 . Copyright (C) 1996 by Erik Stahlman4 .5 . This software may be used and distributed according to the terms6 . of the GNU General Public License, incorporated herein by reference.7 .8 . This file contains register information and access macros for9 . the SMC91xxx chipset.10 .11 . Information contained in this file was obtained from the SMC91C9412 . manual from SMC. To get a copy, if you really want one, you can find13 . information under www.smc.com in the components division.14 . ( this thanks to advice from Donald Becker ).15 .16 . Authors17 . Erik Stahlman ( erik@vt.edu )18 .19 . History20 . 01/06/96 Erik Stahlman moved definitions here from main .c file21 . 01/19/96 Erik Stahlman polished this up some, and added better22 . error handling23 .24 ---------------------------------------------------------------------------*/25#ifndef _SMC9194_H_26#define _SMC9194_H_27 28/* I want some simple types */29 30typedef unsigned char byte;31typedef unsigned short word;32typedef unsigned long int dword;33 34 35/* Because of bank switching, the SMC91xxx uses only 16 I/O ports */36 37#define SMC_IO_EXTENT 1638 39 40/*---------------------------------------------------------------41 .42 . A description of the SMC registers is probably in order here,43 . although for details, the SMC datasheet is invaluable.44 .45 . Basically, the chip has 4 banks of registers ( 0 to 3 ), which46 . are accessed by writing a number into the BANK_SELECT register47 . ( I also use a SMC_SELECT_BANK macro for this ).48 .49 . The banks are configured so that for most purposes, bank 2 is all50 . that is needed for simple run time tasks.51 -----------------------------------------------------------------------*/52 53/*54 . Bank Select Register:55 .56 . yyyy yyyy 0000 00xx57 . xx = bank number58 . yyyy yyyy = 0x33, for identification purposes.59*/60#define BANK_SELECT 1461 62/* BANK 0 */63 64#define TCR 0 /* transmit control register */65#define TCR_ENABLE 0x0001 /* if this is 1, we can transmit */66#define TCR_FDUPLX 0x0800 /* receive packets sent out */67#define TCR_STP_SQET 0x1000 /* stop transmitting if Signal quality error */68#define TCR_MON_CNS 0x0400 /* monitors the carrier status */69#define TCR_PAD_ENABLE 0x0080 /* pads short packets to 64 bytes */70 71#define TCR_CLEAR 0 /* do NOTHING */72/* the normal settings for the TCR register : */73/* QUESTION: do I want to enable padding of short packets ? */74#define TCR_NORMAL TCR_ENABLE75 76 77#define EPH_STATUS 278#define ES_LINK_OK 0x4000 /* is the link integrity ok ? */79 80#define RCR 481#define RCR_SOFTRESET 0x8000 /* resets the chip */82#define RCR_STRIP_CRC 0x200 /* strips CRC */83#define RCR_ENABLE 0x100 /* IFF this is set, we can receive packets */84#define RCR_ALMUL 0x4 /* receive all multicast packets */85#define RCR_PROMISC 0x2 /* enable promiscuous mode */86 87/* the normal settings for the RCR register : */88#define RCR_NORMAL (RCR_STRIP_CRC | RCR_ENABLE)89#define RCR_CLEAR 0x0 /* set it to a base state */90 91#define COUNTER 692#define MIR 893#define MCR 1094/* 12 is reserved */95 96/* BANK 1 */97#define CONFIG 098#define CFG_AUI_SELECT 0x10099#define BASE 2100#define ADDR0 4101#define ADDR1 6102#define ADDR2 8103#define GENERAL 10104#define CONTROL 12105#define CTL_POWERDOWN 0x2000106#define CTL_LE_ENABLE 0x80107#define CTL_CR_ENABLE 0x40108#define CTL_TE_ENABLE 0x0020109#define CTL_AUTO_RELEASE 0x0800110#define CTL_EPROM_ACCESS 0x0003 /* high if Eprom is being read */111 112/* BANK 2 */113#define MMU_CMD 0114#define MC_BUSY 1 /* only readable bit in the register */115#define MC_NOP 0116#define MC_ALLOC 0x20 /* or with number of 256 byte packets */117#define MC_RESET 0x40118#define MC_REMOVE 0x60 /* remove the current rx packet */119#define MC_RELEASE 0x80 /* remove and release the current rx packet */120#define MC_FREEPKT 0xA0 /* Release packet in PNR register */121#define MC_ENQUEUE 0xC0 /* Enqueue the packet for transmit */122 123#define PNR_ARR 2124#define FIFO_PORTS 4125 126#define FP_RXEMPTY 0x8000127#define FP_TXEMPTY 0x80128 129#define POINTER 6130#define PTR_READ 0x2000131#define PTR_RCV 0x8000132#define PTR_AUTOINC 0x4000133#define PTR_AUTO_INC 0x0040134 135#define DATA_1 8136#define DATA_2 10137#define INTERRUPT 12138 139#define INT_MASK 13140#define IM_RCV_INT 0x1141#define IM_TX_INT 0x2142#define IM_TX_EMPTY_INT 0x4143#define IM_ALLOC_INT 0x8144#define IM_RX_OVRN_INT 0x10145#define IM_EPH_INT 0x20146#define IM_ERCV_INT 0x40 /* not on SMC9192 */147 148/* BANK 3 */149#define MULTICAST1 0150#define MULTICAST2 2151#define MULTICAST3 4152#define MULTICAST4 6153#define MGMT 8154#define REVISION 10 /* ( hi: chip id low: rev # ) */155 156 157/* this is NOT on SMC9192 */158#define ERCV 12159 160#define CHIP_9190 3161#define CHIP_9194 4162#define CHIP_9195 5163#define CHIP_91100 7164 165static const char * chip_ids[ 15 ] = {166 NULL, NULL, NULL,167 /* 3 */ "SMC91C90/91C92",168 /* 4 */ "SMC91C94",169 /* 5 */ "SMC91C95",170 NULL,171 /* 7 */ "SMC91C100",172 /* 8 */ "SMC91C100FD",173 NULL, NULL, NULL,174 NULL, NULL, NULL};175 176/*177 . Transmit status bits178*/179#define TS_SUCCESS 0x0001180#define TS_LOSTCAR 0x0400181#define TS_LATCOL 0x0200182#define TS_16COL 0x0010183 184/*185 . Receive status bits186*/187#define RS_ALGNERR 0x8000188#define RS_BADCRC 0x2000189#define RS_ODDFRAME 0x1000190#define RS_TOOLONG 0x0800191#define RS_TOOSHORT 0x0400192#define RS_MULTICAST 0x0001193#define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT)194 195static const char * interfaces[ 2 ] = { "TP", "AUI" };196 197/*-------------------------------------------------------------------------198 . I define some macros to make it easier to do somewhat common199 . or slightly complicated, repeated tasks.200 --------------------------------------------------------------------------*/201 202/* select a register bank, 0 to 3 */203 204#define SMC_SELECT_BANK(x) { outw( x, ioaddr + BANK_SELECT ); }205 206/* define a small delay for the reset */207#define SMC_DELAY() { inw( ioaddr + RCR );\208 inw( ioaddr + RCR );\209 inw( ioaddr + RCR ); }210 211/* this enables an interrupt in the interrupt mask register */212#define SMC_ENABLE_INT(x) {\213 unsigned char mask;\214 SMC_SELECT_BANK(2);\215 mask = inb( ioaddr + INT_MASK );\216 mask |= (x);\217 outb( mask, ioaddr + INT_MASK ); \218}219 220/* this disables an interrupt from the interrupt mask register */221 222#define SMC_DISABLE_INT(x) {\223 unsigned char mask;\224 SMC_SELECT_BANK(2);\225 mask = inb( ioaddr + INT_MASK );\226 mask &= ~(x);\227 outb( mask, ioaddr + INT_MASK ); \228}229 230/*----------------------------------------------------------------------231 . Define the interrupts that I want to receive from the card232 .233 . I want:234 . IM_EPH_INT, for nasty errors235 . IM_RCV_INT, for happy received packets236 . IM_RX_OVRN_INT, because I have to kick the receiver237 --------------------------------------------------------------------------*/238#define SMC_INTERRUPT_MASK (IM_EPH_INT | IM_RX_OVRN_INT | IM_RCV_INT)239 240#endif /* _SMC_9194_H_ */241 242