413 lines · c
1/* SPDX-License-Identifier: GPL-2.0-or-later */2/***************************************************************************3 *4 * Copyright (C) 2004-2008 SMSC5 * Copyright (C) 2005-2008 ARM6 *7 ***************************************************************************/8#ifndef __SMSC911X_H__9#define __SMSC911X_H__10 11/*Chip ID*/12#define LAN9115 0x0115000013#define LAN9116 0x0116000014#define LAN9117 0x0117000015#define LAN9118 0x0118000016#define LAN9215 0x115A000017#define LAN9216 0x116A000018#define LAN9217 0x117A000019#define LAN9218 0x118A000020#define LAN9210 0x9210000021#define LAN9211 0x9211000022#define LAN9220 0x9220000023#define LAN9221 0x9221000024#define LAN9250 0x9250000025#define LAN89218 0x218A000026 27#define TX_FIFO_LOW_THRESHOLD ((u32)1600)28#define SMSC911X_EEPROM_SIZE ((u32)128)29#define USE_DEBUG 030 31/* This is the maximum number of packets to be received every32 * NAPI poll */33#define SMSC_NAPI_WEIGHT 1634 35/* implements a PHY loopback test at initialisation time, to ensure a packet36 * can be successfully looped back */37#define USE_PHY_WORK_AROUND38 39#if USE_DEBUG >= 140#define SMSC_WARN(pdata, nlevel, fmt, args...) \41 netif_warn(pdata, nlevel, (pdata)->dev, \42 "%s: " fmt "\n", __func__, ##args)43#else44#define SMSC_WARN(pdata, nlevel, fmt, args...) \45 no_printk(fmt "\n", ##args)46#endif47 48#if USE_DEBUG >= 249#define SMSC_TRACE(pdata, nlevel, fmt, args...) \50 netif_info(pdata, nlevel, pdata->dev, fmt "\n", ##args)51#else52#define SMSC_TRACE(pdata, nlevel, fmt, args...) \53 no_printk(fmt "\n", ##args)54#endif55 56#ifdef CONFIG_DEBUG_SPINLOCK57#define SMSC_ASSERT_MAC_LOCK(pdata) \58 lockdep_assert_held(&pdata->mac_lock)59#else60#define SMSC_ASSERT_MAC_LOCK(pdata) do {} while (0)61#endif /* CONFIG_DEBUG_SPINLOCK */62 63/* SMSC911x registers and bitfields */64#define RX_DATA_FIFO 0x0065 66#define TX_DATA_FIFO 0x2067#define TX_CMD_A_ON_COMP_ 0x8000000068#define TX_CMD_A_BUF_END_ALGN_ 0x0300000069#define TX_CMD_A_4_BYTE_ALGN_ 0x0000000070#define TX_CMD_A_16_BYTE_ALGN_ 0x0100000071#define TX_CMD_A_32_BYTE_ALGN_ 0x0200000072#define TX_CMD_A_DATA_OFFSET_ 0x001F000073#define TX_CMD_A_FIRST_SEG_ 0x0000200074#define TX_CMD_A_LAST_SEG_ 0x0000100075#define TX_CMD_A_BUF_SIZE_ 0x000007FF76#define TX_CMD_B_PKT_TAG_ 0xFFFF000077#define TX_CMD_B_ADD_CRC_DISABLE_ 0x0000200078#define TX_CMD_B_DISABLE_PADDING_ 0x0000100079#define TX_CMD_B_PKT_BYTE_LENGTH_ 0x000007FF80 81#define RX_STATUS_FIFO 0x4082#define RX_STS_ES_ 0x0000800083#define RX_STS_LENGTH_ERR_ 0x0000100084#define RX_STS_MCAST_ 0x0000040085#define RX_STS_FRAME_TYPE_ 0x0000002086#define RX_STS_CRC_ERR_ 0x0000000287 88#define RX_STATUS_FIFO_PEEK 0x4489 90#define TX_STATUS_FIFO 0x4891#define TX_STS_ES_ 0x0000800092#define TX_STS_LOST_CARRIER_ 0x0000080093#define TX_STS_NO_CARRIER_ 0x0000040094#define TX_STS_LATE_COL_ 0x0000020095#define TX_STS_EXCESS_COL_ 0x0000010096 97#define TX_STATUS_FIFO_PEEK 0x4C98 99#define ID_REV 0x50100#define ID_REV_CHIP_ID_ 0xFFFF0000101#define ID_REV_REV_ID_ 0x0000FFFF102 103#define INT_CFG 0x54104#define INT_CFG_INT_DEAS_ 0xFF000000105#define INT_CFG_INT_DEAS_CLR_ 0x00004000106#define INT_CFG_INT_DEAS_STS_ 0x00002000107#define INT_CFG_IRQ_INT_ 0x00001000108#define INT_CFG_IRQ_EN_ 0x00000100109#define INT_CFG_IRQ_POL_ 0x00000010110#define INT_CFG_IRQ_TYPE_ 0x00000001111 112#define INT_STS 0x58113#define INT_STS_SW_INT_ 0x80000000114#define INT_STS_TXSTOP_INT_ 0x02000000115#define INT_STS_RXSTOP_INT_ 0x01000000116#define INT_STS_RXDFH_INT_ 0x00800000117#define INT_STS_RXDF_INT_ 0x00400000118#define INT_STS_TX_IOC_ 0x00200000119#define INT_STS_RXD_INT_ 0x00100000120#define INT_STS_GPT_INT_ 0x00080000121#define INT_STS_PHY_INT_ 0x00040000122#define INT_STS_PME_INT_ 0x00020000123#define INT_STS_TXSO_ 0x00010000124#define INT_STS_RWT_ 0x00008000125#define INT_STS_RXE_ 0x00004000126#define INT_STS_TXE_ 0x00002000127#define INT_STS_TDFU_ 0x00000800128#define INT_STS_TDFO_ 0x00000400129#define INT_STS_TDFA_ 0x00000200130#define INT_STS_TSFF_ 0x00000100131#define INT_STS_TSFL_ 0x00000080132#define INT_STS_RXDF_ 0x00000040133#define INT_STS_RDFL_ 0x00000020134#define INT_STS_RSFF_ 0x00000010135#define INT_STS_RSFL_ 0x00000008136#define INT_STS_GPIO2_INT_ 0x00000004137#define INT_STS_GPIO1_INT_ 0x00000002138#define INT_STS_GPIO0_INT_ 0x00000001139 140#define INT_EN 0x5C141#define INT_EN_SW_INT_EN_ 0x80000000142#define INT_EN_TXSTOP_INT_EN_ 0x02000000143#define INT_EN_RXSTOP_INT_EN_ 0x01000000144#define INT_EN_RXDFH_INT_EN_ 0x00800000145#define INT_EN_TIOC_INT_EN_ 0x00200000146#define INT_EN_RXD_INT_EN_ 0x00100000147#define INT_EN_GPT_INT_EN_ 0x00080000148#define INT_EN_PHY_INT_EN_ 0x00040000149#define INT_EN_PME_INT_EN_ 0x00020000150#define INT_EN_TXSO_EN_ 0x00010000151#define INT_EN_RWT_EN_ 0x00008000152#define INT_EN_RXE_EN_ 0x00004000153#define INT_EN_TXE_EN_ 0x00002000154#define INT_EN_TDFU_EN_ 0x00000800155#define INT_EN_TDFO_EN_ 0x00000400156#define INT_EN_TDFA_EN_ 0x00000200157#define INT_EN_TSFF_EN_ 0x00000100158#define INT_EN_TSFL_EN_ 0x00000080159#define INT_EN_RXDF_EN_ 0x00000040160#define INT_EN_RDFL_EN_ 0x00000020161#define INT_EN_RSFF_EN_ 0x00000010162#define INT_EN_RSFL_EN_ 0x00000008163#define INT_EN_GPIO2_INT_ 0x00000004164#define INT_EN_GPIO1_INT_ 0x00000002165#define INT_EN_GPIO0_INT_ 0x00000001166 167#define BYTE_TEST 0x64168 169#define FIFO_INT 0x68170#define FIFO_INT_TX_AVAIL_LEVEL_ 0xFF000000171#define FIFO_INT_TX_STS_LEVEL_ 0x00FF0000172#define FIFO_INT_RX_AVAIL_LEVEL_ 0x0000FF00173#define FIFO_INT_RX_STS_LEVEL_ 0x000000FF174 175#define RX_CFG 0x6C176#define RX_CFG_RX_END_ALGN_ 0xC0000000177#define RX_CFG_RX_END_ALGN4_ 0x00000000178#define RX_CFG_RX_END_ALGN16_ 0x40000000179#define RX_CFG_RX_END_ALGN32_ 0x80000000180#define RX_CFG_RX_DMA_CNT_ 0x0FFF0000181#define RX_CFG_RX_DUMP_ 0x00008000182#define RX_CFG_RXDOFF_ 0x00001F00183 184#define TX_CFG 0x70185#define TX_CFG_TXS_DUMP_ 0x00008000186#define TX_CFG_TXD_DUMP_ 0x00004000187#define TX_CFG_TXSAO_ 0x00000004188#define TX_CFG_TX_ON_ 0x00000002189#define TX_CFG_STOP_TX_ 0x00000001190 191#define HW_CFG 0x74192#define HW_CFG_TTM_ 0x00200000193#define HW_CFG_SF_ 0x00100000194#define HW_CFG_TX_FIF_SZ_ 0x000F0000195#define HW_CFG_TR_ 0x00003000196#define HW_CFG_SRST_ 0x00000001197 198/* only available on 115/117 */199#define HW_CFG_PHY_CLK_SEL_ 0x00000060200#define HW_CFG_PHY_CLK_SEL_INT_PHY_ 0x00000000201#define HW_CFG_PHY_CLK_SEL_EXT_PHY_ 0x00000020202#define HW_CFG_PHY_CLK_SEL_CLK_DIS_ 0x00000040203#define HW_CFG_SMI_SEL_ 0x00000010204#define HW_CFG_EXT_PHY_DET_ 0x00000008205#define HW_CFG_EXT_PHY_EN_ 0x00000004206#define HW_CFG_SRST_TO_ 0x00000002207 208/* only available on 116/118 */209#define HW_CFG_32_16_BIT_MODE_ 0x00000004210 211#define RX_DP_CTRL 0x78212#define RX_DP_CTRL_RX_FFWD_ 0x80000000213 214#define RX_FIFO_INF 0x7C215#define RX_FIFO_INF_RXSUSED_ 0x00FF0000216#define RX_FIFO_INF_RXDUSED_ 0x0000FFFF217 218#define TX_FIFO_INF 0x80219#define TX_FIFO_INF_TSUSED_ 0x00FF0000220#define TX_FIFO_INF_TDFREE_ 0x0000FFFF221 222#define PMT_CTRL 0x84223#define PMT_CTRL_PM_MODE_ 0x00003000224#define PMT_CTRL_PM_MODE_D0_ 0x00000000225#define PMT_CTRL_PM_MODE_D1_ 0x00001000226#define PMT_CTRL_PM_MODE_D2_ 0x00002000227#define PMT_CTRL_PM_MODE_D3_ 0x00003000228#define PMT_CTRL_PHY_RST_ 0x00000400229#define PMT_CTRL_WOL_EN_ 0x00000200230#define PMT_CTRL_ED_EN_ 0x00000100231#define PMT_CTRL_PME_TYPE_ 0x00000040232#define PMT_CTRL_WUPS_ 0x00000030233#define PMT_CTRL_WUPS_NOWAKE_ 0x00000000234#define PMT_CTRL_WUPS_ED_ 0x00000010235#define PMT_CTRL_WUPS_WOL_ 0x00000020236#define PMT_CTRL_WUPS_MULTI_ 0x00000030237#define PMT_CTRL_PME_IND_ 0x00000008238#define PMT_CTRL_PME_POL_ 0x00000004239#define PMT_CTRL_PME_EN_ 0x00000002240#define PMT_CTRL_READY_ 0x00000001241 242#define GPIO_CFG 0x88243#define GPIO_CFG_LED3_EN_ 0x40000000244#define GPIO_CFG_LED2_EN_ 0x20000000245#define GPIO_CFG_LED1_EN_ 0x10000000246#define GPIO_CFG_GPIO2_INT_POL_ 0x04000000247#define GPIO_CFG_GPIO1_INT_POL_ 0x02000000248#define GPIO_CFG_GPIO0_INT_POL_ 0x01000000249#define GPIO_CFG_EEPR_EN_ 0x00700000250#define GPIO_CFG_GPIOBUF2_ 0x00040000251#define GPIO_CFG_GPIOBUF1_ 0x00020000252#define GPIO_CFG_GPIOBUF0_ 0x00010000253#define GPIO_CFG_GPIODIR2_ 0x00000400254#define GPIO_CFG_GPIODIR1_ 0x00000200255#define GPIO_CFG_GPIODIR0_ 0x00000100256#define GPIO_CFG_GPIOD4_ 0x00000020257#define GPIO_CFG_GPIOD3_ 0x00000010258#define GPIO_CFG_GPIOD2_ 0x00000004259#define GPIO_CFG_GPIOD1_ 0x00000002260#define GPIO_CFG_GPIOD0_ 0x00000001261 262#define GPT_CFG 0x8C263#define GPT_CFG_TIMER_EN_ 0x20000000264#define GPT_CFG_GPT_LOAD_ 0x0000FFFF265 266#define GPT_CNT 0x90267#define GPT_CNT_GPT_CNT_ 0x0000FFFF268 269#define WORD_SWAP 0x98270 271#define FREE_RUN 0x9C272 273#define RX_DROP 0xA0274 275#define MAC_CSR_CMD 0xA4276#define MAC_CSR_CMD_CSR_BUSY_ 0x80000000277#define MAC_CSR_CMD_R_NOT_W_ 0x40000000278#define MAC_CSR_CMD_CSR_ADDR_ 0x000000FF279 280#define MAC_CSR_DATA 0xA8281 282#define AFC_CFG 0xAC283#define AFC_CFG_AFC_HI_ 0x00FF0000284#define AFC_CFG_AFC_LO_ 0x0000FF00285#define AFC_CFG_BACK_DUR_ 0x000000F0286#define AFC_CFG_FCMULT_ 0x00000008287#define AFC_CFG_FCBRD_ 0x00000004288#define AFC_CFG_FCADD_ 0x00000002289#define AFC_CFG_FCANY_ 0x00000001290 291#define E2P_CMD 0xB0292#define E2P_CMD_EPC_BUSY_ 0x80000000293#define E2P_CMD_EPC_CMD_ 0x70000000294#define E2P_CMD_EPC_CMD_READ_ 0x00000000295#define E2P_CMD_EPC_CMD_EWDS_ 0x10000000296#define E2P_CMD_EPC_CMD_EWEN_ 0x20000000297#define E2P_CMD_EPC_CMD_WRITE_ 0x30000000298#define E2P_CMD_EPC_CMD_WRAL_ 0x40000000299#define E2P_CMD_EPC_CMD_ERASE_ 0x50000000300#define E2P_CMD_EPC_CMD_ERAL_ 0x60000000301#define E2P_CMD_EPC_CMD_RELOAD_ 0x70000000302#define E2P_CMD_EPC_TIMEOUT_ 0x00000200303#define E2P_CMD_MAC_ADDR_LOADED_ 0x00000100304#define E2P_CMD_EPC_ADDR_ 0x000000FF305 306#define E2P_DATA 0xB4307#define E2P_DATA_EEPROM_DATA_ 0x000000FF308#define LAN_REGISTER_EXTENT 0x00000100309 310#define RESET_CTL 0x1F8311#define RESET_CTL_DIGITAL_RST_ 0x00000001312 313/*314 * MAC Control and Status Register (Indirect Address)315 * Offset (through the MAC_CSR CMD and DATA port)316 */317#define MAC_CR 0x01318#define MAC_CR_RXALL_ 0x80000000319#define MAC_CR_HBDIS_ 0x10000000320#define MAC_CR_RCVOWN_ 0x00800000321#define MAC_CR_LOOPBK_ 0x00200000322#define MAC_CR_FDPX_ 0x00100000323#define MAC_CR_MCPAS_ 0x00080000324#define MAC_CR_PRMS_ 0x00040000325#define MAC_CR_INVFILT_ 0x00020000326#define MAC_CR_PASSBAD_ 0x00010000327#define MAC_CR_HFILT_ 0x00008000328#define MAC_CR_HPFILT_ 0x00002000329#define MAC_CR_LCOLL_ 0x00001000330#define MAC_CR_BCAST_ 0x00000800331#define MAC_CR_DISRTY_ 0x00000400332#define MAC_CR_PADSTR_ 0x00000100333#define MAC_CR_BOLMT_MASK_ 0x000000C0334#define MAC_CR_DFCHK_ 0x00000020335#define MAC_CR_TXEN_ 0x00000008336#define MAC_CR_RXEN_ 0x00000004337 338#define ADDRH 0x02339 340#define ADDRL 0x03341 342#define HASHH 0x04343 344#define HASHL 0x05345 346#define MII_ACC 0x06347#define MII_ACC_PHY_ADDR_ 0x0000F800348#define MII_ACC_MIIRINDA_ 0x000007C0349#define MII_ACC_MII_WRITE_ 0x00000002350#define MII_ACC_MII_BUSY_ 0x00000001351 352#define MII_DATA 0x07353 354#define FLOW 0x08355#define FLOW_FCPT_ 0xFFFF0000356#define FLOW_FCPASS_ 0x00000004357#define FLOW_FCEN_ 0x00000002358#define FLOW_FCBSY_ 0x00000001359 360#define VLAN1 0x09361 362#define VLAN2 0x0A363 364#define WUFF 0x0B365 366#define WUCSR 0x0C367#define WUCSR_GUE_ 0x00000200368#define WUCSR_WUFR_ 0x00000040369#define WUCSR_MPR_ 0x00000020370#define WUCSR_WAKE_EN_ 0x00000004371#define WUCSR_MPEN_ 0x00000002372 373/*374 * Phy definitions (vendor-specific)375 */376#define LAN9118_PHY_ID 0x00C0001C377 378#define MII_INTSTS 0x1D379 380#define MII_INTMSK 0x1E381#define PHY_INTMSK_AN_RCV_ (1 << 1)382#define PHY_INTMSK_PDFAULT_ (1 << 2)383#define PHY_INTMSK_AN_ACK_ (1 << 3)384#define PHY_INTMSK_LNKDOWN_ (1 << 4)385#define PHY_INTMSK_RFAULT_ (1 << 5)386#define PHY_INTMSK_AN_COMP_ (1 << 6)387#define PHY_INTMSK_ENERGYON_ (1 << 7)388#define PHY_INTMSK_DEFAULT_ (PHY_INTMSK_ENERGYON_ | \389 PHY_INTMSK_AN_COMP_ | \390 PHY_INTMSK_RFAULT_ | \391 PHY_INTMSK_LNKDOWN_)392 393#define ADVERTISE_PAUSE_ALL (ADVERTISE_PAUSE_CAP | \394 ADVERTISE_PAUSE_ASYM)395 396#define LPA_PAUSE_ALL (LPA_PAUSE_CAP | \397 LPA_PAUSE_ASYM)398 399/*400 * Provide hooks to let the arch add to the initialisation procedure401 * and to override the source of the MAC address.402 */403#define SMSC_INITIALIZE() do {} while (0)404#define smsc_get_mac(dev) smsc911x_read_mac_address((dev))405 406#ifdef CONFIG_SMSC911X_ARCH_HOOKS407#include <asm/smsc911x.h>408#endif409 410#include <linux/smscphy.h>411 412#endif /* __SMSC911X_H__ */413