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1// SPDX-License-Identifier: GPL-2.0-or-later2 /***************************************************************************3 *4 * Copyright (C) 2007,2008 SMSC5 *6 ***************************************************************************7 */8 9#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt10 11#include <linux/interrupt.h>12#include <linux/kernel.h>13#include <linux/netdevice.h>14#include <linux/phy.h>15#include <linux/pci.h>16#include <linux/if_vlan.h>17#include <linux/dma-mapping.h>18#include <linux/crc32.h>19#include <linux/slab.h>20#include <linux/module.h>21#include <linux/unaligned.h>22#include "smsc9420.h"23 24#define DRV_NAME "smsc9420"25#define DRV_MDIONAME "smsc9420-mdio"26#define DRV_DESCRIPTION "SMSC LAN9420 driver"27#define DRV_VERSION "1.01"28 29MODULE_DESCRIPTION("SMSC LAN9420 Ethernet driver");30MODULE_LICENSE("GPL");31MODULE_VERSION(DRV_VERSION);32 33struct smsc9420_dma_desc {34 u32 status;35 u32 length;36 u32 buffer1;37 u32 buffer2;38};39 40struct smsc9420_ring_info {41 struct sk_buff *skb;42 dma_addr_t mapping;43};44 45struct smsc9420_pdata {46 void __iomem *ioaddr;47 struct pci_dev *pdev;48 struct net_device *dev;49 50 struct smsc9420_dma_desc *rx_ring;51 struct smsc9420_dma_desc *tx_ring;52 struct smsc9420_ring_info *tx_buffers;53 struct smsc9420_ring_info *rx_buffers;54 dma_addr_t rx_dma_addr;55 dma_addr_t tx_dma_addr;56 int tx_ring_head, tx_ring_tail;57 int rx_ring_head, rx_ring_tail;58 59 spinlock_t int_lock;60 spinlock_t phy_lock;61 62 struct napi_struct napi;63 64 bool software_irq_signal;65 bool rx_csum;66 u32 msg_enable;67 68 struct mii_bus *mii_bus;69 int last_duplex;70 int last_carrier;71};72 73static const struct pci_device_id smsc9420_id_table[] = {74 { PCI_VENDOR_ID_9420, PCI_DEVICE_ID_9420, PCI_ANY_ID, PCI_ANY_ID, },75 { 0, }76};77 78MODULE_DEVICE_TABLE(pci, smsc9420_id_table);79 80#define SMSC_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)81 82static uint smsc_debug;83static uint debug = -1;84module_param(debug, uint, 0);85MODULE_PARM_DESC(debug, "debug level");86 87static inline u32 smsc9420_reg_read(struct smsc9420_pdata *pd, u32 offset)88{89 return ioread32(pd->ioaddr + offset);90}91 92static inline void93smsc9420_reg_write(struct smsc9420_pdata *pd, u32 offset, u32 value)94{95 iowrite32(value, pd->ioaddr + offset);96}97 98static inline void smsc9420_pci_flush_write(struct smsc9420_pdata *pd)99{100 /* to ensure PCI write completion, we must perform a PCI read */101 smsc9420_reg_read(pd, ID_REV);102}103 104static int smsc9420_mii_read(struct mii_bus *bus, int phyaddr, int regidx)105{106 struct smsc9420_pdata *pd = bus->priv;107 unsigned long flags;108 u32 addr;109 int i, reg = -EIO;110 111 spin_lock_irqsave(&pd->phy_lock, flags);112 113 /* confirm MII not busy */114 if ((smsc9420_reg_read(pd, MII_ACCESS) & MII_ACCESS_MII_BUSY_)) {115 netif_warn(pd, drv, pd->dev, "MII is busy???\n");116 goto out;117 }118 119 /* set the address, index & direction (read from PHY) */120 addr = ((phyaddr & 0x1F) << 11) | ((regidx & 0x1F) << 6) |121 MII_ACCESS_MII_READ_;122 smsc9420_reg_write(pd, MII_ACCESS, addr);123 124 /* wait for read to complete with 50us timeout */125 for (i = 0; i < 5; i++) {126 if (!(smsc9420_reg_read(pd, MII_ACCESS) &127 MII_ACCESS_MII_BUSY_)) {128 reg = (u16)smsc9420_reg_read(pd, MII_DATA);129 goto out;130 }131 udelay(10);132 }133 134 netif_warn(pd, drv, pd->dev, "MII busy timeout!\n");135 136out:137 spin_unlock_irqrestore(&pd->phy_lock, flags);138 return reg;139}140 141static int smsc9420_mii_write(struct mii_bus *bus, int phyaddr, int regidx,142 u16 val)143{144 struct smsc9420_pdata *pd = bus->priv;145 unsigned long flags;146 u32 addr;147 int i, reg = -EIO;148 149 spin_lock_irqsave(&pd->phy_lock, flags);150 151 /* confirm MII not busy */152 if ((smsc9420_reg_read(pd, MII_ACCESS) & MII_ACCESS_MII_BUSY_)) {153 netif_warn(pd, drv, pd->dev, "MII is busy???\n");154 goto out;155 }156 157 /* put the data to write in the MAC */158 smsc9420_reg_write(pd, MII_DATA, (u32)val);159 160 /* set the address, index & direction (write to PHY) */161 addr = ((phyaddr & 0x1F) << 11) | ((regidx & 0x1F) << 6) |162 MII_ACCESS_MII_WRITE_;163 smsc9420_reg_write(pd, MII_ACCESS, addr);164 165 /* wait for write to complete with 50us timeout */166 for (i = 0; i < 5; i++) {167 if (!(smsc9420_reg_read(pd, MII_ACCESS) &168 MII_ACCESS_MII_BUSY_)) {169 reg = 0;170 goto out;171 }172 udelay(10);173 }174 175 netif_warn(pd, drv, pd->dev, "MII busy timeout!\n");176 177out:178 spin_unlock_irqrestore(&pd->phy_lock, flags);179 return reg;180}181 182/* Returns hash bit number for given MAC address183 * Example:184 * 01 00 5E 00 00 01 -> returns bit number 31 */185static u32 smsc9420_hash(u8 addr[ETH_ALEN])186{187 return (ether_crc(ETH_ALEN, addr) >> 26) & 0x3f;188}189 190static int smsc9420_eeprom_reload(struct smsc9420_pdata *pd)191{192 int timeout = 100000;193 194 BUG_ON(!pd);195 196 if (smsc9420_reg_read(pd, E2P_CMD) & E2P_CMD_EPC_BUSY_) {197 netif_dbg(pd, drv, pd->dev, "%s: Eeprom busy\n", __func__);198 return -EIO;199 }200 201 smsc9420_reg_write(pd, E2P_CMD,202 (E2P_CMD_EPC_BUSY_ | E2P_CMD_EPC_CMD_RELOAD_));203 204 do {205 udelay(10);206 if (!(smsc9420_reg_read(pd, E2P_CMD) & E2P_CMD_EPC_BUSY_))207 return 0;208 } while (timeout--);209 210 netif_warn(pd, drv, pd->dev, "%s: Eeprom timed out\n", __func__);211 return -EIO;212}213 214static void smsc9420_ethtool_get_drvinfo(struct net_device *netdev,215 struct ethtool_drvinfo *drvinfo)216{217 struct smsc9420_pdata *pd = netdev_priv(netdev);218 219 strscpy(drvinfo->driver, DRV_NAME, sizeof(drvinfo->driver));220 strscpy(drvinfo->bus_info, pci_name(pd->pdev),221 sizeof(drvinfo->bus_info));222 strscpy(drvinfo->version, DRV_VERSION, sizeof(drvinfo->version));223}224 225static u32 smsc9420_ethtool_get_msglevel(struct net_device *netdev)226{227 struct smsc9420_pdata *pd = netdev_priv(netdev);228 return pd->msg_enable;229}230 231static void smsc9420_ethtool_set_msglevel(struct net_device *netdev, u32 data)232{233 struct smsc9420_pdata *pd = netdev_priv(netdev);234 pd->msg_enable = data;235}236 237static int smsc9420_ethtool_getregslen(struct net_device *dev)238{239 /* all smsc9420 registers plus all phy registers */240 return 0x100 + (32 * sizeof(u32));241}242 243static void244smsc9420_ethtool_getregs(struct net_device *dev, struct ethtool_regs *regs,245 void *buf)246{247 struct smsc9420_pdata *pd = netdev_priv(dev);248 struct phy_device *phy_dev = dev->phydev;249 unsigned int i, j = 0;250 u32 *data = buf;251 252 regs->version = smsc9420_reg_read(pd, ID_REV);253 for (i = 0; i < 0x100; i += (sizeof(u32)))254 data[j++] = smsc9420_reg_read(pd, i);255 256 // cannot read phy registers if the net device is down257 if (!phy_dev)258 return;259 260 for (i = 0; i <= 31; i++)261 data[j++] = smsc9420_mii_read(phy_dev->mdio.bus,262 phy_dev->mdio.addr, i);263}264 265static void smsc9420_eeprom_enable_access(struct smsc9420_pdata *pd)266{267 unsigned int temp = smsc9420_reg_read(pd, GPIO_CFG);268 temp &= ~GPIO_CFG_EEPR_EN_;269 smsc9420_reg_write(pd, GPIO_CFG, temp);270 msleep(1);271}272 273static int smsc9420_eeprom_send_cmd(struct smsc9420_pdata *pd, u32 op)274{275 int timeout = 100;276 u32 e2cmd;277 278 netif_dbg(pd, hw, pd->dev, "op 0x%08x\n", op);279 if (smsc9420_reg_read(pd, E2P_CMD) & E2P_CMD_EPC_BUSY_) {280 netif_warn(pd, hw, pd->dev, "Busy at start\n");281 return -EBUSY;282 }283 284 e2cmd = op | E2P_CMD_EPC_BUSY_;285 smsc9420_reg_write(pd, E2P_CMD, e2cmd);286 287 do {288 msleep(1);289 e2cmd = smsc9420_reg_read(pd, E2P_CMD);290 } while ((e2cmd & E2P_CMD_EPC_BUSY_) && (--timeout));291 292 if (!timeout) {293 netif_info(pd, hw, pd->dev, "TIMED OUT\n");294 return -EAGAIN;295 }296 297 if (e2cmd & E2P_CMD_EPC_TIMEOUT_) {298 netif_info(pd, hw, pd->dev,299 "Error occurred during eeprom operation\n");300 return -EINVAL;301 }302 303 return 0;304}305 306static int smsc9420_eeprom_read_location(struct smsc9420_pdata *pd,307 u8 address, u8 *data)308{309 u32 op = E2P_CMD_EPC_CMD_READ_ | address;310 int ret;311 312 netif_dbg(pd, hw, pd->dev, "address 0x%x\n", address);313 ret = smsc9420_eeprom_send_cmd(pd, op);314 315 if (!ret)316 data[address] = smsc9420_reg_read(pd, E2P_DATA);317 318 return ret;319}320 321static int smsc9420_eeprom_write_location(struct smsc9420_pdata *pd,322 u8 address, u8 data)323{324 u32 op = E2P_CMD_EPC_CMD_ERASE_ | address;325 int ret;326 327 netif_dbg(pd, hw, pd->dev, "address 0x%x, data 0x%x\n", address, data);328 ret = smsc9420_eeprom_send_cmd(pd, op);329 330 if (!ret) {331 op = E2P_CMD_EPC_CMD_WRITE_ | address;332 smsc9420_reg_write(pd, E2P_DATA, (u32)data);333 ret = smsc9420_eeprom_send_cmd(pd, op);334 }335 336 return ret;337}338 339static int smsc9420_ethtool_get_eeprom_len(struct net_device *dev)340{341 return SMSC9420_EEPROM_SIZE;342}343 344static int smsc9420_ethtool_get_eeprom(struct net_device *dev,345 struct ethtool_eeprom *eeprom, u8 *data)346{347 struct smsc9420_pdata *pd = netdev_priv(dev);348 u8 eeprom_data[SMSC9420_EEPROM_SIZE];349 int len, i;350 351 smsc9420_eeprom_enable_access(pd);352 353 len = min(eeprom->len, SMSC9420_EEPROM_SIZE);354 for (i = 0; i < len; i++) {355 int ret = smsc9420_eeprom_read_location(pd, i, eeprom_data);356 if (ret < 0) {357 eeprom->len = 0;358 return ret;359 }360 }361 362 memcpy(data, &eeprom_data[eeprom->offset], len);363 eeprom->magic = SMSC9420_EEPROM_MAGIC;364 eeprom->len = len;365 return 0;366}367 368static int smsc9420_ethtool_set_eeprom(struct net_device *dev,369 struct ethtool_eeprom *eeprom, u8 *data)370{371 struct smsc9420_pdata *pd = netdev_priv(dev);372 int ret;373 374 if (eeprom->magic != SMSC9420_EEPROM_MAGIC)375 return -EINVAL;376 377 smsc9420_eeprom_enable_access(pd);378 smsc9420_eeprom_send_cmd(pd, E2P_CMD_EPC_CMD_EWEN_);379 ret = smsc9420_eeprom_write_location(pd, eeprom->offset, *data);380 smsc9420_eeprom_send_cmd(pd, E2P_CMD_EPC_CMD_EWDS_);381 382 /* Single byte write, according to man page */383 eeprom->len = 1;384 385 return ret;386}387 388static const struct ethtool_ops smsc9420_ethtool_ops = {389 .get_drvinfo = smsc9420_ethtool_get_drvinfo,390 .get_msglevel = smsc9420_ethtool_get_msglevel,391 .set_msglevel = smsc9420_ethtool_set_msglevel,392 .nway_reset = phy_ethtool_nway_reset,393 .get_link = ethtool_op_get_link,394 .get_eeprom_len = smsc9420_ethtool_get_eeprom_len,395 .get_eeprom = smsc9420_ethtool_get_eeprom,396 .set_eeprom = smsc9420_ethtool_set_eeprom,397 .get_regs_len = smsc9420_ethtool_getregslen,398 .get_regs = smsc9420_ethtool_getregs,399 .get_ts_info = ethtool_op_get_ts_info,400 .get_link_ksettings = phy_ethtool_get_link_ksettings,401 .set_link_ksettings = phy_ethtool_set_link_ksettings,402};403 404/* Sets the device MAC address to dev_addr */405static void smsc9420_set_mac_address(struct net_device *dev)406{407 struct smsc9420_pdata *pd = netdev_priv(dev);408 const u8 *dev_addr = dev->dev_addr;409 u32 mac_high16 = (dev_addr[5] << 8) | dev_addr[4];410 u32 mac_low32 = (dev_addr[3] << 24) | (dev_addr[2] << 16) |411 (dev_addr[1] << 8) | dev_addr[0];412 413 smsc9420_reg_write(pd, ADDRH, mac_high16);414 smsc9420_reg_write(pd, ADDRL, mac_low32);415}416 417static void smsc9420_check_mac_address(struct net_device *dev)418{419 struct smsc9420_pdata *pd = netdev_priv(dev);420 u8 addr[ETH_ALEN];421 422 /* Check if mac address has been specified when bringing interface up */423 if (is_valid_ether_addr(dev->dev_addr)) {424 smsc9420_set_mac_address(dev);425 netif_dbg(pd, probe, pd->dev,426 "MAC Address is specified by configuration\n");427 } else {428 /* Try reading mac address from device. if EEPROM is present429 * it will already have been set */430 u32 mac_high16 = smsc9420_reg_read(pd, ADDRH);431 u32 mac_low32 = smsc9420_reg_read(pd, ADDRL);432 addr[0] = (u8)(mac_low32);433 addr[1] = (u8)(mac_low32 >> 8);434 addr[2] = (u8)(mac_low32 >> 16);435 addr[3] = (u8)(mac_low32 >> 24);436 addr[4] = (u8)(mac_high16);437 addr[5] = (u8)(mac_high16 >> 8);438 439 if (is_valid_ether_addr(addr)) {440 /* eeprom values are valid so use them */441 eth_hw_addr_set(dev, addr);442 netif_dbg(pd, probe, pd->dev,443 "Mac Address is read from EEPROM\n");444 } else {445 /* eeprom values are invalid, generate random MAC */446 eth_hw_addr_random(dev);447 smsc9420_set_mac_address(dev);448 netif_dbg(pd, probe, pd->dev,449 "MAC Address is set to random\n");450 }451 }452}453 454static void smsc9420_stop_tx(struct smsc9420_pdata *pd)455{456 u32 dmac_control, mac_cr, dma_intr_ena;457 int timeout = 1000;458 459 /* disable TX DMAC */460 dmac_control = smsc9420_reg_read(pd, DMAC_CONTROL);461 dmac_control &= (~DMAC_CONTROL_ST_);462 smsc9420_reg_write(pd, DMAC_CONTROL, dmac_control);463 464 /* Wait max 10ms for transmit process to stop */465 while (--timeout) {466 if (smsc9420_reg_read(pd, DMAC_STATUS) & DMAC_STS_TS_)467 break;468 udelay(10);469 }470 471 if (!timeout)472 netif_warn(pd, ifdown, pd->dev, "TX DMAC failed to stop\n");473 474 /* ACK Tx DMAC stop bit */475 smsc9420_reg_write(pd, DMAC_STATUS, DMAC_STS_TXPS_);476 477 /* mask TX DMAC interrupts */478 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA);479 dma_intr_ena &= ~(DMAC_INTR_ENA_TX_);480 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena);481 smsc9420_pci_flush_write(pd);482 483 /* stop MAC TX */484 mac_cr = smsc9420_reg_read(pd, MAC_CR) & (~MAC_CR_TXEN_);485 smsc9420_reg_write(pd, MAC_CR, mac_cr);486 smsc9420_pci_flush_write(pd);487}488 489static void smsc9420_free_tx_ring(struct smsc9420_pdata *pd)490{491 int i;492 493 BUG_ON(!pd->tx_ring);494 495 if (!pd->tx_buffers)496 return;497 498 for (i = 0; i < TX_RING_SIZE; i++) {499 struct sk_buff *skb = pd->tx_buffers[i].skb;500 501 if (skb) {502 BUG_ON(!pd->tx_buffers[i].mapping);503 dma_unmap_single(&pd->pdev->dev,504 pd->tx_buffers[i].mapping, skb->len,505 DMA_TO_DEVICE);506 dev_kfree_skb_any(skb);507 }508 509 pd->tx_ring[i].status = 0;510 pd->tx_ring[i].length = 0;511 pd->tx_ring[i].buffer1 = 0;512 pd->tx_ring[i].buffer2 = 0;513 }514 wmb();515 516 kfree(pd->tx_buffers);517 pd->tx_buffers = NULL;518 519 pd->tx_ring_head = 0;520 pd->tx_ring_tail = 0;521}522 523static void smsc9420_free_rx_ring(struct smsc9420_pdata *pd)524{525 int i;526 527 BUG_ON(!pd->rx_ring);528 529 if (!pd->rx_buffers)530 return;531 532 for (i = 0; i < RX_RING_SIZE; i++) {533 if (pd->rx_buffers[i].skb)534 dev_kfree_skb_any(pd->rx_buffers[i].skb);535 536 if (pd->rx_buffers[i].mapping)537 dma_unmap_single(&pd->pdev->dev,538 pd->rx_buffers[i].mapping,539 PKT_BUF_SZ, DMA_FROM_DEVICE);540 541 pd->rx_ring[i].status = 0;542 pd->rx_ring[i].length = 0;543 pd->rx_ring[i].buffer1 = 0;544 pd->rx_ring[i].buffer2 = 0;545 }546 wmb();547 548 kfree(pd->rx_buffers);549 pd->rx_buffers = NULL;550 551 pd->rx_ring_head = 0;552 pd->rx_ring_tail = 0;553}554 555static void smsc9420_stop_rx(struct smsc9420_pdata *pd)556{557 int timeout = 1000;558 u32 mac_cr, dmac_control, dma_intr_ena;559 560 /* mask RX DMAC interrupts */561 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA);562 dma_intr_ena &= (~DMAC_INTR_ENA_RX_);563 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena);564 smsc9420_pci_flush_write(pd);565 566 /* stop RX MAC prior to stoping DMA */567 mac_cr = smsc9420_reg_read(pd, MAC_CR) & (~MAC_CR_RXEN_);568 smsc9420_reg_write(pd, MAC_CR, mac_cr);569 smsc9420_pci_flush_write(pd);570 571 /* stop RX DMAC */572 dmac_control = smsc9420_reg_read(pd, DMAC_CONTROL);573 dmac_control &= (~DMAC_CONTROL_SR_);574 smsc9420_reg_write(pd, DMAC_CONTROL, dmac_control);575 smsc9420_pci_flush_write(pd);576 577 /* wait up to 10ms for receive to stop */578 while (--timeout) {579 if (smsc9420_reg_read(pd, DMAC_STATUS) & DMAC_STS_RS_)580 break;581 udelay(10);582 }583 584 if (!timeout)585 netif_warn(pd, ifdown, pd->dev,586 "RX DMAC did not stop! timeout\n");587 588 /* ACK the Rx DMAC stop bit */589 smsc9420_reg_write(pd, DMAC_STATUS, DMAC_STS_RXPS_);590}591 592static irqreturn_t smsc9420_isr(int irq, void *dev_id)593{594 struct smsc9420_pdata *pd = dev_id;595 u32 int_cfg, int_sts, int_ctl;596 irqreturn_t ret = IRQ_NONE;597 ulong flags;598 599 BUG_ON(!pd);600 BUG_ON(!pd->ioaddr);601 602 int_cfg = smsc9420_reg_read(pd, INT_CFG);603 604 /* check if it's our interrupt */605 if ((int_cfg & (INT_CFG_IRQ_EN_ | INT_CFG_IRQ_INT_)) !=606 (INT_CFG_IRQ_EN_ | INT_CFG_IRQ_INT_))607 return IRQ_NONE;608 609 int_sts = smsc9420_reg_read(pd, INT_STAT);610 611 if (likely(INT_STAT_DMAC_INT_ & int_sts)) {612 u32 status = smsc9420_reg_read(pd, DMAC_STATUS);613 u32 ints_to_clear = 0;614 615 if (status & DMAC_STS_TX_) {616 ints_to_clear |= (DMAC_STS_TX_ | DMAC_STS_NIS_);617 netif_wake_queue(pd->dev);618 }619 620 if (status & DMAC_STS_RX_) {621 /* mask RX DMAC interrupts */622 u32 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA);623 dma_intr_ena &= (~DMAC_INTR_ENA_RX_);624 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena);625 smsc9420_pci_flush_write(pd);626 627 ints_to_clear |= (DMAC_STS_RX_ | DMAC_STS_NIS_);628 napi_schedule(&pd->napi);629 }630 631 if (ints_to_clear)632 smsc9420_reg_write(pd, DMAC_STATUS, ints_to_clear);633 634 ret = IRQ_HANDLED;635 }636 637 if (unlikely(INT_STAT_SW_INT_ & int_sts)) {638 /* mask software interrupt */639 spin_lock_irqsave(&pd->int_lock, flags);640 int_ctl = smsc9420_reg_read(pd, INT_CTL);641 int_ctl &= (~INT_CTL_SW_INT_EN_);642 smsc9420_reg_write(pd, INT_CTL, int_ctl);643 spin_unlock_irqrestore(&pd->int_lock, flags);644 645 smsc9420_reg_write(pd, INT_STAT, INT_STAT_SW_INT_);646 pd->software_irq_signal = true;647 smp_wmb();648 649 ret = IRQ_HANDLED;650 }651 652 /* to ensure PCI write completion, we must perform a PCI read */653 smsc9420_pci_flush_write(pd);654 655 return ret;656}657 658#ifdef CONFIG_NET_POLL_CONTROLLER659static void smsc9420_poll_controller(struct net_device *dev)660{661 struct smsc9420_pdata *pd = netdev_priv(dev);662 const int irq = pd->pdev->irq;663 664 disable_irq(irq);665 smsc9420_isr(0, dev);666 enable_irq(irq);667}668#endif /* CONFIG_NET_POLL_CONTROLLER */669 670static void smsc9420_dmac_soft_reset(struct smsc9420_pdata *pd)671{672 smsc9420_reg_write(pd, BUS_MODE, BUS_MODE_SWR_);673 smsc9420_reg_read(pd, BUS_MODE);674 udelay(2);675 if (smsc9420_reg_read(pd, BUS_MODE) & BUS_MODE_SWR_)676 netif_warn(pd, drv, pd->dev, "Software reset not cleared\n");677}678 679static int smsc9420_stop(struct net_device *dev)680{681 struct smsc9420_pdata *pd = netdev_priv(dev);682 u32 int_cfg;683 ulong flags;684 685 BUG_ON(!pd);686 BUG_ON(!dev->phydev);687 688 /* disable master interrupt */689 spin_lock_irqsave(&pd->int_lock, flags);690 int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_);691 smsc9420_reg_write(pd, INT_CFG, int_cfg);692 spin_unlock_irqrestore(&pd->int_lock, flags);693 694 netif_tx_disable(dev);695 napi_disable(&pd->napi);696 697 smsc9420_stop_tx(pd);698 smsc9420_free_tx_ring(pd);699 700 smsc9420_stop_rx(pd);701 smsc9420_free_rx_ring(pd);702 703 free_irq(pd->pdev->irq, pd);704 705 smsc9420_dmac_soft_reset(pd);706 707 phy_stop(dev->phydev);708 709 phy_disconnect(dev->phydev);710 mdiobus_unregister(pd->mii_bus);711 mdiobus_free(pd->mii_bus);712 713 return 0;714}715 716static void smsc9420_rx_count_stats(struct net_device *dev, u32 desc_status)717{718 if (unlikely(desc_status & RDES0_ERROR_SUMMARY_)) {719 dev->stats.rx_errors++;720 if (desc_status & RDES0_DESCRIPTOR_ERROR_)721 dev->stats.rx_over_errors++;722 else if (desc_status & (RDES0_FRAME_TOO_LONG_ |723 RDES0_RUNT_FRAME_ | RDES0_COLLISION_SEEN_))724 dev->stats.rx_frame_errors++;725 else if (desc_status & RDES0_CRC_ERROR_)726 dev->stats.rx_crc_errors++;727 }728 729 if (unlikely(desc_status & RDES0_LENGTH_ERROR_))730 dev->stats.rx_length_errors++;731 732 if (unlikely(!((desc_status & RDES0_LAST_DESCRIPTOR_) &&733 (desc_status & RDES0_FIRST_DESCRIPTOR_))))734 dev->stats.rx_length_errors++;735 736 if (desc_status & RDES0_MULTICAST_FRAME_)737 dev->stats.multicast++;738}739 740static void smsc9420_rx_handoff(struct smsc9420_pdata *pd, const int index,741 const u32 status)742{743 struct net_device *dev = pd->dev;744 struct sk_buff *skb;745 u16 packet_length = (status & RDES0_FRAME_LENGTH_MASK_)746 >> RDES0_FRAME_LENGTH_SHFT_;747 748 /* remove crc from packet lendth */749 packet_length -= 4;750 751 if (pd->rx_csum)752 packet_length -= 2;753 754 dev->stats.rx_packets++;755 dev->stats.rx_bytes += packet_length;756 757 dma_unmap_single(&pd->pdev->dev, pd->rx_buffers[index].mapping,758 PKT_BUF_SZ, DMA_FROM_DEVICE);759 pd->rx_buffers[index].mapping = 0;760 761 skb = pd->rx_buffers[index].skb;762 pd->rx_buffers[index].skb = NULL;763 764 if (pd->rx_csum) {765 u16 hw_csum = get_unaligned_le16(skb_tail_pointer(skb) +766 NET_IP_ALIGN + packet_length + 4);767 put_unaligned_le16(hw_csum, &skb->csum);768 skb->ip_summed = CHECKSUM_COMPLETE;769 }770 771 skb_reserve(skb, NET_IP_ALIGN);772 skb_put(skb, packet_length);773 774 skb->protocol = eth_type_trans(skb, dev);775 776 netif_receive_skb(skb);777}778 779static int smsc9420_alloc_rx_buffer(struct smsc9420_pdata *pd, int index)780{781 struct sk_buff *skb = netdev_alloc_skb(pd->dev, PKT_BUF_SZ);782 dma_addr_t mapping;783 784 BUG_ON(pd->rx_buffers[index].skb);785 BUG_ON(pd->rx_buffers[index].mapping);786 787 if (unlikely(!skb))788 return -ENOMEM;789 790 mapping = dma_map_single(&pd->pdev->dev, skb_tail_pointer(skb),791 PKT_BUF_SZ, DMA_FROM_DEVICE);792 if (dma_mapping_error(&pd->pdev->dev, mapping)) {793 dev_kfree_skb_any(skb);794 netif_warn(pd, rx_err, pd->dev, "dma_map_single failed!\n");795 return -ENOMEM;796 }797 798 pd->rx_buffers[index].skb = skb;799 pd->rx_buffers[index].mapping = mapping;800 pd->rx_ring[index].buffer1 = mapping + NET_IP_ALIGN;801 pd->rx_ring[index].status = RDES0_OWN_;802 wmb();803 804 return 0;805}806 807static void smsc9420_alloc_new_rx_buffers(struct smsc9420_pdata *pd)808{809 while (pd->rx_ring_tail != pd->rx_ring_head) {810 if (smsc9420_alloc_rx_buffer(pd, pd->rx_ring_tail))811 break;812 813 pd->rx_ring_tail = (pd->rx_ring_tail + 1) % RX_RING_SIZE;814 }815}816 817static int smsc9420_rx_poll(struct napi_struct *napi, int budget)818{819 struct smsc9420_pdata *pd =820 container_of(napi, struct smsc9420_pdata, napi);821 struct net_device *dev = pd->dev;822 u32 drop_frame_cnt, dma_intr_ena, status;823 int work_done;824 825 for (work_done = 0; work_done < budget; work_done++) {826 rmb();827 status = pd->rx_ring[pd->rx_ring_head].status;828 829 /* stop if DMAC owns this dma descriptor */830 if (status & RDES0_OWN_)831 break;832 833 smsc9420_rx_count_stats(dev, status);834 smsc9420_rx_handoff(pd, pd->rx_ring_head, status);835 pd->rx_ring_head = (pd->rx_ring_head + 1) % RX_RING_SIZE;836 smsc9420_alloc_new_rx_buffers(pd);837 }838 839 drop_frame_cnt = smsc9420_reg_read(pd, MISS_FRAME_CNTR);840 dev->stats.rx_dropped +=841 (drop_frame_cnt & 0xFFFF) + ((drop_frame_cnt >> 17) & 0x3FF);842 843 /* Kick RXDMA */844 smsc9420_reg_write(pd, RX_POLL_DEMAND, 1);845 smsc9420_pci_flush_write(pd);846 847 if (work_done < budget) {848 napi_complete_done(&pd->napi, work_done);849 850 /* re-enable RX DMA interrupts */851 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA);852 dma_intr_ena |= (DMAC_INTR_ENA_RX_ | DMAC_INTR_ENA_NIS_);853 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena);854 smsc9420_pci_flush_write(pd);855 }856 return work_done;857}858 859static void860smsc9420_tx_update_stats(struct net_device *dev, u32 status, u32 length)861{862 if (unlikely(status & TDES0_ERROR_SUMMARY_)) {863 dev->stats.tx_errors++;864 if (status & (TDES0_EXCESSIVE_DEFERRAL_ |865 TDES0_EXCESSIVE_COLLISIONS_))866 dev->stats.tx_aborted_errors++;867 868 if (status & (TDES0_LOSS_OF_CARRIER_ | TDES0_NO_CARRIER_))869 dev->stats.tx_carrier_errors++;870 } else {871 dev->stats.tx_packets++;872 dev->stats.tx_bytes += (length & 0x7FF);873 }874 875 if (unlikely(status & TDES0_EXCESSIVE_COLLISIONS_)) {876 dev->stats.collisions += 16;877 } else {878 dev->stats.collisions +=879 (status & TDES0_COLLISION_COUNT_MASK_) >>880 TDES0_COLLISION_COUNT_SHFT_;881 }882 883 if (unlikely(status & TDES0_HEARTBEAT_FAIL_))884 dev->stats.tx_heartbeat_errors++;885}886 887/* Check for completed dma transfers, update stats and free skbs */888static void smsc9420_complete_tx(struct net_device *dev)889{890 struct smsc9420_pdata *pd = netdev_priv(dev);891 892 while (pd->tx_ring_tail != pd->tx_ring_head) {893 int index = pd->tx_ring_tail;894 u32 status, length;895 896 rmb();897 status = pd->tx_ring[index].status;898 length = pd->tx_ring[index].length;899 900 /* Check if DMA still owns this descriptor */901 if (unlikely(TDES0_OWN_ & status))902 break;903 904 smsc9420_tx_update_stats(dev, status, length);905 906 BUG_ON(!pd->tx_buffers[index].skb);907 BUG_ON(!pd->tx_buffers[index].mapping);908 909 dma_unmap_single(&pd->pdev->dev,910 pd->tx_buffers[index].mapping,911 pd->tx_buffers[index].skb->len,912 DMA_TO_DEVICE);913 pd->tx_buffers[index].mapping = 0;914 915 dev_kfree_skb_any(pd->tx_buffers[index].skb);916 pd->tx_buffers[index].skb = NULL;917 918 pd->tx_ring[index].buffer1 = 0;919 wmb();920 921 pd->tx_ring_tail = (pd->tx_ring_tail + 1) % TX_RING_SIZE;922 }923}924 925static netdev_tx_t smsc9420_hard_start_xmit(struct sk_buff *skb,926 struct net_device *dev)927{928 struct smsc9420_pdata *pd = netdev_priv(dev);929 dma_addr_t mapping;930 int index = pd->tx_ring_head;931 u32 tmp_desc1;932 bool about_to_take_last_desc =933 (((pd->tx_ring_head + 2) % TX_RING_SIZE) == pd->tx_ring_tail);934 935 smsc9420_complete_tx(dev);936 937 rmb();938 BUG_ON(pd->tx_ring[index].status & TDES0_OWN_);939 BUG_ON(pd->tx_buffers[index].skb);940 BUG_ON(pd->tx_buffers[index].mapping);941 942 mapping = dma_map_single(&pd->pdev->dev, skb->data, skb->len,943 DMA_TO_DEVICE);944 if (dma_mapping_error(&pd->pdev->dev, mapping)) {945 netif_warn(pd, tx_err, pd->dev,946 "dma_map_single failed, dropping packet\n");947 return NETDEV_TX_BUSY;948 }949 950 pd->tx_buffers[index].skb = skb;951 pd->tx_buffers[index].mapping = mapping;952 953 tmp_desc1 = (TDES1_LS_ | ((u32)skb->len & 0x7FF));954 if (unlikely(about_to_take_last_desc)) {955 tmp_desc1 |= TDES1_IC_;956 netif_stop_queue(pd->dev);957 }958 959 /* check if we are at the last descriptor and need to set EOR */960 if (unlikely(index == (TX_RING_SIZE - 1)))961 tmp_desc1 |= TDES1_TER_;962 963 pd->tx_ring[index].buffer1 = mapping;964 pd->tx_ring[index].length = tmp_desc1;965 wmb();966 967 /* increment head */968 pd->tx_ring_head = (pd->tx_ring_head + 1) % TX_RING_SIZE;969 970 /* assign ownership to DMAC */971 pd->tx_ring[index].status = TDES0_OWN_;972 wmb();973 974 skb_tx_timestamp(skb);975 976 /* kick the DMA */977 smsc9420_reg_write(pd, TX_POLL_DEMAND, 1);978 smsc9420_pci_flush_write(pd);979 980 return NETDEV_TX_OK;981}982 983static struct net_device_stats *smsc9420_get_stats(struct net_device *dev)984{985 struct smsc9420_pdata *pd = netdev_priv(dev);986 u32 counter = smsc9420_reg_read(pd, MISS_FRAME_CNTR);987 dev->stats.rx_dropped +=988 (counter & 0x0000FFFF) + ((counter >> 17) & 0x000003FF);989 return &dev->stats;990}991 992static void smsc9420_set_multicast_list(struct net_device *dev)993{994 struct smsc9420_pdata *pd = netdev_priv(dev);995 u32 mac_cr = smsc9420_reg_read(pd, MAC_CR);996 997 if (dev->flags & IFF_PROMISC) {998 netif_dbg(pd, hw, pd->dev, "Promiscuous Mode Enabled\n");999 mac_cr |= MAC_CR_PRMS_;1000 mac_cr &= (~MAC_CR_MCPAS_);1001 mac_cr &= (~MAC_CR_HPFILT_);1002 } else if (dev->flags & IFF_ALLMULTI) {1003 netif_dbg(pd, hw, pd->dev, "Receive all Multicast Enabled\n");1004 mac_cr &= (~MAC_CR_PRMS_);1005 mac_cr |= MAC_CR_MCPAS_;1006 mac_cr &= (~MAC_CR_HPFILT_);1007 } else if (!netdev_mc_empty(dev)) {1008 struct netdev_hw_addr *ha;1009 u32 hash_lo = 0, hash_hi = 0;1010 1011 netif_dbg(pd, hw, pd->dev, "Multicast filter enabled\n");1012 netdev_for_each_mc_addr(ha, dev) {1013 u32 bit_num = smsc9420_hash(ha->addr);1014 u32 mask = 1 << (bit_num & 0x1F);1015 1016 if (bit_num & 0x20)1017 hash_hi |= mask;1018 else1019 hash_lo |= mask;1020 1021 }1022 smsc9420_reg_write(pd, HASHH, hash_hi);1023 smsc9420_reg_write(pd, HASHL, hash_lo);1024 1025 mac_cr &= (~MAC_CR_PRMS_);1026 mac_cr &= (~MAC_CR_MCPAS_);1027 mac_cr |= MAC_CR_HPFILT_;1028 } else {1029 netif_dbg(pd, hw, pd->dev, "Receive own packets only\n");1030 smsc9420_reg_write(pd, HASHH, 0);1031 smsc9420_reg_write(pd, HASHL, 0);1032 1033 mac_cr &= (~MAC_CR_PRMS_);1034 mac_cr &= (~MAC_CR_MCPAS_);1035 mac_cr &= (~MAC_CR_HPFILT_);1036 }1037 1038 smsc9420_reg_write(pd, MAC_CR, mac_cr);1039 smsc9420_pci_flush_write(pd);1040}1041 1042static void smsc9420_phy_update_flowcontrol(struct smsc9420_pdata *pd)1043{1044 struct net_device *dev = pd->dev;1045 struct phy_device *phy_dev = dev->phydev;1046 u32 flow;1047 1048 if (phy_dev->duplex == DUPLEX_FULL) {1049 u16 lcladv = phy_read(phy_dev, MII_ADVERTISE);1050 u16 rmtadv = phy_read(phy_dev, MII_LPA);1051 u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv);1052 1053 if (cap & FLOW_CTRL_RX)1054 flow = 0xFFFF0002;1055 else1056 flow = 0;1057 1058 netif_info(pd, link, pd->dev, "rx pause %s, tx pause %s\n",1059 cap & FLOW_CTRL_RX ? "enabled" : "disabled",1060 cap & FLOW_CTRL_TX ? "enabled" : "disabled");1061 } else {1062 netif_info(pd, link, pd->dev, "half duplex\n");1063 flow = 0;1064 }1065 1066 smsc9420_reg_write(pd, FLOW, flow);1067}1068 1069/* Update link mode if anything has changed. Called periodically when the1070 * PHY is in polling mode, even if nothing has changed. */1071static void smsc9420_phy_adjust_link(struct net_device *dev)1072{1073 struct smsc9420_pdata *pd = netdev_priv(dev);1074 struct phy_device *phy_dev = dev->phydev;1075 int carrier;1076 1077 if (phy_dev->duplex != pd->last_duplex) {1078 u32 mac_cr = smsc9420_reg_read(pd, MAC_CR);1079 if (phy_dev->duplex) {1080 netif_dbg(pd, link, pd->dev, "full duplex mode\n");1081 mac_cr |= MAC_CR_FDPX_;1082 } else {1083 netif_dbg(pd, link, pd->dev, "half duplex mode\n");1084 mac_cr &= ~MAC_CR_FDPX_;1085 }1086 smsc9420_reg_write(pd, MAC_CR, mac_cr);1087 1088 smsc9420_phy_update_flowcontrol(pd);1089 pd->last_duplex = phy_dev->duplex;1090 }1091 1092 carrier = netif_carrier_ok(dev);1093 if (carrier != pd->last_carrier) {1094 if (carrier)1095 netif_dbg(pd, link, pd->dev, "carrier OK\n");1096 else1097 netif_dbg(pd, link, pd->dev, "no carrier\n");1098 pd->last_carrier = carrier;1099 }1100}1101 1102static int smsc9420_mii_probe(struct net_device *dev)1103{1104 struct smsc9420_pdata *pd = netdev_priv(dev);1105 struct phy_device *phydev = NULL;1106 1107 BUG_ON(dev->phydev);1108 1109 /* Device only supports internal PHY at address 1 */1110 phydev = mdiobus_get_phy(pd->mii_bus, 1);1111 if (!phydev) {1112 netdev_err(dev, "no PHY found at address 1\n");1113 return -ENODEV;1114 }1115 1116 phydev = phy_connect(dev, phydev_name(phydev),1117 smsc9420_phy_adjust_link, PHY_INTERFACE_MODE_MII);1118 1119 if (IS_ERR(phydev)) {1120 netdev_err(dev, "Could not attach to PHY\n");1121 return PTR_ERR(phydev);1122 }1123 1124 phy_set_max_speed(phydev, SPEED_100);1125 1126 /* mask with MAC supported features */1127 phy_support_asym_pause(phydev);1128 1129 phy_attached_info(phydev);1130 1131 pd->last_duplex = -1;1132 pd->last_carrier = -1;1133 1134 return 0;1135}1136 1137static int smsc9420_mii_init(struct net_device *dev)1138{1139 struct smsc9420_pdata *pd = netdev_priv(dev);1140 int err = -ENXIO;1141 1142 pd->mii_bus = mdiobus_alloc();1143 if (!pd->mii_bus) {1144 err = -ENOMEM;1145 goto err_out_1;1146 }1147 pd->mii_bus->name = DRV_MDIONAME;1148 snprintf(pd->mii_bus->id, MII_BUS_ID_SIZE, "%x", pci_dev_id(pd->pdev));1149 pd->mii_bus->priv = pd;1150 pd->mii_bus->read = smsc9420_mii_read;1151 pd->mii_bus->write = smsc9420_mii_write;1152 1153 /* Mask all PHYs except ID 1 (internal) */1154 pd->mii_bus->phy_mask = ~(1 << 1);1155 1156 if (mdiobus_register(pd->mii_bus)) {1157 netif_warn(pd, probe, pd->dev, "Error registering mii bus\n");1158 goto err_out_free_bus_2;1159 }1160 1161 if (smsc9420_mii_probe(dev) < 0) {1162 netif_warn(pd, probe, pd->dev, "Error probing mii bus\n");1163 goto err_out_unregister_bus_3;1164 }1165 1166 return 0;1167 1168err_out_unregister_bus_3:1169 mdiobus_unregister(pd->mii_bus);1170err_out_free_bus_2:1171 mdiobus_free(pd->mii_bus);1172err_out_1:1173 return err;1174}1175 1176static int smsc9420_alloc_tx_ring(struct smsc9420_pdata *pd)1177{1178 int i;1179 1180 BUG_ON(!pd->tx_ring);1181 1182 pd->tx_buffers = kmalloc_array(TX_RING_SIZE,1183 sizeof(struct smsc9420_ring_info),1184 GFP_KERNEL);1185 if (!pd->tx_buffers)1186 return -ENOMEM;1187 1188 /* Initialize the TX Ring */1189 for (i = 0; i < TX_RING_SIZE; i++) {1190 pd->tx_buffers[i].skb = NULL;1191 pd->tx_buffers[i].mapping = 0;1192 pd->tx_ring[i].status = 0;1193 pd->tx_ring[i].length = 0;1194 pd->tx_ring[i].buffer1 = 0;1195 pd->tx_ring[i].buffer2 = 0;1196 }1197 pd->tx_ring[TX_RING_SIZE - 1].length = TDES1_TER_;1198 wmb();1199 1200 pd->tx_ring_head = 0;1201 pd->tx_ring_tail = 0;1202 1203 smsc9420_reg_write(pd, TX_BASE_ADDR, pd->tx_dma_addr);1204 smsc9420_pci_flush_write(pd);1205 1206 return 0;1207}1208 1209static int smsc9420_alloc_rx_ring(struct smsc9420_pdata *pd)1210{1211 int i;1212 1213 BUG_ON(!pd->rx_ring);1214 1215 pd->rx_buffers = kmalloc_array(RX_RING_SIZE,1216 sizeof(struct smsc9420_ring_info),1217 GFP_KERNEL);1218 if (pd->rx_buffers == NULL)1219 goto out;1220 1221 /* initialize the rx ring */1222 for (i = 0; i < RX_RING_SIZE; i++) {1223 pd->rx_ring[i].status = 0;1224 pd->rx_ring[i].length = PKT_BUF_SZ;1225 pd->rx_ring[i].buffer2 = 0;1226 pd->rx_buffers[i].skb = NULL;1227 pd->rx_buffers[i].mapping = 0;1228 }1229 pd->rx_ring[RX_RING_SIZE - 1].length = (PKT_BUF_SZ | RDES1_RER_);1230 1231 /* now allocate the entire ring of skbs */1232 for (i = 0; i < RX_RING_SIZE; i++) {1233 if (smsc9420_alloc_rx_buffer(pd, i)) {1234 netif_warn(pd, ifup, pd->dev,1235 "failed to allocate rx skb %d\n", i);1236 goto out_free_rx_skbs;1237 }1238 }1239 1240 pd->rx_ring_head = 0;1241 pd->rx_ring_tail = 0;1242 1243 smsc9420_reg_write(pd, VLAN1, ETH_P_8021Q);1244 netif_dbg(pd, ifup, pd->dev, "VLAN1 = 0x%08x\n",1245 smsc9420_reg_read(pd, VLAN1));1246 1247 if (pd->rx_csum) {1248 /* Enable RX COE */1249 u32 coe = smsc9420_reg_read(pd, COE_CR) | RX_COE_EN;1250 smsc9420_reg_write(pd, COE_CR, coe);1251 netif_dbg(pd, ifup, pd->dev, "COE_CR = 0x%08x\n", coe);1252 }1253 1254 smsc9420_reg_write(pd, RX_BASE_ADDR, pd->rx_dma_addr);1255 smsc9420_pci_flush_write(pd);1256 1257 return 0;1258 1259out_free_rx_skbs:1260 smsc9420_free_rx_ring(pd);1261out:1262 return -ENOMEM;1263}1264 1265static int smsc9420_open(struct net_device *dev)1266{1267 struct smsc9420_pdata *pd = netdev_priv(dev);1268 u32 bus_mode, mac_cr, dmac_control, int_cfg, dma_intr_ena, int_ctl;1269 const int irq = pd->pdev->irq;1270 unsigned long flags;1271 int result = 0, timeout;1272 1273 if (!is_valid_ether_addr(dev->dev_addr)) {1274 netif_warn(pd, ifup, pd->dev,1275 "dev_addr is not a valid MAC address\n");1276 result = -EADDRNOTAVAIL;1277 goto out_0;1278 }1279 1280 netif_carrier_off(dev);1281 1282 /* disable, mask and acknowledge all interrupts */1283 spin_lock_irqsave(&pd->int_lock, flags);1284 int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_);1285 smsc9420_reg_write(pd, INT_CFG, int_cfg);1286 smsc9420_reg_write(pd, INT_CTL, 0);1287 spin_unlock_irqrestore(&pd->int_lock, flags);1288 smsc9420_reg_write(pd, DMAC_INTR_ENA, 0);1289 smsc9420_reg_write(pd, INT_STAT, 0xFFFFFFFF);1290 smsc9420_pci_flush_write(pd);1291 1292 result = request_irq(irq, smsc9420_isr, IRQF_SHARED, DRV_NAME, pd);1293 if (result) {1294 netif_warn(pd, ifup, pd->dev, "Unable to use IRQ = %d\n", irq);1295 result = -ENODEV;1296 goto out_0;1297 }1298 1299 smsc9420_dmac_soft_reset(pd);1300 1301 /* make sure MAC_CR is sane */1302 smsc9420_reg_write(pd, MAC_CR, 0);1303 1304 smsc9420_set_mac_address(dev);1305 1306 /* Configure GPIO pins to drive LEDs */1307 smsc9420_reg_write(pd, GPIO_CFG,1308 (GPIO_CFG_LED_3_ | GPIO_CFG_LED_2_ | GPIO_CFG_LED_1_));1309 1310 bus_mode = BUS_MODE_DMA_BURST_LENGTH_16;1311 1312#ifdef __BIG_ENDIAN1313 bus_mode |= BUS_MODE_DBO_;1314#endif1315 1316 smsc9420_reg_write(pd, BUS_MODE, bus_mode);1317 1318 smsc9420_pci_flush_write(pd);1319 1320 /* set bus master bridge arbitration priority for Rx and TX DMA */1321 smsc9420_reg_write(pd, BUS_CFG, BUS_CFG_RXTXWEIGHT_4_1);1322 1323 smsc9420_reg_write(pd, DMAC_CONTROL,1324 (DMAC_CONTROL_SF_ | DMAC_CONTROL_OSF_));1325 1326 smsc9420_pci_flush_write(pd);1327 1328 /* test the IRQ connection to the ISR */1329 netif_dbg(pd, ifup, pd->dev, "Testing ISR using IRQ %d\n", irq);1330 pd->software_irq_signal = false;1331 1332 spin_lock_irqsave(&pd->int_lock, flags);1333 /* configure interrupt deassertion timer and enable interrupts */1334 int_cfg = smsc9420_reg_read(pd, INT_CFG) | INT_CFG_IRQ_EN_;1335 int_cfg &= ~(INT_CFG_INT_DEAS_MASK);1336 int_cfg |= (INT_DEAS_TIME & INT_CFG_INT_DEAS_MASK);1337 smsc9420_reg_write(pd, INT_CFG, int_cfg);1338 1339 /* unmask software interrupt */1340 int_ctl = smsc9420_reg_read(pd, INT_CTL) | INT_CTL_SW_INT_EN_;1341 smsc9420_reg_write(pd, INT_CTL, int_ctl);1342 spin_unlock_irqrestore(&pd->int_lock, flags);1343 smsc9420_pci_flush_write(pd);1344 1345 timeout = 1000;1346 while (timeout--) {1347 if (pd->software_irq_signal)1348 break;1349 msleep(1);1350 }1351 1352 /* disable interrupts */1353 spin_lock_irqsave(&pd->int_lock, flags);1354 int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_);1355 smsc9420_reg_write(pd, INT_CFG, int_cfg);1356 spin_unlock_irqrestore(&pd->int_lock, flags);1357 1358 if (!pd->software_irq_signal) {1359 netif_warn(pd, ifup, pd->dev, "ISR failed signaling test\n");1360 result = -ENODEV;1361 goto out_free_irq_1;1362 }1363 1364 netif_dbg(pd, ifup, pd->dev, "ISR passed test using IRQ %d\n", irq);1365 1366 result = smsc9420_alloc_tx_ring(pd);1367 if (result) {1368 netif_warn(pd, ifup, pd->dev,1369 "Failed to Initialize tx dma ring\n");1370 result = -ENOMEM;1371 goto out_free_irq_1;1372 }1373 1374 result = smsc9420_alloc_rx_ring(pd);1375 if (result) {1376 netif_warn(pd, ifup, pd->dev,1377 "Failed to Initialize rx dma ring\n");1378 result = -ENOMEM;1379 goto out_free_tx_ring_2;1380 }1381 1382 result = smsc9420_mii_init(dev);1383 if (result) {1384 netif_warn(pd, ifup, pd->dev, "Failed to initialize Phy\n");1385 result = -ENODEV;1386 goto out_free_rx_ring_3;1387 }1388 1389 /* Bring the PHY up */1390 phy_start(dev->phydev);1391 1392 napi_enable(&pd->napi);1393 1394 /* start tx and rx */1395 mac_cr = smsc9420_reg_read(pd, MAC_CR) | MAC_CR_TXEN_ | MAC_CR_RXEN_;1396 smsc9420_reg_write(pd, MAC_CR, mac_cr);1397 1398 dmac_control = smsc9420_reg_read(pd, DMAC_CONTROL);1399 dmac_control |= DMAC_CONTROL_ST_ | DMAC_CONTROL_SR_;1400 smsc9420_reg_write(pd, DMAC_CONTROL, dmac_control);1401 smsc9420_pci_flush_write(pd);1402 1403 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA);1404 dma_intr_ena |=1405 (DMAC_INTR_ENA_TX_ | DMAC_INTR_ENA_RX_ | DMAC_INTR_ENA_NIS_);1406 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena);1407 smsc9420_pci_flush_write(pd);1408 1409 netif_wake_queue(dev);1410 1411 smsc9420_reg_write(pd, RX_POLL_DEMAND, 1);1412 1413 /* enable interrupts */1414 spin_lock_irqsave(&pd->int_lock, flags);1415 int_cfg = smsc9420_reg_read(pd, INT_CFG) | INT_CFG_IRQ_EN_;1416 smsc9420_reg_write(pd, INT_CFG, int_cfg);1417 spin_unlock_irqrestore(&pd->int_lock, flags);1418 1419 return 0;1420 1421out_free_rx_ring_3:1422 smsc9420_free_rx_ring(pd);1423out_free_tx_ring_2:1424 smsc9420_free_tx_ring(pd);1425out_free_irq_1:1426 free_irq(irq, pd);1427out_0:1428 return result;1429}1430 1431static int __maybe_unused smsc9420_suspend(struct device *dev_d)1432{1433 struct net_device *dev = dev_get_drvdata(dev_d);1434 struct smsc9420_pdata *pd = netdev_priv(dev);1435 u32 int_cfg;1436 ulong flags;1437 1438 /* disable interrupts */1439 spin_lock_irqsave(&pd->int_lock, flags);1440 int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_);1441 smsc9420_reg_write(pd, INT_CFG, int_cfg);1442 spin_unlock_irqrestore(&pd->int_lock, flags);1443 1444 if (netif_running(dev)) {1445 netif_tx_disable(dev);1446 smsc9420_stop_tx(pd);1447 smsc9420_free_tx_ring(pd);1448 1449 napi_disable(&pd->napi);1450 smsc9420_stop_rx(pd);1451 smsc9420_free_rx_ring(pd);1452 1453 free_irq(pd->pdev->irq, pd);1454 1455 netif_device_detach(dev);1456 }1457 1458 device_wakeup_disable(dev_d);1459 1460 return 0;1461}1462 1463static int __maybe_unused smsc9420_resume(struct device *dev_d)1464{1465 struct net_device *dev = dev_get_drvdata(dev_d);1466 int err;1467 1468 pci_set_master(to_pci_dev(dev_d));1469 1470 device_wakeup_disable(dev_d);1471 1472 err = 0;1473 if (netif_running(dev)) {1474 /* FIXME: gross. It looks like ancient PM relic.*/1475 err = smsc9420_open(dev);1476 netif_device_attach(dev);1477 }1478 return err;1479}1480 1481static const struct net_device_ops smsc9420_netdev_ops = {1482 .ndo_open = smsc9420_open,1483 .ndo_stop = smsc9420_stop,1484 .ndo_start_xmit = smsc9420_hard_start_xmit,1485 .ndo_get_stats = smsc9420_get_stats,1486 .ndo_set_rx_mode = smsc9420_set_multicast_list,1487 .ndo_eth_ioctl = phy_do_ioctl_running,1488 .ndo_validate_addr = eth_validate_addr,1489 .ndo_set_mac_address = eth_mac_addr,1490#ifdef CONFIG_NET_POLL_CONTROLLER1491 .ndo_poll_controller = smsc9420_poll_controller,1492#endif /* CONFIG_NET_POLL_CONTROLLER */1493};1494 1495static int1496smsc9420_probe(struct pci_dev *pdev, const struct pci_device_id *id)1497{1498 struct net_device *dev;1499 struct smsc9420_pdata *pd;1500 void __iomem *virt_addr;1501 int result = 0;1502 u32 id_rev;1503 1504 pr_info("%s version %s\n", DRV_DESCRIPTION, DRV_VERSION);1505 1506 /* First do the PCI initialisation */1507 result = pci_enable_device(pdev);1508 if (unlikely(result)) {1509 pr_err("Cannot enable smsc9420\n");1510 goto out_0;1511 }1512 1513 pci_set_master(pdev);1514 1515 dev = alloc_etherdev(sizeof(*pd));1516 if (!dev)1517 goto out_disable_pci_device_1;1518 1519 SET_NETDEV_DEV(dev, &pdev->dev);1520 1521 if (!(pci_resource_flags(pdev, SMSC_BAR) & IORESOURCE_MEM)) {1522 netdev_err(dev, "Cannot find PCI device base address\n");1523 goto out_free_netdev_2;1524 }1525 1526 if ((pci_request_regions(pdev, DRV_NAME))) {1527 netdev_err(dev, "Cannot obtain PCI resources, aborting\n");1528 goto out_free_netdev_2;1529 }1530 1531 if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(32))) {1532 netdev_err(dev, "No usable DMA configuration, aborting\n");1533 goto out_free_regions_3;1534 }1535 1536 virt_addr = ioremap(pci_resource_start(pdev, SMSC_BAR),1537 pci_resource_len(pdev, SMSC_BAR));1538 if (!virt_addr) {1539 netdev_err(dev, "Cannot map device registers, aborting\n");1540 goto out_free_regions_3;1541 }1542 1543 /* registers are double mapped with 0 offset for LE and 0x200 for BE */1544 virt_addr += LAN9420_CPSR_ENDIAN_OFFSET;1545 1546 pd = netdev_priv(dev);1547 1548 /* pci descriptors are created in the PCI consistent area */1549 pd->rx_ring = dma_alloc_coherent(&pdev->dev,1550 sizeof(struct smsc9420_dma_desc) * (RX_RING_SIZE + TX_RING_SIZE),1551 &pd->rx_dma_addr, GFP_KERNEL);1552 1553 if (!pd->rx_ring)1554 goto out_free_io_4;1555 1556 /* descriptors are aligned due to the nature of dma_alloc_coherent */1557 pd->tx_ring = (pd->rx_ring + RX_RING_SIZE);1558 pd->tx_dma_addr = pd->rx_dma_addr +1559 sizeof(struct smsc9420_dma_desc) * RX_RING_SIZE;1560 1561 pd->pdev = pdev;1562 pd->dev = dev;1563 pd->ioaddr = virt_addr;1564 pd->msg_enable = smsc_debug;1565 pd->rx_csum = true;1566 1567 netif_dbg(pd, probe, pd->dev, "lan_base=0x%08lx\n", (ulong)virt_addr);1568 1569 id_rev = smsc9420_reg_read(pd, ID_REV);1570 switch (id_rev & 0xFFFF0000) {1571 case 0x94200000:1572 netif_info(pd, probe, pd->dev,1573 "LAN9420 identified, ID_REV=0x%08X\n", id_rev);1574 break;1575 default:1576 netif_warn(pd, probe, pd->dev, "LAN9420 NOT identified\n");1577 netif_warn(pd, probe, pd->dev, "ID_REV=0x%08X\n", id_rev);1578 goto out_free_dmadesc_5;1579 }1580 1581 smsc9420_dmac_soft_reset(pd);1582 smsc9420_eeprom_reload(pd);1583 smsc9420_check_mac_address(dev);1584 1585 dev->netdev_ops = &smsc9420_netdev_ops;1586 dev->ethtool_ops = &smsc9420_ethtool_ops;1587 1588 netif_napi_add(dev, &pd->napi, smsc9420_rx_poll);1589 1590 result = register_netdev(dev);1591 if (result) {1592 netif_warn(pd, probe, pd->dev, "error %i registering device\n",1593 result);1594 goto out_free_dmadesc_5;1595 }1596 1597 pci_set_drvdata(pdev, dev);1598 1599 spin_lock_init(&pd->int_lock);1600 spin_lock_init(&pd->phy_lock);1601 1602 dev_info(&dev->dev, "MAC Address: %pM\n", dev->dev_addr);1603 1604 return 0;1605 1606out_free_dmadesc_5:1607 dma_free_coherent(&pdev->dev,1608 sizeof(struct smsc9420_dma_desc) * (RX_RING_SIZE + TX_RING_SIZE),1609 pd->rx_ring, pd->rx_dma_addr);1610out_free_io_4:1611 iounmap(virt_addr - LAN9420_CPSR_ENDIAN_OFFSET);1612out_free_regions_3:1613 pci_release_regions(pdev);1614out_free_netdev_2:1615 free_netdev(dev);1616out_disable_pci_device_1:1617 pci_disable_device(pdev);1618out_0:1619 return -ENODEV;1620}1621 1622static void smsc9420_remove(struct pci_dev *pdev)1623{1624 struct net_device *dev;1625 struct smsc9420_pdata *pd;1626 1627 dev = pci_get_drvdata(pdev);1628 if (!dev)1629 return;1630 1631 pd = netdev_priv(dev);1632 unregister_netdev(dev);1633 1634 /* tx_buffers and rx_buffers are freed in stop */1635 BUG_ON(pd->tx_buffers);1636 BUG_ON(pd->rx_buffers);1637 1638 BUG_ON(!pd->tx_ring);1639 BUG_ON(!pd->rx_ring);1640 1641 dma_free_coherent(&pdev->dev,1642 sizeof(struct smsc9420_dma_desc) * (RX_RING_SIZE + TX_RING_SIZE),1643 pd->rx_ring, pd->rx_dma_addr);1644 1645 iounmap(pd->ioaddr - LAN9420_CPSR_ENDIAN_OFFSET);1646 pci_release_regions(pdev);1647 free_netdev(dev);1648 pci_disable_device(pdev);1649}1650 1651static SIMPLE_DEV_PM_OPS(smsc9420_pm_ops, smsc9420_suspend, smsc9420_resume);1652 1653static struct pci_driver smsc9420_driver = {1654 .name = DRV_NAME,1655 .id_table = smsc9420_id_table,1656 .probe = smsc9420_probe,1657 .remove = smsc9420_remove,1658 .driver.pm = &smsc9420_pm_ops,1659};1660 1661static int __init smsc9420_init_module(void)1662{1663 smsc_debug = netif_msg_init(debug, SMSC_MSG_DEFAULT);1664 1665 return pci_register_driver(&smsc9420_driver);1666}1667 1668static void __exit smsc9420_exit_module(void)1669{1670 pci_unregister_driver(&smsc9420_driver);1671}1672 1673module_init(smsc9420_init_module);1674module_exit(smsc9420_exit_module);1675